From 2b8367ed4b1a1a92a4f56dabab284aaceb53f6c7 Mon Sep 17 00:00:00 2001
From: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Date: Thu, 13 Jun 2024 10:53:15 +0800
Subject: mb/google/nissa/var/pujjoga: disable pcie port7

Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test.

BUG=b:335312655
TEST=Build and check S0ix function and verify FAFT sleep funciton.

Change-Id: I7918e26fe382d4d9992a0e2744a2f8894a070e36
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/pujjoga/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb
index 500f21c7fe..789e578081 100644
--- a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb
@@ -358,6 +358,7 @@ chip soc/intel/alderlake
 				device pci 00.0 on end
 			end
 		end
+		device ref pcie_rp7 off end
 		device ref pch_espi on
 			chip ec/google/chromeec
 				use conn0 as mux_conn[0]
-- 
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