From 28d71b9445ef2774baa5e1f5ad17160d90b0e8bb Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Fri, 5 Jun 2009 10:00:07 +0000 Subject: After I modify the pci_ext_read_config32 and pci_ext_read_config32, the step 6a starts to play its role. Then the system hangs at HDA init. I dont know what the VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)" in 5.10.2. Before I know what it is, I think it is better to skip it. Tested on dbm690t. Add comment from Rudolf, " VC is virtual channel. Its used for isochronous transfer of data to sound card. The virtual channel guarantee "on time" delivery. In other words it sets up a channel for data to sound card, which means that that arrivs in time and there will be no interuptions in audio stream. http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx " Signed-off-by: Zheng Bao Acked-by: Carl-Daniel Hailfinger git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/rs690/rs690_pcie.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c index 12fea1f2c9..b454783aae 100644 --- a/src/southbridge/amd/rs690/rs690_pcie.c +++ b/src/southbridge/amd/rs690/rs690_pcie.c @@ -276,6 +276,9 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) /* step 6a: VCI */ sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); if (port == 8) { + /* The code below between #if and #endif causes a hang on HDA init. + * So we skip it. */ +#if 0 /* Clear bits 7:1 */ pci_ext_write_config32(nb_dev, sb_dev, 0x114, 0x3f << 1, 0 << 1); /* Maps Traffic Class 1-7 to VC1 */ @@ -284,7 +287,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) pci_ext_write_config32(nb_dev, sb_dev, 0x120, 7 << 24, 1 << 24); /* Enables VC1 */ pci_ext_write_config32(nb_dev, sb_dev, 0x120, 1 << 31, 1 << 31); -#if 0 + do { reg16 = pci_ext_read_config32(nb_dev, sb_dev, 0x124); reg16 &= 0x2; -- cgit v1.2.3