From 28371e282690dd32ea78a52479331463215e18df Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 23 Oct 2020 19:36:25 +0530 Subject: soc/intel/alderlake/romstage: Skip GPIO configuration from FSP Set GpioOverride UPD to 1 to skip GPIO configuration in FSP phases TEST=Able to build and boot ADLRVP to OS. Change-Id: Ie965a85d9da9b6a23b385536313b852e66909cf4 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46696 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh --- src/soc/intel/alderlake/romstage/fsp_params.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 38c1a1b279..868d75e9da 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -157,6 +157,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); m_cfg->TmeEnable = CONFIG(INTEL_TME); + + /* Skip GPIO configuration from FSP */ + m_cfg->GpioOverride = 0x1; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- cgit v1.2.3