From 27d34022588717dd5e5f9c309d362b645c2a9ffa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Mon, 8 Jan 2018 18:31:42 +0100 Subject: arch/riscv: Align trap_entry to 4 bytes, as required by spec MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The RISC-V Privileged Architecture spec 1.10 requires that the address part of mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should be zero for now. Add the necessary alignment directive before trap_entry. Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/23173 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/trap_util.S | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 72a9ae1ced..8aba48b986 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -109,6 +109,7 @@ .text .global trap_entry + .align 2 # four byte alignment, as required by mtvec trap_entry: csrw mscratch, sp -- cgit v1.2.3