From 26a77eb4d1074327282eeb65407aec130c0bb3ba Mon Sep 17 00:00:00 2001
From: Tim Wawrzynczak <twawrzynczak@chromium.org>
Date: Thu, 26 Aug 2021 09:20:44 -0600
Subject: soc/intel/elkhartlake: Lock PAM registers in finalize

Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.

Change-Id: Ib6fce70d6b0386906850884880dadbf45597452d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/intel/elkhartlake/finalize.c   | 9 +++++++++
 src/soc/intel/elkhartlake/fsp_params.c | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c
index 5c36721ef5..3d1430fbe3 100644
--- a/src/soc/intel/elkhartlake/finalize.c
+++ b/src/soc/intel/elkhartlake/finalize.c
@@ -9,8 +9,10 @@
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
+#include <intelpch/lockdown.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
@@ -47,12 +49,19 @@ static void pch_finalize(void)
 	pmc_clear_pmcon_sts();
 }
 
+static void sa_finalize(void)
+{
+	if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
+		sa_lock_pam();
+}
+
 static void soc_finalize(void *unused)
 {
 	printk(BIOS_DEBUG, "Finalizing chipset.\n");
 
 	pch_finalize();
 	apm_control(APM_CNT_FINALIZE);
+	sa_finalize();
 
 	/* Indicate finalize step with post code */
 	post_code(POST_OS_BOOT);
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index ae9584c81b..2bf4a51131 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -148,6 +148,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PchWriteProtectionEnable[0] = 0;
 		params->PchUnlockGpioPads = 1;
 		params->RtcMemoryLock = 0;
+		params->SkipPamLock = 1;
 	} else {
 		params->PchLockDownGlobalSmi = 1;
 		params->PchLockDownBiosLock = 1;
@@ -155,6 +156,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PchWriteProtectionEnable[0] = 1;
 		params->PchUnlockGpioPads = 0;
 		params->RtcMemoryLock = 1;
+		params->SkipPamLock = 0;
 	}
 
 	/* Disable PAVP */
-- 
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