From 23c40997b408ba94328fdf7b8f1c4325512f15d7 Mon Sep 17 00:00:00 2001 From: Wentao Qin Date: Mon, 29 May 2023 18:47:00 +0800 Subject: =?UTF-8?q?mb/google/rex/var/screebo:=20Set=20TCC=20to=2090=C2=B0C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set tcc_offset value to 20 in devicetree for Thermal Control Circuit (TCC) activation feature for proto phase. BUG=b:282865187 BRANCH=None TEST=Build FW and test on Screebo board Change-Id: I3a929aa20a700376d2a0a150911fed34e67f78eb Signed-off-by: Wentao Qin Reviewed-on: https://review.coreboot.org/c/coreboot/+/75360 Reviewed-by: Subrata Banik Reviewed-by: Haikun Zhou Tested-by: build bot (Jenkins) --- src/mainboard/google/rex/variants/screebo/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 1178c07b68..ec59b8ff64 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -50,6 +50,9 @@ chip soc/intel/meteorlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" + # Temporary setting TCC of 90C = Tj max - Tcc + register "tcc_offset" = "20" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- cgit v1.2.3