From 2317b4f1140821051d8688a95fcfd7e0eedaa773 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 28 Nov 2019 12:59:44 +0100 Subject: sb/amd/cimx: replace cimx_util with common ACPIMMIO AMD block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the redundant cimx_util, remove the includes when appropriate and replace the implementation with amdblocks/acpimmio where needed. TEST=boot PC Engines apu1 and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski Change-Id: I66b1f82926372b6ebb570893b6eb73c7f2935b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37328 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Patrick Georgi --- src/mainboard/amd/inagua/mainboard.c | 6 +-- src/mainboard/amd/persimmon/mainboard.c | 6 +-- src/mainboard/amd/south_station/mainboard.c | 6 +-- src/mainboard/amd/union_station/mainboard.c | 6 +-- src/mainboard/asrock/e350m1/mainboard.c | 6 +-- src/mainboard/elmex/pcm205400/mainboard.c | 6 +-- src/mainboard/gizmosphere/gizmo/mainboard.c | 1 - src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 7 ++-- src/mainboard/lippert/frontrunner-af/mainboard.c | 6 +-- src/mainboard/lippert/toucan-af/mainboard.c | 6 +-- src/mainboard/pcengines/apu1/gpio_ftns.c | 17 +++----- src/mainboard/pcengines/apu1/mainboard.c | 1 - src/mainboard/pcengines/apu1/romstage.c | 10 ++--- src/mainboard/pcengines/apu2/gpio_ftns.c | 1 - src/southbridge/amd/cimx/Makefile.inc | 4 -- src/southbridge/amd/cimx/cimx_util.c | 51 ------------------------ src/southbridge/amd/cimx/cimx_util.h | 37 ----------------- src/southbridge/amd/cimx/sb800/Kconfig | 3 ++ src/southbridge/amd/cimx/sb800/fan.c | 12 +++--- 19 files changed, 46 insertions(+), 146 deletions(-) delete mode 100644 src/southbridge/amd/cimx/cimx_util.c delete mode 100644 src/southbridge/amd/cimx/cimx_util.h diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index cf40e262aa..83fe394be7 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ +#include #include #include -#include #include /* Platform Specific Definitions */ static void init_gpios(void) @@ -63,8 +63,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 43be863f4d..0e89ffde05 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ +#include #include #include #include #include -#include #include #include #include @@ -139,8 +139,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index c6f219662f..9b041e0111 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ +#include #include #include #include -#include #include /* Platform Specific Definitions */ /** @@ -59,8 +59,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index e2c0ac7370..d680520d47 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ +#include #include #include -#include #include /* Platform Specific Definitions */ /********************************************** @@ -31,8 +31,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index b83a57f78d..e2f4f2b259 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ +#include #include #include #include -#include #include /********************************************** @@ -46,8 +46,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index 43be863f4d..0e89ffde05 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ +#include #include #include #include #include -#include #include #include #include @@ -139,8 +139,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 36fa5f9074..8196922571 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include /********************************************** diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 3439d2fa4e..0a12c3f66a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ - +#include #include #include #include @@ -23,7 +23,6 @@ #include #include #include -#include #include /*********************************************************** @@ -142,8 +141,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 44d0104e00..ea473c035c 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -21,7 +22,6 @@ #include #include #include -#include #include #include /* SMBUS0_BASE_ADDRESS */ #include @@ -136,8 +136,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 746b1953f8..b000688da6 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -14,13 +14,13 @@ */ #include +#include #include #include #include #include #include #include -#include #include #include /* SMBUS0_BASE_ADDRESS */ #include @@ -101,8 +101,8 @@ static void mainboard_enable(struct device *dev) * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ - pm_iowrite(0x29, 0x80); - pm_iowrite(0x28, 0x61); + pm_write8(0x29, 0x80); + pm_write8(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c index 7a988e7ec6..bedd15a514 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.c +++ b/src/mainboard/pcengines/apu1/gpio_ftns.c @@ -14,25 +14,18 @@ */ #include +#include #include #include -#include #include "gpio_ftns.h" uintptr_t find_gpio_base(void) { - u8 pm_index, pm_data; - uintptr_t base_addr = 0; - - /* Find the ACPImmioAddr base address */ - for (pm_index = 0x27; pm_index > 0x23; pm_index--) { - outb(pm_index, PM_INDEX); - pm_data = inb(PM_DATA); - base_addr <<= 8; - base_addr |= (u32)pm_data; - } + uintptr_t base_addr; + /* Get the ACPIMMIO base address */ + base_addr = pm_read32(0x24); base_addr &= 0xFFFFF000; - return (base_addr); + return base_addr; } void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting) diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 088c839239..1c302912a9 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index ab48943c55..89bf3049d6 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ +#include #include -#include #include #include #include "gpio_ftns.h" @@ -33,16 +33,16 @@ static void early_lpc_init(void) * controlled in PM_REG 5Bh register. "Always Power On" works by writing a * value of 05h. */ - u8 bdata = pm_ioread(SB_PMIOA_REG5B); + u8 bdata = pm_read8(SB_PMIOA_REG5B); bdata &= 0xf8; //clear bits 0-2 bdata |= 0x05; //set bits 0,2 - pm_iowrite(SB_PMIOA_REG5B, bdata); + pm_write8(SB_PMIOA_REG5B, bdata); /* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */ - bdata = pm_ioread(SB_PMIOA_REGEA); + bdata = pm_read8(SB_PMIOA_REGEA); bdata &= 0xfe; //clear bit 0 bdata |= 0x01; //set bit 0 - pm_iowrite(SB_PMIOA_REGEA, bdata); + pm_write8(SB_PMIOA_REGEA, bdata); //configure required GPIOs mmio_base = find_gpio_base(); diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index a1e2e51952..249ecc3494 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -15,7 +15,6 @@ #include #include -#include #include #include "gpio_ftns.h" diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index 5d1d3f683b..6161c1493a 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -14,7 +14,3 @@ # subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 - -romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c - -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c diff --git a/src/southbridge/amd/cimx/cimx_util.c b/src/southbridge/amd/cimx/cimx_util.c deleted file mode 100644 index 1db04d8311..0000000000 --- a/src/southbridge/amd/cimx/cimx_util.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "cimx_util.h" - -static void pmio_write_index(u16 port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} - -static u8 pmio_read_index(u16 port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -} - -void pm_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM_INDEX, reg, value); -} - -u8 pm_ioread(u8 reg) -{ - return pmio_read_index(PM_INDEX, reg); -} - -void pm2_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM2_INDEX, reg, value); -} - -u8 pm2_ioread(u8 reg) -{ - return pmio_read_index(PM2_INDEX, reg); -} diff --git a/src/southbridge/amd/cimx/cimx_util.h b/src/southbridge/amd/cimx/cimx_util.h deleted file mode 100644 index bf41e8ab72..0000000000 --- a/src/southbridge/amd/cimx/cimx_util.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CIMX_UTIL_H -#define CIMX_UTIL_H - -#include - -/* FCH index/data registers */ -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 -#define PM2_INDEX 0xcd0 -#define PM2_DATA 0xcd1 -#define PCI_INTR_INDEX 0xc00 -#define PCI_INTR_DATA 0xc01 - -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); - -#endif /* CIMX_UTIL_H */ diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index aa5160b68f..0b790b06dc 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -21,6 +21,9 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select AMD_SB_CIMX select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index a8dfa31d9a..42c13d74a7 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include /* device_operations */ #include @@ -31,27 +31,27 @@ void init_sb800_MANUAL_fans(struct device *dev) /* Init Fan 0 */ if (sb_chip->fan0_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]); + pm2_write8(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]); /* Init Fan 1 */ if (sb_chip->fan1_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]); + pm2_write8(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]); /* Init Fan 2 */ if (sb_chip->fan2_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]); + pm2_write8(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]); /* Init Fan 3 */ if (sb_chip->fan3_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]); + pm2_write8(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]); /* Init Fan 4 */ if (sb_chip->fan4_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_iowrite(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]); + pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]); } -- cgit v1.2.3