From 22a6d11a5472080f38f1ef2def8fffc1a5de091c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 21 Jun 2020 18:50:22 +0200 Subject: mb/emulation/qemu-q35: Use common early SPI code Tested, it still boots. It is unknown whether this has any effect on emulated hardware, which is most likely not emulating SPI transfers. Change-Id: I44397c46dc0715697ca8680f418888804e4ea7e4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42669 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/emulation/qemu-q35/bootblock.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 3168f47756..fafa03b45d 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -37,20 +38,9 @@ static void bootblock_northbridge_init(void) die("You must run qemu for machine Q35 (-M q35)"); } -static void enable_spi_prefetch(void) -{ - u8 reg8; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); -} - static void bootblock_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetching_and_caching(); /* Enable RCBA */ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, -- cgit v1.2.3