From 21e2b5a0ce790b1f67c13a140b28635b3acf4a08 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Thu, 28 Jan 2021 10:57:53 -0800 Subject: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0 A minimum of 100ms delay is required before sending a configuration request to the downstream components. Since the kernel already adds 100ms, this change drops the extra 100ms delay in TBT PCIe root ports _PS0 method in order to improve resume time. BUG=b:177519081 TEST=Boot to kernel and validated various tests on Voxel. Signed-off-by: John Zhao Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50086 Reviewed-by: Duncan Laurie Reviewed-by: Tim Wawrzynczak Reviewed-by: Sukumar Ghorai Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/acpi/tcss_pcierp.asl | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 08d890087c..39180f7393 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -196,8 +196,6 @@ Method (_PS0, 0, Serialized) If (PMEX == 1) { PMEX = 0 /* Disable Power Management SCI */ } - - Sleep(100) /* Wait for 100ms before return to OS starts any OS activities. */ } Method (_PS3, 0, Serialized) -- cgit v1.2.3