From 21be665c9a449cff7f9c07e41b032c2d8f596c55 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 27 Sep 2023 16:47:15 -0600 Subject: mb/amd/onyx: Add USB configuration Drive board specific USB configuration from the coreboot devicetree into the opensil input block. In the process of scrubbing opensil for public release USB became non functional. Signed-off-by: Arthur Heymans Signed-off-by: Martin Roth Change-Id: I62eefe1061446612168dd27e673a2742903456c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78920 Reviewed-by: Varshit Pandya Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/amd/onyx/devicetree.cb | 39 ++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb index 2b37b761fd..04262e3785 100644 --- a/src/mainboard/amd/onyx/devicetree.cb +++ b/src/mainboard/amd/onyx/devicetree.cb @@ -1,5 +1,31 @@ chip soc/amd/genoa + # USB configuration + register "usb.xhci0_enable" = "1" + register "usb.xhci1_enable" = "1" + # OC pins + register "usb.usb2_oc_pins[0].port0" = "0x0" + register "usb.usb2_oc_pins[0].port1" = "0x1" + register "usb.usb2_oc_pins[0].port2" = "0x0" + register "usb.usb2_oc_pins[0].port3" = "0x1" + + register "usb.usb2_oc_pins[1].port0" = "0x0" + register "usb.usb2_oc_pins[1].port1" = "0x1" + + register "usb.usb3_oc_pins[0].port0" = "0x0" + register "usb.usb3_oc_pins[0].port1" = "0x1" + register "usb.usb3_oc_pins[0].port2" = "0x0" + register "usb.usb3_oc_pins[0].port3" = "0x1" + register "usb.usb3_oc_pins[1].port0" = "0x0" + register "usb.usb3_oc_pins[1].port1" = "0x1" + + register "usb.polarity_cfg_low" = "true" + + register "usb.usb3_force_gen1.port0" = "3" + register "usb.usb3_force_gen1.port1" = "3" + register "usb.usb3_force_gen1.port2" = "3" + register "usb.usb3_force_gen1.port3" = "3" + # eSPI configuration register "common_config.espi_config" = "{ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN, @@ -13,6 +39,19 @@ chip soc/amd/genoa .flash_ch_en = 0, }" + # PHY settings + register "usb.usb31_phy_enable" = "1" + register "usb.usb31_phy" = "{ + {0x01, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00}, + {0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00}, + {0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00}, + {0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00}, + {0x05, 0x01, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05}, + {0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05}, + {0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05}, + {0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05}, + }" + device domain 0 on end -- cgit v1.2.3