From 2151f7561d728a9280d69d20ef56a9fe44db7cb1 Mon Sep 17 00:00:00 2001
From: V Sowmya <v.sowmya@intel.com>
Date: Wed, 20 Jan 2021 08:00:26 +0530
Subject: mb/intel/shadowmountain: Add the ASL code

This patch includes the DSDT ASL code for shadowmountain board.

BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49733
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/shadowmountain/dsdt.asl | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl
index c8dc9ee2c3..f94ad378c9 100644
--- a/src/mainboard/intel/shadowmountain/dsdt.asl
+++ b/src/mainboard/intel/shadowmountain/dsdt.asl
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <acpi/acpi.h>
+#include <baseboard/ec.h>
+#include <baseboard/gpio.h>
 
 DefinitionBlock(
 	"dsdt.aml",
@@ -12,4 +14,31 @@ DefinitionBlock(
 )
 {
 	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	/* CPU */
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+			#include <soc/intel/alderlake/acpi/southbridge.asl>
+			#include <soc/intel/alderlake/acpi/tcss.asl>
+		}
+	}
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		// ACPI code for EC SuperIO functions
+		#include <ec/google/chromeec/acpi/superio.asl>
+		// ACPI code for EC functions
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
 }
-- 
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