From 1f30de08f67a534eac5d30b414f231c1166a817e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 26 Oct 2019 10:44:33 +0200 Subject: soc/intel/cannonlake: set FSP param to enable or skip GOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to enable or skip GOP. Change-Id: I7f7b2c688e46534046dc0976458c4c96614100b0 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36351 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/fsp_params.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 74884fde1f..0713ef4604 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -460,6 +460,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SpiFlashCfgLockDown = 1; #endif } + + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; } /* Mainboard GPIO Configuration */ -- cgit v1.2.3