From 1ce0b3022c723ca7c9f00cc884e8e3282cb0dcdb Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 10 Oct 2013 12:47:47 -0500 Subject: baytrail: allow downstream use of SSE instructions If a payload is compiled to use SSE instructions it will fault with an undefined opcode because SSE instructions weren't enabled. Therefore enable SSE instructions at runtime. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted with SSE enabled payload. No exceptions seen. Change-Id: I919c1ad319c6ce8befec5b4b1fd8c6343d51ccc1 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/172642 Reviewed-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/4881 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/soc/intel/baytrail/ramstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 10c030fcb3..229e3679df 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -109,6 +110,9 @@ void baytrail_init_pre_device(void) fill_in_pattrs(); + /* Allow for SSE instructions to be executed. */ + write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + /* Get GPIO initial states from mainboard */ config = mainboard_get_gpios(); setup_soc_gpios(config); -- cgit v1.2.3