From 1a5c3bb7fa56378664ce221cd749f118ef6a09f6 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Fri, 13 Dec 2019 23:37:22 +1100 Subject: mainboard/google/puff: Toggle on DqPinsInterleaved BRANCH=none BUG=b:146172098 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ib2da3baace9255ef25c0f03390a064fd77ef9ae5 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37696 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh Reviewed-by: Kangheui Won --- src/mainboard/google/hatch/romstage_spd_smbus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index 74d59a59f5..9073744850 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -45,6 +45,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */ memcfg.vref_ca_config = 2; + memcfg.dq_pins_interleaved = 1; cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } -- cgit v1.2.3