From 17d71937a19604090258853b0856dfbe915edb0e Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 27 Jul 2022 10:05:29 -0600 Subject: mb/google/brya/var/agah: Optimize dGPU GCOFF entry After staring at lots of scope shots, the EE has determined that a few modifications to the GCOFF sequence can be made: - Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion - Remove delay after ramping down FBVDD This patch implements these minor changes. BUG=b:240199017 TEST=verified by EE Signed-off-by: Tim Wawrzynczak Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Ivy Jian Reviewed-by: Subrata Banik --- src/mainboard/google/brya/acpi/power.asl | 2 -- src/mainboard/google/brya/variants/agah/variant.c | 3 +-- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl index e52ff8753c..6f69c89374 100644 --- a/src/mainboard/google/brya/acpi/power.asl +++ b/src/mainboard/google/brya/acpi/power.asl @@ -174,7 +174,6 @@ Method (PGOF, 0, Serialized) /* Assert PERST# */ \_SB.PCI0.CTXS (GPIO_GPU_PERST_L) - Sleep (5) /* All rails are about to go down */ \_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG) @@ -183,7 +182,6 @@ Method (PGOF, 0, Serialized) /* Ramp down FBVDD (active-low) and let rail discharge to <10% */ \_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN) GPPL (GPIO_FBVDD_PG, 0, 20) - Sleep (40) /* Ramp down PEXVDD and let rail discharge to <10% */ \_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN) diff --git a/src/mainboard/google/brya/variants/agah/variant.c b/src/mainboard/google/brya/variants/agah/variant.c index b0baab356b..841d210469 100644 --- a/src/mainboard/google/brya/variants/agah/variant.c +++ b/src/mainboard/google/brya/variants/agah/variant.c @@ -56,7 +56,7 @@ static const struct power_rail_sequence gpu_on_seq[] = { /* In GCOFF entry order (i.e., power-off order) */ static const struct power_rail_sequence gpu_off_seq[] = { - { "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, 40,}, + { "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, 0,}, { "PEXVDD", PEXVDD_PWR_EN, false, PEXVDD_PG, 10,}, { "NVVDD+MSVDD", NVVDD_PWR_EN, false, NVVDD_PG, 2,}, { "NV3_3", NV33_PWR_EN, false, NV33_PG, 4,}, @@ -89,7 +89,6 @@ static void dgpu_power_sequence_off(void) { /* Assert reset and clear power-good */ gpio_output(GPU_PERST_L, 0); - mdelay(5); /* Inform the GPU that the power is no longer good. */ gpio_output(GPU_ALLRAILS_PG, 0); -- cgit v1.2.3