From 142b10ee1fa1c68f0c147665ff55b43eb8f0317d Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 1 Jul 2019 08:54:56 +0300 Subject: cpu/x86: Fix MSR_PLATFORM_INFO definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While common to many Intel CPUs, this is not an architectural MSR that should be globally defined for all x86. Change-Id: Ibeed022dc2ba2e90f71511f9bd2640a7cafa5292 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34090 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: David Guckian --- src/include/cpu/x86/tsc.h | 2 -- src/northbridge/intel/fsp_rangeley/udelay.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 8dd9b7519c..dd333e8930 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -11,8 +11,6 @@ #define TSC_SYNC #endif -#define MSR_PLATFORM_INFO 0xce - struct tsc_struct { unsigned int lo; unsigned int hi; diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c index 01989abb37..08301a37f6 100644 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ b/src/northbridge/intel/fsp_rangeley/udelay.c @@ -18,6 +18,8 @@ #include #include +#define MSR_PLATFORM_INFO 0xce + /** * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz */ -- cgit v1.2.3