From 13e7a2fd353cb07802c86f2258d41a2c5e54eab7 Mon Sep 17 00:00:00 2001 From: Matthew Garrett Date: Fri, 19 Jul 2019 17:02:07 -0700 Subject: soc/intel/skylake: Enable Energy/Performance Bias control Bit 18 of MSR_POWER_CTL is documented as reserved, but we're setting it on Haswell in order to enable EPB. It seems to work on SKL/KBL as well, so do it there too. Signed-off-by: Matthew Garrett Change-Id: I83da1a57a04dac206cc67f2c256d0c102965abc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34458 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/skylake/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5f4ce87236..2fd01b471a 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -313,6 +313,7 @@ static void configure_misc(void) msr = rdmsr(MSR_POWER_CTL); msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */ msr.lo &= ~POWER_CTL_C1E_MASK; /* Disable C1E */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); -- cgit v1.2.3