From 1366e4438d07c2de905454421e18d1e5f68de47d Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 29 Sep 2020 13:55:50 +0530 Subject: soc/intel: Move pch_enable_ioapic() to common code List of changes: 1. Move pch_enable_ioapic() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/lpc.c | 24 +-------------------- .../common/block/include/intelblocks/lpc_lib.h | 2 ++ src/soc/intel/common/block/lpc/lpc_lib.c | 25 ++++++++++++++++++++++ src/soc/intel/elkhartlake/espi.c | 24 +-------------------- src/soc/intel/icelake/espi.c | 24 +-------------------- src/soc/intel/jasperlake/espi.c | 24 +-------------------- src/soc/intel/skylake/lpc.c | 25 +--------------------- src/soc/intel/tigerlake/espi.c | 24 +-------------------- src/soc/intel/xeon_sp/cpx/chip.c | 24 ++------------------- 9 files changed, 35 insertions(+), 161 deletions(-) diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 50af9ee360..9d36f32970 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -90,28 +90,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} /* * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -207,7 +185,7 @@ void lpc_soc_init(struct device *dev) lpc_set_serirq_mode(config->serirq_mode); /* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index ff4ba1ad05..5bbc384e82 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -107,5 +107,7 @@ void soc_setup_dmi_pcr_io_dec(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); /* Add resource into LPC PCI device space */ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset, uintptr_t base, size_t size, unsigned long flags); +/* Enable PCH IOAPIC */ +void pch_enable_ioapic(void); #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index ff44cc1a67..87ee11056e 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -2,6 +2,7 @@ #define __SIMPLE_DEVICE__ +#include #include #include #include @@ -292,3 +293,27 @@ void lpc_disable_clkrun(void) const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL); pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN); } + +/* Enable PCH IOAPIC */ +void pch_enable_ioapic(void) +{ + uint32_t reg32; + /* PCH-LP has 120 redirection entries */ + const int redir_entries = 120; + + set_ioapic_id((void *)IO_APIC_ADDR, 0x02); + + /* affirm full set of redirection table entries ("write once") */ + reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); + + reg32 &= ~0x00ff0000; + reg32 |= (redir_entries - 1) << 16; + + io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); +} diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index 71339971fa..241262344f 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -64,28 +64,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - uint32_t reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} /* * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -182,7 +160,7 @@ void lpc_soc_init(struct device *dev) lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 1497c8d8e4..bf5c50d7f6 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -83,28 +83,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} /* * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -201,7 +179,7 @@ void lpc_soc_init(struct device *dev) lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index bf82067b8c..24b50579fc 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -65,28 +65,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} /* * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -183,7 +161,7 @@ void lpc_soc_init(struct device *dev) lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 7dc90f07a1..e514e1a66a 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -29,29 +29,6 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) return skl_lpc_fixed_mmio_ranges; } -static void pch_enable_ioapic(struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} - void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) { const config_t *config = config_of(dev); @@ -96,7 +73,7 @@ void lpc_soc_init(struct device *dev) lpc_set_serirq_mode(config->serirq_mode); /* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 513da5a79e..eb44a6a65d 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -71,28 +71,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} /* * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -189,7 +167,7 @@ void lpc_soc_init(struct device *dev) lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ - pch_enable_ioapic(dev); + pch_enable_ioapic(); soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 5ee7f6c0a4..11fe44b1b2 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -557,27 +558,6 @@ static void attach_iio_stacks(struct device *dev) DEV_FUNC_EXIT(dev); } -static void pch_enable_ioapic(const struct device *dev) -{ - uint32_t reg32; - - set_ioapic_id((void *)IO_APIC_ADDR, 2); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 1); - - reg32 &= ~0x00ff0000; - reg32 |= (C620_IOAPIC_REDIR_ENTRIES - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 1, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 3, 1); -} - struct pci_operations soc_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -604,7 +584,7 @@ static void chip_init(void *data) { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(false); - pch_enable_ioapic(NULL); + pch_enable_ioapic(); setup_lapic(); p2sb_unhide(); } -- cgit v1.2.3