From 11284d7d4374c15e81e805301d448de1a8576a18 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 13 Jan 2018 17:11:37 +0200 Subject: AGESA f15 cimx/sb700: Remove vendorcode source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: If5a72786d1119908073488c1d6d8787ac0f4f95c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/23276 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/vendorcode/amd/agesa/f15/AGESA.h | 3562 ------------------ src/vendorcode/amd/agesa/f15/AMD.h | 478 --- .../amd/agesa/f15/Config/OptionApmInstall.h | 87 - .../amd/agesa/f15/Config/OptionC6Install.h | 164 - .../amd/agesa/f15/Config/OptionCpbInstall.h | 170 - .../f15/Config/OptionCpuCacheFlushOnHaltInstall.h | 126 - .../f15/Config/OptionCpuCoreLevelingInstall.h | 120 - .../agesa/f15/Config/OptionCpuFamiliesInstall.h | 382 -- .../agesa/f15/Config/OptionCpuFeaturesInstall.h | 80 - .../amd/agesa/f15/Config/OptionDmiInstall.h | 213 -- .../amd/agesa/f15/Config/OptionFamily10hInstall.h | 2056 ----------- .../amd/agesa/f15/Config/OptionFamily15hInstall.h | 1570 -------- .../amd/agesa/f15/Config/OptionFchInstall.h | 988 ----- .../agesa/f15/Config/OptionGfxRecoveryInstall.h | 52 - .../amd/agesa/f15/Config/OptionGnbInstall.h | 591 --- .../amd/agesa/f15/Config/OptionHtInstall.h | 319 -- .../amd/agesa/f15/Config/OptionHwC1eInstall.h | 79 - .../amd/agesa/f15/Config/OptionIdsInstall.h | 581 --- .../amd/agesa/f15/Config/OptionIoCstateInstall.h | 133 - .../amd/agesa/f15/Config/OptionL3FeaturesInstall.h | 117 - .../agesa/f15/Config/OptionLowPwrPstateInstall.h | 87 - .../amd/agesa/f15/Config/OptionMemoryInstall.h | 3778 -------------------- .../agesa/f15/Config/OptionMsgBasedC1eInstall.h | 116 - .../agesa/f15/Config/OptionMultiSocketInstall.h | 103 - .../f15/Config/OptionPreserveMailboxInstall.h | 123 - .../agesa/f15/Config/OptionPstateHpcModeInstall.h | 88 - .../amd/agesa/f15/Config/OptionPstateInstall.h | 264 -- .../amd/agesa/f15/Config/OptionS3ScriptInstall.h | 90 - .../amd/agesa/f15/Config/OptionSlitInstall.h | 78 - .../amd/agesa/f15/Config/OptionSratInstall.h | 72 - .../amd/agesa/f15/Config/OptionSwC1eInstall.h | 79 - .../amd/agesa/f15/Config/OptionWheaInstall.h | 73 - .../amd/agesa/f15/Config/PlatformInstall.h | 2615 -------------- src/vendorcode/amd/agesa/f15/Dispatcher.h | 50 - src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h | 165 - .../amd/agesa/f15/Include/CommonReturns.h | 123 - src/vendorcode/amd/agesa/f15/Include/Filecode.h | 1174 ------ .../amd/agesa/f15/Include/GeneralServices.h | 200 -- .../amd/agesa/f15/Include/GnbInterface.h | 100 - .../amd/agesa/f15/Include/GnbInterfaceStub.h | 301 -- src/vendorcode/amd/agesa/f15/Include/GnbPage.h | 1972 ---------- src/vendorcode/amd/agesa/f15/Include/Ids.h | 1159 ------ src/vendorcode/amd/agesa/f15/Include/IdsHt.h | 122 - .../amd/agesa/f15/Include/MaranelloInstall.h | 116 - src/vendorcode/amd/agesa/f15/Include/OptionDmi.h | 88 - .../agesa/f15/Include/OptionFamily15hEarlySample.h | 231 -- .../amd/agesa/f15/Include/OptionGfxRecovery.h | 80 - src/vendorcode/amd/agesa/f15/Include/OptionGnb.h | 109 - .../amd/agesa/f15/Include/OptionMemory.h | 358 -- .../amd/agesa/f15/Include/OptionMultiSocket.h | 214 -- .../amd/agesa/f15/Include/OptionPstate.h | 114 - src/vendorcode/amd/agesa/f15/Include/OptionSlit.h | 95 - src/vendorcode/amd/agesa/f15/Include/OptionSrat.h | 81 - src/vendorcode/amd/agesa/f15/Include/OptionWhea.h | 82 - src/vendorcode/amd/agesa/f15/Include/Options.h | 69 - src/vendorcode/amd/agesa/f15/Include/OptionsHt.h | 110 - src/vendorcode/amd/agesa/f15/Include/OptionsPage.h | 378 -- .../f15/Include/PlatformMemoryConfiguration.h | 499 --- .../amd/agesa/f15/Include/SanMarinoInstall.h | 116 - src/vendorcode/amd/agesa/f15/Include/Topology.h | 161 - .../amd/agesa/f15/Legacy/Proc/Dispatcher.c | 136 - .../amd/agesa/f15/Legacy/Proc/Makefile.inc | 3 - .../amd/agesa/f15/Legacy/Proc/agesaCallouts.c | 441 --- .../amd/agesa/f15/Legacy/Proc/hobTransfer.c | 393 -- src/vendorcode/amd/agesa/f15/MainPage.h | 120 - src/vendorcode/amd/agesa/f15/Makefile.inc | 55 - .../f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c | 126 - .../agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c | 300 -- .../Proc/CPU/Family/0x10/F10MultiLinkPciTables.c | 1537 -------- .../f15/Proc/CPU/Family/0x10/F10PackageType.h | 84 - .../f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c | 176 - .../f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h | 78 - .../CPU/Family/0x10/F10PmDualPlaneOnlySupport.c | 243 -- .../CPU/Family/0x10/F10PmDualPlaneOnlySupport.h | 78 - .../f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c | 296 -- .../f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h | 77 - .../f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c | 185 - .../f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.h | 77 - .../Proc/CPU/Family/0x10/F10SingleLinkPciTables.c | 2251 ------------ .../agesa/f15/Proc/CPU/Family/0x10/Makefile.inc | 34 - .../Family/0x10/RevD/F10MicrocodePatch010000c5.c | 1039 ------ .../Family/0x10/RevD/F10MicrocodePatch010000d9.c | 1039 ------ .../Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c | 516 --- .../Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c | 282 -- .../Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c | 455 --- .../Family/0x10/RevD/HY/F10HyEquivalenceTable.c | 114 - .../CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c | 1294 ------- .../CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c | 144 - .../CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c | 116 - .../0x10/RevD/HY/F10HyMicrocodePatchTables.c | 114 - .../Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c | 137 - .../Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c | 384 -- .../f15/Proc/CPU/Family/0x10/RevD/HY/Makefile.inc | 14 - .../f15/Proc/CPU/Family/0x10/RevD/Makefile.inc | 10 - .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.c | 329 -- .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.h | 120 - .../agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c | 160 - .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c | 335 -- .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c | 136 - .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c | 135 - .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c | 179 - .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c | 127 - .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c | 128 - .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c | 142 - .../f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c | 131 - .../Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c | 167 - .../amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Cpb.c | 169 - .../amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c | 519 --- .../f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c | 454 --- .../f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.h | 79 - .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c | 393 -- .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h | 195 - .../f15/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c | 751 ---- .../f15/Proc/CPU/Family/0x10/cpuF10MsrTables.c | 289 -- .../f15/Proc/CPU/Family/0x10/cpuF10PciTables.c | 772 ---- .../f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c | 411 --- .../f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.h | 83 - .../f15/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h | 547 --- .../CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c | 182 - .../f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.c | 485 --- .../f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.h | 77 - .../agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c | 894 ----- .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c | 124 - .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h | 79 - .../f15/Proc/CPU/Family/0x10/cpuF10Utilities.c | 1176 ------ .../f15/Proc/CPU/Family/0x10/cpuF10Utilities.h | 206 -- .../CPU/Family/0x10/cpuF10WheaInitDataTables.c | 128 - .../Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c | 184 - .../f15/Proc/CPU/Family/0x15/F15PackageType.h | 79 - .../f15/Proc/CPU/Family/0x15/F15PstateHpcMode.c | 208 -- .../agesa/f15/Proc/CPU/Family/0x15/Makefile.inc | 11 - .../f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c | 186 - .../agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c | 183 - .../Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c | 834 ----- .../CPU/Family/0x15/OR/F15OrEquivalenceTable.c | 135 - .../f15/Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c | 833 ----- .../Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c | 187 - .../f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c | 377 -- .../f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c | 549 --- .../Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c | 120 - .../Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c | 234 -- .../Family/0x15/OR/F15OrMicrocodePatch06000425.c | 2673 -------------- .../0x15/OR/F15OrMicrocodePatch0600050D_Enc.c | 2674 -------------- .../0x15/OR/F15OrMicrocodePatch06000624_Enc.c | 2673 -------------- .../CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c | 112 - .../f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c | 305 -- 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.../f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c | 422 --- .../CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c | 422 --- .../CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.h | 211 -- .../Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c | 349 -- .../Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.h | 79 - .../Proc/CPU/Family/0x15/OR/cpuF15OrPowerMgmt.h | 534 --- .../f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c | 920 ----- .../CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c | 128 - .../CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.h | 79 - .../Proc/CPU/Family/0x15/cpuCommonF15Utilities.c | 179 - .../Proc/CPU/Family/0x15/cpuCommonF15Utilities.h | 90 - .../amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c | 124 - .../agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c | 221 -- .../f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c | 196 - .../amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c | 122 - .../amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.h | 75 - .../f15/Proc/CPU/Family/0x15/cpuF15MsrTables.c | 136 - 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src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c | 160 - src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S | 209 -- .../amd/agesa/f15/Proc/CPU/cpuApicUtilities.c | 1443 -------- .../amd/agesa/f15/Proc/CPU/cpuApicUtilities.h | 304 -- src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBist.c | 172 - src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBrandId.c | 313 -- .../amd/agesa/f15/Proc/CPU/cpuEarlyInit.c | 411 --- .../amd/agesa/f15/Proc/CPU/cpuEarlyInit.h | 302 -- src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEnvInit.h | 72 - .../amd/agesa/f15/Proc/CPU/cpuEventLog.c | 409 --- .../amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.c | 484 --- .../amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h | 1008 ------ .../amd/agesa/f15/Proc/CPU/cpuGeneralServices.c | 1237 ------- .../amd/agesa/f15/Proc/CPU/cpuInitEarlyTable.c | 125 - .../amd/agesa/f15/Proc/CPU/cpuLateInit.c | 392 -- .../amd/agesa/f15/Proc/CPU/cpuLateInit.h | 888 ----- .../amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c | 422 --- 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sub-project: Include - * @e \$Revision: 60222 $ @e \$Date: 2011-10-10 23:39:36 -0600 (Mon, 10 Oct 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#ifndef _AGESA_H_ -#define _AGESA_H_ - -#include "Porting.h" -#include "AMD.h" - -// -// -// AGESA Types and Definitions -// -// - -// AGESA BASIC CALLOUTS -#define AGESA_MEM_RELEASE 0x00028000 - -// AGESA ADVANCED CALLOUTS, Processor -#define AGESA_CHECK_UMA 0x00028100 -#define AGESA_DO_RESET 0x00028101 -#define AGESA_ALLOCATE_BUFFER 0x00028102 -#define AGESA_DEALLOCATE_BUFFER 0x00028103 -#define AGESA_LOCATE_BUFFER 0x00028104 -#define AGESA_RUNFUNC_ONAP 0x00028105 - -// AGESA ADVANCED CALLOUTS, HyperTransport - -// AGESA ADVANCED CALLOUTS, Memory -#define AGESA_READ_SPD 0x00028140 -#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141 -#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142 -#define AGESA_READ_SPD_RECOVERY 0x00028143 -#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144 -#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145 -#define AGESA_EXTERNAL____TRAIN_VREF_CHANGE 0x00028146 - -// AGESA IDS CALLOUTS -#define AGESA_GET_IDS_INIT_DATA 0x00028200 - -// AGESA GNB CALLOUTS -#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301 - -// AGESA FCH CALLOUTS -#define AGESA_FCH_OEM_CALLOUT 0x00028401 - -//------------------------------------------------------------------------ -// -// HyperTransport Interface - - - -//----------------------------------------------------------------------------- -// HT DEFINITIONS AND MACROS -// -//----------------------------------------------------------------------------- - - -// Width equates for call backs -#define HT_WIDTH_8_BITS 8 ///< Specifies 8 bit, or up to 8 bit widths. -#define HT_WIDTH_16_BITS 16 ///< Specifies 16 bit, or up to 16 bit widths. -#define HT_WIDTH_4_BITS 4 -#define HT_WIDTH_2_BITS 2 -#define HT_WIDTH_NO_LIMIT HT_WIDTH_16_BITS - -// Frequency Limit equates for call backs which take a frequency supported mask. -#define HT_FREQUENCY_LIMIT_200M 1 ///< Specifies a limit of no more than 200 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_400M 7 ///< Specifies a limit of no more than 400 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_600M 0x1F ///< Specifies a limit of no more than 600 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_800M 0x3F ///< Specifies a limit of no more than 800 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_1000M 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_HT1_ONLY 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_1200M 0xFF ///< Specifies a limit of no more than 1200 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_1400M 0x1FF ///< Specifies a limit of no more than 1400 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_1600M 0x3FF ///< Specifies a limit of no more than 1600 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_1800M 0x7FF ///< Specifies a limit of no more than 1800 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_2000M 0xFFF ///< Specifies a limit of no more than 2000 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_2200M 0x1FFF ///< Specifies a limit of no more than 2200 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_2400M 0x3FFF ///< Specifies a limit of no more than 2400 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_2600M 0x7FFF ///< Specifies a limit of no more than 2600 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_2800M 0x27FFF ///< Specifies a limit of no more than 2800 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_3000M 0x67FFF ///< Specifies a limit of no more than 3000 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_3200M 0xE7FFF ///< Specifies a limit of no more than 3200 MHz HT frequency. -#define HT_FREQUENCY_LIMIT_3600M 0x1E7FFF -#define HT_FREQUENCY_LIMIT_MAX HT_FREQUENCY_LIMIT_3600M -#define HT_FREQUENCY_NO_LIMIT 0xFFFFFFFF ///< Specifies a no limit of HT frequency. - -// Unit ID Clumping special values -#define HT_CLUMPING_DISABLE 0x00000000 -#define HT_CLUMPING_NO_LIMIT 0xFFFFFFFF - -#define HT_LIST_TERMINAL 0xFF ///< End of list. -#define HT_LIST_MATCH_ANY 0xFE ///< Match Any value, used for Sockets, Links, IO Chain Depth. -#define HT_LIST_MATCH_INTERNAL_LINK 0xFD ///< Match all of the internal links. - -// Event Notify definitions - -// Event definitions. - -// Coherent subfunction events -#define HT_EVENT_COH_EVENTS 0x10001000 -#define HT_EVENT_COH_NO_TOPOLOGY 0x10011000 ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY. -#define HT_EVENT_COH_OBSOLETE000 0x10021000 // No longer used. -#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000 ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX. -#define HT_EVENT_COH_NODE_DISCOVERED 0x10041000 ///< See ::HT_EVENT_COH_NODE_DISCOVERED. -#define HT_EVENT_COH_MPCAP_MISMATCH 0x10051000 ///< See ::HT_EVENT_COH_MPCAP_MISMATCH. - -// Non-coherent subfunction events -#define HT_EVENT_NCOH_EVENTS 0x10002000 -#define HT_EVENT_NCOH_BUID_EXCEED 0x10012000 ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED -#define HT_EVENT_NCOH_OBSOLETE000 0x10022000 // No longer used. -#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000 ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED. -#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000 ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED. -#define HT_EVENT_NCOH_DEVICE_FAILED 0x10052000 ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED -#define HT_EVENT_NCOH_AUTO_DEPTH 0x10062000 ///< See ::HT_EVENT_NCOH_AUTO_DEPTH - -// Optimization subfunction events -#define HT_EVENT_OPT_EVENTS 0x10003000 -#define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x10013000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP. -#define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x10023000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP. -#define HT_EVENT_OPT_UNUSED_LINKS 0x10033000 ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS. -#define HT_EVENT_OPT_LINK_PAIR_EXCEED 0x10043000 ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED. - -// HW Fault events -#define HT_EVENT_HW_EVENTS 0x10004000 -#define HT_EVENT_HW_SYNCFLOOD 0x10014000 ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD. -#define HT_EVENT_HW_HTCRC 0x10024000 ///< See ::HT_EVENT_DATA_HW_HT_CRC. - -// The Recovery HT component uses 0x10005000 for events. -// For consistency, we avoid that range here. - -#define HT_MAX_NC_BUIDS 32 -//---------------------------------------------------------------------------- -// HT TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- - -/// Specify the state redundant links are to be left in after match. -/// -/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone, -/// or powered off. - -typedef enum { - MATCHED, ///< The link matches the requested customization. - ///< When used with IGNORE_LINK, - ///< this will generally require other software to initialize the link. - ///< When used with SKIP_REGANG, - ///< the two unganged links will be available for distribution. - - POWERED_OFF, ///< Power the link off. Support may vary based on processor model. - ///< Power Off is only supported for coherent links. - ///< Link power off may occur at a warm reset rather than immediately. - ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link. - - UNMATCHED, ///< The link should be processed according to normal defaults. - ///< Effectively, the link does not match the requested customization. - ///< This can be used to exclude links from a following match any. - - MaxFinalLinkState ///< Not a final link state, use for limit checking. -} FINAL_LINK_STATE; - -/// Swap a device from its current id to a new one. - -typedef struct { - IN UINT8 FromId; ///< The device responding to FromId, - IN UINT8 ToId; ///< will be moved to ToId. -} BUID_SWAP_ITEM; - - -/// Each Non-coherent chain may have a list of device swaps. After performing the swaps, -/// the final in order list of device ids is provided. (There can be more swaps than devices.) -/// The unused entries in both are filled with 0xFF. - -typedef struct { - IN BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform - IN UINT8 FinalIds[HT_MAX_NC_BUIDS]; ///< The ordered final BUIDs, resulting from the swaps -} BUID_SWAP_LIST; - - -/// Control Manual Initialization of Non-Coherent Chains -/// -/// This interface is checked every time a non-coherent chain is -/// processed. BUID assignment may be controlled explicitly on a -/// non-coherent chain. Provide a swap list. Swaps controls the -/// BUID assignment and FinalIds provides the device to device -/// Linking. Device orientation can be detected automatically, or -/// explicitly. See interface documentation for more details. -/// -/// If a manual swap list is not supplied, -/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially -/// based on each device's unit count. - -typedef struct { - // Match fields - IN UINT8 Socket; ///< The Socket on which this chain is located - IN UINT8 Link; ///< The Link on the host for this chain - // Override fields - IN BUID_SWAP_LIST SwapList; ///< The swap list -} MANUAL_BUID_SWAP_LIST; - - -/// Override options for DEVICE_CAP_OVERRIDE. -/// -/// Specify which override actions should be performed. For Checks, 1 means to check the item -/// and 0 means to skip the check. For the override options, 1 means to apply the override and -/// 0 means to ignore the override. - -typedef struct { - IN UINT32 IsCheckDevVenId:1; ///< Check Match on Device/Vendor id - IN UINT32 IsCheckRevision:1; ///< Check Match on device Revision - IN UINT32 IsOverrideWidthIn:1; ///< Override Width In - IN UINT32 IsOverrideWidthOut:1; ///< Override Width Out - IN UINT32 IsOverrideFreq:1; ///< Override Frequency - IN UINT32 IsOverrideClumping:1; ///< Override Clumping - IN UINT32 IsDoCallout:1; ///< Make the optional callout -} DEVICE_CAP_OVERRIDE_OPTIONS; - -/// Override capabilities of a device. -/// -/// This interface is checked once for every Link on every IO device. -/// Provide the width and frequency capability if needed for this device. -/// This is used along with device capabilities, the limit interfaces, and northbridge -/// limits to compute the default settings. The components of the device's PCI config -/// address are provided, so its settings can be consulted if need be. -/// The optional callout is a catch all. - -typedef struct { - // Match fields - IN UINT8 HostSocket; ///< The Socket on which this chain is located. - IN UINT8 HostLink; ///< The Link on the host for this chain. - IN UINT8 Depth; ///< The Depth in the I/O chain from the Host. - IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00). - IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08). - IN UINT8 Link; ///< The Device's Link number (0 or 1). - IN DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override. - // Override fields - IN UINT8 LinkWidthIn; ///< modify to change the Link Width In. - IN UINT8 LinkWidthOut; ///< modify to change the Link Width Out. - IN UINT32 FreqCap; ///< modify to change the Link's frequency capability. - IN UINT32 Clumping; ///< modify to change Unit ID clumping support. - IN CALLOUT_ENTRY Callout; ///< optional call for really complex cases, or NULL. -} DEVICE_CAP_OVERRIDE; - -/// Callout param struct for override capabilities of a device. -/// -/// If the optional callout is implemented this param struct is passed to it. - -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - // Match fields - IN UINT8 HostSocket; ///< The Socket on which this chain is located. - IN UINT8 HostLink; ///< The Link on the host for this chain. - IN UINT8 Depth; ///< The Depth in the I/O chain from the Host. - IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00). - IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08). - IN UINT8 Link; ///< The Device's Link number (0 or 1). - IN PCI_ADDR PciAddress; ///< The Device's PCI Address. - // Override fields - OUT UINT8 *LinkWidthIn; ///< modify to change the Link Width In. - OUT UINT8 *LinkWidthOut; ///< modify to change the Link Width Out. - OUT UINT32 *FreqCap; ///< modify to change the Link's frequency capability. - OUT UINT32 *Clumping; ///< modify to change Unit ID clumping support. -} DEVICE_CAP_CALLOUT_PARAMS; - -/// Limits for CPU to CPU Links. -/// -/// For each coherent connection this interface is checked once. -/// Provide the frequency and width if needed for this Link (usually based on board -/// restriction). This is used with CPU device capabilities and northbridge limits -/// to compute the default settings. - -typedef struct { - // Match fields - IN UINT8 SocketA; ///< One Socket on which this Link is located - IN UINT8 LinkA; ///< The Link on this Node - IN UINT8 SocketB; ///< The other Socket on which this Link is located - IN UINT8 LinkB; ///< The Link on that Node - // Limit fields - IN UINT8 ABLinkWidthLimit; ///< modify to change the Link Width A->B - IN UINT8 BALinkWidthLimit; ///< modify to change the Link Width B-AHCI mode - SataAhci7804, ///< AHCI mode as 7804 ID (AMD driver) - SataIde2Ahci7804 ///< IDE->AHCI mode as 7804 ID (AMD driver) -} SATA_CLASS; - -/// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG -typedef enum { - PortA4 = 0, ///< 4:0:0:0 - PortA2B2 = 2, ///< 2:2:0:0 - PortA2B1C1 = 3, ///< 2:1:1:0 - PortA1B1C1D1 = 4 ///< 1:1:1:1 -} GPP_LINKMODE; - -/// Configuration values for FchPowerFail -typedef enum { - AlwaysOff = 0, ///< Always power off after power resumes - AlwaysOn = 1, ///< Always power on after power resumes - UsePrevious = 3, ///< Resume to same setting when power fails -} POWER_FAIL; - - -/// Configuration values for SATA Link Speed -typedef enum { - Gen1 = 1, ///< SATA port GEN1 speed - Gen2 = 2, ///< SATA port GEN2 speed - Gen3 = 3, ///< SATA port GEN3 speed -} SATA_SPEED; - - -/// Configuration values for GPIO function -typedef enum { - Function0 = 0, ///< GPIO Function 1 - Function1 = 1, ///< GPIO Function 1 - Function2 = 2, ///< GPIO Function 2 - Function3 = 3, ///< GPIO Function 3 -} GPIO_FUN; - - -/// Configuration values for GPIO_CFG -typedef enum { - OwnedByEc = 1 << 0, ///< This bit can only be written by EC - OwnedByHost = 1 << 1, ///< This bit can only be written by host (BIOS) - Sticky = 1 << 2, ///< If set, [6:3] are sticky - PullUpB = 1 << 3, ///< 0: Pullup enable; 1: Pullup disabled - PullDown = 1 << 4, ///< 0: Pulldown disabled; 1: Pulldown enable - GpioOutEnB = 1 << 5, ///< 0: Output enable; 1: Output disable - GpioOut = 1 << 6, ///< Output state when GpioOutEnB is 0 - GpioIn = 1 << 7, ///< This bit is read only - current pin state -} CFG_BYTE; - -/// FCH GPIO CONTROL -typedef struct { - IN UINT8 GpioPin; ///< Gpio Pin, valid range: 0-67, 128-150, 160-228 - IN GPIO_FUN PinFunction; ///< Multi-function selection - IN CFG_BYTE CfgByte; ///< GPIO Register value -} GPIO_CONTROL; - -/// -/// FCH SCI MAP CONTROL -/// -typedef struct { - IN UINT8 InputPin; ///< Input Pin, valid range 0-63 - IN UINT8 GpeMap; ///< Gpe Map, valid range 0-31 -} SCI_MAP_CONTROL; - -/// -/// FCH SATA PHY CONTROL -/// -typedef struct { - IN BOOLEAN CommonPhy; ///< Common PHY or not - ///< @li FALSE - Only applied to specified port - ///< @li TRUE - Apply to all SATA ports - IN SATA_SPEED Gen; ///< SATA speed - IN UINT8 Port; ///< Port number, valid range: 0-7 - IN UINT32 PhyData; ///< SATA PHY data, valid range: 0-0xFFFFFFFF -} SATA_PHY_CONTROL; - -/// -/// FCH Component Data Structure in InitReset stage -/// -typedef struct { - IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI - ///< @li FALSE - Disable Gen2 - ///< @li TRUE - Enable Gen2 - - IN BOOLEAN SataEnable; ///< SATA controller function - ///< @li FALSE - SATA controller is disabled - ///< @li TRUE - SATA controller is enabled - - IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled - ///< @li FALSE - IDE controller is disabled - ///< @li TRUE - IDE controller is enabled - - IN BOOLEAN GppEnable; ///< Master switch of GPP function - ///< @li FALSE - GPP disabled - ///< @li TRUE - GPP enabled - - IN BOOLEAN Xhci0Enable; ///< XHCI0 controller function - ///< @li FALSE - XHCI0 controller disabled - ///< @li TRUE - XHCI0 controller enabled - - IN BOOLEAN Xhci1Enable; ///< XHCI1 controller function - ///< @li FALSE - XHCI1 controller disabled - ///< @li TRUE - XHCI1 controller enabled -} FCH_RESET_INTERFACE; - - -/// -/// FCH Component Data Structure from InitEnv stage -/// -typedef struct { - IN SD_MODE SdConfig; ///< Secure Digital (SD) controller mode - IN HDA_CONFIG AzaliaController; ///< Azalia HD Audio Controller - - IN IR_CONFIG IrConfig; ///< Infrared (IR) Configuration - IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI - ///< @li FALSE - Disable Gen2 - ///< @li TRUE - Enable Gen2 - - IN SATA_CLASS SataClass; ///< SATA controller mode - IN BOOLEAN SataEnable; ///< SATA controller function - ///< @li FALSE - SATA controller is disabled - ///< @li TRUE - SATA controller is enabled - - IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled - ///< @li FALSE - IDE controller is disabled - ///< @li TRUE - IDE controller is enabled - - IN BOOLEAN SataIdeMode; ///< Native mode of SATA IDE controller - ///< @li FALSE - Legacy IDE mode - ///< @li TRUE - Native IDE mode - - IN BOOLEAN Ohci1Enable; ///< OHCI controller #1 Function - ///< @li FALSE - OHCI1 is disabled - ///< @li TRUE - OHCI1 is enabled - - IN BOOLEAN Ohci2Enable; ///< OHCI controller #2 Function - ///< @li FALSE - OHCI2 is disabled - ///< @li TRUE - OHCI2 is enabled - - IN BOOLEAN Ohci3Enable; ///< OHCI controller #3 Function - ///< @li FALSE - OHCI3 is disabled - ///< @li TRUE - OHCI3 is enabled - - IN BOOLEAN Ohci4Enable; ///< OHCI controller #4 Function - ///< @li FALSE - OHCI4 is disabled - ///< @li TRUE - OHCI4 is enabled - - IN BOOLEAN XhciSwitch; ///< XHCI controller Function - ///< @li FALSE - XHCI is disabled - ///< @li TRUE - XHCI is enabled - - IN BOOLEAN GppEnable; ///< Master switch of GPP function - ///< @li FALSE - GPP disabled - ///< @li TRUE - GPP enabled - - IN POWER_FAIL FchPowerFail; ///< FCH power failure option -} FCH_INTERFACE; - - -/*---------------------------------------------------------------------------- - * CPU Feature related info - *---------------------------------------------------------------------------- - */ - -/// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE -typedef enum { - C1eModeDisabled = 0, ///< Disabled - C1eModeAuto = 1, ///< Auto mode enables the best C1e method for the - ///< currently installed processor - C1eModeHardware = 2, ///< Hardware method - C1eModeMsgBased = 3, ///< Message-based method - C1eModeSoftwareDeprecated = 4, ///< Deprecated software SMI method. - ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for - ///< example host BIOS SMM Handler implementation - C1eModeHardwareSoftwareDeprecated = 5, ///< Hardware or deprecated software SMI method - MaxC1eMode = 6 ///< Not a valid value, used for verifying input -} PLATFORM_C1E_MODES; - -/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE -typedef enum { - CStateModeDisabled = 0, ///< Disabled - CStateModeC6 = 1, ///< C6 State - MaxCStateMode = 2 ///< Not a valid value, used for verifying input -} PLATFORM_CSTATE_MODES; - -/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE -typedef enum { - CpbModeAuto = 0, ///< Auto - CpbModeDisabled = 1, ///< Disabled - MaxCpbMode = 2 ///< Not a valid value, used for verifying input -} PLATFORM_CPB_MODES; - -/// Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE -typedef enum { - LOW_POWER_PSTATE_FOR_PROCHOT_AUTO = 0, ///< Auto - LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE = 1, ///< Disabled - MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE = 2 ///< Not a valid value, used for verifying input -} PLATFORM_LOW_POWER_PSTATE_MODES; - -/*---------------------------------------------------------------------------- - * GNB PCIe configuration info - *---------------------------------------------------------------------------- - */ - -// Event definitions - - -#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000 // User configuration invalid -#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001 // Requested lane allocation for PCIe port can not be supported -#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002 // Requested incorrect PCIe port device address -#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003 // Incorrect parameter in DDI link configuration -#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004 // Invalid with for PCIe port or DDI link -#define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005 // Lane double subscribe lanes -#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006 // Requested lane allocation for DDI link(s) can not be supported -#define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000 // PCIe Link training fail -#define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000 // Broken lane workaround applied to recover link training -#define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000 // Scale back to GEN1 to recover link training - - -#define DESCRIPTOR_TERMINATE_LIST 0x80000000ull -#define DESCRIPTOR_IGNORE 0x40000000ull - -/// PCIe port misc extended controls -typedef struct { - IN UINT8 LinkComplianceMode :1; ///< Force port into compliance mode (device will not be trained, port output compliance pattern) - IN UINT8 LinkSafeMode :2; /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability) - * @li @b 0 - port can advertize muximum supported capability - * @li @b 1 - port limit advertized capability and speed to PCIe Gen1 - */ - IN UINT8 SbLink :1; /**< PCIe link type - * @li @b 0 - General purpose port - * @li @b 1 - Port connected to SB - */ -} PCIe_PORT_MISC_CONTROL; - - -/// PCIe port configuration data -typedef struct { - IN UINT8 PortPresent; ///< Enable PCIe port for initialization. - IN UINT8 ChannelType; /**< Channel type. - * @li @b 0 - "lowLoss", - * @li @b 1 - "highLoss", - * @li @b 2 - "mob0db", - * @li @b 3 - "mob3db", - * @li @b 4 - "extnd6db" - * @li @b 5 - "extnd8db" - */ - IN UINT8 DeviceNumber; /**< PCI Device number for port. - * @li @b 0 - Native port device number - * @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12", @ref F14ONLaneConfigurations "Family 0x14(ON)") - */ - IN UINT8 FunctionNumber; ///< Reserved for future use - IN UINT8 LinkSpeedCapability; /**< PCIe link speed/ - * @li @b 0 - Maximum supported by silicon - * @li @b 1 - Gen1 - * @li @b 2 - Gen2 - * @li @b 3 - Gen3 - */ - IN UINT8 LinkAspm; /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM) - * @li @b 0 - Disabled - * @li @b 1 - L0s only - * @li @b 2 - L1 only - * @li @b 3 - L0s and L1 - */ - IN UINT8 LinkHotplug; /**< Hotplug control. - * @li @b 0 - Disabled - * @li @b 1 - Basic - * @li @b 2 - Server - * @li @b 3 - Enhanced - */ - IN UINT8 ResetId; /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO - * identification which control reset for given port. - * Each port with unique GPIO should have unique ResetId assigned. - * All ports use same GPIO to control reset should have same ResetId assigned. - * see AgesaPcieSlotResetContol. - */ - IN PCIe_PORT_MISC_CONTROL MiscControls; ///< Misc extended controls -} PCIe_PORT_DATA; - -/// DDI channel lane mapping -typedef struct { ///< Structure that discribe lane mapping - IN UINT8 Lane0 :2; /**< Lane 0 mapping - * @li @b 0 - Map to lane 0 - * @li @b 1 - Map to lane 1 - * @li @b 2 - Map to lane 2 - * @li @b 2 - Map to lane 3 - */ - IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping") - IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping") - IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping") -} CHANNEL_MAPPING; ///< Lane mapping - -/// Common Channel Mapping -typedef union { - IN UINT8 ChannelMappingValue; ///< Raw lane mapping - IN CHANNEL_MAPPING ChannelMapping; ///< Channel mapping -} CONN_CHANNEL_MAPPING; - -/// DDI Configuration data -typedef struct { - IN UINT8 ConnectorType; /**< Display Connector Type - * @li @b 0 - DP - * @li @b 1 - eDP - * @li @b 2 - Single Link DVI-D - * @li @b 3 - Dual Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description") - * @li @b 4 - HDMI - * @li @b 5 - Travis DP-to-VGA - * @li @b 6 - Travis DP-to-LVDS - * @li @b 7 - Hudson-2 NutMeg DP-to-VGA - * @li @b 8 - Single Link DVI-I - * @li @b 9 - Native CRT (Family 0x14) - * @li @b 10 - Native LVDS (Family 0x14) - * @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS - * The auto detection method only support panel with EDID. - */ - IN UINT8 AuxIndex; /**< Indicates which AUX or DDC Line is used - * @li @b 0 - AUX1 - * @li @b 1 - AUX2 - * @li @b 2 - AUX3 - * @li @b 3 - AUX4 - * @li @b 4 - AUX5 - * @li @b 5 - AUX6 - */ - IN UINT8 HdpIndex; /**< Indicates which HDP pin is used - * @li @b 0 - HDP1 - * @li @b 1 - HDP2 - * @li @b 2 - HDP3 - * @li @b 3 - HDP4 - * @li @b 4 - HDP5 - * @li @b 5 - HDP6 - */ - IN CONN_CHANNEL_MAPPING Mapping[2]; /**< Set specific mapping of lanes to connector pins - * @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane - * @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link) - * if Mapping[x] set to 0 than default mapping assumed - */ - IN UINT8 LanePnInversionMask; /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port. - * @li 0 - Do not invert (default) - * @li 1 - Invert P and N on this lane - */ -} PCIe_DDI_DATA; - -/// Engine Configuration -typedef struct { - IN UINT8 EngineType; /**< Engine type - * @li @b 0 - Ignore engine configuration - * @li @b 1 - PCIe port - * @li @b 2 - DDI - */ - IN UINT16 StartLane; /**< Start Lane ID (in reversed configuration StartLane > EndLane) - * See lane description for @ref F12PcieLaneDescription "Family 0x12" - * @ref F14ONPcieLaneDescription "Family 0x14(ON)". - * See lane configurations for @ref F12LaneConfigurations "Family 0x12" - * @ref F14ONLaneConfigurations "Family 0x14(ON)". - */ - IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane) - * See lane description for @ref F12PcieLaneDescription "Family 0x12", - * @ref F14ONPcieLaneDescription "Family 0x14(ON)". - * See lane configurations for @ref F12LaneConfigurations "Family 0x12" - * @ref F14ONLaneConfigurations "Family 0x14(ON)". - */ - -} PCIe_ENGINE_DATA; - -/// PCIe port descriptor -typedef struct { - IN UINT32 Flags; /**< Descriptor flags - * @li @b Bit31 - last descriptor in complex - */ - IN PCIe_ENGINE_DATA EngineData; ///< Engine data - IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info -} PCIe_PORT_DESCRIPTOR; - -/// DDI descriptor -typedef struct { - IN UINT32 Flags; /**< Descriptor flags - * @li @b Bit31 - last descriptor in complex - */ - IN PCIe_ENGINE_DATA EngineData; ///< Engine data - IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info -} PCIe_DDI_DESCRIPTOR; - -/// PCIe Complex descriptor -typedef struct { - IN UINT32 Flags; /**< Descriptor flags - * @li @b Bit31 - last descriptor in topology - */ - IN UINT32 SocketId; ///< Socket Id - IN PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). - IN PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). - IN VOID *Reserved; ///< Reserved for future use -} PCIe_COMPLEX_DESCRIPTOR; - -/// Action to control PCIe slot reset -typedef enum { - AssertSlotReset, ///< Assert slot reset - DeassertSlotReset ///< Deassert slot reset -} PCIE_RESET_CONTROL; - -///Slot Reset Info -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR - IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL -} PCIe_SLOT_RESET_INFO; - -/// Engine descriptor type -typedef enum { - PcieUnusedEngine = 0, ///< Unused descriptor - PciePortEngine = 1, ///< PCIe port - PcieDdiEngine = 2, ///< DDI - MaxPcieEngine ///< Max engine type for boundary check. -} PCIE_ENGINE_TYPE; - -/// PCIe link capability/speed -typedef enum { - PcieGenMaxSupported, ///< Maximum supported - PcieGen1 = 1, ///< Gen1 - PcieGen2, ///< Gen2 - MaxPcieGen ///< Max Gen for boundary check -} PCIE_LINK_SPEED_CAP; - -/// PCIe PSPP Power policy -typedef enum { - PsppDisabled, ///< PSPP disabled - PsppPerformance = 1, ///< Performance - PsppBalanceHigh, ///< Balance-High - PsppBalanceLow, ///< Balance-Low - PsppPowerSaving, ///< Power Saving - MaxPspp ///< Max Pspp for boundary check -} PCIE_PSPP_POLICY; - -/// DDI display connector type -typedef enum { - ConnectorTypeDP, ///< DP - ConnectorTypeEDP, ///< eDP - ConnectorTypeSingleLinkDVI, ///< Single Link DVI-D - ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D - ConnectorTypeHDMI, ///< HDMI - ConnectorTypeTravisDpToVga, ///< Travis DP-to-VGA - ConnectorTypeTravisDpToLvds, ///< Travis DP-to-LVDS - ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA - ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I - ConnectorTypeCrt, ///< CRT (VGA) - ConnectorTypeLvds, ///< LVDS - ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS) - MaxConnectorType ///< Not valid value, used to verify input -} PCIE_CONNECTOR_TYPE; - -/// PCIe link channel type -typedef enum { - ChannelTypeLowLoss, ///< Low Loss - ChannelTypeHighLoss, ///< High Loss - ChannelTypeMob0db, ///< Mobile 0dB - ChannelTypeMob3db, ///< Mobile 3dB - ChannelTypeExt6db, ///< Extended 6dB - ChannelTypeExt8db, ///< Extended 8dB - MaxChannelType ///< Not valid value, used to verify input -} PCIE_CHANNEL_TYPE; - -/// PCIe link ASPM -typedef enum { - AspmDisabled, ///< Disabled - AspmL0s, ///< PCIe L0s link state - AspmL1, ///< PCIe L1 link state - AspmL0sL1, ///< PCIe L0s & L1 link state - MaxAspm ///< Not valid value, used to verify input -} PCIE_ASPM_TYPE; - -/// PCIe link hotplug support -typedef enum { - HotplugDisabled, ///< Hotplug disable - HotplugBasic, ///< Basic Hotplug - HotplugServer, ///< Server Hotplug - HotplugEnhanced, ///< Enhanced - HotplugInboard, ///< Inboard - MaxHotplug ///< Not valid value, used to verify input -} PCIE_HOTPLUG_TYPE; - -/// PCIe link initialization -typedef enum { - PortDisabled, ///< Disable - PortEnabled ///< Enable -} PCIE_PORT_ENABLE; - -/// DDI Aux channel -typedef enum { - Aux1, ///< Aux1 - Aux2, ///< Aux2 - Aux3, ///< Aux3 - Aux4, ///< Aux4 - Aux5, ///< Aux5 - Aux6, ///< Aux6 - MaxAux ///< Not valid value, used to verify input -} PCIE_AUX_TYPE; - -/// DDI Hdp Index -typedef enum { - Hdp1, ///< Hdp1 - Hdp2, ///< Hdp2 - Hdp3, ///< Hdp3 - Hdp4, ///< Hdp4 - Hdp5, ///< Hdp5 - Hdp6, ///< Hdp6 - MaxHdp ///< Not valid value, used to verify input -} PCIE_HDP_TYPE; - -// Macro for statically initialization of various structures -#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane} -#define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \ -{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap} } -#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ -{mConnectorType, mAuxIndex, mHpdIndex, {0, 0}, 0} -#define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \ -{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion} - -///IOMMU requestor ID -typedef struct { - IN UINT16 Bus :8; ///< Bus - IN UINT16 Device :5; ///< Device - IN UINT16 Function :3; ///< Function -} IOMMU_REQUESTOR_ID; - -/// IVMD exclusion range descriptor -typedef struct { - IN UINT32 Flags; /**< Descriptor flags - * @li @b Flags[31] - Terminate descriptor array. - * @li @b Flags[30] - Ignore descriptor. - */ - IN IOMMU_REQUESTOR_ID RequestorIdStart; ///< Requestor ID start - IN IOMMU_REQUESTOR_ID RequestorIdEnd; ///< Requestor ID end (use same as start for single ID) - IN UINT64 RangeBaseAddress; ///< Phisical base address of exclusion range - IN UINT64 RangeLength; ///< Length of exclusion range in bytes -} IOMMU_EXCLUSION_RANGE_DESCRIPTOR; - -/*---------------------------------------------------------------------------- - * GNB configuration info - *---------------------------------------------------------------------------- - */ - -/// LVDS Misc Control Field -typedef struct { - IN UINT8 FpdiMode:1; ///< This item configures LVDS 888bit panel mode - ///< @li FALSE = LVDS 888 panel in LDI mode - ///< @li TRUE = LVDS 888 panel in FPDI mode - ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE} - IN UINT8 DlChSwap:1; ///< This item configures LVDS panel lower and upper link mapping - ///< @li FALSE = Lower link and upper link not swap - ///< @li TRUE = Lower link and upper link are swapped - ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP} - IN UINT8 VsyncActiveLow:1; ///< This item configures polarity of frame pulse encoded in lvds data stream - ///< @li FALSE = Active high Frame Pulse/Vsync - ///< @li TRUE = Active low Frame Pulse/Vsync - ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW} - IN UINT8 HsyncActiveLow:1; ///< This item configures polarity of line pulse encoded in lvds data - ///< @li FALSE = Active high Line Pulse - ///< @li TRUE = Active low Line Pulse / Hsync - ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW} - IN UINT8 BLONActiveLow:1; ///< This item configures polarity of signal sent to digital BLON output pin - ///< @li FALSE = Not inverted(active high) - ///< @li TRUE = Inverted (active low) - ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW} - IN UINT8 Reserved:3; ///< Reserved -} LVDS_MISC_CONTROL_FIELD; - -/// LVDS Misc Control -typedef union _LVDS_MISC_CONTROL { - IN LVDS_MISC_CONTROL_FIELD Field; ///< LVDS_MISC_CONTROL_FIELD - IN UINT8 Value; ///< LVDS Misc Control Value -} LVDS_MISC_CONTROL; - -/// Configuration settings for GNB. -typedef struct { - IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID. - ///< @li 0 = Stereo 3D is disabled (default). - ///< @li 1 = Use processor pin HPD1. - ///< @li 2 = Use processor pin HPD2 - ///< @li 3 = Use processor pin HPD3 - ///< @li 4 = Use processor pin HPD4 - ///< @li 5 = Use processor pin HPD5 - ///< @li 6 = Use processor pin HPD6 - ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT} - IN BOOLEAN IommuSupport; ///< IOMMU support. - ///< @li FALSE = Disabled. Disable and hide IOMMU device. - ///< @li TRUE = Initialize IOMMU subsystem. Generate ACPI IVRS table. - ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT} - IN UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % - ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} - IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz - ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} - IN UINT8 LvdsPowerOnSeqDigonToDe; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE} - IN UINT8 LvdsPowerOnSeqDeToVaryBl; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL} - IN UINT8 LvdsPowerOnSeqDeToDigon; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON} - IN UINT8 LvdsPowerOnSeqVaryBlToDe; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE} - IN UINT8 LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY} - IN UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON} - IN UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing. - ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL} - IN UINT16 LvdsMaxPixelClockFreq; ///< This item configures the maximum pixel clock frequency supported. - ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ} - IN UINT32 LcdBitDepthControlValue; ///< This item configures the LCD bit depth control settings. - ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE} - IN UINT8 Lvds24bbpPanelMode; ///< This item configures the LVDS 24 BBP mode. - ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE} - IN LVDS_MISC_CONTROL LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON - IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % - ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} - IN BOOLEAN GnbRemoteDisplaySupport; ///< This item enables Wireless Display Support - ///< @li TRUE = Enable Wireless Display Support - ///< @li FALSE = Disable Wireless Display Support - ///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT} -} GNB_ENV_CONFIGURATION; - -/// GNB configuration info -typedef struct { - IN const PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST - * Example of topology definition for single socket system: - * @code - * PCIe_PORT_DESCRIPTOR PortList [] = { - * // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) - * { - * 0, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), - * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - * }, - * // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) - * { - * 0, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), - * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - * }, - * // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - * } - * }; - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...) - * { - * 0, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - * }, - * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) - * } - * }; - * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list - * 0, //Socket ID - * &PortList[0], - * &DdiList[0], - * } - * @endcode - */ - IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy) - * @li @b 0 - Disabled - * @li @b 1 - Performance - * @li @b 2 - Balance-High - * @li @b 3 - Balance-Low - * @li @b 4 - Power Saving - */ - -} GNB_CONFIGURATION; -// -// MEMORY-SPECIFIC DATA STRUCTURES -// -// -// -// -// AGESA MAXIMIUM VALUES -// -// These Max values are used to define array sizes and associated loop -// counts in the code. They reflect the maximum values that AGESA -// currently supports and does not necessarily reflect the hardware -// capabilities of configuration. -// - -#define MAX_SOCKETS_SUPPORTED 8 ///< Max number of sockets in system -#define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets -#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform) -#define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT. - ///< Eg: UINT16 *RcvEnDlys; - ///< UINT8 *WrDqsDlys; - ///< UINT8 *RdDqsDlys; - ///< UINT8 *WrDatDlys; - ///< UINT8 *RdDqsMinDlys; - ///< UINT8 *RdDqsMaxDlys; - ///< UINT8 *WrDatMinDlys; - ///< UINT8 *WrDatMaxDlys; -#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables - -#define MAX_PLATFORM_TYPES 16 ///< Platform types per system - -#define MCT_TRNG_KEEPOUT_START 0x00004000 ///< base [39:8] -#define MCT_TRNG_KEEPOUT_END 0x00007FFF ///< base [39:8] - -#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000 ///< Uma Region is interleaved -#define UMA_ATTRIBUTE_ON_DCT0 0x40000000 ///< UMA resides on memory that belongs to DCT0 -#define UMA_ATTRIBUTE_ON_DCT1 0x20000000 ///< UMA resides on memory that belongs to DCT1 - -typedef UINT8 PSO_TABLE; ///< Platform Configuration Table - -// AGESA DEFINITIONS -// -// Many of these are derived from the platform and hardware specific definitions - -/// EccSymbolSize override value -#define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value -#define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4 -#define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8 -/// CPU Package Type -#define PT_L1 0 ///< L1 Package type -#define PT_M2 1 ///< AM Package type -#define PT_S1 2 ///< S1 Package type - -/// Structures use to pass system Logical CPU-ID -typedef struct { - IN OUT UINT64 Family; ///< Indicates logical ID Family - IN OUT UINT64 Revision; ///< Indicates logical ID Family -} CPU_LOGICAL_ID; - -/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE -typedef enum { - AMD_PLATFORM_SERVER = 0x8000, ///< Server - AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop - AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile -} AMD_PLATFORM_TYPE; - -/// Dram technology type -typedef enum { - DDR2_TECHNOLOGY, ///< DDR2 technology - DDR3_TECHNOLOGY ///< DDR3 technology -} TECHNOLOGY_TYPE; - -/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT -typedef enum { - DDR400_FREQUENCY = 200, ///< DDR 400 - DDR533_FREQUENCY = 266, ///< DDR 533 - DDR667_FREQUENCY = 333, ///< DDR 667 - DDR800_FREQUENCY = 400, ///< DDR 800 - DDR1066_FREQUENCY = 533, ///< DDR 1066 - DDR1333_FREQUENCY = 667, ///< DDR 1333 - DDR1600_FREQUENCY = 800, ///< DDR 1600 - DDR1866_FREQUENCY = 933, ///< DDR 1866 - DDR2100_FREQUENCY = 1050, ///< DDR 2100 - DDR2133_FREQUENCY = 1066, ///< DDR 2133 - DDR2400_FREQUENCY = 1200, ///< DDR 2400 - UNSUPPORTED_DDR_FREQUENCY ///< Highest limit of DDR frequency -} MEMORY_BUS_SPEED; - -/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE -typedef enum { - QUADRANK_REGISTERED, ///< Quadrank registered DIMM - QUADRANK_UNBUFFERED ///< Quadrank unbuffered DIMM -} QUANDRANK_TYPE; - -/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT -typedef enum { - TIMING_MODE_AUTO, ///< Use best rate possible - TIMING_MODE_LIMITED, ///< Set user top limit - TIMING_MODE_SPECIFIC ///< Set user specified speed -} USER_MEMORY_TIMING_MODE; - -/// Build Configuration values for BLDCFG_POWER_DOWN_MODE -typedef enum { - POWER_DOWN_BY_CHANNEL, ///< Channel power down mode - POWER_DOWN_BY_CHIP_SELECT, ///< Chip select power down mode - POWER_DOWN_MODE_AUTO ///< AGESA to select power down mode -} POWER_DOWN_MODE; - -/// Low voltage support -typedef enum { - VOLT_INITIAL, ///< Initial value for VDDIO - VOLT1_5, ///< 1.5 Volt - VOLT1_35, ///< 1.35 Volt - VOLT1_25, ///< 1.25 Volt - VOLT_UNSUPPORTED = 0xFF ///< No common voltage found -} DIMM_VOLTAGE; - -/// UMA Mode -typedef enum { - UMA_NONE = 0, ///< UMA None - UMA_SPECIFIED = 1, ///< UMA Specified - UMA_AUTO = 2 ///< UMA Auto -} UMA_MODE; - -/// Force Training Mode -typedef enum { - FORCE_TRAIN_1D = 0, ///< 1D Training only - FORCE_TRAIN___ = 1, ///< - FORCE_TRAIN_AUTO = 2 ///< Auto -} FORCE_TRAIN_MODE; - -/// The possible DRAM prefetch mode settings. -typedef enum { - DRAM_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. - DISABLE_DRAM_PREFETCH_FOR_IO, ///< Disable DRAM prefetching for I/O requests only. - DISABLE_DRAM_PREFETCH_FOR_CPU, ///< Disable DRAM prefetching for requests from processor cores only. - DISABLE_DRAM_PREFETCHER, ///< Disable DRAM prefetching. - MAX_DRAM_FREFETCH_MODE ///< Not a DRAM prefetch mode, use for limit checking. -} DRAM_PREFETCH_MODE; - -/// Build Configuration values for BLDCFG_UMA_ALIGNMENT -typedef enum { - NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned - UMA_4MB_ALIGNED = 0x00FFFFC0, ///< UMA 4MB aligned - UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned - UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned - UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned -} UMA_ALIGNMENT; - -/// -/// Global MCT Configuration Status Word (GStatus) -/// -typedef enum { - GsbMTRRshort, ///< Ran out of MTRRs while mapping memory - GsbAllECCDimms, ///< All banks of all Nodes are ECC capable - GsbDramECCDis, ///< Dram ECC requested but not enabled. - GsbSoftHole, ///< A Node Base gap was created - GsbHWHole, ///< A HW dram remap was created - GsbNodeIntlv, ///< Node Memory interleaving was enabled - GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping - GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset - - GsbEOL ///< End of list -} GLOBAL_STATUS_FIELD; - -/// -/// Local Error Status (DIE_STRUCT.ErrStatus[31:0]) -/// -typedef enum { - EsbNoDimms, ///< No DIMMs - EsbSpdChkSum, ///< SPD Checksum fail - EsbDimmMismatchM, ///< dimm module type(buffer) mismatch - EsbDimmMismatchT, ///< dimm CL/T mismatch - EsbDimmMismatchO, ///< dimm organization mismatch (128-bit) - EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info - EsbNoCycTime, ///< SPD missing byte 23 or 25 - EsbBkIntDis, ///< Bank interleave requested but not enabled - EsbDramECCDis, ///< Dram ECC requested but not enabled - EsbSpareDis, ///< Online spare requested but not enabled - EsbMinimumMode, ///< Running in Minimum Mode - EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found - EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range) - EsbNoDqsPos, ///< No DQS-DQ passing positions - EsbSmallDqs, ///< DQS-DQ passing window too small - EsbDCBKScrubDis, ///< DCache scrub requested but not enabled - - EsbEMPNotSupported, ///< Processor is not capable for EMP. - EsbEMPConflict, ///< EMP requested but cannot be enabled since - ///< channel interleaving, bank interleaving, or bank swizzle is enabled. - EsbEMPDis, ///< EMP requested but cannot be enabled since - ///< memory size of each DCT is not a power of two. - - EsbEOL ///< End of list -} ERROR_STATUS_FIELD; - -/// -/// Local Configuration Status (DIE_STRUCT.Status[31:0]) -/// -typedef enum { - SbRegistered, ///< All DIMMs are Registered - SbEccDimms, ///< All banks ECC capable - SbParDimms, ///< All banks Addr/CMD Parity capable - SbDiagClks, ///< Jedec ALL slots clock enable diag mode - Sb128bitmode, ///< DCT in 128-bit mode operation - Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode. - Sb2TMode, ///< 2T CMD timing mode is enabled. - SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap. - SbHWHole, ///< Memory Hole created on this Node using HW remapping. - SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag - SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz - SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound. - SbExtConfig, ///< Indicate the default setting for extended PCI configuration support - SbLrdimms, ///< All DIMMs are LRDIMMs - - SbEOL ///< End of list -} LOCAL_STATUS_FIELD; - - -///< CPU MSR Register definitions ------------------------------------------ -#define SYS_CFG 0xC0010010 -#define TOP_MEM 0xC001001Aul -#define TOP_MEM2 0xC001001Dul -#define HWCR 0xC0010015 -#define NB_CFG 0xC001001F - -#define FS_BASE 0xC0000100 -#define IORR0_BASE 0xC0010016 -#define IORR0_MASK 0xC0010017 -#define BU_CFG 0xC0011023 -#define BU_CFG2 0xC001102A -#define COFVID_STAT 0xC0010071 -#define TSC 0x10 - -//----------------------------------------------------------------------------- -/// -/// SPD Data for each DIMM. -/// -typedef struct _SPD_DEF_STRUCT { - IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid - IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM -} SPD_DEF_STRUCT; - -/// -/// Channel Definition Structure. -/// This data structure defines entries that are specific to the channel initialization -/// -typedef struct _CH_DEF_STRUCT { - OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D) - OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel - OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. - ///< DIMM# Select Signal - ///< 0 MA0_CS_L[0, 1] - ///< 1 MB0_CS_L[0, 1] - ///< 2 MA1_CS_L[0, 1] - ///< 3 MB1_CS_L[0, 1] - ///< 4 MA2_CS_L[0, 1] - ///< 5 MB2_CS_L[0, 1] - ///< 6 MA3_CS_L[0, 1] - ///< 7 MB3_CS_L[0, 1] - - OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel. - OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel. - OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor) - OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to - ///< SPD Data for each Dimm. (Setup by Tech Block Constructor) - OUT UINT8 ChDimmValid; ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved. - ///< - OUT UINT8 RegDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved. - OUT UINT8 LrDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved. - OUT UINT8 SODimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved. - OUT UINT8 Loads; ///< Number of devices loading bus - OUT UINT8 Dimms; ///< Number of DIMMs loading Channel - OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA - OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) - ///< FALSE = 1T - ///< TRUE = 2T - ///< The following pointers will be pointed to dynamically allocated buffers. - ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below. - ///< Example: If DIMM and Byte based training, then - ///< XX is a value in Hex - ///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE - ///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX - ///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX - OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays - OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3) - OUT UINT8 *RdDqsDlys; ///< Read Dqs delays - OUT UINT8 *WrDatDlys; ///< Write Data delays - OUT UINT8 *RdDqs__Dlys; ///< Read DQS data - OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS - OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS - OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data - OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data - OUT UINT16 *RcvEnDlysMemPs1; ///< DQS Receiver Enable Delays for Mem Pstate 1 - OUT UINT8 *WrDqsDlysMemPs1; ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1 - OUT UINT8 *RdDqsDlysMemPs1; ///< Read Dqs delays for Memory Pstate 1 - OUT UINT8 *WrDatDlysMemPs1; ///< Write Data delays for Memory Pstate 1 - OUT UINT8 *RdDqs__DlysMemPs1; ///< Read DQS data for Memory Pstate 1 - OUT UINT8 *RdDqsMinDlysMemPs1; ///< Minimum Window for Read DQS for Memory Pstate 1 - OUT UINT8 *RdDqsMaxDlysMemPs1; ///< Maximum Window for Read DQS for Memory Pstate 1 - OUT UINT8 *WrDatMinDlysMemPs1; ///< Minimum Window for Write data for Memory Pstate 1 - OUT UINT8 *WrDatMaxDlysMemPs1; ///< Maximum Window for Write data for Memory Pstate 1 - OUT UINT8 RowCount; ///< Number of rows of the allocated buffer. - OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer. - OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits - OUT UINT8 *FailingBitMaskMemPs1; ///< Table of masks to Track Failing bits for Memory Pstate 1 - OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h) - OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) - OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h) - OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h) - OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h) - OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183) - OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8]) - OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like... - OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale - OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern - OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern - OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7) - OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write) - OUT UINT8 Pattern; ///< Current pattern - OUT UINT8 DqsDelay; ///< Current DQS delay value - OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. - OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. - OUT UINT16 DctMaxRdLat[4]; ///< Max Read Latency (ns) for the DCT - ///< DctMaxRdLat [i] is for NBPstate i - OUT UINT8 DIMMValidCh; ///< DIMM# in CH - OUT UINT8 MaxCh; ///< Max number of CH in system - OUT UINT8 Dct; ///< Dct pointer - OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value - OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low - - OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB - OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly - OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K) - OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag - OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag - OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training - - OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory - OUT UINT32 NodeSysBase; ///< for channel interleave usage - OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected - OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM - OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM - OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM - OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM - OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM - - OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present - OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved. - OUT UINT8 DimmSpdCse; ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved. - OUT UINT8 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved. - OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006 - OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June) - OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present. - OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present? - OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present - OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present - OUT UINT8 Dimmx4Present; ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved. - OUT UINT8 Dimmx8Present; ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved. - OUT UINT8 Dimmx16Present; ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved. - OUT UINT8 LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs - OUT UINT8 LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration - OUT UINT8 LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm. - OUT UINT8 DimmNibbleAccess; ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved. - OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes - ///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will - ///< base on this array to disable unused MemClk to save power. - ///< - ///< The array must have 8 entries. Each entry, which associates with - ///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to. - ///< Example: - ///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package - ///< is like below: - ///< Bit AM3/S1g3 pin name - ///< 0 M[B,A]_CLK_H/L[0] - ///< 1 M[B,A]_CLK_H/L[1] - ///< 2 M[B,A]_CLK_H/L[2] - ///< 3 M[B,A]_CLK_H/L[3] - ///< 4 M[B,A]_CLK_H/L[4] - ///< 5 M[B,A]_CLK_H/L[5] - ///< 6 M[B,A]_CLK_H/L[6] - ///< 7 M[B,A]_CLK_H/L[7] - ///< And platform has the following routing: - ///< CS0 M[B,A]_CLK_H/L[4] - ///< CS1 M[B,A]_CLK_H/L[2] - ///< CS2 M[B,A]_CLK_H/L[3] - ///< CS3 M[B,A]_CLK_H/L[5] - ///< Then MemClkDisMap should be pointed to the following array: - ///< CLK_2 CLK_3 CLK_4 CLK_5 - ///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00 - ///< Each entry of the array is the bitmask of 8 chip selects. - - OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes - ///< the routing of CKE pins to the DIMMs' ranks. - ///< The array must have 2 entries. Each entry, which associates with - ///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to. - ///< AGESA will base on this array to disable unused CKE pins to save power. - - OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes - ///< the routing of ODT pins to the DIMMs' ranks. - ///< The array must have 4 entries. Each entry, which associates with - ///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to. - ///< AGESA will base on this array to disable unused ODT pins to save power. - - OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes - ///< the routing of chip select pins to the DIMMs' ranks. - ///< The array must have 8 entries. Each entry is a bitmap of 8 CS. - ///< AGESA will base on this array to disable unused Chip select pins to save power. - - OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel. - - OUT UINT8 MaxVref; ///< Maximum Vref Value for channel - - OUT UINT8 Reserved[100]; ///< Reserved -} CH_DEF_STRUCT; - -/// -/// DCT Channel Timing Parameters. -/// This data structure sets timings that are specific to the channel. -/// -typedef struct _CH_TIMING_STRUCT { - OUT UINT16 DctDimmValid; ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved. - OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved. - OUT UINT16 DimmSpdCse; ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved. - OUT UINT16 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved. - OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present - OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled - OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled - OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training - OUT UINT16 DIMM1KPage; ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved - OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present? - OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved - OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved - OUT UINT16 Dimmx4Present; ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved - OUT UINT16 Dimmx8Present; ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved - OUT UINT16 Dimmx16Present; ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved - - OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs - OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs - OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs - OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs - OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs - OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs - OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs - OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs - OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs - OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz - OUT UINT16 Speed; ///< DRAM bus speed in MHz - ///< 400 (MHz) - ///< 533 (MHz) - ///< 667 (MHz) - ///< 800 (MHz) - ///< and so on... - OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks) - OUT UINT8 Trcd; ///< DCT Trcd (busclocks) - OUT UINT8 Trp; ///< DCT Trp (busclocks) - OUT UINT8 Trtp; ///< DCT Trtp (busclocks) - OUT UINT8 Tras; ///< DCT Tras (busclocks) - OUT UINT8 Trc; ///< DCT Trc (busclocks) - OUT UINT8 Twr; ///< DCT Twr (busclocks) - OUT UINT8 Trrd; ///< DCT Trrd (busclocks) - OUT UINT8 Twtr; ///< DCT Twtr (busclocks) - OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks) - OUT UINT8 Trfc0; ///< DCT Logical DIMM0 Trfc - ///< 0 = 75ns (for 256Mb devs) - ///< 1 = 105ns (for 512Mb devs) - ///< 2 = 127.5ns (for 1Gb devs) - ///< 3 = 195ns (for 2Gb devs) - ///< 4 = 327.5ns (for 4Gb devs) - OUT UINT8 Trfc1; ///< DCT Logical DIMM1 Trfc (see Trfc0 for format) - OUT UINT8 Trfc2; ///< DCT Logical DIMM2 Trfc (see Trfc0 for format) - OUT UINT8 Trfc3; ///< DCT Logical DIMM3 Trfc (see Trfc0 for format) - OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT. - ///< - OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) - ///< FALSE = 1T - ///< TRUE = 2T - OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks) - OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks) - OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks) - OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks) - OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks) - OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks) - OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks) - OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks) - OUT UINT16 MaxRdLat; ///< Max Read Latency - OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed - OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed -} CH_TIMING_STRUCT; - -/// -/// Data for each DCT. -/// This data structure defines data used to configure each DRAM controller. -/// -typedef struct _DCT_STRUCT { - OUT UINT8 Dct; ///< Current Dct - OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure - OUT CH_TIMING_STRUCT *TimingsMemPs1; ///< Pointed to channel timing structure for memory Pstate 1 - OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures - OUT UINT8 ChannelCount; ///< Number of channel per this DCT - OUT BOOLEAN BkIntDis; ///< Bank interleave requested but not enabled on current DCT -} DCT_STRUCT; - - -/// -/// Data Structure defining each Die. -/// This data structure contains information that is used to configure each Die. -/// -typedef struct _DIE_STRUCT { - - /// Advanced: - - OUT UINT8 NodeId; ///< Node ID of current controller - OUT UINT8 SocketId; ///< Socket ID of this Die - OUT UINT8 DieId; ///< ID of this die relative to the socket - OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller. - OUT AGESA_STATUS ErrCode; ///< Current error condition of Node - ///< 0x0 = AGESA_SUCCESS - ///< 0x1 = AGESA_UNSUPPORTED - ///< 0x2 = AGESA_BOUNDS_CHK - ///< 0x3 = AGESA_ALERT - ///< 0x4 = AGESA_WARNING - ///< 0x5 = AGESA_ERROR - ///< 0x6 = AGESA_CRITICAL - ///< 0x7 = AGESA_FATAL - ///< - OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field - ///< - OUT BOOLEAN Status[SbEOL]; ///< Status bit Field - ///< - OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node. - ///< - OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node. - ///< - OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node - ///< - OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node. - ///< - OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. - ///< DIMM# Select Signal - ///< 0 MA0_CS_L[0, 1] - ///< 1 MB0_CS_L[0, 1] - ///< 2 MA1_CS_L[0, 1] - ///< 3 MB1_CS_L[0, 1] - ///< 4 MA2_CS_L[0, 1] - ///< 5 MB2_CS_L[0, 1] - ///< 6 MA3_CS_L[0, 1] - ///< 7 MB3_CS_L[0, 1] - ///< - OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured - OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM - OUT UINT32 LrDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM - OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable. - OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable. - ///< - OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training - OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects - ///< 0 in any bit field indicates Channel 0 - ///< 1 in any bit field indicates Channel 1 - OUT UINT8 Dct; ///< Need to be removed - ///< DCT pointer - OUT BOOLEAN GangedMode; ///< Ganged mode - ///< 0 = disabled - ///< 1 = enabled - OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node - ///< - OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. - ///< - OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. - ///< - OUT UINT8 MLoad; ///< Need to be removed - ///< Number of devices loading MAA bus - ///< - OUT UINT8 MaxAsyncLat; ///< Legacy wrapper - ///< - OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper - ///< - OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0 - ///< - OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay - - OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs - OUT UINT8 DctCount; ///< Number of DCTs per this Die - OUT UINT8 Reserved[16]; ///< Reserved -} DIE_STRUCT; - -/********************************************************************** - * S3 Support structure - **********************************************************************/ -/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure -typedef struct { - OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM - OUT UINT16 Version; ///< S3 Params version number - IN OUT UINT32 Flags; ///< Indicates operation - IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data - IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region - IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data - IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region -} AMD_S3_PARAMS; - -///=============================================================================== -/// MEM_PARAMETER_STRUCT -/// This data structure is used to pass wrapper parameters to the memory configuration code -/// -typedef struct _MEM_PARAMETER_STRUCT { - - // Basic (Return parameters) - // (This section contains the outbound parameters from the memory init code) - - OUT BOOLEAN GStatus[GsbEOL]; ///< Global Status bitfield. - ///< - OUT UINT32 HoleBase; ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping. - ///< - OUT UINT32 Sub4GCacheTop; ///< If not zero, the 32-bit top of cacheable memory. - ///< - OUT UINT32 Sub1THoleBase; ///< If not zero Base[47:16] (system address) of sub 1TB dram hole. - ///< - OUT UINT32 SysLimit; ///< Limit[47:16] (system address). - ///< - OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS. - ///< - OUT UINT8 ExternalVrefValue; ///< Target reference voltage for external Vref for training - ///< - OUT struct _MEM_DATA_STRUCT *MemData; ///< Access to global memory init data. - - // Advanced (Optional parameters) - // Optional (all defaults values will be initialized by the - // 'AmdMemInitDataStructDef' based on AMD defaults. It is up - // to the IBV/OEM to change the defaults after initialization - // but prior to the main entry to the memory code): - - // Memory Map/Mgt. - - IN UINT16 BottomIo; ///< Bottom of 32-bit IO space (8-bits). - ///< NV_BOTTOM_IO[7:0]=Addr[31:24] - ///< - IN BOOLEAN MemHoleRemapping; ///< Memory Hole Remapping (1-bit). - ///< FALSE = disable - ///< TRUE = enable - ///< - IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB - ///< FALSE = disable - ///< TRUE = enable - ///< - ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB} - - - // Dram Timing - - IN USER_MEMORY_TIMING_MODE UserTimingMode; ///< User Memclock Mode. - ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT} - - IN MEMORY_BUS_SPEED MemClockValue; ///< Memory Clock Value. - ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT} - - - // Dram Configuration - - IN BOOLEAN EnableBankIntlv; ///< Dram Bank (chip-select) Interleaving (1-bit). - ///< - FALSE =disable (default) - ///< - TRUE = enable - ///< - ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING} - - IN BOOLEAN EnableNodeIntlv; ///< Node Memory Interleaving (1-bit). - ///< - FALSE = disable (default) - ///< - TRUE = enable - ///< - ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING} - - IN BOOLEAN EnableChannelIntlv; ///< Channel Interleaving (1-bit). - ///< - FALSE = disable (default) - ///< - TRUE = enable - ///< - ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING} - // ECC - - IN BOOLEAN EnableEccFeature; ///< enable ECC error to go into MCE. - ///< - FALSE = disable (default) - ///< - TRUE = enable - ///< - ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE} - // Dram Power - - IN BOOLEAN EnablePowerDown; ///< CKE based power down mode (1-bit). - ///< - FALSE =disable (default) - ///< - TRUE =enable - ///< - ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN} - - // Online Spare - - IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0. - ///< - FALSE = disable Spare (default) - ///< - TRUE = enable Spare - ///< - ///< @BldCfgItem{BLDCFG_ONLINE_SPARE} - - IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings. - - IN PSO_TABLE *PlatformMemoryConfiguration; - ///< A table that contains platform specific settings. - ///< For example, MemClk routing, the number of DIMM slots per channel, .... - ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that - ///< contains default conservative settings. Platform BIOS can either tweak - ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table. - ///< - IN BOOLEAN EnableParity; ///< Parity control. - ///< - TRUE = enable - ///< - FALSE = disable (default) - ///< - ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE} - - IN BOOLEAN EnableBankSwizzle; ///< BankSwizzle control. - ///< - FALSE = disable - ///< - TRUE = enable (default) - ///< - ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE} - - ///< - - IN BOOLEAN EnableMemClr; ///< Memory Clear functionality control. - ///< - FALSE = disable - ///< - TRUE = enable (default) - ///< - - // Uma Configuration - - IN UMA_MODE UmaMode; ///< Uma Mode - ///< 0 = None - ///< 1 = Specified - ///< 2 = Auto - IN OUT UINT32 UmaSize; ///< The size of shared graphics dram (16-bits) - ///< NV_UMA_Size[31:0]=Addr[47:16] - ///< - OUT UINT32 UmaBase; ///< The allocated Uma base address (32-bits) - ///< NV_UMA_Base[31:0]=Addr[47:16] - ///< - - /// Memory Restore Feature - - IN BOOLEAN MemRestoreCtl; ///< Memory context restore control - ///< FALSE = perform memory init as normal (AMD default) - ///< TRUE = restore memory context and skip training. This requires - ///< MemContext is valid before AmdInitPost - ///< - IN BOOLEAN SaveMemContextCtl; ///< Control switch to save memory context at the end of MemAuto - ///< TRUE = AGESA will setup MemContext block before exit AmdInitPost - ///< FALSE = AGESA will not setup MemContext block. Platform is - ///< expected to call S3Save later in POST if it wants to - ///< use memory context restore feature. - ///< - IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to - ///< save and restore for memory context restore feature to work. - ///< It uses the subset of S3Save block to save/restore. Hence platform - ///< may save only S3 block and uses it for both S3 resume and - ///< memory context restore. - ///< - If MemRestoreCtl is TRUE, platform needs to pass in MemContext - ///< before AmdInitPost. - ///< - If SaveMemContextCtl is TRUE, platform needs to save MemContext - ///< right after AmdInitPost. - ///< - IN BOOLEAN ExternalVrefCtl; ///< Control the use of external Vref - ///< TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_VREF_CHANGE" in function list - ///< to change the vref - ///< FALSE = AGESA will will use the internal vref control. - ///< @BldCfgItem{BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE} - ///< - IN FORCE_TRAIN_MODE ForceTrainMode; ///< Training Mode - ///< 0 = Force 1D Training for all configurations - ///< 1 = Force training for all configurations - ///< 2 = Auto - AGESA will control -} MEM_PARAMETER_STRUCT; - - -/// -/// Function definition. -/// This data structure passes function pointers to the memory configuration code. -/// The wrapper can use this structure with customized versions. -/// -typedef struct _MEM_FUNCTION_STRUCT { - - // PUBLIC required Internal functions - - IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData); ///< Proc for Unbuffered DIMMs, platform specific - IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData); ///< Proc for Registered DIMMs, platform specific - - // PUBLIC optional functions - - IN OUT VOID (*amdMemEccInit) (VOID *pMemData); ///< NB proc for ECC feature - IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature - IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData); ///< NB proc for Channel interleave feature - IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData); ///< NB proc for Node interleave feature - IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData); ///< NB proc for parallel training feature - IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData); ///< NB code for early sample support feature - IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData); ///< NB code for 'multi-part' - IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData); ///< NB code for On-Line Spare feature - IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData); ///< NB code for UDIMMs - IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData); ///< NB code for RDIMMs - IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData); ///< NB code for LRDIMMs - IN OUT UINT32 Reserved[100]; ///< Reserved for later function definition -} MEM_FUNCTION_STRUCT; - -/// -/// Socket Structure -/// -/// -typedef struct _MEM_SOCKET_STRUCT { - OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels training data - - OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels timing data -} MEM_SOCKET_STRUCT; - -/// -/// Contains all data relevant to Memory Initialization. -/// -typedef struct _MEM_DATA_STRUCT { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - - IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///< List of input Parameters - - OUT MEM_FUNCTION_STRUCT FunctionList; ///< List of function Pointers - - IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info - - IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling - - - OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///< Socket list for memory code. - ///< SocketList is a shortcut for IBVs to retrieve training - ///< and timing data for each channel indexed by socket/channel, - ///< eliminating their need to parse die/dct/channel etc. - ///< It contains pointers to the populated data structures for - ///< each channel and skips the channel structures that are - ///< unpopulated. In the case of channels sharing the same DCT, - ///< the pTimings pointers will point to the same DCT Timing data. - - OUT DIE_STRUCT *DiesPerSystem; ///< Pointed to an array of DIE_STRUCTs - OUT UINT8 DieCount; ///< Number of MCTs in the system. - - IN SPD_DEF_STRUCT *SpdDataStructure; ///< Pointer to SPD Data structure - - IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///< Platform profile/build option config structure - - IN OUT BOOLEAN IsFlowControlSupported; ///< Indicates if flow control is supported - - OUT UINT32 TscRate; ///< The rate at which the TSC increments in megahertz. - -} MEM_DATA_STRUCT; - -/// -/// Uma Structure -/// -/// -typedef struct _UMA_INFO { - OUT UINT64 UmaBase; ///< UmaBase[63:0] = Addr[63:0] - OUT UINT32 UmaSize; ///< UmaSize[31:0] = Addr[31:0] - OUT UINT32 UmaAttributes; ///< Indicate the attribute of Uma - OUT UINT8 UmaMode; ///< Indicate the mode of Uma - OUT UINT16 MemClock; ///< Indicate memory running speed in MHz - OUT UINT8 Reserved[3]; ///< Reserved for future usage -} UMA_INFO; - -/// Bitfield for ID -typedef struct { - OUT UINT16 SocketId:8; ///< Socket ID - OUT UINT16 ModuleId:8; ///< Module ID -} ID_FIELD; -/// -/// Union for ID of socket and module that will be passed out in call out -/// -typedef union { - OUT ID_FIELD IdField; ///< Bitfield for ID - OUT UINT16 IdInformation; ///< ID information for call out -} ID_INFO; - -// AGESA MEMORY ERRORS - -// AGESA_ALERT Memory Errors -#define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000 ///< TIMING_MODE_SPECIFIC is requested but - ///< cannot be applied to current configurations. -#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100 ///< DIMM organization miss-match -#define MEM_ALERT_BK_INT_DIS 0x04010200 ///< Bank interleaving disable for internal issue - -// AGESA_ERROR Memory Errors -#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300 ///< No DQS Position window for RD DQS -#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300 ///< Small DQS Position window for RD DQS -#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300 ///< No DQS Position window for WR DQS -#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300 ///< Small DQS Position window for WR DQS -#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues -#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large -#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window -#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit -#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit -#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit -#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit -#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit -#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit -#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit -#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit -#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit -#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit -#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit -#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit -#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit -#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training -#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP -#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training -#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm -#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value -#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit -#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200 ///< SPD Checksum error for NV_SPDCHK_RESTRT -#define MEM_ERROR_NO_CHIPSELECT 0x04011300 ///< No chipselects found -#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500 ///< Unbuffered dimm is not supported at 333MHz -#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300 ///< Returned PRE value during write levelizzation was out of range -#define MEM_ERROR_NO____RDDQS_WINDOW 0x040D0300 ///< No RdDqs Window -#define MEM_ERROR_NO____RDDQS_HEIGHT 0x040E0300 ///< No RdDqs Height -#define MEM_ERROR____DQS_ERROR 0x040F0300 ///< RdDqs Error -#define MEM_ERROR_INVALID____RDDQS_VALUE 0x04022400 ///< RdDqs invalid value found -#define MEM_ERROR____DQS_VREF_MARGIN_ERROR 0x04023400 ///< RdDqs Vef Margin error found -#define MEM_ERROR_LR_IBT_NOT_FOUND 0x04013500 ///< No LR dimm IBT value is found -#define MEM_ERROR_MR0_NOT_FOUND 0x04023500 ///< No MR0 value is found -#define MEM_ERROR_ODT_PATTERN_NOT_FOUND 0x04033500 ///< No odt pattern value is found -#define MEM_ERROR_RC2_IBT_NOT_FOUND 0x04043500 ///< No RC2 IBT value is found -#define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND 0x04053500 ///< No RC10 op speed is found -#define MEM_ERROR_RTT_NOT_FOUND 0x04063500 ///< No RTT value is found -#define MEM_ERROR_P___NOT_FOUND 0x04073500 ///< No training config value is found -#define MEM_ERROR_SAO_NOT_FOUND 0x04083500 ///< No slow access mode, Address timing and Output driver compensation value is found -#define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND 0x04093500 ///< No CLK disable map is found -#define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND 0x040A3500 ///< No CKE tristate map is found -#define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500 ///< No ODT tristate map is found -#define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500 ///< No CS tristate map is found -#define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500 ///< No training seed is found - -// AGESA_WARNING Memory Errors -#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600 ///< QR DIMMs detected but not supported -#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600 ///< U DIMMs detected but not supported -#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600 ///< SO-DIMMs detected but not supported -#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600 ///< x4 DIMMs detected but not supported -#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600 ///< R DIMMs detected but not supported -#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600 ///< LR DIMMs detected but not supported -#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700 ///< Processor is not capable for EMP -#define MEM_WARNING_EMP_CONFLICT 0x04021700 ///< EMP cannot be enabled if channel interleaving, -#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700 ///< Memory size is not power of two. -#define MEM_WARNING_ECC_DIS 0x04041700 ///< ECC has been disabled as a result of an internal issue -#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800 ///< Performance has been enabled, but battery life is preferred. - ///< bank interleaving, or bank swizzle is enabled. -#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900 ///< No Trc timing value found in SPD of a dimm. -#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000 ///< Node Interleaveing Requested, but could not be enabled -#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled -#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled -#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported -#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400 ///< DDR3 voltage initial value is not 0 -#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO 0x04012500 ///< Cannot find a commonly supported VDDIO - -// AGESA_FATAL Memory Errors -#define MEM_ERROR_MINIMUM_MODE 0x04011A00 ///< Running in minimum mode -#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00 ///< DIMM modules are miss-matched -#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs have been found -#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00 ///< DIMM clocks miss-matched -#define MEM_ERROR_NO_CYC_TIME 0x04011E00 ///< No cycle time found -#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00 ///< Heap allocation error with dynamic storing of trained timings -#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT -#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV -#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00 ///< Heap allocation error for SPD data -#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00 ///< Heap allocation error for RECEIVED_DATA during parallel training -#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00 ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER" -#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00 ///< Heap allocation error for Training Data -#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00 ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK -#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300 ///< No Constructor for DIMM Identify -#define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500 ///< VDDIO of the dimms on the board is not supported -#define MEM_ERROR_HEAP_ALLOCATE_FOR___ 0x040B1F00 ///< Heap allocation error for training data -#define MEM_ERROR_HEAP_DEALLOCATE_FOR___ 0x040C1F00 ///< Heap de-allocation error for training data - -// AGESA_CRITICAL Memory Errors -#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00 ///< Heap allocation error for DMI table for DDR3 -#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00 ///< Heap allocation error for DMI table for DDR2 -#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400 ///< Dimm population is not supported - - - -/*---------------------------------------------------------------------------- - * - * END OF MEMORY-SPECIFIC DATA STRUCTURES - * - *---------------------------------------------------------------------------- - */ - - - - -/*---------------------------------------------------------------------------- - * - * CPU RELATED DEFINITIONS - * - *---------------------------------------------------------------------------- - */ - -// CPU Event definitions. - -// Defines used to filter CPU events based on functional blocks -#define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00 -#define CPU_EVENT_PM_EVENT_CLASS 0x08000400 - -//================================================================ -// CPU General events -// Heap allocation (AppFunction = 01h) -#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100 -#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100 -#define CPU_ERROR_HEAP_IS_FULL 0x08020100 -#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100 -#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100 -// BrandId (AppFunction = 02h) -#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200 -// Micro code patch (AppFunction = 03h) -#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300 -// Power management (AppFunction = 04h) -#define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400 -#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400 -#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400 -#define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400 -// Other CPU events (AppFunction = 05h) -#define CPU_EVENT_BIST_ERROR 0x08000500 -#define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY 0x08010500 -#define CPU_EVENT_STACK_REENTRY 0x08020500 -#define CPU_EVENT_CORE_NOT_IDENTIFIED 0x08030500 - -//================================================================= -// CPU Feature events -// Execution cache (AppFunction = 21h) -// AGESA_CACHE_SIZE_REDUCED 2101 -// AGESA_CACHE_REGIONS_ACROSS_1MB 2102 -// AGESA_CACHE_REGIONS_ACROSS_4GB 2103 -// AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104 -// AGESA_CACHE_START_ADDRESS_LESS_D0000 2105 -// AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106 -// AGESA_DEALLOCATE_CACHE_REGIONS 2107 -#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100 -// Core Leveling (AppFunction = 22h) -#define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200 -// HT Assist (AppFunction = 23h) -#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG 0x08002300 - -// CPU Build Configuration structures and definitions - -/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS -typedef struct { - IN UINT32 MsrAddr; ///< Fixed-Sized MTRR address - IN UINT64 MsrData; ///< MTRR Settings -} AP_MTRR_SETTINGS; - -#define AMD_AP_MTRR_FIX64k_00000 0x00000250 -#define AMD_AP_MTRR_FIX16k_80000 0x00000258 -#define AMD_AP_MTRR_FIX16k_A0000 0x00000259 -#define AMD_AP_MTRR_FIX4k_C0000 0x00000268 -#define AMD_AP_MTRR_FIX4k_C8000 0x00000269 -#define AMD_AP_MTRR_FIX4k_D0000 0x0000026A -#define AMD_AP_MTRR_FIX4k_D8000 0x0000026B -#define AMD_AP_MTRR_FIX4k_E0000 0x0000026C -#define AMD_AP_MTRR_FIX4k_E8000 0x0000026D -#define AMD_AP_MTRR_FIX4k_F0000 0x0000026E -#define AMD_AP_MTRR_FIX4k_F8000 0x0000026F -#define CPU_LIST_TERMINAL 0xFFFFFFFF - -/// Data structure for the Mapping Item between Unified ID for IDS Setup Option -/// and the option value. -/// -typedef struct { - IN UINT16 IdsNvId; ///< Unified ID for IDS Setup Option. - OUT UINT16 IdsNvValue; ///< The value of IDS Setup Option. -} IDS_NV_ITEM; - -/// Data Structure for IDS CallOut Function -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN IDS_NV_ITEM *IdsNvPtr; ///< Memory Pointer of IDS NV Table - IN OUT UINTN Reserved; ///< reserved -} IDS_CALLOUT_STRUCT; - -/************************************************************************ - * - * AGESA interface Call-Out function parameter structures - * - ***********************************************************************/ - -/// Parameters structure for interface call-out AgesaAllocateBuffer -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN OUT UINT32 BufferLength; ///< Size of buffer to allocate - IN UINT32 BufferHandle; ///< Identifier or name for the buffer - OUT VOID *BufferPointer; ///< location of the created buffer -} AGESA_BUFFER_PARAMS; - -/// Parameters structure for interface call-out AgesaRunCodeOnAp -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT32 FunctionNumber; ///< Index of the procedure to execute - IN VOID *RelatedDataBlock; ///< Location of data structure the procedure will use - IN UINT32 RelatedBlockLength; ///< Size of the related data block -} AP_EXE_PARAMS; - -/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT8 SocketId; ///< Address of SPD - socket ID - IN UINT8 MemChannelId; ///< Address of SPD - memory channel ID - IN UINT8 DimmId; ///< Address of SPD - DIMM ID - IN OUT UINT8 *Buffer; ///< Location where to place the SPD content - IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference -} AGESA_READ_SPD_PARAMS; - -/// Buffer Handles -typedef enum { - AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000, ///< Assign 0x000D000 buffer handle to DMI function - AMD_PSTATE_DATA_BUFFER_HANDLE, ///< Assign 0x000D001 buffer handle to Pstate data - AMD_PSTATE_ACPI_BUFFER_HANDLE, ///< Assign 0x000D002 buffer handle to Pstate table - AMD_BRAND_ID_BUFFER_HANDLE, ///< Assign 0x000D003 buffer handle to Brand ID - AMD_ACPI_SLIT_BUFFER_HANDLE, ///< Assign 0x000D004 buffer handle to SLIT function - AMD_SRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D005 buffer handle to SRAT function - AMD_WHEA_BUFFER_HANDLE, ///< Assign 0x000D006 buffer handle to WHEA function - AMD_S3_INFO_BUFFER_HANDLE, ///< Assign 0x000D007 buffer handle to S3 function - AMD_S3_NB_INFO_BUFFER_HANDLE, ///< Assign 0x000D008 buffer handle to S3 NB device info - AMD_ACPI_ALIB_BUFFER_HANDLE, ///< Assign 0x000D009 buffer handle to ALIB SSDT table - AMD_ACPI_IVRS_BUFFER_HANDLE ///< Assign 0x000D00A buffer handle to IOMMU IVRS table -} AMD_BUFFER_HANDLE; -/************************************************************************ - * - * AGESA interface Call-Out function prototypes - * - ***********************************************************************/ - -VOID -AgesaDoReset ( - IN UINTN ResetType, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -AgesaAllocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *AllocParams - ); - -AGESA_STATUS -AgesaDeallocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *DeallocParams - ); - -AGESA_STATUS -AgesaLocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *LocateParams - ); - -AGESA_STATUS -AgesaReadSpd ( - IN UINTN FcnData, - IN OUT AGESA_READ_SPD_PARAMS *ReadSpd - ); - -AGESA_STATUS -AgesaReadSpdRecovery ( - IN UINTN FcnData, - IN OUT AGESA_READ_SPD_PARAMS *ReadSpd - ); - -AGESA_STATUS -AgesaHookBeforeDramInitRecovery ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ); - -AGESA_STATUS -AgesaRunFcnOnAp ( - IN UINTN ApicIdOfCore, - IN AP_EXE_PARAMS *LaunchApParams - ); - -AGESA_STATUS -AgesaHookBeforeDramInit ( - IN UINTN SocketIdModuleId, - IN OUT MEM_DATA_STRUCT *MemData - ); - -AGESA_STATUS -AgesaHookBeforeDQSTraining ( - IN UINTN SocketIdModuleId, - IN OUT MEM_DATA_STRUCT *MemData - ); - -AGESA_STATUS -AgesaHookBeforeExitSelfRefresh ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ); - -AGESA_STATUS -AgesaPcieSlotResetControl ( - IN UINTN FcnData, - IN PCIe_SLOT_RESET_INFO *ResetInfo - ); - -AGESA_STATUS -AgesaFchOemCallout ( - IN VOID *FchData - ); - -AGESA_STATUS -AgesaExternal__TrainVrefChange ( - IN UINTN SocketIdModuleId, - IN OUT MEM_DATA_STRUCT *MemData - ); - -AGESA_STATUS -AgesaGetIdsData ( - IN UINTN Data, - IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData - ); -/************************************************************************ - * - * AGESA interface structure definition and function prototypes - * - ***********************************************************************/ - -/********************************************************************** - * Platform Configuration: The parameters in boot branch function - **********************************************************************/ - -/// The possible platform control flow settings. -typedef enum { - Nfcm, ///< Normal Flow Control Mode. - UmaDr, ///< UMA using Display Refresh flow control. - UmaIfcm, ///< UMA using Isochronous Flow Control. - Ifcm, ///< Isochronous Flow Control Mode (other than for UMA). - Iommu, ///< An IOMMU is in use in the system. - MaxControlFlow ///< Not a control flow mode, use for limit checking. -} PLATFORM_CONTROL_FLOW; - -/// Platform Deemphasis Levels. -/// -/// The deemphasis level is set for the receiver, based on link characterization. The DCV level is -/// set based on the level of the far transmitter. -typedef enum { - DeemphasisLevelNone, ///< No Deemphasis. - DeemphasisLevelMinus3, ///< Minus 3 db deemphasis. - DeemphasisLevelMinus6, ///< Minus 6 db deemphasis. - DeemphasisLevelMinus8, ///< Minus 8 db deemphasis. - DeemphasisLevelMinus11, ///< Minus 11 db deemphasis. - DeemphasisLevelMinus11pre8, ///< Minus 11, Minus 8 precursor db deemphasis. - DcvLevelNone = 16, ///< No DCV Deemphasis. - DcvLevelMinus2, ///< Minus 2 db DCV deemphasis. - DcvLevelMinus3, ///< Minus 3 db DCV deemphasis. - DcvLevelMinus5, ///< Minus 5 db DCV deemphasis. - DcvLevelMinus6, ///< Minus 6 db DCV deemphasis. - DcvLevelMinus7, ///< Minus 7 db DCV deemphasis. - DcvLevelMinus8, ///< Minus 8 db DCV deemphasis. - DcvLevelMinus9, ///< Minus 9 db DCV deemphasis. - DcvLevelMinus11, ///< Minus 11 db DCV deemphasis. - MaxPlatformDeemphasisLevel ///< Not a deemphasis level, use for limit checking. -} PLATFORM_DEEMPHASIS_LEVEL; - -/// Provide Deemphasis Levels for HT Links. -/// -/// For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will -/// be checked for a match. The item matches for a Socket, Link if the link frequency is -/// is in the inclusive range HighFreq:LoFreq. -/// AGESA does not set deemphasis in IO devices, only in processors. - -typedef struct { - // Match fields - IN UINT8 Socket; ///< One Socket on which this Link is located - IN UINT8 Link; ///< The Link on this Processor. - IN UINT8 LoFreq; ///< If the link is set to this frequency or greater, apply these levels, and - IN UINT8 HighFreq; ///< If the link is set to this frequency or less, apply these levels. - // Value fields - IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis; ///< The deemphasis level for this link - IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis; ///< The DCV, or far transmitter deemphasis level. -} CPU_HT_DEEMPHASIS_LEVEL; - - -/// The possible hardware prefetch mode settings. -typedef enum { - HARDWARE_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. - DISABLE_L1_PREFETCHER, ///< Use the recommended settings for the hardware prefetcher, but disable L1 prefetching. - DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< Use the recommended setting for the hardware prefetcher, but disable training on software prefetches. - DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< Use the recommended settings for the hardware prefetcher, but disable both the L1 prefetcher and training on software prefetches. - DISABLE_HARDWARE_PREFETCH, ///< Disable hardware prefetching. - MAX_HARDWARE_PREFETCH_MODE ///< Not a hardware prefetch mode, use for limit checking. -} HARDWARE_PREFETCH_MODE; - -/// The possible software prefetch mode settings. -typedef enum { - SOFTWARE_PREFETCHES_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. - DISABLE_SOFTWARE_PREFETCHES, ///< Disable software prefetches (convert software prefetch instructions to NOP). - MAX_SOFTWARE_PREFETCH_MODE ///< Not a software prefetch mode, use for limit checking. -} SOFTWARE_PREFETCH_MODE; - -/// Advanced performance tunings, prefetchers. -/// These settings provide for performance tuning to optimize for specific workloads. -typedef struct { - IN HARDWARE_PREFETCH_MODE HardwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the hardware prefetcher setting. - IN SOFTWARE_PREFETCH_MODE SoftwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the software prefetch instructions. - IN DRAM_PREFETCH_MODE DramPrefetchMode; ///< This value provides for advanced performance tuning by controlling the DRAM prefetcher setting. -} ADVANCED_PERFORMANCE_PROFILE; - -/// The possible platform power policy settings. -typedef enum { - Performance, ///< Optimize for performance. - BatteryLife, ///< Optimize for battery life. - MaxPowerPolicy ///< Not a power policy mode, use for limit checking. -} PLATFORM_POWER_POLICY; - -/// Platform performance settings for optimized settings. -/// Several configuration settings for the processor depend upon other parts and -/// general designer choices for the system. The determination of these data points -/// is not standard for all platforms, so the host environment needs to provide these -/// to specify how the system is to be configured. -typedef struct { - IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; ///< The platform's control flow mode for optimum platform performance. - ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE} - IN BOOLEAN UseHtAssist; ///< HyperTransport link traffic optimization. - ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST} - IN BOOLEAN UseAtmMode; ///< HyperTransport link traffic optimization. - ///< @BldCfgItem{BLDCFG_USE_ATM_MODE} - IN BOOLEAN Use32ByteRefresh; ///< Display Refresh traffic generates 32 byte requests. - ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH} - IN BOOLEAN UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority. - ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY} - IN ADVANCED_PERFORMANCE_PROFILE AdvancedPerformanceProfile; ///< The advanced platform performance settings. - IN PLATFORM_POWER_POLICY PlatformPowerPolicy; ///< The platform's desired power policy - ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE} -} PERFORMANCE_PROFILE; - -/// Platform settings that describe the voltage regulator modules of the system. -/// Many power management settings are dependent upon the characteristics of the -/// on-board voltage regulator module (VRM). The host environment needs to provide -/// these to specify how the system is to be configured. -typedef struct { - IN UINT32 CurrentLimit; ///< Vrm Current Limit. - ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT} - ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT} - IN UINT32 LowPowerThreshold; ///< Vrm Low Power Threshold. - ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD} - ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD} - IN UINT32 SlewRate; ///< Vrm Slew Rate. - ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE} - ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE} - IN UINT32 AdditionalDelay; ///< Vrm Additional Delay. - ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY} - ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY} - IN BOOLEAN HiSpeedEnable; ///< Select high speed VRM. - ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE} - ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE} - IN UINT32 InrushCurrentLimit; ///< Vrm Inrush Current Limit. - ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT} - ///< @BldCfgItem{BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT} -} PLATFORM_VRM_CONFIGURATION; - -/// The VRM types to characterize. -typedef enum { - CoreVrm, ///< VDD plane. - NbVrm, ///< VDDNB plane. - MaxVrmType ///< Not a valid VRM type, use for limit checking. -} PLATFORM_VRM_TYPE; - - -/// FCH Platform Configuration Policy -typedef struct { - IN UINT16 CfgSmbus0BaseAddress; ///< SMBUS0 Controller Base Address - IN UINT16 CfgSmbus1BaseAddress; ///< SMBUS1 Controller Base Address - IN UINT16 CfgSioPmeBaseAddress; ///< I/O base address for LPC I/O target range - IN UINT16 CfgAcpiPm1EvtBlkAddr; ///< I/O base address of ACPI power management Event Block - IN UINT16 CfgAcpiPm1CntBlkAddr; ///< I/O base address of ACPI power management Control Block - IN UINT16 CfgAcpiPmTmrBlkAddr; ///< I/O base address of ACPI power management Timer Block - IN UINT16 CfgCpuControlBlkAddr; ///< I/O base address of ACPI power management CPU Control Block - IN UINT16 CfgAcpiGpe0BlkAddr; ///< I/O base address of ACPI power management General Purpose Event Block - IN UINT16 CfgSmiCmdPortAddr; ///< I/O base address of ACPI SMI Command Block - IN UINT16 CfgAcpiPmaCntBlkAddr; ///< I/O base address of ACPI power management additional control block - IN UINT32 CfgGecShadowRomBase; ///< 32-bit base address to the GEC shadow ROM - IN UINT32 CfgWatchDogTimerBase; ///< Watchdog Timer base address - IN UINT32 CfgSpiRomBaseAddress; ///< Base address for the SPI ROM controller - IN UINT32 CfgHpetBaseAddress; ///< HPET MMIO base address - IN UINT32 CfgAzaliaSsid; ///< Subsystem ID of HD Audio controller - IN UINT32 CfgSmbusSsid; ///< Subsystem ID of SMBUS controller - IN UINT32 CfgIdeSsid; ///< Subsystem ID of IDE controller - IN UINT32 CfgSataAhciSsid; ///< Subsystem ID of SATA controller in AHCI mode - IN UINT32 CfgSataIdeSsid; ///< Subsystem ID of SATA controller in IDE mode - IN UINT32 CfgSataRaid5Ssid; ///< Subsystem ID of SATA controller in RAID5 mode - IN UINT32 CfgSataRaidSsid; ///< Subsystem ID of SATA controller in RAID mode - IN UINT32 CfgEhciSsid; ///< Subsystem ID of EHCI - IN UINT32 CfgOhciSsid; ///< Subsystem ID of OHCI - IN UINT32 CfgLpcSsid; ///< Subsystem ID of LPC ISA Bridge - IN UINT32 CfgSdSsid; ///< Subsystem ID of SecureDigital controller - IN UINT32 CfgXhciSsid; ///< Subsystem ID of XHCI - IN BOOLEAN CfgFchPort80BehindPcib; ///< Is port80 cycle going to the PCI bridge - IN BOOLEAN CfgFchEnableAcpiSleepTrap; ///< ACPI sleep SMI enable/disable - IN GPP_LINKMODE CfgFchGppLinkConfig; ///< GPP link configuration - IN BOOLEAN CfgFchGppPort0Present; ///< Is FCH GPP port 0 present - IN BOOLEAN CfgFchGppPort1Present; ///< Is FCH GPP port 1 present - IN BOOLEAN CfgFchGppPort2Present; ///< Is FCH GPP port 2 present - IN BOOLEAN CfgFchGppPort3Present; ///< Is FCH GPP port 3 present - IN BOOLEAN CfgFchGppPort0HotPlug; ///< Is FCH GPP port 0 hotplug capable - IN BOOLEAN CfgFchGppPort1HotPlug; ///< Is FCH GPP port 1 hotplug capable - IN BOOLEAN CfgFchGppPort2HotPlug; ///< Is FCH GPP port 2 hotplug capable - IN BOOLEAN CfgFchGppPort3HotPlug; ///< Is FCH GPP port 3 hotplug capable - - IN UINT8 CfgFchEsataPortBitMap; ///< ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable - IN UINT8 CfgFchIrPinControl; ///< Register bitfield describing Infrared Pin Control: - ///< [0] - IR Enable 0 - ///< [1] - IR Enable 1 - ///< [2] - IR Tx0 - ///< [3] - IR Tx1 - ///< [4] - IR Open Drain - ///< [5] - IR Enable LED - IN SD_CLOCK_CONTROL CfgFchSdClockControl; ///< FCH SD Clock Control - IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control - IN SATA_PHY_CONTROL *CfgFchSataPhyControl; ///< FCH SATA PHY Control - IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control -} FCH_PLATFORM_POLICY; - - -/// Build Option/Configuration Boolean Structure. -typedef struct { - IN AMD_CODE_HEADER VersionString; ///< AMD embedded code version string - - //Build Option Area - IN BOOLEAN OptionUDimms; ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT" - IN BOOLEAN OptionRDimms; ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT" - IN BOOLEAN OptionLrDimms; ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT" - IN BOOLEAN OptionEcc; ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT" - IN BOOLEAN OptionBankInterleave; ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE" - IN BOOLEAN OptionDctInterleave; ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE" - IN BOOLEAN OptionNodeInterleave; ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE" - IN BOOLEAN OptionParallelTraining; ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING" - IN BOOLEAN OptionOnlineSpare; ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT" - IN BOOLEAN OptionMemRestore; ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT" - IN BOOLEAN OptionMultisocket; ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT" - IN BOOLEAN OptionAcpiPstates; ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES" - IN BOOLEAN OptionPStatesInHpcMode; ///< @ref BLDCFG_PSTATE_HPC_MODE "BLDCFG_PSTATE_HPC_MODE" - IN BOOLEAN OptionSrat; ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT" - IN BOOLEAN OptionSlit; ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT" - IN BOOLEAN OptionWhea; ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA" - IN BOOLEAN OptionDmi; ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI" - IN BOOLEAN OptionEarlySamples; ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES" - IN BOOLEAN OptionAddrToCsTranslator; ///< ADDR_TO_CS_TRANSLATOR - - //Build Configuration Area - IN UINT64 CfgPciMmioAddress; ///< Pci Mmio Base Address to use for PCI Config accesses. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE} - IN UINT32 CfgPciMmioSize; ///< Pci Mmio region Size. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE} - IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules. - IN UINT32 CfgPlatNumIoApics; ///< The number of IO APICS for the platform. - IN UINT32 CfgMemInitPstate; ///< Memory Init Pstate. - IN PLATFORM_C1E_MODES CfgPlatformC1eMode; ///< Select the C1e Mode that will used. - IN UINT32 CfgPlatformC1eOpData; ///< An IO port or additional C1e setup data, depends on C1e mode. - IN UINT32 CfgPlatformC1eOpData1; ///< An IO port or additional C1e setup data, depends on C1e mode. - IN UINT32 CfgPlatformC1eOpData2; ///< An IO port or additional C1e setup data, depends on C1e mode. - IN UINT32 CfgPlatformC1eOpData3; ///< An IO port or additional C1e setup data, depends on C1e mode. - IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used. - IN UINT32 CfgPlatformCStateOpData; ///< An IO port or additional C-State setup data, depends on C-State mode. - IN UINT16 CfgPlatformCStateIoBaseAddress; ///< Specifies I/O ports that can be used to allow CPU to enter CStates - IN PLATFORM_CPB_MODES CfgPlatformCpbMode; ///< Enable or disable core performance boost - IN PLATFORM_LOW_POWER_PSTATE_MODES CfgLowPowerPstateForProcHot; ///< Low power Pstate for PROCHOT mode - IN UINT32 CfgCoreLevelingMode; ///< Apply any downcoring or core count leveling as specified. - IN PERFORMANCE_PROFILE CfgPerformanceProfile; ///< The platform's control flow mode and platform performance settings. - IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links. - - IN UINT32 CfgAmdPlatformType; ///< Designate the platform as a Server, Desktop, or Mobile. - IN UINT32 CfgAmdPstateCapValue; ///< Amd pstate ceiling enabling deck - - IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT} - IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED} - IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE} - IN QUANDRANK_TYPE CfgMemoryQuadrankType; ///< Memory Quadrank Type. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE} - IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable. - IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable. - IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable. - IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE} - IN BOOLEAN CfgLimitMemoryToBelow1Tb; ///< Limit memory address space to below 1TB - IN BOOLEAN CfgMemoryEnableBankInterleaving; ///< Memory Enable Bank Interleaving. - IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving. - IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving. - IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down. - IN POWER_DOWN_MODE CfgPowerDownMode; ///< Power Down Mode. - IN BOOLEAN CfgOnlineSpare; ///< Online Spare. - IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable. - IN BOOLEAN CfgBankSwizzle; ///< Bank Swizzle. - IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select. - IN MEMORY_BUS_SPEED CfgMemoryClockSelect; ///< Memory Clock Select. - IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL} - IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM} - IN BOOLEAN CfgUseBurstMode; ///< Use Burst Mode. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE} - IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON} - IN BOOLEAN CfgEnableEccFeature; ///< Enable ECC Feature. - IN BOOLEAN CfgEccRedirection; ///< ECC Redirection. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION} - IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE} - IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE} - IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE} - IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE} - IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE} - IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD} - IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE} - IN UINT64 CfgHeapDramAddress; ///< Heap contents will be temporarily stored in this address during the transition. - ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS} - IN BOOLEAN CfgNodeMem1GBAlign; ///< Node Mem 1GB boundary Alignment - IN BOOLEAN CfgS3LateRestore; ///< S3 Late Restore - IN BOOLEAN CfgAcpiPstateIndependent; ///< PSD method dependent/Independent - IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList; ///< The AP's MTRR settings before final halt - ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST} - IN UMA_MODE CfgUmaMode; ///< Uma Mode - IN UINT32 CfgUmaSize; ///< Uma Size [31:0]=Addr[47:16] - IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support - IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment - IN BOOLEAN CfgProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope - IN CHAR8 CfgProcessorScopeName0; ///< OEM specific 1st character of processor scope name. - IN CHAR8 CfgProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. - IN UINT8 CfgGnbHdAudio; ///< GNB HD Audio - IN UINT8 CfgAbmSupport; ///< Abm Support - IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate - IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control - IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID. - IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address - ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS} - IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID - ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID} - IN UINT32 CfgGnbHDAudioSSID; ///< Gnb HD Audio SSID - ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID} - IN UINT32 CfgGnbPcieSSID; ///< Gnb PCIe SSID - ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID} - IN UINT16 CfgLvdsSpreadSpectrum; ///< Lvds Spread Spectrum - ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} - IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate - ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} - IN FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy - - IN BOOLEAN CfgIommuSupport; ///< IOMMU support - IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqDeToDigon; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing - IN UINT8 CfgLvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing - IN UINT16 CfgLvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported - IN UINT32 CfgLcdBitDepthControlValue; ///< The LCD bit depth control settings - IN UINT8 CfgLvds24bbpPanelMode; ///< The LVDS 24 BBP mode - IN LVDS_MISC_CONTROL CfgLvdsMiscControl; ///< THe LVDS Misc control - IN UINT16 CfgPcieRefClkSpreadSpectrum; ///< PCIe Reference Clock Spread Spectrum - ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} - IN BOOLEAN CfgExternalVrefCtlFeature; ///< External Vref control - IN FORCE_TRAIN_MODE CfgForceTrainMode; ///< Force Train Mode - IN BOOLEAN CfgGnbRemoteDisplaySupport; ///< Wireless Display Support - IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *CfgIvrsExclusionRangeList; - IN BOOLEAN Reserved; ///< reserved... -} BUILD_OPT_CFG; - -/// A structure containing platform specific operational characteristics. This -/// structure is initially populated by the initializer with a copy of the same -/// structure that was created at build time using the build configuration controls. -typedef struct _PLATFORM_CONFIGURATION { - IN PERFORMANCE_PROFILE PlatformProfile; ///< Several configuration settings for the processor. - IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links. - ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}. - ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples". - IN UINT8 CoreLevelingMode; ///< Indicates how to balance the number of cores per processor. - ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE} - IN PLATFORM_C1E_MODES C1eMode; ///< Specifies the method of C1e enablement - Disabled, HW, or message based. - ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE} - IN UINT32 C1ePlatformData; ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform. - ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA} - IN UINT32 C1ePlatformData1; ///< If C1eMode is SW, specifies the address of chipset's SMI command port. - ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1} - IN UINT32 C1ePlatformData2; ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source. - ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2} - IN UINT32 C1ePlatformData3; ///< If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e - ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA3} - IN PLATFORM_CSTATE_MODES CStateMode; ///< Specifies the method of C-State enablement - Disabled, or C6. - ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE} - IN UINT32 CStatePlatformData; ///< This element specifies some pertinent data needed for the operation of the Cstate feature - ///< If CStateMode is CStateModeC6, this item is reserved - ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA} - IN UINT16 CStateIoBaseAddress; ///< This item specifies a free block of 8 consecutive bytes of I/O ports that - ///< can be used to allow the CPU to enter Cstates. - ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS} - IN PLATFORM_CPB_MODES CpbMode; ///< Specifies the method of core performance boost enablement - Disabled, or Auto. - ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE} - IN BOOLEAN UserOptionDmi; ///< When set to TRUE, the DMI data table is generated. - IN BOOLEAN UserOptionPState; ///< When set to TRUE, the PState data tables are generated. - IN BOOLEAN UserOptionSrat; ///< When set to TRUE, the SRAT data table is generated. - IN BOOLEAN UserOptionSlit; ///< When set to TRUE, the SLIT data table is generated. - IN BOOLEAN UserOptionWhea; ///< When set to TRUE, the WHEA data table is generated. - IN PLATFORM_LOW_POWER_PSTATE_MODES LowPowerPstateForProcHot; ///< Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto. - IN UINT32 PowerCeiling; ///< P-State Ceiling Enabling Deck - Max power milli-watts. - IN BOOLEAN ForcePstateIndependent; ///< P-State _PSD independence or dependence. - ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT} - IN BOOLEAN PStatesInHpcMode; ///< @BldCfgItem{BLDCFG_PSTATE_HPC_MODE} - IN UINT32 NumberOfIoApics; ///< Number of I/O APICs in the system - ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS} - IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules. - IN BOOLEAN ProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope - ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB} - IN CHAR8 ProcessorScopeName0; ///< OEM specific 1st character of processor scope name. - ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0} - IN CHAR8 ProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. - ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1} - IN UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output), - ///< essentially it enables function 1 of graphics device. - ///< @li 0 = HD Audio disable - ///< @li 1 = HD Audio enable - ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO} - IN UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is - ///< characteristic specific to display panel which used by platform design. - ///< @li 0 = ABM support disabled - ///< @li 1 = ABM support enabled - ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT} - IN UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP. - ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE} - IN UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control. - ///< If equal to 0 backlight not controlled by iGPU - ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL} -} PLATFORM_CONFIGURATION; - - -/********************************************************************** - * Structures for: AmdInitLate - **********************************************************************/ -#define PROC_VERSION_LENGTH 48 -#define MAX_DIMMS_PER_SOCKET 16 - -/* Interface Parameter Structures */ -/// DMI Type4 - Processor ID -typedef struct { - OUT UINT32 ProcIdLsd; ///< Lower half of 64b ID - OUT UINT32 ProcIdMsd; ///< Upper half of 64b ID -} TYPE4_PROC_ID; - -/// DMI Type 4 - Processor information -typedef struct { - OUT UINT8 T4ProcType; ///< CPU Type - OUT UINT8 T4ProcFamily; ///< Family 1 - OUT TYPE4_PROC_ID T4ProcId; ///< Id - OUT UINT8 T4Voltage; ///< Voltage - OUT UINT16 T4ExternalClock; ///< External clock - OUT UINT16 T4MaxSpeed; ///< Max speed - OUT UINT16 T4CurrentSpeed; ///< Current speed - OUT UINT8 T4Status; ///< Status - OUT UINT8 T4ProcUpgrade; ///< Up grade - OUT UINT8 T4CoreCount; ///< Core count - OUT UINT8 T4CoreEnabled; ///< Core Enable - OUT UINT8 T4ThreadCount; ///< Thread count - OUT UINT16 T4ProcCharacteristics; ///< Characteristics - OUT UINT16 T4ProcFamily2; ///< Family 2 - OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version -} TYPE4_DMI_INFO; - -/// DMI Type 7 - Cache information -typedef struct _TYPE7_DMI_INFO { - OUT UINT16 T7CacheCfg; ///< Cache cfg - OUT UINT16 T7MaxCacheSize; ///< Max size - OUT UINT16 T7InstallSize; ///< Install size - OUT UINT16 T7SupportedSramType; ///< Supported Sram Type - OUT UINT16 T7CurrentSramType; ///< Current type - OUT UINT8 T7CacheSpeed; ///< Speed - OUT UINT8 T7ErrorCorrectionType; ///< ECC type - OUT UINT8 T7SystemCacheType; ///< Cache type - OUT UINT8 T7Associativity; ///< Associativity -} TYPE7_DMI_INFO; - -/// DMI Type 16 offset 04h - Location -typedef enum { - OtherLocation = 0x01, ///< Assign 01 to Other - UnknownLocation, ///< Assign 02 to Unknown - SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard - IsaAddonCard, ///< Assign 04 to ISA add-on card - EisaAddonCard, ///< Assign 05 to EISA add-on card - PciAddonCard, ///< Assign 06 to PCI add-on card - McaAddonCard, ///< Assign 07 to MCA add-on card - PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card - ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card - NuBus, ///< Assign 0A to NuBus - Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card - Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card - Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card - Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card -} DMI_T16_LOCATION; - -/// DMI Type 16 offset 05h - Memory Error Correction -typedef enum { - OtherUse = 0x01, ///< Assign 01 to Other - UnknownUse, ///< Assign 02 to Unknown - SystemMemory, ///< Assign 03 to system memory - VideoMemory, ///< Assign 04 to video memory - FlashMemory, ///< Assign 05 to flash memory - NonvolatileRam, ///< Assign 06 to non-volatile RAM - CacheMemory ///< Assign 07 to cache memory -} DMI_T16_USE; - -/// DMI Type 16 offset 07h - Maximum Capacity -typedef enum { - Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other - Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown - Dmi16NoneErrCorrection, ///< Assign 03 to None - Dmi16Parity, ///< Assign 04 to parity - Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC - Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC - Dmi16Crc ///< Assign 07 to CRC -} DMI_T16_ERROR_CORRECTION; - -/// DMI Type 16 - Physical Memory Array -typedef struct { - OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array, - ///< whether on the system board or an add-in board. - OUT DMI_T16_USE Use; ///< Identifies the function for which the array - ///< is used. - OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or - ///< detection method supported by this memory array. - OUT UINT32 MaximumCapacity; ///< The maximum memory capacity, in kilobytes, - ///< for the array. - OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available - ///< for memory devices in this array. - OUT UINT64 ExtMaxCapacity; ///< The maximum memory capacity, in bytes, - ///< for this array. -} TYPE16_DMI_INFO; - -/// DMI Type 17 offset 0Eh - Form Factor -typedef enum { - OtherFormFactor = 0x01, ///< Assign 01 to Other - UnknowFormFactor, ///< Assign 02 to Unknown - SimmFormFactor, ///< Assign 03 to SIMM - SipFormFactor, ///< Assign 04 to SIP - ChipFormFactor, ///< Assign 05 to Chip - DipFormFactor, ///< Assign 06 to DIP - ZipFormFactor, ///< Assign 07 to ZIP - ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card - DimmFormFactorFormFactor, ///< Assign 09 to DIMM - TsopFormFactor, ///< Assign 10 to TSOP - RowOfChipsFormFactor, ///< Assign 11 to Row of chips - RimmFormFactor, ///< Assign 12 to RIMM - SodimmFormFactor, ///< Assign 13 to SODIMM - SrimmFormFactor, ///< Assign 14 to SRIMM - FbDimmFormFactor ///< Assign 15 to FB-DIMM -} DMI_T17_FORM_FACTOR; - -/// DMI Type 17 offset 12h - Memory Type -typedef enum { - OtherMemType = 0x01, ///< Assign 01 to Other - UnknownMemType, ///< Assign 02 to Unknown - DramMemType, ///< Assign 03 to DRAM - EdramMemType, ///< Assign 04 to EDRAM - VramMemType, ///< Assign 05 to VRAM - SramMemType, ///< Assign 06 to SRAM - RamMemType, ///< Assign 07 to RAM - RomMemType, ///< Assign 08 to ROM - FlashMemType, ///< Assign 09 to Flash - EepromMemType, ///< Assign 10 to EEPROM - FepromMemType, ///< Assign 11 to FEPROM - EpromMemType, ///< Assign 12 to EPROM - CdramMemType, ///< Assign 13 to CDRAM - ThreeDramMemType, ///< Assign 14 to 3DRAM - SdramMemType, ///< Assign 15 to SDRAM - SgramMemType, ///< Assign 16 to SGRAM - RdramMemType, ///< Assign 17 to RDRAM - DdrMemType, ///< Assign 18 to DDR - Ddr2MemType, ///< Assign 19 to DDR2 - Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM - Ddr3MemType = 0x18, ///< Assign 24 to DDR3 - Fbd2MemType ///< Assign 25 to FBD2 -} DMI_T17_MEMORY_TYPE; - -/// DMI Type 17 offset 13h - Type Detail -typedef struct { - OUT UINT16 Reserved1:1; ///< Reserved - OUT UINT16 Other:1; ///< Other - OUT UINT16 Unknown:1; ///< Unknown - OUT UINT16 FastPaged:1; ///< Fast-Paged - OUT UINT16 StaticColumn:1; ///< Static column - OUT UINT16 PseudoStatic:1; ///< Pseudo-static - OUT UINT16 Rambus:1; ///< RAMBUS - OUT UINT16 Synchronous:1; ///< Synchronous - OUT UINT16 Cmos:1; ///< CMOS - OUT UINT16 Edo:1; ///< EDO - OUT UINT16 WindowDram:1; ///< Window DRAM - OUT UINT16 CacheDram:1; ///< Cache Dram - OUT UINT16 NonVolatile:1; ///< Non-volatile - OUT UINT16 Reserved2:3; ///< Reserved -} DMI_T17_TYPE_DETAIL; - -/// DMI Type 17 - Memory Device -typedef struct { - OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. - OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. - OUT UINT16 MemorySize; ///< The size of the memory device. - OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. - OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of - ///< Memory Devices that must be populated with all devices of - ///< the same type and size, and the set to which this device belongs. - OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. - OUT CHAR8 BankLocator[10]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. - OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. - OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type - OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). - OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. - OUT CHAR8 SerialNumber[9]; ///< Serial Number. - OUT CHAR8 PartNumber[19]; ///< Part Number. - OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. - OUT UINT32 ExtSize; ///< Extended Size. - OUT UINT16 ConfigSpeed; ///< Configured memory clock speed -} TYPE17_DMI_INFO; - -/// Memory DMI Type 17 and 20 - for memory use -typedef struct { - OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. - OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. - OUT UINT16 MemorySize; ///< The size of the memory device. - OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. - OUT UINT8 DeviceLocator; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. - OUT UINT8 BankLocator; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. - OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). - OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. - OUT UINT8 SerialNumber[4]; ///< Serial Number. - OUT UINT8 PartNumber[18]; ///< Part Number. - OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. - OUT UINT32 ExtSize; ///< Extended Size. - OUT UINT8 Socket:3; ///< Socket ID - OUT UINT8 Channel:2; ///< Channel ID - OUT UINT8 Dimm:2; ///< DIMM ID - OUT UINT8 DimmPresent:1; ///< Dimm Present - OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range - ///< of memory mapped to the referenced Memory Device. - OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with - ///< the Memory Device structure to which this address - ///< range is mapped. - OUT UINT16 ConfigSpeed; ///< Configured memory clock speed - OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of - ///< memory mapped to the referenced Memory Device. - OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of - ///< a range of addresses mapped to the referenced Memory Device. -} MEM_DMI_INFO; - -/// DMI Type 19 - Memory Array Mapped Address -typedef struct { - OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, - ///< of a range of memory mapped to the - ///< specified physical memory array. - OUT UINT32 EndingAddr; ///< The physical ending address of the - ///< last kilobyte of a range of addresses - ///< mapped to the specified physical memory array. - OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated - ///< with the physical memory array to which this - ///< address range is mapped. - OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that - ///< form a single row of memory for the address - ///< partition defined by this structure. - OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of - ///< memory mapped to the specified Physical Memory Array. - OUT UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of - ///< memory mapped to the specified Physical Memory Array. -} TYPE19_DMI_INFO; - -///DMI Type 20 - Memory Device Mapped Address -typedef struct { - OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range - ///< of memory mapped to the referenced Memory Device. - OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with - ///< the Memory Device structure to which this address - ///< range is mapped. - OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with - ///< the Memory Device structure to which this address - ///< range is mapped. - OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated - ///< with the Memory Array Mapped Address structure to - ///< which this device address range is mapped. - OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory - ///< Device in a row of the address partition. - OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in - ///< an interleave. - OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the - ///< referenced Memory Device that are accessed in a - ///< single interleaved transfer. - OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of - ///< memory mapped to the referenced Memory Device. - OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of - ///< a range of addresses mapped to the referenced Memory Device. -} TYPE20_DMI_INFO; - -/// Collection of pointers to the DMI records -typedef struct { - OUT TYPE4_DMI_INFO T4[MAX_SOCKETS_SUPPORTED]; ///< Type 4 struc - OUT TYPE7_DMI_INFO T7L1[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 1 - OUT TYPE7_DMI_INFO T7L2[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 2 - OUT TYPE7_DMI_INFO T7L3[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 3 - OUT TYPE16_DMI_INFO T16; ///< Type 16 struc - OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc - OUT TYPE19_DMI_INFO T19; ///< Type 19 struc - OUT TYPE20_DMI_INFO T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc -} DMI_INFO; - -/********************************************************************** - * Interface call: AllocateExecutionCache - **********************************************************************/ -#define MAX_CACHE_REGIONS 3 - -/// AllocateExecutionCache sub param structure for cached memory region -typedef struct { - IN OUT UINT32 ExeCacheStartAddr; ///< Start address - IN OUT UINT32 ExeCacheSize; ///< Size -} EXECUTION_CACHE_REGION; - -/********************************************************************** - * Interface call: AmdGetAvailableExeCacheSize - **********************************************************************/ -/// Get available Cache remain -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - OUT UINT32 AvailableExeCacheSize; ///< Remain size -} AMD_GET_EXE_SIZE_PARAMS; - -AGESA_STATUS -AmdGetAvailableExeCacheSize ( - IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams - ); - -/// Selection type for core leveling -typedef enum { - CORE_LEVEL_LOWEST, ///< Level to lowest common denominator - CORE_LEVEL_TWO, ///< Level to 2 cores - CORE_LEVEL_POWER_OF_TWO, ///< Level to 1,2,4 or 8 - CORE_LEVEL_NONE, ///< Do no leveling - CORE_LEVEL_COMPUTE_UNIT, ///< Level cores to one core per compute unit - CORE_LEVEL_ONE, ///< Level to 1 core - CORE_LEVEL_THREE, ///< Level to 3 cores - CORE_LEVEL_FOUR, ///< Level to 4 cores - CORE_LEVEL_FIVE, ///< Level to 5 cores - CORE_LEVEL_SIX, ///< Level to 6 cores - CORE_LEVEL_SEVEN, ///< Level to 7 cores - CORE_LEVEL_EIGHT, ///< Level to 8 cores - CORE_LEVEL_NINE, ///< Level to 9 cores - CORE_LEVEL_TEN, ///< Level to 10 cores - CORE_LEVEL_ELEVEN, ///< Level to 11 cores - CORE_LEVEL_TWELVE, ///< Level to 12 cores - CORE_LEVEL_THIRTEEN, ///< Level to 13 cores - CORE_LEVEL_FOURTEEN, ///< Level to 14 cores - CORE_LEVEL_FIFTEEN, ///< Level to 15 cores - CoreLevelModeMax ///< Used for bounds checking -} CORE_LEVELING_TYPE; - - - - - -/************************************************************************ - * - * AGESA Basic Level interface structure definition and function prototypes - * - ***********************************************************************/ - -/********************************************************************** - * Interface call: AmdCreateStruct - **********************************************************************/ -AGESA_STATUS -AmdCreateStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ); - -/********************************************************************** - * Interface call: AmdReleaseStruct - **********************************************************************/ -AGESA_STATUS -AmdReleaseStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ); - -/********************************************************************** - * Interface call: AmdInitReset - **********************************************************************/ -/// AmdInitReset param structure -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region - IN AMD_HT_RESET_INTERFACE HtConfig; ///< The interface for Ht Recovery - IN FCH_RESET_INTERFACE FchInterface; ///< Interface for FCH configuration -} AMD_RESET_PARAMS; - -AGESA_STATUS -AmdInitReset ( - IN OUT AMD_RESET_PARAMS *ResetParams - ); - - -/********************************************************************** - * Interface call: AmdInitEarly - **********************************************************************/ -/// InitEarly param structure -/// -/// Provide defaults or customizations to each service performed in AmdInitEarly. -/// -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< Execution Map Interface - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN AMD_HT_INTERFACE HtConfig; ///< HyperTransport Interface - IN GNB_CONFIGURATION GnbConfig; ///< GNB configuration -} AMD_EARLY_PARAMS; - -AGESA_STATUS -AmdInitEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParams - ); - - -/********************************************************************** - * Interface call: AmdInitPost - **********************************************************************/ -/// AmdInitPost param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param -} AMD_POST_PARAMS; - -AGESA_STATUS -AmdInitPost ( - IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param - ); - - -/********************************************************************** - * Interface call: AmdInitEnv - **********************************************************************/ -/// AmdInitEnv param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< platform operational characteristics. - IN FCH_INTERFACE FchInterface; ///< FCH configuration -} AMD_ENV_PARAMS; - -AGESA_STATUS -AmdInitEnv ( - IN OUT AMD_ENV_PARAMS *EnvParams - ); - - -/********************************************************************** - * Interface call: AmdInitMid - **********************************************************************/ -/// AmdInitMid param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN FCH_INTERFACE FchInterface; ///< FCH configuration -} AMD_MID_PARAMS; - -AGESA_STATUS -AmdInitMid ( - IN OUT AMD_MID_PARAMS *MidParams - ); - - -/********************************************************************** - * Interface call: AmdInitLate - **********************************************************************/ -/// AmdInitLate param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *IvrsExclusionRangeList; ///< Pointer to array of exclusion ranges - OUT DMI_INFO *DmiTable; ///< DMI Interface - OUT VOID *AcpiPState; ///< Acpi Pstate SSDT Table - OUT VOID *AcpiSrat; ///< SRAT Table - OUT VOID *AcpiSlit; ///< SLIT Table - OUT VOID *AcpiWheaMce; ///< WHEA MCE Table - OUT VOID *AcpiWheaCmc; ///< WHEA CMC Table - OUT VOID *AcpiAlib; ///< ACPI SSDT table with ALIB implementation - OUT VOID *AcpiIvrs; ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table - OUT VOID *AcpiCrat; ///< Component Resource Affinity Table table - OUT VOID *AcpiCdit; ///< Component Locality Distance Information table -} AMD_LATE_PARAMS; - -AGESA_STATUS -AmdInitLate ( - IN OUT AMD_LATE_PARAMS *LateParams - ); - -/********************************************************************** - * Interface call: AmdInitRecovery - **********************************************************************/ -/// CPU Recovery Parameters -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. -} AMD_CPU_RECOVERY_PARAMS; - -/// AmdInitRecovery param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param - IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region. And the max cache region is 3 - IN AMD_CPU_RECOVERY_PARAMS CpuRecoveryParams; ///< Params for CPU related recovery init. -} AMD_RECOVERY_PARAMS; - -AGESA_STATUS -AmdInitRecovery ( - IN OUT AMD_RECOVERY_PARAMS *RecoveryParams - ); - -/********************************************************************** - * Interface call: AmdInitResume - **********************************************************************/ -/// AmdInitResume param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics - IN AMD_S3_PARAMS S3DataBlock; ///< Save state data -} AMD_RESUME_PARAMS; - -AGESA_STATUS -AmdInitResume ( - IN AMD_RESUME_PARAMS *ResumeParams - ); - - -/********************************************************************** - * Interface call: AmdS3LateRestore - **********************************************************************/ -/// AmdS3LateRestore param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - IN AMD_S3_PARAMS S3DataBlock; ///< Save state data -} AMD_S3LATE_PARAMS; - -AGESA_STATUS -AmdS3LateRestore ( - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ); - - -/********************************************************************** - * Interface call: AmdS3Save - **********************************************************************/ -/// AmdS3Save param structure -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - OUT AMD_S3_PARAMS S3DataBlock; ///< Standard header - IN FCH_INTERFACE FchInterface; ///< FCH configuration -} AMD_S3SAVE_PARAMS; - -AGESA_STATUS -AmdS3Save ( - IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams - ); - - -/********************************************************************** - * Interface call: AmdLateRunApTask - **********************************************************************/ -/** - * Entry point for AP tasking. - */ -AGESA_STATUS -AmdLateRunApTask ( - IN AP_EXE_PARAMS *AmdApExeParams -); - -// -// General Services API -// - -/********************************************************************** - * Interface service call: AmdGetApicId - **********************************************************************/ -/// Request the APIC ID of a particular core. - -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT8 Socket; ///< The Core's Socket. - IN UINT8 Core; ///< The Core id. - OUT BOOLEAN IsPresent; ///< The Core is present, and ApicAddress is valid. - OUT UINT8 ApicAddress; ///< The Core's APIC ID. -} AMD_APIC_PARAMS; - -/** - * Get a specified Core's APIC ID. - */ -AGESA_STATUS -AmdGetApicId ( - IN OUT AMD_APIC_PARAMS *AmdParamApic -); - -/********************************************************************** - * Interface service call: AmdGetPciAddress - **********************************************************************/ -/// Request the PCI Address of a Processor Module (that is, its Northbridge) - -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT8 Socket; ///< The Processor's socket - IN UINT8 Module; ///< The Module in that Processor - OUT BOOLEAN IsPresent; ///< The Core is present, and PciAddress is valid. - OUT PCI_ADDR PciAddress; ///< The Processor's PCI Config Space address (Function 0, Register 0) -} AMD_GET_PCI_PARAMS; - -/** - * Get Processor Module's PCI Config Space address. - */ -AGESA_STATUS -AmdGetPciAddress ( - IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci -); - -/********************************************************************** - * Interface service call: AmdIdentifyCore - **********************************************************************/ -/// Request the identity (Socket, Module, Core) of the current Processor Core - -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - OUT UINT8 Socket; ///< The current Core's Socket - OUT UINT8 Module; ///< The current Core's Processor Module - OUT UINT8 Core; ///< The current Core's core id. -} AMD_IDENTIFY_PARAMS; - -/** - * "Who am I" for the current running core. - */ -AGESA_STATUS -AmdIdentifyCore ( - IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify -); - -/********************************************************************** - * Interface service call: AmdReadEventLog - **********************************************************************/ -/// An Event Log Entry. -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - OUT UINT32 EventClass; ///< The severity of this event, matches AGESA_STATUS. - OUT UINT32 EventInfo; ///< The unique event identifier, zero means "no event". - OUT UINT32 DataParam1; ///< Data specific to the Event. - OUT UINT32 DataParam2; ///< Data specific to the Event. - OUT UINT32 DataParam3; ///< Data specific to the Event. - OUT UINT32 DataParam4; ///< Data specific to the Event. -} EVENT_PARAMS; - -/** - * Read an Event from the Event Log. - */ -AGESA_STATUS -AmdReadEventLog ( - IN EVENT_PARAMS *Event -); - -/********************************************************************** - * Interface service call: AmdIdentifyDimm - **********************************************************************/ -/// Request the identity of dimm from system address - -typedef struct { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN UINT64 MemoryAddress; ///< System Address that needs to be translated to dimm identification. - OUT UINT8 SocketId; ///< The socket on which the targeted address locates. - OUT UINT8 MemChannelId; ///< The channel on which the targeted address locates. - OUT UINT8 DimmId; ///< The dimm on which the targeted address locates. -} AMD_IDENTIFY_DIMM; - -/** - * Get the dimm identification for the address. - */ -AGESA_STATUS -AmdIdentifyDimm ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify -); - -AGESA_STATUS -AmdIdsRunApTaskLate ( - IN AP_EXE_PARAMS *AmdApExeParams - ); - - -#define AGESA_IDS_DFT_VAL 0xFFFF ///< Default value of every uninitlized NV item, the action for it will be ignored -#define AGESA_IDS_NV_END 0xFFFF ///< Flag specify end of option structure -/// WARNING: Don't change the comment below, it used as signature for script -/// AGESA IDS NV ID Definitions -typedef enum { - AGESA_IDS_EXT_ID_START = 0x0000,///< 0x0000 specify the start of external NV id - - AGESA_IDS_NV_UCODE, ///< 0x0001 Enable or disable microcode patching - - AGESA_IDS_NV_TARGET_PSTATE, ///< 0x0002 Set the P-state required to be activated - AGESA_IDS_NV_POSTPSTATE, ///< 0x0003 Set the P-state required to be activated through POST - - AGESA_IDS_NV_BANK_INTERLEAVE, ///< 0x0004 Enable or disable Bank Interleave - AGESA_IDS_NV_CHANNEL_INTERLEAVE, ///< 0x0005 Enable or disable Channel Interleave - AGESA_IDS_NV_NODE_INTERLEAVE, ///< 0x0006 Enable or disable Node Interleave - AGESA_IDS_NV_MEMHOLE, ///< 0x0007 Enables or disable memory hole - - AGESA_IDS_NV_SCRUB_REDIRECTION, ///< 0x0008 Enable or disable a write to dram with corrected data - AGESA_IDS_NV_DRAM_SCRUB, ///< 0x0009 Set the rate of background scrubbing for DRAM - AGESA_IDS_NV_DCACHE_SCRUB, ///< 0x000A Set the rate of background scrubbing for the DCache. - AGESA_IDS_NV_L2_SCRUB, ///< 0x000B Set the rate of background scrubbing for the L2 cache - AGESA_IDS_NV_L3_SCRUB, ///< 0x000C Set the rate of background scrubbing for the L3 cache - AGESA_IDS_NV_ICACHE_SCRUB, ///< 0x000D Set the rate of background scrubbing for the Icache - AGESA_IDS_NV_SYNC_ON_ECC_ERROR, ///< 0x000E Enable or disable the sync flood on un-correctable ECC error - AGESA_IDS_NV_ECC_SYMBOL_SIZE, ///< 0x000F Set ECC symbol size - - AGESA_IDS_NV_ALL_MEMCLKS, ///< 0x0010 Enable or disable all memory clocks enable - AGESA_IDS_NV_DCT_GANGING_MODE, ///< 0x0011 Set the Ganged mode - AGESA_IDS_NV_DRAM_BURST_LENGTH32, ///< 0x0012 Set the DRAM Burst Length 32 - AGESA_IDS_NV_MEMORY_POWER_DOWN, ///< 0x0013 Enable or disable Memory power down mode - AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, ///< 0x0014 Set the Memory power down mode - AGESA_IDS_NV_DLL_SHUT_DOWN, ///< 0x0015 Enable or disable DLLShutdown - AGESA_IDS_NV_ONLINE_SPARE, ///< 0x0016 Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap - - AGESA_IDS_NV_HT_ASSIST, ///< 0x0017 Enable or Disable HT Assist - AGESA_IDS_NV_ATMMODE, ///< 0x0018 Enable or Disable ATM mode - - AGESA_IDS_NV_HDTOUT, ///< 0x0019 Enable or disable HDTOUT feature - - AGESA_IDS_NV_HTLINKSOCKET, ///< 0x001A HT Link Socket - AGESA_IDS_NV_HTLINKPORT, ///< 0x001B HT Link Port - AGESA_IDS_NV_HTLINKFREQ, ///< 0x001C HT Link Frequency - AGESA_IDS_NV_HTLINKWIDTHIN, ///< 0x001D HT Link In Width - AGESA_IDS_NV_HTLINKWIDTHOUT, ///< 0x001E HT Link Out Width - - AGESA_IDS_NV_GNBHDAUDIOEN, ///< 0x001F Enable or disable GNB HD Audio - - AGESA_IDS_NV_CPB_EN, ///< 0x0020 Core Performance Boost - - AGESA_IDS_NV_HTC_EN, ///< 0x0021 HTC Enable - AGESA_IDS_NV_HTC_OVERRIDE, ///< 0x0022 HTC Override - AGESA_IDS_NV_HTC_PSTATE_LIMIT, ///< 0x0023 HTC P-state limit select - AGESA_IDS_NV_HTC_TEMP_HYS, ///< 0x0024 HTC Temperature Hysteresis - AGESA_IDS_NV_HTC_ACT_TEMP, ///< 0x0025 HTC Activation Temp - - AGESA_IDS_NV_POWER_POLICY, ///< 0x0026 Select Platform Power Policy - AGESA_IDS_EXT_ID_END, ///< 0x0027 specify the end of external NV ID -} IDS_EX_NV_ID; - - -#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1) - -#endif // _AGESA_H_ diff --git a/src/vendorcode/amd/agesa/f15/AMD.h b/src/vendorcode/amd/agesa/f15/AMD.h deleted file mode 100644 index dcbf0dc95d..0000000000 --- a/src/vendorcode/amd/agesa/f15/AMD.h +++ /dev/null @@ -1,478 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA core interface - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - -#ifndef _AMD_H_ -#define _AMD_H_ - -#define AGESA_REVISION "Arch2008" -#define AGESA_ID "AGESA" - -#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) -#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) -// -// -// AGESA Types and Definitions -// -// -#define LAST_ENTRY 0xFFFFFFFF -#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') -#define IOCF8 0xCF8 -#define IOCFC 0xCFC - -/// The return status for all AGESA public services. -/// -/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK -/// will have log entries with more detail. -/// -typedef enum { - AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged. - AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested. - ///< Not logged. - AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided. - ///< Example, memory address not installed, heap buffer handle not found. - ///< Not Logged. - // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available. - AGESA_ALERT, ///< An observed condition, but no loss of function. - ///< See log. Example, HT CRC. - AGESA_WARNING, ///< Possible or minor loss of function. See Log. - AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log. - AGESA_CRITICAL, ///< Continue boot only to notify user. See Log. - AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems - ///< may not be able to reliably produce log events. - AgesaStatusMax ///< Not a status, for limit checking. -} AGESA_STATUS; - -/// For checking whether a status is at or above the mandatory log level. -#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT - -/** - * Callout method to the host environment. - * - * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment. - * - * @param[in] Function The specific callout function being invoked. - * @param[in] FcnData Function specific data item. - * @param[in,out] ConfigPtr Reference to Callout params. - */ -typedef AGESA_STATUS (*CALLOUT_ENTRY) ( - IN UINT32 Function, - IN UINTN FcnData, - IN OUT VOID *ConfigPtr - ); - -typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr); -typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr); - -///This allocation type is used by the AmdCreateStruct entry point -typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. -} ALLOCATION_METHOD; - -/// These width descriptors are used by the library function, and others, to specify the data size -typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. - - AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. -} ACCESS_WIDTH; - -/// AGESA struct name -typedef enum { - // AGESA BASIC FUNCTIONS - AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle - AMD_CREATE_STRUCT, ///< AmdCreateStruct handle - AMD_INIT_EARLY, ///< AmdInitEarly entry point handle - AMD_INIT_ENV, ///< AmdInitEnv entry point handle - AMD_INIT_LATE, ///< AmdInitLate entry point handle - AMD_INIT_MID, ///< AmdInitMid entry point handle - AMD_INIT_POST, ///< AmdInitPost entry point handle - AMD_INIT_RESET, ///< AmdInitReset entry point handle - AMD_INIT_RESUME, ///< AmdInitResume entry point handle - AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle - AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle - AMD_S3_SAVE, ///< AmdS3Save entry point handle - AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle - AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle - AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle - AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle - AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle - AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle -} AGESA_STRUCT_NAME; - - /* ResetType constant values */ -#define WARM_RESET_WHENEVER 1 -#define COLD_RESET_WHENEVER 2 -#define WARM_RESET_IMMEDIATELY 3 -#define COLD_RESET_IMMEDIATELY 4 - - -// AGESA Structures - -/// The standard header for all AGESA services. -/// For internal AGESA naming conventions, see @ref amdconfigparamname . -typedef struct { - IN UINT32 ImageBasePtr; ///< The AGESA Image base address. - IN UINT32 Func; ///< The service desired - IN UINT32 AltImageBasePtr; ///< Alternate Image location - IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA - IN UINT8 HeapStatus; ///< For heap status from boot time slide. - IN UINT64 HeapBasePtr; ///< Location of the heap - IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use. -} AMD_CONFIG_PARAMS; - - -/// Create Struct Interface. -typedef struct { - IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header - IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init - IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation - IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only. - IN OUT VOID *NewStructPtr; ///< The struct for the service. - ///< The struct to init for ByHost allocation, - ///< the initialized struct on return. -} AMD_INTERFACE_PARAMS; - -#define FUNC_0 0 // bit-placed for PCI address creation -#define FUNC_1 1 -#define FUNC_2 2 -#define FUNC_3 3 -#define FUNC_4 4 -#define FUNC_5 5 -#define FUNC_6 6 -#define FUNC_7 7 - -/// AGESA Binary module header structure -typedef struct { - IN UINT32 Signature; ///< Binary Signature - IN CHAR8 CreatorID[8]; ///< 8 characters ID - IN CHAR8 Version[12]; ///< 12 characters version - IN UINT32 ModuleInfoOffset; ///< Offset of module - IN UINT32 EntryPointAddress; ///< Entry address - IN UINT32 ImageBase; ///< Image base - IN UINT32 RelocTableOffset; ///< Relocate Table offset - IN UINT32 ImageSize; ///< Size - IN UINT16 Checksum; ///< Checksum - IN UINT8 ImageType; ///< Type - IN UINT8 V_Reserved; ///< Reserved -} AMD_IMAGE_HEADER; -/// AGESA Binary module header structure -typedef struct _AMD_MODULE_HEADER { - IN UINT32 ModuleHeaderSignature; ///< Module signature - IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID - IN CHAR8 ModuleVersion[12]; ///< 12 characters version - IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher - IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link -} AMD_MODULE_HEADER; - -// AMD_CODE_HEADER Signatures. -#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '} -#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'} -#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'} - -/// AGESA_CODE_SIGNATURE -typedef struct { - IN CHAR8 Signature[8]; ///< code header Signature - IN CHAR8 ComponentName[8]; ///< 8 character name of the code module - IN CHAR8 Version[12]; ///< 12 character version string - IN CHAR8 TerminatorNull; ///< null terminated string - IN CHAR8 VerReserved[7]; ///< reserved space -} AMD_CODE_HEADER; - -/// Extended PCI address format -typedef struct { - IN OUT UINT32 Register:12; ///< Register offset - IN OUT UINT32 Function:3; ///< Function number - IN OUT UINT32 Device:5; ///< Device number - IN OUT UINT32 Bus:8; ///< Bus number - IN OUT UINT32 Segment:4; ///< Segment -} EXT_PCI_ADDR; - -/// Union type for PCI address -typedef union _PCI_ADDR { - IN UINT32 AddressValue; ///< Formal address - IN EXT_PCI_ADDR Address; ///< Extended address -} PCI_ADDR; - -// SBDFO - Segment Bus Device Function Offset -// 31:28 Segment (4-bits) -// 27:20 Bus (8-bits) -// 19:15 Device (5-bits) -// 14:12 Function(3-bits) -// 11:00 Offset (12-bits) - -#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ - (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off))) -#define ILLEGAL_SBDFO 0xFFFFFFFF - -/// CPUID data received registers format -typedef struct { - OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX - OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX - OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX - OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX -} CPUID_DATA; - -/// HT frequency for external callbacks -typedef enum { - HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks - HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks - HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks - HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks - HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks - HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks - HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks - HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks - HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks - HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks - HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks - HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks - HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks - HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks - HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks - HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks - HT_FREQUENCY_MAX ///< Limit check. -} HT_FREQUENCIES; -// The minimum HT3 frequency -#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M - -#ifndef BIT0 - #define BIT0 0x0000000000000001ull -#endif -#ifndef BIT1 - #define BIT1 0x0000000000000002ull -#endif -#ifndef BIT2 - #define BIT2 0x0000000000000004ull -#endif -#ifndef BIT3 - #define BIT3 0x0000000000000008ull -#endif -#ifndef BIT4 - #define BIT4 0x0000000000000010ull -#endif -#ifndef BIT5 - #define BIT5 0x0000000000000020ull -#endif -#ifndef BIT6 - #define BIT6 0x0000000000000040ull -#endif -#ifndef BIT7 - #define BIT7 0x0000000000000080ull -#endif -#ifndef BIT8 - #define BIT8 0x0000000000000100ull -#endif -#ifndef BIT9 - #define BIT9 0x0000000000000200ull -#endif -#ifndef BIT10 - #define BIT10 0x0000000000000400ull -#endif -#ifndef BIT11 - #define BIT11 0x0000000000000800ull -#endif -#ifndef BIT12 - #define BIT12 0x0000000000001000ull -#endif -#ifndef BIT13 - #define BIT13 0x0000000000002000ull -#endif -#ifndef BIT14 - #define BIT14 0x0000000000004000ull -#endif -#ifndef BIT15 - #define BIT15 0x0000000000008000ull -#endif -#ifndef BIT16 - #define BIT16 0x0000000000010000ull -#endif -#ifndef BIT17 - #define BIT17 0x0000000000020000ull -#endif -#ifndef BIT18 - #define BIT18 0x0000000000040000ull -#endif -#ifndef BIT19 - #define BIT19 0x0000000000080000ull -#endif -#ifndef BIT20 - #define BIT20 0x0000000000100000ull -#endif -#ifndef BIT21 - #define BIT21 0x0000000000200000ull -#endif -#ifndef BIT22 - #define BIT22 0x0000000000400000ull -#endif -#ifndef BIT23 - #define BIT23 0x0000000000800000ull -#endif -#ifndef BIT24 - #define BIT24 0x0000000001000000ull -#endif -#ifndef BIT25 - #define BIT25 0x0000000002000000ull -#endif -#ifndef BIT26 - #define BIT26 0x0000000004000000ull -#endif -#ifndef BIT27 - #define BIT27 0x0000000008000000ull -#endif -#ifndef BIT28 - #define BIT28 0x0000000010000000ull -#endif -#ifndef BIT29 - #define BIT29 0x0000000020000000ull -#endif -#ifndef BIT30 - #define BIT30 0x0000000040000000ull -#endif -#ifndef BIT31 - #define BIT31 0x0000000080000000ull -#endif -#ifndef BIT32 - #define BIT32 0x0000000100000000ull -#endif -#ifndef BIT33 - #define BIT33 0x0000000200000000ull -#endif -#ifndef BIT34 - #define BIT34 0x0000000400000000ull -#endif -#ifndef BIT35 - #define BIT35 0x0000000800000000ull -#endif -#ifndef BIT36 - #define BIT36 0x0000001000000000ull -#endif -#ifndef BIT37 - #define BIT37 0x0000002000000000ull -#endif -#ifndef BIT38 - #define BIT38 0x0000004000000000ull -#endif -#ifndef BIT39 - #define BIT39 0x0000008000000000ull -#endif -#ifndef BIT40 - #define BIT40 0x0000010000000000ull -#endif -#ifndef BIT41 - #define BIT41 0x0000020000000000ull -#endif -#ifndef BIT42 - #define BIT42 0x0000040000000000ull -#endif -#ifndef BIT43 - #define BIT43 0x0000080000000000ull -#endif -#ifndef BIT44 - #define BIT44 0x0000100000000000ull -#endif -#ifndef BIT45 - #define BIT45 0x0000200000000000ull -#endif -#ifndef BIT46 - #define BIT46 0x0000400000000000ull -#endif -#ifndef BIT47 - #define BIT47 0x0000800000000000ull -#endif -#ifndef BIT48 - #define BIT48 0x0001000000000000ull -#endif -#ifndef BIT49 - #define BIT49 0x0002000000000000ull -#endif -#ifndef BIT50 - #define BIT50 0x0004000000000000ull -#endif -#ifndef BIT51 - #define BIT51 0x0008000000000000ull -#endif -#ifndef BIT52 - #define BIT52 0x0010000000000000ull -#endif -#ifndef BIT53 - #define BIT53 0x0020000000000000ull -#endif -#ifndef BIT54 - #define BIT54 0x0040000000000000ull -#endif -#ifndef BIT55 - #define BIT55 0x0080000000000000ull -#endif -#ifndef BIT56 - #define BIT56 0x0100000000000000ull -#endif -#ifndef BIT57 - #define BIT57 0x0200000000000000ull -#endif -#ifndef BIT58 - #define BIT58 0x0400000000000000ull -#endif -#ifndef BIT59 - #define BIT59 0x0800000000000000ull -#endif -#ifndef BIT60 - #define BIT60 0x1000000000000000ull -#endif -#ifndef BIT61 - #define BIT61 0x2000000000000000ull -#endif -#ifndef BIT62 - #define BIT62 0x4000000000000000ull -#endif -#ifndef BIT63 - #define BIT63 0x8000000000000000ull -#endif - -#endif // _AMD_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionApmInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionApmInstall.h deleted file mode 100644 index 4b3b9a8a25..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionApmInstall.h +++ /dev/null @@ -1,87 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Application Power Management (APM). - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 54493 $ @e \$Date: 2011-06-08 15:21:06 -0600 (Wed, 08 Jun 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_APM_INSTALL_H_ -#define _OPTION_APM_INSTALL_H_ - -#include "cpuApm.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_APM_FEAT -#define F15_APM_SUPPORT - -#if OPTION_CPU_APM == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - // Family 15h - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_KM == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm; - #undef OPTION_CPU_APM_FEAT - #define OPTION_CPU_APM_FEAT &CpuFeatureApm, - extern CONST APM_FAMILY_SERVICES ROMDATA F15ApmSupport; - #undef F15_APM_SUPPORT - #define F15_APM_SUPPORT {AMD_FAMILY_15_OR | AMD_FAMILY_15_KM, &F15ApmSupport}, - #endif - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA ApmFamilyServiceArray[] = -{ - F15_APM_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA ApmFamilyServiceTable = -{ - (sizeof (ApmFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &ApmFamilyServiceArray[0] -}; - -#endif // _OPTION_APM_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionC6Install.h b/src/vendorcode/amd/agesa/f15/Config/OptionC6Install.h deleted file mode 100644 index 2e944bf65a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionC6Install.h +++ /dev/null @@ -1,164 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: C6 C-state - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_C6_STATE_INSTALL_H_ -#define _OPTION_C6_STATE_INSTALL_H_ - -#include "cpuC6State.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_C6_STATE_FEAT -#define F12_C6_STATE_SUPPORT -#define F14_ON_C6_STATE_SUPPORT -#define F15_OR_C6_STATE_SUPPORT - -#if OPTION_C6_STATE == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - #if OPTION_FAMILY12H_LN == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; - #undef OPTION_C6_STATE_FEAT - #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, - extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support; - #undef F12_C6_STATE_SUPPORT - #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support}, - - #if OPTION_EARLY_SAMPLES == TRUE - extern F_F12_ES_C6_INIT F12C6A0Workaround; - - CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support = - { - F12C6A0Workaround - }; - #else - CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support = - { - (PF_F12_ES_C6_INIT) CommonVoid - }; - #endif - - #endif - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - #if (OPTION_FAMILY14H_ON == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; - #undef OPTION_C6_STATE_FEAT - #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, - extern CONST C6_FAMILY_SERVICES ROMDATA F14OnC6Support; - #undef F14_ON_C6_STATE_SUPPORT - #define F14_ON_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14OnC6Support}, - - #if (OPTION_EARLY_SAMPLES == TRUE) - extern F_F14_ON_ES_IS_C6_SUPPORTED F14IsC6DisabledEarlySample; - extern F_F14_ON_ES_C6_INIT F14C6A0Workaround; - - CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support = - { - F14IsC6DisabledEarlySample, - F14C6A0Workaround - }; - #else - CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support = - { - (PF_F14_ON_ES_IS_C6_SUPPORTED) CommonVoid, - (PF_F14_ON_ES_C6_INIT) CommonVoid - }; - #endif - #endif - - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_FAMILY15H_OR == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; - #undef OPTION_C6_STATE_FEAT - #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, - extern CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support; - #undef F15_OR_C6_STATE_SUPPORT - #define F15_OR_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrC6Support}, - - #if (OPTION_EARLY_SAMPLES == TRUE) - extern F_F15_OR_ES_IS_C6_SUPPORTED F15OrIsC6DisabledEarlySample; - - CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support = - { - F15OrIsC6DisabledEarlySample - }; - #else - CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support = - { - (PF_F15_OR_ES_IS_C6_SUPPORTED) CommonVoid - }; - #endif - #endif - - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] = -{ - F12_C6_STATE_SUPPORT - F14_ON_C6_STATE_SUPPORT - F15_OR_C6_STATE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable = -{ - (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &C6FamilyServiceArray[0] -}; - -#endif // _OPTION_C6_STATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionCpbInstall.h deleted file mode 100644 index d47619baa7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionCpbInstall.h +++ /dev/null @@ -1,170 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Core Performance Boost - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 46389 $ @e \$Date: 2011-01-31 20:22:49 -0700 (Mon, 31 Jan 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_CPB_INSTALL_H_ -#define _OPTION_CPB_INSTALL_H_ - -#include "cpuCpb.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPB_FEAT -#define F10_CPB_SUPPORT -#define F12_CPB_SUPPORT -#define F14_ON_CPB_SUPPORT -#define F15_OR_CPB_SUPPORT - -#if OPTION_CPB == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - // Family 10h - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_PH == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport; - #undef F10_CPB_SUPPORT - #define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport}, - #endif - #endif - #endif - - // Family 12h - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - #if OPTION_FAMILY12H_LN == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport; - #undef F12_CPB_SUPPORT - #define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport}, - #if OPTION_EARLY_SAMPLES == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) - extern F_F12_ES_CPB_INIT F12LnA1CpbHook; - - CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport = - { - F12LnA1CpbHook - }; - #else - CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport = - { - (PF_F12_ES_CPB_INIT) CommonVoid - }; - #endif - #else - CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport = - { - (PF_F12_ES_CPB_INIT) CommonVoid - }; - #endif - #endif - #endif - #endif - - // Family 14h - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - #if OPTION_FAMILY14H_ON == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport; - #undef F14_ON_CPB_SUPPORT - #define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport}, - #endif - #endif - #endif - - // Family 15h - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_FAMILY15H_OR == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; - #undef OPTION_CPB_FEAT - #define OPTION_CPB_FEAT &CpuFeatureCpb, - extern CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport; - #undef F15_OR_CPB_SUPPORT - #define F15_OR_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15OrCpbSupport}, - - #if OPTION_EARLY_SAMPLES == TRUE - extern F_F15_OR_ES_IS_CPB_SUPPORTED F15OrIsCpbDisabledEarlySample; - - CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport = - { - F15OrIsCpbDisabledEarlySample - }; - #else - CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport = - { - (PF_F15_OR_ES_IS_CPB_SUPPORTED) CommonVoid - }; - #endif - #endif - #endif - #endif - - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] = -{ - F10_CPB_SUPPORT - F12_CPB_SUPPORT - F14_ON_CPB_SUPPORT - F15_OR_CPB_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable = -{ - (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CpbFamilyServiceArray[0] -}; - -#endif // _OPTION_CPB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionCpuCacheFlushOnHaltInstall.h deleted file mode 100644 index 35362ffdb7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionCpuCacheFlushOnHaltInstall.h +++ /dev/null @@ -1,126 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: CPU Cache Flush On Halt - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 56186 $ @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ -#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ - -#include "cpuPostInit.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT -#define F10_BL_CPU_CFOH_SUPPORT -#define F10_DA_CPU_CFOH_SUPPORT -#define F10_CPU_CFOH_SUPPORT -#define F15_OR_CPU_CFOH_SUPPORT -#define F15_TN_CPU_CFOH_SUPPORT - -#if OPTION_CPU_CFOH == TRUE - #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt; - - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT - #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt, - - #if OPTION_FAMILY10H_BL == TRUE - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt; - #undef F10_BL_CPU_CFOH_SUPPORT - #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt}, - #endif - - #if OPTION_FAMILY10H_DA == TRUE - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt; - #undef F10_DA_CPU_CFOH_SUPPORT - #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt}, - #endif - - #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt; - #undef F10_CPU_CFOH_SUPPORT - #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT - #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt, - - #if OPTION_FAMILY15H_OR == TRUE - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt; - #undef F15_OR_CPU_CFOH_SUPPORT - #define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15OrCacheFlushOnHalt}, - #endif - - #if OPTION_FAMILY15H_TN == TRUE - extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt; - #undef F15_TN_CPU_CFOH_SUPPORT - #define F15_TN_CPU_CFOH_SUPPORT {AMD_FAMILY_15_TN, &F15TnCacheFlushOnHalt}, - #endif - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] = -{ - F10_BL_CPU_CFOH_SUPPORT - F10_DA_CPU_CFOH_SUPPORT - F10_CPU_CFOH_SUPPORT - F15_OR_CPU_CFOH_SUPPORT - F15_TN_CPU_CFOH_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable = -{ - (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CacheFlushOnHaltFamilyServiceArray[0] -}; - -#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionCpuCoreLevelingInstall.h deleted file mode 100644 index d0743ecc3c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionCpuCoreLevelingInstall.h +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: CPU Core Leveling - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 56186 $ @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_ -#define _OPTION_CPU_CORELEVELING_INSTALL_H_ - - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_CORE_LEVELING_FEAT -#define F10_REVE_CPU_CORELEVELING_SUPPORT -#define F10_REVD_CPU_CORELEVELING_SUPPORT -#define F10_REVC_CPU_CORELEVELING_SUPPORT -#define F15_OR_CPU_CORELEVELING_SUPPORT -#define F15_TN_CPU_CORELEVELING_SUPPORT - -#if OPTION_CPU_CORELEVLING == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling; - - // Family 10h - #if OPTION_FAMILY10H == TRUE - #undef OPTION_CPU_CORE_LEVELING_FEAT - #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling, - #if OPTION_FAMILY10H_HY == TRUE - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling; - #undef F10_REVD_CPU_CORELEVELING_SUPPORT - #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling}, - #endif - - #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling; - #undef F10_REVC_CPU_CORELEVELING_SUPPORT - #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling}, - #endif - - #if (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling; - #undef F10_REVE_CPU_CORELEVELING_SUPPORT - #define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling}, - #endif - #endif - // Family 15h - #if OPTION_FAMILY15H == TRUE - #undef OPTION_CPU_CORE_LEVELING_FEAT - #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling, - - #if (OPTION_FAMILY15H_OR == TRUE) - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling; - #undef F15_OR_CPU_CORELEVELING_SUPPORT - #define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling}, - #endif - #if (OPTION_FAMILY15H_TN == TRUE) - extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling; - #undef F15_TN_CPU_CORELEVELING_SUPPORT - #define F15_TN_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_TN, &F15TnCoreLeveling}, - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] = -{ - F15_TN_CPU_CORELEVELING_SUPPORT - F15_OR_CPU_CORELEVELING_SUPPORT - F10_REVE_CPU_CORELEVELING_SUPPORT - F10_REVD_CPU_CORELEVELING_SUPPORT - F10_REVC_CPU_CORELEVELING_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable = -{ - (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CoreLevelingFamilyServiceArray[0] -}; - -#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionCpuFamiliesInstall.h deleted file mode 100644 index 2aafe65910..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionCpuFamiliesInstall.h +++ /dev/null @@ -1,382 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of all appropriate CPU family specific support. - * - * This file generates the defaults tables for all family specific - * combinations. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 50628 $ @e \$Date: 2011-04-12 15:18:38 -0600 (Tue, 12 Apr 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -/* Default all CPU Specific Service members to off. They - will be enabled as needed by cross referencing families - with entry points in the family / model install files. */ -#define GET_PSTATE_POWER FALSE -#define GET_PSTATE_FREQ FALSE -#define DISABLE_PSTATE FALSE -#define TRANSITION_PSTATE FALSE -#define PROC_IDD_MAX FALSE -#define GET_TSC_RATE FALSE -#define PSTATE_TRANSITION_LATENCY FALSE -#define GET_PSTATE_REGISTER_INFO FALSE -#define GET_PSTATE_MAX_STATE FALSE -#define SET_PSTATE_LEVELING_REG FALSE -#define GET_NB_FREQ FALSE -#define GET_NB_IDD_MAX FALSE -#define IS_NBCOF_INIT_NEEDED FALSE -#define AP_INITIAL_LAUNCH FALSE -#define GET_AP_MAILBOX_FROM_HW FALSE -#define SET_AP_CORE_NUMBER FALSE -#define GET_AP_CORE_NUMBER FALSE -#define TRANSFER_AP_CORE_NUMBER FALSE -#define ID_POSITION_INITIAL_APICID FALSE -#define SAVE_FEATURES FALSE -#define WRITE_FEATURES FALSE -#define SET_DOWN_CORE_REG FALSE -#define SET_WARM_RESET_FLAG FALSE -#define GET_WARM_RESET_FLAG FALSE -#define USES_REGISTER_TABLES FALSE -#define BASE_FAMILY_PCI FALSE -#define MODEL_SPECIFIC_PCI FALSE -#define BASE_FAMILY_MSR FALSE -#define MODEL_SPECIFIC_MSR FALSE -#define BRAND_STRING1 FALSE -#define BRAND_STRING2 FALSE -#define BASE_FAMILY_HT_PCI FALSE -#define MODEL_SPECIFIC_HT_PCI FALSE -#define BASE_FAMILY_WORKAROUNDS FALSE -#define GET_PATCHES FALSE -#define GET_PATCHES_EQUIVALENCE_TABLE FALSE -#define GET_CACHE_INFO FALSE -#define GET_SYSTEM_PM_TABLE FALSE -#define GET_WHEA_INIT FALSE -#define GET_CFOH_REG FALSE -#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE -#define IS_NB_PSTATE_ENABLED FALSE - -/* - * Pull in family specific services based on entry point - */ -#if AGESA_ENTRY_INIT_RESET == TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE - #undef GET_AP_MAILBOX_FROM_HW - #define GET_AP_MAILBOX_FROM_HW TRUE - #undef SET_WARM_RESET_FLAG - #define SET_WARM_RESET_FLAG TRUE - #undef GET_WARM_RESET_FLAG - #define GET_WARM_RESET_FLAG TRUE - #undef GET_CACHE_INFO - #define GET_CACHE_INFO TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef TRANSFER_AP_CORE_NUMBER - #define TRANSFER_AP_CORE_NUMBER TRUE -#endif - -#if AGESA_ENTRY_INIT_EARLY == TRUE - #undef TRANSITION_PSTATE - #define TRANSITION_PSTATE TRUE - #undef DISABLE_PSTATE - #define DISABLE_PSTATE TRUE - #undef PROC_IDD_MAX - #define PROC_IDD_MAX TRUE - #undef GET_TSC_RATE - #define GET_TSC_RATE TRUE - #undef GET_NB_FREQ - #define GET_NB_FREQ TRUE - #undef GET_NB_IDD_MAX - #define GET_NB_IDD_MAX TRUE - #undef IS_NBCOF_INIT_NEEDED - #define IS_NBCOF_INIT_NEEDED TRUE - #undef AP_INITIAL_LAUNCH - #define AP_INITIAL_LAUNCH TRUE - #undef GET_AP_MAILBOX_FROM_HW - #define GET_AP_MAILBOX_FROM_HW TRUE - #undef SET_AP_CORE_NUMBER - #define SET_AP_CORE_NUMBER TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef TRANSFER_AP_CORE_NUMBER - #define TRANSFER_AP_CORE_NUMBER TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE - #undef SET_DOWN_CORE_REG - #define SET_DOWN_CORE_REG TRUE - #undef SET_WARM_RESET_FLAG - #define SET_WARM_RESET_FLAG TRUE - #undef GET_WARM_RESET_FLAG - #define GET_WARM_RESET_FLAG TRUE - #undef USES_REGISTER_TABLES - #define USES_REGISTER_TABLES TRUE - #undef BASE_FAMILY_PCI - #define BASE_FAMILY_PCI TRUE - #undef MODEL_SPECIFIC_PCI - #define MODEL_SPECIFIC_PCI TRUE - #undef BASE_FAMILY_MSR - #define BASE_FAMILY_MSR TRUE - #undef MODEL_SPECIFIC_MSR - #define MODEL_SPECIFIC_MSR TRUE - #undef BRAND_STRING1 - #define BRAND_STRING1 TRUE - #undef BRAND_STRING2 - #define BRAND_STRING2 TRUE - #undef BASE_FAMILY_HT_PCI - #define BASE_FAMILY_HT_PCI TRUE - #undef MODEL_SPECIFIC_HT_PCI - #define MODEL_SPECIFIC_HT_PCI TRUE - #undef BASE_FAMILY_WORKAROUNDS - #define BASE_FAMILY_WORKAROUNDS TRUE - #undef GET_PATCHES - #define GET_PATCHES TRUE - #undef GET_PATCHES_EQUIVALENCE_TABLE - #define GET_PATCHES_EQUIVALENCE_TABLE TRUE - #undef GET_SYSTEM_PM_TABLE - #define GET_SYSTEM_PM_TABLE TRUE - #undef GET_CACHE_INFO - #define GET_CACHE_INFO TRUE - #undef GET_PLATFORM_TYPE_SPECIFIC_INFO - #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE - #undef IS_NB_PSTATE_ENABLED - #define IS_NB_PSTATE_ENABLED TRUE -#endif - -#if AGESA_ENTRY_INIT_POST == TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE - #undef GET_PSTATE_POWER - #define GET_PSTATE_POWER TRUE - #undef GET_PSTATE_FREQ - #define GET_PSTATE_FREQ TRUE - #undef TRANSITION_PSTATE - #define TRANSITION_PSTATE TRUE - #undef PROC_IDD_MAX - #define PROC_IDD_MAX TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef GET_PSTATE_REGISTER_INFO - #define GET_PSTATE_REGISTER_INFO TRUE - #undef GET_PSTATE_MAX_STATE - #define GET_PSTATE_MAX_STATE TRUE - #undef SET_PSTATE_LEVELING_REG - #define SET_PSTATE_LEVELING_REG TRUE - #undef SET_WARM_RESET_FLAG - #define SET_WARM_RESET_FLAG TRUE - #undef GET_WARM_RESET_FLAG - #define GET_WARM_RESET_FLAG TRUE - #undef SAVE_FEATURES - #define SAVE_FEATURES TRUE - #undef WRITE_FEATURES - #define WRITE_FEATURES TRUE - #undef GET_CFOH_REG - #define GET_CFOH_REG TRUE - #undef IS_NB_PSTATE_ENABLED - #define IS_NB_PSTATE_ENABLED TRUE -#endif - -#if AGESA_ENTRY_INIT_ENV == TRUE -#endif - -#if AGESA_ENTRY_INIT_MID == TRUE -#endif - -#if AGESA_ENTRY_INIT_LATE == TRUE - #undef GET_AP_CORE_NUMBER - #define GET_AP_CORE_NUMBER TRUE - #undef GET_PSTATE_FREQ - #define GET_PSTATE_FREQ TRUE - #undef TRANSITION_PSTATE - #define TRANSITION_PSTATE TRUE - #undef PSTATE_TRANSITION_LATENCY - #define PSTATE_TRANSITION_LATENCY TRUE - #undef GET_WHEA_INIT - #define GET_WHEA_INIT TRUE - #undef GET_PLATFORM_TYPE_SPECIFIC_INFO - #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE - #undef GET_TSC_RATE - #define GET_TSC_RATE TRUE - #undef BRAND_STRING1 - #define BRAND_STRING1 TRUE - #undef BRAND_STRING2 - #define BRAND_STRING2 TRUE -#endif - -#if AGESA_ENTRY_INIT_S3SAVE == TRUE -#endif - -#if AGESA_ENTRY_INIT_RESUME == TRUE - #undef GET_CFOH_REG - #define GET_CFOH_REG TRUE -#endif - -#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE -#endif - -#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - #undef ID_POSITION_INITIAL_APICID - #define ID_POSITION_INITIAL_APICID TRUE -#endif - -/* - * Initialize PCI MMIO mask to 0 - */ -#define FAMILY_MMIO_BASE_MASK (0ull) - - -/* - * Initialize all families to disabled - */ -#define OPT_F10_TABLE -#define OPT_F12_TABLE -#define OPT_F14_TABLE -#define OPT_F15_TABLE - -#define OPT_F10_ID_TABLE -#define OPT_F12_ID_TABLE -#define OPT_F14_ID_TABLE -#define OPT_F15_ID_TABLE - - -/* - * Install family specific support - */ -#if (OPTION_FAMILY10H == TRUE) - #include "OptionFamily10hInstall.h" -#endif - -#if (OPTION_FAMILY12H == TRUE) - #include "OptionFamily12hInstall.h" -#endif - -#if (OPTION_FAMILY14H == TRUE) - #include "OptionFamily14hInstall.h" -#endif - -#if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_TN == TRUE) || (OPTION_FAMILY15H_KM == TRUE) - #include "OptionFamily15hInstall.h" -#endif - - -/* - * Process PCI MMIO mask - */ - -// If size is 0, but base is not, break the build. -#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0) - #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 -#endif - -// If base is 0, but size is not, break the build. -#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0) - #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater -#endif - -#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0) - // Both are non-zero, begin further processing. - - // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB. - #if (CFG_PCI_MMIO_BASE < 0x800000) - #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater - #endif - - // Break the build if the address is too high for the enabled families. - #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0) - #error BLDCFG: Invalid PCI MMIO base address for the installed CPU families - #endif - - // If the size parameter is not valid, break the build. - #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16) - #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256) - #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 - #endif - #endif - - #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1) - // If the base is not aligned according to size, break the build. - #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0) - #error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size - #endif - #undef PCI_MMIO_ALIGNMENT -#endif - -/* - * Process sockets / modules - */ -#ifndef ADVCFG_PLATFORM_SOCKETS - #error BLDOPT Set Family supported sockets. -#endif -#ifndef ADVCFG_PLATFORM_MODULES - #error BLDOPT Set Family supported modules. -#endif - -CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration = -{ - ADVCFG_PLATFORM_SOCKETS, - ADVCFG_PLATFORM_MODULES -}; - -/* - * Instantiate global data needed for processor identification - */ -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] = -{ - OPT_F10_TABLE - OPT_F12_TABLE - OPT_F14_TABLE - OPT_F15_TABLE -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable = -{ - (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &CpuSupportedFamiliesArray[0] -}; - - -CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] = -{ - OPT_F10_ID_TABLE - OPT_F12_ID_TABLE - OPT_F14_ID_TABLE - OPT_F15_ID_TABLE -}; - -CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable = -{ - (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)), - CpuSupportedFamilyIdArray -}; diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionCpuFeaturesInstall.h deleted file mode 100644 index 44df5ba631..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionCpuFeaturesInstall.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of multiple CPU features. - * - * Aggregates enabled CPU features into a list for the dispatcher to process. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 54493 $ @e \$Date: 2011-06-08 15:21:06 -0600 (Wed, 08 Jun 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_CPU_FEATURES_INSTALL_H_ -#define _OPTION_CPU_FEATURES_INSTALL_H_ - -#include "OptionHwC1eInstall.h" -#include "OptionMsgBasedC1eInstall.h" -#include "OptionSwC1eInstall.h" -#include "OptionL3FeaturesInstall.h" -#include "OptionCpuCoreLevelingInstall.h" -#include "OptionIoCstateInstall.h" -#include "OptionC6Install.h" -#include "OptionCpbInstall.h" -#include "OptionCpuCacheFlushOnHaltInstall.h" -#include "OptionPstateHpcModeInstall.h" -#include "OptionLowPwrPstateInstall.h" -#include "OptionApmInstall.h" -#include "OptionPreserveMailboxInstall.h" - -CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] = -{ - OPTION_HW_C1E_FEAT - OPTION_MSG_BASED_C1E_FEAT - OPTION_SW_C1E_FEAT - OPTION_L3_FEAT - OPTION_CPU_CORE_LEVELING_FEAT - OPTION_IO_CSTATE_FEAT - OPTION_C6_STATE_FEAT - OPTION_CPB_FEAT - OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT - OPTION_CPU_PSTATE_HPC_MODE_FEAT // this function should be run before low power pstate for prochot - OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT // this function should be run before creating ACPI objects and after Pstate initialization - OPTION_CPU_APM_FEAT - OPTION_PRESERVE_MAILBOX_FEAT - NULL -}; - - -#endif // _OPTION_CPU_FEATURES_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionDmiInstall.h deleted file mode 100644 index b09a58ff0b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionDmiInstall.h +++ /dev/null @@ -1,213 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: DMI - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_DMI_INSTALL_H_ -#define _OPTION_DMI_INSTALL_H_ - -#include "cpuLateInit.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_DMI - #error BLDOPT: Option not defined: "OPTION_DMI" - #endif - #if OPTION_DMI == TRUE - OPTION_DMI_FEATURE GetDmiInfoMain; - OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer; - #define USER_DMI_OPTION &GetDmiInfoMain - #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer - - // This additional check keeps AP launch routines from being unnecessarily included - // in single socket systems. - #if OPTION_MULTISOCKET == TRUE - #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, - #else - #define CPU_DMI_AP_GET_TYPE4_TYPE7 - #endif - - // Family 10 - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - extern PROC_FAMILY_TABLE ProcFamily10DmiTable; - #define FAM10_DMI_SUPPORT FAM10_ENABLED, - #define FAM10_DMI_TABLE &ProcFamily10DmiTable, - #else - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #endif - #else - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #endif - - // Family 12 - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - extern PROC_FAMILY_TABLE ProcFamily12DmiTable; - #define FAM12_DMI_SUPPORT FAM12_ENABLED, - #define FAM12_DMI_TABLE &ProcFamily12DmiTable, - #else - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #endif - #else - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #endif - - // Family 14 - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - extern PROC_FAMILY_TABLE ProcFamily14DmiTable; - #define FAM14_DMI_SUPPORT FAM14_ENABLED, - #define FAM14_DMI_TABLE &ProcFamily14DmiTable, - #else - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #endif - #else - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #endif - - // Family 15 - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - extern PROC_FAMILY_TABLE ProcFamily15OrDmiTable; - #define FAM15_OR_DMI_SUPPORT FAM15_OR_ENABLED, - #define FAM15_OR_DMI_TABLE &ProcFamily15OrDmiTable, - #else - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #endif - #if OPTION_FAMILY15H_TN == TRUE - extern PROC_FAMILY_TABLE ProcFamily15TnDmiTable; - #define FAM15_TN_DMI_SUPPORT FAM15_TN_ENABLED, - #define FAM15_TN_DMI_TABLE &ProcFamily15TnDmiTable, - #else - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #endif - #else - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #endif - #else - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #endif - - #else - OPTION_DMI_FEATURE GetDmiInfoStub; - OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; - #define USER_DMI_OPTION GetDmiInfoStub - #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #define CPU_DMI_AP_GET_TYPE4_TYPE7 - #endif -#else - OPTION_DMI_FEATURE GetDmiInfoStub; - OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; - #define USER_DMI_OPTION GetDmiInfoStub - #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub - #define FAM10_DMI_SUPPORT - #define FAM10_DMI_TABLE - #define FAM12_DMI_SUPPORT - #define FAM12_DMI_TABLE - #define FAM14_DMI_SUPPORT - #define FAM14_DMI_TABLE - #define FAM15_OR_DMI_SUPPORT - #define FAM15_OR_DMI_TABLE - #define FAM15_TN_DMI_SUPPORT - #define FAM15_TN_DMI_TABLE - #define CPU_DMI_AP_GET_TYPE4_TYPE7 -#endif - -/// DMI supported families enum -typedef enum { - FAM10_DMI_SUPPORT ///< Conditionally define F10 support - FAM12_DMI_SUPPORT ///< Conditionally define F12 support - FAM14_DMI_SUPPORT ///< Conditionally define F14 support - FAM15_OR_DMI_SUPPORT ///< Conditionally define F15 OR support - FAM15_TN_DMI_SUPPORT ///< Conditionally define F15 TN support - NUM_DMI_FAMILIES ///< Number of installed families -} AGESA_DMI_SUPPORTED_FAM; - -/* Declare the Family List. An array of pointers to tables that each describe a family */ -CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = { - FAM10_DMI_TABLE - FAM12_DMI_TABLE - FAM14_DMI_TABLE - FAM15_OR_DMI_TABLE - FAM15_TN_DMI_TABLE - NULL -}; - -/* Declare the instance of the DMI option configuration structure */ -CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = { - DMI_STRUCT_VERSION, - USER_DMI_OPTION, - USER_DMI_RELEASE_BUFFER, - NUM_DMI_FAMILIES, - (VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl -}; - -#endif // _OPTION_DMI_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionFamily10hInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionFamily10hInstall.h deleted file mode 100644 index cb30a7fb56..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionFamily10hInstall.h +++ /dev/null @@ -1,2056 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of family 10h support - * - * This file generates the defaults tables for family 10h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 60726 $ @e \$Date: 2011-10-20 17:08:02 -0600 (Thu, 20 Oct 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_FAMILY_10H_INSTALL_H_ -#define _OPTION_FAMILY_10H_INSTALL_H_ - -/* - * Common Family 10h routines - */ -extern F_CPU_DISABLE_PSTATE F10DisablePstate; -extern F_CPU_TRANSITION_PSTATE F10TransitionPstate; -extern F_CPU_GET_TSC_RATE F10GetTscRate; -extern F_CPU_GET_NB_FREQ F10GetCurrentNbFrequency; -extern F_CPU_AP_INITIAL_LAUNCH F10LaunchApCore; -extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F10GetApMailboxFromHardware; -extern F_CPU_SET_AP_CORE_NUMBER F10SetApCoreNumber; -extern F_CPU_GET_AP_CORE_NUMBER F10GetApCoreNumber; -extern F_CPU_TRANSFER_AP_CORE_NUMBER F10TransferApCoreNumber; -extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F10CpuAmdCoreIdPositionInInitialApicId; -extern F_CPU_SAVE_FEATURES F10SaveFeatures; -extern F_CPU_WRITE_FEATURES F10WriteFeatures; -extern F_CPU_SET_WARM_RESET_FLAG F10SetAgesaWarmResetFlag; -extern F_CPU_GET_WARM_RESET_FLAG F10GetAgesaWarmResetFlag; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString1; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString2; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10CacheInfo; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10SysPmTable; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10WheaInitData; -extern F_CPU_SET_CFOH_REG SetF10CacheFlushOnHaltRegister; -extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F10GetPlatformTypeSpecificInfo; -extern F_NEXT_LINK_HAS_HTFPY_FEATS F10NextLinkHasHtPhyFeats; -extern F_SET_HT_PHY_REGISTER F10SetHtPhyRegister; -extern F_GET_NEXT_HT_LINK_FEATURES F10GetNextHtLinkFeatures; -extern CONST REGISTER_TABLE ROMDATA F10PciRegisterTable; -extern CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable; -extern CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable; -extern CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable; -extern CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable; -extern CONST REGISTER_TABLE ROMDATA F10WorkaroundsTable; -extern F_GET_EARLY_INIT_TABLE GetF10EarlyInitOnCoreTable; - - -/* - * Install family 10h model 5 support - */ -#ifdef OPTION_FAMILY10H_BL - #if OPTION_FAMILY10H_BL == TRUE - extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicroCodePatchesStruct; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicrocodeEquivalenceTable; - extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax; - extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo; - extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency; - extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate; - extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled; - extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores; - - #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F10BlRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F10PciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10SingleLinkPciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10RevCPciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10BlPciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F10MsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F10RevCMsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F10BlMsrRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10HtPhyRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10RevCHtPhyRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10BlHtPhyRegisterTable, - #endif - #if BASE_FAMILY_WORKAROUNDS == TRUE - &F10WorkaroundsTable, - #endif - // the end. - NULL - }; - #endif - - #if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10BlTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {HtPhyRegister, SetRegisterForHtPhyEntry}, - {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, - {DeemphasisRegister, SetRegisterForDeemphasisEntry}, - {ProfileFixup, SetRegisterForPerformanceProfileEntry}, - {HtHostPciRegister, SetRegisterForHtHostEntry}, - {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid}, - {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, - {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, - {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, - {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; - #endif - - CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10BlServices = - { - 0, - #if DISABLE_PSTATE == TRUE - F10DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F10TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F10CommonRevCGetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F10GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10GetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10RevCGetMinMaxNbFrequency, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10CommonRevCGetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F10CommonRevCGetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F10LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F10CommonRevCGetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F10GetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - F10SetApCoreNumber, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F10GetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - F10TransferApCoreNumber, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F10CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - F10SaveFeatures, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - F10WriteFeatures, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F10SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F10GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - GetF10BrandIdString1, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - GetF10BrandIdString2, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetF10BlMicroCodePatchesStruct, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetF10BlMicrocodeEquivalenceTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF10CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF10SysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF10WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - F10GetPlatformTypeSpecificInfo, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - F10CommonRevCIsNbPstateEnabled, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10NextLinkHasHtPhyFeats, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10SetHtPhyRegister, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - F10GetNextHtLinkFeatures, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F10BlRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10BlTableEntryTypeDescriptors, - #else - NULL, - #endif - NULL, - NULL, - InitCacheDisabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetF10EarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif - }; - - #define BL_SOCKETS 1 - #define BL_MODULES 1 - #define BL_RECOVERY_SOCKETS 1 - #define BL_RECOVERY_MODULES 1 - extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10BlLogicalIdAndRev; - #define OPT_F10_BL_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10BlLogicalIdAndRev, - #ifndef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS - #else - #if ADVCFG_PLATFORM_SOCKETS < BL_SOCKETS - #undef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS - #endif - #endif - #ifndef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES BL_MODULES - #else - #if ADVCFG_PLATFORM_MODULES < BL_MODULES - #undef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES BL_MODULES - #endif - #endif - - #if GET_PATCHES == TRUE - #define F10_BL_UCODE_C6 - #define F10_BL_UCODE_C8 - - #if AGESA_ENTRY_INIT_EARLY == TRUE - #if OPTION_AM3_SOCKET_SUPPORT == TRUE - extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6; - #undef F10_BL_UCODE_C6 - #define F10_BL_UCODE_C6 &CpuF10MicrocodePatch010000c6, - #endif - #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE) - extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8; - #undef F10_BL_UCODE_C8 - #define F10_BL_UCODE_C8 &CpuF10MicrocodePatch010000c8, - #endif - #endif - - CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] = - { - F10_BL_UCODE_C6 - F10_BL_UCODE_C8 - NULL - }; - - CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10BlMicroCodePatchArray) / sizeof (CpuF10BlMicroCodePatchArray[0])) - 1); - #endif - - #define OPT_F10_BL_CPU {AMD_FAMILY_10_BL, &cpuF10BlServices}, - #else - #define OPT_F10_BL_CPU - #define OPT_F10_BL_ID - #endif -#else - #define OPT_F10_BL_CPU - #define OPT_F10_BL_ID -#endif - -/* - * Install family 10h model 6 support - */ -#ifdef OPTION_FAMILY10H_DA - #if OPTION_FAMILY10H_DA == TRUE - extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicroCodePatchesStruct; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicrocodeEquivalenceTable; - extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax; - extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo; - extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency; - extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate; - extern F_CPU_SET_CFOH_REG SetF10DaCacheFlushOnHaltRegister; - extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled; - extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores; - - #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F10DaRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F10PciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10SingleLinkPciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10RevCPciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10DaPciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F10MsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F10RevCMsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F10DaMsrRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10HtPhyRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10RevCHtPhyRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10DaHtPhyRegisterTable, - #endif - #if BASE_FAMILY_WORKAROUNDS == TRUE - &F10WorkaroundsTable, - #endif - // the end. - NULL - }; - #endif - - #if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10DaTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {HtPhyRegister, SetRegisterForHtPhyEntry}, - {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, - {DeemphasisRegister, SetRegisterForDeemphasisEntry}, - {ProfileFixup, SetRegisterForPerformanceProfileEntry}, - {HtHostPciRegister, SetRegisterForHtHostEntry}, - {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid}, - {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, - {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, - {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, - {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; - #endif - - CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10DaServices = - { - 0, - #if DISABLE_PSTATE == TRUE - F10DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F10TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F10CommonRevCGetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F10GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10GetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10RevCGetMinMaxNbFrequency, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10CommonRevCGetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F10CommonRevCGetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F10LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F10CommonRevCGetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F10GetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - F10SetApCoreNumber, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F10GetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - F10TransferApCoreNumber, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F10CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - F10SaveFeatures, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - F10WriteFeatures, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F10SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F10GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - GetF10BrandIdString1, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - GetF10BrandIdString2, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetF10DaMicroCodePatchesStruct, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetF10DaMicrocodeEquivalenceTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF10CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF10SysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF10WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - F10GetPlatformTypeSpecificInfo, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - F10CommonRevCIsNbPstateEnabled, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10NextLinkHasHtPhyFeats, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10SetHtPhyRegister, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - F10GetNextHtLinkFeatures, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F10DaRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10DaTableEntryTypeDescriptors, - #else - NULL, - #endif - NULL, - NULL, - InitCacheDisabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetF10EarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif - }; - - #define DA_SOCKETS 1 - #define DA_MODULES 1 - #define DA_RECOVERY_SOCKETS 1 - #define DA_RECOVERY_MODULES 1 - extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10DaLogicalIdAndRev; - #define OPT_F10_DA_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10DaLogicalIdAndRev, - #ifndef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS - #else - #if ADVCFG_PLATFORM_SOCKETS < DA_SOCKETS - #undef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS - #endif - #endif - #ifndef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES DA_MODULES - #else - #if ADVCFG_PLATFORM_MODULES < DA_MODULES - #undef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES DA_MODULES - #endif - #endif - - #if GET_PATCHES == TRUE - #define F10_DA_UCODE_C7 - #define F10_DA_UCODE_C8 - - // If a patch is required for recovery mode to function properly, add a - // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in. - #if AGESA_ENTRY_INIT_EARLY == TRUE - #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) - extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7; - #undef F10_DA_UCODE_C7 - #define F10_DA_UCODE_C7 &CpuF10MicrocodePatch010000c7, - #endif - #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE) - extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8; - #undef F10_DA_UCODE_C8 - #define F10_DA_UCODE_C8 &CpuF10MicrocodePatch010000c8, - #endif - #endif - - CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] = - { - F10_DA_UCODE_C7 - F10_DA_UCODE_C8 - NULL - }; - - CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10DaMicroCodePatchArray) / sizeof (CpuF10DaMicroCodePatchArray[0])) - 1); - #endif - - #define OPT_F10_DA_CPU {AMD_FAMILY_10_DA, &cpuF10DaServices}, - #else - #define OPT_F10_DA_CPU - #define OPT_F10_DA_ID - #endif -#else - #define OPT_F10_DA_CPU - #define OPT_F10_DA_ID -#endif - -/* - * Install family 10h models 8 & 9 support - */ -#ifdef OPTION_FAMILY10H_HY - #if OPTION_FAMILY10H_HY == TRUE - extern CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicroCodePatchesStruct; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicrocodeEquivalenceTable; - extern F_CPU_GET_IDD_MAX F10CommonRevDGetProcIddMax; - extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevDGetNbPstateInfo; - extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevDGetMinMaxNbFrequency; - extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevDGetNbCofVidUpdate; - extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[]; - extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevDGetNumberOfPhysicalCores; - extern F_GET_EARLY_INIT_TABLE GetF10HyEarlyInitOnCoreTable; - - #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F10HyRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F10PciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10MultiLinkPciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10HyPciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F10MsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F10HyMsrRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10HtPhyRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10HyHtPhyRegisterTable, - #endif - #if BASE_FAMILY_WORKAROUNDS == TRUE - &F10WorkaroundsTable, - #endif - // the end. - NULL - }; - #endif - - #if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10HyTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {HtPhyRegister, SetRegisterForHtPhyEntry}, - {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, - {DeemphasisRegister, SetRegisterForDeemphasisEntry}, - {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry}, - {ProfileFixup, SetRegisterForPerformanceProfileEntry}, - {HtHostPciRegister, SetRegisterForHtHostEntry}, - {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry}, - {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, - {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, - {TokenPciRegister, SetRegisterForTokenPciEntry}, - {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, - {HtLinkPciRegister, SetRegisterForHtLinkPciEntry}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; - #endif - - CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10HyServices = - { - 0, - #if DISABLE_PSTATE == TRUE - F10DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F10TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F10CommonRevDGetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F10GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10GetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10RevDGetMinMaxNbFrequency, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10CommonRevDGetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F10CommonRevDGetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F10LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F10CommonRevDGetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F10GetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - F10SetApCoreNumber, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F10GetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - F10TransferApCoreNumber, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F10CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - F10SaveFeatures, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - F10WriteFeatures, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F10SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F10GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - GetF10BrandIdString1, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - GetF10BrandIdString2, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetF10HyMicroCodePatchesStruct, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetF10HyMicrocodeEquivalenceTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF10CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF10SysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF10WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - F10GetPlatformTypeSpecificInfo, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10NextLinkHasHtPhyFeats, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10SetHtPhyRegister, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - F10GetNextHtLinkFeatures, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F10HyRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10HyTableEntryTypeDescriptors, - #else - NULL, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap, - #else - NULL, - #endif - NULL, - InitCacheDisabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - #if OPTION_C32_SOCKET_SUPPORT == TRUE - GetF10HyEarlyInitOnCoreTable - #else - GetF10EarlyInitOnCoreTable - #endif - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif - }; - - #define HY_SOCKETS 8 - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) - #define HY_MODULES 2 - #else - #define HY_MODULES 1 - #endif - #define HY_RECOVERY_SOCKETS 1 - #define HY_RECOVERY_MODULES 1 - extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10HyLogicalIdAndRev; - #define OPT_F10_HY_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10HyLogicalIdAndRev, - #ifndef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS - #else - #if ADVCFG_PLATFORM_SOCKETS < HY_SOCKETS - #undef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS - #endif - #endif - #ifndef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES HY_MODULES - #else - #if ADVCFG_PLATFORM_MODULES < HY_MODULES - #undef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES HY_MODULES - #endif - #endif - - #if GET_PATCHES == TRUE - #define F10_HY_UCODE_D9 - #define F10_HY_UCODE_C5 - - // If a patch is required for recovery mode to function properly, add a - // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in. - #if AGESA_ENTRY_INIT_EARLY == TRUE - #if OPTION_C32_SOCKET_SUPPORT == TRUE - extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5; - #undef F10_HY_UCODE_C5 - #define F10_HY_UCODE_C5 &CpuF10MicrocodePatch010000c5, - #endif - #if (OPTION_C32_SOCKET_SUPPORT == TRUE) || (OPTION_G34_SOCKET_SUPPORT == TRUE) - extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000d9; - #undef F10_HY_UCODE_D9 - #define F10_HY_UCODE_D9 &CpuF10MicrocodePatch010000d9, - #endif - #endif - - CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] = - { - F10_HY_UCODE_D9 - F10_HY_UCODE_C5 - NULL - }; - - CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10HyMicroCodePatchArray) / sizeof (CpuF10HyMicroCodePatchArray[0])) - 1); - #endif - - #define OPT_F10_HY_CPU {AMD_FAMILY_10_HY, &cpuF10HyServices}, - #else - #define OPT_F10_HY_CPU - #define OPT_F10_HY_ID - #endif -#else - #define OPT_F10_HY_CPU - #define OPT_F10_HY_ID -#endif - -/* - * Install family 10h model 10 support - */ -#ifdef OPTION_FAMILY10H_PH - #if OPTION_FAMILY10H_PH == TRUE - extern CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10RevEMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10RevEHtPhyRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10PhPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10PhMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10PhHtPhyRegisterTable; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicroCodePatchesStruct; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicrocodeEquivalenceTable; - extern F_CPU_GET_IDD_MAX F10CommonRevEGetProcIddMax; - extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevEGetNbPstateInfo; - extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevEGetMinMaxNbFrequency; - extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevEGetNbCofVidUpdate; - extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevEGetNumberOfPhysicalCores; - - #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F10PhRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F10PciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10SingleLinkPciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10RevEPciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F10MsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F10RevEMsrRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10HtPhyRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10RevEHtPhyRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10PhHtPhyRegisterTable, - #endif - #if BASE_FAMILY_WORKAROUNDS == TRUE - &F10WorkaroundsTable, - #endif - // the end. - NULL - }; - #endif - - #if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10PhTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {HtPhyRegister, SetRegisterForHtPhyEntry}, - {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, - {DeemphasisRegister, SetRegisterForDeemphasisEntry}, - {ProfileFixup, SetRegisterForPerformanceProfileEntry}, - {HtHostPciRegister, SetRegisterForHtHostEntry}, - {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid}, - {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, - {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, - {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, - {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; - #endif - - CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10PhServices = - { - 0, - #if DISABLE_PSTATE == TRUE - F10DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F10TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F10CommonRevEGetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F10GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10GetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10RevEGetMinMaxNbFrequency, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10CommonRevEGetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F10CommonRevEGetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F10LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F10CommonRevEGetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F10GetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - F10SetApCoreNumber, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F10GetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - F10TransferApCoreNumber, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F10CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - F10SaveFeatures, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - F10WriteFeatures, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F10SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F10GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - GetF10BrandIdString1, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - GetF10BrandIdString2, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetF10PhMicroCodePatchesStruct, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetF10PhMicrocodeEquivalenceTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF10CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF10SysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF10WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - F10GetPlatformTypeSpecificInfo, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10NextLinkHasHtPhyFeats, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10SetHtPhyRegister, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - F10GetNextHtLinkFeatures, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F10PhRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10PhTableEntryTypeDescriptors, - #else - NULL, - #endif - NULL, - NULL, - InitCacheDisabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetF10EarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif - }; - - #define PH_SOCKETS 1 - #define PH_MODULES 1 - #define PH_RECOVERY_SOCKETS 1 - #define PH_RECOVERY_MODULES 1 - extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10PhLogicalIdAndRev; - #define OPT_F10_PH_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10PhLogicalIdAndRev, - #ifndef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS - #else - #if ADVCFG_PLATFORM_SOCKETS < PH_SOCKETS - #undef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS - #endif - #endif - #ifndef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES PH_MODULES - #else - #if ADVCFG_PLATFORM_MODULES < PH_MODULES - #undef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES PH_MODULES - #endif - #endif - - #if GET_PATCHES == TRUE - #define F10_PH_UCODE_BF - - // If a patch is required for recovery mode to function properly, add a - // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in. - #if AGESA_ENTRY_INIT_EARLY == TRUE - #if OPTION_AM3_SOCKET_SUPPORT == TRUE - extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000bf; - #undef F10_PH_UCODE_BF - #define F10_PH_UCODE_BF &CpuF10MicrocodePatch010000bf, - #endif - #endif - - CONST MICROCODE_PATCHES ROMDATA *CpuF10PhMicroCodePatchArray[] = - { - F10_PH_UCODE_BF - NULL - }; - - CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10PhMicroCodePatchArray) / sizeof (CpuF10PhMicroCodePatchArray[0])) - 1); - #endif - - #define OPT_F10_PH_CPU {AMD_FAMILY_10_PH, &cpuF10PhServices}, - #else - #define OPT_F10_PH_CPU - #define OPT_F10_PH_ID - #endif -#else - #define OPT_F10_PH_CPU - #define OPT_F10_PH_ID -#endif - - -/* - * Install family 10h model 4 support - */ -#ifdef OPTION_FAMILY10H_RB - #if OPTION_FAMILY10H_RB == TRUE - extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicroCodePatchesStruct; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicrocodeEquivalenceTable; - extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax; - extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo; - extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency; - extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate; - extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled; - extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores; - - #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F10RbRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F10PciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10MultiLinkPciRegisterTable, - &F10SingleLinkPciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10RevCPciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F10RbPciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F10MsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F10RevCMsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F10RbMsrRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10HtPhyRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10RevCHtPhyRegisterTable, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F10RbHtPhyRegisterTable, - #endif - #if BASE_FAMILY_WORKAROUNDS == TRUE - &F10WorkaroundsTable, - #endif - // the end. - NULL - }; - #endif - - #if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10RbTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {HtPhyRegister, SetRegisterForHtPhyEntry}, - {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, - {DeemphasisRegister, SetRegisterForDeemphasisEntry}, - {ProfileFixup, SetRegisterForPerformanceProfileEntry}, - {HtHostPciRegister, SetRegisterForHtHostEntry}, - {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry}, - {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, - {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, - {TokenPciRegister, SetRegisterForTokenPciEntry}, - {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, - {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; - #endif - - CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10RbServices = - { - 0, - #if DISABLE_PSTATE == TRUE - F10DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F10TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F10CommonRevCGetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F10GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10GetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10RevCGetMinMaxNbFrequency, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10CommonRevCGetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F10CommonRevCGetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F10LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F10CommonRevCGetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F10GetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - F10SetApCoreNumber, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F10GetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - F10TransferApCoreNumber, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F10CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - F10SaveFeatures, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - F10WriteFeatures, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F10SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F10GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - GetF10BrandIdString1, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - GetF10BrandIdString2, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetF10RbMicroCodePatchesStruct, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetF10RbMicrocodeEquivalenceTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF10CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF10SysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF10WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - F10GetPlatformTypeSpecificInfo, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - F10CommonRevCIsNbPstateEnabled, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10NextLinkHasHtPhyFeats, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10SetHtPhyRegister, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - F10GetNextHtLinkFeatures, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F10RbRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10RbTableEntryTypeDescriptors, - #else - NULL, - #endif - NULL, - NULL, - InitCacheDisabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetF10EarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif - }; - - #define RB_SOCKETS 8 - #define RB_MODULES 1 - #define RB_RECOVERY_SOCKETS 1 - #define RB_RECOVERY_MODULES 1 - extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10RbLogicalIdAndRev; - #define OPT_F10_RB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10RbLogicalIdAndRev, - #ifndef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS - #else - #if ADVCFG_PLATFORM_SOCKETS < RB_SOCKETS - #undef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS - #endif - #endif - #ifndef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES RB_MODULES - #else - #if ADVCFG_PLATFORM_MODULES < RB_MODULES - #undef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES RB_MODULES - #endif - #endif - - #if GET_PATCHES == TRUE - #define F10_RB_UCODE_85 - #define F10_RB_UCODE_C6 - #define F10_RB_UCODE_C8 - - // If a patch is required for recovery mode to function properly, add a - // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in. - #if AGESA_ENTRY_INIT_EARLY == TRUE - #if OPTION_AM3_SOCKET_SUPPORT == TRUE - extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085; - extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6; - extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8; - #undef F10_RB_UCODE_85 - #define F10_RB_UCODE_85 &CpuF10MicrocodePatch01000085, - #undef F10_RB_UCODE_C6 - #define F10_RB_UCODE_C6 &CpuF10MicrocodePatch010000c6, - #undef F10_RB_UCODE_C8 - #define F10_RB_UCODE_C8 &CpuF10MicrocodePatch010000c8, - #endif - #endif - - CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[] = - { - F10_RB_UCODE_85 - F10_RB_UCODE_C6 - F10_RB_UCODE_C8 - NULL - }; - - CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10RbMicroCodePatchArray) / sizeof (CpuF10RbMicroCodePatchArray[0])) - 1); - #endif - - #define OPT_F10_RB_CPU {AMD_FAMILY_10_RB, &cpuF10RbServices}, - #else - #define OPT_F10_RB_CPU - #define OPT_F10_RB_ID - #endif -#else - #define OPT_F10_RB_CPU - #define OPT_F10_RB_ID -#endif - - -/* - * Install unknown family 10h support - */ - -#if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F10UnknownRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F10PciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F10MsrRegisterTable, - #endif - #if BASE_FAMILY_HT_PCI == TRUE - &F10HtPhyRegisterTable, - #endif - #if OPTION_MULTISOCKET == TRUE - #if MODEL_SPECIFIC_PCI == TRUE - &F10MultiLinkPciRegisterTable, - #endif - #endif - #if OPTION_MULTISOCKET == FALSE - #if MODEL_SPECIFIC_PCI == TRUE - &F10SingleLinkPciRegisterTable, - #endif - #endif - #if BASE_FAMILY_WORKAROUNDS == TRUE - &F10WorkaroundsTable, - #endif - // the end. - NULL - }; -#endif - -#if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10UnknownTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {HtPhyRegister, SetRegisterForHtPhyEntry}, - {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, - {DeemphasisRegister, SetRegisterForDeemphasisEntry}, - {ProfileFixup, SetRegisterForPerformanceProfileEntry}, - {HtHostPciRegister, SetRegisterForHtHostEntry}, - {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid}, - {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, - {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, - {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; -#endif - - -CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10UnknownServices = -{ - 0, - #if DISABLE_PSTATE == TRUE - F10DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F10TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - (PF_CPU_GET_IDD_MAX) CommonReturnFalse, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F10GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F10GetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonReturnFalse, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F10LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonReturnZero8, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F10GetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - F10SetApCoreNumber, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F10GetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - F10TransferApCoreNumber, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F10CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - F10SaveFeatures, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - F10WriteFeatures, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F10SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F10GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - GetF10BrandIdString1, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - GetF10BrandIdString2, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetEmptyArray, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetEmptyArray, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF10CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF10SysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF10WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - F10GetPlatformTypeSpecificInfo, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10NextLinkHasHtPhyFeats, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F10SetHtPhyRegister, - #else - (PF_SET_HT_PHY_REGISTER) CommonVoid, - #endif - #if BASE_FAMILY_PCI == TRUE - F10GetNextHtLinkFeatures, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F10UnknownRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10UnknownTableEntryTypeDescriptors, - #else - NULL, - #endif - NULL, - NULL, - InitCacheDisabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetF10EarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif -}; - -// Family 10h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate. -#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull) - #undef FAMILY_MMIO_BASE_MASK - #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull) -#endif - -#undef OPT_F10_ID_TABLE -#define OPT_F10_ID_TABLE {0x10, {AMD_FAMILY_10, AMD_F10_UNKNOWN}, F10LogicalIdTable, (sizeof (F10LogicalIdTable) / sizeof (F10LogicalIdTable[0]))}, -#define OPT_F10_UNKNOWN_CPU {AMD_FAMILY_10, &cpuF10UnknownServices}, - -#undef OPT_F10_TABLE -#define OPT_F10_TABLE OPT_F10_BL_CPU OPT_F10_DA_CPU OPT_F10_HY_CPU OPT_F10_PH_CPU OPT_F10_RB_CPU OPT_F10_UNKNOWN_CPU - -#if OPTION_G34_SOCKET_SUPPORT == TRUE - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34; - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34; - #define F10_G34_BRANDSTRING1 &F10BrandIdString1ArrayG34, - #define F10_G34_BRANDSTRING2 &F10BrandIdString2ArrayG34, -#else - #define F10_G34_BRANDSTRING1 - #define F10_G34_BRANDSTRING2 -#endif -#if OPTION_C32_SOCKET_SUPPORT == TRUE - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32; - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32; - #define F10_C32_BRANDSTRING1 &F10BrandIdString1ArrayC32, - #define F10_C32_BRANDSTRING2 &F10BrandIdString2ArrayC32, -#else - #define F10_C32_BRANDSTRING1 - #define F10_C32_BRANDSTRING2 -#endif -#if OPTION_S1G3_SOCKET_SUPPORT == TRUE - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3; - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3; - #define F10_S1G3_BRANDSTRING1 &F10BrandIdString1ArrayS1g3, - #define F10_S1G3_BRANDSTRING2 &F10BrandIdString2ArrayS1g3, -#else - #define F10_S1G3_BRANDSTRING1 - #define F10_S1G3_BRANDSTRING2 -#endif -#if OPTION_S1G4_SOCKET_SUPPORT == TRUE - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4; - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4; - #define F10_S1G4_BRANDSTRING1 &F10BrandIdString1ArrayS1g4, - #define F10_S1G4_BRANDSTRING2 &F10BrandIdString2ArrayS1g4, -#else - #define F10_S1G4_BRANDSTRING1 - #define F10_S1G4_BRANDSTRING2 -#endif -#if OPTION_ASB2_SOCKET_SUPPORT == TRUE - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2; - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2; - #define F10_ASB2_BRANDSTRING1 &F10BrandIdString1ArrayAsb2, - #define F10_ASB2_BRANDSTRING2 &F10BrandIdString2ArrayAsb2, -#else - #define F10_ASB2_BRANDSTRING1 - #define F10_ASB2_BRANDSTRING2 -#endif -#if OPTION_AM3_SOCKET_SUPPORT == TRUE - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3; - extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3; - #define F10_AM3_BRANDSTRING1 &F10BrandIdString1ArrayAm3, - #define F10_AM3_BRANDSTRING2 &F10BrandIdString2ArrayAm3, -#else - #define F10_AM3_BRANDSTRING1 - #define F10_AM3_BRANDSTRING2 -#endif - -#if BRAND_STRING1 == TRUE - CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] = - { - F10_G34_BRANDSTRING1 - F10_C32_BRANDSTRING1 - F10_S1G3_BRANDSTRING1 - F10_S1G4_BRANDSTRING1 - F10_ASB2_BRANDSTRING1 - F10_AM3_BRANDSTRING1 - }; - - CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0])); -#endif - -#if BRAND_STRING2 == TRUE - CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] = - { - F10_G34_BRANDSTRING2 - F10_C32_BRANDSTRING2 - F10_S1G3_BRANDSTRING2 - F10_S1G4_BRANDSTRING2 - F10_ASB2_BRANDSTRING2 - F10_AM3_BRANDSTRING2 - }; - - CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0])); -#endif - -CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F10LogicalIdTable[] = -{ - OPT_F10_BL_ID - OPT_F10_DA_ID - OPT_F10_HY_ID - OPT_F10_PH_ID - OPT_F10_RB_ID -}; - -#endif // _OPTION_FAMILY_10H_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionFamily15hInstall.h deleted file mode 100644 index 73eeb6fca4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionFamily15hInstall.h +++ /dev/null @@ -1,1570 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of family 15h support - * - * This file generates the defaults tables for family 15h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 60770 $ @e \$Date: 2011-10-21 15:51:10 -0600 (Fri, 21 Oct 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_FAMILY_15H_INSTALL_H_ -#define _OPTION_FAMILY_15H_INSTALL_H_ - -#include "OptionFamily15hEarlySample.h" - -/* - * Pull in family specific services based on entry point - */ - -/* - * Common Family 15h routines - */ -extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled; - -/* - * Install family 15h model 0 support - */ -#ifdef OPTION_FAMILY15H_OR - #if OPTION_FAMILY15H_OR == TRUE - extern F_CPU_GET_IDD_MAX F15OrGetProcIddMax; - extern F_CPU_GET_NB_PSTATE_INFO F15OrGetNbPstateInfo; - extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate; - extern F_CPU_DISABLE_PSTATE F15DisablePstate; - extern F_CPU_TRANSITION_PSTATE F15TransitionPstate; - extern F_CPU_GET_TSC_RATE F15GetTscRate; - extern F_CPU_GET_NB_FREQ F15OrGetCurrentNbFrequency; - extern F_CPU_GET_MIN_MAX_NB_FREQ F15OrGetMinMaxNbFrequency; - extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore; - extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15OrGetNumberOfPhysicalCores; - extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15OrGetApMailboxFromHardware; - extern F_CPU_SET_AP_CORE_NUMBER F15OrSetApCoreNumber; - extern F_CPU_GET_AP_CORE_NUMBER F15OrGetApCoreNumber; - extern F_CPU_TRANSFER_AP_CORE_NUMBER F15OrTransferApCoreNumber; - extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId; - extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag; - extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrSysPmTable; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData; - extern F_CPU_SET_CFOH_REG SetF15OrCacheFlushOnHaltRegister; - extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats; - extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister; - extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable; - extern F_GET_EARLY_INIT_TABLE GetF15OrEarlyInitOnCoreTable; - extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15OrAM3MsrWorkaroundTable; - extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrCuRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrWorkaroundTable; - extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15OrMultiLinkPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15OrSingleLinkPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15OrWorkaroundsTable; - extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[]; - - #if OPTION_EARLY_SAMPLES == TRUE - extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleWorkaroundsTable; - extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrWorkaroundTable; - extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15OrEarlySamplePciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleMsrRegisterTable; - #endif - /** - * Core Pair and core pair primary determination table. - * - * The two fields from the core pair hardware register can be used to determine whether - * even number cores are primary or all cores are primary. It can be extended if it is - * decided to have other configs as well. The other logically possible value sets are BitMapMapping, - * but they are currently not supported by the processor. - */ - CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] = - { - {1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores - {3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores - {7, 7, EvenCoresMapping}, ///< 3 Compute Units all with 2 Cores - {0xF, 0xF, EvenCoresMapping}, ///< 4 Compute Units all with 2 Cores - {1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core - {3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core - {7, 0, AllCoresMapping}, ///< 3 Compute Units all with 1 Core - {0xF, 0, AllCoresMapping}, ///< 4 Compute Units all with 1 Core - {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End - }; - - - #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F15PciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F15OrMultiLinkPciRegisterTable, - &F15OrSingleLinkPciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F15OrPciRegisterTable, - #if OPTION_EARLY_SAMPLES == TRUE - &F15OrEarlySamplePciRegisterTable, - #endif - #endif - #if BASE_FAMILY_MSR == TRUE - &F15MsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F15OrMsrRegisterTable, - #if (OPTION_AM3_SOCKET_SUPPORT == TRUE) && (CFG_FORCE_MICROSERVER == FALSE) - &F15OrAM3MsrWorkaroundTable, - #endif - #if OPTION_EARLY_SAMPLES == TRUE - &F15OrEarlySampleMsrRegisterTable, - #endif - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F15OrSharedMsrRegisterTable, - &F15OrSharedMsrCuRegisterTable, - &F15OrSharedMsrWorkaroundTable, - #if OPTION_EARLY_SAMPLES == TRUE - &F15OrEarlySampleSharedMsrRegisterTable, - &F15OrEarlySampleSharedMsrWorkaroundTable, - #endif - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - &F15OrHtPhyRegisterTable, - #endif - #if BASE_FAMILY_WORKAROUNDS == TRUE - &F15OrWorkaroundsTable, - #if OPTION_EARLY_SAMPLES == TRUE - &F15OrEarlySampleWorkaroundsTable, - #endif - #endif - // the end. - NULL - }; - #endif - - #if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {HtPhyRegister, SetRegisterForHtPhyEntry}, - {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, - {DeemphasisRegister, SetRegisterForDeemphasisEntry}, - {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry}, - {ProfileFixup, SetRegisterForPerformanceProfileEntry}, - {HtHostPciRegister, SetRegisterForHtHostEntry}, - {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry}, - {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry}, - {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, - {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, - {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry}, - {TokenPciRegister, SetRegisterForTokenPciEntry}, - {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, - {HtLinkPciRegister, SetRegisterForHtLinkPciEntry}, - {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; - #endif - - CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices = - { - 0, - #if DISABLE_PSTATE == TRUE - F15DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F15TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F15OrGetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F15GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F15OrGetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F15OrGetMinMaxNbFrequency, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F15OrGetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F15CommonGetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F15LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F15OrGetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F15OrGetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - F15OrSetApCoreNumber, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F15OrGetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - F15OrTransferApCoreNumber, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F15CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - // F15OrSaveFeatures, - (PF_CPU_SAVE_FEATURES) CommonVoid, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - // F15OrWriteFeatures, - (PF_CPU_WRITE_FEATURES) CommonVoid, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F15SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F15GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetF15OrMicroCodePatchesStruct, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetF15OrMicrocodeEquivalenceTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF15CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF15OrSysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF15WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - F15IsNbPstateEnabled, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F15NextLinkHasHtPhyFeats, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F15SetHtPhyRegister, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - F15GetNextHtLinkFeatures, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F15OrRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors, - #else - NULL, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap, - #else - NULL, - #endif - (CORE_PAIR_MAP *) &HtFam15CorePairMapping, - InitCacheEnabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetF15OrEarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif - }; - - #define OR_SOCKETS 8 - #define OR_MODULES 2 - #define OR_RECOVERY_SOCKETS 1 - #define OR_RECOVERY_MODULES 1 - extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev; - #define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev, - #ifndef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS - #else - #if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS - #undef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS - #endif - #endif - #ifndef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES OR_MODULES - #else - #if ADVCFG_PLATFORM_MODULES < OR_MODULES - #undef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES OR_MODULES - #endif - #endif - - #if GET_PATCHES == TRUE - #define F15_OR_UCODE_17_UNENC - #define F15_OR_UCODE_11F_UNENC - #define F15_OR_UCODE_425 - #define F15_OR_UCODE_50D - #define F15_OR_UCODE_624 - - #if AGESA_ENTRY_INIT_EARLY == TRUE - #if OPTION_EARLY_SAMPLES == TRUE - extern CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000425 []; - #undef F15_OR_UCODE_425 - #define F15_OR_UCODE_425 CpuF15OrMicrocodePatch06000425, - - extern CONST UINT8 ROMDATA CpuF15OrMicrocodePatch0600050D_Enc []; - #undef F15_OR_UCODE_50D - #define F15_OR_UCODE_50D CpuF15OrMicrocodePatch0600050D_Enc, - #endif - extern CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000624_Enc []; - #undef F15_OR_UCODE_624 - #define F15_OR_UCODE_624 CpuF15OrMicrocodePatch06000624_Enc, - #endif - - CONST UINT8 ROMDATA *CpuF15OrMicroCodePatchArray[] = - { - F15_OR_UCODE_624 - F15_OR_UCODE_50D - F15_OR_UCODE_425 - NULL - }; - - CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1); - #endif - - #if OPTION_EARLY_SAMPLES == TRUE - extern F_F15_OR_ES_AVOID_NB_CYCLES_START F15OrEarlySamplesAvoidNbCyclesStart; - extern F_F15_OR_ES_AVOID_NB_CYCLES_END F15OrEarlySamplesAvoidNbCyclesEnd; - extern F_F15_OR_ES_LOAD_MCU_PATCH F15OrEarlySamplesLoadMicrocodePatch; - extern F_F15_OR_ES_AFTER_PATCH_LOADED F15OrEarlySamplesAfterPatchLoaded; - - CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch = - { - F15OrEarlySamplesAvoidNbCyclesStart, - F15OrEarlySamplesAvoidNbCyclesEnd, - F15OrEarlySamplesLoadMicrocodePatch, - F15OrEarlySamplesAfterPatchLoaded - }; - #else - CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch = - { - (PF_F15_OR_ES_AVOID_NB_CYCLES_START) CommonVoid, - (PF_F15_OR_ES_AVOID_NB_CYCLES_END) CommonVoid, - (PF_F15_OR_ES_LOAD_MCU_PATCH) LoadMicrocodePatch, - (PF_F15_OR_ES_AFTER_PATCH_LOADED) CommonVoid - }; - #endif - - #if OPTION_EARLY_SAMPLES == TRUE - extern F_F15_OR_ES_HTC_INIT_HOOK F15OrHtcInitEarlySampleHook; - - CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport = - { - #if AGESA_ENTRY_INIT_EARLY == TRUE - F15OrHtcInitEarlySampleHook, - #else - (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert, - #endif - }; - #else - CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport = - { - #if AGESA_ENTRY_INIT_EARLY == TRUE - (PF_F15_OR_ES_HTC_INIT_HOOK) CommonVoid, - #else - (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert, - #endif - }; - #endif - - #define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices}, - - #else // OPTION_FAMILY15H_OR == TRUE - #define OPT_F15_OR_CPU - #define OPT_F15_OR_ID - #endif // OPTION_FAMILY15H_OR == TRUE -#else // defined (OPTION_FAMILY15H_OR) - #define OPT_F15_OR_CPU - #define OPT_F15_OR_ID -#endif // defined (OPTION_FAMILY15H_OR) - - -/* - * Install family 15h model 10h - 1Fh support - */ -#ifdef OPTION_FAMILY15H_TN - #if OPTION_FAMILY15H_TN == TRUE - extern F_CPU_GET_IDD_MAX F15TnGetProcIddMax; - extern F_CPU_GET_NB_PSTATE_INFO F15TnGetNbPstateInfo; - extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate; - extern F_CPU_GET_NB_IDD_MAX F15TnGetNbIddMax; - extern F_CPU_DISABLE_PSTATE F15DisablePstate; - extern F_CPU_TRANSITION_PSTATE F15TransitionPstate; - extern F_CPU_GET_TSC_RATE F15GetTscRate; - extern F_CPU_GET_NB_FREQ F15TnGetCurrentNbFrequency; - extern F_CPU_GET_MIN_MAX_NB_FREQ F15TnGetMinMaxNbFrequency; - extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore; - extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15TnGetNumberOfPhysicalCores; - extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15TnGetApMailboxFromHardware; - extern F_CPU_GET_AP_CORE_NUMBER F15TnGetApCoreNumber; - extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId; - extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag; - extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnSysPmTable; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData; - extern F_CPU_SET_CFOH_REG SetF15TnCacheFlushOnHaltRegister; - extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats; - extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister; - extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicroCodePatchesStruct; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicrocodeEquivalenceTable; - extern F_GET_EARLY_INIT_TABLE GetF15TnEarlyInitOnCoreTable; - extern CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable; - extern CONST REGISTER_TABLE ROMDATA F15TnMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrCuRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable; - extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable; - - /** - * Core Pair and core pair primary determination table. - * - * The two fields from the core pair hardware register can be used to determine whether - * even number cores are primary or all cores are primary. It can be extended if it is - * decided to have other configs as well. The other logically possible value sets are BitMapMapping, - * but they are currently not supported by the processor. - */ - CONST CORE_PAIR_MAP ROMDATA HtFam15TnCorePairMapping[] = - { - {1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores - {3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores - {1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core - {3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core - {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End - }; - - - #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F15TnRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F15PciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F15TnPciRegisterTable, - &F15TnPciWorkaroundTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F15MsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F15TnMsrRegisterTable, - &F15TnSharedMsrRegisterTable, - &F15TnSharedMsrCuRegisterTable, - &F15TnSharedMsrWorkaroundTable, - #endif - // the end. - NULL - }; - #endif - - #if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15TnTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {ProfileFixup, SetRegisterForPerformanceProfileEntry}, - {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry}, - {HtPhyRegister, SetRegisterForHtPhyEntry}, - {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, - {DeemphasisRegister, SetRegisterForDeemphasisEntry}, - {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry}, - {HtHostPciRegister, SetRegisterForHtHostEntry}, - {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry}, - {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry}, - {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, - {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, - {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry}, - {TokenPciRegister, SetRegisterForTokenPciEntry}, - {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, - {HtLinkPciRegister, SetRegisterForHtLinkPciEntry}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; - #endif - - CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15TnServices = - { - 0, - #if DISABLE_PSTATE == TRUE - F15DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F15TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F15TnGetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F15GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F15TnGetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F15TnGetMinMaxNbFrequency, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F15TnGetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F15CommonGetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) F15TnGetNbIddMax, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F15LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F15TnGetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F15TnGetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F15TnGetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F15CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - (PF_CPU_SAVE_FEATURES) CommonVoid, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - (PF_CPU_WRITE_FEATURES) CommonVoid, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F15SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F15GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetF15TnMicroCodePatchesStruct, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetF15TnMicrocodeEquivalenceTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF15CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF15TnSysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF15WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - F15IsNbPstateEnabled, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F15NextLinkHasHtPhyFeats, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F15SetHtPhyRegister, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - F15GetNextHtLinkFeatures, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F15TnRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15TnTableEntryTypeDescriptors, - #else - NULL, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - NULL, - #else - NULL, - #endif - (CORE_PAIR_MAP *) &HtFam15TnCorePairMapping, - InitCacheEnabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetF15TnEarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif - }; - - #define TN_SOCKETS 1 - #define TN_MODULES 1 - #define TN_RECOVERY_SOCKETS 1 - #define TN_RECOVERY_MODULES 1 - extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15TnLogicalIdAndRev; - #define OPT_F15_TN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15TnLogicalIdAndRev, - #ifndef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS - #else - #if ADVCFG_PLATFORM_SOCKETS < TN_SOCKETS - #undef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS - #endif - #endif - #ifndef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES TN_MODULES - #else - #if ADVCFG_PLATFORM_MODULES < TN_MODULES - #undef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES TN_MODULES - #endif - #endif - - #if GET_PATCHES == TRUE - #define F15_TN_UCODE_04 - #define F15_TN_UCODE_04_UNENC - - #if AGESA_ENTRY_INIT_EARLY == TRUE - #if OPTION_EARLY_SAMPLES == TRUE - extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch06001004_Unenc []; - #undef F15_TN_UCODE_04_UNENC - #define F15_TN_UCODE_04_UNENC CpuF15TnMicrocodePatch06001004_Unenc, - - extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch06001004 []; - #undef F15_TN_UCODE_04 - #define F15_TN_UCODE_04 CpuF15TnMicrocodePatch06001004, - #endif - #endif - - CONST UINT8 ROMDATA *CpuF15TnMicroCodePatchArray[] = - { - F15_TN_UCODE_04 - F15_TN_UCODE_04_UNENC - NULL - }; - - CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15TnMicroCodePatchArray) / sizeof (CpuF15TnMicroCodePatchArray[0])) - 1); - #endif - - #if OPTION_EARLY_SAMPLES == TRUE - extern F_F15_TN_ES_LOAD_MCU_PATCH F15TnEarlySamplesLoadMicrocodePatch; - - CONST F15_TN_ES_MCU_PATCH ROMDATA F15TnEarlySampleLoadMcuPatch = - { - F15TnEarlySamplesLoadMicrocodePatch - }; - #else - CONST F15_TN_ES_MCU_PATCH ROMDATA F15TnEarlySampleLoadMcuPatch = - { - (PF_F15_TN_ES_LOAD_MCU_PATCH) LoadMicrocodePatch - }; - #endif - - #define OPT_F15_TN_CPU {AMD_FAMILY_15_TN, &cpuF15TnServices}, - - #else // OPTION_FAMILY15H_TN == TRUE - #define OPT_F15_TN_CPU - #define OPT_F15_TN_ID - #endif // OPTION_FAMILY15H_TN == TRUE -#else // defined (OPTION_FAMILY15H_TN) - #define OPT_F15_TN_CPU - #define OPT_F15_TN_ID -#endif // defined (OPTION_FAMILY15H_TN) - -/* - * Install family 15h model 20h - 2Fh support - */ -#ifdef OPTION_FAMILY15H_KM - #if OPTION_FAMILY15H_KM == TRUE - extern F_CPU_GET_IDD_MAX F15KmGetProcIddMax; - extern F_CPU_GET_NB_PSTATE_INFO F15KmGetNbPstateInfo; - extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate; - extern F_CPU_DISABLE_PSTATE F15DisablePstate; - extern F_CPU_TRANSITION_PSTATE F15TransitionPstate; - extern F_CPU_GET_TSC_RATE F15GetTscRate; - extern F_CPU_GET_NB_FREQ F15KmGetCurrentNbFrequency; - extern F_CPU_GET_MIN_MAX_NB_FREQ F15KmGetMinMaxNbFrequency; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo; - extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore; - extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15KmGetNumberOfPhysicalCores; - extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15KmGetApMailboxFromHardware; - extern F_CPU_SET_AP_CORE_NUMBER F15KmSetApCoreNumber; - extern F_CPU_GET_AP_CORE_NUMBER F15KmGetApCoreNumber; - extern F_CPU_TRANSFER_AP_CORE_NUMBER F15KmTransferApCoreNumber; - extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId; - extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag; - extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmSysPmTable; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData; - extern F_CPU_SET_CFOH_REG SetF15KmCacheFlushOnHaltRegister; - extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats; - extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister; - extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmMicroCodePatchesStruct; - extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmMicrocodeEquivalenceTable; - extern F_GET_EARLY_INIT_TABLE GetF15KmEarlyInitOnCoreTable; - extern CONST REGISTER_TABLE ROMDATA F15KmPciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15KmMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15KmSharedMsrRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15KmSharedMsrCuRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable; - extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable; - extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15Mod2xPackageLinkMap[]; - /** - * Core Pair and core pair primary determination table. - * - * The two fields from the core pair hardware register can be used to determine whether - * even number cores are primary or all cores are primary. It can be extended if it is - * decided to have other configs as well. The other logically possible value sets are BitMapMapping, - * but they are currently not supported by the processor. - */ - CONST CORE_PAIR_MAP ROMDATA HtFam15KmCorePairMapping[] = - { - {1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores - {3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores - {7, 7, EvenCoresMapping}, ///< 3 Compute Units all with 2 Cores - {0xF, 0xF, EvenCoresMapping}, ///< 4 Compute Units all with 2 Cores - {0x1F, 0x1F, EvenCoresMapping}, ///< 5 Compute Units all with 2 Cores - {1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core - {3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core - {7, 0, AllCoresMapping}, ///< 3 Compute Units all with 1 Core - {0xF, 0, AllCoresMapping}, ///< 4 Compute Units all with 1 Core - {0x1F, 0, AllCoresMapping}, ///< 5 Compute Units all with 1 Core - {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End - }; - - - #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F15KmRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F15PciRegisterTable, - #endif - #if MODEL_SPECIFIC_PCI == TRUE - &F15KmPciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F15MsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F15KmMsrRegisterTable, - #endif - #if MODEL_SPECIFIC_MSR == TRUE - &F15KmSharedMsrRegisterTable, - &F15KmSharedMsrCuRegisterTable, - #endif - // the end. - NULL - }; - #endif - - #if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15KmTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {HtPhyRegister, SetRegisterForHtPhyEntry}, - {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, - {DeemphasisRegister, SetRegisterForDeemphasisEntry}, - {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry}, - {ProfileFixup, SetRegisterForPerformanceProfileEntry}, - {HtHostPciRegister, SetRegisterForHtHostEntry}, - {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry}, - {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry}, - {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, - {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, - {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry}, - {TokenPciRegister, SetRegisterForTokenPciEntry}, - {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, - {HtLinkPciRegister, SetRegisterForHtLinkPciEntry}, - {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; - #endif - - CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15KmServices = - { - 0, - #if DISABLE_PSTATE == TRUE - F15DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F15TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - F15KmGetProcIddMax, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F15GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F15KmGetCurrentNbFrequency, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F15KmGetMinMaxNbFrequency, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - F15KmGetNbPstateInfo, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - F15CommonGetNbCofVidUpdate, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F15LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - F15KmGetNumberOfPhysicalCores, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - F15KmGetApMailboxFromHardware, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - F15KmSetApCoreNumber, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - F15KmGetApCoreNumber, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - F15KmTransferApCoreNumber, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F15CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - (PF_CPU_SAVE_FEATURES) CommonVoid, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - (PF_CPU_WRITE_FEATURES) CommonVoid, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F15SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F15GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetF15KmMicroCodePatchesStruct, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetF15KmMicrocodeEquivalenceTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - GetF15CacheInfo, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetF15KmSysPmTable, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF15WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - F15IsNbPstateEnabled, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F15NextLinkHasHtPhyFeats, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F15SetHtPhyRegister, - #else - (PF_SET_HT_PHY_REGISTER) CommonAssert, - #endif - #if BASE_FAMILY_PCI == TRUE - F15GetNextHtLinkFeatures, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F15KmRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15KmTableEntryTypeDescriptors, - #else - NULL, - #endif - #if MODEL_SPECIFIC_HT_PCI == TRUE - (PACKAGE_HTLINK_MAP) &HtFam15Mod2xPackageLinkMap, - #else - NULL, - #endif - (CORE_PAIR_MAP *) &HtFam15KmCorePairMapping, - InitCacheEnabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - GetF15KmEarlyInitOnCoreTable - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif - }; - - #define KM_SOCKETS 8 - #define KM_MODULES 2 - #define KM_RECOVERY_SOCKETS 1 - #define KM_RECOVERY_MODULES 1 - extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15KmLogicalIdAndRev; - #define OPT_F15_KM_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15KmLogicalIdAndRev, - #ifndef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS KM_SOCKETS - #else - #if ADVCFG_PLATFORM_SOCKETS < KM_SOCKETS - #undef ADVCFG_PLATFORM_SOCKETS - #define ADVCFG_PLATFORM_SOCKETS KM_SOCKETS - #endif - #endif - #ifndef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES KM_MODULES - #else - #if ADVCFG_PLATFORM_MODULES < KM_MODULES - #undef ADVCFG_PLATFORM_MODULES - #define ADVCFG_PLATFORM_MODULES KM_MODULES - #endif - #endif - - #if GET_PATCHES == TRUE - - #if AGESA_ENTRY_INIT_EARLY == TRUE - #if OPTION_EARLY_SAMPLES == TRUE - #endif - #endif - - CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15KmMicroCodePatchArray[] = - { - NULL - }; - - CONST UINT8 ROMDATA CpuF15KmNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15KmMicroCodePatchArray) / sizeof (CpuF15KmMicroCodePatchArray[0])) - 1); - #endif - - #define OPT_F15_KM_CPU {AMD_FAMILY_15_KM, &cpuF15KmServices}, - - #else // OPTION_FAMILY15H_KM == TRUE - #define OPT_F15_KM_CPU - #define OPT_F15_KM_ID - #endif // OPTION_FAMILY15H_KM == TRUE -#else // defined (OPTION_FAMILY15H_KM) - #define OPT_F15_KM_CPU - #define OPT_F15_KM_ID -#endif // defined (OPTION_FAMILY15H_KM) - -/* - * Install unknown family 15h support - */ - - -#if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] = - { - #if BASE_FAMILY_PCI == TRUE - &F15PciRegisterTable, - #endif - #if BASE_FAMILY_MSR == TRUE - &F15MsrRegisterTable, - #endif - // the end. - NULL - }; -#endif - -#if USES_REGISTER_TABLES == TRUE - CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] = - { - {MsrRegister, SetRegisterForMsrEntry}, - {PciRegister, SetRegisterForPciEntry}, - {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, - {HtPhyRegister, SetRegisterForHtPhyEntry}, - {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, - {DeemphasisRegister, SetRegisterForDeemphasisEntry}, - {ProfileFixup, SetRegisterForPerformanceProfileEntry}, - {HtHostPciRegister, SetRegisterForHtHostEntry}, - {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry}, - {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid}, - {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, - {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, - {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry}, - {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, - {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry}, - // End - {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} - }; -#endif - - -CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices = -{ - 0, - #if DISABLE_PSTATE == TRUE - F15DisablePstate, - #else - (PF_CPU_DISABLE_PSTATE) CommonAssert, - #endif - #if TRANSITION_PSTATE == TRUE - F15TransitionPstate, - #else - (PF_CPU_TRANSITION_PSTATE) CommonAssert, - #endif - #if PROC_IDD_MAX == TRUE - (PF_CPU_GET_IDD_MAX) CommonReturnFalse, - #else - (PF_CPU_GET_IDD_MAX) CommonAssert, - #endif - #if GET_TSC_RATE == TRUE - F15GetTscRate, - #else - (PF_CPU_GET_TSC_RATE) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - (PF_CPU_GET_NB_FREQ) CommonAssert, - #else - (PF_CPU_GET_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #else - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, - #endif - #if GET_NB_FREQ == TRUE - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #else - (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, - #endif - #if IS_NBCOF_INIT_NEEDED == TRUE - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse, - #else - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, - #endif - #if GET_NB_IDD_MAX == TRUE - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #else - (PF_CPU_GET_NB_IDD_MAX) CommonAssert, - #endif - #if AP_INITIAL_LAUNCH == TRUE - F15LaunchApCore, - #else - (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, - #endif - #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonVoid, - #else - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, - #endif - #if GET_AP_MAILBOX_FROM_HW == TRUE - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #else - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, - #endif - #if SET_AP_CORE_NUMBER == TRUE - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #else - (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, - #endif - #if GET_AP_CORE_NUMBER == TRUE - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #else - (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, - #endif - #if TRANSFER_AP_CORE_NUMBER == TRUE - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #else - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, - #endif - #if ID_POSITION_INITIAL_APICID == TRUE - F15CpuAmdCoreIdPositionInInitialApicId, - #else - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, - #endif - #if SAVE_FEATURES == TRUE - // F15SaveFeatures, - (PF_CPU_SAVE_FEATURES) CommonVoid, - #else - (PF_CPU_SAVE_FEATURES) CommonAssert, - #endif - #if WRITE_FEATURES == TRUE - // F15WriteFeatures, - (PF_CPU_WRITE_FEATURES) CommonVoid, - #else - (PF_CPU_WRITE_FEATURES) CommonAssert, - #endif - #if SET_WARM_RESET_FLAG == TRUE - F15SetAgesaWarmResetFlag, - #else - (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, - #endif - #if GET_WARM_RESET_FLAG == TRUE - F15GetAgesaWarmResetFlag, - #else - (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, - #endif - #if BRAND_STRING1 == TRUE - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if BRAND_STRING2 == TRUE - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES == TRUE - GetEmptyArray, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE - GetEmptyArray, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_CACHE_INFO == TRUE - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_SYSTEM_PM_TABLE == TRUE - GetEmptyArray, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_WHEA_INIT == TRUE - GetF15WheaInitData, - #else - (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, - #endif - #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess, - #else - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, - #endif - #if IS_NB_PSTATE_ENABLED == TRUE - F15IsNbPstateEnabled, - #else - (PF_IS_NB_PSTATE_ENABLED) CommonAssert, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F15NextLinkHasHtPhyFeats, - #else - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - #endif - #if (BASE_FAMILY_HT_PCI == TRUE) - F15SetHtPhyRegister, - #else - (PF_SET_HT_PHY_REGISTER) CommonVoid, - #endif - #if BASE_FAMILY_PCI == TRUE - F15GetNextHtLinkFeatures, - #else - (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert, - #endif - #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F15UnknownRegisterTables, - #else - NULL, - #endif - #if USES_REGISTER_TABLES == TRUE - (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors, - #else - NULL, - #endif - NULL, - NULL, - InitCacheEnabled, - #if AGESA_ENTRY_INIT_EARLY == TRUE - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #else - (PF_GET_EARLY_INIT_TABLE) CommonVoid - #endif -}; - -// Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate. -#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull) - #undef FAMILY_MMIO_BASE_MASK - #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull) -#endif - - -#undef OPT_F15_ID_TABLE -#define OPT_F15_ID_TABLE {0x15, {AMD_FAMILY_15, AMD_F15_UNKNOWN}, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))}, -#define OPT_F15_UNKNOWN_CPU {AMD_FAMILY_15, &cpuF15UnknownServices}, - -#undef OPT_F15_TABLE -#define OPT_F15_TABLE OPT_F15_OR_CPU OPT_F15_TN_CPU OPT_F15_KM_CPU OPT_F15_UNKNOWN_CPU - - -#if OPTION_G34_SOCKET_SUPPORT == TRUE - #define F15_G34_BRANDSTRING1 NULL, - #define F15_G34_BRANDSTRING2 NULL, -#else - #define F15_G34_BRANDSTRING1 - #define F15_G34_BRANDSTRING2 -#endif -#if OPTION_C32_SOCKET_SUPPORT == TRUE - #define F15_C32_BRANDSTRING1 NULL, - #define F15_C32_BRANDSTRING2 NULL, -#else - #define F15_C32_BRANDSTRING1 - #define F15_C32_BRANDSTRING2 -#endif -#if OPTION_AM3_SOCKET_SUPPORT == TRUE - #define F15_AM3_BRANDSTRING1 NULL, - #define F15_AM3_BRANDSTRING2 NULL, -#else - #define F15_AM3_BRANDSTRING1 - #define F15_AM3_BRANDSTRING2 -#endif -#if OPTION_FS1_SOCKET_SUPPORT == TRUE - #define F15_FS1_BRANDSTRING1 NULL, - #define F15_FS1_BRANDSTRING2 NULL, -#else - #define F15_FS1_BRANDSTRING1 - #define F15_FS1_BRANDSTRING2 -#endif -#if OPTION_FM2_SOCKET_SUPPORT == TRUE - #define F15_FM2_BRANDSTRING1 NULL, - #define F15_FM2_BRANDSTRING2 NULL, -#else - #define F15_FM2_BRANDSTRING1 - #define F15_FM2_BRANDSTRING2 -#endif -#if OPTION_FP2_SOCKET_SUPPORT == TRUE - #define F15_FP2_BRANDSTRING1 NULL, - #define F15_FP2_BRANDSTRING2 NULL, -#else - #define F15_FP2_BRANDSTRING1 - #define F15_FP2_BRANDSTRING2 -#endif -#if OPTION_G2012_SOCKET_SUPPORT == TRUE - #define F15_G2012_BRANDSTRING1 NULL, - #define F15_G2012_BRANDSTRING2 NULL, -#else - #define F15_G2012_BRANDSTRING1 - #define F15_G2012_BRANDSTRING2 -#endif -#if OPTION_C2012_SOCKET_SUPPORT == TRUE - #define F15_C2012_BRANDSTRING1 NULL, - #define F15_C2012_BRANDSTRING2 NULL, -#else - #define F15_C2012_BRANDSTRING1 - #define F15_C2012_BRANDSTRING2 -#endif - - -#if BRAND_STRING1 == TRUE - CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] = - { - F15_G34_BRANDSTRING1 - F15_C32_BRANDSTRING1 - F15_AM3_BRANDSTRING1 - F15_FS1_BRANDSTRING1 - F15_FM2_BRANDSTRING1 - F15_FP2_BRANDSTRING1 - F15_G2012_BRANDSTRING1 - F15_C2012_BRANDSTRING1 - }; - - CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0])); -#endif - -#if BRAND_STRING2 == TRUE - CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] = - { - F15_G34_BRANDSTRING2 - F15_C32_BRANDSTRING2 - F15_AM3_BRANDSTRING2 - F15_FS1_BRANDSTRING2 - F15_FM2_BRANDSTRING2 - F15_FP2_BRANDSTRING2 - F15_G2012_BRANDSTRING2 - F15_C2012_BRANDSTRING2 - }; - - CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0])); -#endif - -CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] = -{ - OPT_F15_OR_ID - OPT_F15_TN_ID - OPT_F15_KM_ID -}; - -#endif // _OPTION_FAMILY_15H_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionFchInstall.h deleted file mode 100644 index 715e1628d5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionFchInstall.h +++ /dev/null @@ -1,988 +0,0 @@ -/********************************************************************************* -; -; Copyright (C) 2012 Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;*********************************************************************************/ - -#ifndef _OPTION_FCH_INSTALL_H_ -#define _OPTION_FCH_INSTALL_H_ - -#include "AmdFch.h" - -#define FCH_SUPPORT FALSE - - -/* ACPI block register offset definitions */ -#define PM1_STATUS_OFFSET 0x00 -#define PM1_ENABLE_OFFSET 0x02 -#define PM_CONTROL_OFFSET 0x04 -#define PM_TIMER_OFFSET 0x08 -#define CPU_CONTROL_OFFSET 0x10 -#define EVENT_STATUS_OFFSET 0x20 -#define EVENT_ENABLE_OFFSET 0x24 - - -#if FCH_SUPPORT == TRUE - /* - * FCH subfunctions - */ - #ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - extern FCH_TASK_ENTRY FchInitResetHwAcpiP; - extern FCH_TASK_ENTRY FchInitResetHwAcpi; - extern FCH_TASK_ENTRY FchInitResetAb; - extern FCH_TASK_ENTRY FchInitResetSpi; - extern FCH_TASK_ENTRY FchInitResetGec; - extern FCH_TASK_ENTRY FchInitResetSata; - extern FCH_TASK_ENTRY FchInitResetLpc; - extern FCH_TASK_ENTRY FchInitResetPcib; - extern FCH_TASK_ENTRY FchInitResetPcie; - extern FCH_TASK_ENTRY FchInitResetGpp; - extern FCH_TASK_ENTRY FchInitResetUsb; - extern FCH_TASK_ENTRY FchInitResetEhci; - extern FCH_TASK_ENTRY FchInitResetOhci; - extern FCH_TASK_ENTRY FchInitResetXhci; - extern FCH_TASK_ENTRY FchInitResetImc; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - extern FCH_TASK_ENTRY FchInitEnvUsbXhci; - extern FCH_TASK_ENTRY FchInitEnvUsbOhci; - extern FCH_TASK_ENTRY FchInitEnvUsbEhci; - extern FCH_TASK_ENTRY FchInitEnvUsb; - extern FCH_TASK_ENTRY FchInitEnvAb; - extern FCH_TASK_ENTRY FchInitEnvGpp; - extern FCH_TASK_ENTRY FchInitEnvPcie; - extern FCH_TASK_ENTRY FchInitEnvPcib; - extern FCH_TASK_ENTRY FchInitEnvHwAcpiP; - extern FCH_TASK_ENTRY FchInitEnvHwAcpi; - extern FCH_TASK_ENTRY FchInitEnvAbSpecial; - extern FCH_TASK_ENTRY FchInitEnvSpi; - extern FCH_TASK_ENTRY FchInitEnvGec; - extern FCH_TASK_ENTRY FchInitEnvSata; - extern FCH_TASK_ENTRY FchInitEnvIde; - extern FCH_TASK_ENTRY FchInitEnvSd; - extern FCH_TASK_ENTRY FchInitEnvIr; - extern FCH_TASK_ENTRY FchInitEnvAzalia; - extern FCH_TASK_ENTRY FchInitEnvHwm; - extern FCH_TASK_ENTRY FchInitEnvImc; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_MID - #if AGESA_ENTRY_INIT_MID == TRUE - extern FCH_TASK_ENTRY FchInitMidHwm; - extern FCH_TASK_ENTRY FchInitMidAzalia; - extern FCH_TASK_ENTRY FchInitMidGec; - extern FCH_TASK_ENTRY FchInitMidSata; - extern FCH_TASK_ENTRY FchInitMidIde; - extern FCH_TASK_ENTRY FchInitMidAb; - extern FCH_TASK_ENTRY FchInitMidUsb; - extern FCH_TASK_ENTRY FchInitMidUsbEhci; - extern FCH_TASK_ENTRY FchInitMidUsbOhci; - extern FCH_TASK_ENTRY FchInitMidUsbXhci; - extern FCH_TASK_ENTRY FchInitMidImc; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - extern FCH_TASK_ENTRY FchInitLateHwAcpi; - extern FCH_TASK_ENTRY FchInitLateSpi; - extern FCH_TASK_ENTRY FchInitLateGec; - extern FCH_TASK_ENTRY FchInitLateSata; - extern FCH_TASK_ENTRY FchInitLateIde; - extern FCH_TASK_ENTRY FchInitLatePcib; - extern FCH_TASK_ENTRY FchInitLateAb; - extern FCH_TASK_ENTRY FchInitLatePcie; - extern FCH_TASK_ENTRY FchInitLateGpp; - extern FCH_TASK_ENTRY FchInitLateUsb; - extern FCH_TASK_ENTRY FchInitLateUsbEhci; - extern FCH_TASK_ENTRY FchInitLateUsbOhci; - extern FCH_TASK_ENTRY FchInitLateUsbXhci; - extern FCH_TASK_ENTRY FchInitLateImc; - extern FCH_TASK_ENTRY FchInitLateAzalia; - extern FCH_TASK_ENTRY FchInitLateHwm; - #endif - #endif - - extern FCH_TASK_ENTRY FchTaskDummy; - extern FCH_TASK_ENTRY FchGppHotplugSmiCallback; - /* FCH Interface entries */ - extern FCH_INIT CommonFchInitStub; - - /* FCH Interface entries */ - #ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - extern FCH_INIT FchInitReset; - extern FCH_INIT FchResetConstructor; - - #define FP_FCH_INIT_RESET &FchInitReset - #define FP_FCH_INIT_RESET_CONSTRUCT &FchResetConstructor - #else - #define FP_FCH_INIT_RESET &CommonFchInitStub - #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - extern FCH_INIT FchInitEnv; - extern FCH_INIT FchEnvConstructor; - - #define FP_FCH_INIT_ENV &FchInitEnv - #define FP_FCH_INIT_ENV_CONSTRUCT &FchEnvConstructor - #else - #define FP_FCH_INIT_ENV &CommonFchInitStub - #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_MID - #if AGESA_ENTRY_INIT_MID == TRUE - extern FCH_INIT FchInitMid; - extern FCH_INIT FchMidConstructor; - - #define FP_FCH_INIT_MID &FchInitMid - #define FP_FCH_INIT_MID_CONSTRUCT &FchMidConstructor - #else - #define FP_FCH_INIT_MID &CommonFchInitStub - #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - extern FCH_INIT FchInitLate; - extern FCH_INIT FchLateConstructor; - - #define FP_FCH_INIT_LATE &FchInitLate - #define FP_FCH_INIT_LATE_CONSTRUCT &FchLateConstructor - #else - #define FP_FCH_INIT_LATE &CommonFchInitStub - #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub - #endif - #endif - - /* FCH subcomponent build options */ - #undef FCH_NO_HWACPI_SUPPORT - #undef FCH_NO_AB_SUPPORT - #undef FCH_NO_SPI_SUPPORT - #undef FCH_NO_GEC_SUPPORT - #undef FCH_NO_SATA_SUPPORT - #undef FCH_NO_IDE_SUPPORT - #undef FCH_NO_LPC_SUPPORT - #undef FCH_NO_PCIB_SUPPORT - #undef FCH_NO_PCIE_SUPPORT - #undef FCH_NO_GPP_SUPPORT - #undef FCH_NO_USB_SUPPORT - #undef FCH_NO_EHCI_SUPPORT - #undef FCH_NO_OHCI_SUPPORT - #undef FCH_NO_XHCI_SUPPORT - #undef FCH_NO_IMC_SUPPORT - #undef FCH_NO_SD_SUPPORT - #undef FCH_NO_IR_SUPPORT - #undef FCH_NO_AZALIA_SUPPORT - #undef FCH_NO_HWM_SUPPORT - - // - // Installable blocks depending on build switches - // - #ifndef FCH_NO_HWACPI_SUPPORT - #define BLOCK_HWACPI_SIZE sizeof (FCH_ACPI) - #define InstallFchInitResetHwAcpiP &FchInitResetHwAcpiP - #define InstallFchInitResetHwAcpi &FchInitResetHwAcpi - #define InstallFchInitEnvHwAcpiP &FchInitEnvHwAcpiP - #define InstallFchInitEnvHwAcpi &FchInitEnvHwAcpi - #define InstallFchInitMidHwAcpi &FchTaskDummy - #define InstallFchInitLateHwAcpi &FchInitLateHwAcpi - #else - #define BLOCK_HWACPI_SIZE 0 - #define InstallFchInitResetHwAcpiP &FchTaskDummy - #define InstallFchInitResetHwAcpi &FchTaskDummy - #define InstallFchInitEnvHwAcpi &FchTaskDummy - #define InstallFchInitMidHwAcpi &FchTaskDummy - #define InstallFchInitLateHwAcpi &FchTaskDummy - #endif - - #ifndef FCH_NO_AB_SUPPORT - #define BLOCK_AB_SIZE sizeof (FCH_AB) - #define InstallFchInitResetAb &FchInitResetAb - #define InstallFchInitEnvAb &FchInitEnvAb - #define InstallFchInitEnvAbS &FchInitEnvAbSpecial - #define InstallFchInitMidAb &FchInitMidAb - #define InstallFchInitLateAb &FchInitLateAb - #else - #define BLOCK_AB_SIZE 0 - #define InstallFchInitResetAb &FchTaskDummy - #define InstallFchInitEnvAb &FchTaskDummy - #define InstallFchInitEnvAbS &FchTaskDummy - #define InstallFchInitMidAb &FchTaskDummy - #define InstallFchInitLateAb &FchTaskDummy - #endif - - #ifndef FCH_NO_SPI_SUPPORT - #define BLOCK_SPI_SIZE sizeof (FCH_SPI) - #define InstallFchInitResetSpi &FchInitResetSpi - #define InstallFchInitEnvSpi &FchInitEnvSpi - #define InstallFchInitMidSpi &FchTaskDummy - #define InstallFchInitLateSpi &FchInitLateSpi - #else - #define BLOCK_SPI_SIZE 0 - #define InstallFchInitResetSpi &FchTaskDummy - #define InstallFchInitEnvSpi &FchTaskDummy - #define InstallFchInitMidSpi &FchTaskDummy - #define InstallFchInitLateSpi &FchTaskDummy - #endif - - #ifndef FCH_NO_GEC_SUPPORT - #define BLOCK_GEC_SIZE sizeof (FCH_GEC) - #define InstallFchInitResetGec &FchInitResetGec - #define InstallFchInitEnvGec &FchInitEnvGec - #define InstallFchInitMidGec &FchInitMidGec - #define InstallFchInitLateGec &FchInitLateGec - #else - #define BLOCK_GEC_SIZE 0 - #define InstallFchInitResetGec &FchTaskDummy - #define InstallFchInitEnvGec &FchTaskDummy - #define InstallFchInitMidGec &FchTaskDummy - #define InstallFchInitLateGec &FchTaskDummy - #endif - - #ifndef FCH_NO_SATA_SUPPORT - #define BLOCK_SATA_SIZE sizeof (FCH_SATA) - #define InstallFchInitResetSata &FchInitResetSata - #define InstallFchInitEnvSata &FchInitEnvSata - #define InstallFchInitMidSata &FchInitMidSata - #define InstallFchInitLateSata &FchInitLateSata - #else - #define BLOCK_SATA_SIZE 0 - #define InstallFchInitResetSata &FchTaskDummy - #define InstallFchInitEnvSata &FchTaskDummy - #define InstallFchInitMidSata &FchTaskDummy - #define InstallFchInitLateSata &FchTaskDummy - #endif - - #ifndef FCH_NO_IDE_SUPPORT - #define BLOCK_IDE_SIZE sizeof (FCH_IDE) - #define InstallFchInitResetIde &FchTaskDummy - #define InstallFchInitEnvIde &FchInitEnvIde - #define InstallFchInitMidIde &FchInitMidIde - #define InstallFchInitLateIde &FchInitLateIde - #else - #define BLOCK_IDE_SIZE 0 - #define InstallFchInitResetIde &FchTaskDummy - #define InstallFchInitEnvIde &FchTaskDummy - #define InstallFchInitMidIde &FchTaskDummy - #define InstallFchInitLateIde &FchTaskDummy - #endif - - #ifndef FCH_NO_LPC_SUPPORT - #define BLOCK_LPC_SIZE sizeof (FCH_LPC) - #define InstallFchInitResetLpc &FchInitResetLpc - #define InstallFchInitEnvLpc &FchTaskDummy - #define InstallFchInitMidLpc &FchTaskDummy - #define InstallFchInitLateLpc &FchTaskDummy - #else - #define BLOCK_LPC_SIZE 0 - #define InstallFchInitResetLpc &FchTaskDummy - #define InstallFchInitEnvLpc &FchTaskDummy - #define InstallFchInitMidLpc &FchTaskDummy - #define InstallFchInitLateLpc &FchTaskDummy - #endif - - #ifndef FCH_NO_PCIB_SUPPORT - #define BLOCK_PCIB_SIZE sizeof (FCH_PCIB) - #define InstallFchInitResetPcib &FchInitResetPcib - #define InstallFchInitEnvPcib &FchInitEnvPcib - #define InstallFchInitMidPcib &FchTaskDummy - #define InstallFchInitLatePcib &FchInitLatePcib - #else - #define BLOCK_PCIB_SIZE 0 - #define InstallFchInitResetPcib &FchTaskDummy - #define InstallFchInitEnvPcib &FchTaskDummy - #define InstallFchInitMidPcib &FchTaskDummy - #define InstallFchInitLatePcib &FchTaskDummy - #endif - - #ifndef FCH_NO_PCIE_SUPPORT - #define InstallFchInitResetPcie &FchInitResetPcie - #define InstallFchInitEnvPcie &FchInitEnvPcie - #define InstallFchInitMidPcie &FchTaskDummy - #define InstallFchInitLatePcie &FchInitLatePcie - #else - #define InstallFchInitResetPcie &FchTaskDummy - #define InstallFchInitEnvPcie &FchTaskDummy - #define InstallFchInitMidPcie &FchTaskDummy - #define InstallFchInitLatePcie &FchTaskDummy - #endif - - #ifndef FCH_NO_GPP_SUPPORT - #define BLOCK_GPP_SIZE sizeof (FCH_GPP) - #define InstallFchInitResetGpp &FchInitResetGpp - #define InstallFchInitEnvGpp &FchInitEnvGpp - #define InstallFchInitMidGpp &FchTaskDummy - #define InstallFchInitLateGpp &FchInitLateGpp - #define InstallHpSmiCallback &FchGppHotplugSmiCallback - #else - #define BLOCK_GPP_SIZE 0 - #define InstallFchInitResetGpp &FchTaskDummy - #define InstallFchInitEnvGpp &FchTaskDummy - #define InstallFchInitMidGpp &FchTaskDummy - #define InstallFchInitLateGpp &FchTaskDummy - #define InstallHpSmiCallback &FchTaskDummy - #endif - - #ifndef FCH_NO_USB_SUPPORT - #define BLOCK_USB_SIZE sizeof (FCH_USB) - #define InstallFchInitResetUsb &FchInitResetUsb - #define InstallFchInitEnvUsb &FchInitEnvUsb - #define InstallFchInitMidUsb &FchInitMidUsb - #define InstallFchInitLateUsb &FchInitLateUsb - #else - #define BLOCK_USB_SIZE 0 - #define InstallFchInitResetUsb &FchTaskDummy - #define InstallFchInitEnvUsb &FchTaskDummy - #define InstallFchInitMidUsb &FchTaskDummy - #define InstallFchInitLateUsb &FchTaskDummy - #endif - - #ifndef FCH_NO_EHCI_SUPPORT - #define InstallFchInitResetUsbEhci &FchInitResetEhci - #define InstallFchInitEnvUsbEhci &FchInitEnvUsbEhci - #define InstallFchInitMidUsbEhci &FchInitMidUsbEhci - #define InstallFchInitLateUsbEhci &FchInitLateUsbEhci - #else - #define InstallFchInitResetUsbEhci &FchTaskDummy - #define InstallFchInitEnvUsbEhci &FchTaskDummy - #define InstallFchInitMidUsbEhci &FchTaskDummy - #define InstallFchInitLateUsbEhci &FchTaskDummy - #endif - - #ifndef FCH_NO_OHCI_SUPPORT - #define InstallFchInitResetUsbOhci &FchInitResetOhci - #define InstallFchInitEnvUsbOhci &FchInitEnvUsbOhci - #define InstallFchInitMidUsbOhci &FchInitMidUsbOhci - #define InstallFchInitLateUsbOhci &FchInitLateUsbOhci - #else - #define InstallFchInitResetUsbOhci &FchTaskDummy - #define InstallFchInitEnvUsbOhci &FchTaskDummy - #define InstallFchInitMidUsbOhci &FchTaskDummy - #define InstallFchInitLateUsbOhci &FchTaskDummy - #endif - - #ifndef FCH_NO_XHCI_SUPPORT - #define InstallFchInitResetUsbXhci &FchInitResetXhci - #define InstallFchInitEnvUsbXhci &FchInitEnvUsbXhci - #define InstallFchInitMidUsbXhci &FchInitMidUsbXhci - #define InstallFchInitLateUsbXhci &FchInitLateUsbXhci - #else - #define InstallFchInitResetUsbXhci &FchTaskDummy - #define InstallFchInitEnvUsbXhci &FchTaskDummy - #define InstallFchInitMidUsbXhci &FchTaskDummy - #define InstallFchInitLateUsbXhci &FchTaskDummy - #endif - - #ifndef FCH_NO_IMC_SUPPORT - #define BLOCK_IMC_SIZE sizeof (FCH_IMC) - #define InstallFchInitResetImc &FchInitResetImc - #define InstallFchInitEnvImc &FchInitEnvImc - #define InstallFchInitMidImc &FchInitMidImc - #define InstallFchInitLateImc &FchInitLateImc - #else - #define BLOCK_IMC_SIZE 0 - #define InstallFchInitResetImc &FchTaskDummy - #define InstallFchInitEnvImc &FchTaskDummy - #define InstallFchInitMidImc &FchTaskDummy - #define InstallFchInitLateImc &FchTaskDummy - #endif - - - #ifndef FCH_NO_SD_SUPPORT - #define BLOCK_SD_SIZE sizeof (FCH_SD) - #define InstallFchInitResetSd &FchTaskDummy - #define InstallFchInitEnvSd &FchInitEnvSd - #define InstallFchInitMidSd &FchTaskDummy - #define InstallFchInitLateSd &FchTaskDummy - #else - #define BLOCK_SD_SIZE 0 - #define InstallFchInitResetSd &FchTaskDummy - #define InstallFchInitEnvSd &FchTaskDummy - #define InstallFchInitMidSd &FchTaskDummy - #define InstallFchInitLateSd &FchTaskDummy - #endif - - #ifndef FCH_NO_IR_SUPPORT - #define BLOCK_IR_SIZE sizeof (FCH_IR) - #define InstallFchInitResetIr &FchTaskDummy - #define InstallFchInitEnvIr &FchInitEnvIr - #define InstallFchInitMidIr &FchTaskDummy - #define InstallFchInitLateIr &FchTaskDummy - #else - #define BLOCK_IR_SIZE 0 - #define InstallFchInitResetIr &FchTaskDummy - #define InstallFchInitEnvIr &FchTaskDummy - #define InstallFchInitMidIr &FchTaskDummy - #define InstallFchInitLateIr &FchTaskDummy - #endif - - #ifndef FCH_NO_AZALIA_SUPPORT - #define BLOCK_AZALIA_SIZE sizeof (FCH_AZALIA) - #define InstallFchInitResetAzalia &FchTaskDummy - #define InstallFchInitEnvAzalia &FchInitEnvAzalia - #define InstallFchInitMidAzalia &FchInitMidAzalia - #define InstallFchInitLateAzalia &FchInitLateAzalia - #else - #define BLOCK_AZALIA_SIZE 0 - #define InstallFchInitResetAzalia &FchTaskDummy - #define InstallFchInitEnvAzalia &FchTaskDummy - #define InstallFchInitMidAzalia &FchTaskDummy - #define InstallFchInitLateAzalia &FchTaskDummy - #endif - - #ifndef FCH_NO_HWM_SUPPORT - #define BLOCK_HWM_SIZE sizeof (FCH_HWM) - #define InstallFchInitResetHwm &FchTaskDummy - #define InstallFchInitEnvHwm &FchInitEnvHwm - #define InstallFchInitMidHwm &FchInitMidHwm - #define InstallFchInitLateHwm &FchInitLateHwm - #else - #define InstallFchInitResetHwm &FchTaskDummy - #define InstallFchInitEnvHwm &FchTaskDummy - #define InstallFchInitMidHwm &FchTaskDummy - #define InstallFchInitLateHwm &FchTaskDummy - #endif - - - #define BLOCK_SMBUS_SIZE sizeof (FCH_SMBUS) - #define BLOCK_HPET_SIZE sizeof (FCH_HPET) - #define BLOCK_GCPU_SIZE sizeof (FCH_GCPU) - #define BLOCK_SDB_SIZE sizeof (FCH_SERIALDB) - #define BLOCK_MISC_SIZE sizeof (FCH_MISC) - - - // Optionally declare OEM hooks after each phase - #ifndef FCH_INIT_RESET_HOOK - #define InstallFchInitResetHook FchTaskDummy - #else - #define InstallFchInitResetHook OemFchInitResetHook - #endif - - - // - // Define FCH build time options and configurations - // - #ifdef BLDCFG_SMBUS0_BASE_ADDRESS - #define CFG_SMBUS0_BASE_ADDRESS BLDCFG_SMBUS0_BASE_ADDRESS - #else - #define CFG_SMBUS0_BASE_ADDRESS DFLT_SMBUS0_BASE_ADDRESS - #endif - - #ifdef BLDCFG_SMBUS1_BASE_ADDRESS - #define CFG_SMBUS1_BASE_ADDRESS BLDCFG_SMBUS1_BASE_ADDRESS - #else - #define CFG_SMBUS1_BASE_ADDRESS DFLT_SMBUS1_BASE_ADDRESS - #endif - - #ifdef BLDCFG_SIO_PME_BASE_ADDRESS - #define CFG_SIO_PME_BASE_ADDRESS BLDCFG_SIO_PME_BASE_ADDRESS - #else - #define CFG_SIO_PME_BASE_ADDRESS DFLT_SIO_PME_BASE_ADDRESS - #endif - - #ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS - #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS - #else - #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS - #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS - #else - #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS - #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS - #else - #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS DFLT_ACPI_PM_TMR_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS - #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS - #else - #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS - #endif - #ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS - #define CFG_ACPI_GPE0_BLOCK_ADDRESS BLDCFG_ACPI_GPE0_BLOCK_ADDRESS - #else - #define CFG_ACPI_GPE0_BLOCK_ADDRESS DFLT_ACPI_GPE0_BLOCK_ADDRESS - #endif - - - #ifdef BLDCFG_WATCHDOG_TIMER_BASE - #define CFG_WATCHDOG_TIMER_BASE BLDCFG_WATCHDOG_TIMER_BASE - #else - #define CFG_WATCHDOG_TIMER_BASE DFLT_WATCHDOG_TIMER_BASE_ADDRESS - #endif - - #ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS - #define CFG_ACPI_PMA_CNTBLK_ADDRESS BLDCFG_ACPI_PMA_BLK_ADDRESS - #else - #define CFG_ACPI_PMA_CNTBLK_ADDRESS DFLT_ACPI_PMA_CNT_BLK_ADDRESS - #endif - - #ifdef BLDCFG_SMI_CMD_PORT_ADDRESS - #define CFG_SMI_CMD_PORT_ADDRESS BLDCFG_SMI_CMD_PORT_ADDRESS - #else - #define CFG_SMI_CMD_PORT_ADDRESS DFLT_SMI_CMD_PORT - #endif - - #ifdef BLDCFG_ROM_BASE_ADDRESS - #define CFG_SPI_ROM_BASE_ADDRESS BLDCFG_ROM_BASE_ADDRESS - #else - #define CFG_SPI_ROM_BASE_ADDRESS DFLT_SPI_BASE_ADDRESS - #endif - - #ifdef BLDCFG_GEC_SHADOW_ROM_BASE - #define CFG_GEC_SHADOW_ROM_BASE BLDCFG_GEC_SHADOW_ROM_BASE - #else - #define CFG_GEC_SHADOW_ROM_BASE DFLT_GEC_BASE_ADDRESS - #endif - - #ifdef BLDCFG_HPET_BASE_ADDRESS - #define CFG_HPET_BASE_ADDRESS BLDCFG_HPET_BASE_ADDRESS - #else - #define CFG_HPET_BASE_ADDRESS DFLT_HPET_BASE_ADDRESS - #endif - - #ifdef BLDCFG_AZALIA_SSID - #define CFG_AZALIA_SSID BLDCFG_AZALIA_SSID - #else - #define CFG_AZALIA_SSID DFLT_AZALIA_SSID - #endif - - #ifdef BLDCFG_SMBUS_SSID - #define CFG_SMBUS_SSID BLDCFG_SMBUS_SSID - #else - #define CFG_SMBUS_SSID DFLT_SMBUS_SSID - #endif - - #ifdef BLDCFG_IDE_SSID - #define CFG_IDE_SSID BLDCFG_IDE_SSID - #else - #define CFG_IDE_SSID DFLT_IDE_SSID - #endif - - #ifdef BLDCFG_SATA_AHCI_SSID - #define CFG_SATA_AHCI_SSID BLDCFG_SATA_AHCI_SSID - #else - #define CFG_SATA_AHCI_SSID DFLT_SATA_AHCI_SSID - #endif - - #ifdef BLDCFG_SATA_IDE_SSID - #define CFG_SATA_IDE_SSID BLDCFG_SATA_IDE_SSID - #else - #define CFG_SATA_IDE_SSID DFLT_SATA_IDE_SSID - #endif - - #ifdef BLDCFG_SATA_RAID5_SSID - #define CFG_SATA_RAID5_SSID BLDCFG_SATA_RAID5_SSID - #else - #define CFG_SATA_RAID5_SSID DFLT_SATA_RAID5_SSID - #endif - - #ifdef BLDCFG_SATA_RAID_SSID - #define CFG_SATA_RAID_SSID BLDCFG_SATA_RAID_SSID - #else - #define CFG_SATA_RAID_SSID DFLT_SATA_RAID_SSID - #endif - - #ifdef BLDCFG_EHCI_SSID - #define CFG_EHCI_SSID BLDCFG_EHCI_SSID - #else - #define CFG_EHCI_SSID DFLT_EHCI_SSID - #endif - - #ifdef BLDCFG_OHCI_SSID - #define CFG_OHCI_SSID BLDCFG_OHCI_SSID - #else - #define CFG_OHCI_SSID DFLT_OHCI_SSID - #endif - - #ifdef BLDCFG_LPC_SSID - #define CFG_LPC_SSID BLDCFG_LPC_SSID - #else - #define CFG_LPC_SSID DFLT_LPC_SSID - #endif - - #ifdef BLDCFG_SD_SSID - #define CFG_SD_SSID BLDCFG_SD_SSID - #else - #define CFG_SD_SSID DFLT_SD_SSID - #endif - - #ifdef BLDCFG_XHCI_SSID - #define CFG_XHCI_SSID BLDCFG_XHCI_SSID - #else - #define CFG_XHCI_SSID DFLT_XHCI_SSID - #endif - - #ifdef BLDCFG_FCH_PORT80_BEHIND_PCIB - #define CFG_FCH_PORT80_BEHIND_PCIB BLDCFG_FCH_PORT80_BEHIND_PCIB - #else - #define CFG_FCH_PORT80_BEHIND_PCIB DFLT_FCH_PORT80_BEHIND_PCIB - #endif - - #ifdef BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP - #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP - #else - #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP - #endif - - #ifdef BLDCFG_FCH_GPP_LINK_CONFIG - #define CFG_FCH_GPP_LINK_CONFIG BLDCFG_FCH_GPP_LINK_CONFIG - #else - #define CFG_FCH_GPP_LINK_CONFIG DFLT_FCH_GPP_LINK_CONFIG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT0_PRESENT - #define CFG_FCH_GPP_PORT0_PRESENT BLDCFG_FCH_GPP_PORT0_PRESENT - #else - #define CFG_FCH_GPP_PORT0_PRESENT DFLT_FCH_GPP_PORT0_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT1_PRESENT - #define CFG_FCH_GPP_PORT1_PRESENT BLDCFG_FCH_GPP_PORT1_PRESENT - #else - #define CFG_FCH_GPP_PORT1_PRESENT DFLT_FCH_GPP_PORT1_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT2_PRESENT - #define CFG_FCH_GPP_PORT2_PRESENT BLDCFG_FCH_GPP_PORT2_PRESENT - #else - #define CFG_FCH_GPP_PORT2_PRESENT DFLT_FCH_GPP_PORT2_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT3_PRESENT - #define CFG_FCH_GPP_PORT3_PRESENT BLDCFG_FCH_GPP_PORT3_PRESENT - #else - #define CFG_FCH_GPP_PORT3_PRESENT DFLT_FCH_GPP_PORT3_PRESENT - #endif - - #ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG - #define CFG_FCH_GPP_PORT0_HOTPLUG BLDCFG_FCH_GPP_PORT0_HOTPLUG - #else - #define CFG_FCH_GPP_PORT0_HOTPLUG DFLT_FCH_GPP_PORT0_HOTPLUG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG - #define CFG_FCH_GPP_PORT1_HOTPLUG BLDCFG_FCH_GPP_PORT1_HOTPLUG - #else - #define CFG_FCH_GPP_PORT1_HOTPLUG DFLT_FCH_GPP_PORT1_HOTPLUG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG - #define CFG_FCH_GPP_PORT2_HOTPLUG BLDCFG_FCH_GPP_PORT2_HOTPLUG - #else - #define CFG_FCH_GPP_PORT2_HOTPLUG DFLT_FCH_GPP_PORT2_HOTPLUG - #endif - - #ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG - #define CFG_FCH_GPP_PORT3_HOTPLUG BLDCFG_FCH_GPP_PORT3_HOTPLUG - #else - #define CFG_FCH_GPP_PORT3_HOTPLUG DFLT_FCH_GPP_PORT3_HOTPLUG - #endif - - #ifdef BLDCFG_FCH_ESATA_PORT_BITMAP - #define CFG_FCH_ESATA_PORT_BITMAP BLDCFG_FCH_ESATA_PORT_BITMAP - #else - #define CFG_FCH_ESATA_PORT_BITMAP 0 - #endif - - #ifdef BLDCFG_FCH_IR_PIN_CONTROL - #define CFG_FCH_IR_PIN_CONTROL BLDCFG_FCH_IR_PIN_CONTROL - #else - #define CFG_FCH_IR_PIN_CONTROL (BIT5 | BIT1 | BIT0) - #endif - - #ifdef BLDCFG_FCH_SD_CLOCK_CONTROL - #define CFG_FCH_SD_CLOCK_CONTROL BLDCFG_FCH_SD_CLOCK_CONTROL - #else - #define CFG_FCH_SD_CLOCK_CONTROL Sd50MhzTraceCableLengthWithinSixInches - #endif - - #ifdef BLDCFG_FCH_SCI_MAP_LIST - #define CFG_FCH_SCI_MAP_LIST BLDCFG_FCH_SCI_MAP_LIST - #else - #define CFG_FCH_SCI_MAP_LIST NULL - #endif - - #ifdef BLDCFG_FCH_SATA_PHY_LIST - #define CFG_FCH_SATA_PHY_LIST BLDCFG_FCH_SATA_PHY_LIST - #else - #define CFG_FCH_SATA_PHY_LIST NULL - #endif - - #ifdef BLDCFG_FCH_GPIO_CONTROL_LIST - #define CFG_FCH_GPIO_CONTROL_LIST BLDCFG_FCH_GPIO_CONTROL_LIST - #else - #define CFG_FCH_GPIO_CONTROL_LIST NULL - #endif - - - #ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - // - // Define task list for InitReset phase - // - FCH_TASK_ENTRY ROMDATA *FchInitResetTaskTable[] = { - InstallFchInitResetHwAcpiP, - InstallFchInitResetAb, - InstallFchInitResetSpi, - InstallFchInitResetGec, - InstallFchInitResetHwAcpi, - InstallFchInitResetSata, - InstallFchInitResetLpc, - InstallFchInitResetPcib, - InstallFchInitResetPcie, - InstallFchInitResetGpp, - InstallFchInitResetUsb, - InstallFchInitResetUsbEhci, - InstallFchInitResetUsbOhci, - InstallFchInitResetUsbXhci, - InstallFchInitResetImc, - NULL - }; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - // - // Define task list for InitEnv phase - // - FCH_TASK_ENTRY ROMDATA *FchInitEnvTaskTable[] = { - InstallFchInitEnvHwAcpiP, - InstallFchInitEnvPcib, - InstallFchInitEnvPcie, - InstallFchInitEnvIr, - InstallFchInitEnvHwAcpi, - InstallFchInitEnvSpi, - InstallFchInitEnvSd, - InstallFchInitEnvImc, - InstallFchInitEnvUsb, - InstallFchInitEnvUsbEhci, - InstallFchInitEnvUsbOhci, - InstallFchInitEnvUsbXhci, - InstallFchInitEnvSata, - InstallFchInitEnvIde, - InstallFchInitEnvGec, - InstallFchInitEnvAzalia, - InstallFchInitEnvAb, - InstallFchInitEnvGpp, - InstallFchInitEnvAbS, - InstallFchInitEnvHwm, - NULL - }; - #endif - #endif - - - #ifdef AGESA_ENTRY_INIT_MID - #if AGESA_ENTRY_INIT_MID == TRUE - // - // Define task list for InitMid phase - // - FCH_TASK_ENTRY ROMDATA *FchInitMidTaskTable[] = { - InstallFchInitMidImc, - InstallFchInitMidUsb, - InstallFchInitMidUsbEhci, - InstallFchInitMidUsbOhci, - InstallFchInitMidUsbXhci, - InstallFchInitMidSata, - InstallFchInitMidIde, - InstallFchInitMidGec, - InstallFchInitMidAzalia, - InstallFchInitMidHwm, - NULL - }; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - // - // Define task list for InitLate phase - // - FCH_TASK_ENTRY ROMDATA *FchInitLateTaskTable[] = { - InstallFchInitLatePcie, - InstallFchInitLatePcib, - InstallFchInitLateSpi, - InstallFchInitLateUsb, - InstallFchInitLateUsbEhci, - InstallFchInitLateUsbOhci, - InstallFchInitLateUsbXhci, - InstallFchInitLateSata, - InstallFchInitLateIde, - InstallFchInitLateGec, - InstallFchInitLateAzalia, - InstallFchInitLateImc, - InstallFchInitLateHwm, - InstallFchInitLateGpp, - InstallFchInitLateHwAcpi, - NULL - }; - #endif - #endif - - - #ifdef AGESA_ENTRY_INIT_ENV - #if AGESA_ENTRY_INIT_ENV == TRUE - // - // Define task list for S3 resume before PCI phase - // - FCH_TASK_ENTRY ROMDATA *FchInitS3EarlyTaskTable[] = { - InstallFchInitEnvPcie, - InstallFchInitEnvPcib, - InstallFchInitEnvIr, - InstallFchInitEnvHwAcpi, - InstallFchInitEnvSpi, - InstallFchInitEnvSd, - InstallFchInitEnvUsb, - InstallFchInitEnvSata, - InstallFchInitEnvIde, - InstallFchInitEnvGec, - InstallFchInitEnvAzalia, - InstallFchInitEnvAb, - InstallFchInitEnvGpp, - InstallFchInitEnvAbS, - NULL - }; - #endif - #endif - - #ifdef AGESA_ENTRY_INIT_LATE - #if AGESA_ENTRY_INIT_LATE == TRUE - // - // Define task list for S3 resume after PCI phase - // - FCH_TASK_ENTRY ROMDATA *FchInitS3LateTaskTable[] = { - InstallFchInitLatePcie, - InstallFchInitLatePcib, - InstallFchInitLateSpi, - InstallFchInitLateUsb, - InstallFchInitLateUsbEhci, - InstallFchInitLateUsbOhci, - InstallFchInitLateUsbXhci, - InstallFchInitMidSata, - InstallFchInitMidIde, - InstallFchInitMidGec, - InstallFchInitMidAzalia, - InstallFchInitLateSata, - InstallFchInitLateIde, - InstallFchInitLateHwAcpi, - InstallFchInitEnvHwm, - InstallFchInitLateHwm, - NULL - }; - #endif - #endif - FCH_TASK_ENTRY *FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback; - - -#else // FCH_SUPPORT == FALSE - /* FCH Interface entries */ - extern FCH_INIT CommonFchInitStub; - - #define FP_FCH_INIT_RESET &CommonFchInitStub - #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub - #define FP_FCH_INIT_ENV &CommonFchInitStub - #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub - #define FP_FCH_INIT_MID &CommonFchInitStub - #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub - #define FP_FCH_INIT_LATE &CommonFchInitStub - #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub - - #define CFG_SMBUS0_BASE_ADDRESS 0 - #define CFG_SMBUS1_BASE_ADDRESS 0 - #define CFG_SIO_PME_BASE_ADDRESS 0 - #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0 - #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0 - #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS 0 - #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0 - #define CFG_ACPI_GPE0_BLOCK_ADDRESS 0 - #define CFG_SPI_ROM_BASE_ADDRESS 0 - #define CFG_WATCHDOG_TIMER_BASE 0 - #define CFG_HPET_BASE_ADDRESS 0 - #define CFG_SMI_CMD_PORT_ADDRESS 0 - #define CFG_ACPI_PMA_CNTBLK_ADDRESS 0 - #define CFG_GEC_SHADOW_ROM_BASE 0 - #define CFG_AZALIA_SSID 0 - #define CFG_SMBUS_SSID 0 - #define CFG_IDE_SSID 0 - #define CFG_SATA_AHCI_SSID 0 - #define CFG_SATA_IDE_SSID 0 - #define CFG_SATA_RAID5_SSID 0 - #define CFG_SATA_RAID_SSID 0 - #define CFG_EHCI_SSID 0 - #define CFG_OHCI_SSID 0 - #define CFG_LPC_SSID 0 - #define CFG_SD_SSID 0 - #define CFG_XHCI_SSID 0 - #define CFG_FCH_PORT80_BEHIND_PCIB 0 - #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP 0 - #define CFG_FCH_GPP_LINK_CONFIG 0 - #define CFG_FCH_GPP_PORT0_PRESENT 0 - #define CFG_FCH_GPP_PORT1_PRESENT 0 - #define CFG_FCH_GPP_PORT2_PRESENT 0 - #define CFG_FCH_GPP_PORT3_PRESENT 0 - #define CFG_FCH_GPP_PORT0_HOTPLUG 0 - #define CFG_FCH_GPP_PORT1_HOTPLUG 0 - #define CFG_FCH_GPP_PORT2_HOTPLUG 0 - #define CFG_FCH_GPP_PORT3_HOTPLUG 0 - - #define CFG_FCH_ESATA_PORT_BITMAP 0 - #define CFG_FCH_IR_PIN_CONTROL 0 - #define CFG_FCH_SD_CLOCK_CONTROL 0 - #define CFG_FCH_SCI_MAP_LIST 0 - #define CFG_FCH_SATA_PHY_LIST 0 - #define CFG_FCH_GPIO_CONTROL_LIST 0 - -#endif - - -CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = { - FP_FCH_INIT_RESET, - FP_FCH_INIT_RESET_CONSTRUCT, - FP_FCH_INIT_ENV, - FP_FCH_INIT_ENV_CONSTRUCT, - FP_FCH_INIT_MID, - FP_FCH_INIT_MID_CONSTRUCT, - FP_FCH_INIT_LATE, - FP_FCH_INIT_LATE_CONSTRUCT, -}; - -#endif // _OPTION_FCH_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionGfxRecoveryInstall.h deleted file mode 100644 index c046c24e87..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionGfxRecoveryInstall.h +++ /dev/null @@ -1,52 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: GfxRecovery - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_ -#define _OPTION_GFX_RECOVERY_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - - -#endif // _OPTION_GFX_RECOVERY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionGnbInstall.h deleted file mode 100644 index 7733859aed..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionGnbInstall.h +++ /dev/null @@ -1,591 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: GNB - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 53099 $ @e \$Date: 2011-05-16 01:08:27 -0600 (Mon, 16 May 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_GNB_INSTALL_H_ -#define _OPTION_GNB_INSTALL_H_ - -#include "S3SaveState.h" -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -//--------------------------------------------------------------------------------------------------- -// Family installation -//--------------------------------------------------------------------------------------------------- - - -#define GNB_TYPE_LN FALSE -#define GNB_TYPE_ON FALSE - -#if (OPTION_FAMILY14H_ON == TRUE) - #undef GNB_TYPE_ON - #define GNB_TYPE_ON TRUE -#endif - -#if (OPTION_FAMILY12H_LN == TRUE) - #undef GNB_TYPE_LN - #define GNB_TYPE_LN TRUE -#endif - - -#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) -//--------------------------------------------------------------------------------------------------- -// Service installation -//--------------------------------------------------------------------------------------------------- - - #include "Gnb.h" - #include "GnbPcie.h" - - #define SERVICES_POINTER NULL - GNB_SERVICE *ServiceTable = SERVICES_POINTER; - -//--------------------------------------------------------------------------------------------------- -// BUILD options -//--------------------------------------------------------------------------------------------------- - - #ifndef CFG_IGFX_AS_PCIE_EP - #define CFG_IGFX_AS_PCIE_EP TRUE - #endif - - #ifndef CFG_LCLK_DEEP_SLEEP_EN - #define CFG_LCLK_DEEP_SLEEP_EN TRUE - #endif - - #ifndef CFG_LCLK_DPM_EN - #define CFG_LCLK_DPM_EN TRUE - #endif - - #ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY - #define CFG_GMC_POWER_GATE_STUTTER_ONLY FALSE - #endif - - #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE - #if (GNB_TYPE_ON == TRUE) - #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE - #else - #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE - #endif - #endif - - #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE - #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE - #endif - - #ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT - #define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE - #endif - - #ifndef CFG_GNB_LOAD_REAL_FUSE - #define CFG_GNB_LOAD_REAL_FUSE TRUE - #endif - - #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING - #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) - #endif - - #ifndef CFG_GNB_PCIE_LINK_L0_POOLING - #define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000) - #endif - - #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME - #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) - #endif - - #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME - #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) - #endif - - #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM - #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM - #else - #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard - #endif - - #ifndef CFG_GNB_FORCE_CABLESAFE_OFF - #define CFG_GNB_FORCE_CABLESAFE_OFF FALSE - #endif - - #ifndef CFG_ORB_CLOCK_GATING_ENABLE - #define CFG_ORB_CLOCK_GATING_ENABLE TRUE - #endif - - #ifndef CFG_GNB_PCIE_POWERGATING_FLAGS - #define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0 - #endif - - #ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE - #define CFG_IOC_LCLK_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE - #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE - #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE - #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE - #endif - - #ifndef CFG_GNB_ALTVDDNB_SUPPORT - #define CFG_GNB_ALTVDDNB_SUPPORT TRUE - #endif - - #ifndef CFG_GNB_BAPM_SUPPORT - #define CFG_GNB_BAPM_SUPPORT TRUE - #endif - - #ifndef CFG_UNUSED_SIMD_POWERGATING_ENABLE - #define CFG_UNUSED_SIMD_POWERGATING_ENABLE TRUE - #endif - - #ifndef CFG_UNUSED_RB_POWERGATING_ENABLE - #define CFG_UNUSED_RB_POWERGATING_ENABLE FALSE - #endif - - GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = { - CFG_IGFX_AS_PCIE_EP, - CFG_LCLK_DEEP_SLEEP_EN, - CFG_LCLK_DPM_EN, - CFG_GMC_POWER_GATE_STUTTER_ONLY, - CFG_SMU_SCLK_CLOCK_GATING_ENABLE, - CFG_PCIE_ASPM_BLACK_LIST_ENABLE, - CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT, - CFG_GNB_LOAD_REAL_FUSE, - CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING, - CFG_GNB_PCIE_LINK_L0_POOLING, - CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME, - CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME, - CFG_GNB_PCIE_TRAINING_ALGORITHM, - CFG_GNB_FORCE_CABLESAFE_OFF, - CFG_ORB_CLOCK_GATING_ENABLE, - CFG_GNB_PCIE_POWERGATING_FLAGS, - CFG_IOC_LCLK_CLOCK_GATING_ENABLE, - CFG_IOC_SCLK_CLOCK_GATING_ENABLE, - CFG_IOMMU_L1_CLOCK_GATING_ENABLE, - CFG_IOMMU_L2_CLOCK_GATING_ENABLE, - CFG_GNB_ALTVDDNB_SUPPORT, - CFG_GNB_BAPM_SUPPORT, - CFG_UNUSED_SIMD_POWERGATING_ENABLE, - CFG_UNUSED_RB_POWERGATING_ENABLE - }; - - //--------------------------------------------------------------------------------------------------- - // Module entries - //--------------------------------------------------------------------------------------------------- - - #if (AGESA_ENTRY_INIT_EARLY == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_EARLY_INIT - #define OPTION_NB_EARLY_INIT TRUE - #endif - #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtEarly; - #define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly}, - #else - #define OPTION_NBINITATEARLY_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - // SMU init - #ifndef OPTION_SMU - #define OPTION_SMU TRUE - #endif - #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE F12NbSmuInitFeature; - #define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature}, - #else - #define OPTION_F12NBSMUINITFEATURE_ENTRY - #endif - #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE F14NbSmuInitFeature; - #define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature}, - #else - #define OPTION_F14NBSMUINITFEATURE_ENTRY - #endif - #define OPTION_KRNBSMUINITFEATURE_ENTRY - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_CONFIG_MAP - #define OPTION_PCIE_CONFIG_MAP TRUE - #endif - #if (OPTION_PCIE_CONFIG_MAP == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieConfigurationMap; - #define OPTION_PCIECONFIGURATIONMAP_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationMap}, - #else - #define OPTION_PCIECONFIGURATIONMAP_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_EARLY_INIT - #define OPTION_PCIE_EARLY_INIT TRUE - #endif - #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtEarly; - #define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly}, - #else - #define OPTION_PCIEINITATEARLY_ENTRY - #endif - - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { - OPTION_NBINITATEARLY_ENTRY - OPTION_F12NBSMUINITFEATURE_ENTRY - OPTION_F14NBSMUINITFEATURE_ENTRY - OPTION_PCIECONFIGURATIONMAP_ENTRY - OPTION_PCIEINITATEARLY_ENTRY - {0, NULL} - }; - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_CONFIG_INIT - #define OPTION_PCIE_CONFIG_INIT TRUE - #endif - #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieConfigurationInit; - #define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit}, - #else - #define OPTION_PCIECONFIGURATIONINIT_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_EARLIER_INIT - #define OPTION_NB_EARLIER_INIT TRUE - #endif - - OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = { - OPTION_PCIECONFIGURATIONINIT_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_POST == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_CONFIG_POST_INIT - #define OPTION_GFX_CONFIG_POST_INIT TRUE - #endif - #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxConfigPostInterface; - #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface}, - #else - #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_POST_INIT - #define OPTION_GFX_POST_INIT TRUE - #endif - #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxInitAtPost; - #define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost}, - #else - #define OPTION_GFXINITATPOST_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_POST_INIT - #define OPTION_NB_POST_INIT TRUE - #endif - #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtPost; - #define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost}, - #else - #define OPTION_NBINITATPOST_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_POST_EALRY_INIT - #define OPTION_PCIE_POST_EALRY_INIT TRUE - #endif - #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtPostEarly; - #define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly}, - #else - #define OPTION_PCIEINITATPOSTEARLY_ENTRY - #endif - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_POST_INIT - #define OPTION_PCIE_POST_INIT TRUE - #endif - #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtPost; - #define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost}, - #else - #define OPTION_PCIEINITATPOST_ENTRY - #endif - - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { - OPTION_PCIEINITATPOSTEARLY_ENTRY - OPTION_GFXCONFIGPOSTINTERFACE_ENTRY - OPTION_GFXINITATPOST_ENTRY - OPTION_GFXPOSTINTERFACETN_ENTRY - {0, NULL} - }; - - OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { - OPTION_NBINITATPOST_ENTRY - OPTION_PCIEINITATPOST_ENTRY - OPTION_PCIEPOSTINTERFACETN_ENTRY - OPTION_PCIEPOSTINTERFACEKM_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_ENV == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_FUSE_TABLE_INIT - #define OPTION_FUSE_TABLE_INIT TRUE - #endif - #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbFuseTableFeature; - #define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature}, - #else - #define OPTION_NBFUSETABLEFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_ENV_INIT - #define OPTION_NB_ENV_INIT TRUE - #endif - #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtEnv; - #define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv}, - #else - #define OPTION_NBINITATENVT_ENTRY - #endif - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_CONFIG_ENV_INIT - #define OPTION_GFX_CONFIG_ENV_INIT TRUE - #endif - #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxConfigEnvInterface; - #define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface}, - #else - #define OPTION_GFXCONFIGENVINTERFACE_ENTRY - #endif - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_ENV_INIT - #define OPTION_GFX_ENV_INIT TRUE - #endif - #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxInitAtEnvPost; - #define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost}, - #else - #define OPTION_GFXINITATENVPOST_ENTRY - #endif - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_POWER_GATE - #define OPTION_POWER_GATE TRUE - #endif - #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE F12NbPowerGateFeature; - #define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature}, - #else - #define OPTION_F12NBPOWERGATEFEATURE_ENTRY - #endif - #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE F14NbPowerGateFeature; - #define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature}, - #else - #define OPTION_F14NBPOWERGATEFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_ENV_INIT - #define OPTION_PCIE_ENV_INIT TRUE - #endif - #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtEnv; - #define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv}, - #else - #define OPTION_PCIEINITATENV_ENTRY - #endif - - //--------------------------------------------------------------------------------------------------- - - OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = { - OPTION_NBFUSETABLEFEATURE_ENTRY - OPTION_NBINITATENVT_ENTRY - OPTION_PCIEINITATENV_ENTRY - OPTION_GFXCONFIGENVINTERFACE_ENTRY - OPTION_GFXINITATENVPOST_ENTRY - OPTION_F12NBPOWERGATEFEATURE_ENTRY - OPTION_F14NBPOWERGATEFEATURE_ENTRY - OPTION_KRNBPOWERGATEFEATURE_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_MID == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GNB_CABLESAFE - #define OPTION_GNB_CABLESAFE TRUE - #endif - #if (OPTION_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE GnbCableSafeEntry; - #define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry}, - #else - #define OPTION_GNBCABLESAFEENTRY_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_LCLK_NCLK_RATIO - #define OPTION_NB_LCLK_NCLK_RATIO TRUE - #endif - #if (OPTION_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature; - #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature}, - #else - #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_LCLK_DPM_INIT - #define OPTION_NB_LCLK_DPM_INIT TRUE - #endif - #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbLclkDpmFeature; - #define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature}, - #else - #define OPTION_NBLCLKDPMFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIE_POWER_GATE - #define OPTION_PCIE_POWER_GATE TRUE - #endif - #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) - OPTION_GNB_FEATURE PciePowerGateFeature; - #define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature}, - #else - #define OPTION_PCIEPOWERGATEFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_MID_INIT - #define OPTION_GFX_MID_INIT TRUE - #endif - #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxInitAtMidPost; - #define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost}, - #else - #define OPTION_GFXINITATMIDPOST_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT - #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE - #endif - #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry; - #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry}, - #else - #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_PCIe_MID_INIT - #define OPTION_PCIe_MID_INIT TRUE - #endif - #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieInitAtMid; - #define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid}, - #else - #define OPTION_PCIEINITATMID_ENTRY - #endif - - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_NB_MID_INIT - #define OPTION_NB_MID_INIT TRUE - #endif - #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE NbInitAtLatePost; - #define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost}, - #else - #define OPTION_NBINITATLATEPOST_ENTRY - #endif - - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = { - OPTION_GFXINITATMIDPOST_ENTRY - OPTION_GFXINTEGRATEDINFOTABLE_ENTRY - OPTION_GNBCABLESAFEENTRY_ENTRY - OPTION_PCIEINITATMID_ENTRY - OPTION_NBINITATLATEPOST_ENTRY - OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY - OPTION_NBLCLKDPMFEATURE_ENTRY - OPTION_PCIEPOWERGATEFEATURE_ENTRY - {0, NULL} - }; - #endif - - #if (AGESA_ENTRY_INIT_LATE == TRUE) - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_ALIB - #define OPTION_ALIB FALSE - #endif - #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - OPTION_GNB_FEATURE PcieAlibFeature; - #define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature}, - #else - #define OPTION_PCIEALIBFEATURE_ENTRY - #endif - //--------------------------------------------------------------------------------------------------- - #ifndef OPTION_IOMMU_ACPI_IVRS - #define OPTION_IOMMU_ACPI_IVRS TRUE - #endif - //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = { - OPTION_PCIEALIBFEATURE_ENTRY - OPTIONIOMMUACPIIVRSLATE_ENTRY - {0, NULL} - }; - #endif - - #if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) - S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script; - S3_DISPATCH_FUNCTION PcieLateRestoreS3Script; - S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script; - #define GNB_S3_DISPATCH_FUNCTION_TABLE \ - {NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \ - {NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \ - {PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script}, - #endif - - -#endif -#endif // _OPTION_GNB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionHtInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionHtInstall.h deleted file mode 100644 index 056777d079..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionHtInstall.h +++ /dev/null @@ -1,319 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Ht - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 51975 $ @e \$Date: 2011-04-29 01:33:06 -0600 (Fri, 29 Apr 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_HT_INSTALL_H_ -#define _OPTION_HT_INSTALL_H_ - -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "htTopologies.h" -/* - * Advanced Option only, hardware socket naming is the preferred method. - */ -#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP - #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP) -#else - #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL) -#endif - -/* - * OPTION_IS_RECOVERY_HT is true if Basic API is being used. - */ -#ifndef OPTION_IS_RECOVERY_HT - #define OPTION_IS_RECOVERY_HT TRUE -#endif - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition. - */ - -#ifndef OPTION_MULTISOCKET - #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" -#endif - -/* - * Based on user level options, set Ht internal options. - * For now, Family 10h support will assume single module. For multi module, - * this will have to be changed to not set non-coherent only. - */ -#define OPTION_HT_NON_COHERENT_ONLY FALSE - -#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)) -/* Families with only PCIe do not need a non-coherent only option. */ -#else - // Process Family 10h and 15h Models 00h-0Fh by socket, applying the MultiSocket option where it is allowable. - #if OPTION_G34_SOCKET_SUPPORT == FALSE - // Hydra has coherent support, other Family 10h should follow MultiSocket support. - #if OPTION_MULTISOCKET == FALSE - #undef OPTION_HT_NON_COHERENT_ONLY - #define OPTION_HT_NON_COHERENT_ONLY TRUE - #endif - #endif -#endif - -/* - * Macros will generate the correct item reference based on options - */ -#if AGESA_ENTRY_INIT_EARLY == TRUE - // Select the interface and features - #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)) - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL - #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone - #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly - #else - // Family 10h and 15h Models 00h-0Fh - #if OPTION_HT_NON_COHERENT_ONLY == FALSE - #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault - #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault - #else - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL - #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly - #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly - #endif - #endif - // Select Northbridge components - #if OPTION_FAMILY10H == TRUE - #if OPTION_HT_NON_COHERENT_ONLY == TRUE - #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly, &HtFam10RevENbNonCoherentOnly, - #else - #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault, &HtFam10RevENbDefault, - #endif - #else - #define INTERNAL_HT_OPTION_FAM10_NB - #endif - - #if OPTION_FAMILY12H == TRUE - #define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb, - #else - #define INTERNAL_HT_OPTION_FAM12_NB - #endif - - #if OPTION_FAMILY14H == TRUE - #define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb, - #else - #define INTERNAL_HT_OPTION_FAM14_NB - #endif - - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - #if OPTION_HT_NON_COHERENT_ONLY == TRUE - #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly, - #else - #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault, - #endif - #else - #define INTERNAL_HT_OPTION_FAM15_NB - #endif - #define INTERNAL_HT_OPTION_FAM15TN_NB - #define INTERNAL_HT_OPTION_FAM15KM_NB - #else - #define INTERNAL_HT_OPTION_FAM15_NB - #define INTERNAL_HT_OPTION_FAM15TN_NB - #define INTERNAL_HT_OPTION_FAM15KM_NB - #endif - - #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS, - #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS - #undef INTERNAL_ONLY_NB_LIST_ITEM - #define INTERNAL_ONLY_NB_LIST_ITEM - #endif - - /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item - * is ok to have a comma because the final item (NULL) is added below. - */ - #define INTERNAL_HT_OPTION_SUPPORTED_NBS \ - INTERNAL_ONLY_NB_LIST_ITEM \ - INTERNAL_HT_OPTION_FAM10_NB \ - INTERNAL_HT_OPTION_FAM15_NB \ - INTERNAL_HT_OPTION_FAM12_NB \ - INTERNAL_HT_OPTION_FAM14_NB -#else - // Not Init Early - #define INTERNAL_HT_OPTION_FEATURES NULL - #define INTERNAL_HT_OPTION_INTERFACE NULL - #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL - #define HT_OPTIONS_PLATFORM NULL - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL -#endif - -#ifdef AGESA_ENTRY_INIT_EARLY - #if AGESA_ENTRY_INIT_EARLY == TRUE - - extern HT_FEATURES HtFeaturesDefault; - extern HT_FEATURES HtFeaturesNonCoherentOnly; - extern HT_FEATURES HtFeaturesCoherentOnly; - extern HT_FEATURES HtFeaturesNone; - extern HT_INTERFACE HtInterfaceDefault; - extern HT_INTERFACE HtInterfaceNonCoherentOnly; - extern HT_INTERFACE HtInterfaceCoherentOnly; - extern HT_INTERFACE HtInterfaceMapsOnly; - extern HT_INTERFACE HtInterfaceNone; - extern NORTHBRIDGE HtFam10NbDefault; - extern NORTHBRIDGE HtFam10RevDNbDefault; - extern NORTHBRIDGE HtFam10NbNonCoherentOnly; - extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly; - extern NORTHBRIDGE HtFam10RevENbDefault; - extern NORTHBRIDGE HtFam10RevENbNonCoherentOnly; - extern NORTHBRIDGE HtFam12Nb; - extern NORTHBRIDGE HtFam14Nb; - extern NORTHBRIDGE HtFam10NbNone; - extern NORTHBRIDGE HtFam15NbDefault; - extern NORTHBRIDGE HtFam15NbNonCoherentOnly; - - CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = { - INTERNAL_HT_OPTION_SUPPORTED_NBS - NULL - }; - - STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform = - { - CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM, - (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST, - (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST, - (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST, - (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST, - (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST, - (IGNORE_LINK *)CFG_IGNORE_LINK_LIST, - (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST, - (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST, - (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP - }; - #ifndef HT_OPTIONS_PLATFORM - #define HT_OPTIONS_PLATFORM &HtOptionsPlatform - #endif - - /** - * A list of all the supported topologies. - * - */ - #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES - CONST UINT8 *CONST ROMDATA AmdTopolist[] = - { - amdHtTopologySingleNode, - amdHtTopologyDualNode, - amdHtTopologyThreeLine, - amdHtTopologyTriangle, - amdHtTopologyFourLine, - amdHtTopologyFourStar, - amdHtTopologyFourDegenerate, - amdHtTopologyFourSquare, - amdHtTopologyFourKite, - amdHtTopologyFourFully, - amdHtTopologyFiveFully, - amdHtTopologyFiveTwistedLadder, - amdHtTopologySixFully, - amdHtTopologySixDoubloonLower, - amdHtTopologySixDoubloonUpper, - amdHtTopologySixTwistedLadder, - amdHtTopologySevenFully, - amdHtTopologySevenTwistedLadder, - amdHtTopologyEightFully, - amdHtTopologyEightDoubloon, - amdHtTopologyEightTwistedLadder, - amdHtTopologyEightStraightLadder, - amdHtTopologySixTwinTriangles, - amdHtTopologyEightTwinFullyFourWays, - NULL - }; - #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist - #endif - - /** - * Declare the instance of the Ht option configuration structure - */ - CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = { - OPTION_IS_RECOVERY_HT, - CFG_SET_HTCRC_SYNC_FLOOD, - CFG_USE_UNIT_ID_CLUMPING, - HT_OPTIONS_PLATFORM, - INTERNAL_HT_OPTION_INTERFACE, - INTERNAL_HT_OPTION_FEATURES, - &HtInstalledFamilyNorthbridgeList, - INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES - }; - - #endif -#endif - -#ifndef OPTION_HT_INIIT_RESET_ENTRY - - #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset - #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor - - #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)) - #undef OPTION_HT_INIIT_RESET_ENTRY - #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY - #define OPTION_HT_INIIT_RESET_ENTRY NULL - #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL - #endif - - #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE)) - #undef OPTION_HT_INIIT_RESET_ENTRY - #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY - #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset - #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor - #endif - -#endif - -#ifdef AGESA_ENTRY_INIT_RESET - #if AGESA_ENTRY_INIT_RESET == TRUE - - CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = { - (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST, - 0 // Unused by options - }; - - CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = { - OPTION_HT_INIIT_RESET_ENTRY, - OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY - }; - #endif - -#endif - -#endif // _OPTION_HT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionHwC1eInstall.h deleted file mode 100644 index f01fb04e9e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionHwC1eInstall.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: HW C1e - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_HW_C1E_INSTALL_H_ -#define _OPTION_HW_C1E_INSTALL_H_ - -#include "cpuHwC1e.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_HW_C1E_FEAT -#define F10_HW_C1E_SUPPORT -#if AGESA_ENTRY_INIT_EARLY == TRUE - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e; - #undef OPTION_HW_C1E_FEAT - #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e, - extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e; - #undef F10_HW_C1E_SUPPORT - #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e}, - #endif - #endif - #endif - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] = - { - F10_HW_C1E_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable = - { - (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &HwC1eFamilyServiceArray[0] - }; -#endif - -#endif // _OPTION_HW_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionIdsInstall.h deleted file mode 100644 index 6fa09e98dd..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionIdsInstall.h +++ /dev/null @@ -1,581 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * IDS Option Install File - * - * This file generates the defaults tables for family 10h model 5 processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 55277 $ @e \$Date: 2011-06-19 23:03:21 -0600 (Sun, 19 Jun 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ -#ifndef _OPTION_IDS_INSTALL_H_ -#define _OPTION_IDS_INSTALL_H_ -#include "Ids.h" -#include "IdsHt.h" -#include "IdsLib.h" -#ifdef __IDS_EXTENDED__ - #include OPTION_IDS_EXT_INSTALL_FILE -#endif - -#define IDS_LATE_RUN_AP_TASK - -#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid -#if (IDSOPT_IDS_ENABLED == TRUE) - #if (IDSOPT_CONTROL_ENABLED == TRUE) - // Check for all families which include HT Features. - #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_KM == TRUE)) && (AGESA_ENTRY_INIT_POST == TRUE) - #undef M_HTIDS_PORT_OVERRIDE_HOOK - #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride - #endif - #endif -#endif // OPTION_IDS_LEVEL -CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK; - -#if (IDSOPT_IDS_ENABLED == TRUE) - #if (AGESA_ENTRY_INIT_LATE == TRUE) - #undef IDS_LATE_RUN_AP_TASK - #define IDS_LATE_RUN_AP_TASK - #endif -#endif // OPTION_IDS_LEVEL - -#if (IDSOPT_TRACING_ENABLED == TRUE) - #if (AGESA_ENTRY_INIT_POST == TRUE) - #include - CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, - { (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, - { (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} - }; - #else - CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINTN) CommonReturnFalse, "DefRet()"}, - { (UINTN) CommonReturnFalse, "DefRet()"}, - { (UINTN) CommonReturnFalse, "DefRet()"} - }; - #endif -#else - CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINTN) CommonReturnFalse, "DefRet()"}, - { (UINTN) CommonReturnFalse, "DefRet()"}, - { (UINTN) CommonReturnFalse, "DefRet()"} - }; -#endif - - -#define NV_TO_CMOS(Len, NV_ID) {Len, NV_ID}, -#define OPTION_IDS_NV_TO_CMOS_END NV_TO_CMOS (IDS_NV_TO_CMOS_LEN_END, IDS_NV_TO_CMOS_ID_END) -#if (IDSOPT_IDS_ENABLED == TRUE) - #if ((IDSOPT_CONTROL_ENABLED == TRUE) && \ - ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \ - (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \ - (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))) - #if (IDSOPT_CONTROL_NV_TO_CMOS == TRUE) - #define OPTION_IDS_NV_TO_CMOS_COMMON - - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #define OPTION_IDS_NV_TO_CMOS_F10 - #endif - #endif - - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - #define OPTION_IDS_NV_TO_CMOS_F12 - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - #define OPTION_IDS_NV_TO_CMOS_F14 - #endif - #endif - - #ifdef OPTION_FAMILY15H_OR - #if OPTION_FAMILY15H_OR == TRUE - #define OPTION_IDS_NV_TO_CMOS_F15_OR - #endif - #endif - - #ifdef OPTION_FAMILY15H_TN - #if OPTION_FAMILY15H_TN == TRUE - #define OPTION_IDS_NV_TO_CMOS_F15_TN\ - {IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE}, - #endif - #endif - - #ifndef OPTION_IDS_NV_TO_CMOS_F10 - #define OPTION_IDS_NV_TO_CMOS_F10 - #endif - - #ifndef OPTION_IDS_NV_TO_CMOS_F12 - #define OPTION_IDS_NV_TO_CMOS_F12 - #endif - - #ifndef OPTION_IDS_NV_TO_CMOS_F14 - #define OPTION_IDS_NV_TO_CMOS_F14 - #endif - - #ifndef OPTION_IDS_NV_TO_CMOS_F15_OR - #define OPTION_IDS_NV_TO_CMOS_F15_OR - #endif - - #ifndef OPTION_IDS_NV_TO_CMOS_F15_TN - #define OPTION_IDS_NV_TO_CMOS_F15_TN - #endif - - #ifndef OPTION_IDS_NV_TO_CMOS_EXTEND - #define OPTION_IDS_NV_TO_CMOS_EXTEND - #endif - - IDS_NV_TO_CMOS gIdsNVToCmos[] = { - OPTION_IDS_NV_TO_CMOS_COMMON - OPTION_IDS_NV_TO_CMOS_F10 - OPTION_IDS_NV_TO_CMOS_F12 - OPTION_IDS_NV_TO_CMOS_F14 - OPTION_IDS_NV_TO_CMOS_F15_OR - OPTION_IDS_NV_TO_CMOS_F15_TN - OPTION_IDS_NV_TO_CMOS_EXTEND - OPTION_IDS_NV_TO_CMOS_END - }; - #else - IDS_NV_TO_CMOS gIdsNVToCmos[] = { - OPTION_IDS_NV_TO_CMOS_END - }; - #endif - #else - IDS_NV_TO_CMOS gIdsNVToCmos[] = { - OPTION_IDS_NV_TO_CMOS_END - }; - #endif -#else - IDS_NV_TO_CMOS gIdsNVToCmos[] = { - OPTION_IDS_NV_TO_CMOS_END - }; -#endif - -///Ids Feat Options -#if ((IDSOPT_IDS_ENABLED == TRUE) && \ - ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \ - (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \ - (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))) - #if (IDSOPT_CONTROL_ENABLED == TRUE) - #ifndef OPTION_IDS_EXTEND_FEATS - #define OPTION_IDS_EXTEND_FEATS - #endif - - #define OPTION_IDS_FEAT_ECCCTRL\ - OPTION_IDS_FEAT_ECCCTRL_F10 \ - OPTION_IDS_FEAT_ECCCTRL_F12 \ - OPTION_IDS_FEAT_ECCCTRL_F15_OR - - #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\ - OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \ - OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 \ - OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN - - #define OPTION_IDS_FEAT_CPB_CTRL\ - OPTION_IDS_FEAT_CPB_CTRL_F12 - - #define OPTION_IDS_FEAT_HTC_CTRL\ - OPTION_IDS_FEAT_HTC_CTRL_F15_OR \ - OPTION_IDS_FEAT_HTC_CTRL_F15_TN - - #define OPTION_IDS_FEAT_MEMORY_MAPPING\ - OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \ - OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR \ - OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN - - #define OPTION_IDS_FEAT_HT_ASSIST\ - OPTION_IDS_FEAT_HT_ASSIST_F10HY \ - OPTION_IDS_FEAT_HT_ASSIST_F15_OR - - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE\ - OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \ - OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR - -/*---------------------------------------------------------------------------- - * Family 10 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 - #define OPTION_IDS_FEAT_ECCCTRL_F10 - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE -//Ecc symbol size - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10; - #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10, - -//ECC scrub control - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10; - #undef OPTION_IDS_FEAT_ECCCTRL_F10 - #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10, - #endif - #endif - - //Misc Features - #define OPTION_IDS_FEAT_HT_ASSIST_F10HY - #ifdef OPTION_FAMILY10H_HY - #if OPTION_FAMILY10H_HY == TRUE - #undef OPTION_IDS_FEAT_HT_ASSIST_F10HY - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy; - - #define OPTION_IDS_FEAT_HT_ASSIST_F10HY \ - &IdsFeatHtAssistBlockPlatformCfgF10Hy, - #endif - #endif -/*---------------------------------------------------------------------------- - * Family 12 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 - #define OPTION_IDS_FEAT_ECCCTRL_F12 - #define OPTION_IDS_FEAT_CPB_CTRL_F12 - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F12 - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12; - #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12, - - //ECC scrub control - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12; - #undef OPTION_IDS_FEAT_ECCCTRL_F12 - #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12, - - #undef OPTION_IDS_FEAT_CPB_CTRL_F12 - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12; - #define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12, - - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryChIntlvPostBeforeBlockF12; - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF12; - #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F12 - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \ - &IdsFeatMemoryChIntlvPostBeforeBlockF12, \ - &IdsFeatMemoryMappingChIntlvBlockF12, - - #endif - #endif - -/*---------------------------------------------------------------------------- - * Family 14 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14; - #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14, - #endif - #endif - -/*---------------------------------------------------------------------------- - * Family 15 OR feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR - #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR - #define OPTION_IDS_FEAT_ECCCTRL_F15_OR - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR - #ifdef OPTION_FAMILY15H_OR - #if OPTION_FAMILY15H_OR == TRUE - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Or; - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15Or; - #undef OPTION_IDS_FEAT_HTC_CTRL_F15_OR - #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR\ - &IdsFeatHtcControlBlockF15Or,\ - &IdsFeatHtcControlLateBlockF15Or, - - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Or; - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Or; - #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR\ - &IdsFeatMemoryMappingPostBeforeBlockF15Or,\ - &IdsFeatMemoryMappingChIntlvBlockF15Or, - - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15Or; - #undef OPTION_IDS_FEAT_HT_ASSIST_F15_OR - #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR\ - &IdsFeatHtAssistBlockPlatformCfgF15Or, - - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15Or; - #undef OPTION_IDS_FEAT_ECCCTRL_F15_OR - #define OPTION_IDS_FEAT_ECCCTRL_F15_OR &IdsFeatEccCtrlBlockF15Or, - - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15Or; - #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR &IdsFeatEccSymbolSizeBlockF15Or, - - #endif - #endif -/*---------------------------------------------------------------------------- - * Family 15 TN feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN - #ifdef OPTION_FAMILY15H_TN - #if OPTION_FAMILY15H_TN == TRUE - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Tn; - #undef OPTION_IDS_FEAT_HTC_CTRL_F15_TN - #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN\ - &IdsFeatHtcControlBlockF15Tn, - - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Tn; - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Tn; - #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN\ - &IdsFeatMemoryMappingPostBeforeBlockF15Tn,\ - &IdsFeatMemoryMappingChIntlvBlockF15Tn, - - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF15Tn; - #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN &IdsFeatGnbPlatformCfgBlockF15Tn, - #endif - #endif - - #define OPTION_IDS_FEAT_NV_TO_CMOS - #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE - #undef OPTION_IDS_FEAT_NV_TO_CMOS - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosSaveBlock; - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock; - #define OPTION_IDS_FEAT_NV_TO_CMOS\ - &IdsFeatNvToCmosSaveBlock, \ - &IdsFeatNvToCmosRestoreBlock, - - #endif - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock = - { - IDS_FEAT_UCODE_UPDATE, - IDS_ALL_CORES, - IDS_UCODE, - IDS_FAMILY_ALL, - IdsSubUCode - }; - - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock = - { - IDS_FEAT_POWER_POLICY, - IDS_ALL_CORES, - IDS_PLATFORMCFG_OVERRIDE, - IDS_FAMILY_ALL, - IdsSubPowerPolicyOverride - }; - - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock = - { - IDS_FEAT_TARGET_PSTATE, - IDS_BSP_ONLY, - IDS_INIT_LATE_AFTER, - IDS_FAMILY_ALL, - IdsSubTargetPstate - }; - - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock = - { - IDS_FEAT_POSTPSTATE, - IDS_ALL_CORES, - IDS_CPU_Early_Override, - IDS_FAMILY_ALL, - IdsSubPostPState - }; - - //Dram controller Features - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock = - { - IDS_FEAT_DCT_ALLMEMCLK, - IDS_BSP_ONLY, - IDS_ALL_MEMORY_CLOCK, - IDS_FAMILY_ALL, - IdsSubAllMemClkEn - }; - - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock = - { - IDS_FEAT_DCT_GANGMODE, - IDS_BSP_ONLY, - IDS_GANGING_MODE, - IDS_FAMILY_ALL, - IdsSubGangingMode - }; - - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock = - { - IDS_FEAT_DCT_BURSTLENGTH, - IDS_BSP_ONLY, - IDS_BURST_LENGTH32, - AMD_FAMILY_10, - IdsSubBurstLength32 - }; - - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock = - { - IDS_FEAT_DCT_POWERDOWN, - IDS_BSP_ONLY, - IDS_INIT_POST_BEFORE, - IDS_FAMILY_ALL, - IdsSubPowerDownCtrl - }; - - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock = - { - IDS_FEAT_DCT_DLLSHUTDOWN, - IDS_BSP_ONLY, - IDS_DLL_SHUT_DOWN, - IDS_FAMILY_ALL, - IdsSubDllShutDownSR - }; - - - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock = - { - IDS_FEAT_DCT_POWERDOWN, - IDS_BSP_ONLY, - IDS_POWERDOWN_MODE, - IDS_FAMILY_ALL, - IdsSubPowerDownMode - }; - - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock = - { - IDS_FEAT_HDTOUT, - IDS_BSP_ONLY, - IDS_INIT_EARLY_BEFORE, - IDS_FAMILY_ALL, - IdsSubHdtOut - }; - - CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock = - { - IDS_FEAT_HT_SETTING, - IDS_BSP_ONLY, - IDS_HT_CONTROL, - IDS_FAMILY_ALL, - IdsSubHtLinkControl - }; - - CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] = - { - &IdsFeatUcodeBlock, - &IdsFeatPowerPolicyBlock, - - &IdsFeatTargetPstateBlock, - - &IdsFeatPostPstateBlock, - - OPTION_IDS_FEAT_NV_TO_CMOS - - OPTION_IDS_FEAT_ECCSYMBOLSIZE - - OPTION_IDS_FEAT_ECCCTRL - - &IdsFeatDctAllMemClkBlock, - - &IdsFeatDctGangModeBlock, - - &IdsFeatDctBurstLengthBlock, - - &IdsFeatDctPowerDownCtrlBlock, - - &IdsFeatDctPowerDownModeBlock, - - &IdsFeatDctPowerDownModeBlock, - - OPTION_IDS_FEAT_HT_ASSIST - - &IdsFeatHdtOutBlock, - - &IdsFeatHtSettingBlock, - - OPTION_IDS_FEAT_GNB_PLATFORMCFG - - OPTION_IDS_FEAT_CPB_CTRL - - OPTION_IDS_FEAT_HTC_CTRL - - OPTION_IDS_FEAT_MEMORY_MAPPING - - OPTION_IDS_EXTEND_FEATS - - NULL - }; - #else - CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] = - { - NULL - }; - #endif//IDSOPT_CONTROL_ENABLED - - #define OPTION_IDS_FAM_REGACC\ - OPTION_IDS_FAM_REGACC_F15TN - - #define OPTION_IDS_FAM_REGACC_F15TN - #ifdef OPTION_FAMILY15H_TN - #if OPTION_FAMILY15H_TN == TRUE - extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn; - #undef OPTION_IDS_FAM_REGACC_F15TN - #define OPTION_IDS_FAM_REGACC_F15TN \ - &IdsFeatRegGmmxF15Tn, - #endif - #endif - - CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] = - { - OPTION_IDS_FAM_REGACC - NULL - }; - -#else - CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] = - { - NULL - }; - - CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] = - { - NULL - }; -#endif// IDSOPT_IDS_ENABLED - - -#endif diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionIoCstateInstall.h deleted file mode 100644 index f83ad70f5d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionIoCstateInstall.h +++ /dev/null @@ -1,133 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: IO C-state - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_IO_CSTATE_INSTALL_H_ -#define _OPTION_IO_CSTATE_INSTALL_H_ - -#include "cpuIoCstate.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -#define OPTION_IO_CSTATE_FEAT -#define F10_IO_CSTATE_SUPPORT -#define F12_IO_CSTATE_SUPPORT -#define F14_IO_CSTATE_SUPPORT -#define F15_OR_IO_CSTATE_SUPPORT - -#if OPTION_IO_CSTATE == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_PH == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport; - #undef F10_IO_CSTATE_SUPPORT - #define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - #if OPTION_FAMILY12H_LN == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport; - #undef F12_IO_CSTATE_SUPPORT - #define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - #if (OPTION_FAMILY14H_ON == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport; - #undef F14_IO_CSTATE_SUPPORT - #define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14, &F14IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport; - #undef F15_OR_IO_CSTATE_SUPPORT - #define F15_OR_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrIoCstateSupport}, - #endif - #endif - #endif - - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] = -{ - F10_IO_CSTATE_SUPPORT - F12_IO_CSTATE_SUPPORT - F14_IO_CSTATE_SUPPORT - F15_OR_IO_CSTATE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable = -{ - (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &IoCstateFamilyServiceArray[0] -}; - -#endif // _OPTION_IO_CSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionL3FeaturesInstall.h deleted file mode 100644 index 4a73c40dbc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionL3FeaturesInstall.h +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: L3 Dependent Features - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 56186 $ @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_L3_FEATURES_INSTALL_H_ -#define _OPTION_L3_FEATURES_INSTALL_H_ - -#include "cpuL3Features.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_L3_FEAT -#define F10_L3_FEAT_SUPPORT -#define F15_OR_L3_FEAT_SUPPORT -#define F15_KM_L3_FEAT_SUPPORT -#define L3_FEAT_AP_DISABLE_CACHE -#define L3_FEAT_AP_ENABLE_CACHE - -#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE) - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features; - - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_HY == TRUE - #undef OPTION_L3_FEAT - #define OPTION_L3_FEAT &CpuL3Features, - extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features; - #undef F10_L3_FEAT_SUPPORT - #define F10_L3_FEAT_SUPPORT {AMD_FAMILY_10_HY, &F10L3Features}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H_OR - #if OPTION_FAMILY15H_OR == TRUE - #undef OPTION_L3_FEAT - #define OPTION_L3_FEAT &CpuL3Features, - extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features; - #undef F15_OR_L3_FEAT_SUPPORT - #define F15_OR_L3_FEAT_SUPPORT {AMD_FAMILY_15_OR, &F15OrL3Features}, - #endif - #endif - - #ifdef OPTION_FAMILY15H_KM - #if OPTION_FAMILY15H_KM == TRUE - #undef OPTION_L3_FEAT - #define OPTION_L3_FEAT &CpuL3Features, - extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15KmL3Features; - #undef F15_KM_L3_FEAT_SUPPORT - #define F15_KM_L3_FEAT_SUPPORT {AMD_FAMILY_15_KM, &F15KmL3Features}, - #endif - #endif - - #undef L3_FEAT_AP_DISABLE_CACHE - #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, - #undef L3_FEAT_AP_ENABLE_CACHE - #define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches}, - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] = -{ - F10_L3_FEAT_SUPPORT - F15_OR_L3_FEAT_SUPPORT - F15_KM_L3_FEAT_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable = -{ - (sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &L3FeatureFamilyServiceArray[0] -}; - -#endif // _OPTION_L3_FEATURES_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionLowPwrPstateInstall.h deleted file mode 100644 index 61cf174cc2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionLowPwrPstateInstall.h +++ /dev/null @@ -1,87 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Low Power Pstate for PROCHOT_L Throttling. - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_ -#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_ - -#include "cpuLowPwrPstate.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT -#define F15_OR_LOW_PWR_PSTATE_SUPPORT - -#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - // Family 15h - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate; - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate, - extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport; - #undef F15_OR_LOW_PWR_PSTATE_SUPPORT - #define F15_OR_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrLowPwrPstateSupport}, - #endif - #endif - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] = -{ - F15_OR_LOW_PWR_PSTATE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable = -{ - (sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &LowPwrPstateFamilyServiceArray[0] -}; - -#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionMemoryInstall.h deleted file mode 100644 index 254e22e923..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionMemoryInstall.h +++ /dev/null @@ -1,3778 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Memory - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 56315 $ @e \$Date: 2011-07-11 15:59:14 -0600 (Mon, 11 Jul 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_MEMORY_INSTALL_H_ -#define _OPTION_MEMORY_INSTALL_H_ - -/* Memory Includes */ -#include "OptionMemory.h" - -/*------------------------------------------------------------------------------- - * This option file is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -/*---------------------------------------------------------------------------------- - * FEATURE BLOCK FUNCTIONS - * - * This section defines function names that depend upon options that are selected - * in the platform solution install file. - */ -BOOLEAN MemFDefRet ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return FALSE; -} - -BOOLEAN MemMDefRet ( - IN MEM_MAIN_DATA_BLOCK *MMPtr - ) -{ - return TRUE; -} - -BOOLEAN MemMDefRetFalse ( - IN MEM_MAIN_DATA_BLOCK *MMPtr - ) -{ - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for dimm identification translator - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in,out] NodeID - ID of current node to construct - * @return TRUE - This is the correct constructor for the targeted node. - * @return FALSE - This isn't the correct constructor for the targeted node. - */ -BOOLEAN MemNIdentifyDimmConstructorRetDef ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - return FALSE; -} -/*---------------------------------------------------------------------------------- - * TABLE FEATURE BLOCK FUNCTIONS - * - * This section defines function names that depend upon options that are selected - * in the platform solution install file. - */ -UINT8 MemFTableDefRet ( - IN OUT MEM_TABLE_ALIAS **MTPtr - ) -{ - return 0; -} -/*---------------------------------------------------------------------------------- - * FEATURE S3 BLOCK FUNCTIONS - * - * This section defines function names that depend upon options that are selected - * in the platform solution install file. - */ -BOOLEAN MemFS3DefConstructorRet ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - return TRUE; -} - -#if (OPTION_MEMCTLR_DR == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr; - #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr - #else - #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - #if (OPTION_MEMCTLR_Ni == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet - #endif - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA; - #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb; - #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh; - #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh - #else - #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef - #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef - #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_OR == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr; - #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr - #else - #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_HY == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy; - #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy - #else - #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef - #endif -#endif - -#if (OPTION_MEMCTLR_C32 == TRUE) - #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) - #if (OPTION_S3_MEM_SUPPORT == TRUE) - extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32; - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32 - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet - #endif - #else - #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet - #endif - #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) - extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32; - #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32 - #else - #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef - #endif -#endif - -/*---------------------------------------------------------------------------------- - * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS - * - *---------------------------------------------------------------------------------- -*/ -#define MEM_NB_SUPPORT_DR -#define MEM_NB_SUPPORT_RB -#define MEM_NB_SUPPORT_DA -#define MEM_NB_SUPPORT_Ni -#define MEM_NB_SUPPORT_PH -#define MEM_NB_SUPPORT_HY -#define MEM_NB_SUPPORT_OR -#define MEM_NB_SUPPORT_C32 -#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 } - -#if (AGESA_ENTRY_INIT_POST == TRUE) - /*---------------------------------------------------------------------------------- - * FLOW CONTROL FUNCTION - * - * This section selects the function that controls the memory initialization sequence - * based upon the number of processor families that the BIOS will support. - */ - extern MEM_FLOW_CFG MemMFlowDef; - extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; - - - #if (OPTION_MEMCTLR_DR == TRUE) - extern MEM_FLOW_CFG MemMFlowDr; - #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - extern MEM_FLOW_CFG MemMFlowDA; - #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - extern MEM_FLOW_CFG MemMFlowHy; - #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_OR == TRUE) - extern MEM_FLOW_CFG MemMFlowOr; - #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - extern MEM_FLOW_CFG MemMFlowC32; - #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_Ni == TRUE) - extern MEM_FLOW_CFG MemMFlowDA; - #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - extern MEM_FLOW_CFG MemMFlowRb; - #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef, - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - extern MEM_FLOW_CFG MemMFlowPh; - #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh, - #else - #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef, - #endif - - MEM_FLOW_CFG* memFlowControlInstalled[] = { - MEM_MAIN_FLOW_CONTROL_PTR_Dr - MEM_MAIN_FLOW_CONTROL_PTR_DA - MEM_MAIN_FLOW_CONTROL_PTR_RB - MEM_MAIN_FLOW_CONTROL_PTR_PH - MEM_MAIN_FLOW_CONTROL_PTR_Hy - MEM_MAIN_FLOW_CONTROL_PTR_OR - MEM_MAIN_FLOW_CONTROL_PTR_C32 - MEM_MAIN_FLOW_CONTROL_PTR_Ni - NULL - }; - - #if (OPTION_ONLINE_SPARE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare; - #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMOnlineSpare - extern OPTION_MEM_FEATURE_NB MemFOnlineSpare; - #define MEM_FEATURE_ONLINE_SPARE MemFOnlineSpare - #else - #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMDefRet - #define MEM_FEATURE_ONLINE_SPARE MemFDefRet - #endif - - #if (OPTION_MEM_RESTORE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMContextSave; - extern OPTION_MEM_FEATURE_MAIN MemMContextRestore; - #define MEM_MAIN_FEATURE_MEM_SAVE MemMContextSave - #define MEM_MAIN_FEATURE_MEM_RESTORE MemMContextRestore - #else - #define MEM_MAIN_FEATURE_MEM_SAVE MemMDefRet - #define MEM_MAIN_FEATURE_MEM_RESTORE MemMDefRetFalse - #endif - - #if (OPTION_BANK_INTERLEAVE == TRUE) - extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks; - #define MEM_FEATURE_BANK_INTERLEAVE MemFInterleaveBanks - extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks; - #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks - #else - #define MEM_FEATURE_BANK_INTERLEAVE MemFDefRet - #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet - #endif - - #if (OPTION_NODE_INTERLEAVE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes; - #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMInterleaveNodes - extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes; - extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes; - #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFCheckInterleaveNodes - #define MEM_FEATURE_NODE_INTERLEAVE MemFInterleaveNodes - #else - #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFDefRet - #define MEM_FEATURE_NODE_INTERLEAVE MemFDefRet - #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMDefRet - #endif - - #if (OPTION_DCT_INTERLEAVE == TRUE) - extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels; - #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFInterleaveChannels - #else - #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFDefRet - #endif - - #if (OPTION_ECC == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMEcc; - #define MEM_MAIN_FEATURE_ECC MemMEcc - extern OPTION_MEM_FEATURE_NB MemFCheckECC; - extern OPTION_MEM_FEATURE_NB MemFInitECC; - #define MEM_FEATURE_CK_ECC MemFCheckECC - #define MEM_FEATURE_ECC MemFInitECC - #define MEM_FEATURE_ECCX8 MemMDefRet - #else - #define MEM_MAIN_FEATURE_ECC MemMDefRet - #define MEM_FEATURE_CK_ECC MemFDefRet - #define MEM_FEATURE_ECC MemFDefRet - #define MEM_FEATURE_ECCX8 MemMDefRet - #endif - - #define MEM_FEATURE_EMP MemFDefRet - - extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr; - #define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr - - #if (OPTION_DMI == TRUE) - #if (OPTION_DDR3 == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3; - #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3 - #else - extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2; - #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2 - #endif - #else - #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet - #endif - - #if (OPTION_DDR3 == TRUE) - extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal; - extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3; - extern OPTION_MEM_FEATURE_NB MemFLvDdr3; - #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal - #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3 - #define MEM_FEATURE_LVDDR3 MemFLvDdr3 - #else - #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet - #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet - #define MEM_FEATURE_LVDDR3 MemFDefRet - #endif - - extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion; - #define MEM_FEATURE_REGION_INTERLEAVE MemFInterleaveRegion - - extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc; - #define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc - - #if (OPTION_PARALLEL_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining; - #define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining - #else - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - #endif - - #if (OPTION_DIMM_EXCLUDE == TRUE) - extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM; - #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMRASExcludeDIMM - extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM; - #define MEM_FEATURE_DIMM_EXCLUDE MemFRASExcludeDIMM - #else - #define MEM_FEATURE_DIMM_EXCLUDE MemFDefRet - #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMDefRet - #endif - - /*---------------------------------------------------------------------------------- - * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS - * - *---------------------------------------------------------------------------------- - */ - #if OPTION_DDR2 == TRUE - extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2; - #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2, - #if (OPTION_HW_DRAM_INIT == TRUE) - extern MEM_TECH_FEAT MemTDramInitHw; - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw - #else - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef - #endif - #if (OPTION_SW_DRAM_INIT == TRUE) - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef - #else - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef - #endif - #else - #define MEM_TECH_CONSTRUCTOR_DDR2 - #endif - #if OPTION_DDR3 == TRUE - extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3; - #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3, - #if (OPTION_HW_DRAM_INIT == TRUE) - extern MEM_TECH_FEAT MemTDramInitHw; - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw - #else - #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef - #endif - #if (OPTION_SW_DRAM_INIT == TRUE) - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3 - #else - #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef - #endif - #else - #define MEM_TECH_CONSTRUCTOR_DDR3 - #endif - - - /*--------------------------------------------------------------------------------------------------- - * FEATURE BLOCKS - * - * This section instantiates a feature block structure for each memory controller installed - * by the platform solution install file. - *--------------------------------------------------------------------------------------------------- - */ - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; - #endif - extern OPTION_MEM_FEATURE_NB MemFStandardTraining; - - /*--------------------------------------------------------------------------------------------------- - * DEERHOUND FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DR == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockDr = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MemFDefRet, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_DR - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR; - extern MEM_INITIALIZER MemNInitDefaultsDR; - - - #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, - #endif // OPTION_MEMCTRL_DR - - /*--------------------------------------------------------------------------------------------------- - * DASHOUND FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - #define MEM_FEATURE_TRAINING MemFStandardTraining - - #if (OPTION_MEMCTLR_Ni == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockNi = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_Ni - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi; - extern MEM_INITIALIZER MemNInitDefaultsNi; - - #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA }, - #endif - - #if (OPTION_MEMCTLR_PH == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockPh = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_PH - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh; - extern MEM_INITIALIZER MemNInitDefaultsPh; - - #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, - #endif - - #if (OPTION_MEMCTLR_RB == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockRb = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_RB - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb; - extern MEM_INITIALIZER MemNInitDefaultsRb; - - #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, - #endif - - #if (OPTION_MEMCTLR_DA == TRUE) - MEM_FEAT_BLOCK_NB MemFeatBlockDA = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MemFDefRet, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MemFDefRet, - MemFDefRet, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MemFDefRet, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_DA - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA; - extern MEM_INITIALIZER MemNInitDefaultsDA; - - #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, - #endif - #endif // OPTION_MEMCTRL_DA - - /*--------------------------------------------------------------------------------------------------- - * HYDRA FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_HY == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockHy = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MemFDefRet, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_HY - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY; - extern MEM_INITIALIZER MemNInitDefaultsHY; - #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, - #endif // OPTION_MEMCTRL_HY - /*--------------------------------------------------------------------------------------------------- - * OROCHI FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_OR == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_MAIN_FEATURE_LVDDR3 - extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre; - #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #if (OPTION_G34_SOCKET_SUPPORT || OPTION_C32_SOCKET_SUPPORT) - #undef MEM_FEATURE_REGION_INTERLEAVE - #define MEM_FEATURE_REGION_INTERLEAVE MemFDefRet - #endif - - #if (OPTION_EARLY_SAMPLES == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr; - #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportOr - #else - #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet - #endif - - #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) - extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb; - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemNInitCPGUnb - #else - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - #endif - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockOr = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MEM_FEATURE_REGION_INTERLEAVE, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MEM_EARLY_SAMPLE_SUPPORT, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_OR - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR; - extern MEM_INITIALIZER MemNInitDefaultsOR; - #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, - #endif // OPTION_MEMCTRL_OR - - /*--------------------------------------------------------------------------------------------------- - * C32 FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_C32 == TRUE) - #if OPTION_DDR2 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT - #endif - #if OPTION_DDR3 - #undef MEM_TECH_FEATURE_DRAMINIT - #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT - #endif - - #undef MEM_TECH_FEATURE_CPG - #define MEM_TECH_FEATURE_CPG MemFDefRet - - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #undef MEM_TECH_FEATURE_HWRXEN - #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb - #else - extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; - #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb - #endif - - #undef MEM_MAIN_FEATURE_TRAINING - #undef MEM_FEATURE_TRAINING - #if (OPTION_MEMCTLR_OR == TRUE) - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - #else - #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining - #endif - #define MEM_FEATURE_TRAINING MemFStandardTraining - - MEM_FEAT_BLOCK_NB MemFeatBlockC32 = { - MEM_FEAT_BLOCK_NB_STRUCT_VERSION, - MEM_FEATURE_ONLINE_SPARE, - MEM_FEATURE_BANK_INTERLEAVE, - MEM_FEATURE_UNDO_BANK_INTERLEAVE, - MEM_FEATURE_NODE_INTERLEAVE_CHECK, - MEM_FEATURE_NODE_INTERLEAVE, - MEM_FEATURE_CHANNEL_INTERLEAVE, - MemFDefRet, - MEM_FEATURE_CK_ECC, - MEM_FEATURE_ECC, - MEM_FEATURE_TRAINING, - MEM_FEATURE_LVDDR3, - MEM_FEATURE_ONDIMMTHERMAL, - MEM_TECH_FEATURE_DRAMINIT, - MEM_FEATURE_DIMM_EXCLUDE, - MemFDefRet, - MEM_TECH_FEATURE_CPG, - MEM_TECH_FEATURE_HWRXEN - }; - - #undef MEM_NB_SUPPORT_C32 - extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32; - extern MEM_INITIALIZER MemNInitDefaultsC32; - #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, - #endif // OPTION_MEMCTRL_C32 - - /*--------------------------------------------------------------------------------------------------- - * MAIN FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - MEM_FEAT_BLOCK_MAIN MemFeatMain = { - MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION, - MEM_MAIN_FEATURE_TRAINING, - MEM_MAIN_FEATURE_DIMM_EXCLUDE, - MEM_MAIN_FEATURE_ONLINE_SPARE, - MEM_MAIN_FEATURE_NODE_INTERLEAVE, - MEM_MAIN_FEATURE_ECC, - MEM_MAIN_FEATURE_MEM_CLEAR, - MEM_MAIN_FEATURE_MEM_DMI, - MEM_MAIN_FEATURE_LVDDR3, - MEM_MAIN_FEATURE_UMAALLOC, - MEM_MAIN_FEATURE_MEM_SAVE, - MEM_MAIN_FEATURE_MEM_RESTORE - }; - - - /*--------------------------------------------------------------------------------------------------- - * Technology Training SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0 - #if OPTION_MEMCTLR_DR - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - #define TECH_TRAIN_DQS____DDR2 MemTFeatDef - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Dr = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, - TECH_TRAIN_DQS____DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr }, - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define TECH_TRAIN_DQS____DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - #define TECH_TRAIN_DQS____DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Dr = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, - TECH_TRAIN_DQS____DDR3 - }; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB) - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - #define TECH_TRAIN_DQS____DDR2 MemTFeatDef - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2DA = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, - TECH_TRAIN_DQS____DDR2 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2PH = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, - TECH_TRAIN_DQS____DDR2 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Rb = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, - TECH_TRAIN_DQS____DDR2 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Ni = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, - TECH_TRAIN_DQS____DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #if (OPTION_MEMCTLR_DA) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_PH) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_RB) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if (OPTION_MEMCTLR_Ni) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define TECH_TRAIN_DQS____DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - #define TECH_TRAIN_DQS____DDR3 MemTFeatDef - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3DA = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, - TECH_TRAIN_DQS____DDR3 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ph = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, - TECH_TRAIN_DQS____DDR3 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Rb = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, - TECH_TRAIN_DQS____DDR3 - }; - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ni = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, - TECH_TRAIN_DQS____DDR3 - }; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb - #if (OPTION_MEMCTLR_DA) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_PH) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_RB) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if (OPTION_MEMCTLR_Ni) - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni }, - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if OPTION_MEMCTLR_HY - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy; - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - #define TECH_TRAIN_DQS____DDR2 MemTFeatDef - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Hy = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, - TECH_TRAIN_DQS____DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy }, - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define TECH_TRAIN_DQS____DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - #define TECH_TRAIN_DQS____DDR3 MemTFeatDef - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Hy = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, - TECH_TRAIN_DQS____DDR3 - }; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #if OPTION_MEMCTLR_C32 - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32; - #if OPTION_DDR2 - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #endif - #define TECH_TRAIN_DQS____DDR2 MemTFeatDef - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2C32 = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR2, - TECH_TRAIN_SW_WL_DDR2, - TECH_TRAIN_HW_WL_P1_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_HW_WL_P2_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, - TECH_TRAIN_EXIT_HW_TRN_DDR2, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, - TECH_TRAIN_MAX_RD_LAT_DDR2, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, - TECH_TRAIN_DQS____DDR2 - }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; - #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 }, - #else - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define TECH_TRAIN_DQS____DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - #define TECH_TRAIN_DQS____DDR3 MemTFeatDef - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3C32 = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, - TECH_TRAIN_DQS____DDR3 - }; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - - #if OPTION_MEMCTLR_OR - extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr; - #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef - #define TECH_TRAIN_DQS____DDR2 MemTFeatDef - #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #if OPTION_DDR3 - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining - #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 - #else - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #endif - #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #endif - #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 - #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 - #endif - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 - #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) - #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 - #else - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #else - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect - #else - #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef - #endif - #endif - #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 - #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #else - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #endif - #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 - #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw - #else - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #endif - #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency - #else - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #endif - #define TECH_TRAIN_DQS____DDR3 MemTFeatDef - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3OR = { - MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, - TECH_TRAIN_ENTER_HW_TRN_DDR3, - TECH_TRAIN_SW_WL_DDR3, - TECH_TRAIN_HW_WL_P1_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_HW_WL_P2_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, - TECH_TRAIN_EXIT_HW_TRN_DDR3, - TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, - TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, - TECH_TRAIN_MAX_RD_LAT_DDR3, - TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, - TECH_TRAIN_DQS____DDR3 - }; - #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR }, - #else - #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 - #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef - #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 - #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef - #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef - #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef - #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - #else - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, - #endif - - #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 } - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB - MEM_TECH_ENABLE_TRAINING_SEQUENCE_END - }; - - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH - MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB - MEM_TECH_ENABLE_TRAINING_SEQUENCE_END - }; - /*--------------------------------------------------------------------------------------------------- - * NB TRAINING FLOW CONTROL - * - * - *--------------------------------------------------------------------------------------------------- - */ - OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NB_TRAIN_FLOW_DDR2, - NB_TRAIN_FLOW_DDR3, - }; - /*--------------------------------------------------------------------------------------------------- - * TECHNOLOGY BLOCK - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed - MEM_TECH_CONSTRUCTOR_DDR2 - MEM_TECH_CONSTRUCTOR_DDR3 - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if OPTION_MEMCTLR_HY - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUHy3, - #else - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsRHy3, - #else - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsSHy3, - #else - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { - PLAT_SP_HY_FF_UDIMM2 - PLAT_SP_HY_FF_RDIMM2 - PLAT_SP_HY_FF_SDIMM2 - PLAT_SP_HY_FF_UDIMM3 - PLAT_SP_HY_FF_RDIMM3 - PLAT_SP_HY_FF_SDIMM3 - }; - - #if OPTION_MEMCTLR_DR - #if OPTION_UDIMMS - #if OPTION_DDR2 - extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2; - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDr2, - #else - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDr3, - #else - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2; - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsRDr2, - #else - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsRDr3, - #else - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsSDr3, - #else - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = { - PLAT_SP_DR_FF_UDIMM2 - PLAT_SP_DR_FF_RDIMM2 - PLAT_SP_DR_FF_SDIMM2 - PLAT_SP_DR_FF_UDIMM3 - PLAT_SP_DR_FF_RDIMM3 - PLAT_SP_DR_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_DA == TRUE) - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDA3, - #else - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #else - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsSDA2, - #else - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsSDA3, - #else - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { - PLAT_SP_DA_FF_UDIMM2 - PLAT_SP_DA_FF_RDIMM2 - PLAT_SP_DA_FF_SDIMM2 - PLAT_SP_DA_FF_UDIMM3 - PLAT_SP_DA_FF_RDIMM3 - PLAT_SP_DA_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_Ni == TRUE) - #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsSNi3, - #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUNi3, - #else - #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { - PLAT_SP_NI_FF_UDIMM2 - PLAT_SP_NI_FF_RDIMM2 - PLAT_SP_NI_FF_SDIMM2 - PLAT_SP_NI_FF_UDIMM3 - PLAT_SP_NI_FF_RDIMM3 - PLAT_SP_NI_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_PH == TRUE) - #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsSPh3, - #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUPh3, - #else - #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { - PLAT_SP_PH_FF_UDIMM2 - PLAT_SP_PH_FF_RDIMM2 - PLAT_SP_PH_FF_SDIMM2 - PLAT_SP_PH_FF_UDIMM3 - PLAT_SP_PH_FF_RDIMM3 - PLAT_SP_PH_FF_SDIMM3 - }; - - #if (OPTION_MEMCTLR_RB == TRUE) - #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsSRb3, - #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsURb3, - #else - #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { - PLAT_SP_RB_FF_UDIMM2 - PLAT_SP_RB_FF_RDIMM2 - PLAT_SP_RB_FF_SDIMM2 - PLAT_SP_RB_FF_UDIMM3 - PLAT_SP_RB_FF_RDIMM3 - PLAT_SP_RB_FF_SDIMM3 - }; - - #if OPTION_MEMCTLR_C32 - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUC32_3, - #else - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #else - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #endif - #if OPTION_DDR3 - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsRC32_3, - #else - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, - #endif - #if OPTION_SODIMMS - #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, - #endif - #else - #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, - #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, - #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { - PLAT_SP_C32_FF_UDIMM2 - PLAT_SP_C32_FF_RDIMM2 - PLAT_SP_C32_FF_SDIMM2 - PLAT_SP_C32_FF_UDIMM3 - PLAT_SP_C32_FF_RDIMM3 - PLAT_SP_C32_FF_SDIMM3 - }; - - /*--------------------------------------------------------------------------------------------------- - * PLATFORM-SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - - #if OPTION_MEMCTLR_DR - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_DR_UDIMM_DDR2 //MemAGetPsCfgUDr2 - #else - #define PSC_DR_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DR_UDIMM_DDR3 MemAGetPsCfgUDr3, - #else - #define PSC_DR_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_DR_RDIMM_DDR2 MemAGetPsCfgRDr2, - #else - #define PSC_DR_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DR_RDIMM_DDR3 MemAGetPsCfgRDr3, - #else - #define PSC_DR_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_DR_SODIMM_DDR2 //MemAGetPsCfgSDr2 - #else - #define PSC_DR_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DR_SODIMM_DDR3 //MemAGetPsCfgSDr3 - #else - #define PSC_DR_SODIMM_DDR3 - #endif - #endif - #endif - - #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) - #if OPTION_MEMCTLR_Ni - #define PSC_NI_UDIMM_DDR2 - #define PSC_NI_UDIMM_DDR3 MemAGetPsCfgUNi3, - #define PSC_NI_RDIMM_DDR2 - #define PSC_NI_RDIMM_DDR3 - #define PSC_NI_SODIMM_DDR2 - #define PSC_NI_SODIMM_DDR3 MemAGetPsCfgSNi3, - #endif - #if OPTION_MEMCTLR_PH - #define PSC_PH_UDIMM_DDR2 - #define PSC_PH_UDIMM_DDR3 MemAGetPsCfgUPh3, - #define PSC_PH_RDIMM_DDR2 - #define PSC_PH_RDIMM_DDR3 - #define PSC_PH_SODIMM_DDR2 - #define PSC_PH_SODIMM_DDR3 MemAGetPsCfgSPh3, - #endif - #if OPTION_MEMCTLR_RB - #define PSC_RB_UDIMM_DDR2 - #define PSC_RB_UDIMM_DDR3 MemAGetPsCfgURb3, - #define PSC_RB_RDIMM_DDR2 - #define PSC_RB_RDIMM_DDR3 - #define PSC_RB_SODIMM_DDR2 - #define PSC_RB_SODIMM_DDR3 MemAGetPsCfgSRb3, - #endif - #if OPTION_MEMCTLR_DA - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_DA_UDIMM_DDR2 //MemAGetPsCfgUDr2 - #else - #define PSC_DA_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DA_UDIMM_DDR3 MemAGetPsCfgUDA3, - #else - #define PSC_DA_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_DA_RDIMM_DDR2 - #else - #define PSC_DA_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DA_RDIMM_DDR3 - #else - #define PSC_DA_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_DA_SODIMM_DDR2 MemAGetPsCfgSDA2, - #else - #define PSC_DA_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_DA_SODIMM_DDR3 MemAGetPsCfgSDA3, - #else - #define PSC_DA_SODIMM_DDR3 - #endif - #endif - #endif - #endif - - #if OPTION_MEMCTLR_HY - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_HY_UDIMM_DDR2 //MemAGetPsCfgUDr2, - #else - #define PSC_HY_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_HY_UDIMM_DDR3 MemAGetPsCfgUHy3, - #else - #define PSC_HY_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_HY_RDIMM_DDR2 - #else - #define PSC_HY_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_HY_RDIMM_DDR3 MemAGetPsCfgRHy3, - #else - #define PSC_HY_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_HY_SODIMM_DDR2 //MemAGetPsCfgSHy2, - #else - #define PSC_HY_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_HY_SODIMM_DDR3 //MemAGetPsCfgSHy3, - #else - #define PSC_HY_SODIMM_DDR3 - #endif - #endif - #endif - - #if OPTION_MEMCTLR_C32 - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_C32_UDIMM_DDR2 //MemAGetPsCfgUDr2, - #else - #define PSC_C32_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_C32_UDIMM_DDR3 MemAGetPsCfgUC32_3, - #else - #define PSC_C32_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_C32_RDIMM_DDR2 - #else - #define PSC_C32_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_C32_RDIMM_DDR3 MemAGetPsCfgRC32_3, - #else - #define PSC_C32_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_C32_SODIMM_DDR2 //MemAGetPsCfgSC32_2, - #else - #define PSC_C32_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_C32_SODIMM_DDR3 //MemAGetPsCfgSC32_3, - #else - #define PSC_C32_SODIMM_DDR3 - #endif - #endif - #endif - - #if OPTION_MEMCTLR_OR - #if OPTION_UDIMMS - #if OPTION_DDR2 - #define PSC_OR_UDIMM_DDR2 //MemAGetPsCfgUOr2, - #else - #define PSC_OR_UDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_OR_UDIMM_DDR3 //MemAGetPsCfgUOr3, - #else - #define PSC_OR_UDIMM_DDR3 - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_DDR2 - #define PSC_OR_RDIMM_DDR2 - #else - #define PSC_OR_RDIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_OR_RDIMM_DDR3 //MemAGetPsCfgROr3, - #else - #define PSC_OR_RDIMM_DDR3 - #endif - #endif - #if OPTION_SODIMMS - #if OPTION_DDR2 - #define PSC_OR_SODIMM_DDR2 //MemAGetPsCfgSOr2, - #else - #define PSC_OR_SODIMM_DDR2 - #endif - #if OPTION_DDR3 - #define PSC_OR_SODIMM_DDR3 //MemAGetPsCfgSOr3, - #else - #define PSC_OR_SODIMM_DDR3 - #endif - #endif - #endif - - /*---------------------------------------------------------------------- - * DEFAULT PSCFG DEFINITIONS - * - *---------------------------------------------------------------------- - */ - - #ifndef PSC_DR_UDIMM_DDR2 - #define PSC_DR_UDIMM_DDR2 - #endif - #ifndef PSC_DR_RDIMM_DDR2 - #define PSC_DR_RDIMM_DDR2 - #endif - #ifndef PSC_DR_SODIMM_DDR2 - #define PSC_DR_SODIMM_DDR2 - #endif - #ifndef PSC_DR_UDIMM_DDR3 - #define PSC_DR_UDIMM_DDR3 - #endif - #ifndef PSC_DR_RDIMM_DDR3 - #define PSC_DR_RDIMM_DDR3 - #endif - #ifndef PSC_DR_SODIMM_DDR3 - #define PSC_DR_SODIMM_DDR3 - #endif - #ifndef PSC_RB_UDIMM_DDR2 - #define PSC_RB_UDIMM_DDR2 - #endif - #ifndef PSC_RB_RDIMM_DDR2 - #define PSC_RB_RDIMM_DDR2 - #endif - #ifndef PSC_RB_SODIMM_DDR2 - #define PSC_RB_SODIMM_DDR2 - #endif - #ifndef PSC_RB_UDIMM_DDR3 - #define PSC_RB_UDIMM_DDR3 - #endif - #ifndef PSC_RB_RDIMM_DDR3 - #define PSC_RB_RDIMM_DDR3 - #endif - #ifndef PSC_RB_SODIMM_DDR3 - #define PSC_RB_SODIMM_DDR3 - #endif - #ifndef PSC_DA_UDIMM_DDR2 - #define PSC_DA_UDIMM_DDR2 - #endif - #ifndef PSC_DA_RDIMM_DDR2 - #define PSC_DA_RDIMM_DDR2 - #endif - #ifndef PSC_DA_SODIMM_DDR2 - #define PSC_DA_SODIMM_DDR2 - #endif - #ifndef PSC_DA_UDIMM_DDR3 - #define PSC_DA_UDIMM_DDR3 - #endif - #ifndef PSC_DA_RDIMM_DDR3 - #define PSC_DA_RDIMM_DDR3 - #endif - #ifndef PSC_DA_SODIMM_DDR3 - #define PSC_DA_SODIMM_DDR3 - #endif - #ifndef PSC_NI_UDIMM_DDR2 - #define PSC_NI_UDIMM_DDR2 - #endif - #ifndef PSC_NI_RDIMM_DDR2 - #define PSC_NI_RDIMM_DDR2 - #endif - #ifndef PSC_NI_SODIMM_DDR2 - #define PSC_NI_SODIMM_DDR2 - #endif - #ifndef PSC_NI_UDIMM_DDR3 - #define PSC_NI_UDIMM_DDR3 - #endif - #ifndef PSC_NI_RDIMM_DDR3 - #define PSC_NI_RDIMM_DDR3 - #endif - #ifndef PSC_NI_SODIMM_DDR3 - #define PSC_NI_SODIMM_DDR3 - #endif - #ifndef PSC_PH_UDIMM_DDR2 - #define PSC_PH_UDIMM_DDR2 - #endif - #ifndef PSC_PH_RDIMM_DDR2 - #define PSC_PH_RDIMM_DDR2 - #endif - #ifndef PSC_PH_SODIMM_DDR2 - #define PSC_PH_SODIMM_DDR2 - #endif - #ifndef PSC_PH_UDIMM_DDR3 - #define PSC_PH_UDIMM_DDR3 - #endif - #ifndef PSC_PH_RDIMM_DDR3 - #define PSC_PH_RDIMM_DDR3 - #endif - #ifndef PSC_PH_SODIMM_DDR3 - #define PSC_PH_SODIMM_DDR3 - #endif - #ifndef PSC_HY_UDIMM_DDR2 - #define PSC_HY_UDIMM_DDR2 - #endif - #ifndef PSC_HY_RDIMM_DDR2 - #define PSC_HY_RDIMM_DDR2 - #endif - #ifndef PSC_HY_SODIMM_DDR2 - #define PSC_HY_SODIMM_DDR2 - #endif - #ifndef PSC_HY_UDIMM_DDR3 - #define PSC_HY_UDIMM_DDR3 - #endif - #ifndef PSC_HY_RDIMM_DDR3 - #define PSC_HY_RDIMM_DDR3 - #endif - #ifndef PSC_HY_SODIMM_DDR3 - #define PSC_HY_SODIMM_DDR3 - #endif - #ifndef PSC_LN_UDIMM_DDR2 - #define PSC_LN_UDIMM_DDR2 - #endif - #ifndef PSC_LN_RDIMM_DDR2 - #define PSC_LN_RDIMM_DDR2 - #endif - #ifndef PSC_LN_SODIMM_DDR2 - #define PSC_LN_SODIMM_DDR2 - #endif - #ifndef PSC_LN_UDIMM_DDR3 - #define PSC_LN_UDIMM_DDR3 - #endif - #ifndef PSC_LN_RDIMM_DDR3 - #define PSC_LN_RDIMM_DDR3 - #endif - #ifndef PSC_LN_SODIMM_DDR3 - #define PSC_LN_SODIMM_DDR3 - #endif - #ifndef PSC_OR_UDIMM_DDR2 - #define PSC_OR_UDIMM_DDR2 - #endif - #ifndef PSC_OR_RDIMM_DDR2 - #define PSC_OR_RDIMM_DDR2 - #endif - #ifndef PSC_OR_SODIMM_DDR2 - #define PSC_OR_SODIMM_DDR2 - #endif - #ifndef PSC_OR_UDIMM_DDR3 - #define PSC_OR_UDIMM_DDR3 - #endif - #ifndef PSC_OR_RDIMM_DDR3 - #define PSC_OR_RDIMM_DDR3 - #endif - #ifndef PSC_OR_SODIMM_DDR3 - #define PSC_OR_SODIMM_DDR3 - #endif - #ifndef PSC_C32_UDIMM_DDR3 - #define PSC_C32_UDIMM_DDR3 - #endif - #ifndef PSC_C32_RDIMM_DDR3 - #define PSC_C32_RDIMM_DDR3 - #endif - #ifndef PSC_ON_UDIMM_DDR2 - #define PSC_ON_UDIMM_DDR2 - #endif - #ifndef PSC_ON_RDIMM_DDR2 - #define PSC_ON_RDIMM_DDR2 - #endif - #ifndef PSC_ON_SODIMM_DDR2 - #define PSC_ON_SODIMM_DDR2 - #endif - #ifndef PSC_ON_UDIMM_DDR3 - #define PSC_ON_UDIMM_DDR3 - #endif - #ifndef PSC_ON_RDIMM_DDR3 - #define PSC_ON_RDIMM_DDR3 - #endif - #ifndef PSC_ON_SODIMM_DDR3 - #define PSC_ON_SODIMM_DDR3 - #endif - - MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { - PSC_DR_UDIMM_DDR2 - PSC_DR_RDIMM_DDR2 - PSC_DR_SODIMM_DDR2 - PSC_DR_UDIMM_DDR3 - PSC_DR_RDIMM_DDR3 - PSC_DR_SODIMM_DDR3 - PSC_RB_UDIMM_DDR3 - PSC_RB_SODIMM_DDR3 - PSC_DA_SODIMM_DDR2 - PSC_DA_UDIMM_DDR3 - PSC_DA_SODIMM_DDR3 - PSC_NI_UDIMM_DDR3 - PSC_NI_SODIMM_DDR3 - PSC_PH_UDIMM_DDR3 - PSC_PH_SODIMM_DDR3 - PSC_HY_UDIMM_DDR3 - PSC_HY_RDIMM_DDR3 - PSC_HY_SODIMM_DDR3 - PSC_LN_UDIMM_DDR3 - PSC_LN_RDIMM_DDR3 - PSC_LN_SODIMM_DDR3 - PSC_OR_UDIMM_DDR3 - PSC_OR_RDIMM_DDR3 - PSC_OR_SODIMM_DDR3 - PSC_C32_UDIMM_DDR3 - PSC_C32_RDIMM_DDR3 - PSC_ON_UDIMM_DDR3 - PSC_ON_RDIMM_DDR3 - PSC_ON_SODIMM_DDR3 - NULL - }; - CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*)); -// #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES -// #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES -// #endif - - /*--------------------------------------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #define MEM_PSC_FLOW_BLOCK_END NULL - #define PSC_TBL_END NULL - #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue - - #if OPTION_MEMCTLR_OR - #if OPTION_UDIMMS - #if OPTION_AM3_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 &MaxFreqTblEntUAM3, - extern PSC_TBL_ENTRY DramTermTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &DramTermTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &OdtPat1DTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT____AM3 &OdtPat2DTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &OdtPat3DTblEntUAM3, - extern PSC_TBL_ENTRY SAOTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_SAO_AM3 &SAOTblEntUAM3, - extern PSC_TBL_ENTRY ClkDisMapEntUAM3; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3, - extern PSC_TBL_ENTRY S__TblEntUAM3; - #define PSC_TBL_OR_UDIMM3_S___AM3 &S__TblEntUAM3, - extern PSC_TBL_ENTRY WLPass1SeedEntUAM3; - #define PSC_TBL_OR_UDIMM3_WL_SEED_AM3 &WLPass1SeedEntUAM3, - extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUAM3; - #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 &HWRxEnPass1SeedEntUAM3, - #endif - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUC32; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 &MaxFreqTblEntUC32, - extern PSC_TBL_ENTRY DramTermTblEntUC32; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 &DramTermTblEntUC32, - extern PSC_TBL_ENTRY OdtPat1DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntUC32, - extern PSC_TBL_ENTRY OdtPat2DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT____C32 &OdtPat2DTblEntUC32, - extern PSC_TBL_ENTRY OdtPat3DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntUC32, - extern PSC_TBL_ENTRY SAOTblEntUC32; - #define PSC_TBL_OR_UDIMM3_SAO_C32 &SAOTblEntUC32, - extern PSC_TBL_ENTRY ClkDisMapEntUC32; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32, - extern PSC_TBL_ENTRY ClkDisMap3DEntUC32; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32, - extern PSC_TBL_ENTRY S__TblEntUC32; - #define PSC_TBL_OR_UDIMM3_S___C32 &S__TblEntUC32, - extern PSC_TBL_ENTRY WLPass1SeedEntUC32; - #define PSC_TBL_OR_UDIMM3_WL_SEED_C32 &WLPass1SeedEntUC32, - extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUC32; - #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 &HWRxEnPass1SeedEntUC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUG34; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 &MaxFreqTblEntUG34, - extern PSC_TBL_ENTRY DramTermTblEntUG34; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 &DramTermTblEntUG34, - extern PSC_TBL_ENTRY OdtPat1DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntUG34, - extern PSC_TBL_ENTRY OdtPat2DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT____G34 &OdtPat2DTblEntUG34, - extern PSC_TBL_ENTRY OdtPat3DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntUG34, - extern PSC_TBL_ENTRY SAOTblEntUG34; - #define PSC_TBL_OR_UDIMM3_SAO_G34 &SAOTblEntUG34, - extern PSC_TBL_ENTRY ClkDisMapEntUG34; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34, - extern PSC_TBL_ENTRY S__TblEntUG34; - #define PSC_TBL_OR_UDIMM3_S___G34 &S__TblEntUG34, - extern PSC_TBL_ENTRY WLPass1SeedEntUG34; - #define PSC_TBL_OR_UDIMM3_WL_SEED_G34 &WLPass1SeedEntUG34, - extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUG34; - #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntUG34, - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntRC32; - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 &MaxFreqTblEntRC32, - extern PSC_TBL_ENTRY DramTermTblEntRC32; - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 &DramTermTblEntRC32, - extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntRC32, - extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT____C32 &OdtPat2DTblEntRC32, - extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntRC32, - extern PSC_TBL_ENTRY SAOTblEntRC32; - #define PSC_TBL_OR_RDIMM3_SAO_C32 &SAOTblEntRC32, - extern PSC_TBL_ENTRY RC2IBTTblEntRC32; - #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 &RC2IBTTblEntRC32, - extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32; - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 &RC10OpSpdTblEntRC32, - extern PSC_TBL_ENTRY ClkDisMapEntRC32; - #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32, - extern PSC_TBL_ENTRY S__TblEntRC32; - #define PSC_TBL_OR_RDIMM3_S___C32 &S__TblEntRC32, - extern PSC_TBL_ENTRY WLPass1SeedEntRC32; - #define PSC_TBL_OR_RDIMM3_WL_SEED_C32 &WLPass1SeedEntRC32, - extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRC32; - #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 &HWRxEnPass1SeedEntRC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntRG34; - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 &MaxFreqTblEntRG34, - extern PSC_TBL_ENTRY DramTermTblEntRG34; - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 &DramTermTblEntRG34, - extern PSC_TBL_ENTRY OdtPat1DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntRG34, - extern PSC_TBL_ENTRY OdtPat2DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT____G34 &OdtPat2DTblEntRG34, - extern PSC_TBL_ENTRY OdtPat3DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntRG34, - extern PSC_TBL_ENTRY SAOTblEntRG34; - #define PSC_TBL_OR_RDIMM3_SAO_G34 &SAOTblEntRG34, - extern PSC_TBL_ENTRY RC2IBTTblEntRG34; - #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 &RC2IBTTblEntRG34, - extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34; - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 &RC10OpSpdTblEntRG34, - extern PSC_TBL_ENTRY ClkDisMapEntRG34; - #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34, - extern PSC_TBL_ENTRY S__TblEntRG34; - #define PSC_TBL_OR_RDIMM3_S___G34 &S__TblEntRG34, - extern PSC_TBL_ENTRY WLPass1SeedEntRG34; - #define PSC_TBL_OR_RDIMM3_WL_SEED_G34 &WLPass1SeedEntRG34, - extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRG34; - #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntRG34, - #endif - #endif - //#if OPTION_SODIMMS - //#endif - #if OPTION_LRDIMMS - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntLRC32; - #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 &MaxFreqTblEntLRC32, - extern PSC_TBL_ENTRY DramTermTblEntLRC32; - #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 &DramTermTblEntLRC32, - extern PSC_TBL_ENTRY OdtPat1DTblEntLRC32; - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntLRC32, - extern PSC_TBL_ENTRY OdtPat2DTblEntLRC32; - #define PSC_TBL_OR_LRDIMM3_ODT_PAT____C32 &OdtPat2DTblEntLRC32, - extern PSC_TBL_ENTRY OdtPat3DTblEntLRC32; - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntLRC32, - extern PSC_TBL_ENTRY SAOTblEntLRC32; - #define PSC_TBL_OR_LRDIMM3_SAO_C32 &SAOTblEntLRC32, - extern PSC_TBL_ENTRY IBTTblEntLRC32; - #define PSC_TBL_OR_LRDIMM3_IBT_C32 &IBTTblEntLRC32, - extern PSC_TBL_ENTRY ClkDisMapEntLRC32; - #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32, - extern PSC_TBL_ENTRY S__TblEntLRC32; - #define PSC_TBL_OR_LRDIMM3_S___C32 &S__TblEntLRC32, - extern PSC_TBL_ENTRY WLPass1SeedEntLRC32; - #define PSC_TBL_OR_LRDIMM3_WL_SEED_C32 &WLPass1SeedEntLRC32, - extern PSC_TBL_ENTRY HWRxEnPass1SeedEntLRC32; - #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 &HWRxEnPass1SeedEntLRC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntLRG34; - #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 &MaxFreqTblEntLRG34, - extern PSC_TBL_ENTRY DramTermTblEntLRG34; - #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 &DramTermTblEntLRG34, - extern PSC_TBL_ENTRY OdtPat1DTblEntLRG34; - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntLRG34, - extern PSC_TBL_ENTRY OdtPat2DTblEntLRG34; - #define PSC_TBL_OR_LRDIMM3_ODT_PAT____G34 &OdtPat2DTblEntLRG34, - extern PSC_TBL_ENTRY OdtPat3DTblEntLRG34; - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntLRG34, - extern PSC_TBL_ENTRY SAOTblEntLRG34; - #define PSC_TBL_OR_LRDIMM3_SAO_G34 &SAOTblEntLRG34, - extern PSC_TBL_ENTRY IBTTblEntLRG34; - #define PSC_TBL_OR_LRDIMM3_IBT_G34 &IBTTblEntLRG34, - extern PSC_TBL_ENTRY ClkDisMapEntLRG34; - #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34, - extern PSC_TBL_ENTRY S__TblEntLRG34; - #define PSC_TBL_OR_LRDIMM3_S___G34 &S__TblEntLRG34, - extern PSC_TBL_ENTRY WLPass1SeedEntLRG34; - #define PSC_TBL_OR_LRDIMM3_WL_SEED_G34 &WLPass1SeedEntLRG34, - extern PSC_TBL_ENTRY HWRxEnPass1SeedEntLRG34; - #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntLRG34, - #endif - #endif - extern PSC_TBL_ENTRY MR0WrTblEntry; - #define PSC_TBL_OR_MR0_WR &MR0WrTblEntry, - extern PSC_TBL_ENTRY MR0CLTblEntry; - #define PSC_TBL_OR_MR0_CL &MR0CLTblEntry, - extern PSC_TBL_ENTRY OrDdr3CKETriEnt; - #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt, - extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt; - #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt, - extern PSC_TBL_ENTRY OrDdr3ODTTriEnt; - #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt, - extern PSC_TBL_ENTRY OrUDdr3CSTriEnt; - #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt, - extern PSC_TBL_ENTRY OrDdr3CSTriEnt; - #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt, - extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt; - #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt, - extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt; - #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt, - - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT____AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT____AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT____C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT____C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT____G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT____G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3 - #define PSC_TBL_OR_UDIMM3_SAO_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_C32 - #define PSC_TBL_OR_UDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_G34 - #define PSC_TBL_OR_UDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_S___AM3 - #define PSC_TBL_OR_UDIMM3_S___AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_S___C32 - #define PSC_TBL_OR_UDIMM3_S___C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_S___G34 - #define PSC_TBL_OR_UDIMM3_S___G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_AM3 - #define PSC_TBL_OR_UDIMM3_WL_SEED_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_C32 - #define PSC_TBL_OR_UDIMM3_WL_SEED_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_G34 - #define PSC_TBL_OR_UDIMM3_WL_SEED_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 - #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 - #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 - #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT____AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT____AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT____C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT____C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT____G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT____G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3 - #define PSC_TBL_OR_RDIMM3_SAO_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_C32 - #define PSC_TBL_OR_RDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_G34 - #define PSC_TBL_OR_RDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_S___AM3 - #define PSC_TBL_OR_RDIMM3_S___AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_S___C32 - #define PSC_TBL_OR_RDIMM3_S___C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_S___G34 - #define PSC_TBL_OR_RDIMM3_S___G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32 - #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34 - #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_AM3 - #define PSC_TBL_OR_RDIMM3_WL_SEED_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_C32 - #define PSC_TBL_OR_RDIMM3_WL_SEED_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_G34 - #define PSC_TBL_OR_RDIMM3_WL_SEED_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3 - #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 - #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 - #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT____C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT____C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT____G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT____G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32 - #define PSC_TBL_OR_LRDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34 - #define PSC_TBL_OR_LRDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_S___C32 - #define PSC_TBL_OR_LRDIMM3_S___C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_S___G34 - #define PSC_TBL_OR_LRDIMM3_S___G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32 - #define PSC_TBL_OR_LRDIMM3_IBT_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34 - #define PSC_TBL_OR_LRDIMM3_IBT_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_AM3 - #define PSC_TBL_OR_LRDIMM3_WL_SEED_AM3 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_C32 - #define PSC_TBL_OR_LRDIMM3_WL_SEED_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_G34 - #define PSC_TBL_OR_LRDIMM3_WL_SEED_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3 - #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 - #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 - #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 - #endif - - - PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = { - PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = { - PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = { - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT____AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT____AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_UDIMM3_ODT_PAT____C32 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_RDIMM3_ODT_PAT____C32 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT____C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_UDIMM3_ODT_PAT____G34 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_RDIMM3_ODT_PAT____G34 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT____G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = { - PSC_TBL_OR_UDIMM3_SAO_AM3 - PSC_TBL_OR_UDIMM3_SAO_C32 - PSC_TBL_OR_UDIMM3_SAO_G34 - PSC_TBL_OR_RDIMM3_SAO_AM3 - PSC_TBL_OR_RDIMM3_SAO_C32 - PSC_TBL_OR_RDIMM3_SAO_G34 - PSC_TBL_OR_LRDIMM3_SAO_C32 - PSC_TBL_OR_LRDIMM3_SAO_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblS__ArrayOR[] = { - PSC_TBL_OR_UDIMM3_S___AM3 - PSC_TBL_OR_UDIMM3_S___C32 - PSC_TBL_OR_UDIMM3_S___G34 - PSC_TBL_OR_RDIMM3_S___AM3 - PSC_TBL_OR_RDIMM3_S___C32 - PSC_TBL_OR_RDIMM3_S___G34 - PSC_TBL_OR_LRDIMM3_S___C32 - PSC_TBL_OR_LRDIMM3_S___G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = { - PSC_TBL_OR_MR0_WR - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = { - PSC_TBL_OR_MR0_CL - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = { - PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - PSC_TBL_OR_RDIMM3_RC2IBT_C32 - PSC_TBL_OR_RDIMM3_RC2IBT_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = { - PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = { - PSC_TBL_OR_LRDIMM3_IBT_C32 - PSC_TBL_OR_LRDIMM3_IBT_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = { - PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - PSC_TBL_OR_CKE_TRI - PSC_TBL_OR_ODT_TRI_3D - PSC_TBL_OR_ODT_TRI - PSC_TBL_OR_LRDIMM3_ODT_TRI_3D - PSC_TBL_OR_LRDIMM3_ODT_TRI - PSC_TBL_OR_UDIMM3_CS_TRI - PSC_TBL_OR_CS_TRI - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblWLSeedArrayOR[] = { - PSC_TBL_OR_UDIMM3_WL_SEED_AM3 - PSC_TBL_OR_UDIMM3_WL_SEED_C32 - PSC_TBL_OR_UDIMM3_WL_SEED_G34 - PSC_TBL_OR_RDIMM3_WL_SEED_AM3 - PSC_TBL_OR_RDIMM3_WL_SEED_C32 - PSC_TBL_OR_RDIMM3_WL_SEED_G34 - PSC_TBL_OR_LRDIMM3_WL_SEED_AM3 - PSC_TBL_OR_LRDIMM3_WL_SEED_C32 - PSC_TBL_OR_LRDIMM3_WL_SEED_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblHWRxEnSeedArrayOR[] = { - PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 - PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 - PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 - PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3 - PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 - PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 - PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3 - PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 - PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 - PSC_TBL_END - }; - - MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = { - (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR, - NULL, - NULL, - (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblS__ArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblWLSeedArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblHWRxEnSeedArrayOR - }; - - extern MEM_PSC_FLOW MemPGetMaxFreqSupported; - #define PSC_FLOW_OR_MAX_FREQ MemPGetMaxFreqSupported - extern MEM_PSC_FLOW MemPGetRttNomWr; - #define PSC_FLOW_OR_DRAM_TERM MemPGetRttNomWr - extern MEM_PSC_FLOW MemPGetODTPattern; - #define PSC_FLOW_OR_ODT_PATTERN MemPGetODTPattern - extern MEM_PSC_FLOW MemPGetSAO; - #define PSC_FLOW_OR_SAO MemPGetSAO - extern MEM_PSC_FLOW MemPGetMR0WrCL; - #define PSC_FLOW_OR_MR0_WRCL MemPGetMR0WrCL - extern MEM_PSC_FLOW MemPGetS__; - #define PSC_FLOW_OR_S__ MemPGetS__ - extern MEM_PSC_FLOW MemPGetTrainingSeeds; - #define PSC_FLOW_OR_SEED MemPGetTrainingSeeds - #if OPTION_RDIMMS - extern MEM_PSC_FLOW MemPGetRC2IBT; - #define PSC_FLOW_OR_RC2_IBT MemPGetRC2IBT - extern MEM_PSC_FLOW MemPGetRC10OpSpd; - #define PSC_FLOW_OR_RC10_OPSPD MemPGetRC10OpSpd - #endif - #if OPTION_LRDIMMS - extern MEM_PSC_FLOW MemPGetLRIBT; - #define PSC_FLOW_OR_LR_IBT MemPGetLRIBT - extern MEM_PSC_FLOW MemPGetLRNPR; - #define PSC_FLOW_OR_LR_NPR MemPGetLRNPR - extern MEM_PSC_FLOW MemPGetLRNLR; - #define PSC_FLOW_OR_LR_NLR MemPGetLRNLR - #endif - #ifndef PSC_FLOW_OR_MAX_FREQ - #define PSC_FLOW_OR_MAX_FREQ MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_DRAM_TERM - #define PSC_FLOW_OR_DRAM_TERM MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_ODT_PATTERN - #define PSC_FLOW_OR_ODT_PATTERN MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_SAO - #define PSC_FLOW_OR_SAO MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_MR0_WRCL - #define PSC_FLOW_OR_MR0_WRCL MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_RC2_IBT - #define PSC_FLOW_OR_RC2_IBT MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_RC10_OPSPD - #define PSC_FLOW_OR_RC10_OPSPD MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_IBT - #define PSC_FLOW_OR_LR_IBT MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_NPR - #define PSC_FLOW_OR_LR_NPR MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_NLR - #define PSC_FLOW_OR_LR_NLR MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_S__ - #define PSC_FLOW_OR_S__ MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_SEED - #define PSC_FLOW_OR_SEED MEM_PSC_FLOW_DEFTRUE - #endif - - MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = { - &memPSCTblBlockOr, - PSC_FLOW_OR_MAX_FREQ, - PSC_FLOW_OR_DRAM_TERM, - PSC_FLOW_OR_ODT_PATTERN, - PSC_FLOW_OR_SAO, - PSC_FLOW_OR_MR0_WRCL, - PSC_FLOW_OR_RC2_IBT, - PSC_FLOW_OR_RC10_OPSPD, - PSC_FLOW_OR_LR_IBT, - PSC_FLOW_OR_LR_NPR, - PSC_FLOW_OR_LR_NLR, - PSC_FLOW_OR_S__, - PSC_FLOW_OR_SEED - }; - #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR, - #else - #define MEM_PSC_FLOW_BLOCK_OR - #endif - - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { - MEM_PSC_FLOW_BLOCK_OR - MEM_PSC_FLOW_BLOCK_END - }; - - /*--------------------------------------------------------------------------------------------------- - * - * LRDIMM CONTROL - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_LRDIMMS == TRUE) - #if ((OPTION_MEMCTLR_OR == TRUE)) - #define MEM_TECH_FEATURE_LRDIMM_INIT &MemTLrdimmConstructor3 - #else //#if ((OPTION_MEMCTLR_OR == FALSE)) - #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef - #endif - #else //#if (OPTION_LRDIMMS == FALSE) - #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef - #endif - MEM_TECH_LRDIMM memLrdimmSupported = { - MEM_TECH_LRDIMM_STRUCT_VERSION, - MEM_TECH_FEATURE_LRDIMM_INIT - }; -#else - /*--------------------------------------------------------------------------------------------------- - * MAIN FLOW CONTROL - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_FLOW_CFG* memFlowControlInstalled[] = { - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * NB TRAINING FLOW CONTROL - * - * - *--------------------------------------------------------------------------------------------------- - */ - OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * DEFAULT TECHNOLOGY BLOCK - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed - NULL - }; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT TECHNOLOGY MAP - * - * - *--------------------------------------------------------------------------------------------------- - */ - UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT MAIN FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - MEM_FEAT_BLOCK_MAIN MemFeatMain = { - 0 - }; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT NORTHBRIDGE SUPPORT LIST - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DR == TRUE) - #undef MEM_NB_SUPPORT_DR - #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - #undef MEM_NB_SUPPORT_RB - #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - #undef MEM_NB_SUPPORT_DA - #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - #undef MEM_NB_SUPPORT_PH - #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - #undef MEM_NB_SUPPORT_HY - #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - #undef MEM_NB_SUPPORT_C32 - #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, - #endif - #if (OPTION_MEMCTLR_OR == TRUE) - #undef MEM_NB_SUPPORT_OR - #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, - #endif - /*--------------------------------------------------------------------------------------------------- - * DEFAULT Technology Training - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if OPTION_DDR2 - MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { - 0 - }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - { 0 } - }; - #endif - #if OPTION_DDR3 - MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { - 0 - }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - { 0 } - }; - #endif - /*--------------------------------------------------------------------------------------------------- - * DEFAULT Platform Specific list - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DR == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_Ni == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_OR == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { - NULL - }; - #endif - /*---------------------------------------------------------------------- - * DEFAULT PSCFG DEFINITIONS - * - *---------------------------------------------------------------------- - */ - MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { - NULL - }; - - /*---------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - *---------------------------------------------------------------------- - */ - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { - NULL - }; - - MEM_TECH_LRDIMM memLrdimmSupported = { - MEM_TECH_LRDIMM_STRUCT_VERSION, - NULL - }; -#endif - -/*--------------------------------------------------------------------------------------------------- - * NORTHBRIDGE SUPPORT LIST - * - * - *--------------------------------------------------------------------------------------------------- - */ -MEM_NB_SUPPORT memNBInstalled[] = { - MEM_NB_SUPPORT_RB - MEM_NB_SUPPORT_DA - MEM_NB_SUPPORT_Ni - MEM_NB_SUPPORT_PH - MEM_NB_SUPPORT_HY - MEM_NB_SUPPORT_OR - MEM_NB_SUPPORT_C32 - MEM_NB_SUPPORT_END -}; - -#endif // _OPTION_MEMORY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionMsgBasedC1eInstall.h deleted file mode 100644 index a64321ef38..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionMsgBasedC1eInstall.h +++ /dev/null @@ -1,116 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Message-Based C1e - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 56186 $ @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_ -#define _OPTION_MSG_BASED_C1E_INSTALL_H_ - -#include "cpuMsgBasedC1e.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_MSG_BASED_C1E_FEAT -#define F10_MSG_BASED_C1E_SUPPORT -#define F15_OR_MSG_BASED_C1E_SUPPORT -#if OPTION_MSG_BASED_C1E == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e; - - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_HY == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) - #undef OPTION_MSG_BASED_C1E_FEAT - #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, - #endif - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H_OR - #if OPTION_FAMILY15H_OR == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) - #undef OPTION_MSG_BASED_C1E_FEAT - #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_HY == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) - extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e; - #undef F10_MSG_BASED_C1E_SUPPORT - #define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e}, - #endif - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H_OR - #if OPTION_FAMILY15H_OR == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) - extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e; - #undef F15_OR_MSG_BASED_C1E_SUPPORT - #define F15_OR_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15_OR, &F15OrMsgBasedC1e}, - #endif - #endif - #endif - - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] = - { - F10_MSG_BASED_C1E_SUPPORT - F15_OR_MSG_BASED_C1E_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable = - { - (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &MsgBasedC1eFamilyServiceArray[0] - }; - #endif -#endif -#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionMultiSocketInstall.h deleted file mode 100644 index 26a56a3468..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionMultiSocketInstall.h +++ /dev/null @@ -1,103 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Multiple Socket Support - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_MULTISOCKET_INSTALL_H_ -#define _OPTION_MULTISOCKET_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#ifndef OPTION_MULTISOCKET - #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" -#endif - -#if OPTION_MULTISOCKET == TRUE - OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti; - #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti - OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti; - #define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti - OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti; - #define GET_SYS_NB_COF GetSystemNbCofMulti - OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti; - #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti - OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti; - #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti - OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti; - #define GET_MIN_NB_COF GetMinNbCofMulti - OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrMulti; - #define GET_PCI_ADDRESS GetCurrPciAddrMulti - OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti; - #define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti -#else - OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle; - #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle - OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle; - #define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle - OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle; - #define GET_SYS_NB_COF GetSystemNbCofSingle - OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle; - #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle - OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle; - #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle - OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle; - #define GET_MIN_NB_COF GetMinNbCofSingle - OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrSingle; - #define GET_PCI_ADDRESS GetCurrPciAddrSingle - OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle; - #define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle -#endif - -/* Declare the instance of the multisocket option configuration structure */ -OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = { - MULTISOCKET_STRUCT_VERSION, - GET_NUM_PM_STEPS, - CORE0_PM_TASK, - GET_SYS_NB_COF, - GET_SYS_NB_COF_UPDATE, - GET_EARLY_PM_ERRORS, - GET_MIN_NB_COF, - GET_PCI_ADDRESS, - MODIFY_CURR_SOCKET_PCI -}; - -#endif // _OPTION_MULTISOCKET_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionPreserveMailboxInstall.h deleted file mode 100644 index 2b40f77b17..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionPreserveMailboxInstall.h +++ /dev/null @@ -1,123 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Preserve Mailbox - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 56186 $ @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_ -#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_ - -#include "PreserveMailbox.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_PRESERVE_MAILBOX_FEAT -#define F10_PRESERVE_MAILBOX_SUPPORT -#define F15_PRESERVE_MAILBOX_SUPPORT - -#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) - #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE)) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox; - #undef OPTION_PRESERVE_MAILBOX_FEAT - #define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox, - #endif - #if OPTION_FAMILY10H == TRUE - CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F10PreserveMailboxRegisters [] = { - { - {MAKE_SBDFO (0, 0, 0, 3, 0x168)}, - 0x00000FFF - }, - { - {MAKE_SBDFO (0, 0, 0, 3, 0x170)}, - 0x00000FFF - }, - { - {ILLEGAL_SBDFO}, - 0 - } - }; - CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = { - 0, - TRUE, - (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F10PreserveMailboxRegisters - }; - #undef F10_PRESERVE_MAILBOX_SUPPORT - #define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices}, - #endif - #if OPTION_FAMILY15H == TRUE - CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F15PreserveMailboxRegisters [] = { - { - {MAKE_SBDFO (0, 0, 0, 3, 0x168)}, - 0x00000FFF - }, - { - {MAKE_SBDFO (0, 0, 0, 3, 0x170)}, - 0x00000FFF - }, - { - {ILLEGAL_SBDFO}, - 0 - } - }; - CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = { - 0, - TRUE, - (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F15PreserveMailboxRegisters - }; - #undef F15_PRESERVE_MAILBOX_SUPPORT - #define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices}, - #endif - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] = - { - F10_PRESERVE_MAILBOX_SUPPORT - F15_PRESERVE_MAILBOX_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable = - { - (sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &PreserveMailboxFamilyServiceArray[0] - }; -#endif - -#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionPstateHpcModeInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionPstateHpcModeInstall.h deleted file mode 100644 index 061b6f598b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionPstateHpcModeInstall.h +++ /dev/null @@ -1,88 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Pstate HPC mode. - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 52150 $ @e \$Date: 2011-05-03 01:01:08 -0600 (Tue, 03 May 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_PSTATE_HPC_MODE_INSTALL_H_ -#define _OPTION_PSTATE_HPC_MODE_INSTALL_H_ - -#include "cpuPstateHpcMode.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_PSTATE_HPC_MODE_FEAT -#define F15_PSTATE_HPC_MODE_SUPPORT - -#if OPTION_CPU_PSTATE_HPC_MODE == TRUE - #if (AGESA_ENTRY_INIT_POST == TRUE) - // Family 15h - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - // Orochi and Komodo - #if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_KM == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePstateHpcMode; - #undef OPTION_CPU_PSTATE_HPC_MODE_FEAT - #define OPTION_CPU_PSTATE_HPC_MODE_FEAT &CpuFeaturePstateHpcMode, - extern CONST PSTATE_HPC_MODE_FAMILY_SERVICES ROMDATA F15PstateHpcSupport; - #undef F15_PSTATE_HPC_MODE_SUPPORT - #define F15_PSTATE_HPC_MODE_SUPPORT {(AMD_FAMILY_15_OR | AMD_FAMILY_15_KM), &F15PstateHpcSupport}, - #endif - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateHpcModeFamilyServiceArray[] = -{ - F15_PSTATE_HPC_MODE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateHpcModeFamilyServiceTable = -{ - (sizeof (PstateHpcModeFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &PstateHpcModeFamilyServiceArray[0] -}; - -#endif // _OPTION_PSTATE_HPC_MODE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionPstateInstall.h deleted file mode 100644 index 8ca835c385..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionPstateInstall.h +++ /dev/null @@ -1,264 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: PState - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 52904 $ @e \$Date: 2011-05-12 16:42:35 -0600 (Thu, 12 May 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _OPTION_PSTATE_INSTALL_H_ -#define _OPTION_PSTATE_INSTALL_H_ - -#include "cpuPstateTables.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -#define F10_PSTATE_SERVICE_SUPPORT -#define F12_PSTATE_SERVICE_SUPPORT -#define F14_PSTATE_SERVICE_SUPPORT -#define F15_OR_PSTATE_SERVICE_SUPPORT -#define F15_TN_PSTATE_SERVICE_SUPPORT -#define F15_KM_PSTATE_SERVICE_SUPPORT - - -#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) - // - //Define Pstate CPU Family service - // - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices; - #undef F10_PSTATE_SERVICE_SUPPORT - #define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices; - #undef F12_PSTATE_SERVICE_SUPPORT - #define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices; - #undef F14_PSTATE_SERVICE_SUPPORT - #define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #ifdef OPTION_FAMILY15H_OR - #if OPTION_FAMILY15H_OR == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices; - #undef F15_OR_PSTATE_SERVICE_SUPPORT - #define F15_OR_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_OR, &F15OrPstateServices}, - #endif - #endif - #ifdef OPTION_FAMILY15H_TN - #if OPTION_FAMILY15H_TN == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices; - #undef F15_TN_PSTATE_SERVICE_SUPPORT - #define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices}, - #endif - #endif - #ifdef OPTION_FAMILY15H_KM - #if OPTION_FAMILY15H_KM == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15KmPstateServices; - #undef F15_KM_PSTATE_SERVICE_SUPPORT - #define F15_KM_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_KM, &F15KmPstateServices}, - #endif - #endif - #endif - #endif - // - //Define ACPI Pstate objects. - // - #ifndef OPTION_ACPI_PSTATES - #error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES" - #endif - #if (OPTION_ACPI_PSTATES == TRUE) - OPTION_SSDT_FEATURE GenerateSsdt; - #define USER_SSDT_MAIN GenerateSsdt - #ifndef OPTION_MULTISOCKET - #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" - #endif - - OPTION_ACPI_FEATURE CreatePStateAcpiTables; - OPTION_PSTATE_GATHER PStateGatherMain; - #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)) - OPTION_PSTATE_LEVELING PStateLevelingMain; - #define USER_PSTATE_OPTION_LEVEL PStateLevelingMain - #else - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #endif - #if AGESA_ENTRY_INIT_LATE == TRUE - #define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables - #else - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #endif - #if AGESA_ENTRY_INIT_POST == TRUE - #define USER_PSTATE_OPTION_GATHER PStateGatherMain - #else - OPTION_PSTATE_GATHER PStateGatherStub; - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #endif - #if CFG_ACPI_PSTATES_PPC == TRUE - #define USER_PSTATE_CFG_PPC TRUE - #else - #define USER_PSTATE_CFG_PPC FALSE - #endif - #if CFG_ACPI_PSTATES_PCT == TRUE - #define USER_PSTATE_CFG_PCT TRUE - #else - #define USER_PSTATE_CFG_PCT FALSE - #endif - #if CFG_ACPI_PSTATES_PSD == TRUE - #define USER_PSTATE_CFG_PSD TRUE - #else - #define USER_PSTATE_CFG_PSD FALSE - #endif - #if CFG_ACPI_PSTATES_PSS == TRUE - #define USER_PSTATE_CFG_PSS TRUE - #else - #define USER_PSTATE_CFG_PSS FALSE - #endif - #if CFG_ACPI_PSTATES_XPSS == TRUE - #define USER_PSTATE_CFG_XPSS TRUE - #else - #define USER_PSTATE_CFG_XPSS FALSE - #endif - - #if OPTION_IO_CSTATE == TRUE - OPTION_ACPI_FEATURE CreateCStateAcpiTables; - #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables - #else - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #endif - #else - OPTION_SSDT_FEATURE GenerateSsdtStub; - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - OPTION_PSTATE_GATHER PStateGatherStub; - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_SSDT_MAIN GenerateSsdtStub - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #define USER_PSTATE_CFG_PPC FALSE - #define USER_PSTATE_CFG_PCT FALSE - #define USER_PSTATE_CFG_PSD FALSE - #define USER_PSTATE_CFG_PSS FALSE - #define USER_PSTATE_CFG_XPSS FALSE - - // If ACPI Objects are disabled for PStates, we still need to check - // whether ACPI Objects are enabled for CStates - #if OPTION_IO_CSTATE == TRUE - OPTION_SSDT_FEATURE GenerateSsdt; - OPTION_PSTATE_GATHER PStateGatherMain; - OPTION_ACPI_FEATURE CreateCStateAcpiTables; - #undef USER_SSDT_MAIN - #define USER_SSDT_MAIN GenerateSsdt - #undef USER_PSTATE_OPTION_GATHER - #define USER_PSTATE_OPTION_GATHER PStateGatherMain - #undef USER_CSTATE_OPTION_MAIN - #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables - #endif - #endif -#else - OPTION_SSDT_FEATURE GenerateSsdtStub; - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - OPTION_PSTATE_GATHER PStateGatherStub; - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_SSDT_MAIN GenerateSsdtStub - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #define USER_PSTATE_CFG_PPC FALSE - #define USER_PSTATE_CFG_PCT FALSE - #define USER_PSTATE_CFG_PSD FALSE - #define USER_PSTATE_CFG_PSS FALSE - #define USER_PSTATE_CFG_XPSS FALSE -#endif - -/* Declare the instance of the PSTATE option configuration structure */ -OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { - PSTATE_STRUCT_VERSION, - USER_PSTATE_OPTION_GATHER, - USER_PSTATE_OPTION_LEVEL -}; - -OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = { - PSTATE_STRUCT_VERSION, - USER_SSDT_MAIN, - USER_PSTATE_OPTION_MAIN, - USER_CSTATE_OPTION_MAIN, - USER_PSTATE_CFG_PPC, - USER_PSTATE_CFG_PCT, - USER_PSTATE_CFG_PSD, - USER_PSTATE_CFG_PSS, - USER_PSTATE_CFG_XPSS -}; - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] = -{ - F10_PSTATE_SERVICE_SUPPORT - F12_PSTATE_SERVICE_SUPPORT - F14_PSTATE_SERVICE_SUPPORT - F15_OR_PSTATE_SERVICE_SUPPORT - F15_TN_PSTATE_SERVICE_SUPPORT - F15_KM_PSTATE_SERVICE_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable = -{ - (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &PstateCpuFamilyServiceArray[0] -}; -#endif // _OPTION_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionS3ScriptInstall.h deleted file mode 100644 index e5d93eb1b8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionS3ScriptInstall.h +++ /dev/null @@ -1,90 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: S3SCRIPT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_S3SCRIPT_INSTALL_H_ -#define _OPTION_S3SCRIPT_INSTALL_H_ - -#include "S3SaveState.h" -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#ifndef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT FALSE //if not define assume PI not use script -#endif - -#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) - #if OPTION_S3SCRIPT == TRUE - #define P_S3_SCRIPT_INIT S3ScriptInitState - #endif -#endif - -#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - #if OPTION_S3SCRIPT == TRUE - #define P_S3_SCRIPT_RESTORE S3ScriptRestoreState - #endif -#endif - -#ifndef P_S3_SCRIPT_INIT - #define P_S3_SCRIPT_INIT S3ScriptInitStateStub -#endif - -#ifndef P_S3_SCRIPT_RESTORE - #define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub - #undef GNB_S3_DISPATCH_FUNCTION_TABLE -#endif - -#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE - #define GNB_S3_DISPATCH_FUNCTION_TABLE -#endif - -/* Declare the instance of the S3SCRIPT option configuration structure */ -S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = { - P_S3_SCRIPT_INIT, - P_S3_SCRIPT_RESTORE -}; - -S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = { - GNB_S3_DISPATCH_FUNCTION_TABLE - {0, NULL} -}; -#endif // _OPTION_S3SCRIPT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionSlitInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionSlitInstall.h deleted file mode 100644 index a96b217ce3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionSlitInstall.h +++ /dev/null @@ -1,78 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SLIT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_SLIT_INSTALL_H_ -#define _OPTION_SLIT_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_SLIT - #error BLDOPT: Option not defined: "OPTION_SLIT" - #endif - #if OPTION_SLIT == TRUE - OPTION_SLIT_FEATURE GetAcpiSlitMain; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer; - #define USER_SLIT_OPTION GetAcpiSlitMain - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer - #else - OPTION_SLIT_FEATURE GetAcpiSlitStub; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; - #define USER_SLIT_OPTION GetAcpiSlitStub - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub - #endif -#else - OPTION_SLIT_FEATURE GetAcpiSlitStub; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; - #define USER_SLIT_OPTION GetAcpiSlitStub - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub -#endif -/* Declare the instance of the SLIT option configuration structure */ -OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = { - SLIT_STRUCT_VERSION, - USER_SLIT_OPTION, - USER_SLIT_RELEASE_BUFFER -}; - -#endif // _OPTION_SLIT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionSratInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionSratInstall.h deleted file mode 100644 index 3003cabaa7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionSratInstall.h +++ /dev/null @@ -1,72 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SRAT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_SRAT_INSTALL_H_ -#define _OPTION_SRAT_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_SRAT - #error BLDOPT: Option not defined: "OPTION_SRAT" - #endif - #if OPTION_SRAT == TRUE - OPTION_SRAT_FEATURE GetAcpiSratMain; - #define USER_SRAT_OPTION GetAcpiSratMain - #else - OPTION_SRAT_FEATURE GetAcpiSratStub; - #define USER_SRAT_OPTION GetAcpiSratStub - #endif -#else - OPTION_SRAT_FEATURE GetAcpiSratStub; - #define USER_SRAT_OPTION GetAcpiSratStub -#endif - -/* Declare the instance of the WHEA option configuration structure */ -OPTION_SRAT_CONFIGURATION OptionSratConfiguration = { - SRAT_STRUCT_VERSION, - USER_SRAT_OPTION -}; - -#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionSwC1eInstall.h deleted file mode 100644 index b5ebae7040..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionSwC1eInstall.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SW C1e - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_SW_C1E_INSTALL_H_ -#define _OPTION_SW_C1E_INSTALL_H_ - -#include "cpuSwC1e.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_SW_C1E_FEAT -#define F10_SW_C1E_SUPPORT -#if AGESA_ENTRY_INIT_EARLY == TRUE - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e; - #undef OPTION_SW_C1E_FEAT - #define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e, - extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e; - #undef F10_SW_C1E_SUPPORT - #define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e}, - #endif - #endif - #endif - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] = - { - F10_SW_C1E_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable = - { - (sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &SwC1eFamilyServiceArray[0] - }; -#endif - -#endif // _OPTION_SW_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/OptionWheaInstall.h b/src/vendorcode/amd/agesa/f15/Config/OptionWheaInstall.h deleted file mode 100644 index 1295782a34..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/OptionWheaInstall.h +++ /dev/null @@ -1,73 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: WHEA - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _OPTION_WHEA_INSTALL_H_ -#define _OPTION_WHEA_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_WHEA - #error BLDOPT: Option not defined: "OPTION_WHEA" - #endif - #if OPTION_WHEA == TRUE - OPTION_WHEA_FEATURE GetAcpiWheaMain; - #define USER_WHEA_OPTION GetAcpiWheaMain - #else - OPTION_WHEA_FEATURE GetAcpiWheaStub; - #define USER_WHEA_OPTION GetAcpiWheaStub - #endif - -#else - OPTION_WHEA_FEATURE GetAcpiWheaStub; - #define USER_WHEA_OPTION GetAcpiWheaStub -#endif - -/* Declare the instance of the WHEA option configuration structure */ -OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = { - WHEA_STRUCT_VERSION, - USER_WHEA_OPTION -}; - -#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15/Config/PlatformInstall.h deleted file mode 100644 index 31645c3a15..0000000000 --- a/src/vendorcode/amd/agesa/f15/Config/PlatformInstall.h +++ /dev/null @@ -1,2615 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a combination of package type, processor, and features. - * - * This file generates the defaults tables for the all platform solution - * combinations. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 60740 $ @e \$Date: 2011-10-20 19:47:10 -0600 (Thu, 20 Oct 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -/***************************************************************************** - * - * Start processing the user options: First, set default settings - * - ****************************************************************************/ - -VOLATILE AMD_MODULE_HEADER mCpuModuleID = { - //ModuleHeaderSignature - // Remove 'DOM$' as temp solution before update BinUtil.exe , - Int32FromChar ('0', '0', '0', '0'), - //ModuleIdentifier[8] - AGESA_ID, - //ModuleVersion[12] - AGESA_VERSION_STRING, - //ModuleDispatcher - NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher), - //NextBlock - NULL -}; - - -/* Process solution defined socket / family installations - * - * As part of the release package for each image, define the options below to select the - * AGESA processor support included in that image. - */ - -/* Default sockets to off */ -#define OPTION_G34_SOCKET_SUPPORT FALSE -#define OPTION_C32_SOCKET_SUPPORT FALSE -#define OPTION_G2012_SOCKET_SUPPORT FALSE -#define OPTION_C2012_SOCKET_SUPPORT FALSE -#define OPTION_S1G3_SOCKET_SUPPORT FALSE -#define OPTION_S1G4_SOCKET_SUPPORT FALSE -#define OPTION_ASB2_SOCKET_SUPPORT FALSE -#define OPTION_FS1_SOCKET_SUPPORT FALSE -#define OPTION_FM1_SOCKET_SUPPORT FALSE -#define OPTION_FM2_SOCKET_SUPPORT FALSE -#define OPTION_FP1_SOCKET_SUPPORT FALSE -#define OPTION_FP2_SOCKET_SUPPORT FALSE -#define OPTION_FT1_SOCKET_SUPPORT FALSE -#define OPTION_FT2_SOCKET_SUPPORT FALSE -#define OPTION_AM3_SOCKET_SUPPORT FALSE - -/* Default families to off */ -#define OPTION_FAMILY10H FALSE -#define OPTION_FAMILY12H FALSE -#define OPTION_FAMILY14H FALSE -#define OPTION_FAMILY15H FALSE -#define OPTION_FAMILY15H_MODEL_0x FALSE -#define OPTION_FAMILY15H_MODEL_1x FALSE -#define OPTION_FAMILY15H_MODEL_2x FALSE - - -/* Enable the appropriate socket support */ -#ifdef INSTALL_G34_SOCKET_SUPPORT - #if INSTALL_G34_SOCKET_SUPPORT == TRUE - #undef OPTION_G34_SOCKET_SUPPORT - #define OPTION_G34_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_C32_SOCKET_SUPPORT - #if INSTALL_C32_SOCKET_SUPPORT == TRUE - #undef OPTION_C32_SOCKET_SUPPORT - #define OPTION_C32_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_G2012_SOCKET_SUPPORT - #if INSTALL_G2012_SOCKET_SUPPORT == TRUE - #undef OPTION_G2012_SOCKET_SUPPORT - #define OPTION_G2012_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_C2012_SOCKET_SUPPORT - #if INSTALL_C2012_SOCKET_SUPPORT == TRUE - #undef OPTION_C2012_SOCKET_SUPPORT - #define OPTION_C2012_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_S1G3_SOCKET_SUPPORT - #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE - #undef OPTION_S1G3_SOCKET_SUPPORT - #define OPTION_S1G3_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_S1G4_SOCKET_SUPPORT - #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE - #undef OPTION_S1G4_SOCKET_SUPPORT - #define OPTION_S1G4_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_ASB2_SOCKET_SUPPORT - #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE - #undef OPTION_ASB2_SOCKET_SUPPORT - #define OPTION_ASB2_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FS1_SOCKET_SUPPORT - #if INSTALL_FS1_SOCKET_SUPPORT == TRUE - #undef OPTION_FS1_SOCKET_SUPPORT - #define OPTION_FS1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FM1_SOCKET_SUPPORT - #if INSTALL_FM1_SOCKET_SUPPORT == TRUE - #undef OPTION_FM1_SOCKET_SUPPORT - #define OPTION_FM1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FM2_SOCKET_SUPPORT - #if INSTALL_FM2_SOCKET_SUPPORT == TRUE - #undef OPTION_FM2_SOCKET_SUPPORT - #define OPTION_FM2_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FP1_SOCKET_SUPPORT - #if INSTALL_FP1_SOCKET_SUPPORT == TRUE - #undef OPTION_FP1_SOCKET_SUPPORT - #define OPTION_FP1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FP2_SOCKET_SUPPORT - #if INSTALL_FP2_SOCKET_SUPPORT == TRUE - #undef OPTION_FP2_SOCKET_SUPPORT - #define OPTION_FP2_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FT1_SOCKET_SUPPORT - #if INSTALL_FT1_SOCKET_SUPPORT == TRUE - #undef OPTION_FT1_SOCKET_SUPPORT - #define OPTION_FT1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FT2_SOCKET_SUPPORT - #if INSTALL_FT2_SOCKET_SUPPORT == TRUE - #undef OPTION_FT2_SOCKET_SUPPORT - #define OPTION_FT2_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_AM3_SOCKET_SUPPORT - #if INSTALL_AM3_SOCKET_SUPPORT == TRUE - #undef OPTION_AM3_SOCKET_SUPPORT - #define OPTION_AM3_SOCKET_SUPPORT TRUE - #endif -#endif - - -/* Enable the appropriate family support */ -// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3 -#ifdef INSTALL_FAMILY_10_SUPPORT - #if INSTALL_FAMILY_10_SUPPORT == TRUE - #undef OPTION_FAMILY10H - #define OPTION_FAMILY10H TRUE - #endif -#endif - -// F12 is supported in FP1, FS1, & FM1 -#ifdef INSTALL_FAMILY_12_SUPPORT - #if INSTALL_FAMILY_12_SUPPORT == TRUE - #undef OPTION_FAMILY12H - #define OPTION_FAMILY12H TRUE - #endif -#endif - -// F14 is supported in FT1 and FT2 -#ifdef INSTALL_FAMILY_14_SUPPORT - #if INSTALL_FAMILY_14_SUPPORT == TRUE - #undef OPTION_FAMILY14H - #define OPTION_FAMILY14H TRUE - #endif -#endif - -// F15_0x is supported in G34, C32, & AM3 -#ifdef INSTALL_FAMILY_15_MODEL_0x_SUPPORT - #if INSTALL_FAMILY_15_MODEL_0x_SUPPORT == TRUE - #undef OPTION_FAMILY15H - #define OPTION_FAMILY15H TRUE - #undef OPTION_FAMILY15H_MODEL_0x - #define OPTION_FAMILY15H_MODEL_0x TRUE - #endif -#endif - -// F15_1x is supported in FS1r2, FM2, & FP2 -#ifdef INSTALL_FAMILY_15_MODEL_1x_SUPPORT - #if INSTALL_FAMILY_15_MODEL_1x_SUPPORT == TRUE - #undef OPTION_FAMILY15H - #define OPTION_FAMILY15H TRUE - #undef OPTION_FAMILY15H_MODEL_1x - #define OPTION_FAMILY15H_MODEL_1x TRUE - #endif -#endif - -// F15_2x is supported in G2012, C2012, & FM2 -#ifdef INSTALL_FAMILY_15_MODEL_2x_SUPPORT - #if INSTALL_FAMILY_15_MODEL_2x_SUPPORT == TRUE - #undef OPTION_FAMILY15H - #define OPTION_FAMILY15H TRUE - #undef OPTION_FAMILY15H_MODEL_2x - #define OPTION_FAMILY15H_MODEL_2x TRUE - #endif -#endif - - -/* Turn off families not required by socket designations */ -#if (OPTION_FAMILY10H == TRUE) - #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY10H - #define OPTION_FAMILY10H FALSE - #endif -#endif - -#if (OPTION_FAMILY12H == TRUE) - #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY12H - #define OPTION_FAMILY12H FALSE - #endif -#endif - -#if (OPTION_FAMILY14H == TRUE) - #if (OPTION_FT1_SOCKET_SUPPORT == FALSE) && (OPTION_FT2_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY14H - #define OPTION_FAMILY14H FALSE - #endif -#endif - -#if (OPTION_FAMILY15H_MODEL_0x == TRUE) - #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY15H_MODEL_0x - #define OPTION_FAMILY15H_MODEL_0x FALSE - #endif -#endif - -#if (OPTION_FAMILY15H_MODEL_1x == TRUE) - #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM2_SOCKET_SUPPORT == FALSE) && (OPTION_FP2_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY15H_MODEL_1x - #define OPTION_FAMILY15H_MODEL_1x FALSE - #endif -#endif - -#if (OPTION_FAMILY15H_MODEL_2x == TRUE) - #if (OPTION_G2012_SOCKET_SUPPORT == FALSE) && (OPTION_C2012_SOCKET_SUPPORT == FALSE) && (OPTION_FM2_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY15H_MODEL_2x - #define OPTION_FAMILY15H_MODEL_2x FALSE - #endif -#endif - -#if (OPTION_FAMILY15H_MODEL_0x == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE) && (OPTION_FAMILY15H_MODEL_2x == FALSE) - #undef OPTION_FAMILY15H - #define OPTION_FAMILY15H FALSE -#endif - -/* Check for invalid combinations of socket/family */ -#if (OPTION_G34_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE) - #error No G34 supported families included in the build - #endif -#endif - -#if (OPTION_C32_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE) - #error No C32 supported families included in the build - #endif -#endif - -#if (OPTION_G2012_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY15H_MODEL_2x == FALSE) - #error No G2012 supported families included in the build - #endif -#endif - -#if (OPTION_C2012_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY15H_MODEL_2x == FALSE) - #error No C2012 supported families included in the build - #endif -#endif - -#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No S1G3 supported families included in the build - #endif -#endif - -#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No S1G4 supported families included in the build - #endif -#endif - -#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No ASB2 supported families included in the build - #endif -#endif - -#if (OPTION_FS1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE) - #error No FS1 supported families included in the build - #endif -#endif - -#if (OPTION_FM1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) - #error No FM1 supported families included in the build - #endif -#endif - -#if (OPTION_FM2_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY15H_MODEL_1x == FALSE) && (OPTION_FAMILY15H_MODEL_2x == FALSE) - #error No FM2 supported families included in the build - #endif -#endif - -#if (OPTION_FP1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) - #error No FP1 supported families included in the build - #endif -#endif - -#if (OPTION_FP2_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY15H_MODEL_1x == FALSE) - #error No FP2 supported families included in the build - #endif -#endif - -#if (OPTION_FT1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY14H == FALSE) - #error No FT1 supported families included in the build - #endif -#endif - -#if (OPTION_FT2_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY14H == FALSE) - #error No FT2 supported families included in the build - #endif -#endif - -#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE) - #error No AM3 supported families included in the build - #endif -#endif - - -/* Process AGESA private data - * - * Turn on appropriate CPU models and memory controllers, - * as well as some other memory controls. - */ - -/* Default all models to off */ -#define OPTION_FAMILY10H_BL FALSE -#define OPTION_FAMILY10H_DA FALSE -#define OPTION_FAMILY10H_HY FALSE -#define OPTION_FAMILY10H_PH FALSE -#define OPTION_FAMILY10H_RB FALSE -#define OPTION_FAMILY12H_LN FALSE -#define OPTION_FAMILY14H_ON FALSE -#define OPTION_FAMILY14H_KR FALSE -#define OPTION_FAMILY15H_OR FALSE -#define OPTION_FAMILY15H_TN FALSE -#define OPTION_FAMILY15H_KM FALSE - -/* Default all memory controllers to off */ -#define OPTION_MEMCTLR_DR FALSE -#define OPTION_MEMCTLR_HY FALSE -#define OPTION_MEMCTLR_OR FALSE -#define OPTION_MEMCTLR_C32 FALSE -#define OPTION_MEMCTLR_DA FALSE -#define OPTION_MEMCTLR_LN FALSE -#define OPTION_MEMCTLR_ON FALSE -#define OPTION_MEMCTLR_KR FALSE -#define OPTION_MEMCTLR_Ni FALSE -#define OPTION_MEMCTLR_PH FALSE -#define OPTION_MEMCTLR_RB FALSE -#define OPTION_MEMCTLR_TN FALSE -#define OPTION_MEMCTLR_KM FALSE - -/* Default all memory controls to off */ -#define OPTION_HW_WRITE_LEV_TRAINING FALSE -#define OPTION_SW_WRITE_LEV_TRAINING FALSE -#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE -#define OPTION_HW_DQS_REC_EN_TRAINING FALSE -#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE -#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE -#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE -#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE -#define OPTION_MAX_RD_LAT_TRAINING FALSE -#define OPTION_HW_DRAM_INIT FALSE -#define OPTION_SW_DRAM_INIT FALSE -#define OPTION_S3_MEM_SUPPORT FALSE -#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE -#define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE -#define OPTION_RDDQS____TRAINING FALSE - -/* Defaults for public user options */ -#define OPTION_UDIMMS FALSE -#define OPTION_RDIMMS FALSE -#define OPTION_SODIMMS FALSE -#define OPTION_LRDIMMS FALSE -#define OPTION_DDR2 FALSE -#define OPTION_DDR3 FALSE -#define OPTION_ECC FALSE -#define OPTION_BANK_INTERLEAVE FALSE -#define OPTION_DCT_INTERLEAVE FALSE -#define OPTION_NODE_INTERLEAVE FALSE -#define OPTION_PARALLEL_TRAINING FALSE -#define OPTION_ONLINE_SPARE FALSE -#define OPTION_MEM_RESTORE FALSE -#define OPTION_DIMM_EXCLUDE FALSE - -/* Default all CPU controls to off */ -#define OPTION_MULTISOCKET FALSE -#define OPTION_SRAT FALSE -#define OPTION_SLIT FALSE -#define OPTION_HT_ASSIST FALSE -#define OPTION_ATM_MODE FALSE -#define OPTION_CPU_CORELEVLING FALSE -#define OPTION_MSG_BASED_C1E FALSE -#define OPTION_CPU_CFOH FALSE -#define OPTION_C6_STATE FALSE -#define OPTION_IO_CSTATE FALSE -#define OPTION_CPB FALSE -#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE -#define OPTION_CPU_PSTATE_HPC_MODE FALSE -#define OPTION_CPU_APM FALSE -#define OPTION_S3SCRIPT FALSE -#define OPTION_GFX_RECOVERY FALSE - -/* Default FCH controls to off */ -#define FCH_SUPPORT FALSE - -/* Enable all private controls based on socket/family enables */ -#if (OPTION_G34_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_HY - #define OPTION_FAMILY10H_HY TRUE - #undef OPTION_MEMCTLR_HY - #define OPTION_MEMCTLR_HY TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H_MODEL_0x == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE - #undef OPTION_CPU_APM - #define OPTION_CPU_APM TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_C32_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_HY - #define OPTION_FAMILY10H_HY TRUE - #undef OPTION_MEMCTLR_C32 - #define OPTION_MEMCTLR_C32 TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H_MODEL_0x == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE - #undef OPTION_CPU_APM - #define OPTION_CPU_APM TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_Ni - #define OPTION_MEMCTLR_Ni TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_FAMILY10H_PH - #define OPTION_FAMILY10H_PH TRUE - #undef OPTION_FAMILY10H_RB - #define OPTION_FAMILY10H_RB TRUE - #undef OPTION_MEMCTLR_RB - #define OPTION_MEMCTLR_RB TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_MEMCTLR_PH - #define OPTION_MEMCTLR_PH TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H_MODEL_0x == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_APM - #define OPTION_CPU_APM TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#define OPTION_ACPI_PSTATES TRUE -#define OPTION_WHEA TRUE -#define OPTION_DMI TRUE -#define OPTION_EARLY_SAMPLES FALSE -#define CFG_ACPI_PSTATES_PPC TRUE -#define CFG_ACPI_PSTATES_PCT TRUE -#define CFG_ACPI_PSTATES_PSD TRUE -#define CFG_ACPI_PSTATES_PSS TRUE -#define CFG_ACPI_PSTATES_XPSS TRUE -#define CFG_ACPI_PSTATE_PSD_INDPX FALSE -#define CFG_VRM_HIGH_SPEED_ENABLE FALSE -#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define OPTION_ALIB TRUE -/*--------------------------------------------------------------------------- - * Processing the options: Second, process the user's selections - *--------------------------------------------------------------------------*/ -#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT - #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ECC_SUPPORT - #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE - #undef OPTION_ECC - #define OPTION_ECC FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT - #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT - #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT - #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT - #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE - #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE - #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE - #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING - #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT - #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING - #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE - #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING - #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ACPI_PSTATES - #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE - #undef OPTION_ACPI_PSTATES - #define OPTION_ACPI_PSTATES FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SRAT - #if BLDOPT_REMOVE_SRAT == TRUE - #undef OPTION_SRAT - #define OPTION_SRAT FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SLIT - #if BLDOPT_REMOVE_SLIT == TRUE - #undef OPTION_SLIT - #define OPTION_SLIT FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_WHEA - #if BLDOPT_REMOVE_WHEA == TRUE - #undef OPTION_WHEA - #define OPTION_WHEA FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_DMI - #if BLDOPT_REMOVE_DMI == TRUE - #undef OPTION_DMI - #define OPTION_DMI FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR - #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_HT_ASSIST - #if BLDOPT_REMOVE_HT_ASSIST == TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_ATM_MODE - #if BLDOPT_REMOVE_ATM_MODE == TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_MSG_BASED_C1E - #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_C6_STATE - #if BLDOPT_REMOVE_C6_STATE == TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_GFX_RECOVERY - #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC - #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE - #undef CFG_ACPI_PSTATES_PPC - #define CFG_ACPI_PSTATES_PPC FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT - #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE - #undef CFG_ACPI_PSTATES_PCT - #define CFG_ACPI_PSTATES_PCT FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD - #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE - #undef CFG_ACPI_PSTATES_PSD - #define CFG_ACPI_PSTATES_PSD FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS - #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE - #undef CFG_ACPI_PSTATES_PSS - #define CFG_ACPI_PSTATES_PSS FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS - #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE - #undef CFG_ACPI_PSTATES_XPSS - #define CFG_ACPI_PSTATES_XPSS FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT - #if BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT == TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE - #endif -#endif - -#ifdef BLDCFG_PSTATE_HPC_MODE - #if BLDCFG_PSTATE_HPC_MODE == TRUE - #undef OPTION_CPU_PSTATE_HPC_MODE - #define OPTION_CPU_PSTATE_HPC_MODE TRUE - #endif -#endif - -#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT - #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE - #undef CFG_ACPI_PSTATE_PSD_INDPX - #define CFG_ACPI_PSTATE_PSD_INDPX TRUE - #endif -#endif - -#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE - #undef CFG_VRM_HIGH_SPEED_ENABLE - #define CFG_VRM_HIGH_SPEED_ENABLE TRUE - #endif -#endif - -#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE - #undef CFG_VRM_NB_HIGH_SPEED_ENABLE - #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE - #endif -#endif - -#ifdef BLDCFG_STARTING_BUSNUM - #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM) -#else - #define CFG_STARTING_BUSNUM (0) -#endif - -#ifdef BLDCFG_AMD_PLATFORM_TYPE - #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE -#else - #define CFG_AMD_PLATFORM_TYPE 0 -#endif - -CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; - -#ifdef BLDCFG_MAXIMUM_BUSNUM - #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM) -#else - #define CFG_MAXIMUM_BUSNUM (0xF8) -#endif - -#ifdef BLDCFG_ALLOCATED_BUSNUM - #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM) -#else - #define CFG_ALLOCATED_BUSNUM (0x20) -#endif - -#ifdef BLDCFG_BUID_SWAP_LIST - #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST) -#else - #define CFG_BUID_SWAP_LIST (NULL) -#endif - -#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST - #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST) -#else - #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL) -#endif - -#ifdef BLDCFG_HTFABRIC_LIMITS_LIST - #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST) -#else - #define CFG_HTFABRIC_LIMITS_LIST (NULL) -#endif - -#ifdef BLDCFG_HTCHAIN_LIMITS_LIST - #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST) -#else - #define CFG_HTCHAIN_LIMITS_LIST (NULL) -#endif - -#ifdef BLDCFG_BUS_NUMBERS_LIST - #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST) -#else - #define CFG_BUS_NUMBERS_LIST (NULL) -#endif - -#ifdef BLDCFG_IGNORE_LINK_LIST - #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST) -#else - #define CFG_IGNORE_LINK_LIST (NULL) -#endif - -#ifdef BLDCFG_LINK_SKIP_REGANG_LIST - #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST) -#else - #define CFG_LINK_SKIP_REGANG_LIST (NULL) -#endif - -#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD - #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD) -#else - #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE) -#endif - -#ifdef BLDCFG_USE_UNIT_ID_CLUMPING - #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING) -#else - #define CFG_USE_UNIT_ID_CLUMPING (FALSE) -#endif - -#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST - #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST) -#else - #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL) -#endif - -#ifdef BLDCFG_USE_HT_ASSIST - #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST) -#else - #define CFG_USE_HT_ASSIST (TRUE) -#endif - -#ifdef BLDCFG_USE_ATM_MODE - #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE) -#else - #define CFG_USE_ATM_MODE (TRUE) -#endif - -#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE - #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE) -#else - #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm) -#endif - -#ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER - #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER) -#else - #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (HARDWARE_PREFETCHER_AUTO) -#endif - -#ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES - #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES) -#else - #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (SOFTWARE_PREFETCHES_AUTO) -#endif - -#ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER - #define CFG_PERFORMANCE_DRAM_PREFETCHER (BLDCFG_PERFORMANCE_DRAM_PREFETCHER) -#else - #define CFG_PERFORMANCE_DRAM_PREFETCHER (DRAM_PREFETCHER_AUTO) -#endif - -#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST - #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST) -#else - #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL) -#endif - -#ifdef BLDCFG_VRM_ADDITIONAL_DELAY - #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY) -#else - #define CFG_VRM_ADDITIONAL_DELAY (0) -#endif - -#ifdef BLDCFG_VRM_CURRENT_LIMIT - #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT -#else - #define CFG_VRM_CURRENT_LIMIT 0 -#endif - -#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD - #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD -#else - #define CFG_VRM_LOW_POWER_THRESHOLD 0 -#endif - -#ifdef BLDCFG_VRM_SLEW_RATE - #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#else - #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE -#endif - -#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT - #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT -#else - #define CFG_VRM_INRUSH_CURRENT_LIMIT 0 -#endif - -#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY - #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY) -#else - #define CFG_VRM_NB_ADDITIONAL_DELAY (0) -#endif - -#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT - #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT -#else - #define CFG_VRM_NB_CURRENT_LIMIT (0) -#endif - -#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD - #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD -#else - #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0) -#endif - -#ifdef BLDCFG_VRM_NB_SLEW_RATE - #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE -#else - #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE -#endif - -#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT - #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT -#else - #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0) -#endif - - -#ifdef BLDCFG_PLAT_NUM_IO_APICS - #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS -#else - #define CFG_PLAT_NUM_IO_APICS 0 -#endif - -#ifdef BLDCFG_MEM_INIT_PSTATE - #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE -#else - #define CFG_MEM_INIT_PSTATE 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_MODE - #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE -#else - #define CFG_C1E_MODE C1eModeDisabled -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA - #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA -#else - #define CFG_C1E_OPDATA 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA1 - #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1 -#else - #define CFG_C1E_OPDATA1 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA2 - #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2 -#else - #define CFG_C1E_OPDATA2 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA3 - #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3 -#else - #define CFG_C1E_OPDATA3 0 -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_MODE - #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE -#else - #define CFG_CSTATE_MODE CStateModeDisabled -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA - #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA -#else - #define CFG_CSTATE_OPDATA 0 -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS - #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS -#else - #define CFG_CSTATE_IO_BASE_ADDRESS 0 -#endif - -#ifdef BLDCFG_PLATFORM_CPB_MODE - #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE -#else - #define CFG_CPB_MODE CpbModeAuto -#endif - -#ifdef BLDCFG_CORE_LEVELING_MODE - #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE -#else - #define CFG_CORE_LEVELING_MODE 0 -#endif - -#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE - #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE -#else - #define CFG_AMD_PSTATE_CAP_VALUE 0 -#endif - -#ifdef BLDCFG_HEAP_DRAM_ADDRESS - #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS -#else - #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS -#endif - -#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT -#else - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY -#endif - -#ifdef BLDCFG_MEMORY_MODE_UNGANGED - #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED -#else - #define CFG_MEMORY_MODE_UNGANGED TRUE -#endif - -#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE - #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE -#else - #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_QUADRANK_TYPE - #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE -#else - #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE -#endif - -#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE - #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE -#else - #define CFG_MEMORY_RDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE - #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE -#else - #define CFG_MEMORY_LRDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE - #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE -#else - #define CFG_MEMORY_UDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE - #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE -#else - #define CFG_MEMORY_SODIMM_CAPABLE FALSE -#endif - -#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB - #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB -#else - #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE -#endif - -#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING - #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING -#else - #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#endif - -#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING - #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING -#else - #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#endif - -#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING - #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING -#else - #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#endif - -#ifdef BLDCFG_MEMORY_POWER_DOWN - #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN -#else - #define CFG_MEMORY_POWER_DOWN FALSE -#endif - -#ifdef BLDCFG_POWER_DOWN_MODE - #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE -#else - #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO -#endif - -#ifdef BLDCFG_ONLINE_SPARE - #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE -#else - #define CFG_ONLINE_SPARE FALSE -#endif - -#ifdef BLDCFG_MEMORY_PARITY_ENABLE - #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE -#else - #define CFG_MEMORY_PARITY_ENABLE FALSE -#endif - -#ifdef BLDCFG_BANK_SWIZZLE - #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE -#else - #define CFG_BANK_SWIZZLE TRUE -#endif - -#ifdef BLDCFG_TIMING_MODE_SELECT - #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT -#else - #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#endif - -#ifdef BLDCFG_MEMORY_CLOCK_SELECT - #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT -#else - #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY -#endif - -#ifdef BLDCFG_DQS_TRAINING_CONTROL - #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL -#else - #define CFG_DQS_TRAINING_CONTROL TRUE -#endif - -#ifdef BLDCFG_IGNORE_SPD_CHECKSUM - #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM -#else - #define CFG_IGNORE_SPD_CHECKSUM FALSE -#endif - -#ifdef BLDCFG_USE_BURST_MODE - #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE -#else - #define CFG_USE_BURST_MODE FALSE -#endif - -#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON - #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON -#else - #define CFG_MEMORY_ALL_CLOCKS_ON FALSE -#endif - -#ifdef BLDCFG_ENABLE_ECC_FEATURE - #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE -#else - #define CFG_ENABLE_ECC_FEATURE TRUE -#endif - -#ifdef BLDCFG_ECC_REDIRECTION - #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION -#else - #define CFG_ECC_REDIRECTION FALSE -#endif - -#ifdef BLDCFG_SCRUB_DRAM_RATE - #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE -#else - #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE -#endif - -#ifdef BLDCFG_SCRUB_L2_RATE - #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE -#else - #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE -#endif - -#ifdef BLDCFG_SCRUB_L3_RATE - #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE -#else - #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE -#endif - -#ifdef BLDCFG_SCRUB_IC_RATE - #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE -#else - #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE -#endif - -#ifdef BLDCFG_SCRUB_DC_RATE - #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE -#else - #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE -#endif - -#ifdef BLDCFG_ECC_SYNC_FLOOD - #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD -#else - #define CFG_ECC_SYNC_FLOOD TRUE -#endif - -#ifdef BLDCFG_ECC_SYMBOL_SIZE - #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE -#else - #define CFG_ECC_SYMBOL_SIZE 0 -#endif - -#ifdef BLDCFG_1GB_ALIGN - #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN -#else - #define CFG_1GB_ALIGN FALSE -#endif - -#ifdef BLDCFG_UMA_ALLOCATION_MODE - #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE -#else - #define CFG_UMA_MODE UMA_AUTO -#endif - -#ifdef BLDCFG_FORCE_TRAINING_MODE - #define CFG_FORCE_TRAIN_MODE BLDCFG_FORCE_TRAINING_MODE -#else - #define CFG_FORCE_TRAIN_MODE FORCE_TRAIN_AUTO -#endif - -#ifdef BLDCFG_UMA_ALLOCATION_SIZE - #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE -#else - #define CFG_UMA_SIZE 0 -#endif - -#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT - #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT -#else - #define CFG_UMA_ABOVE4G FALSE -#endif - -#ifdef BLDCFG_UMA_ALIGNMENT - #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT -#else - #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB - #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB -#else - #define CFG_PROCESSOR_SCOPE_IN_SB FALSE -#endif - -#ifdef BLDCFG_S3_LATE_RESTORE - #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE -#else - #define CFG_S3_LATE_RESTORE TRUE -#endif - -#ifdef BLDCFG_USE_32_BYTE_REFRESH - #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH) -#else - #define CFG_USE_32_BYTE_REFRESH (FALSE) -#endif - -#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY - #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY) -#else - #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE) -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0 - #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0 -#else - #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1 - #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1 -#else - #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1 -#endif - -#ifdef BLDCFG_CFG_GNB_HD_AUDIO - #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO -#else - #define CFG_GNB_HD_AUDIO TRUE -#endif - -#ifdef BLDCFG_CFG_ABM_SUPPORT - #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT -#else - #define CFG_ABM_SUPPORT FALSE -#endif - -#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE - #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE -#else - #define CFG_DYNAMIC_REFRESH_RATE 0 -#endif - -#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL - #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL -#else - #define CFG_LCD_BACK_LIGHT_CONTROL 0 -#endif - -#ifdef BLDCFG_STEREO_3D_PINOUT - #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT -#else - #define CFG_GNB_STEREO_3D_PINOUT 0 -#endif - -#ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT - #define CFG_GNB_REMOTE_DISPLAY_SUPPORT BLDCFG_REMOTE_DISPLAY_SUPPORT -#else - #define CFG_GNB_REMOTE_DISPLAY_SUPPORT FALSE -#endif - -#ifdef BLDCFG_IGPU_SUBSYSTEM_ID - #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID -#else - #define CFG_GNB_IGPU_SSID 0 -#endif - -#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID - #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID -#else - #define CFG_GNB_HDAUDIO_SSID 0 -#endif - -#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID - #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID -#else - #define CFG_GNB_PCIE_SSID 0x12341022 -#endif - -#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM - #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM -#else - #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0 -#endif - -#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE - #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE -#else - #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0 -#endif - -#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM - #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM -#else - #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0 -#endif - -#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS - #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS -#else - #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -#endif - -#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE - #define CFG_ENABLE_EXTERNAL_VREF BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE -#else - #define CFG_ENABLE_EXTERNAL_VREF FALSE -#endif - -#ifdef BLDOPT_REMOVE_EARLY_SAMPLES - #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE - #undef OPTION_EARLY_SAMPLES - #define OPTION_EARLY_SAMPLES FALSE - #else - #undef OPTION_EARLY_SAMPLES - #define OPTION_EARLY_SAMPLES TRUE - #endif -#endif - -#ifdef BLDOPT_REMOVE_ALIB - #if BLDOPT_REMOVE_ALIB == TRUE - #undef OPTION_ALIB - #define OPTION_ALIB FALSE - #else - #undef OPTION_ALIB - #define OPTION_ALIB TRUE - #endif -#endif - -#ifdef BLDOPT_REMOVE_FCH_COMPONENT - #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE - #undef FCH_SUPPORT - #define FCH_SUPPORT FALSE - #endif -#endif - -#ifdef BLDCFG_IOMMU_SUPPORT - #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT -#else - #define CFG_IOMMU_SUPPORT TRUE -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE - #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE -#else - #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL -#else - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON -#else - #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0 -#endif - -#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE - #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE -#else - #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY - #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY -#else - #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON - #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON -#else - #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0 -#endif - -#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL - #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL -#else - #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0 -#endif - -#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ - #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ -#else - #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0 -#endif - -#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE - #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE -#else - #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0 -#endif - - -// BLDCFG_LVDS_24BBP_PANEL_MODE -// This specifies the LVDS 24 BBP mode. -// 0 - Use LDI mode (default). -// 1 - Use FPDI mode. -#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE - #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE -#else - #define CFG_LVDS_24BBP_PANEL_MODE 0 -#endif - -#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE - #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE -#else - #define CFG_LVDS_MISC_888_FPDI_MODE FALSE -#endif - -#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP - #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP -#else - #define CFG_LVDS_MISC_DL_CH_SWAP FALSE -#endif - -#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW - #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW -#else - #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE -#endif - -#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW - #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW -#else - #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE -#endif - -#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW - #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW -#else - #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE -#endif - -#ifdef BLDCFG_FORCE_MICROSERVER - #define CFG_FORCE_MICROSERVER BLDCFG_FORCE_MICROSERVER -#else - #define CFG_FORCE_MICROSERVER FALSE -#endif - -#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE - #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE) -#else - #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) -#endif - -#ifdef BLDCFG_PCI_MMIO_BASE - #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE) -#else - #define CFG_PCI_MMIO_BASE (0) -#endif - -#ifdef BLDCFG_PCI_MMIO_SIZE - #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE) -#else - #define CFG_PCI_MMIO_SIZE (0) -#endif - -#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST - #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) -#else - #define CFG_AP_MTRR_SETTINGS_LIST (NULL) -#endif - -#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST - #define CFG_IOMMU_EXCLUSION_RANGE_LIST (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST) -#else - #define CFG_IOMMU_EXCLUSION_RANGE_LIST (NULL) -#endif - -/*--------------------------------------------------------------------------- - * Processing the options: Third, perform the option cross checks - *--------------------------------------------------------------------------*/ -// Assure that at least one type of memory support is included -#if OPTION_UDIMMS == FALSE - #if OPTION_RDIMMS == FALSE - #if OPTION_SODIMMS == FALSE - #if OPTION_LRDIMMS == FALSE - #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE. - #endif - #endif - #endif -#endif -// Ensure at least one dimm type is capable -#if CFG_MEMORY_RDIMM_CAPABLE == FALSE - #if CFG_MEMORY_UDIMM_CAPABLE == FALSE - #if CFG_MEMORY_SODIMM_CAPABLE == FALSE - #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE - #error BLDCFG: No dimm type is capable - #endif - #endif - #endif -#endif -// Turn off multi-socket based features if only one node... -#if OPTION_MULTISOCKET == FALSE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING FALSE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE FALSE -#endif -// Ensure that at least one write leveling option is selected -#if OPTION_DDR3 == TRUE - #if OPTION_HW_WRITE_LEV_TRAINING == FALSE - #if OPTION_SW_WRITE_LEV_TRAINING == FALSE - #error No Write leveling option selected for DDR3 - #endif - #endif - #if OPTION_SW_DRAM_INIT == FALSE - #error Software dram init must be enabled for DDR3 dimms - #endif -#endif -// Ensure at least one DQS receiver training option is selected -#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE - #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE - #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE - #error No DQS receiver training option has been slected - #endif - #endif -#endif -// Ensure at least one Rd Wr position training option has been selected -#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE - #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE - #error No Rd Wr position training option has been selected - #endif -#endif -// Ensure at least one dram init option has been selected -#if OPTION_HW_DRAM_INIT == FALSE - #if OPTION_SW_DRAM_INIT == FALSE - #error No Dram init option has been selected - #endif -#endif -// Ensure the frequency limit is valid -#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200) - #error BLDCFG: Unsupported memory bus frequency - #endif - #endif - #endif - #endif - #endif - #endif - #endif -#endif -// Ensure timing mode is valid -#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC - #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED - #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO - #error BLDCFG: Invalid timing mode is set - #endif - #endif -#endif -// Ensure the scrub rate is valid -#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF)) - #error BLDCFG: Unsupported dram scrub rate set -#endif -#if CFG_SCRUB_L2_RATE > 0x16 - #error BLDCFG: Unsupported L2 scrubber rate set -#endif -#if CFG_SCRUB_L3_RATE > 0x16 - #error BLDCFG: unsupported L3 scrubber rate set -#endif -#if CFG_SCRUB_IC_RATE > 0x16 - #error BLDCFG: Unsupported Instruction cache scrub rate set -#endif -#if CFG_SCRUB_DC_RATE > 0x16 - #error BLDCFG: Unsupported Dcache scrub rate set -#endif -// Ensure Quad rank dimm type is valid -#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED - #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED - #error BLDCFG: Invalid quad rank dimm type set - #endif -#endif -// Ensure ECC symbol size is valid -#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG - #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4 - #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8 - #error BLDCFG: Invalid Ecc symbol size set - #endif - #endif -#endif -// Ensure power down mode is valid -#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT - #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL - #error BLDCFG: Invalid power down mode set - #endif -#endif - -/***************************************************************************** - * - * Process the option logic, setting local control variables - * - ****************************************************************************/ -#if OPTION_ACPI_PSTATES == TRUE - #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain - #define OPTFCN_GATHER_DATA PStateGatherData - #if OPTION_MULTISOCKET == TRUE - #define OPTFCN_PSTATE_LEVELING PStateLeveling - #else - #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess - #endif -#else - #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess - #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess - #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess -#endif - - -/***************************************************************************** - * - * Include the structure definitions for the defaults table structures - * - ****************************************************************************/ -#include -#include -#include "Options.h" -#include "OptionCpuFamiliesInstall.h" -#include "OptionsHt.h" -#include "OptionHtInstall.h" -#include "OptionMemory.h" -#include "OptionMemoryInstall.h" -#include "OptionCpuFeaturesInstall.h" -#include "OptionDmi.h" -#include "OptionDmiInstall.h" -#include "OptionPstate.h" -#include "OptionPstateInstall.h" -#include "OptionWhea.h" -#include "OptionWheaInstall.h" -#include "OptionSrat.h" -#include "OptionSratInstall.h" -#include "OptionSlit.h" -#include "OptionSlitInstall.h" -#include "OptionMultiSocket.h" -#include "OptionMultiSocketInstall.h" -#include "OptionIdsInstall.h" -#include "OptionGfxRecovery.h" -#include "OptionGfxRecoveryInstall.h" -#include "OptionGnb.h" -#include "OptionGnbInstall.h" -#include "OptionS3ScriptInstall.h" -#include "OptionFchInstall.h" - - -/***************************************************************************** - * - * Generate the output structures (defaults tables) - * - ****************************************************************************/ - -FCH_PLATFORM_POLICY FchUserOptions = { - CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress - CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress - CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress - CFG_ACPI_PM1_EVT_BLOCK_ADDRESS, // CfgAcpiPm1EvtBlkAddr - CFG_ACPI_PM1_CNT_BLOCK_ADDRESS, // CfgAcpiPm1CntBlkAddr - CFG_ACPI_PM_TMR_BLOCK_ADDRESS, // CfgAcpiPmTmrBlkAddr - CFG_ACPI_CPU_CNT_BLOCK_ADDRESS, // CfgCpuControlBlkAddr - CFG_ACPI_GPE0_BLOCK_ADDRESS, // CfgAcpiGpe0BlkAddr - CFG_SMI_CMD_PORT_ADDRESS, // CfgSmiCmdPortAddr - CFG_ACPI_PMA_CNTBLK_ADDRESS, // CfgAcpiPmaCntBlkAddr - CFG_GEC_SHADOW_ROM_BASE, // CfgGecShadowRomBase - CFG_WATCHDOG_TIMER_BASE, // CfgWatchDogTimerBase - CFG_SPI_ROM_BASE_ADDRESS, // CfgSpiRomBaseAddress - CFG_HPET_BASE_ADDRESS, // CfgHpetBaseAddress - CFG_AZALIA_SSID, // CfgAzaliaSsid - CFG_SMBUS_SSID, // CfgSmbusSsid - CFG_IDE_SSID, // CfgIdeSsid - CFG_SATA_AHCI_SSID, // CfgSataAhciSsid - CFG_SATA_IDE_SSID, // CfgSataIdeSsid - CFG_SATA_RAID5_SSID, // CfgSataRaid5Ssid - CFG_SATA_RAID_SSID, // CfgSataRaidSsid - CFG_EHCI_SSID, // CfgEhcidSsid - CFG_OHCI_SSID, // CfgOhcidSsid - CFG_LPC_SSID, // CfgLpcSsid - CFG_SD_SSID, // CfgSdSsid - CFG_XHCI_SSID, // CfgXhciSsid - CFG_FCH_PORT80_BEHIND_PCIB, // CfgFchPort80BehindPcib - CFG_FCH_ENABLE_ACPI_SLEEP_TRAP, // CfgFchEnableAcpiSleepTrap - CFG_FCH_GPP_LINK_CONFIG, // CfgFchGppLinkConfig - CFG_FCH_GPP_PORT0_PRESENT, // CfgFchGppPort0Present - CFG_FCH_GPP_PORT1_PRESENT, // CfgFchGppPort1Present - CFG_FCH_GPP_PORT2_PRESENT, // CfgFchGppPort2Present - CFG_FCH_GPP_PORT3_PRESENT, // CfgFchGppPort3Present - CFG_FCH_GPP_PORT0_HOTPLUG, // CfgFchGppPort0HotPlug - CFG_FCH_GPP_PORT1_HOTPLUG, // CfgFchGppPort1HotPlug - CFG_FCH_GPP_PORT2_HOTPLUG, // CfgFchGppPort2HotPlug - CFG_FCH_GPP_PORT3_HOTPLUG, // CfgFchGppPort3HotPlug - - CFG_FCH_ESATA_PORT_BITMAP, // CfgFchEsataPortBitMap - CFG_FCH_IR_PIN_CONTROL, // CfgFchIrPinControl - CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl - CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl - CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl - CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl -}; - -BUILD_OPT_CFG UserOptions = { - { // AGESA version string - AGESA_CODE_SIGNATURE, // code header Signature - AGESA_PACKAGE_STRING, // 8 character ID - AGESA_VERSION_STRING, // 12 character version string - 0 // null string terminator - }, - //Build Option Area - OPTION_UDIMMS, //UDIMMS - OPTION_RDIMMS, //RDIMMS - OPTION_LRDIMMS, //LRDIMMS - OPTION_ECC, //ECC - OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE - OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE - OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE - OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING - OPTION_ONLINE_SPARE, //ONLINE_SPARE - OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE - OPTION_MULTISOCKET, //MULTISOCKET - OPTION_ACPI_PSTATES, //ACPI_PSTATES - OPTION_CPU_PSTATE_HPC_MODE, //High Preformace Computing (HPC) mode - OPTION_SRAT, //SRAT - OPTION_SLIT, //SLIT - OPTION_WHEA, //WHEA - OPTION_DMI, //DMI - OPTION_EARLY_SAMPLES, //EARLY_SAMPLES - OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR - - //Build Configuration Area - CFG_PCI_MMIO_BASE, - CFG_PCI_MMIO_SIZE, - { - // CoreVrm - { - CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit - CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold - CFG_VRM_SLEW_RATE, // VrmSlewRate - CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay - CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable - CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit - }, - // NbVrm - { - CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit - CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold - CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate - CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay - CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable - CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit - } - }, - CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber - CFG_MEM_INIT_PSTATE, //MemoryInitPstate - CFG_C1E_MODE, //C1eMode - CFG_C1E_OPDATA, //C1ePlatformData - CFG_C1E_OPDATA1, //C1ePlatformData1 - CFG_C1E_OPDATA2, //C1ePlatformData2 - CFG_C1E_OPDATA3, //C1ePlatformData3 - CFG_CSTATE_MODE, //CStateMode - CFG_CSTATE_OPDATA, //CStatePlatformData - CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress - CFG_CPB_MODE, //CpbMode - LOW_POWER_PSTATE_FOR_PROCHOT_AUTO, //Low power Pstate for PROCHOT, it's always set to 'AUTO' - CFG_CORE_LEVELING_MODE, //CoreLevelingCofig - { - CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode. - CFG_USE_HT_ASSIST, // CfgUseHtAssist - CFG_USE_ATM_MODE, // CfgUseAtmMode - CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets. - CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority. - // ADVANCED_PERFORMANCE_PROFILE - { - CFG_PERFORMANCE_HARDWARE_PREFETCHER, // Hardware prefetcher mode - CFG_PERFORMANCE_SOFTWARE_PREFETCHES, // Software prefetcher mode - CFG_PERFORMANCE_DRAM_PREFETCHER // Dram prefetcher mode - }, - CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode. - }, - (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings - CFG_AMD_PLATFORM_TYPE, //AmdPlatformType - CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck - - CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit - CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged - CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable - CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType - CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable - CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable - CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable - CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable - CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb - CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving - CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving - CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving - CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown - CFG_POWER_DOWN_MODE, // CfgPowerDownMode - CFG_ONLINE_SPARE, // CfgOnlineSpare - CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable - CFG_BANK_SWIZZLE, // CfgBankSwizzle - CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect - CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect - CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl - CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum - CFG_USE_BURST_MODE, // CfgUseBurstMode - CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn - CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature - CFG_ECC_REDIRECTION, // CfgEccRedirection - CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate - CFG_SCRUB_L2_RATE, // CfgScrubL2Rate - CFG_SCRUB_L3_RATE, // CfgScrubL3Rate - CFG_SCRUB_IC_RATE, // CfgScrubIcRate - CFG_SCRUB_DC_RATE, // CfgScrubDcRate - CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood - CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize - CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress - CFG_1GB_ALIGN, // CfgNodeMem1GBAlign - CFG_S3_LATE_RESTORE, // CfgS3LateRestore - CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent - (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList - CFG_UMA_MODE, // CfgUmaMode - CFG_UMA_SIZE, // CfgUmaSize - CFG_UMA_ABOVE4G, // CfgUmaAbove4G - CFG_UMA_ALIGNMENT, // CfgUmaAlignment - CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb - CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0 - CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1 - CFG_GNB_HD_AUDIO, // CfgGnbHdAudio - CFG_ABM_SUPPORT, // CfgAbmSupport - CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate - CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl - CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex - CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress - CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID - CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID - CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID - CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum - CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate - - &FchUserOptions, // FchBldCfg - - CFG_IOMMU_SUPPORT, // CfgIommuSupport - CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE, // CfgLvdsPowerOnSeqDigonToDe - CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL, // CfgLvdsPowerOnSeqDeToVaryBl - CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON, // CfgLvdsPowerOnSeqDeToDigon - CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe - CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay - CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon - CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl - CFG_LVDS_MAX_PIXEL_CLOCK_FREQ, // CfgLvdsMaxPixelClockFreq - CFG_LCD_BIT_DEPTH_CONTROL_VALUE, // CfgLcdBitDepthControlValue - CFG_LVDS_24BBP_PANEL_MODE, // CfgLvds24bbpPanelMode - {{ - CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl - CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl - CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl - CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl - CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl - }}, - CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum - CFG_ENABLE_EXTERNAL_VREF, // CfgExternalVrefCtlFeature - CFG_FORCE_TRAIN_MODE, // CfgForceTrainMode - CFG_GNB_REMOTE_DISPLAY_SUPPORT, // CfgGnbRemoteDisplaySupport - (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList - 0, //reserved... -}; - -CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = -{ - IDS_LATE_RUN_AP_TASK - // Get DMI info - CPU_DMI_AP_GET_TYPE4_TYPE7 - // Probe filter enable - L3_FEAT_AP_DISABLE_CACHE - L3_FEAT_AP_ENABLE_CACHE - // Cpu Late Init - CPU_LATE_INIT_AP_TASK - { 0, NULL } -}; - -#if AGESA_ENTRY_INIT_EARLY == TRUE - #if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_TRACING_ENABLED == TRUE - #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y) - CONST CHAR8 *BldOptDebugOutput[] = { - #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE - //Build Option Area - MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS) - MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS) - MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS) - MAKE_DBG_STR (\nOptECC, OPTION_ECC) - MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE) - MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE) - MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE) - //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING) - MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE) - MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR) - MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE) - MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET) - MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES) - MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT) - MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT) - MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA) - MAKE_DBG_STR (\nOptDMI, OPTION_DMI) - MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES), - - //Build Configuration Area - // CoreVrm - MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT) - MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD) - MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE) - MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY) - MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE) - MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT) - // NbVrm - MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT) - MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD) - MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE) - MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY) - MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE) - MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT), - - MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS) - MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE) - MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE) - MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA) - MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1) - MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2) - MAKE_DBG_STR (\nC1eOpdata3 , CFG_C1E_OPDATA3) - MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE) - MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA) - MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS) - MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE) - MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE), - - MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE) - MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST) - MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE) - MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH) - MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY) - MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD) - - MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST) - - MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE) - MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE) - MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE) - MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE), - - MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT) - MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT) - MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT) - - MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED) - MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE) - MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE) - MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE) - MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE) - MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE) - MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE) - MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL) - MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM) - MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE) - MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON), - - MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN) - MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE) - MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE) - MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE) - MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE) - MAKE_DBG_STR (\nLimitBelow1TB , CFG_LIMIT_MEMORY_TO_BELOW_1TB) - MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING) - MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING) - MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING), - - MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE) - MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE) - MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G) - MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT) - - MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE) - MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION) - MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE) - MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE) - MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE) - MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE) - MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE) - MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD) - MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE) - MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS) - MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN), - - MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE) - MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX) - - MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST) - - MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB) - MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0) - MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1) - MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO) - MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT) - MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE) - MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL) - MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT) - MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS), - MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID) - MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID) - MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID) - MAKE_DBG_STR (\nCfgIommuSupport , CFG_IOMMU_SUPPORT) - MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM) - MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON) - MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL) - MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ) - MAKE_DBG_STR (\nCfgLcdBitDepthControlValue , CFG_LCD_BIT_DEPTH_CONTROL_VALUE) - MAKE_DBG_STR (\nCfgLvds24bbpPanelMode , CFG_LVDS_24BBP_PANEL_MODE), - MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE), - MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP), - MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW), - MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW), - MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW), - MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM), - MAKE_DBG_STR (\nCfgExtVref , CFG_ENABLE_EXTERNAL_VREF), - MAKE_DBG_STR (\nCfgForceTrainMode , CFG_FORCE_TRAIN_MODE), - MAKE_DBG_STR (\nCfgGnbRemoteDisplaySupport , CFG_GNB_REMOTE_DISPLAY_CONFIG), - MAKE_DBG_STR (\nCfgIvrsExclusionRangeList , CFG_IOMMU_EXCLUSION_RANGE_LIST), - #endif - NULL - }; - #endif - #endif -#endif diff --git a/src/vendorcode/amd/agesa/f15/Dispatcher.h b/src/vendorcode/amd/agesa/f15/Dispatcher.h deleted file mode 100644 index a17757b1cc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Dispatcher.h +++ /dev/null @@ -1,50 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Pushhigh Interface - * - * Contains interface to Pushhigh entry - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Legacy - * - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - */ - -#ifndef _DISPATCHER_H_ -#define _DISPATCHER_H_ - -// AGESA function prototypes -AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr ); -AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINTN Data, IN OUT VOID *ConfigPtr ); - -#endif // _DISPATCHER_H_ diff --git a/src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h deleted file mode 100644 index 666377f4f3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h +++ /dev/null @@ -1,165 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Advanced API Interface for HT, Memory and CPU - * - * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as - * would be required by the basic interface implementations. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - -#ifndef _ADVANCED_API_H_ -#define _ADVANCED_API_H_ - -/*---------------------------------------------------------------------------- - * HT FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * A constructor for the HyperTransport input structure. - * - * Sets inputs to valid, basic level, defaults. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] AmdHtInterface HT Interface structure to initialize. - * - * @retval AGESA_SUCCESS Constructors are not allowed to fail -*/ -AGESA_STATUS -AmdHtInterfaceConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_INTERFACE *AmdHtInterface - ); - -/** - * The top level external interface for Hypertransport Initialization. - * - * Create our initial internal state, initialize the coherent fabric, - * initialize the non-coherent chains, and perform any required fabric tuning or - * optimization. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] PlatformConfiguration The platform configuration options. - * @param[in] AmdHtInterface HT Interface structure. - * - * @retval AGESA_SUCCESS Only information events logged. - * @retval AGESA_ALERT Sync Flood or CRC error logged. - * @retval AGESA_WARNING Example: expected capability not found - * @retval AGESA_ERROR logged events indicating some devices may not be available - * @retval AGESA_FATAL Mixed Family or MP capability mismatch - * - */ -AGESA_STATUS -AmdHtInitialize ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfiguration, - IN AMD_HT_INTERFACE *AmdHtInterface - ); - -/*---------------------------------------------------------------------------- - * HT Recovery FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * A constructor for the HyperTransport input structure. - * - */ -AGESA_STATUS -AmdHtResetConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ); - -/** - * Initialize HT at Reset for both Normal and Recovery. - * - */ -AGESA_STATUS -AmdHtInitReset ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ); - -/** - * Initialize the Node and Socket maps for an AP Core. - * - */ -AGESA_STATUS -AmdHtInitRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -///---------------------------------------------------------------------------- -/// MEMORY FUNCTIONS PROTOTYPE -/// -///---------------------------------------------------------------------------- - -AGESA_STATUS -AmdMemRecovery ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -AGESA_STATUS -AmdMemAuto ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -AmdMemInitDataStructDef ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT PLATFORM_CONFIGURATION *PlatFormConfig - ); - -VOID -memDefRet ( VOID ); - -BOOLEAN -memDefTrue ( VOID ); - -BOOLEAN -memDefFalse ( VOID ); - -VOID -MemRecDefRet ( VOID ); - -BOOLEAN -MemRecDefTrue ( VOID ); - -#endif // _ADVANCED_API_H_ diff --git a/src/vendorcode/amd/agesa/f15/Include/CommonReturns.h b/src/vendorcode/amd/agesa/f15/Include/CommonReturns.h deleted file mode 100644 index ada41543a3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Include/CommonReturns.h +++ /dev/null @@ -1,123 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Common Return routines. - * - * Routines which do nothing, returning a result (preferably some version of zero) which - * is consistent with "do nothing" or "default". Useful for function pointer tables. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _COMMON_RETURNS_H_ -#define _COMMON_RETURNS_H_ - - -/** -* Return True -* -* @retval True Default case, no special action -*/ -BOOLEAN -CommonReturnTrue ( VOID ); - -/** -* Return False. -* -* @retval FALSE Default case, no special action -*/ -BOOLEAN -CommonReturnFalse ( VOID ); - -/** - * Return (UINT8)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT8 -CommonReturnZero8 ( VOID ); - -/** - * Return (UINT32)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT32 -CommonReturnZero32 ( VOID ); - -/** - * Return (UINT64)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT64 -CommonReturnZero64 ( VOID ); - -/** - * Return NULL - * - * @retval NULL pointer to nothing - */ -VOID * -CommonReturnNULL ( VOID ); - -/** -* Return AGESA_SUCCESS. -* -* @retval AGESA_SUCCESS Success. -*/ -AGESA_STATUS -CommonReturnAgesaSuccess ( VOID ); - -/** - * Do Nothing. - * - */ -VOID -CommonVoid ( VOID ); - -/** - * ASSERT if this routine is called. - * - */ -VOID -CommonAssert ( VOID ); - -#endif // _COMMON_RETURNS_H_ diff --git a/src/vendorcode/amd/agesa/f15/Include/Filecode.h b/src/vendorcode/amd/agesa/f15/Include/Filecode.h deleted file mode 100644 index 0d9f67af11..0000000000 --- a/src/vendorcode/amd/agesa/f15/Include/Filecode.h +++ /dev/null @@ -1,1174 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Collectively assign unique filecodes for assert and debug to each source file. - * - * Publish values for decorated filenames, which can be used for - * ASSERT and debug support using a preprocessor define like: - * @n \#define FILECODE MY_C_FILENAME_FILECODE @n - * This file serves as a reference for debugging to associate the code and filename. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 56033 $ @e \$Date: 2011-07-06 01:12:20 -0600 (Wed, 06 Jul 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _FILECODE_H_ -#define _FILECODE_H_ - -#define UNASSIGNED_FILE_FILECODE (0xFFFF) - -/// For debug use in any Platform's options C file. -/// Can be reused for platforms and image builds, since only one options file can be built. -#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB) - - -#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001) -#define PROC_GNB_GFX_FAMILY_LN_F12GFXSERVICES_FILECODE (0xA002) -#define PROC_GNB_GFX_FAMILY_ON_F14GFXSERVICES_FILECODE (0xA003) -#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE (0xA004) -#define PROC_GNB_GFX_GFXGMCINIT_FILECODE (0xA006) -#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE (0xA010) -#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE (0xA011) -#define PROC_GNB_GFX_GFXINITATPOST_FILECODE (0xA012) -#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE (0xA013) -#define PROC_GNB_GFX_GFXLIB_FILECODE (0xA014) -#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE (0xA015) -#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE (0xA016) -#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017) -#define PROC_GNB_GNBINITATENV_FILECODE (0xA020) -#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021) -#define PROC_GNB_GNBINITATMID_FILECODE (0xA022) -#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023) -#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033) -#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034) -#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE (0xA035) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE (0xA03A) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049) -#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A) -#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B) -#define PROC_GNB_NB_FAMILY_LN_F12NBPOWERGATE_FILECODE (0xA04C) -#define PROC_GNB_NB_FAMILY_LN_F12NBSERVICES_FILECODE (0xA04D) -#define PROC_GNB_NB_FAMILY_LN_F12NBSMU_FILECODE (0xA04E) -#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKNCLKRATIO_FILECODE (0xA04F) -#define PROC_GNB_NB_FAMILY_ON_F14NBPOWERGATE_FILECODE (0xA050) -#define PROC_GNB_NB_FAMILY_ON_F14NBSERVICES_FILECODE (0xA051) -#define PROC_GNB_NB_FAMILY_ON_F14NBSMU_FILECODE (0xA052) -#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE (0xA053) -#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE (0xA054) -#define PROC_GNB_NB_FAMILY_LN_F12NBLCLKDPM_FILECODE (0xA055) -#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKDPM_FILECODE (0xA056) -#define PROC_GNB_NB_NBCONFIGDATA_FILECODE (0xA060) -#define PROC_GNB_NB_NBINIT_FILECODE (0xA061) -#define PROC_GNB_NB_NBINITATEARLY_FILECODE (0xA062) -#define PROC_GNB_NB_NBINITATENV_FILECODE (0xA063) -#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE (0xA070) -#define PROC_GNB_NB_NBINITATPOST_FILECODE (0xA071) -#define PROC_GNB_NB_NBINITATRESET_FILECODE (0xA072) -#define PROC_GNB_NB_NBPOWERMGMT_FILECODE (0xA073) -#define PROC_GNB_NB_NBSMULIB_FILECODE (0xA074) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIB_FILECODE (0xA075) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXCONFIG_FILECODE (0xA076) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXSERVICES_FILECODE (0xA077) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPHYSERVICES_FILECODE (0xA078) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPIFSERVICES_FILECODE (0xA079) -#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEWRAPPERSERVICES_FILECODE (0xA07A) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEALIB_FILECODE (0xA07D) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXCONFIG_FILECODE (0xA07E) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXSERVICES_FILECODE (0xA07F) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPHYSERVICES_FILECODE (0xA080) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPIFSERVICES_FILECODE (0xA081) -#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEWRAPPERSERVICES_FILECODE (0xA082) -#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE (0xA083) -#define PROC_GNB_PCIE_PCIEINIT_FILECODE (0xA084) -#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE (0xA085) -#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE (0xA086) -#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE (0xA087) -#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE (0xA088) -#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE (0xA089) -#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE (0xA08B) -#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE (0xA08C) -#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE (0xA08D) -#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E) -#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F) -#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE (0xA090) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE (0xA091) -#define PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE (0xA092) -#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE (0xA093) -#define PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE (0xA094) -#define PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE (0xA095) -#define PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE (0xA096) -#define PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE (0xA097) -#define PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE (0xA098) -#define PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE (0xA09A) -#define PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE (0xA09B) -#define PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE (0xA09C) -#define PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE (0xA09D) -#define PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE (0xA09E) -#define PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE (0xA09F) -#define PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE (0xA0A0) -#define PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE (0xA0A1) -#define PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE (0xA0A2) -#define PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE (0xA0A3) -#define PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE (0xA0A4) -#define PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE (0xA0A5) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6) -#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE (0xA0A7) -#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE (0xA0A8) -#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE (0xA0A9) -#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE (0xA0AA) -#define PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE (0xA0AB) -#define PROC_GNB_GFX_FAMILY_KR_KRGFXSERVICES_FILECODE (0xA0AC) -#define PROC_GNB_NB_FAMILY_KR_KRNBSMU_FILECODE (0xA0AD) -#define PROC_GNB_NB_FAMILY_KR_KRNBPOWERGATE_FILECODE (0xA0AE) -#define PROC_GNB_NB_FAMILY_KR_KRNBSERVICES_FILECODE (0xA0AF) -#define PROC_GNB_NB_FAMILY_KR_KRNBLCLKNCLKRATIO_FILECODE (0xA0B0) -#define PROC_GNB_NB_FAMILY_KR_KRNBLCLKDPM_FILECODE (0xA0B1) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEALIB_FILECODE (0xA0B2) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIECOMPLEXCONFIG_FILECODE (0xA0B3) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIECOMPLEXSERVICES_FILECODE (0xA0B4) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEPHYSERVICES_FILECODE (0xA0B5) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEWRAPPERSERVICES_FILECODE (0xA0B6) -#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEPIFSERVICES_FILECODE (0xA0B7) -#define PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE (0xA0B8) -#define PROC_GNB_MODULES_GNBINITTN_PCIEALIBTN_FILECODE (0xA0B9) -#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE (0xA0BA) -#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE (0xA0BB) -#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE (0xA0BC) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBSTALL_FILECODE (0xA0BD) -#define PROC_GNB_MODULES_GNBMSOCKETLIB_GNBMSOCKETLIB_FILECODE (0xA0BE) -#define PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE (0xA0BF) -#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE (0xA0C0) - -#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPHYSERVICESV5_FILECODE (0xA0C5) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE (0xA0C6) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE (0xA0C7) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE (0xA0C8) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA) -#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE (0xA0CB) - -#define PROC_GNB_MODULES_GNBINITKM_GNBEARLYINITKM_FILECODE (0xA0CC) -#define PROC_GNB_MODULES_GNBINITKM_GNBENVINITKM_FILECODE (0xA0CD) -#define PROC_GNB_MODULES_GNBINITKM_GNBIOMMUIVRSKM_FILECODE (0xA0CE) -#define PROC_GNB_MODULES_GNBINITKM_GNBMIDINITKM_FILECODE (0xA0CF) -#define PROC_GNB_MODULES_GNBINITKM_GNBPOSTINITKM_FILECODE (0xA0D0) -#define PROC_GNB_MODULES_GNBINITKM_GNBREGISTERACCKM_FILECODE (0xA0D1) -#define PROC_GNB_MODULES_GNBINITKM_PCIECOMPLEXDATAKMC2012_FILECODE (0xA0D2) -#define PROC_GNB_MODULES_GNBINITKM_PCIECOMPLEXDATAKMFM2_FILECODE (0xA0D3) -#define PROC_GNB_MODULES_GNBINITKM_PCIECOMPLEXDATAKMG2012_FILECODE (0xA0D4) -#define PROC_GNB_MODULES_GNBINITKM_PCIECONFIGKM_FILECODE (0xA0D5) -#define PROC_GNB_MODULES_GNBINITKM_PCIEEARLYINITKM_FILECODE (0xA0D6) -#define PROC_GNB_MODULES_GNBINITKM_PCIEENVINITKM_FILECODE (0xA0D7) -#define PROC_GNB_MODULES_GNBINITKM_PCIELIBKM_FILECODE (0xA0D8) -#define PROC_GNB_MODULES_GNBINITKM_PCIEMIDINITKM_FILECODE (0xA0D9) -#define PROC_GNB_MODULES_GNBINITKM_PCIEPOSTINITKM_FILECODE (0xA0DA) -#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE (0xA0DB) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE (0xA0DC) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE (0xA0DD) - -#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01) -#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02) - -// FCH -#define PROC_FCH_AZALIA_AZALIARESET_FILECODE (0xB001) -#define PROC_FCH_AZALIA_AZALIAENV_FILECODE (0xB002) -#define PROC_FCH_AZALIA_AZALIAMID_FILECODE (0xB003) -#define PROC_FCH_AZALIA_AZALIALATE_FILECODE (0xB004) -#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010) -#define PROC_FCH_COMMON_FCHLIB_FILECODE (0xB011) -#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012) -#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013) -#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014) -#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015) -#define PROC_FCH_COMMON_FCHPELIB_FILECODE (0xB016) -#define PROC_FCH_GEC_GECRESET_FILECODE (0xB020) -#define PROC_FCH_GEC_GECENV_FILECODE (0xB021) -#define PROC_FCH_GEC_GECMID_FILECODE (0xB022) -#define PROC_FCH_GEC_GECLATE_FILECODE (0xB023) -#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE (0xB024) -#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE (0xB025) -#define PROC_FCH_GEC_FAMILY_YUBA_YUBAGECSERVICE_FILECODE (0xB026) -#define PROC_FCH_GEC_FAMILY_YUBA_YUBAGECENVSERVICE_FILECODE (0xB027) -#define PROC_FCH_HWACPI_HWACPIRESET_FILECODE (0xB030) -#define PROC_FCH_HWACPI_HWACPIENV_FILECODE (0xB031) -#define PROC_FCH_HWACPI_HWACPIMID_FILECODE (0xB032) -#define PROC_FCH_HWACPI_HWACPILATE_FILECODE (0xB033) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE (0xB034) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE (0xB035) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE (0xB036) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE (0xB037) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPIENVSERVICE_FILECODE (0xB038) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPIMIDSERVICE_FILECODE (0xB039) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPILATESERVICE_FILECODE (0xB03A) -#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBASSSERVICE_FILECODE (0xB03B) -#define PROC_FCH_HWM_HWMRESET_FILECODE (0xB040) -#define PROC_FCH_HWM_HWMENV_FILECODE (0xB041) -#define PROC_FCH_HWM_HWMMID_FILECODE (0xB042) -#define PROC_FCH_HWM_HWMLATE_FILECODE (0xB043) -#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE (0xB044) -#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE (0xB045) -#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE (0xB046) -#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMENVSERVICE_FILECODE (0xB047) -#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMMIDSERVICE_FILECODE (0xB048) -#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMLATESERVICE_FILECODE (0xB049) -#define PROC_FCH_IDE_IDEENV_FILECODE (0xB050) -#define PROC_FCH_IDE_IDEMID_FILECODE (0xB051) -#define PROC_FCH_IDE_IDELATE_FILECODE (0xB052) -#define PROC_FCH_IMC_IMCENV_FILECODE (0xB060) -#define PROC_FCH_IMC_IMCMID_FILECODE (0xB061) -#define PROC_FCH_IMC_IMCLATE_FILECODE (0xB062) -#define PROC_FCH_IMC_IMCLIB_FILECODE (0xB063) -#define PROC_FCH_IMC_IMCRESET_FILECODE (0xB064) -#define PROC_FCH_IMC_FCHECENV_FILECODE (0xB065) -#define PROC_FCH_IMC_FCHECMID_FILECODE (0xB066) -#define PROC_FCH_IMC_FCHECLATE_FILECODE (0xB067) -#define PROC_FCH_IMC_FCHECRESET_FILECODE (0xB068) -#define PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE (0xB069) -#define PROC_FCH_IMC_FAMILY_YUBA_YUBAIMCSERVICE_FILECODE (0xB06A) -#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE (0xB070) -#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE (0xB071) -#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE (0xB072) -#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE (0xB073) -#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE (0xB074) -#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE (0xB075) -#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE (0xB076) -#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE (0xB077) -#define PROC_FCH_IR_IRENV_FILECODE (0xB080) -#define PROC_FCH_IR_IRMID_FILECODE (0xB081) -#define PROC_FCH_IR_IRLATE_FILECODE (0xB082) -#define PROC_FCH_PCIB_PCIBRESET_FILECODE (0xB090) -#define PROC_FCH_PCIB_PCIBENV_FILECODE (0xB091) -#define PROC_FCH_PCIB_PCIBMID_FILECODE (0xB092) -#define PROC_FCH_PCIB_PCIBLATE_FILECODE (0xB093) -#define PROC_FCH_PCIE_ABRESET_FILECODE (0xB0A0) -#define PROC_FCH_PCIE_ABENV_FILECODE (0xB0A1) -#define PROC_FCH_PCIE_ABMID_FILECODE (0xB0A2) -#define PROC_FCH_PCIE_ABLATE_FILECODE (0xB0A3) -#define PROC_FCH_PCIE_GPPHP_FILECODE (0xB0A4) -#define PROC_FCH_PCIE_GPPLIB_FILECODE (0xB0A5) -#define PROC_FCH_PCIE_GPPRESET_FILECODE (0xB0A6) -#define PROC_FCH_PCIE_GPPENV_FILECODE (0xB0A7) -#define PROC_FCH_PCIE_GPPMID_FILECODE (0xB0A8) -#define PROC_FCH_PCIE_GPPLATE_FILECODE (0xB0A9) -#define PROC_FCH_PCIE_PCIERESET_FILECODE (0xB0AA) -#define PROC_FCH_PCIE_PCIEENV_FILECODE (0xB0AB) -#define PROC_FCH_PCIE_PCIEMID_FILECODE (0xB0AC) -#define PROC_FCH_PCIE_PCIELATE_FILECODE (0xB0AD) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE (0xB0AE) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE (0xB0AF) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE (0xB0B0) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE (0xB0B1) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE (0xB0B2) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE (0xB0B3) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE (0xB0B4) -#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABRESETSERVICE_FILECODE (0xB0B5) -#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABENVSERVICE_FILECODE (0xB0B6) -#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABSERVICE_FILECODE (0xB0B7) -#define PROC_FCH_SATA_AHCIENV_FILECODE (0xB0C0) -#define PROC_FCH_SATA_AHCIMID_FILECODE (0xB0C1) -#define PROC_FCH_SATA_AHCILATE_FILECODE (0xB0C2) -#define PROC_FCH_SATA_AHCILIB_FILECODE (0xB0C3) -#define PROC_FCH_SATA_IDE2AHCIENV_FILECODE (0xB0C4) -#define PROC_FCH_SATA_IDE2AHCIMID_FILECODE (0xB0C5) -#define PROC_FCH_SATA_IDE2AHCILATE_FILECODE (0xB0C6) -#define PROC_FCH_SATA_IDE2AHCILIB_FILECODE (0xB0C7) -#define PROC_FCH_SATA_RAIDENV_FILECODE (0xB0C8) -#define PROC_FCH_SATA_RAIDMID_FILECODE (0xB0C9) -#define PROC_FCH_SATA_RAIDLATE_FILECODE (0xB0CA) -#define PROC_FCH_SATA_RAIDLIB_FILECODE (0xB0CB) -#define PROC_FCH_SATA_SATAENV_FILECODE (0xB0CC) -#define PROC_FCH_SATA_SATAENVLIB_FILECODE (0xB0CD) -#define PROC_FCH_SATA_SATAIDEENV_FILECODE (0xB0CE) -#define PROC_FCH_SATA_SATAIDEMID_FILECODE (0xB0CF) -#define PROC_FCH_SATA_SATAIDELATE_FILECODE (0xB0D0) -#define PROC_FCH_SATA_SATAIDELIB_FILECODE (0xB0D1) -#define PROC_FCH_SATA_SATAMID_FILECODE (0xB0D2) -#define PROC_FCH_SATA_SATALATE_FILECODE (0xB0D3) -#define PROC_FCH_SATA_SATALIB_FILECODE (0xB0D4) -#define PROC_FCH_SATA_SATARESET_FILECODE (0xB0D5) -#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE (0xB0D6) -#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE (0xB0D7) -#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE (0xB0D8) -#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATARESETSERVICE_FILECODE (0xB0D9) -#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATAENVSERVICE_FILECODE (0xB0DA) -#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATASERVICE_FILECODE (0xB0DB) -#define PROC_FCH_SD_SDENV_FILECODE (0xB0E0) -#define PROC_FCH_SD_SDMID_FILECODE (0xB0E1) -#define PROC_FCH_SD_SDLATE_FILECODE (0xB0E2) -#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDSERVICE_FILECODE (0xB0E3) -#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDRESETSERVICE_FILECODE (0xB0E4) -#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDENVSERVICE_FILECODE (0xB0E5) -#define PROC_FCH_SD_FAMILY_YUBA_YUBASDSERVICE_FILECODE (0xB0E6) -#define PROC_FCH_SD_FAMILY_YUBA_YUBASDRESETSERVICE_FILECODE (0xB0E7) -#define PROC_FCH_SD_FAMILY_YUBA_YUBASDENVSERVICE_FILECODE (0xB0E8) -#define PROC_FCH_SPI_LPCRESET_FILECODE (0xB0F0) -#define PROC_FCH_SPI_LPCENV_FILECODE (0xB0F1) -#define PROC_FCH_SPI_LPCMID_FILECODE (0xB0F2) -#define PROC_FCH_SPI_LPCLATE_FILECODE (0xB0F3) -#define PROC_FCH_SPI_SPIRESET_FILECODE (0xB0F4) -#define PROC_FCH_SPI_SPIENV_FILECODE (0xB0F5) -#define PROC_FCH_SPI_SPIMID_FILECODE (0xB0F6) -#define PROC_FCH_SPI_SPILATE_FILECODE (0xB0F7) -#define PROC_FCH_USB_EHCIRESET_FILECODE (0xB100) -#define PROC_FCH_USB_EHCIENV_FILECODE (0xB101) -#define PROC_FCH_USB_EHCIMID_FILECODE (0xB102) -#define PROC_FCH_USB_EHCILATE_FILECODE (0xB103) -#define PROC_FCH_USB_OHCIRESET_FILECODE (0xB104) -#define PROC_FCH_USB_OHCIENV_FILECODE (0xB105) -#define PROC_FCH_USB_OHCIMID_FILECODE (0xB106) -#define PROC_FCH_USB_OHCILATE_FILECODE (0xB107) -#define PROC_FCH_USB_USBRESET_FILECODE (0xB108) -#define PROC_FCH_USB_USBENV_FILECODE (0xB109) -#define PROC_FCH_USB_USBMID_FILECODE (0xB10A) -#define PROC_FCH_USB_USBLATE_FILECODE (0xB10B) -#define PROC_FCH_USB_XHCIRESET_FILECODE (0xB10C) -#define PROC_FCH_USB_XHCIENV_FILECODE (0xB10D) -#define PROC_FCH_USB_XHCIMID_FILECODE (0xB10E) -#define PROC_FCH_USB_XHCILATE_FILECODE (0xB10F) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE (0xB110) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE (0xB111) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE (0xB112) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE (0xB113) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE (0xB114) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE (0xB115) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE (0xB116) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE (0xB117) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE (0xB118) -#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE (0xB119) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCIENVSERVICE_FILECODE (0xB11A) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCIMIDSERVICE_FILECODE (0xB11B) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCILATESERVICE_FILECODE (0xB11C) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCIENVSERVICE_FILECODE (0xB11D) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCIMIDSERVICE_FILECODE (0xB11E) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCILATESERVICE_FILECODE (0xB11F) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIRESETSERVICE_FILECODE (0xB120) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIENVSERVICE_FILECODE (0xB121) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIMIDSERVICE_FILECODE (0xB122) -#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCILATESERVICE_FILECODE (0xB123) -#define PROC_FCH_USB_XHCIRECOVERY_FILECODE (0xB124) -#define PROC_FCH_PCIE_GPPPORTINIT_FILECODE (0xB125) - -#define UEFI_DXE_FCHDXE_FCHDXE_FILECODE (0xB200) -#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE (0xB220) -#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB221) -#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB222) -#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB230) -#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB240) -#define UEFI_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB250) -#define UEFI_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB251) -#define UEFI_DXE_FCHDXELIB_FCHDXELIB_FILECODE (0xB252) -#define UEFI_PEI_FCHPEI_FCHPEI_FILECODE (0xB260) -#define UEFI_PEI_FCHPEI_FCHRESET_FILECODE (0xB261) -#define UEFI_PEI_FCHPEI_FCHSTALL_FILECODE (0xB262) -#define UEFI_PEI_FCHPEI_LIBAMDPEI_FILECODE (0xB263) -#define UEFI_PEI_SMBUS_SMBUS_FILECODE (0xB270) -#define UEFI_SMM_FCHSMM_FCHSMM_FILECODE (0xB280) -#define UEFI_SMM_FCHSMM_GPESMI_FILECODE (0xB282) -#define UEFI_SMM_FCHSMM_IOTRAPSMI_FILECODE (0xB283) -#define UEFI_SMM_FCHSMM_MISCSMI_FILECODE (0xB284) -#define UEFI_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE (0xB285) -#define UEFI_SMM_FCHSMM_POWERBUTTONSMI_FILECODE (0xB286) -#define UEFI_SMM_FCHSMM_SWSMI_FILECODE (0xB287) -#define UEFI_SMM_FCHSMM_SXSMI_FILECODE (0xB288) -#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB2A0) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE (0xB290) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE (0xB292) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE (0xB293) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE (0xB294) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB295) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE (0xB296) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE (0xB297) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE (0xB298) -#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE (0xB299) - -#define LIB_AMDLIB_FILECODE (0xC001) - -#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010) -#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011) -#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012) - -#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120) - -#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140) -#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141) -#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142) -#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE (0xC162) - -#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020) -#define PROC_COMMON_AMDINITENV_FILECODE (0xC021) -#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022) -#define PROC_COMMON_AMDINITMID_FILECODE (0xC023) -#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024) -#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025) -#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026) -#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027) -#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028) -#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029) -#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A) - -#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0) -#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0) -#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0) -#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8) -#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9) - -#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401) -#define PROC_CPU_CPUBRANDID_FILECODE (0xC402) -#define PROC_CPU_TABLE_FILECODE (0xC403) -#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405) -#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406) -#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407) -#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408) -#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC409) -#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A) -#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B) -#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C) -#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D) -#define PROC_CPU_CPUBIST_FILECODE (0xC40E) - -#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420) -#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430) -#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431) -#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432) -#define PROC_CPU_S3_FILECODE (0xC460) - -// Family 10h -#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE (0xC801) -#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE (0xC802) -#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE (0xC803) -#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE (0xC804) -#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE (0xC805) -#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE (0xC806) -#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE (0xC807) -#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE (0xC808) -#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE (0xC809) -#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE (0xC80A) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE (0xC80B) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE (0xC80C) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE (0xC80D) -#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE (0xC80E) -#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE (0xC80F) -#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE (0xC810) -#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE (0xC811) -#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE (0xC812) -#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE (0xC813) -#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE (0xC820) -#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE (0xC821) -#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE (0xC822) -#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE (0xC823) -#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE (0xC824) -#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE (0xC825) -#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE (0xC826) -#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE (0xC827) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE (0xC830) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE (0xC831) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE (0xC832) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE (0xC833) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE (0xC834) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE (0xC835) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE (0xC836) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE (0xC837) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE (0xC838) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE (0xC839) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE (0xC83A) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE (0xC83B) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE (0xC83C) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE (0xC83D) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE (0xC83E) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE (0xC83F) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE (0xC840) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE (0xC841) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE (0xC842) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE (0xC843) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE (0xC844) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE (0xC845) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE (0xC846) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE (0xC847) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE (0xC848) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE (0xC849) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE (0xC850) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE (0xC851) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDL3FEATURES_FILECODE (0xC852) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE (0xC853) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE (0xC854) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE (0xC855) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE (0xC856) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE (0xC857) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE (0xC858) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE (0xC859) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE (0xC860) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE (0xC861) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE (0xC862) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE (0xC863) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE (0xC864) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE (0xC865) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE (0xC866) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE (0xC867) - -// Family 12h -#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE (0xC901) -#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE (0xC902) -#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE (0xC903) -#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE (0xC904) -#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE (0xC905) -#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE (0xC906) -#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE (0xC907) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE (0xC908) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE (0xC909) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE (0xC90A) -#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE (0xC90B) -#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE (0xC90C) -#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE (0xC90D) -#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE (0xC90E) -#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE (0xC90F) -#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE (0xC910) -#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE (0xC911) -#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE (0xC921) -#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE (0xC922) -#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE (0xC923) -#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE (0xC924) -#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE (0xC925) - -// Family 14h -#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE (0xCA01) -#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE (0xCA02) -#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE (0xCA03) -#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE (0xCA04) -#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE (0xCA05) -#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE (0xCA06) -#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE (0xCA07) -#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE (0xCA08) -#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0xCA09) -#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE (0xCA0A) -#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA0B) - -#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERPLANE_FILECODE (0xCA21) -#define PROC_CPU_FAMILY_0X14_ON_F14ONC6STATE_FILECODE (0xCA22) -#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA23) -#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA24) -#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA25) -#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE (0xCA26) -#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE (0xCA27) -#define PROC_CPU_FAMILY_0X14_ON_F14ONMSRTABLES_FILECODE (0xCA28) -#define PROC_CPU_FAMILY_0X14_ON_F14ONUTILITIES_FILECODE (0xCA29) -#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERMGMTSYSTEMTABLES_FILECODE (0xCA2A) -#define PROC_CPU_FAMILY_0X14_ON_F14ONLOWPOWERINIT_FILECODE (0xCA2B) -#define PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE (0xCA2C) -#define PROC_CPU_FAMILY_0X14_ON_F14ONSOFTWARETHERMAL_FILECODE (0xCA2D) -#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERCHECK_FILECODE (0xCA2E) - -#define PROC_CPU_FAMILY_0X14_KR_F14KREQUIVALENCETABLE_FILECODE (0xCA41) -#define PROC_CPU_FAMILY_0X14_KR_F14KRINITEARLYTABLE_FILECODE (0xCA42) -#define PROC_CPU_FAMILY_0X14_KR_F14KRLOGICALIDTABLES_FILECODE (0xCA43) -#define PROC_CPU_FAMILY_0X14_KR_F14KRMICROCODEPATCHTABLES_FILECODE (0xCA44) -#define PROC_CPU_FAMILY_0X14_KR_F14KRCPB_FILECODE (0xCA45) -#define PROC_CPU_FAMILY_0X14_KR_F14KRC6STATE_FILECODE (0xCA46) -#define PROC_CPU_FAMILY_0X14_KR_F14KRUTILITIES_FILECODE (0xCA47) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERPLANE_FILECODE (0xCA48) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERMGMTSYSTEMTABLES_FILECODE (0xCA49) -#define PROC_CPU_FAMILY_0X14_KR_F14KREARLYNBPSTATEINIT_FILECODE (0xCA4A) -#define PROC_CPU_FAMILY_0X14_KR_F14KRMSRTABLES_FILECODE (0xCA4B) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPCITABLES_FILECODE (0xCA4C) -#define PROC_CPU_FAMILY_0X14_KR_F14KRSOFTWARETHERMAL_FILECODE (0xCA4D) -#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERCHECK_FILECODE (0xCA4E) - -// Family 15h -#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01) -#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02) -#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03) -#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB04) -#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE (0xCB05) -#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE (0xCB06) -#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE (0xCB07) -#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB08) -#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB09) -#define PROC_CPU_FAMILY_0X15_F15PSTATEHPCMODE_FILECODE (0xCB0A) -#define PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE (0xCB0B) - -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCOREAFTERRESET_FILECODE (0xCB20) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORDMI_FILECODE (0xCB21) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORNBAFTERRESET_FILECODE (0xCB22) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORPSTATE_FILECODE (0xCB23) -#define PROC_CPU_FAMILY_0X15_OR_F15ORL3FEATURES_FILECODE (0xCB24) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE (0xCB25) -#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE (0xCB26) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE (0xCB27) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE (0xCB28) -#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE (0xCB29) -#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE (0xCB2A) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE (0xCB2B) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERMGMTSYSTEMTABLES_FILECODE (0xCB2C) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERPLANE_FILECODE (0xCB2D) -#define PROC_CPU_FAMILY_0X15_OR_F15ORUTILITIES_FILECODE (0xCB2E) -#define PROC_CPU_FAMILY_0X15_OR_F15ORWORKAROUNDSTABLE_FILECODE (0xCB2F) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPMNBCOFVIDINIT_FILECODE (0xCB30) -#define PROC_CPU_FAMILY_0X15_OR_F15ORLOWPWRPSTATE_FILECODE (0xCB31) -#define PROC_CPU_FAMILY_0X15_OR_F15ORSINGLELINKPCITABLES_FILECODE (0xCB32) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMULTILINKPCITABLES_FILECODE (0xCB33) -#define PROC_CPU_FAMILY_0X15_OR_F15ORC6STATE_FILECODE (0xCB34) -#define PROC_CPU_FAMILY_0X15_OR_F15OREARLYSAMPLES_FILECODE (0xCB35) -#define PROC_CPU_FAMILY_0X15_OR_F15ORCPB_FILECODE (0xCB36) -#define PROC_CPU_FAMILY_0X15_OR_F15ORIOCSTATE_FILECODE (0xCB37) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCACHEFLUSHONHALT_FILECODE (0xCB38) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORFEATURELEVELING_FILECODE (0xCB39) -#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORSOFTWARETHERMAL_FILECODE (0xCB3A) -#define PROC_CPU_FAMILY_0X15_OR_F15ORINITEARLYTABLE_FILECODE (0xCB3B) - -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE (0xCB50) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNDMI_FILECODE (0xCB51) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE (0xCB52) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSTATE_FILECODE (0xCB53) -#define PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE (0xCB54) -#define PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE (0xCB55) -#define PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE (0xCB56) -#define PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE (0xCB57) -#define PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE (0xCB58) -#define PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE (0xCB59) -#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE (0xCB5A) -#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE (0xCB5B) -#define PROC_CPU_FAMILY_0X15_TN_F15TNUTILITIES_FILECODE (0xCB5C) -#define PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE (0xCB5D) -#define PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE (0xCB5E) -#define PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE (0xCB5F) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE (0xCB60) -#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNSOFTWARETHERMAL_FILECODE (0xCB61) -#define PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE (0xCB62) -#define PROC_CPU_FAMILY_0X15_TN_F15TNEARLYSAMPLES_FILECODE (0xCB63) - -#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMCOREAFTERRESET_FILECODE (0xCB80) -#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMDMI_FILECODE (0xCB81) -#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMNBAFTERRESET_FILECODE (0xCB82) -#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMPSTATE_FILECODE (0xCB83) -#define PROC_CPU_FAMILY_0X15_KM_F15KML3FEATURES_FILECODE (0xCB84) -#define PROC_CPU_FAMILY_0X15_KM_F15KMMSGBASEDC1E_FILECODE (0xCB85) -#define PROC_CPU_FAMILY_0X15_KM_F15KMLOGICALIDTABLES_FILECODE (0xCB86) -#define PROC_CPU_FAMILY_0X15_KM_F15KMMICROCODEPATCHTABLES_FILECODE (0xCB87) -#define PROC_CPU_FAMILY_0X15_KM_F15KMMSRTABLES_FILECODE (0xCB88) -#define PROC_CPU_FAMILY_0X15_KM_F15KMSHAREDMSRTABLE_FILECODE (0xCB89) -#define PROC_CPU_FAMILY_0X15_KM_F15KMEQUIVALENCETABLE_FILECODE (0xCB8A) -#define PROC_CPU_FAMILY_0X15_KM_F15KMPCITABLES_FILECODE (0xCB8B) -#define PROC_CPU_FAMILY_0X15_KM_F15KMPOWERMGMTSYSTEMTABLES_FILECODE (0xCB8C) -#define PROC_CPU_FAMILY_0X15_KM_F15KMPOWERPLANE_FILECODE (0xCB8D) -#define PROC_CPU_FAMILY_0X15_KM_F15KMUTILITIES_FILECODE (0xCB8E) -#define PROC_CPU_FAMILY_0X15_KM_F15KMWORKAROUNDSTABLE_FILECODE (0xCB8F) -#define PROC_CPU_FAMILY_0X15_KM_F15KMPMNBCOFVIDINIT_FILECODE (0xCB90) -#define PROC_CPU_FAMILY_0X15_KM_F15KMLOWPWRPSTATE_FILECODE (0xCB91) -#define PROC_CPU_FAMILY_0X15_KM_F15KMSINGLELINKPCITABLES_FILECODE (0xCB92) -#define PROC_CPU_FAMILY_0X15_KM_F15KMMULTILINKPCITABLES_FILECODE (0xCB93) -#define PROC_CPU_FAMILY_0X15_KM_F15KMC6STATE_FILECODE (0xCB94) -#define PROC_CPU_FAMILY_0X15_KM_F15KMCPB_FILECODE (0xCB95) -#define PROC_CPU_FAMILY_0X15_KM_F15KMIOCSTATE_FILECODE (0xCB96) -#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMCACHEFLUSHONHALT_FILECODE (0xCB97) -#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMFEATURELEVELING_FILECODE (0xCB98) -#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMSOFTWARETHERMAL_FILECODE (0xCB99) -#define PROC_CPU_FAMILY_0X15_KM_F15KMINITEARLYTABLE_FILECODE (0xCB9A) - -#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01) -#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02) -#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10) -#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE (0xDC20) -#define PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE (0xDC30) -#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41) -#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42) -#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43) -#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50) -#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60) -#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70) -#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE (0xDC80) -#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE (0xDC81) -#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82) -#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83) -#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE (0xDC84) -#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85) -#define PROC_CPU_FEATURE_CPUPSTATEHPCMODE_FILECODE (0xDC86) -#define PROC_CPU_FEATURE_CPUAPM_FILECODE (0xDC87) -#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90) -#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE (0xDCA0) -#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0) -#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE (0xDCC0) - -#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01) - -#define PROC_HT_FEATURES_HTFEATSETS_FILECODE (0xE001) -#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE (0xE002) -#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE (0xE003) -#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE (0xE004) -#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE (0xE005) -#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE (0xE006) -#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE (0xE007) -#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE (0xE008) -#define PROC_HT_FEATURES_HTIDS_FILECODE (0xE009) -#define PROC_HT_HTFEAT_FILECODE (0xE021) -#define PROC_HT_HTINTERFACE_FILECODE (0xE022) -#define PROC_HT_HTINTERFACECOHERENT_FILECODE (0xE023) -#define PROC_HT_HTINTERFACEGENERAL_FILECODE (0xE024) -#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE (0xE025) -#define PROC_HT_HTMAIN_FILECODE (0xE026) -#define PROC_HT_HTNOTIFY_FILECODE (0xE027) -#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE (0xE028) -#define PROC_HT_HTNB_FILECODE (0xE081) -#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE (0xE082) -#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE (0xE083) -#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE (0xE084) -#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE (0xE085) -#define PROC_HT_FAM10_HTNBFAM10_FILECODE (0xE0C1) -#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE (0xE0C2) -#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE (0xE0C3) -#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE (0xE0C4) -#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE (0xE0C5) -#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE (0xE0C6) -#define PROC_HT_FAM12_HTNBFAM12_FILECODE (0xE101) -#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE (0xE102) -#define PROC_HT_FAM14_HTNBFAM14_FILECODE (0xE141) -#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE (0xE142) -#define PROC_HT_FAM15_HTNBFAM15_FILECODE (0xE181) -#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE (0xE182) -#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE (0xE183) -#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE (0xE184) -#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE (0xE185) -#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE (0xE186) -#define PROC_HT_FAM15MOD1X_HTNBFAM15MOD1X_FILECODE (0xE187) -#define PROC_HT_FAM15MOD1X_HTNBUTILITIESFAM15MOD1X_FILECODE (0xE188) -#define PROC_HT_FAM14MOD1X_HTNBFAM14MOD1X_FILECODE (0xE189) -#define PROC_HT_FAM14MOD1X_HTNBUTILITIESFAM14MOD1X_FILECODE (0xE18A) -#define PROC_HT_FAM15MOD2X_HTNBFAM15MOD2X_FILECODE (0xE191) -#define PROC_HT_FAM15MOD2X_HTNBCOHERENTFAM15MOD2X_FILECODE (0xE192) -#define PROC_HT_FAM15MOD2X_HTNBNONCOHERENTFAM15MOD2X_FILECODE (0xE193) -#define PROC_HT_FAM15MOD2X_HTNBOPTIMIZATIONFAM15MOD2X_FILECODE (0xE194) -#define PROC_HT_FAM15MOD2X_HTNBSYSTEMFAM15MOD2X_FILECODE (0xE195) -#define PROC_HT_FAM15MOD2X_HTNBUTILITIESFAM15MOD2X_FILECODE (0xE196) - -#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE (0xE302) -#define PROC_RECOVERY_HT_HTINITRESET_FILECODE (0xE301) - -#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801) -#define PROC_IDS_LIBRARY_IDSLIB_FILECODE (0xE802) -#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803) -#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804) -#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE (0xE805) -#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE (0xE806) -#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE (0xE807) -#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE (0xE808) -#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE (0xE809) -#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE (0xE80A) -#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE (0xE80B) -#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C) -#define PROC_IDS_FAMILY_0X14_KR_IDSF14KRALLSERVICE_FILECODE (0xE80D) -#define PROC_IDS_FAMILY_0X15_OR_IDSF15ORALLSERVICE_FILECODE (0xE80E) -#define PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE (0xE80F) -#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE (0xE810) - -#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E) -#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F) - -///0xE820 ~ 0xE840 is reserved for ids extend module - -#define PROC_MEM_ARDK_MA_FILECODE (0xF001) -#define PROC_MEM_ARDK_DR_MARDR2_FILECODE (0xF002) -#define PROC_MEM_ARDK_DR_MARDR3_FILECODE (0xF003) -#define PROC_MEM_ARDK_HY_MARHY3_FILECODE (0xF004) -#define PROC_MEM_ARDK_LN_MASLN3_FILECODE (0xF005) -#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE (0xF006) -#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE (0xF007) -#define PROC_MEM_ARDK_LN_MAULN3_FILECODE (0xF008) -#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE (0xF009) -#define PROC_MEM_ARDK_DA_MASDA2_FILECODE (0xF00A) -#define PROC_MEM_ARDK_DA_MASDA3_FILECODE (0xF00B) -#define PROC_MEM_ARDK_NI_MASNI3_FILECODE (0xF00C) -#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE (0xF00D) -#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE (0xF00E) -#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE (0xF00F) -#define PROC_MEM_ARDK_ON_MASON3_FILECODE (0xF010) -#define PROC_MEM_ARDK_ON_MAUON3_FILECODE (0xF011) -#define PROC_MEM_ARDK_PH_MASPH3_FILECODE (0xF012) -#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE (0xF013) -#define PROC_MEM_ARDK_OR_MAROR3_FILECODE (0xF014) -#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE (0xF017) -#define PROC_MEM_ARDK_RB_MASRB3_FILECODE (0xF018) -#define PROC_MEM_ARDK_RB_MAURB3_FILECODE (0xF019) - -#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081) -#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082) -#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083) -#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085) -#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086) -#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088) -#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089) -#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A) -#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B) -#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C) -#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D) -#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E) -#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F) -#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091) -#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092) -#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093) - -#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101) -#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102) -#define PROC_MEM_MAIN_MM_FILECODE (0xF103) -#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104) -#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105) -#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106) -#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE (0xF107) -#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE (0xF108) -#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE (0xF109) -#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE (0xF10A) -#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B) -#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C) -#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D) -#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E) -#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F) -#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110) -#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE (0xF111) -#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112) -#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113) -#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE (0xF114) -#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115) -#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116) -#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117) -#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118) -#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE (0xF119) -#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE (0xF11A) -#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B) -#define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE (0xF11C) -#define PROC_MEM_MAIN_KR_MMFLOWKR_FILECODE (0xF11D) - -#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213) -#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214) -#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216) -#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217) -#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218) -#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219) -#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A) -#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C) -#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D) -#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E) -#define PROC_MEM_NB_RB_MNRB_FILECODE (0XF220) -#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0XF221) -#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0XF222) -#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0XF223) -#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233) -#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235) -#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236) -#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237) -#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238) -#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239) -#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A) -#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B) -#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C) -#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D) -#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E) -#define PROC_MEM_NB_ON_MNON_FILECODE (0xF240) -#define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241) -#define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242) -#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE (0xF244) -#define PROC_MEM_NB_ON_MNMCTON_FILECODE (0xF245) -#define PROC_MEM_NB_ON_MNOTON_FILECODE (0xF246) -#define PROC_MEM_NB_ON_MNPHYON_FILECODE (0xF247) -#define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248) -#define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249) -#define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A) -#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252) -#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253) -#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254) -#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255) -#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256) -#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257) -#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258) -#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259) -#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A) -#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B) -#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260) -#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261) -#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263) -#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264) -#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265) -#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266) -#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267) -#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269) -#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A) -#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B) -#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C) -#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D) -#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E) -#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F) -#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270) -#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271) -#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272) -#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273) -#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274) -#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275) -#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286) -#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287) -#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0XF288) -#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0XF289) -#define PROC_MEM_NB_PH_MNPH_FILECODE (0XF28A) -#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0XF28B) -#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0XF28C) -#define PROC_MEM_NB_PH_MNMCTPH_FILECODE (0XF28D) -#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0XF290) -#define PROC_MEM_NB_OR_MNOR_FILECODE (0XF291) -#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0XF292) -#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0XF293) -#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0XF294) -#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0XF295) -#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0XF296) -#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0XF297) -#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0XF298) -#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0XF299) -#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0XF29A) -#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0XF29B) -#define PROC_MEM_NB_TN_MNTN_FILECODE (0XF29C) -#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0XF29D) -#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0XF29E) -#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0XF29F) -#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0XF2A0) -#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0XF2A1) -#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0XF2A2) -#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0XF2A3) -#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0XF2A4) -#define PROC_MEM_NB_KR_MNREGKR_FILECODE (0xF2A5) -#define PROC_MEM_NB_KR_MNDCTKR_FILECODE (0xF2A6) -#define PROC_MEM_NB_KR_MNIDENDIMMKR_FILECODE (0xF2A7) -#define PROC_MEM_NB_KR_MNMCTKR_FILECODE (0xF2A8) -#define PROC_MEM_NB_KR_MNOTKR_FILECODE (0xF2A9) -#define PROC_MEM_NB_KR_MNPHYKR_FILECODE (0xF2AA) -#define PROC_MEM_NB_KR_MNS3KR_FILECODE (0xF2AB) -#define PROC_MEM_NB_KR_MNFLOWKR_FILECODE (0xF2AC) -#define PROC_MEM_NB_KR_MNPROTOKR_FILECODE (0xF2AD) -#define PROC_MEM_NB_KR_MNKR_FILECODE (0xF2AE) -#define PROC_MEM_NB_KM_MNREGKM_FILECODE (0XF2AF) -#define PROC_MEM_NB_KM_MNKM_FILECODE (0XF2B0) -#define PROC_MEM_NB_KM_MNMCTKM_FILECODE (0XF2B1) -#define PROC_MEM_NB_KM_MNOTKM_FILECODE (0XF2B2) -#define PROC_MEM_NB_KM_MNDCTKM_FILECODE (0XF2B3) -#define PROC_MEM_NB_KM_MNPHYKM_FILECODE (0XF2B4) -#define PROC_MEM_NB_KM_MNS3KM_FILECODE (0XF2B5) -#define PROC_MEM_NB_KM_MNIDENDIMMKM_FILECODE (0XF2B6) -#define PROC_MEM_NB_KM_MNFLOWKM_FILECODE (0XF2B7) -#define PROC_MEM_NB_KM_MNPROTOKM_FILECODE (0XF2B8) - - -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402) -#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403) -#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404) -#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405) -#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406) -#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407) -#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408) -#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409) -#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A) -#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B) -#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C) -#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D) -#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E) -#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F) -#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410) -#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411) -#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412) -#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413) -#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414) -#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415) -#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0XF416) -#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0XF417) -#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0XF418) -#define PROC_MEM_PS_RB_MPURB3_FILECODE (0XF419) -#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0XF41A) -#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0XF41B) -#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0XF41C) -#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0XF41D) -#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0XF41E) -#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0XF41F) -#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0XF420) -#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0XF421) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_OR_MPOR3_FILECODE (0XF42C) -#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0XF42D) -#define PROC_MEM_PS_TN_MPTN3_FILECODE (0XF42E) -#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0XF42F) -#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0XF430) -#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0XF431) -#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0XF432) -#define PROC_MEM_PS_KR_MPKR3_FILECODE (0XF433) -#define PROC_MEM_PS_KR_MPUKR3_FILECODE (0XF434) -#define PROC_MEM_PS_KR_MPSKR3_FILECODE (0XF435) -#define PROC_MEM_PS_MPS___FILECODE (0XF436) -#define PROC_MEM_PS_KM_FM2_MPUKMFM2_FILECODE (0XF437) -#define PROC_MEM_PS_KM_FM2_MPSKMFM2_FILECODE (0XF438) -#define PROC_MEM_PS_KM_C2012_MPRKMC3_FILECODE (0XF439) -#define PROC_MEM_PS_KM_C2012_MPUKMC3_FILECODE (0XF43A) -#define PROC_MEM_PS_KM_C2012_MPLKMC3_FILECODE (0XF43B) -#define PROC_MEM_PS_KM_G2012_MPRKMG3_FILECODE (0XF43C) -#define PROC_MEM_PS_KM_G2012_MPUKMG3_FILECODE (0XF43D) -#define PROC_MEM_PS_KM_G2012_MPLKMG3_FILECODE (0XF43E) -#define PROC_MEM_PS_KM_MPKM3_FILECODE (0XF43F) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF440) - -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541) -#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543) -#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) - -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812) -#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813) -#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821) -#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822) -#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823) -#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825) -#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831) -#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832) -#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833) -#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842) -#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843) -#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845) -#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851) -#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852) -#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853) -#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861) -#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862) -#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863) -#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE (0xF871) -#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE (0xF881) -#define PROC_RECOVERY_MEM_NB_KR_MRNDCTKR_FILECODE (0xF891) -#define PROC_RECOVERY_MEM_NB_KR_MRNMCTKR_FILECODE (0xF892) -#define PROC_RECOVERY_MEM_NB_KR_MRNKR_FILECODE (0xF893) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0XF8CD) -#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0XF8CE) -#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0XF8CF) -#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0XF8D0) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0XF8F3) -#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0XF8F4) -#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0XF8F5) -#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0XF8F6) -#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0XF8F7) -#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0XF8F8) -#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0XF8F9) -#define PROC_RECOVERY_MEM_NB_KM_MRNDCTKM_FILECODE (0XF8FA) -#define PROC_RECOVERY_MEM_NB_KM_MRNKM_FILECODE (0XF8FB) -#define PROC_RECOVERY_MEM_NB_KM_MRNMCTKM_FILECODE (0XF8FC) -#define PROC_RECOVERY_MEM_NB_KM_MRNPROTOKM_FILECODE (0XF8FD) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FE) - -#endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h deleted file mode 100644 index aff8d7d4f1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h +++ /dev/null @@ -1,200 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * General Services - * - * Provides Services similar to the external General Services API, except - * suited to use within AGESA components. Socket, Core and PCI identification. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _GENERAL_SERVICES_H_ -#define _GENERAL_SERVICES_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -#define NUMBER_OF_EVENT_DATA_PARAMS 4 - -/** - * AMD Device id for MMIO check. - */ -#define AMD_DEV_VEN_ID 0x1022 -#define AMD_DEV_VEN_ID_ADDRESS 0 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * An AGESA Event Log entry. - */ -typedef struct { - AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS. - UINT32 EventInfo; ///< Uniquely identifies the event. - UINT32 DataParam1; ///< Event specific additional data - UINT32 DataParam2; ///< Event specific additional data - UINT32 DataParam3; ///< Event specific additional data - UINT32 DataParam4; ///< Event specific additional data -} AGESA_EVENT; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -/** - * Get a specified Core's APIC ID. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The Core's Socket. - * @param[in] Core The Core id. - * @param[out] ApicAddress The Core's APIC ID. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, APIC Id valid - * @retval FALSE The core is not present, APIC Id not valid. - */ -BOOLEAN -GetApicId ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Core, - OUT UINT8 *ApicAddress, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * Get Processor Module's PCI Config Space address. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The Core's Socket. - * @param[in] Module The Module in that Processor - * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, PCI Address valid - * @retval FALSE The core is not present, PCI Address not valid. - */ -BOOLEAN -GetPciAddress ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Module, - OUT PCI_ADDR *PciAddress, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * "Who am I" for the current running core. - * - * @param[in] StdHeader Header for library and services. - * @param[out] Socket The current Core's Socket - * @param[out] Module The current Core's Processor Module - * @param[out] Core The current Core's core id. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - */ -VOID -IdentifyCore ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT UINT32 *Socket, - OUT UINT32 *Module, - OUT UINT32 *Core, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * A boolean function determine executed CPU is BSP core. - */ -BOOLEAN -IsBsp ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - OUT AGESA_STATUS *AgesaStatus - ); - -/** - * This function logs AGESA events into the event log. - */ -VOID -PutEventLog ( - IN AGESA_STATUS EventClass, - IN UINT32 EventInfo, - IN UINT32 DataParam1, - IN UINT32 DataParam2, - IN UINT32 DataParam3, - IN UINT32 DataParam4, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function gets event logs from the circular buffer. - */ -AGESA_STATUS -GetEventLog ( - OUT AGESA_EVENT *EventRecord, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function gets event logs from the circular buffer without flushing the entry. - */ -BOOLEAN -PeekEventLog ( - OUT AGESA_EVENT *EventRecord, - IN UINT16 Index, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * This routine programs the registers necessary to get the PCI MMIO mechanism - * up and functioning. - */ -VOID -InitializePciMmio ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _GENERAL_SERVICES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f15/Include/GnbInterface.h deleted file mode 100644 index ca53656996..0000000000 --- a/src/vendorcode/amd/agesa/f15/Include/GnbInterface.h +++ /dev/null @@ -1,100 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB API definition. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _GNBINTERFACE_H_ -#define _GNBINTERFACE_H_ - -AGESA_STATUS -GnbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GnbInitAtEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ); - -AGESA_STATUS -GnbInitAtPost ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -VOID -GnbInitDataStructAtEnvDef ( - IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, - IN AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -GnbInitAtEnv ( - IN AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -GnbInitAtMid ( - IN OUT AMD_MID_PARAMS *MidParamsPtr - ); - -AGESA_STATUS -GnbInitAtLate ( - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ); - -AGESA_STATUS -GnbInitAtPostAfterDram ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -AGESA_STATUS -AmdGnbRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GnbInitAtEarlier ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ); -#endif diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h deleted file mode 100644 index e4f89d859a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h +++ /dev/null @@ -1,301 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GnbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GnbInitAtEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ); - -VOID -GnbInitDataStructAtEnvDef ( - IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, - IN AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -GnbInitAtEnv ( - IN AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -GnbInitAtPost ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -AGESA_STATUS -GnbInitAtMid ( - IN OUT AMD_MID_PARAMS *MidParamsPtr - ); - -AGESA_STATUS -GnbInitAtLate ( - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ); - -AGESA_STATUS -AmdGnbRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GnbInitAtPostAfterDram ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -AGESA_STATUS -GnbInitAtEarlier ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Reset Stub - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Early Stub - * - * - * - * @param[in,out] EarlyParamsPtr Pointer to early configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Default constructor of GNB configuration at Env - * - * - * - * @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params. - * @param[in] EnvParamsPtr Pointer to env configuration params. - */ -VOID -GnbInitDataStructAtEnvDef ( - IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Env - * - * - * - * @param[in] EnvParamsPtr Pointer to env configuration params. -* @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtEnv ( - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post - * - * - * - * @param[in,out] PostParamsPtr Pointer to Post configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtPost ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Mid post - * - * - * - * @param[in,out] MidParamsPtr Pointer to mid configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtMid ( - IN OUT AMD_MID_PARAMS *MidParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Late post - * - * - * - * @param[in,out] LateParamsPtr Pointer to late configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtLate ( - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * AmdGnbRecovery - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Always succeeds - */ -AGESA_STATUS -AmdGnbRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post after DRAM init - * - * - * - * @param[in] PostParamsPtr Pointer to post configuration parameters - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtPostAfterDram ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Early Before CPU Stub - * - * - * - * @param[in,out] EarlyParamsPtr Pointer to early configuration params. - * @retval AGESA_SUCCESS Always succeeds - */ - -AGESA_STATUS -GnbInitAtEarlier ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ) -{ - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbPage.h b/src/vendorcode/amd/agesa/f15/Include/GnbPage.h deleted file mode 100644 index b571128a79..0000000000 --- a/src/vendorcode/amd/agesa/f15/Include/GnbPage.h +++ /dev/null @@ -1,1972 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for GNB Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/** - * @page gnbmain GNB Component Documentation - * - * Additional documentation for the GNB component consists of - * - * - Maintenance Guides: - * - @subpage F12PcieLaneDescription "Family 0x12 PCIe/DDI Lane description table" - * - @subpage F14ONPcieLaneDescription "Family 0x14(ON) PCIe/DDI Lane description table" - * - @subpage F12LaneConfigurations "Family 0x12 PCIe port/DDI link configurations" - * - @subpage F14ONLaneConfigurations "Family 0x14(ON) PCIe port/DDI link configurations" - * - @subpage F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description" - * - add here >>> - * - Design Guides: - * - add here >>> - * - */ - - -/** - * @page F12PcieLaneDescription Family 0x12 PCIe/DDI Lanes - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Lane IDLane groupPin
0 SB P_SB_RX[P/N]/TX[P/N][0]
1 SB P_SB_RX[P/N]/TX[P/N][1]
2 SB P_SB_RX[P/N]/TX[P/N][2]
3 SB P_SB_RX[P/N]/TX[P/N][3]
4 GPPP_GPP_RX[P/N]/TX[P/N][0]
5 GPPP_GPP_RX[P/N]/TX[P/N][1]
6 GPPP_GPP_RX[P/N]/TX[P/N][2]
7 GPPP_GPP_RX[P/N]/TX[P/N][3]
8 GFXP_GFX_RX[P/N]/TX[P/N][0]
9 GFXP_GFX_RX[P/N]/TX[P/N][1]
10GFXP_GFX_RX[P/N]/TX[P/N][2]
11GFXP_GFX_RX[P/N]/TX[P/N][3]
12GFXP_GFX_RX[P/N]/TX[P/N][4]
13GFXP_GFX_RX[P/N]/TX[P/N][5]
14GFXP_GFX_RX[P/N]/TX[P/N][6]
15GFXP_GFX_RX[P/N]/TX[P/N][7]
16GFXP_GFX_RX[P/N]/TX[P/N][8]
17GFXP_GFX_RX[P/N]/TX[P/N][9]
18GFXP_GFX_RX[P/N]/TX[P/N][10]
19GFXP_GFX_RX[P/N]/TX[P/N][11]
20GFXP_GFX_RX[P/N]/TX[P/N][12]
21GFXP_GFX_RX[P/N]/TX[P/N][13]
22GFXP_GFX_RX[P/N]/TX[P/N][14]
23GFXP_GFX_RX[P/N]/TX[P/N][15]
24DDIDP1_TXP/N[0]
25DDIDP1_TXP/N[1]
26DDIDP1_TXP/N[2]
27DDIDP1_TXP/N[3]
28DDIDP0_TXP/N[0]
29DDIDP0_TXP/N[1]
30DDIDP0_TXP/N[2]
31DDIDP0_TXP/N[3]
- * - */ - - -/** - * @page F14ONPcieLaneDescription Family 0x14(ON) PCIe/DDI Lanes - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Lane IDLane groupPin
0 SB P_SB_RX[P/N]/TX[P/N][0]
1 SB P_SB_RX[P/N]/TX[P/N][1]
2 SB P_SB_RX[P/N]/TX[P/N][2]
3 SB P_SB_RX[P/N]/TX[P/N][3]
4 GPPP_GPP_RX[P/N]/TX[P/N][0]
5 GPPP_GPP_RX[P/N]/TX[P/N][1]
6 GPPP_GPP_RX[P/N]/TX[P/N][2]
7 GPPP_GPP_RX[P/N]/TX[P/N][3]
8DDIDP0_TXP/N[0]
9DDIDP0_TXP/N[1]
10DDIDP0_TXP/N[2]
11DDIDP0_TXP/N[3]
12DDIDP1_TXP/N[0]
13DDIDP1_TXP/N[1]
14DDIDP1_TXP/N[2]
15DDIDP1_TXP/N[3]
- * - */ - - -/** - * @page F12DualLinkDviDescription Family 0x12 Dual Link DVI connector description - * Examples of various Dual Link DVI descriptors. - * @code - * // Dual Link DVI on dedicated display lanes. DP1_TXP/N[0]..DP1_TXP/N[3] - master, DP0_TXP/N[0]..DP0_TXP/N[3] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) - * } - * } - * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) - * } - * } - * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave. - * PCIe_PORT_DESCRIPTOR DdiList [] = { - * { - * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags - * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) - * } - * } - * @endcode - */ - -/** - * @page F12LaneConfigurations Family 0x12 PCIe port/DDI link configurations - *
- * - *

PCIe port - * configurations for lane 8 through 23.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

PCIe Port Device Number

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A*

- * 		- *

2

- *

 

- * 		- *

8(23)

- * 		- *

23(8)

- *
- *

8(15)

- * 		- *

15(8)

- *
- *

8(11)

- * 		- *

11(8)

- *
- *

8(9)

- * 		- *

9(8)

- *
- *

10(11)

- * 		- *

11(10)

- *
- *

12(15)

- * 		- *

15(12)

- *
- *

12(13)

- * 		- *

13(12)

- *
- *

14(15)

- * 		- *

15(14)

- *
- *

16(23)

- * 		- *

23(16)

- *
- *

16(19)

- * 		- *

19(16)

- *
- *

16(17)

- * 		- *

17(16)

- *
- *

18(19)

- * 		- *

19(18)

- *
- *

20(23)

- * 		- *

23(20)

- *
- *

20(21)

- * 		- *

21(20)

- *
- *

22(23)

- * 		- *

23(22)

- *
- *

3

- *

 

- * 		- *

8(15)

- * 		- *

15(8)

- *
- *

8(11)

- * 		- *

11(8)

- *
- *

8(9)

- * 		- *

9(8)

- *
- *

10(11)

- * 		- *

11(10)

- *
- *

12(15)

- * 		- *

15(12)

- *
- *

12(13)

- * 		- *

13(12)

- *
- *

14(15)

- * 		- *

15(14)

- *
- *

16(23)

- * 		- *

23(16)

- *
- *

16(19)

- * 		- *

19(16)

- *
- *

16(17)

- * 		- *

17(16)

- *
- *

18(19)

- * 		- *

19(18)

- *
- *

20(23)

- * 		- *

23(20)

- *
- *

20(21)

- * 		- *

21(20)

- *
- *

22(23)

- * 		- *

23(22)

- *
- *

* Lanes selection for port 2/3 should not overlap in port configuration

- *
- * - *

 

- * - *

PCIe port - * configurations for lane 4 through 7.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

PCIe Port Device Number

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A

- * 		- *

4

- * 		- *

4(7)

- * 		- *

7(4)

- *
- *

4(5)

- * 		- *

5(4)

- *
- *

4

- * 		- *

4

- *
- *

Config B

- * 		- *

4

- * 		- *

4(5)

- * 		- *

5(4)

- *
- *

4

- * 		- *

4

- *
- *

5 or 6

- * 		- *

6(7)

- * 		- *

7(6)

- *
- *

6

- * 		- *

6

- *
- *

Config C

- * 		- *

4

- * 		- *

4(5)

- * 		- *

5(4)

- *
- *

4

- * 		- *

4

- *
- *

5 or 6

- * 		- *

6

- * 		- *

6

- *
- *

6 or 7

- * 		- *

7

- * 		- *

7

- *
- *

Config D

- * 		- *

4

- * 		- *

4

- * 		- *

4

- *
- *

5

- * 		- *

5

- * 		- *

5

- *
- *

6

- * 		- *

6

- * 		- *

6

- *
- *

7

- * 		- *

7

- * 		- *

7

- *
- * - *

 

- * - *

DDI link - * configurations for lanes 24 through 31.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

Connector type

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A

- * 		- *

Dual Link DVI-D

- * 		- *

24(31)

- * 		- *

31(24)

- *
- *

Config B

- * 		- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

24

- * 		- *

27

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

28

- * 		- *

31

- *
- * - *

 

- * - *

DDI link - * configurations for lanes 8 through 23.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

Connector type

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A

- * 		- *

Dual Link DVI-D

- * 		- *

8(15)

- * 		- *

15(8)

- *
- *

Dual Link DVI-D

- * 		- *

16(23)

- * 		- *

23(16)

- *
- *

Config B

- * 		- *

Dual Link DVI-D

- * 		- *

8(15)

- * 		- *

15(8)

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

16

- * 		- *

19

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

20

- * 		- *

23

- *
- *

Config C

- * 		- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

8

- * 		- *

11

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

12

- * 		- *

15

- *
- *

Dual Link DVI-D

- * 		- *

16(23)

- * 		- *

23(16)

- *
- *

Config D

- * 		- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

8

- * 		- *

11

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

12

- * 		- *

15

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

16

- * 		- *

19

- *
- *

HDMI

- *

Single Link DVI-D

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

20

- * 		- *

23

- *
- * - *

 

- *
- */ - -/** - * @page F14ONLaneConfigurations Family 0x14(ON) PCIe port/DDI link configurations - *
- *

PCIe port - * configurations for lane 4 through 7.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

PCIe Port Device Number

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A

- * 		- *

4

- * 		- *

4(7)

- * 		- *

7(4)

- *
- *

4(5)

- * 		- *

5(4)

- *
- *

4

- * 		- *

4

- *
- *

Config B

- * 		- *

4

- * 		- *

4(5)

- * 		- *

5(4)

- *
- *

4

- * 		- *

4

- *
- *

5 or 6

- * 		- *

6(7)

- * 		- *

7(6)

- *
- *

6

- * 		- *

6

- *
- *

Config C

- * 		- *

4

- * 		- *

4(5)

- * 		- *

5(4)

- *
- *

4

- * 		- *

4

- *
- *

5 or 6

- * 		- *

6

- * 		- *

6

- *
- *

6 or 7

- * 		- *

7

- * 		- *

7

- *
- *

Config D

- * 		- *

4

- * 		- *

4

- * 		- *

4

- *
- *

5

- * 		- *

5

- * 		- *

5

- *
- *

6

- * 		- *

6

- * 		- *

6

- *
- *

7

- * 		- *

7

- * 		- *

7

- *
- * - *

 

- * - *

CRT/DDI link - * configurations for lanes 8 through 19.

- * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
- *

Configuration

- * 		- *

Connector type

- * 		- *

Start Lane (Start Lane in reverse - * configuration)

- * 		- *

End Line (End lane in reverse - * configuration)

- *
- *

Config A

- * 		- *

HDMI

- *

Single Link DVI-D

- *

Single Link DVI-I*

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

8

- * 		- *

11

- *
- *

HDMI

- *

Single Link DVI-D

- *

Single Link DVI-I*

- *

DP

- *

eDP

- *

Travis DP-to-CRT

- *

Travis DP-to-LVDS

- *

Hudson2 DP-to-CRT

- * 		- *

12

- * 		- *

15

- *
- *

CRT*

- * 		- *

16

- * 		- *

19

- *
- *

* - Only one connector of this time can exist in configuration

- *
- * - *

 

- * - *

 

- * - *
- */ diff --git a/src/vendorcode/amd/agesa/f15/Include/Ids.h b/src/vendorcode/amd/agesa/f15/Include/Ids.h deleted file mode 100644 index e980688711..0000000000 --- a/src/vendorcode/amd/agesa/f15/Include/Ids.h +++ /dev/null @@ -1,1159 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD IDS Routines - * - * Contains AMD AGESA Integrated Debug Macros - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: IDS - * @e \$Revision: 55079 $ @e \$Date: 2011-06-16 03:48:27 -0600 (Thu, 16 Jun 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - /* Macros to aid debugging */ - /* These definitions expand to zero (0) bytes of code when disabled */ - -#ifndef _IDS_H_ -#define _IDS_H_ - -#undef FALSE -#undef TRUE -#define FALSE 0 -#define TRUE 1 -// Proto type for optionsids.h -typedef UINT32 IDS_STATUS; ///< Status of IDS function. -#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful. -#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed. - -#define IDS_STRINGIZE(a) #a ///< for define stringize macro -#ifndef IDS_DEADLOOP - #define IDS_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); } -#endif -/** - * IDS Option Hook Points - * - * These are the values to indicate hook point in AGESA for IDS Options. - * - */ -typedef enum { //vv- for debug reference only - IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY. - ///< IDS Object is initialized. - ///< Override CPU Core Leveling Mode. - ///< Set P-State in Post - IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY. - IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE. - ///< It will be used to control the following tables. - ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC) - ///< ACPI SRAT Table - ///< ACPI SLIT Table - ///< ACPI WHEA Table - ///< DMI Table - IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE. - IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID. - IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID. - IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST. - ///< Control Interleaving and DRAM memory hole - ///< Override the setting of ECC Control - ///< Override the setting of Online Spare Rank - IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST. - IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET. - IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET. - IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST. - IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save. - IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore - IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save - IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore - IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training - IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization - IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change - IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset - IDS_BEFORE_PCI_INIT, ///< 13 Override PCI or MSR Registers Before PCI Init - IDS_BEFORE_AP_EARLY_HALT, ///< 14 Option Hook Point before AP early halt - IDS_BEFORE_S3_RESUME, ///< 15 Option Hook Point before s3 resume - IDS_AFTER_S3_RESUME, ///< 16 Option Hook Point after s3 resume - IDS_BEFORE_PM_INIT, ///< 17 Option Hook Point Before Pm Init - - IDS_MT_BASE = 0x20, ///< 0x20 ~ 0x38 24 time points reserved for MTTime - - IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used - - // All the above timing point is used by BVM, their value should never be changed - IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control - IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP# - IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing - ///< Dram Controller, Drive Strength and DQS Timing - IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing - IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged - IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode - IDS_BURST_LENGTH32, ///< 46 override Burst Length32 - IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable - IDS_ECC, ///< 48 override ECC parameter - IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size - IDS_CPU_Early_Override, ///< 4a override CPU early parameter - IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt - IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave - IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery - IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times - IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit - IDS_HT_ASSIST, ///< 50 Override Probe Filter - IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result - IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down - IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement - IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature - IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure - IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support - IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory - IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service - IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake - IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config - IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration - IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep - IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config - IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings - IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature - IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control - IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around - IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register - IDS_REG_TABLE, ///< 63 Hook for add IDS register table to the loop - IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation - IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions - IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry - IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround - IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit - IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting - IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting - IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg - IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature - IDS_CST_CREATE, ///< 6d Hook for create _CST - IDS_CST_SIZE, ///< 6e Hook for get _CST size - IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO - IDS_STRETCH_FREQUENCY_LIMIT, ///< 70 Hook for enforcing memory stretch frequency limit - IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table - IDS_SKIP_FUSED_MAX_RATE, ///< 72 Hook to skip fused max rate cap - IDS_FCH_INIT_AT_RESET, ///< 73 Hook for FCH reset parameter - IDS_FCH_INIT_AT_ENV, ///< 74 Hook for FCH ENV parameter - IDS_ENFORCE_PLAT_TABLES, ///< 75 Hook to enforce platform specific tables - IDS_NBPS_MIN_FREQ, ///< 76 Hook for override MIN nb ps freq - IDS_GNB_FORCE_CABLESAFE, ///< 77 Hook for override Force Cable Safe - IDS_SKIP_PM_TRANSITION_STEP, ///< 78 Hook for provide IDS ability to skip this PM step - IDS_GNB_PROPERTY, ///< 79 Hook for GNB Property - IDS_GNB_PCIE_POWER_GATING, ///< 7A Hook for GNB PCIe Power Gating - IDS_MEM_DYN_DRAM_TERM, ///< 7B Hook for Override Dynamic Dram Term - IDS_MEM_DRAM_TERM, ///< 7C Hook for Override Dram Term - IDS_TRACE_MODE, ///< 7D Trace Mode - IDS_GNB_ALTVDDNB, ///< 7E Hook for Override AltVddNB - IDS_UCODE, ///< 7F Enable or Disable microcode patching - IDS_FAM_REG_GMMX, ///< 80 GMMX register access - IDS_MEMORY_POWER_POLICY, ///< 81 Memory power policy - IDS_GET_STRETCH_FREQUENCY_LIMIT, ///< 82 Hook for enforcing memory stretch frequency limit - IDS_CPU_FEAT, ///< 83 Hook for runtime force cpu feature disable - IDS_OPTION_END, ///< 84 End of IDS option -} AGESA_IDS_OPTION; - -#include "OptionsIds.h" -#include "Filecode.h" - -/* Initialize IDS controls */ -#ifndef IDSOPT_IDS_ENABLED - #define IDSOPT_IDS_ENABLED FALSE -#endif - -#ifndef IDSOPT_CONTROL_ENABLED - #define IDSOPT_CONTROL_ENABLED FALSE -#endif - -#ifndef IDSOPT_CONTROL_NV_TO_CMOS - #define IDSOPT_CONTROL_NV_TO_CMOS FALSE -#endif - -#ifndef IDSOPT_TRACING_ENABLED - #define IDSOPT_TRACING_ENABLED FALSE -#endif - -#ifndef IDSOPT_TRACE_USER_OPTIONS - #define IDSOPT_TRACE_USER_OPTIONS TRUE -#endif - -#ifndef IDSOPT_PERF_ANALYSIS - #define IDSOPT_PERF_ANALYSIS FALSE -#endif - -#ifndef IDSOPT_HEAP_CHECKING - #define IDSOPT_HEAP_CHECKING FALSE -#endif - -#ifndef IDSOPT_ASSERT_ENABLED - #define IDSOPT_ASSERT_ENABLED FALSE -#endif - -#ifndef IDSOPT_ERROR_TRAP_ENABLED - #define IDSOPT_ERROR_TRAP_ENABLED FALSE -#endif - -#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE -#endif - -#ifndef IDSOPT_DEBUG_CODE_ENABLED - #define IDSOPT_DEBUG_CODE_ENABLED FALSE -#endif - -#ifndef IDSOPT_IDT_EXCEPTION_TRAP - #define IDSOPT_IDT_EXCEPTION_TRAP FALSE -#endif - -#ifndef IDSOPT_C_OPTIMIZATION_DISABLED - #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE -#endif - -#if IDSOPT_IDS_ENABLED == FALSE - #undef IDSOPT_CONTROL_ENABLED - #undef IDSOPT_TRACING_ENABLED - #undef IDSOPT_PERF_ANALYSIS - #undef IDSOPT_HEAP_CHECKING - #undef IDSOPT_ASSERT_ENABLED - #undef IDSOPT_ERROR_TRAP_ENABLED - #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - #undef IDSOPT_DEBUG_CODE_ENABLED - #undef IDSOPT_TRACE_USER_OPTIONS - - #define IDSOPT_CONTROL_ENABLED FALSE - #define IDSOPT_TRACING_ENABLED FALSE - #define IDSOPT_PERF_ANALYSIS FALSE - #define IDSOPT_HEAP_CHECKING FALSE - #define IDSOPT_ASSERT_ENABLED FALSE - #define IDSOPT_ERROR_TRAP_ENABLED FALSE - #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE - #define IDSOPT_DEBUG_CODE_ENABLED FALSE - #define IDSOPT_TRACE_USER_OPTIONS FALSE -#endif - -/** - * Make a Progress Report to the User. - * - * This Macro is always enabled. The default action is to write the TestPoint value - * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80. - * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port - * in OptionsIds.h in their build tip. - * - * @param[in] TestPoint The value for display indicating progress - * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS - * - **/ - -#define AGESA_TESTPOINT(TestPoint, StdHeader) - -#ifndef IDS_DEBUG_PORT - #define IDS_DEBUG_PORT 0x80 -#endif - -/** - * @def STOP_HERE - * (macro) - Causes program to halt. This is @b only for use during active debugging . - * - * Causes the program to halt and display the file number of the source of the - * halt (displayed in decimal). - * - **/ -#if IDSOPT_IDS_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - #define STOP_HERE IdsErrorStop (STOP_CODE); -#else - #define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds." -#endif - -/** - * @def ASSERT - * Test an assertion that the given statement is True. - * - * The statement is evaluated to a boolean value. If the statement is True, - * then no action is taken (no error). If the statement is False, a error stop - * is generated to halt the program. Used for testing for fatal errors that - * must be resolved before production. This is used to do parameter checks, - * bounds checking, range checks and 'sanity' checks. - * - * @param[in] conditional Assert that evaluating this conditional results in TRUE. - * - **/ -#ifndef ASSERT - #if IDSOPT_ASSERT_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - - #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE)); - #else - #define ASSERT(conditional) - #endif -#endif - -#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE - #undef IDSOPT_ERROR_TRAP_ENABLED - #define IDSOPT_ERROR_TRAP_ENABLED TRUE - #define IDS_CAR_CORRUPTION_CHECK(StdHeader) -#else - #define IDS_CAR_CORRUPTION_CHECK(StdHeader) -#endif - -#ifndef DEBUG_CODE - #if IDSOPT_DEBUG_CODE_ENABLED == TRUE - #define DEBUG_CODE(Code) - #else - #define DEBUG_CODE(Code) - #endif -#endif - -/** - * @def IDS_ERROR_TRAP - * Trap AGESA Error events with stop code display. - * - * Works similarly to use of "ASSERT (FALSE);" - * - */ -#if IDSOPT_ERROR_TRAP_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - - #define IDS_ERROR_TRAP IdsErrorStop (STOP_CODE) -#else - #define IDS_ERROR_TRAP -#endif - -///give the extended Macro default value -#ifndef __IDS_EXTENDED__ - #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS - #define IDS_INITIAL_F10_PM_STEP - #define IDS_INITIAL_F12_PM_STEP - #define IDS_INITIAL_F14_PM_STEP - #define IDS_INITIAL_F15_OR_PM_STEP - #define IDS_INITIAL_F15_TN_PM_STEP - #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader) - #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader) - #define IDS_EXTENDED_HEAP_SIZE 0 - #define IDS_EXT_INCLUDE_F10(file) - #define IDS_EXT_INCLUDE_F12(file) - #define IDS_EXT_INCLUDE_F14(file) - #define IDS_EXT_INCLUDE_F15(file) - #define IDS_EXT_INCLUDE(file) - #define IDS_PAD_4K -#endif - -#ifndef IDS_NUM_NV_ITEM - #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM) -#endif - -#define IDS_CMOS_INDEX_PORT 0x70 -#define IDS_CMOS_DATA_PORT 0x71 -#define IDS_CMOS_REGION_START 0x20 -#define IDS_CMOS_REGION_END 0x7F -#define IDS_AP_GET_NV_FROM_CMOS(x) FALSE - -#if IDSOPT_CONTROL_ENABLED == TRUE - #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) - - #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) - #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE - #undef IDS_AP_GET_NV_FROM_CMOS - #define IDS_AP_GET_NV_FROM_CMOS(x) - #ifdef IDS_OPT_CMOS_INDEX_PORT - #undef IDS_CMOS_INDEX_PORT - #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT - #endif - - #ifdef IDS_OPT_CMOS_DATA_PORT - #undef IDS_CMOS_DATA_PORT - #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT - #endif - - #ifdef IDS_OPT_CMOS_REGION_START - #undef IDS_CMOS_REGION_START - #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START - #endif - - #ifdef IDS_OPT_CMOS_REGION_END - #undef IDS_CMOS_REGION_END - #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END - #endif - #endif -#else - #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) - - #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) AGESA_SUCCESS -#endif - -/** - * Macro to add a *skip* hook for IDS options - * - * The default minimal action is to do nothing and there is no any code to increase. - * For debug environments, IDS dispatcher function will be called to perform - * the detailed action and to skip AGESA code if necessary. - * - * @param[in] IdsOption IDS Option ID for this hook point - * @param[in, out] DataPtr Data Pointer to override - * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS - * - * - **/ - -#if IDSOPT_CONTROL_ENABLED == TRUE - #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) -#else - #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) -#endif - -/** - * Macro to add a heap manager routine - * - * when memory is allocated the heap manager actually allocates two extra dwords of data, - * one dword buffer before the actual memory, and one dword afterwards. - * a complete heap walk and check to be performed at any time. - * it would ASSERT if the heap is corrupt - * - * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS - * - * - **/ - -// Heap debug feature -#define SENTINEL_BEFORE_VALUE 0x64616548 // "Head" -#define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail" -#if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_HEAP_CHECKING == TRUE - #define SIZE_OF_SENTINEL 4 - #define NUM_OF_SENTINEL 2 // Before ("Head") and After ("Tail") - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE); - #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE); - #define Heap_Check(stdheader) - #else - #define SIZE_OF_SENTINEL 0 - #define NUM_OF_SENTINEL 0 - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) - #define SET_SENTINEL_AFTER(NodePtr) - #define Heap_Check(stdheader) - #endif -#else - #define SIZE_OF_SENTINEL 0 - #define NUM_OF_SENTINEL 0 - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) - #define SET_SENTINEL_AFTER(NodePtr) - #define Heap_Check(stdheader) -#endif - -/** - * Macro to add IDT for debugging exception. - * - * A debug feature. Adding a 'jmp $' into every exception handler. - * So debugger could use HDT to skip 'jmp $' and execute the iret, - * then they could find which instruction cause the exception. - * - * @param[in] FunctionId IDS Function ID for this hook point - * @param[in, out] DataPtr Data Pointer to override - * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS - * - * - **/ -#if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE - #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) - #else - #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) - #endif -#else - #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) -#endif - - - - -/** - * Macro to add HDT OUT - * - * The default minimal action is to do nothing and there is no any code to increase. - * For debug environments, the debug information can be displayed in HDT or other - * devices. - * - **/ -#if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_TRACING_ENABLED == TRUE - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - - #ifndef __GNUC__ - #pragma warning(disable: 4127) - #define IDS_HDT_CONSOLE(f, s, ...) - #else - #define IDS_HDT_CONSOLE(f, s, ...) printk (BIOS_DEBUG, s, ##__VA_ARGS__); - #endif - - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) - //#define CONSOLE(s, ...) - #else - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - #define IDS_HDT_CONSOLE(f, s, ...) - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) - //#define CONSOLE(s, ...) CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds." - #endif -#else - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - #define IDS_HDT_CONSOLE(f, s, ...) - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) -// #define CONSOLE(s, ...) CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds." -#endif - -#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS - -#if IDSOPT_PERF_ANALYSIS == TRUE - #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) - #define IDS_PERF_ANALYSE(StdHeader) - #define IDS_PERF_TIME_MEASURE(StdHeader) -#else - #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) - #define IDS_PERF_ANALYSE(StdHeader) - #define IDS_PERF_TIME_MEASURE(StdHeader) -#endif - -///For IDS feat use -#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull -#define IDS_BSP_ONLY TRUE -#define IDS_ALL_CORES FALSE - -#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_LIBRARY_IDSLIB_FILECODE - -#define IDS_CALLOUT_INIT 0x01 ///< The function data of IDS callout function of initialization. - -/// Function entry for HDT script to call -typedef struct _SCRIPT_FUNCTION { - UINTN FuncAddr; ///< Function address in ROM - CHAR8 FuncName[40]; ///< Function name -} SCRIPT_FUNCTION; - -/// Data Structure for Mem ECC parameter override -typedef struct { - IN BOOLEAN CfgEccRedirection; ///< ECC Redirection - IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate - IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate - IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate - IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate - IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate - IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood -} ECC_OVERRIDE_STRUCT; - - - - -/** - * AGESA Test Points - * - * These are the values displayed to the user to indicate progress through boot. - * These can be used in a debug environment to stop the debugger at a specific - * test point: - * For SimNow!, this command - * bi 81 w vb 49 - * will stop the debugger on one of the TracePoints (49 is the TP value in this example). - * - */ -typedef enum { - StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs - - // Memory test points - TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface) - TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface) - TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface) - TpProcMemDramInit, ///< 04 .. DRAM initialization - TpProcMemSPDChecking, ///< 05 .. - TpProcMemModeChecking, ///< 06 .. - TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration - TpProcMemSpdTiming, ///< 08 .. - TpProcMemDramMapping, ///< 09 .. - TpProcMemPlatformSpecificConfig, ///< 0A .. - TPProcMemPhyCompensation, ///< 0B .. - TpProcMemStartDcts, ///< 0C .. - TpProcMemBeforeDramInit, ///< 0D .. (Public interface) - TpProcMemPhyFenceTraining, ///< 0E .. - TpProcMemSynchronizeDcts, ///< 0F .. - TpProcMemSystemMemoryMapping, ///< 10 .. - TpProcMemMtrrConfiguration, ///< 11 .. - TpProcMemDramTraining, ///< 12 .. - TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface) - TpProcMemWriteLevelizationTraining, ///< 14 .. - TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start - TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start - TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured - TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL - TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL - TpProcMemReceiverEnableTraining, ///< 1A .. - TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop - TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay - TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern - TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern - TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern - TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel - TpProcMemReceiveDqsTraining, ///< 21 .. - TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay - TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern - TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep - TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay - TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern - TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern - TpProcMemRcvDqsResults, ///< 28 .. Update results - TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window - TpProcMemTransmitDqsTraining, ///< 2A .. - TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep - TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay - TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern - TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern - TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern - TpProcMemTxDqResults, ///< 30 .. Update results - TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window - TpProcMemMaxRdLatencyTraining, ///< 32 .. - TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep - TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay - TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern - TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern - TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern - TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init - TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init - TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init - TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init - TpProcMemEccInitialization, ///< 3C .. ECC initialization - TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init - TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd" - TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd" - TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit" - TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining" - TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining" - TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit - TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT - TpProcMemLvDdr3, ///< 48 .. Before LV DDR3 - TpProcMemInitMCT, ///< 49 .. Before InitMCT - TpProcMemOtherTiming, ///< 4A.. Before OtherTiming - TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping - TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs - TpProcMemMemClr, ///< 4D .. Before MemClr - TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal - TpProcMemDmi, ///< 4F .. Before DMI - TpProcMemEnd, ///< 50 .. End of memory code - - // CPU test points - TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords - TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt - TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling - TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData - TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea - TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat - TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit - TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing - TpProcCpuSetBrandID, ///< 59 .. Set brand ID - TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC - TpProcCpuLoadUcode, ///< 5B .. Load microcode patch - TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point - TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing - TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point - TpProcCpuCoreLeveling, ///< 5F .. Core Leveling - TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up - TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point - TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling - TpProcCpuBeforeRelinquishAPsFeatureInit, ///< 63 .. Before Relinquishing control of APs feature dispatch point - TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer - TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer - TpProcCpuBeforeAllocateSratBuffer, ///< 66 .. Before the SRAT init code calls out to allocate a buffer - TpProcCpuAfterAllocateSratBuffer, ///< 67 .. After the SRAT init code calls out to allocate a buffer - TpProcCpuBeforeLocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to locate a buffer - TpProcCpuAfterLocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to locate a buffer - TpProcCpuBeforeAllocateSsdtBuffer, ///< 6A .. Before the P-state init code calls out to allocate a buffer - TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer - - // HT test points - TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface) - TpProcHtTopology, ///< 72 .. Topology match, routing, begin - TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin - TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin - TpProcHtOptGather, ///< 75 .. Optimization: Gather begin - TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin - TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin - TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin - TpProcHtOptFinish, ///< 79 .. Optimization: Set begin - TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin - TpProcHtTuning, ///< 7B .. Misc Tuning Begin - TpProcHtDone, ///< 7C .. HT Init complete - TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin - TpProcHtApMapDone, ///< 7E .. AP HT: Complete - - // Extended memory test point - TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2 - TpProcMemSendMRS3, ///< 81 .. Sedding MRS3 - TpProcMemSendMRS1, ///< 82 .. Sending MRS1 - TpProcMemSendMRS0, ///< 83 .. Sending MRS0 - TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read - TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write - TpProcMem__RdDqsTraining, ///< 86 .. Mem: RdDqs Training begin - TpProcMemBefore__TrainExtVrefChange,///< 87 .. Mem: Before optional callout to platfrom BIOS to change External Vref during training - TpProcMemAfter__TrainExtVrefChange, ///< 88 .. Mem: After optional callout to platfrom BIOS to change External Vref during training - - StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs - TpNbxxx, ///< 91 . - EndNbTestPoints, ///< 92 End of TP range for NB - - StartFchTestPoints = 0xB0, ///< B0 Entry used for range testing for @b FCH related TPs - TpFchInitResetDispatching, ///< B1 .. FCH InitReset dispatch point - TpFchGppBeforePortTraining, ///< B2 .. Before FCH GPP port training - TpFchGppGen1PortPolling, ///< B3 .. FCH GPP port polling with GEN1 speed - TpFchGppGen2PortPolling, ///< B4 .. FCH GPP port polling with GEN2 speed - TpFchGppAfterPortTraining, ///< B5 .. After FCH GPP port training - TpFchInitEnvDispatching, ///< B6 .. FCH InitEnv dispatch point - TpFchInitMidDispatching, ///< B7 .. FCH InitMid dispatch point - TpFchInitLateDispatching, ///< B8 .. FCH InitLate dispatch point - TpFchGppHotPlugging, ///< B9 .. FCH GPP hot plug event - TpFchGppHotUnplugging, ///< BA .. AFCH GPP hot unplug event - TpFchInitS3EarlyDispatching, ///< BB .. FCH InitS3Early dispatch point - TpFchInitS3LateDispatching, ///< BC .. FCH InitS3Late dispatch point - EndFchTestPoints, ///< BF End of TP range for FCH - - // Interface test points - TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset - TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset - TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery - TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery - TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly - TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly - TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost - TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost - TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv - TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv - TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid - TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid - TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate - TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate - TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save - TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save - TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume - TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume - TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore - TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore - TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore - TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore - TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog - TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog - TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId - TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId - TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress - TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress - TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore - TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore - TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP - TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP - TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data - TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data - TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer - TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer - TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer - TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer - TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer - TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer - TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP - TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP - TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP - TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP - TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer - TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer - TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer - TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer - TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer - TpPerfUnit, ///< F8 .. The Unit of performance measure. - EndAgesaTps = 0xFF, ///< Last defined AGESA TP -} AGESA_TP; - -///Ids Feat description -typedef enum { - IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update - IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate - IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate - IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control - IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size - IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock - IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode - IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length - IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down - IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down - IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter - IDS_FEAT_HDTOUT, ///< Feat for hdt out - IDS_FEAT_HT_SETTING, ///< Feat for Ht setting - IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config - IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature - IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control - IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping - IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy - IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS - IDS_FEAT_COMMON, ///< Common Feat - IDS_FEAT_END = 0xFF ///< End of Common feat -} IDS_FEAT; - -///Ids IDT table function ID -typedef enum { - IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000, ///< Function ID for saving IDTR for BSC - IDS_IDT_RESTORE_IDTR_FOR_BSC, ///< Function ID for restoring IDTR for BSC - IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, ///< Function ID for updating exception vector -} IDS_IDT_FUNC_ID; - -typedef IDS_STATUS IDS_COMMON_FUNC ( - IN OUT VOID *DataPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN IDS_NV_ITEM *IdsNvPtr - ); - -typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC; - -/// Data Structure of IDS Feature block -typedef struct _IDS_FAMILY_FEAT_STRUCT { - IDS_FEAT IdsFeat; ///< Ids Feat ID - BOOLEAN IsBsp; ///< swith for Bsp check - AGESA_IDS_OPTION IdsOption; ///< IDS option - UINT64 CpuFamily; ///< - PIDS_COMMON_FUNC pf_idsoption; /// /P /EP /C /FAs @n - * PreProcessor output is produced in an .i file in the directory where the project - * file is located. - * - Design Guides: - * - add here >>> - * - */ - -/** - * @page platforminstall Platform Build Options. - * - * Build options are boolean constants. The purpose of build options is to remove code - * from the build to reduce the overall code size present in the ROM image. Unless - * otherwise specified, the default action is to include all options. If a build option is - * not specifically listed as disabled, then it is included into the build. - * - * The documented build options are imported from a user controlled file for - * processing. The build options for all platform solutions are listed below: - * - * @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n - * If unbuffered DIMMs are NOT expected to be required in the system, the code that - * handles unbuffered DIMMs can be removed from the build. - * - * @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n - * If registered DIMMs are NOT expected to be required in the system, the code - * that handles registered DIMMs can be removed from the build. - * - * @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_LRDIMMS_SUPPORT @n - * If Load Reduced DIMMs are NOT expected to be required in the system, the code - * that handles Load Reduced DIMMs can be removed from the build. - * - * @note The above three options operate independently from each other; however, at - * least one of the unbuffered , registered or load reduced DIMM options must be present in the build. - * - * @anchor BLDOPT_REMOVE_ECC_SUPPORT - * @li @e BLDOPT_REMOVE_ECC_SUPPORT @n - * Use this option to remove the code for Error Checking & Correction. - * - * @anchor BLDOPT_REMOVE_BANK_INTERLEAVE - * @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory between banks on a DIMM. - * - * @anchor BLDOPT_REMOVE_DCT_INTERLEAVE - * @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory from two DRAM controllers. - * - * @anchor BLDOPT_REMOVE_NODE_INTERLEAVE - * @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory from two HyperTransport nodes. - * - * @anchor BLDOPT_REMOVE_PARALLEL_TRAINING - * @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n - * For multi-socket systems, training memory in parallel can reduce the time - * needed to boot. - * - * @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - * @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n - * Online Spare support is removed by this option. - * - * @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n - * Many systems use only a single socket and may benefit in code space to remove - * this code. However, certain processors have multiple HyperTransport nodes - * within a single socket. For these processors, the multi-node support is - * required and this option has no effect. - * - * @anchor BLDOPT_REMOVE_ACPI_PSTATES - * @li @e BLDOPT_REMOVE_ACPI_PSTATES @n - * This option removes the code that generates the ACPI tables used in power - * management. - * - * @anchor BLDCFG_PSTATE_HPC_MODE - * @li @e BLDCFG_PSTATE_HPC_MODE @n - * This option enables PStates high performance computing mode (HPC mode) - * - * @anchor BLDOPT_REMOVE_SRAT - * @li @e BLDOPT_REMOVE_SRAT @n - * This option removes the code that generates the SRAT tables used in performance - * tuning. - * - * @anchor BLDOPT_REMOVE_SLIT - * @li @e BLDOPT_REMOVE_SLIT @n - * This option removes the code that generates the SLIT tables used in performance - * tuning. - * - * @anchor BLDOPT_REMOVE_WHEA - * @li @e BLDOPT_REMOVE_WHEA @n - * This option removes the code that generates the WHEA tables used in error - * handling and reporting. - * - * @anchor BLDOPT_REMOVE_DMI - * @li @e BLDOPT_REMOVE_DMI @n - * This option removes the code that generates the DMI tables used in system - * management. - * - * @anchor BLDOPT_REMOVE_DQS_TRAINING - * @li @e BLDOPT_REMOVE_DQS_TRAINING @n - * This option removes the code used in memory performance tuning. - * - * @anchor BLDOPT_REMOVE_EARLY_SAMPLES - * @li @e BLDOPT_REMOVE_EARLY_SAMPLES @n - * Special support for Early Samples is included. Default setting is FALSE. - * - * @anchor BLDOPT_REMOVE_HT_ASSIST - * @li @e BLDOPT_REMOVE_HT_ASSIST @n - * This option removes the code which implements the HT Assist feature. - * - * @anchor BLDOPT_REMOVE_ATM_MODE - * @li @e BLDOPT_REMOVE_ATM_MODE @n - * This option removes the code which implements the ATM feature. - * - * @anchor BLDOPT_REMOVE_MSG_BASED_C1E - * @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n - * This option removes the code which implements the Message Based C1e feature. - * - * @anchor BLDOPT_REMOVE_C6_STATE - * @li @e BLDOPT_REMOVE_C6_STATE @n - * This option removes the code which implements the C6 C-state feature. - * - * @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT - * @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n - * This option removes the memory context restore feature. - * - * @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_10_SUPPORT @n - * If the package contains support for family 10h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_12_SUPPORT @n - * If the package contains support for family 10h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_14_SUPPORT @n - * If the package contains support for family 14h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_15_SUPPORT @n - * If the package contains support for family 15h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for AM3 sockets. - * - * @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for ASB2 sockets. - * - * @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for C32 sockets. - * - * @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FM1 sockets. - * - * @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FP1 sockets. - * - * @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FS1 sockets. - * - * @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FT1 sockets. - * - * @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for G34 sockets. - * - * @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for S1G3 sockets. - * - * @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for S1G4 sockets. - */ - -/** - * @page examplecustomizations Customization Examples - * - * The Addendum \Options.c file for each platform contains the minimum required - * customizations for that platform. That is, it contains settings which would be needed - * to boot a SimNow! bsd for that platform. - * However, each individual product based on that platform will have customizations necessary for - * that hardware. Since the actual customizations needed vary so much, they are not included in - * the \Options.c. This section provides examples of useful customizations that you can use or - * modify to suit your needs. - * - * @par - * - * Source for the examples shown can be found at Addendum\\Examples. @n - * - * - @ref DeemphasisExamples "Deemphasis List Examples" - * - @ref FrequencyLimitExamples "Frequency Limit Examples" - * - @ref PerfPerWattHt "A performance-per-watt optimization Example" - * - * @anchor DeemphasisExamples - * @par Deemphasis List Examples - * - * These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList. - * Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n - * @dontinclude DeemphasisExamples.c - *
    - *
  • - * The following deemphasis list provides an example for a 2P MCM Max Performance configuration. - * High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of - * putting specified link matches before all uses of match any. It often works well to specify the non-coherent links - * and use match any for the coherent links. - * @skip DinarDeemphasisList - * @until { - * The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2. - * @until { - * @line } - * @line { - * @line } - * The coherent links can run up to 3200 MHz. - * @until HT_FREQUENCY_MAX - * @line } - * end of list: - * @until } - * Make this list the build time customized deemphasis list. - * @line define - * - *
  • - * - * The following deemphasis list provides an example for a 4P MCM Max Performance configuration. - * This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long. - * There can be one to four IO Chains, depending on the IO board. - * @skipline DoubloonDeemphasisList - * @until DoubloonDeemphasisList - * - *
  • - * - * The following deemphasis list further illustrates complex coherent system deemphasis. This is the same - * Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as - * might be needed if each link has unique characterization). For this example, we skip the non-coherent chains. - * (A real system would have to include them, see example above.) - * @skip DinarPerLinkDeemphasisList - * @until { - * Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2. - * Provide entries to customize all HT3 frequencies at which the links may run. This example covers all HT3 speeds. - * @until { - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * Link 3 on both sockets connects different internal die: sublink 0 connects the internal node zeroes, and - * sublink 1 connects the internal node ones. So the link is unganged and both sublinks must be specifically - * customized. - * @until { - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * end of list: - * @until define - * - *
- * - * @anchor FrequencyLimitExamples - * @par Frequency Limit Examples - * - * These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList. - * Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n - * @dontinclude FrequencyLimitExamples.c - *
    - *
  • - * The following list provides an example for limiting all coherent links to non-extended frequencies, - * that is, to 2600 MHz or less. - * @skipline NonExtendedCpuToCpuLimitList - * @until { - * Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited. - * @until HT_FREQUENCY_LIMIT_2600M - * End of list: - * @until ; - * Customize the build to use this cpu to cpu frequency limit. - * @until NonExtendedCpuToCpuLimitList - * @n
    • - *
  • - * The following list provides an example for limiting all coherent links to HT 1 frequencies, - * that is, to 1000 MHz or less. This is sometimes useful for test and debug. - * @skipline Ht1CpuToCpuLimitList - * @until Ht1CpuToCpuLimitList - * @n
    • - *
  • - * The following list provides an example for limiting all non-coherent links to 2400 MHz or less. - * The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device - * to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any. - * @skipline No2600MhzIoLimitList - * @until No2600MhzIoLimitList - * @n
    • - *
  • - * The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency, - * that is, to 1200 MHz or less. This can be useful for test and debug. - * @skipline MinHt3IoLimitList - * @until MinHt3IoLimitList - * @n
    • - * - *
- * - * @anchor PerfPerWattHt - * @par Performance-per-Watt Optimization Example - * - * This example customizes AMD_HT_INTERFACE.SkipRegangList. - * Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n - * @dontinclude PerfPerWatt.c - * To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n - * @skipline PerfPerWatt - * @until PerfPerWatt - * - */ diff --git a/src/vendorcode/amd/agesa/f15/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/agesa/f15/Include/PlatformMemoryConfiguration.h deleted file mode 100644 index 402b1cf3e1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Include/PlatformMemoryConfiguration.h +++ /dev/null @@ -1,499 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Platform Specific Memory Configuration - * - * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 52513 $ @e \$Date: 2011-05-08 21:50:58 -0600 (Sun, 08 May 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_ -#define _PLATFORM_MEMORY_CONFIGURATION_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -#ifndef PSO_ENTRY - #define PSO_ENTRY UINT8 -#endif - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------- - * PLATFORM SPECIFIC MEMORY DEFINITIONS - *---------------------------------------------------------------------------------------- - */ -/// -/// Memory Speed and DIMM Population Masks -/// -///< DDR Speed Masks -///< Specifies the DDR Speed on a memory channel -/// -#define ANY_SPEED 0xFFFFFFFF -#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66)) -#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66)) -#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66)) -#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66)) -#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66)) -#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66)) -#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66)) -#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66)) -#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66)) -#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66)) -/// -///< DIMM POPULATION MASKS -///< Specifies the DIMM Population on a channel (can be added together to specify configuration). -///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1 -///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1 -/// -#define ANY_ 0xFF ///< Any dimm configuration the current channel -#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel -#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel -#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel -#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel -#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel -#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel -#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel -#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel -#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel -#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel -#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel -#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel -#define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel -#define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel -#define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel -#define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel -#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel -#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel -#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel -#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel -/// -///< CS POPULATION MASKS -///< Specifies the CS Population on a channel (can be added together to specify configuration). -///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting -/// -#define CS_ANY_ 0xFF ///< Any CS configuration -#define CS0_ 0x01 ///< CS0 bit map mask -#define CS1_ 0x02 ///< CS1 bit map mask -#define CS2_ 0x04 ///< CS2 bit map mask -#define CS3_ 0x08 ///< CS3 bit map mask -#define CS4_ 0x10 ///< CS4 bit map mask -#define CS5_ 0x20 ///< CS5 bit map mask -#define CS6_ 0x40 ///< CS6 bit map mask -#define CS7_ 0x80 ///< CS7 bit map mask -/// -///< Number of Dimms on the current channel -///< This is a mask used to indicate the number of dimms in a channel -///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms) -/// -#define ANY_NUM 0xFF ///< Any number of Dimms -#define NO_DIMM 0x00 ///< No Dimms present -#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel -#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel -#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel -#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel - -/// -///< DIMM VOLTAGE MASKS -/// -#define VOLT_ANY_ 0xFF ///< Any voltage configuration -#define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask -#define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask -#define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask - -// -// < Not applicable -// -#define NA_ 0 ///< Not applicable - -/*---------------------------------------------------------------------------------------- - * - * Platform Specific Override Definitions for Socket, Channel and Dimm - * This indicates where a platform override will be applied. - * - *---------------------------------------------------------------------------------------- - */ -/// -///< SOCKET MASKS -///< Indicates associated processor sockets to apply override settings -/// -#define ANY_SOCKET 0xFF ///< Apply to all sockets -#define SOCKET0 0x01 ///< Apply to socket 0 -#define SOCKET1 0x02 ///< Apply to socket 1 -#define SOCKET2 0x04 ///< Apply to socket 2 -#define SOCKET3 0x08 ///< Apply to socket 3 -#define SOCKET4 0x10 ///< Apply to socket 4 -#define SOCKET5 0x20 ///< Apply to socket 5 -#define SOCKET6 0x40 ///< Apply to socket 6 -#define SOCKET7 0x80 ///< Apply to socket 7 -/// -///< CHANNEL MASKS -///< Indicates Memory channels where override should be applied -/// -#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels -#define CHANNEL_A 0x01 ///< Apply to Channel A -#define CHANNEL_B 0x02 ///< Apply to Channel B -#define CHANNEL_C 0x04 ///< Apply to Channel C -#define CHANNEL_D 0x08 ///< Apply to Channel D -/// -/// DIMM MASKS -/// Indicates Dimm Slots where override should be applied -/// -#define ALL_DIMMS 0xFF ///< Apply to all dimm slots -#define DIMM0 0x01 ///< Apply to Dimm Slot 0 -#define DIMM1 0x02 ///< Apply to Dimm Slot 1 -#define DIMM2 0x04 ///< Apply to Dimm Slot 2 -#define DIMM3 0x08 ///< Apply to Dimm Slot 3 -/// -/// REGISTER ACCESS MASKS -/// Not supported as an at this time -/// -#define ACCESS_NB0 0x0 -#define ACCESS_NB1 0x1 -#define ACCESS_NB2 0x2 -#define ACCESS_NB3 0x3 -#define ACCESS_NB4 0x4 -#define ACCESS_PHY 0x5 -#define ACCESS_DCT_XT 0x6 -/*---------------------------------------------------------------------------------------- - * - * Platform Specific Overriding Table Definitions - * - *---------------------------------------------------------------------------------------- - */ - -#define PSO_END 0 ///< Table End -#define PSO_CKE_TRI 1 ///< CKE Tristate Map -#define PSO_ODT_TRI 2 ///< ODT Tristate Map -#define PSO_CS_TRI 3 ///< CS Tristate Map -#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel -#define PSO_CLK_SPEED 5 ///< Clock Speed -#define PSO_DIMM_TYPE 6 ///< Dimm Type -#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map -#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket -#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed -#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel -#define PSO_MEM_TECH 11 ///< Channel Memory Type -#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay -#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed -#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs -#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type -#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V -#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width -#define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent - -/*---------------------------------- - * CONDITIONAL PSO SPECIFIC ENTRIES - *---------------------------------*/ -// Condition Types -#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types -#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block -#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected -#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel -#define PSO_CONDITION_REG 103 // Reserved -#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types -// Action Types -#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types -#define PSO_ACTION_ODT 120 ///< ODT values to override -#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override -#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override -#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override -#define PSO_ACTION_REG 124 // Reserved -#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration -#define PSO_ACTION_MAX 125 ///< End of Action Entry Types -#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types - -/*---------------------------------- - * TABLE DRIVEN PSO SPECIFIC ENTRIES - *---------------------------------*/ -// Condition descriptor -#define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor - -// Overriding entry types -#define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types -#define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit -#define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom -#define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr -#define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns -#define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values -#define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values -#define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode -#define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL] -#define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR] -#define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT] -#define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed] -#define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT -#define PSO_TBLDRV____TRAINING 222 ///< training -#define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type -#define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types - -/*---------------------------------------------------------------------------------------- - * CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ -#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \ - PSO_CPU_FAMILY_TO_OVERRIDE, 4, \ - ((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF) - -#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ - PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \ - , Bit7Map - -#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \ - PSO_CKE_TRI, 5, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map - -#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \ - PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map - -#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ - PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map - -#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \ - PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel - -#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \ - PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel - -#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \ - PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket - -#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \ - PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \ - BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24) - -#define DRAM_TECHNOLOGY(SocketID, MemTechType) \ - PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24) - -#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed) \ - PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed - -#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed) \ - PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \ - Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \ - Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8) - -#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \ - PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE - -#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \ - PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE - -#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \ - PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE - -#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \ - PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth - -/*---------------------------------------------------------------------------------------- - * CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ -#define CONDITION_AND \ - PSO_CONDITION_AND, 0 - -#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \ - PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk - -#define COND_SPD(Byte, Mask, Value) \ - PSO_CONDITION_SPD, 3, Byte, Mask, Value - -#define COND_REG(Access, Offset, Mask, Value) \ - PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \ - ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \ - ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF) - -#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \ - PSO_ACTION_ODT, 9, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \ - Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt - -#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \ - PSO_ACTION_ADDRTMG, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF) - -#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \ - PSO_ACTION_ODCCONTROL, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF) - -#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \ - PSO_ACTION_SLEWRATE, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF) - -#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \ - PSO_ACTION_SPEEDLIMIT, 9, \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \ - (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \ - (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \ - (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF) - -/*---------------------------------------------------------------------------------------- - * END OF CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------- - * TABLE DRIVEN OVERRIDE MACROS - *---------------------------------------------------------------------------------------- - */ -/// Configuration sub-descriptors -typedef enum { - CONFIG_GENERAL, ///< CONFIG_GENERAL - CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT - CONFIG_RC2IBT, ///< CONFIG_RC2IBT - CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE -} Config_Type; - -// ==================== -// Configuration Macros -// ==================== -#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \ - PSO_TBLDRV_CONFIG, 9, \ - CONFIG_GENERAL, \ - DimmPerCH, DimmVolt, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF) - -#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \ - PSO_TBLDRV_CONFIG, 7, \ - CONFIG_SPEEDLIMIT, \ - DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm - -#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \ - PSO_TBLDRV_CONFIG, 10, \ - CONFIG_RC2IBT, \ - DimmPerCH, DimmVolt, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - NumOfReg - -//================== -// Overriding Macros -//================== -#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \ - PSO_TBLDRV_SPEEDLIMIT, 6, \ - (SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \ - (SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \ - (SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF) - -#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \ - PSO_TBLDRV_ODT_RTTNOM, 2, \ - TgtCS, RttNom - -#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \ - PSO_TBLDRV_ODT_RTTWR, 2, \ - TgtCS, RttWr - -#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \ - PSO_TBLDRV_ODTPATTERN, 16, \ - ((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \ - ((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \ - ((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \ - ((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF) - -#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \ - PSO_TBLDRV_ADDRTMG, 4, \ - ((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF) - -#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \ - PSO_TBLDRV_ODCCTRL, 4, \ - ((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF) - -#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \ - PSO_TBLDRV_SLOWACCMODE, 1, \ - SlowAccMode - -#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \ - PSO_TBLDRV_RC2_IBT, 2, \ - TgtDimm, IBT - -#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \ - PSO_TBLDRV_CONFIG, 1, \ - CONFIG_DONT_CARE, \ - PSO_TBLDRV_MR0_CL, 3, \ - RegValOfTcl, MR0CL13, MR0CL0 - -#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \ - PSO_TBLDRV_CONFIG, 1, \ - CONFIG_DONT_CARE, \ - PSO_TBLDRV_MR0_WR, 2, \ - RegValOfTwr, MR0WR - -#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \ - PSO_TBLDRV_CONFIG, 1, \ - CONFIG_DONT_CARE, \ - PSO_TBLDRV_RC10_OPSPEED, 5, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - MR10OPSPEED - -#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \ - PSO_TBLDRV_LRDIMM_IBT, 4, \ - F0RC8, F1RC0, F1RC1, F1RC2 - -#define TBLDRV_CONFIG_ENTRY____TRAINING(Training__Mode) \ - PSO_TBLDRV____TRAINING, 1, \ - Training__Mode - -//============================ -// Macros for removing entries -//============================ -#define INVALID_CONFIG_FLAG 0x8000 - -#define TBLDRV_INVALID_CONFIG \ - PSO_TBLDRV_INVALID_TYPE, 0 - -/*---------------------------------------------------------------------------------------- - * END OF TABLE DRIVEN OVERRIDE MACROS - *---------------------------------------------------------------------------------------- - */ - -#endif // _PLATFORM_MEMORY_CONFIGURATION_H_ diff --git a/src/vendorcode/amd/agesa/f15/Include/SanMarinoInstall.h b/src/vendorcode/amd/agesa/f15/Include/SanMarinoInstall.h deleted file mode 100644 index 6e0393c4c7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Include/SanMarinoInstall.h +++ /dev/null @@ -1,116 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a SanMarino platform solution - * - * This file generates the defaults tables for the "San Marino" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 59375 $ @e \$Date: 2011-09-21 13:24:35 -0600 (Wed, 21 Sep 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterfaceStub.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "OrochiPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '2', '.', '0', '.', '0', ' ', ' ', ' ', ' '} - - -// The San Marino solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the C32 socket. -#define INSTALL_C32_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_10_SUPPORT TRUE -#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE - -#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT - #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE - #undef INSTALL_FAMILY_10_SUPPORT - #define INSTALL_FAMILY_10_SUPPORT FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT - #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE - #undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT - #define INSTALL_FAMILY_15_MODEL_0x_SUPPORT FALSE - #endif -#endif - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0xFF) -#define DFLT_SCRUB_L2_RATE (0x10) -#define DFLT_SCRUB_L3_RATE (0x10) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0x12) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define DFLT_VRM_SLEW_RATE (2500) - - -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/f15/Include/Topology.h b/src/vendorcode/amd/agesa/f15/Include/Topology.h deleted file mode 100644 index 30e4ae66a5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Include/Topology.h +++ /dev/null @@ -1,161 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Topology interface definitions. - * - * Contains AMD AGESA internal interface for topology related data which - * is consumed by code other than HyperTransport init (and produced by - * HyperTransport init.) - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _TOPOLOGY_H_ -#define _TOPOLOGY_H_ - -// Defines for limiting data structure maximum allocation and limit checking. -#define MAX_NODES 8 -#define MAX_SOCKETS MAX_NODES -#define MAX_DIES 2 - -// Defines useful with package link -#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA -#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB -#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC - -/** - * Hop Count Table. - * This is a heap data structure. The Hops array is filled as a size x size matrix. - * The unused space, if any, is all at the end. - */ -typedef struct { - UINT8 Size; ///< The row and column size of actual hop count data */ - UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */ -} HOP_COUNT_TABLE; - -/** - * Socket and Module to Node Map Item. - * Provide the Node Id and core id range for each module in each processor. - */ -typedef struct { - UINT8 Node; ///< The module's Node id. - UINT8 LowCore; ///< The lowest processor core id for this module. - UINT8 HighCore; ///< The highest processor core id for this module. - UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module. - UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module. -} SOCKET_DIE_TO_NODE_ITEM; - -/** - * Socket and Module to Node Map. - * This type is a pointer to the actual map, it can be used for a struct item or - * for typecasting a heap buffer pointer. - */ -typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES]; - -/** - * Node id to Socket Die Map Item. - */ -typedef struct { - UINT8 Socket; ///< socket of the processor containing the Node. - UINT8 Die; ///< the module in the processor which is Node. -} NODE_TO_SOCKET_DIE_ITEM; - -/** - * Node id to Socket Die Map. - */ -typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES]; - -/** - * Provide AP core with socket and node context at start up. - * This information is posted to the AP cores using a register as a mailbox. - */ -typedef struct { - UINT32 Node:4; ///< The node id of Core's node. - UINT32 Socket:4; ///< The socket of this Core's node. - UINT32 Module:2; ///< The internal module number for Core's node. - UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1. - UINT32 :20; ///< Reserved -} AP_MAIL_INFO_FIELDS; - -/** - * AP info fields can be written and read to a register. - */ -typedef union { - UINT32 Info; ///< Just a number for register access, or opaque passing. - AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields. -} AP_MAIL_INFO; - -/** - * Provide AP core with system degree and system core number at start up. - * This information is posted to the AP cores using a register as a mailbox. - */ -typedef struct { - UINT32 SystemDegree:3; ///< The number of connected links - UINT32 :3; ///< Reserved - UINT32 HeapIndex:6; ///< The zero-based system core number - UINT32 :20; ///< Reserved -} AP_MAIL_EXT_INFO_FIELDS; - -/** - * AP info fields can be written and read to a register. - */ -typedef union { - UINT32 Info; ///< Just a number for register access, or opaque passing. - AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields. -} AP_MAIL_EXT_INFO; - -/** - * AP Info mailbox set. - */ -typedef struct { - AP_MAIL_INFO ApMailInfo; ///< The AP mail info - AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info -} AP_MAILBOXES; - -/** - * Provide a northbridge to package mapping for link assignments. - * - */ -typedef struct { - UINT8 Link; ///< The Node's link - UINT8 Module; ///< The internal module position of Node - UINT8 PackageLink; ///< The corresponding package link -} PACKAGE_HTLINK_MAP_ITEM; - -/** - * A Processor's complete set of link assignments - */ -typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[]; - -#endif // _TOPOLOGY_H_ diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c deleted file mode 100644 index 7d570679f1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c +++ /dev/null @@ -1,136 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD binary block interface - * - * Contains the block entry function dispatcher - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Legacy - * @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Dispatcher.h" -#include "Options.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CONST DISPATCH_TABLE DispatchTable[]; -extern AMD_MODULE_HEADER mCpuModuleID; - -/*---------------------------------------------------------------------------------------*/ -/** - * The Dispatcher is the entry point into the AGESA software. It takes a function - * number as entry parameter in order to invoke the published function - * - * @param[in,out] ConfigPtr - * - * @return AGESA Status. - * - */ -AGESA_STATUS -CALLCONV -AmdAgesaDispatcher ( - IN OUT VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - MODULE_ENTRY ModuleEntry; - DISPATCH_TABLE *Entry; - - Status = AGESA_UNSUPPORTED; - ModuleEntry = NULL; - - Entry = (DISPATCH_TABLE *) DispatchTable; - while (Entry->FunctionId != 0) { - if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) { - Status = Entry->EntryPoint (ConfigPtr); - break; - } - Entry++; - } - - // 2. Try next dispatcher if possible, and we have not already got status back - if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) { - ModuleEntry = (MODULE_ENTRY) (mCpuModuleID.NextBlock->ModuleDispatcher); - if (ModuleEntry != NULL) { - Status = (*ModuleEntry) (ConfigPtr); - } - } - - return (Status); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * The host environment interface of callout. - * - * @param[in] Func - * @param[in] Data - * @param[in,out] ConfigPtr - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -CALLCONV -AmdAgesaCallout ( - IN UINT32 Func, - IN UINTN Data, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 Result; - Result = AGESA_UNSUPPORTED; - if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) { - return Result; - } - - Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr); - return (Result); -} diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Makefile.inc b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Makefile.inc deleted file mode 100644 index 80cdf12a7d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -libagesa-y += Dispatcher.c -libagesa-y += agesaCallouts.c -libagesa-y += hobTransfer.c diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/agesaCallouts.c deleted file mode 100644 index 1af03b9c64..0000000000 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/agesaCallouts.c +++ /dev/null @@ -1,441 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU AGESA Callout Functions - * - * Contains code to set / get useful platform information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 50871 $ @e \$Date: 2011-04-14 15:39:51 -0600 (Thu, 14 Apr 2011) $ - * - */ -/***************************************************************************** - * AMD Generic Encapsulated Software Architecture - * - * Description: agesaCallouts.c - AGESA Call out functions - * - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Dispatcher.h" -#include "cpuServices.h" -#include "Ids.h" -#include "Filecode.h" - -#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - (AGESA ONLY) - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Call the host environment interface to do the warm or cold reset. - * - * @param[in] ResetType Warm or Cold Reset is requested - * @param[in,out] StdHeader Config header - * - */ -VOID -AgesaDoReset ( - IN UINTN ResetType, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - WARM_RESET_REQUEST Request; - - // Clear warm request bit and set state bits to the current post stage - GetWarmResetFlag (StdHeader, &Request); - Request.RequestBit = FALSE; - Request.StateBits = Request.PostStage; - SetWarmResetFlag (StdHeader, &Request); - - Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Call the host environment interface to allocate buffer in main system memory. - * - * @param[in] FcnData - * @param[in,out] AllocParams Heap manager parameters - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaAllocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *AllocParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to deallocate buffer in main system memory. - * - * @param[in] FcnData - * @param[in,out] DeallocParams Heap Manager parameters - * - * @return The AGESA Status returned from the callout. - */ -AGESA_STATUS -AgesaDeallocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *DeallocParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Call the host environment interface to Locate buffer Pointer in main system memory - * - * @param[in] FcnData - * @param[in,out] LocateParams Heap manager parameters - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaLocateBuffer ( - IN UINTN FcnData, - IN OUT AGESA_BUFFER_PARAMS *LocateParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to launch APs - * - * @param[in] ApicIdOfCore - * @param[in,out] LaunchApParams - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaRunFcnOnAp ( - IN UINTN ApicIdOfCore, - IN AP_EXE_PARAMS *LaunchApParams - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to read an SPD's content. - * - * @param[in] FcnData - * @param[in,out] ReadSpd - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaReadSpd ( - IN UINTN FcnData, - IN OUT AGESA_READ_SPD_PARAMS *ReadSpd - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to read an SPD's content. - * - * @param[in] FcnData - * @param[in,out] ReadSpd - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaReadSpdRecovery ( - IN UINTN FcnData, - IN OUT AGESA_READ_SPD_PARAMS *ReadSpd - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] FcnData - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeDramInitRecovery ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData); - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeDramInit ( - IN UINTN SocketIdModuleId, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)SocketIdModuleId, MemData); - - return Status; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeDQSTraining ( - IN UINTN SocketIdModuleId, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)SocketIdModuleId, MemData); - - return Status; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] FcnData - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaHookBeforeExitSelfRefresh ( - IN UINTN FcnData, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData); - - return Status; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Call the host environment interface to provide a user hook opportunity. - * - * @param[in] Data - * @param[in,out] IdsCalloutData - * - * @return The AGESA Status returned from the callout. - * - */ - - -AGESA_STATUS -AgesaGetIdsData ( - IN UINTN Data, - IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData); - - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * PCIE slot reset control - * - * - * - * @param[in] FcnData Function data - * @param[in] ResetInfo Reset information - * @retval Status Agesa status - */ - -AGESA_STATUS -AgesaPcieSlotResetControl ( - IN UINTN FcnData, - IN PCIe_SLOT_RESET_INFO *ResetInfo - ) -{ - AGESA_STATUS Status; - Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * OEM callout function for FCH data override - * - * - * @param[in] FchData FCH data pointer - * @retval Status This feature is not supported - */ - -AGESA_STATUS -AgesaFchOemCallout ( - IN VOID *FchData - ) -{ - return AGESA_UNSUPPORTED; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Optional call to the host environment interface to change the external Vref for training. - * - * @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId - * @param[in,out] MemData - * - * @return The AGESA Status returned from the callout. - * - */ -AGESA_STATUS -AgesaExternal__TrainVrefChange ( - IN UINTN SocketIdModuleId, - IN OUT MEM_DATA_STRUCT *MemData - ) -{ - AGESA_STATUS Status; - - Status = AmdAgesaCallout (AGESA_EXTERNAL____TRAIN_VREF_CHANGE, (UINT32)SocketIdModuleId, MemData); - - return Status; -} diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c deleted file mode 100644 index c56f95ec55..0000000000 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c +++ /dev/null @@ -1,393 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Hob Transfer functions. - * - * Contains code that copy Heap to temp memory or main memory. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuCacheInit.h" -#include "cpuFamilyTranslation.h" -#include "heapManager.h" -#include "cpuLateInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * CopyHeapToTempRamAtPost - * - * This function copies BSP heap content to RAM - * - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -CopyHeapToTempRamAtPost ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddressInCache; - UINT8 *BaseAddressInTempMem; - UINT8 *Source; - UINT8 *Destination; - UINT8 AlignTo16ByteInCache; - UINT8 AlignTo16ByteInTempMem; - UINT8 Ignored; - UINT32 SizeOfNodeData; - UINT32 TotalSize; - UINT32 HeapRamFixMtrr; - UINT32 HeapRamVariableMtrr; - UINT32 HeapInCacheOffset; - UINT64 MsrData; - UINT64 VariableMtrrBase; - UINT64 VariableMtrrMask; - UINTN AmdHeapRamAddress; - AGESA_STATUS IgnoredStatus; - BUFFER_NODE *HeapInCache; - BUFFER_NODE *HeapInTempMem; - HEAP_MANAGER *HeapManagerInCache; - HEAP_MANAGER *HeapManagerInTempMem; - CACHE_INFO *CacheInfoPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress; - // - //If the user define address above 1M, Mem Init has already set - //whole available memory as WB cacheable. - // - if (AmdHeapRamAddress < 0x100000) { - // Region below 1MB - // Fixed MTRR region - // turn on modification bit - LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); - MsrData |= 0x80000; - LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); - - if (AmdHeapRamAddress >= 0xC0000) { - // - // 0xC0000 ~ 0xFFFFF - // - HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + ((((UINTN)AmdHeapRamAddress >> 16) & 0x3) * 2)); - MsrData = AMD_MTRR_FIX4K_UC_DRAM; - LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader); - LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader); - } else if (AmdHeapRamAddress >= 0x80000) { - // - // 0x80000~0xBFFFF - // - HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + (((UINTN)AmdHeapRamAddress >> 17) & 0x1)); - MsrData = AMD_MTRR_FIX16K_UC_DRAM; - LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader); - } else { - // - // 0x0 ~ 0x7FFFF - // - LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); - MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7)))); - MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * (((UINTN)AmdHeapRamAddress >> 16) & 0x7))); - LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); - } - - // Turn on MTRR enable bit and turn off modification bit - LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); - MsrData |= 0x40000; - MsrData &= 0xFFFFFFFFFFF7FFFF; - LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); - } else { - // Region above 1MB - // Variable MTRR region - // Get family specific cache Info - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); - - // Find an empty MTRRphysBase/MTRRphysMask - for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE; - HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0; - HeapRamVariableMtrr--) { - LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) { - break; - } - } - if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) { - // All variable MTRR is used. - ASSERT (FALSE); - } - - // Set variable MTRR base and mask - // If the address ranges of two or more MTRRs overlap - // and if at least one of the memory types is UC, the UC memory type is used. - VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask); - VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK; - LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - } - // Copying Heap content - if (IsBsp (StdHeader, &IgnoredStatus)) { - TotalSize = sizeof (HEAP_MANAGER); - SizeOfNodeData = 0; - AlignTo16ByteInTempMem = 0; - BaseAddressInCache = (UINT8 *) (UINTN)StdHeader->HeapBasePtr; - HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache; - HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset; - HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); - - BaseAddressInTempMem = (UINT8 *) (UINTN) UserOptions.CfgHeapDramAddress; - HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); - - // copy heap from cache to temp memory. - // only heap with persist great than HEAP_LOCAL_CACHE will be copied. - // Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE. - while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) { - if (HeapInCache->Persist > HEAP_LOCAL_CACHE) { - AlignTo16ByteInCache = HeapInCache->PadSize; - AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF); - SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache; - TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem); - Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache; - Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem; - LibAmdMemCopy (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader); - LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader); - HeapInTempMem->OffsetOfNextNode = TotalSize; - HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem; - HeapInTempMem->PadSize = AlignTo16ByteInTempMem; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); - } - HeapInCacheOffset = HeapInCache->OffsetOfNextNode; - HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); - } - // initialize heap manager - if (TotalSize == sizeof (HEAP_MANAGER)) { - // heap is empty - HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER); - HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); - } else { - // heap is NOT empty - HeapManagerInTempMem->UsedSize = TotalSize; - HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER); - HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE)); - HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); - } - // heap signature - HeapManagerInCache->Signature = 0x00000000; - HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID; - // Free space node - HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize); - HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - } - return AGESA_SUCCESS; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * CopyHeapToMainRamAtPost - * - * This function copies Temp Ram heap content to Main Ram - * - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -CopyHeapToMainRamAtPost ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddressInTempMem; - UINT8 *BaseAddressInMainMem; - UINT8 *Source; - UINT8 *Destination; - UINT8 AlignTo16ByteInTempMem; - UINT8 AlignTo16ByteInMainMem; - UINT8 Ignored; - UINT32 SizeOfNodeData; - UINT32 TotalSize; - UINT32 HeapInTempMemOffset; - UINT32 HeapRamVariableMtrr; - UINT64 VariableMtrrBase; - UINT64 VariableMtrrMask; - AGESA_STATUS IgnoredStatus; - BUFFER_NODE *HeapInTempMem; - BUFFER_NODE *HeapInMainMem; - HEAP_MANAGER *HeapManagerInTempMem; - HEAP_MANAGER *HeapManagerInMainMem; - AGESA_BUFFER_PARAMS AgesaBuffer; - CACHE_INFO *CacheInfoPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - if (IsBsp (StdHeader, &IgnoredStatus)) { - TotalSize = sizeof (HEAP_MANAGER); - SizeOfNodeData = 0; - AlignTo16ByteInMainMem = 0; - BaseAddressInTempMem = (UINT8 *)(UINTN) StdHeader->HeapBasePtr; - HeapManagerInTempMem = (HEAP_MANAGER *)(UINTN) StdHeader->HeapBasePtr; - HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset); - - AgesaBuffer.StdHeader = *StdHeader; - AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE; - AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE; - if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer; - HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); - LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader); - // copy heap from temp memory to main memory. - // only heap with persist great than HEAP_TEMP_MEM will be copied. - // Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM. - while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) { - if (HeapInTempMem->Persist > HEAP_TEMP_MEM) { - AlignTo16ByteInTempMem = HeapInTempMem->PadSize; - AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF); - SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem; - TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem); - Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem; - Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem; - LibAmdMemCopy (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader); - LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader); - HeapInMainMem->OffsetOfNextNode = TotalSize; - HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem; - HeapInMainMem->PadSize = AlignTo16ByteInMainMem; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); - } - HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode; - HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset); - } - // initialize heap manager - if (TotalSize == sizeof (HEAP_MANAGER)) { - // heap is empty - HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER); - HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); - } else { - // heap is NOT empty - HeapManagerInMainMem->UsedSize = TotalSize; - HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER); - HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE)); - HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); - } - // heap signature - HeapManagerInTempMem->Signature = 0x00000000; - HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID; - // Free space node - HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize; - HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - } - // if address of heap in temp memory is above 1M, then we must used one variable MTRR. - if ( (UINTN) StdHeader->HeapBasePtr >= 0x100000) { - // Find out which variable MTRR was used in CopyHeapToTempRamAtPost. - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); - for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE; - HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0; - HeapRamVariableMtrr--) { - LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - if ((VariableMtrrBase == (UINT64) (UINTN) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) && - (VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) { - break; - } - } - if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) { - // Clear variable MTRR which set in CopyHeapToTempRamAtPost. - VariableMtrrBase = 0; - VariableMtrrMask = 0; - LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); - LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - } - } - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/MainPage.h b/src/vendorcode/amd/agesa/f15/MainPage.h deleted file mode 100644 index c2bb983fec..0000000000 --- a/src/vendorcode/amd/agesa/f15/MainPage.h +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @mainpage - * - * The design and maintenance documentation for AGESA Sample Code is organized as - * follows. On this page, you can reference design guides, maintenance guides, and - * general documentation. Detailed Data Structure, Function, and Interface documentation - * may be found using the Data Structures or Files tabs. See Related Pages for a - * Release content summary, and, if this is not a production release, lists of To Do's, - * Deprecated items, etc. - * - * @subpage starthere "Start Here - Initial Porting and Integration." - * - * @subpage optionmain "Build Configuration and Options Guides and Documentation." - * - * @subpage commonmain "Processor Common Component Guides and Documentation." - * - * @subpage cpumain "CPU Component Guides and Documentation." - * - * @subpage htmain "HT Component Guides and Documentation." - * - * @subpage memmain "MEM Component Guides and Documentation." - * - * @subpage gnbmain "GNB Component Documentation." - * - * @subpage fchmain "FCH Component Documentation." - * - * @subpage idsmain "IDS Component Guides and Documentation." - * - * @subpage recoverymain "Recovery Component Guides and Documentation." - * - */ - -/** - * @page starthere Initial Porting and Integration - * - * @par Basic Check List - * - *
    - *
  • Copy the \Options.c file from the Addendum directory to the platform tip build directory. - * AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files. - *
  • Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory - * and make changes to enable the IDS support desired. It is highly recommended to set the following for - * initial integration and development:@n - * @code - * #define IDSOPT_IDS_ENABLED TRUE - * #define IDSOPT_ERROR_TRAP_ENABLED TRUE - * #define IDSOPT_ASSERT_ENABLED TRUE - * @endcode - *
  • Edit and modify the option selections in those two files to meet the needs of the specific platform. - *
  • Set the environment variable AGESA_ROOT to the root folder of the AGESA code. - *
  • Set the environment variable AGESA_OptsDir the platform build tip AGESA directory. - *
  • Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package. - *
- * - * @par Debugging Using ASSERT and IDS_ERROR_TRAP - * - * While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also - * catch and assist debug of wrapper and platform BIOS issues. - * - * When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a - * Stop Code. A Stop Code is eight hex digits. The first (most significant) four are the FILECODE. - * FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro. Each file has a - * unique code value. - * The least significant digits are the line number in that file. - * For example, 0210 means the macro is on line two hundred ten. - * (see ::IdsErrorStop for more details on stop code display.) - * - * Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist. - * Comments near each macro use will describe the nature of the error and typical wrapper errors or other - * root causes. - * - * After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in - * OptionsIds.h, except for regression testing. IDS is not expected to be enabled in production BIOS builds. - * - */ diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc deleted file mode 100644 index 7a29a81804..0000000000 --- a/src/vendorcode/amd/agesa/f15/Makefile.inc +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# Copyright (C) 2014 Edward O'Callaghan -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - - -## ABSOLUTE AGESA V5 ROOT PATH ## -AGESA_ROOT ?= $(PWD) -AGESA_ROOT = src/vendorcode/amd/agesa/f15 - -AGESA_AUTOINCLUDES := $(shell find $(AGESA_ROOT)/Proc -type d -exec echo -n "-I"{}" " \;) - -AGESA_INC = -I$(src)/vendorcode/amd/include -AGESA_INC += -I$(AGESA_ROOT) -AGESA_INC += -I$(AGESA_ROOT)/../common -AGESA_INC += -I$(AGESA_ROOT)/Include -AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) # OptionsIds.h - -BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) - -## AGESA need sse feature ## -CFLAGS_x86_32 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -CFLAGS_x86_64 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing - -# These are invalid, coreboot proper should not require -# use of AGESA internal header files. -CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family - -CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) -CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) - -####################################################################### - -subdirs-y += Legacy/Proc -subdirs-y += $(dir $(shell cd $(dir); find Proc -name Makefile.inc)) - -$(obj)/libagesa.fam15.a: $$(libagesa-objs) - @printf " AGESA $(subst $(obj)/,,$(@))\n" - $(AR_libagesa) rcs $@ $+ - -romstage-libs += $(obj)/libagesa.fam15.a -ramstage-libs += $(obj)/libagesa.fam15.a diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c deleted file mode 100644 index c54537359c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize the Family 10h specific way of running early initialization. - * - * Returns the table of initialization steps to perform at - * AmdInitEarly. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -GetF10EarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly; - -CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10EarlyInitOnCoreTable[] = -{ - {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {LoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET}, - {NULL, 0} -}; - -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a - * processor that uses the standard initialization steps should take. - * - * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[out] Table Table of appropriate init steps for the executing core. - * @param[in] EarlyParams Service Interface structure to initialize. - * @param[in] StdHeader Opaque handle to standard config header. - * - */ -VOID -GetF10EarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *Table = F10EarlyInitOnCoreTable; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c deleted file mode 100644 index 904e60b44f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c +++ /dev/null @@ -1,300 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 IO C-state feature support functions. - * - * Provides the functions necessary to initialize the IO C-state feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFeatures.h" -#include "cpuIoCstate.h" -#include "cpuF10PowerMgmt.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "CommonReturns.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F10InitializeIoCstateOnCore ( - IN VOID *CstateBaseMsr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F10IsIoCstateFeatureSupported ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable IO Cstate on a family 10h CPU. - * - * @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F10InitializeIoCstate ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - AP_TASK TaskPtr; - - if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { - // Initialize MSRC001_0073[CstateAddr] on each core to a region of - // the IO address map with 8 consecutive available addresses. - LocalMsrRegister = 0; - - ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress; - - TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable CState on a family 10h core. - * - * @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F10InitializeIoCstateOnCore ( - IN VOID *CstateBaseMsr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Initialize MSRC001_0073[CstateAddr] on each core - LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the size of CST object - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data - * @param[in] StdHeader Config Handle for library, services. - * - * @retval CstObjSize Size of CST Object - * - */ -UINT32 -STATIC -F10GetAcpiCstObj ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (CST_HEADER_SIZE + CST_BODY_SIZE); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Routine to generate the C-State ACPI objects - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] LocalApicId Local Apic Id for each core. - * @param[in, out] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F10CreateAcpiCstObj ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT8 LocalApicId, - IN OUT VOID **PstateAcpiBufferPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrData; - CST_HEADER_STRUCT *CstHeaderPtr; - CST_BODY_STRUCT *CstBodyPtr; - - // Read from MSR C0010073 to obtain CstateAddr - LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader); - ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) && - (((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8)); - - // Typecast the pointer - CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr; - - // Set CST Header - CstHeaderPtr->NameOpcode = NAME_OPCODE; - CstHeaderPtr->CstName_a__ = CST_NAME__; - CstHeaderPtr->CstName_a_C = CST_NAME_C; - CstHeaderPtr->CstName_a_S = CST_NAME_S; - CstHeaderPtr->CstName_a_T = CST_NAME_T; - - // Typecast the pointer - CstHeaderPtr++; - CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr; - - // Set CST Body - CstBodyPtr->PkgOpcode = PACKAGE_OPCODE; - CstBodyPtr->PkgLength = CST_LENGTH; - CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS; - CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE; - CstBodyPtr->Count = CST_COUNT; - CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE; - CstBodyPtr->PkgLength2 = CST_PKG_LENGTH; - CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS; - CstBodyPtr->BufferOpcode = BUFFER_OPCODE; - CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH; - CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS; - CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE; - CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION; - CstBodyPtr->GdrLength = CST_GDR_LENGTH; - CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO; - CstBodyPtr->RegBitWidth = 0x08; - CstBodyPtr->RegBitOffset = 0x00; - CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS; - CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr; - CstBodyPtr->EndTag = 0x0079; - CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE; - CstBodyPtr->Type = CST_C2_TYPE; - CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE; - CstBodyPtr->Latency = 0x4B; - CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE; - CstBodyPtr->Power = 0; - - CstBodyPtr++; - - //Update the pointer - *PstateAcpiBufferPtr = CstBodyPtr; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Routine to check whether IO Cstate should be supported. - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] Socket Zero-based socket number. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Support IO Cstate. - * @retval FALSE Do not support IO Cstate. - * - */ -BOOLEAN -F10IsIoCstateFeatureSupported ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - CPUID_DATA CpuId; - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - // Only Rev.E processor with CPB enabled and ucode 010000BF or later loaded - // MSR_C001_0073 can be programmed - if ((LogicalId.Revision & AMD_F10_Ex) != 0) { - LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader); - if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) { - LibAmdMsrRead (MSR_PATCH_LEVEL, &LocalMsrRegister, StdHeader); - if ((LocalMsrRegister & 0xffffffff) >= 0x010000BF) { - return TRUE; - } - } - } - return FALSE; -} - -CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport = -{ - 0, - F10IsIoCstateFeatureSupported, - F10InitializeIoCstate, - F10GetAcpiCstObj, - F10CreateAcpiCstObj, - (PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c deleted file mode 100644 index 61914a6759..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c +++ /dev/null @@ -1,1537 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 PCI tables from Multi-Link BKDG paragraph recommended settings. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x10 - * @e \$Revision: 59564 $ @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10MultiLinkPciRegisters[] = -{ - // Function 0 - -// F0x68 - Link Transaction Control -// bit[14:13], BufPriRel = 02h - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - (AMD_F10_ALL & ~AMD_F10_Dx), // CpuRevision rev C or less. - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x00004000, // regData - 0x00006000, // regMask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 2 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 2 - // 17:16 NpReqData: 2 - // 15:12 ProbeCmd: 9 - // 11:8 RspCmd: 9 - // 7:5 PReq: 2 - // 4:0 NpReqCmd: 4 -{ - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - HT_HOST_FEAT_COHERENT, // link features - 0x10, // address - 0x048A9944, // data - 0x0FFFFFFF // mask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 2 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 1 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 4 - // 4:0 NpReqCmd: 18 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Cx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - HT_HOST_FEAT_NONCOHERENT, // link features - 0x10, // address - 0x04850292, // data - 0x0FFFFFFF // mask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 1 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 6 - // 4:0 NpReqCmd: 16 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - HT_HOST_FEAT_NONCOHERENT, // link features - 0x10, // address - 0x008502D0, // data - 0x0FFFFFFF // mask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 3 - // 17:16 NpReqData: 2 - // 15:12 ProbeCmd: 8 - // 11:8 RspCmd: 9 - // 7:5 PReq: 2 - // 4:0 NpReqCmd: 4 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - HT_HOST_FEAT_COHERENT, // link features - 0x10, // address - 0x008E8944, // data - 0x0FFFFFFF // mask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 1 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 6 - // 4:0 NpReqCmd: 15 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - HT_HOST_FEAT_NONCOHERENT, // link features - 0x10, // address - 0x008502CF, // data - 0x0FFFFFFF // mask - }} - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 0 -{ - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - HT_HOST_FEAT_COHERENT, // link features - 0x14, // address - 0x00000000, // data - 0x1FFF0000 // mask - }} - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 0 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - HT_HOST_FEAT_NONCOHERENT, // link features - 0x14, // address - 0x00000000, // data - 0x1FFF0000 // mask - }} - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 1 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 1 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - HT_HOST_FEAT_COHERENT, // link features - 0x14, // address - 0x02010000, // data - 0x1FFF0000 // mask - }} - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 1 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - HT_HOST_FEAT_NONCOHERENT, // link features - 0x14, // address - 0x00010000, // data - 0x1FFF0000 // mask - }} - }, - -// Function 3 - Misc. Control - -// F3x6C - Data Buffer Control -// XBAR buffer settings -// bits[2:0] UpReqDBC = 2 -// bits[5:4] DnReqDBC = 1 -// bits[7:6] DnRspDBC = 1 -// bit[15] DatBuf24 = 1 -// bits[18:16] UpRspDBC = 1 -// bits[30:28] IsocRspDBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Cx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C), // Address - 0x00018052, // regData - 0x700780F7, // regMask - }} - }, -// F3x6C - Data Buffer Control -// XBAR buffer settings -// bits[2:0] UpReqDBC = 2 -// bits[5:4] DnReqDBC = 1 -// bits[7:6] DnRspDBC = 1 -// bit[15] DatBuf24 = 1 -// bits[18:16] UpRspDBC = 2 -// bits[30:28] IsocRspDBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C), // Address - 0x00028052, // regData - 0x700780F7, // regMask - }} - }, -// F3x6C - Data Buffer Control -// bits[2:0] UpReqDBC = 2 -// bits[5:4] DnReqDBC = 1 -// bits[7:6] DnRspDBC = 1 -// bit[15] DatBuf24 = 1 -// bits[18:16] UpRspDBC = 1 -// bits[30:28] IsocRspDBC = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address - 0x10018052, // regData - 0x700780F7, // regMask - }} - }, -// F3x70 - SRI_to_XBAR Command Buffer Count -// bits[2:0] UpReqCBC = 3 -// bits[5:4] DnReqCBC = 1 -// bits[7:6] DnRspCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 1 -// bits[18:16] UpRspCBC = 4 -// bits[22:20] IsocReqCBC = 0 -// bits[26:24] IsocPreqCBC = 0 -// bits[30:28] IsocRspCBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Cx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address - 0x00041153, // regData - 0x777777F7, // regMask - }} - }, -// F3x70 - SRI_to_XBAR Command Buffer Count -// bits[2:0] UpReqCBC = 3 -// bits[5:4] DnReqCBC = 1 -// bits[7:6] DnRspCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 1 -// bits[18:16] UpRspCBC = 5 -// bits[22:20] IsocReqCBC = 0 -// bits[26:24] IsocPreqCBC = 0 -// bits[30:28] IsocRspCBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address - 0x00051153, // regData - 0x777777F7, // regMask - }} - }, -// F3x70 - SRI_to_XBAR Command Buffer Count -// bits[2:0] UpReqCBC = 3 -// bits[5:4] DnReqCBC = 1 -// bits[7:6] DnRspCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 1 -// bits[18:16] UpRspCBC = 5 -// bits[22:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 0 -// bits[30:28] IsocRspCBC = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address - 0x10151153, // regData - 0x777777F7, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 1 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 0 -// bits[26:24] IsocPreqCBC = 0 -// bits[30:28] DRReqCBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x00081111, // regData - 0x00FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 1 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 0 -// bits[30:28] DRReqCBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x00181111, // regData - 0x00FF7777, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 20 -// bits[11:8] Sri2XbarFreeXreqCBC = 9 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 9 -// bits[22:20] Sri2XbarFreeRspDBC = 0 -// bits[30:28] Xbar2SriFreeListCBInc = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Cx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00090914, // regData - 0x707FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 24 -// bits[11:8] Sri2XbarFreeXreqCBC = 9 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 9 -// bits[22:20] Sri2XbarFreeRspDBC = 0 -// bits[30:28] Xbar2SriFreeListCBInc = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE), // 4 or fewer cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00090A18, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 22 -// bits[11:8] Sri2XbarFreeXreqCBC = 9 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 9 -// bits[22:20] Sri2XbarFreeRspDBC = 0 -// bits[30:28] Xbar2SriFreeListCBInc = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // greater than 4, ex. 6. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00090A16, // regData - 0x707FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 23 -// bits[11:8] Sri2XbarFreeXreqCBC = 9 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 9 -// bits[22:20] Sri2XbarFreeRspDBC = 0 -// bits[30:28] Xbar2SriFreeListCBInc = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Cx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00090917, // regData - 0x707FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 23 -// bits[11:8] Sri2XbarFreeXreqCBC = 9 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 9 -// bits[22:20] Sri2XbarFreeRspDBC = 0 -// bits[30:28] Xbar2SriFreeListCBInc = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE), // 4 or fewer cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00090917, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 21 -// bits[11:8] Sri2XbarFreeXreqCBC = 9 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 9 -// bits[22:20] Sri2XbarFreeRspDBC = 0 -// bits[30:28] Xbar2SriFreeListCBInc = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // greater than 4, ex. 6. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00090915, // regData - 0x707FFF1F, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 1 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 0 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 0 -// bits[23:20] FreeTok = A - { - ProcCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | PROCESSOR_RANGE_1 (3, COUNT_RANGE_HIGH)), // anything but two. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00A00755, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 1 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 0 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 0 -// bits[23:20] FreeTok = 8 - { - ProcCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // exactly two. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00800755, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 1 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 1 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 1 -// bits[23:20] FreeTok = 10 - { - TokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // 2 Socket, half populated. - PACKAGE_TYPE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00A11755, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 1 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 1 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 1 -// bits[23:20] FreeTok = 9 - { - TokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, - (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // 2 Socket, half populated. - PACKAGE_TYPE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00911755, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 1 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 1 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 1 -// bits[23:20] FreeTok = 5 - { - TokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // 2 Socket, fully populated. - PACKAGE_TYPE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00511755, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 1 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 1 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 1 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 1 -// bits[23:20] FreeTok = 7 - { - TokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, - (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // 2 Socket, fully populated. - PACKAGE_TYPE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00711555, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 1 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 1 -// bits[15:14] IsocPreqTok = ] -// bits[17:16] IsocRspTok = 1 -// bits[23:20] FreeTok = 8 - { - TokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // 4 Socket, half populated. - PACKAGE_TYPE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00811755, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 1 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 1 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 2 -// bits[23:20] FreeTok = 2 - { - TokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // 4 Socket, fully populated. - PACKAGE_TYPE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00211755, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 1 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 1 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 1 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 1 -// bits[23:20] FreeTok = 6 - { - TokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, - (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // 4 Socket, fully populated. - PACKAGE_TYPE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00611555, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 2 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 0 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 0 -// bits[23:20] FreeTok = 8 - { - TokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_C32_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), - PACKAGE_TYPE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00800756, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 2 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 1 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 1 -// bits[23:20] FreeTok = 8 - { - TokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_C32_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), - PACKAGE_TYPE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00811756, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 3 -// bits[7:4] ProbeTok = 3 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000033, // regData - 0x000000FF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 5 -// bits[7:4] ProbeTok = 1 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000015, // regData - 0x000000FF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// All non probe filter configs -// bits[3:0] RspTok = 3 -// bits[7:4] ProbeTok = 3 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000033, // regData - 0x000000FF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 4 -// bits[7:4] ProbeTok = 1 - { - TokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, // Features - (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | DEGREE_RANGE_1 (4, COUNT_RANGE_HIGH)), // 2 Socket, half populated, or 4 Socket, fully populated. - PACKAGE_TYPE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000014, // regData - 0x000000FF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 5 -// bits[7:4] ProbeTok = 1 - { - TokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, // Features - (DEGREE_RANGE_0 (2, 2) | DEGREE_RANGE_1 (3, 3)), // 2 Socket, fully populated, or 4 Socket, half populated. - PACKAGE_TYPE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000015, // regData - 0x000000FF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 5 -// bits[7:4] ProbeTok = 1 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_C32_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000015, // regData - 0x000000FF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 0 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - HT_HOST_FEAT_GANGED, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x000000AA, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - HT_HOST_FEAT_UNGANGED, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x00550055, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - HT_HOST_FEAT_UNGANGED, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x00550055, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 0 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 1 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - HT_HOST_FEAT_UNGANGED, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x00554055, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - HT_HOST_FEAT_NONCOHERENT, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000012A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x000001A6, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE), - PERFORMANCE_PROBEFILTER, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000016A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 1 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 1 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x01550155, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 1 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 1 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x01550155, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 2 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - HT_HOST_FEAT_NONCOHERENT, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000022A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 1 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 1 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x01554155, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x000001A6, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 =1 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), - PERFORMANCE_PROBEFILTER, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x00000196, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 0 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 3 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_C32_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) }, // platformFeatures - {{ - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - HT_HOST_FEATURES_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000C0AA, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 2 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_C32_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - HT_HOST_FEAT_NONCOHERENT, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000812A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 2 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_C32_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) }, // platformFeatures - {{ - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), - PERFORMANCE_PROFILE_ALL, - HT_HOST_FEAT_COHERENT, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x000081AA, // regData - 0xD5FFFFFF, // regMask - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable = { - PrimaryCores, - (sizeof (F10MultiLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F10MultiLinkPciRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PackageType.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PackageType.h deleted file mode 100644 index b8a3fe2019..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PackageType.h +++ /dev/null @@ -1,84 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Package Type Definitions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _F10_PACKAGE_TYPE_H_ -#define _F10_PACKAGE_TYPE_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - -// Below equates are defined to cooperate with LibAmdGetPackageType. -#define PACKAGE_TYPE_FR2_FR5_FR6 (1 << 0) -#define PACKAGE_TYPE_AM2R2_AM3 (1 << 1) -#define PACKAGE_TYPE_S1G3_S1G4 (1 << 2) -#define PACKAGE_TYPE_G34 (1 << 3) -#define PACKAGE_TYPE_ASB2 (1 << 4) -#define PACKAGE_TYPE_C32 (1 << 5) - -#define PACKAGE_TYPE_FR2 PACKAGE_TYPE_FR2_FR5_FR6 -#define PACKAGE_TYPE_FR5 PACKAGE_TYPE_FR2_FR5_FR6 -#define PACKAGE_TYPE_FR6 PACKAGE_TYPE_FR2_FR5_FR6 -#define PACKAGE_TYPE_S1G3 PACKAGE_TYPE_S1G3_S1G4 -#define PACKAGE_TYPE_S1G4 PACKAGE_TYPE_S1G3_S1G4 - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -#endif // _F10_PACKAGE_TYPE_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c deleted file mode 100644 index 8c31a4ded2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c +++ /dev/null @@ -1,176 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Asymmetric Boost Initialization - * - * Performs the "BIOS Configuration for Asymmetric Boost" as - * described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF10PowerMgmt.h" -#include "F10PmAsymBoostInit.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -SetAsymBoost ( - IN VOID *AsymBoostRegister, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 10h core 0 entry point for performing the "Asymmetric Boost - * Configuration" algorithm. - * - * The algorithm is as follows: - * // Determine whether the processor support boost - * if (CPUID CPUID Fn8000_0007[CPB]==1)&& CPUID Fn8000_0008[NC]==5) { - * Core0 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore0] - * Core1 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore1] - * Core2 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore2] - * Core3 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore3] - * Core4 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore4] - * Core5 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore5] - * } - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service related parameters (unused). - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F10PmAsymBoostInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - CPUID_DATA CpuidData; - - // Check if CPB is supported. if yes, skip boosted p-state. - LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader); - if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) { - LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuidData, StdHeader); - if ((CpuidData.ECX_Reg & 0x000000FF) == 5) { - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - // Read F3x10C [Boost Offset] - PciAddress.AddressValue = F3x10C_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - TaskPtr.FuncAddress.PfApTaskI = SetAsymBoost; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.DataTransfer.DataSizeInDwords = 1; - TaskPtr.DataTransfer.DataPtr = &LocalPciRegister; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set Asymmetric Boost. - * - * This function set Asymmetric Boost. - * - * @param[in] AsymBoostRegister Contains the value of Asymmetric Boost register - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -SetAsymBoost ( - IN VOID *AsymBoostRegister, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 ControlByte; - UINT32 Core; - UINT32 Ignored; - UINT64 MsrValue; - AGESA_STATUS IgnoredSts; - - IdentifyCore (StdHeader, &Ignored, &Ignored, &Core, &IgnoredSts); - ControlByte = (UINT8) ((Core & 0xFF) * 2); - LibAmdMsrRead (MSR_PSTATE_0, &MsrValue, StdHeader); - // Bits 5:0 - ((PSTATE_MSR *) &MsrValue)->CpuFid += ((*(UINT32*) AsymBoostRegister >> ControlByte) & 0x3); - LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader); -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h deleted file mode 100644 index d03d676a81..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h +++ /dev/null @@ -1,78 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Asymmetric Boost Initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F10_ASYM_BOOST_H_ -#define _CPU_F10_ASYM_BOOST_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F10PmAsymBoostInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F10_ASYM_BOOST_H_ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c deleted file mode 100644 index 0fc1631ca6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c +++ /dev/null @@ -1,243 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Dual-plane Only Support - * - * Performs the "BIOS Configuration for Dual-plane Only Support" as - * described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF10PowerMgmt.h" -#include "F10PmDualPlaneOnlySupport.h" -#include "F10PackageType.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT32 -STATIC -SetPstateMSR ( - IN VOID *CPB, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 10h core 0 entry point for performing the "Dual-plane Only Support" algorithm. - * - * The algorithm is as follows: - * // Determine whether algorithm applies to this processor - * if (CPUID Fn8000_0001_EBX[PkgType] == 0001b && (revision C or E) { - * // Determine whether processor is supported in this infrastructure - * if (((F3x1FC[DualPlaneOnly] == 1) && (this is a dual-plane platform)) - * || ((F3x1FC[AM3r2Only] == 1) && (this is an AM3r2 platform))) { - * // Fixup the P-state MSRs - * for (each core in the system) { - * if (CPUID Fn8000_0007[CPB]) { - * Copy MSRC001_0065 as MinPstate; - * Copy MSRC001_0068 to MSRC001_0065; - * Copy MinPstate to MSRC001_0068; - * } else { - * Copy MSRC001_0068 to MSRC001_0064; - * Program MSRC001_0068 = 0; - * } // endif - * for (each MSR in MSRC001_00[68:64]) { - * if (value in MSRC001_00[68:64][IddValue] != 0) { - * Set PstateEn in current MSR to 1; - * } // endif - * } // endfor - * } // endfor - * Set F3xDC[PstateMaxVal] = lowest-performance enabled P-state; - * Set F3xA8[PopDownPstate] = lowest-performance enabled P-state; - * Set F3x64[HtcPstateLimit] = lowest-performance enabled P-state; - * } // endif - * } // endif - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service related parameters (unused). - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F10PmDualPlaneOnlySupport ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - UINT32 CPB; - UINT32 Core; - UINT32 Pvimode; - UINT32 LowestPsEn; - UINT32 LocalPciRegister; - UINT32 ActiveCores; - UINT32 ProcessorPackageType; - PCI_ADDR PciAddress; - CPUID_DATA CpuidData; - CPU_LOGICAL_ID LogicalId; - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - - // get the package type - ProcessorPackageType = LibAmdGetPackageType (StdHeader); - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - if (((LogicalId.Revision & (AMD_F10_Cx | AMD_F10_Ex)) != 0) && ((ProcessorPackageType & PACKAGE_TYPE_AM2R2_AM3) != 0)) { - PciAddress.AddressValue = PRCT_INFO_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &Pvimode, StdHeader); - if ((((LocalPciRegister & 0x80000000) != 0) && (((POWER_CTRL_MISC_REGISTER *) &Pvimode)->PviMode == 0)) - || ((LocalPciRegister & 0x04000000) != 0)) { - CPB = 0; - LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader); - if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) { - CPB = 1; - } - - TaskPtr.FuncAddress.PfApTaskIO = SetPstateMSR; - TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.DataTransfer.DataSizeInDwords = 1; - TaskPtr.DataTransfer.DataPtr = &CPB; - - GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader); - for (Core = 1; Core < (UINT8) ActiveCores; ++Core) { - ApUtilRunCodeOnSocketCore ((UINT8)0, (UINT8)Core, &TaskPtr, StdHeader); - } - LowestPsEn = ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr); - - PciAddress.AddressValue = CPTC2_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = LowestPsEn; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((POPUP_PSTATE_REGISTER *) &LocalPciRegister)->PopDownPstate = LowestPsEn; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - PciAddress.AddressValue = HTC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit = LowestPsEn; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } -} -/*---------------------------------------------------------------------------------------*/ -/** - * Set P-State MSR. - * - * This function set the P-state MSRs per each core in the system. - * - * @param[in] CPB Contains the value of Asymmetric Boost register - * @param[in] StdHeader Config handle for library and services - * - * @return Return the lowest-performance enabled P-state - */ -UINT32 -STATIC -SetPstateMSR ( - IN VOID *CPB, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 dtemp; - UINT32 LowestPsEn; - UINT64 MsrValue; - UINT64 MinMsrValue; - - if (*(UINT32*) CPB != 0) { - LibAmdMsrRead (MSR_PSTATE_1, &MinMsrValue, StdHeader); - LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader); - LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader); - LibAmdMsrWrite (MSR_PSTATE_4, &MinMsrValue, StdHeader); - } else { - LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader); - LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader); - MsrValue = 0; - LibAmdMsrWrite (MSR_PSTATE_4, &MsrValue, StdHeader); - } - - LowestPsEn = 0; - for (dtemp = MSR_PSTATE_0; dtemp <= MSR_PSTATE_4; dtemp++) { - LibAmdMsrRead (dtemp, &MsrValue, StdHeader); - if (((PSTATE_MSR *) &MsrValue)->IddValue != 0) { - MsrValue = MsrValue | BIT63; - LibAmdMsrWrite (dtemp, &MsrValue, StdHeader); - LowestPsEn = dtemp - MSR_PSTATE_0; - } - } - return (LowestPsEn); -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h deleted file mode 100644 index 53ba3995a7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h +++ /dev/null @@ -1,78 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 BIOS Configuration for Dual-plane Only Support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_ -#define _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F10PmDualPlaneOnlySupport ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c deleted file mode 100644 index 515484cfdf..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c +++ /dev/null @@ -1,296 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 NB COF VID Initialization - * - * Performs the "BIOS Northbridge COF and VID Configuration" as - * described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuF10PowerMgmt.h" -#include "cpuApicUtilities.h" -#include "OptionMultiSocket.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF10Utilities.h" -#include "F10PmNbCofVidInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/// Structure used for performing the steps outlined in -/// the NB COFVID configuration sequence -typedef struct { - UINT8 NewNbVid; ///< Destination NB VID code - BOOLEAN NbVidUpdateAll; ///< Status of NbVidUpdateAll -} NB_COF_VID_INIT_WARM; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -PmNbCofVidInitP0P1Core ( - IN VOID *NewNbVid, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -PmNbCofVidInitWarmCore ( - IN VOID *FunctionData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 10h core 0 entry point for performing the "Northbridge COF and - * VID Configuration" algorithm. - * - * The steps are as follows: - * 1. Determine if the algorithm is necessary by checking if all NB FIDs - * match in the coherent fabric. If so, check to see if NbCofVidUpdate - * is zero for all CPUs. If that is also true, no further steps are - * necessary. If not + cold reset, proceed to step 2. If not + warm - * reset, proceed to step 8. - * 2. Determine NewNbVid & NewNbFid. - * 3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores. - * 4. Copy NewNbVid to P0 NbVid on all local cores. - * 5. Transition to P1 on all local cores. - * 6. Transition to P0 on local core 0 only. - * 7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset. - * 8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll - * on all local cores. - * 9. Transition to Startup Pstate on all local cores. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service related parameters (unused). - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F10PmNbCofVidInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN PerformNbCofVidCfg; - BOOLEAN NotUsed; - BOOLEAN SystemNbCofsMatch; - UINT8 NewNbFid; - UINT8 NewNbVid; - UINT32 Core; - UINT32 SystemNbCof; - UINT32 AndMask; - UINT32 OrMask; - UINT32 Ignored; - UINT32 NewNbVoltage; - UINT32 FrequencyDivisor; - WARM_RESET_REQUEST Request; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - NB_COF_VID_INIT_WARM FunctionData; - - PerformNbCofVidCfg = TRUE; - OptionMultiSocketConfiguration.GetSystemNbPstateSettings ((UINT32) 0, &CpuEarlyParamsPtr->PlatformConfig, &SystemNbCof, &FrequencyDivisor, &SystemNbCofsMatch, &NotUsed, StdHeader); - if (SystemNbCofsMatch) { - if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) { - PerformNbCofVidCfg = FALSE; - } - } - if (PerformNbCofVidCfg) { - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - - GetCurrentCore (&Core, StdHeader); - ASSERT (Core == 0); - - // get NewNbVid - FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, - &CpuEarlyParamsPtr->PlatformConfig, - &PciAddress, - (UINT32) 0, - &Ignored, - &Ignored, - &NewNbVoltage, - StdHeader); - ASSERT (((1550000 - NewNbVoltage) % 12500) == 0); - NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500); - ASSERT (NewNbVid < 0x80); - - if (!(IsWarmReset (StdHeader))) { - - // determine NewNbFid - NewNbFid = (UINT8) ((SystemNbCof / 200) - 4); - - TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core; - TaskPtr.DataTransfer.DataSizeInDwords = 1; - TaskPtr.DataTransfer.DataPtr = &NewNbVid; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = 0; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - - // Transition core 0 to P0 and wait for change to complete - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); - - PciAddress.Address.Register = CPTC0_REG; - AndMask = 0xFFFFFFFF; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0; - OrMask = 0x00000000; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - // warm reset request - GetWarmResetFlag (StdHeader, &Request); - Request.RequestBit = TRUE; - Request.StateBits = Request.PostStage - 1; - SetWarmResetFlag (StdHeader, &Request); - } else { - // warm reset path - - FunctionData.NewNbVid = NewNbVid; - FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader); - - TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM); - TaskPtr.DataTransfer.DataPtr = &FunctionData; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - } - } // skip whole algorithm -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Cold reset support routine for F10PmNbCofVidInit. - * - * This function implements steps 3, 4, & 5 on each core. - * - * @param[in] NewNbVid NewNbVid determined by core 0 in step 2. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -PmNbCofVidInitP0P1Core ( - IN VOID *NewNbVid, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - UINT32 MsrAddress; - UINT64 LocalMsrRegister; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - NumBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader); - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &LocalMsrRegister)->StartupPstate) + PS_REG_BASE); - LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader); - LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1 + NumBoostStates), &LocalMsrRegister, StdHeader); - ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = *(UINT8 *) NewNbVid; - LibAmdMsrWrite (PS_REG_BASE + NumBoostStates, &LocalMsrRegister, StdHeader); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Warm reset support routine for F10PmNbCofVidInit. - * - * This function implements steps 8 & 9 on each core. - * - * @param[in] FunctionData Contains NewNbVid determined by core 0 in step - * 2, and NbVidUpdateAll. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -PmNbCofVidInitWarmCore ( - IN VOID *FunctionData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MsrAddress; - UINT64 LocalMsrRegister; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) { - LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->IddValue != 0) { - if ((((PSTATE_MSR *) &LocalMsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) { - ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid; - LibAmdMsrWrite (MsrAddress, &LocalMsrRegister, StdHeader); - } - } - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h deleted file mode 100644 index 94aad6dcf8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 NB COF VID Initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F10_PM_NB_COF_VID_INIT_H_ -#define _CPU_F10_PM_NB_COF_VID_INIT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F10PmNbCofVidInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F10_PM_NB_COF_VID_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c deleted file mode 100644 index bf3f4bd6e4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c +++ /dev/null @@ -1,185 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 NB Pstate Initialization - * - * Performs the action described in F3x1F0[NbPstate] as - * described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuF10PowerMgmt.h" -#include "cpuApicUtilities.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "F10PmNbPstateInit.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/// Structure used for modifying the P-state -/// MSRs on fuse enable CPUs. -typedef struct { - UINT8 NbVid1; ///< Destination NB VID code - UINT8 NbPstate; ///< Status of NbVidUpdateAll -} NB_PSTATE_INIT; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -PmNbPstateInitCore ( - IN VOID *NbPstateParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 10h core 0 entry point for performing the actions described in the - * description of F3x1F0[NbPstate]. - * - * If F3x1F0[NbPstate] is non zero, it specifies the highest performance - * P-state in which to enable NbDid. Each core must loop through their - * P-state MSRs, enabling NbDid and changing NbVid to a lower voltage. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service related parameters (unused). - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F10PmNbPstateInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Core; - UINT32 LocalPciRegister; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - NB_PSTATE_INIT ApParams; - - if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) { - if (CpuEarlyParamsPtr->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife) { - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - GetCurrentCore (&Core, StdHeader); - ASSERT (Core == 0); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x1F0; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & 0x00070000) != 0) { - ApParams.NbPstate = (UINT8) ((LocalPciRegister & 0x00070000) >> 16); - ASSERT (ApParams.NbPstate < NM_PS_REG); - - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = 0x1F4; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ApParams.NbVid1 = (UINT8) ((LocalPciRegister & 0x00003F80) >> 7); - - TaskPtr.FuncAddress.PfApTaskI = PmNbPstateInitCore; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_PSTATE_INIT); - TaskPtr.DataTransfer.DataPtr = &ApParams; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - - } - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F10PmNbPstateInit. - * - * This function modifies NbVid and NbDid on each core. - * - * @param[in] NbPstateParams Appropriate NbVid1 and NbPstate as determined by core 0. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -PmNbPstateInitCore ( - IN VOID *NbPstateParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MsrAddress; - UINT64 LocalMsrRegister; - - for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) { - LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - ((PSTATE_MSR *) &LocalMsrRegister)->NbDid = 1; - ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1; - LibAmdMsrWrite (MsrAddress, &LocalMsrRegister, StdHeader); - } - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.h deleted file mode 100644 index 1701ee4ea0..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 NB P-State Initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F10_PM_NB_PSTATE_INIT_H_ -#define _CPU_F10_PM_NB_PSTATE_INIT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F10PmNbPstateInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F10_PM_NB_PSTATE_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c deleted file mode 100644 index 7a3a3ec6eb..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c +++ /dev/null @@ -1,2251 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 PCI tables in Recommended Settings for Single Link Processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x10 - * @e \$Revision: 59564 $ @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10SingleLinkPciRegisters[] = -{ -// F0x68 - Link Transaction Control -// bit[14:13], BufPriRel = 01b - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x00002000, // regData - 0x00006000, // regMask - }} - }, -// F0x68 - Link Transaction Control -// bit[24], DispRefModeEn = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x00000000, // regData - 0x01000000, // regMask - }} - }, -// F0x68 - Link Transaction Control -// bit[24], DispRefModeEn = 1 for UMA, but can only set it on the warm reset. - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_UMA}, // platform Features - {{ - PERFORMANCE_IS_WARM_RESET, - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x01000000, // regData - 0x01000000, // regMask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 2 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 1 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 4 - // 4:0 NpReqCmd: 18 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, - {{ - HT_HOST_FEATURES_ALL, // Link Features - 0x10, // Address - 0x04850292, // Data - 0x0FFFFFFF // Mask - }}, - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 2 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 1 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 4 - // 4:0 NpReqCmd: 18 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, - {{ - HT_HOST_FEATURES_ALL, // Link Features - 0x10, // Address - 0x04850292, // Data - 0x0FFFFFFF // Mask - }}, - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 2 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 1 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 3 - // 4:0 NpReqCmd: 11 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, - {{ - HT_HOST_FEATURES_ALL, // Link Features - 0x10, // Address - 0x0485026B, // Data - 0x0FFFFFFF // Mask - }}, - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 2 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 1 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 6 - // 4:0 NpReqCmd: 15 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, - {{ - HT_HOST_FEATURES_ALL, // Link Features - 0x10, // Address - 0x008502CF, // Data - 0x0FFFFFFF // Mask - }}, - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 1 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 6 - // 4:0 NpReqCmd: 15 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, - {{ - HT_HOST_FEATURES_ALL, // Link Features - 0x10, // Address - 0x808502CF, // Data - 0x0FFFFFFF // Mask - }}, - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 0 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, - {{ - HT_HOST_FEATURES_ALL, // Link Features - 0x14, // Address - 0x00000000, // Data - 0x1FFF0000 // Mask - }}, - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 0 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, - {{ - HT_HOST_FEATURES_ALL, // Link Features - 0x14, // Address - 0x00000000, // Data - 0x1FFF0000 // Mask - }}, - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 1 - // 18:16 IsocNpReqCmd: 7 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, - {{ - HT_HOST_FEATURES_ALL, // Link Features - 0x14, // Address - 0x000F0000, // Data - 0x1FFF0000 // Mask - }}, - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 1 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, - {{ - HT_HOST_FEATURES_ALL, // Link Features - 0x14, // Address - 0x00010000, // Data - 0x1FFF0000 // Mask - }}, - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 1 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, - {{ - HT_HOST_FEATURES_ALL, // Link Features - 0x14, // Address - 0x00010000, // Data - 0x1FFF0000 // Mask - }}, - }, -// F0x170 - Link Extended Control Register - Link 0, sublink 0 -// bit[8] LS2En = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F2x118 - Memory Controller Configuration Low Register -// bits[13:12] MctPriIsoc = 10b -// bits[31:28] MctVarPriCntLmt = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_UMA | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address - 0x00002000, // regData - 0xF0003000, // regMask - }} - }, -// F2x118 - Memory Controller Configuration Low Register -// bits[13:12] MctPriIsoc = 00b -// bits[31:28] MctVarPriCntLmt = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address - 0x00000000, // regData - 0xF0000000, // regMask - }} - }, -// F2x118 - Memory Controller Configuration Low Register -// bits[13:12] MctPriIsoc = 11b -// bits[31:28] MctVarPriCntLmt = 1 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_UMA | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address - 0x10003000, // regData - 0xF0003000, // regMask - }} - }, -// F2x[1,0]90 - DRAM Configuration Low Register -// bits [10] BurstLength32 0 -// It is okay to write both channels, if one is disabled, this bit has no effect on that channel. -// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting. - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_UMA | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90), // Address - 0x00000000, // regData - 0x00000400, // regMask - }} - }, -// F2x[1,0]90 - DRAM Configuration Low Register -// bits [10] BurstLength32 = 0 -// It is okay to write both channels, if one is disabled, this bit has no effect on that channel. -// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting. - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_UMA | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190), // Address - 0x00000000, // regData - 0x00000400, // regMask - }} - }, -// F2x[1,0]90 - DRAM Configuration Low Register -// bits [10] BurstLength32 = 1 -// It is okay to write both channels, if one is disabled, this bit has no effect on that channel. -// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting. - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_UMA | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90), // Address - 0x00000400, // regData - 0x00000400, // regMask - }} - }, -// F2x[1,0]90 - DRAM Configuration Low Register -// bits [10] BurstLength32 = 1 -// It is okay to write both channels, if one is disabled, this bit has no effect on that channel. -// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting. - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_UMA | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190), // Address - 0x00000400, // regData - 0x00000400, // regMask - }} - }, -// F3x6C - Data Buffer Control -// bits[2:0] UpReqDBC = 2 -// bits[5:4] DnReqDBC = 1 -// bits[7:6] DnRspDBC = 1 -// bit[15] DatBuf24 = 1 -// bits[18:16] UpRspDBC = 1 -// bits[30:28] IsocRspDBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address - 0x00018052, // regData - 0x700780F7, // regMask - }} - }, -// F3x6C - Data Buffer Control -// bits[2:0] UpReqDBC = 1 -// bits[5:4] DnReqDBC = 1 -// bits[7:6] DnRspDBC = 1 -// bit[15] DatBuf24 = 1 -// bits[18:16] UpRspDBC = 1 -// bits[30:28] IsocRspDBC = 6 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address - 0x60018051, // regData - 0x700780F7, // regMask - }} - }, -// F3x6C - Data Buffer Control -// bits[2:0] UpReqDBC = 2 -// bits[5:4] DnReqDBC = 1 -// bits[7:6] DnRspDBC = 1 -// bit[15] DatBuf24 = 1 -// bits[18:16] UpRspDBC = 1 -// bits[30:28] IsocRspDBC = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address - 0x10018052, // regData - 0x700780F7, // regMask - }} - }, -// F3x6C - Data Buffer Control -// bits[2:0] UpReqDBC = 1 -// bits[5:4] DnReqDBC = 1 -// bits[7:6] DnRspDBC = 1 -// bit[15] DatBuf24 = 1 -// bits[18:16] UpRspDBC = 1 -// bits[30:28] IsocRspDBC = 6 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address - 0x60018051, // regData - 0x700780F7, // regMask - }} - }, -// F3x6C - Data Buffer Control -// bits[2:0] UpReqDBC = 2 -// bits[5:4] DnReqDBC = 1 -// bits[7:6] DnRspDBC = 1 -// bit[15] DatBuf24 = 1 -// bits[18:16] UpRspDBC = 1 -// bits[30:28] IsocRspDBC = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address - 0x10018052, // regData - 0x700780F7, // regMask - }} - }, -// F3x70 - SRI_to_XBAR Command Buffer Count -// bits[2:0] UpReqCBC = 3 -// bits[5:4] DnReqCBC = 1 -// bits[7:6] DnRspCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 1 -// bits[18:16] UpRspCBC = 4 -// bits[22:20] IsocReqCBC = 0 -// bits[26:24] IsocPreqCBC = 0 -// bits[30:28] IsocRspCBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address - 0x00041153, // regData - 0x777777F7, // regMask - }} - }, -// F3x70 - SRI_to_XBAR Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[5:4] DnReqCBC = 1 -// bits[7:6] DnRspCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 1 -// bits[18:16] UpRspCBC = 2 -// bits[22:20] IsocReqCBC = 2 -// bits[26:24] IsocPreqCBC = 1 -// bits[30:28] IsocRspCBC = 6 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address - 0x61221151, // regData - 0x777777F7, // regMask - }} - }, -// F3x70 - SRI_to_XBAR Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[5:4] DnReqCBC = 1 -// bits[7:6] DnRspCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 1 -// bits[18:16] UpRspCBC = 2 -// bits[22:20] IsocReqCBC = 2 -// bits[26:24] IsocPreqCBC = 1 -// bits[30:28] IsocRspCBC = 6 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address - 0x61221151, // regData - 0x777777F7, // regMask - }} - }, -// F3x70 - SRI_to_XBAR Command Buffer Count -// bits[2:0] UpReqCBC = 3 -// bits[5:4] DnReqCBC = 1 -// bits[7:6] DnRspCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 1 -// bits[18:16] UpRspCBC = 4 -// bits[22:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[30:28] IsocRspCBC = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address - 0x11141153, // regData - 0x777777F7, // regMask - }} - }, -// F3x70 - SRI_to_XBAR Command Buffer Count -// bits[2:0] UpReqCBC = 3 -// bits[5:4] DnReqCBC = 1 -// bits[7:6] DnRspCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 1 -// bits[18:16] UpRspCBC = 5 -// bits[22:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 0 -// bits[30:28] IsocRspCBC = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address - 0x10151153, // regData - 0x777777F7, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 1 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 0 -// bits[26:24] IsocPreqCBC = 0 -// bits[31:28] DRReqCBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x00081111, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = 9 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x91180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = 9 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x91180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC =1 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 0 -// bits[31:28] DRReqCBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x00181111, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = 8 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_PROFILE_ALL, // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x81180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = 8 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_PROFILE_ALL, // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x81180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = 7 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_PROFILE_ALL, // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x71180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = 7 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_PROFILE_ALL, // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x71180101, // regData - 0xF7FF7777, // regMask - }} - }, - -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = C - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xC1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = C - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xC1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = B - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xB1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = A - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xA1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = B - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xB1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = A - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xA1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = F - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xF1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = F - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xF1181111, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = B - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xB1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = B - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xB1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = A - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xA1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = A - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xA1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = E - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xE1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = E - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xE1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = D - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xD1180101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 1 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = D - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0xD1180101, // regData - 0xF7FF7777, // regMask - }} - }, - -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[2:0] UpReqCBC = 1 -// bits[6:4] DnReqCBC = 0 -// bits[10:8] UpPreqCBC = 1 -// bits[14:12] DnPreqCBC = 0 -// bits[19:16] ProbeCBC = 8 -// bits[23:20] IsocReqCBC = 8 -// bits[26:24] IsocPreqCBC = 1 -// bits[31:28] DRReqCBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x01880101, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 20 -// bits[11:8] Sri2XbarFreeXreqCBC = 9 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 9 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00090914, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[4:0] Xbar2SriFreeListCBC = 15 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080F, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[4:0] Xbar2SriFreeListCBC = 15 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080F, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 12 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080C, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 12 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080C, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 9 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00070809, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 9 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B , // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00070809, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 17 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00070811, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 20 -// bits[11:8] Sri2XbarFreeXreqCBC = 9 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 9 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00090914, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[4:0] Xbar2SriFreeListCBC = 14 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_PROFILE_ALL, - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080E, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[4:0] Xbar2SriFreeListCBC = 14 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_PROFILE_ALL, - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080E, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[4:0] Xbar2SriFreeListCBC = 13 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_PROFILE_ALL, - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080D, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// No Mct Variable Priority or 32 byte requests. -// bits[4:0] Xbar2SriFreeListCBC = 13 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_PROFILE_ALL, - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080D, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 11 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080B, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 11 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080B, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 10 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080A, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 10 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080A, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 8 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00070808, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 8 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B , // Features - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00070808, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 7 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B, // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00070807, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 7 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_REFRESH_REQUEST_32B , // Features - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00070807, // regData - 0x007FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 16 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features - {{ - PERFORMANCE_PROFILE_ALL, - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00070810, // regData - 0x707FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 15 -// bits[11:8] Sri2XbarFreeXreqCBC = 8 -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 7 -// bits[22:20] Sri2XbarFreeRspDBC = 0 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features - {{ - PERFORMANCE_PROFILE_ALL, - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0007080F, // regData - 0x707FFF1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 22, 1-core without L3 cache is 22 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platformFeatures - {{ - PERFORMANCE_NO_L3_CACHE, - (CORE_RANGE_0 (1, 1) | COUNT_RANGE_NONE), // 1 core. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00000016, // regData - 0x0000001F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 20, 2-core is 20 - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platformFeatures - {{ - PERFORMANCE_NO_L3_CACHE, - (CORE_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // 2 core. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00000014, // regData - 0x0000001F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 18, 3-core without L3 cache is 18. - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platformFeatures - {{ - PERFORMANCE_NO_L3_CACHE, - (CORE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // 3 core. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00000012, // regData - 0x0000001F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 14, 4-core without L3 cache is 16. - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platformFeatures - {{ - PERFORMANCE_NO_L3_CACHE, - (CORE_RANGE_0 (4, 4) | COUNT_RANGE_NONE), // 4 core. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00000010, // regData - 0x0000001F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 14, 5-core without L3 cache is 14. - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platformFeatures - {{ - PERFORMANCE_NO_L3_CACHE, - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0000000E, // regData - 0x0000001F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 12, 6-core without L3 cache is 12. - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platformFeatures - {{ - PERFORMANCE_NO_L3_CACHE, - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x0000000C, // regData - 0x0000001F, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 2 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 0 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 0 -// bits[23:20] FreeTok = 8 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00800756, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 2 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 3 -// bits[15:14] IsocPreqTok = 1 -// bits[17:16] IsocRspTok = 3 -// bits[23:20] FreeTok = 12 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00C37756, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 2 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 3 -// bits[15:14] IsocPreqTok = 1 -// bits[17:16] IsocRspTok = 3 -// bits[23:20] FreeTok = 12 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00C37756, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 2 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 2 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 3 -// bits[15:14] IsocPreqTok = 1 -// bits[17:16] IsocRspTok = 3 -// bits[23:20] FreeTok = 12 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00C37656, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 2 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTokC = 1 -// bits[7:6] DnPreqTok = 1 -// bits[9:8] UpRspTok = 3 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 1 -// bits[15:14] IsocPreqTok = 1 -// bits[17:16] IsocRspTok = 1 -// bits[23:20] FreeTok = 8 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00815756, // regData - 0x00F3FFFF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 3 -// bits[7:4] ProbeTok = 3 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000033, // regData - 0x000000FF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 6 -// bits[7:4] ProbeTok = 3 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000036, // regData - 0x000000FF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 6 -// bits[7:4] ProbeTok = 3 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000036, // regData - 0x000000FF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 6 -// bits[7:4] ProbeTok = 3 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000036, // regData - 0x000000FF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 3 -// bits[7:4] ProbeTok = 3 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000033, // regData - 0x000000FF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 0 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 3 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000C0AA, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 1 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 2 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x8000052A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 1 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 2 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x8000052A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 0 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 3 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000C0AA, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 1 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 2 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 3 -// bits[24] IsocReqTok1 = 0 -// bits[25] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0500852A, // regData - 0xC000FFFF, // regMask - }} - }, - // F3x158 - Link to XCS Token Count Registers - // bits [3:0]LnkToXcsDRToken = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_NFCM | AMD_PF_IFCM | AMD_PF_IOMMU) }, - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address - 0x00000000, - 0x0000000F - }} - }, - // F3x158 - Link to XCS Token Count Registers - // bits [3:0]LnkToXcsDRToken = 3 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_UMA_IFCM | AMD_PF_UMA) }, - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address - 0x00000003, - 0x0000000F - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable = { - PrimaryCores, - (sizeof (F10SingleLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F10SingleLinkPciRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/Makefile.inc deleted file mode 100644 index 75f7c1ccd4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/Makefile.inc +++ /dev/null @@ -1,34 +0,0 @@ -libagesa-y += F10InitEarlyTable.c -libagesa-y += F10IoCstate.c -libagesa-y += F10MultiLinkPciTables.c -libagesa-y += F10PmAsymBoostInit.c -libagesa-y += F10PmDualPlaneOnlySupport.c -libagesa-y += F10PmNbCofVidInit.c -libagesa-y += F10PmNbPstateInit.c -libagesa-y += F10SingleLinkPciTables.c -libagesa-y += cpuCommonF10Utilities.c -libagesa-y += cpuF10BrandId.c -libagesa-y += cpuF10BrandIdAm3.c -libagesa-y += cpuF10BrandIdAsb2.c -libagesa-y += cpuF10BrandIdC32.c -libagesa-y += cpuF10BrandIdFr1207.c -libagesa-y += cpuF10BrandIdG34.c -libagesa-y += cpuF10BrandIdS1g3.c -libagesa-y += cpuF10BrandIdS1g4.c -libagesa-y += cpuF10CacheDefaults.c -libagesa-y += cpuF10CacheFlushOnHalt.c -libagesa-y += cpuF10Cpb.c -libagesa-y += cpuF10Dmi.c -libagesa-y += cpuF10EarlyInit.c -libagesa-y += cpuF10FeatureLeveling.c -libagesa-y += cpuF10HtPhyTables.c -libagesa-y += cpuF10MsrTables.c -libagesa-y += cpuF10PciTables.c -libagesa-y += cpuF10PowerCheck.c -libagesa-y += cpuF10PowerMgmtSystemTables.c -libagesa-y += cpuF10PowerPlane.c -libagesa-y += cpuF10Pstate.c -libagesa-y += cpuF10SoftwareThermal.c -libagesa-y += cpuF10Utilities.c -libagesa-y += cpuF10WheaInitDataTables.c -libagesa-y += cpuF10WorkaroundsTable.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c deleted file mode 100644 index 81e2c5820a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +++ /dev/null @@ -1,1039 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Microcode patch. - * - * Fam10 Microcode Patch rev 010000c5 for 1080 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x10/REVD - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -// Patch code 010000c5 for 1080 and equivalent -CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5 = -{{ -0x10, -0x20, -0x05, -0x03, -0xc5, -0x00, -0x00, -0x01, -0x00, -0x80, -0x20, -0x00, -0x83, -0xc5, -0x93, -0xcd, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x80, -0x10, -0x00, -0x00, -0x00, -0xaa, -0xaa, -0xaa, -0x89, -0x0b, -0x00, -0x00, -0x55, -0x03, -0x00, -0x00, -0xff, -0xff, -0xff, -0xff, -0x51, -0x03, -0x00, -0x00, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xff, -0xf8, -0xff, -0x2e, -0xc3, -0x3f, -0xd7, -0xfd, -0xac, -0xff, -0xff, -0xbb, -0x0f, -0xff, -0x5c, -0xd7, -0xf3, -0xdf, -0xfd, -0xc7, -0x3f, -0xfc, -0xe3, -0xf5, -0x00, -0x1d, -0xd5, -0x00, -0x00, -0xfd, -0xff, -0x7f, -0xfa, -0xe1, -0xd9, -0xca, -0x00, -0x66, -0xfa, -0x71, -0x80, -0x07, -0x7f, -0x40, -0x67, -0xd9, -0xff, -0xff, -0xde, -0x1d, -0x7e, -0xb1, -0x00, -0xe0, -0xff, -0x7b, -0x0e, -0x40, -0xbd, -0x55, -0xe0, -0x73, -0xd0, -0x0f, -0xff, -0x00, -0xe0, -0xff, -0x13, -0xf2, -0xc3, -0xbb, -0xff, -0x8b, -0xf8, -0xff, -0x44, -0x59, -0x0e, -0x7f, -0x34, -0x00, -0x10, -0x59, -0xfb, -0x07, -0xe0, -0xfb, -0xc7, -0x06, -0x38, -0xf0, -0xfe, -0x7f, -0x94, -0x9b, -0x1f, -0xe0, -0xe7, -0xe1, -0x03, -0xff, -0x00, -0xfe, -0x7f, -0x00, -0xff, -0x86, -0xff, -0x1e, -0x00, -0xe8, -0xff, -0x8c, -0x07, -0xf0, -0xf4, -0x43, -0xf9, -0x3c, -0x7e, -0x33, -0x0e, -0xc0, -0xd0, -0x0f, -0xe5, -0xf3, -0xf7, -0xcb, -0x38, -0x00, -0x43, -0x3f, -0x94, -0xcf, -0x0c, -0x94, -0x0c, -0x00, -0xf8, -0x0f, -0xfc, -0x03, -0x1b, -0xfe, -0x01, -0xfc, -0xe0, -0x3f, -0xf0, -0x0f, -0x6f, -0xf8, -0x07, -0xf0, -0x80, -0xff, -0xc0, -0x3f, -0xbf, -0xe1, -0x1f, -0xc0, -0x00, -0xfe, -0xbf, -0x07, -0x03, -0xf4, -0xff, -0xff, -0xc8, -0x0f, -0xef, -0x52, -0x4f, -0x30, -0xbf, -0xe0, -0xe0, -0x3a, -0xfc, -0x31, -0x0f, -0xc0, -0xd3, -0xd5, -0x0c, -0x70, -0xe0, -0xcf, -0x03, -0x00, -0xac, -0x5c, -0x7f, -0x00, -0xae, -0x97, -0x6c, -0x80, -0x03, -0x7f, -0xfe, -0x01, -0x78, -0x6e, -0xb1, -0x01, -0x0e, -0xfc, -0xf9, -0x07, -0xe0, -0xf7, -0xc7, -0x06, -0x38, -0xf0, -0x8b, -0x01, -0x80, -0x5f, -0x81, -0x7f, -0x00, -0xff, -0x3f, -0x80, -0x7f, -0xc3, -0x07, -0xfe, -0x01, -0xfc, -0xff, -0x00, -0xfe, -0x0d, -0x1f, -0xf8, -0x07, -0xf0, -0xfc, -0x03, -0xf8, -0x37, -0xff, -0xf7, -0x00, -0xc0, -0xff, -0xc0, -0x3f, -0x80, -0xe1, -0x1f, -0xc0, -0xbf, -0xfe, -0x03, -0xff, -0x00, -0x86, -0x7f, -0x00, -0xff, -0xf8, -0x0f, -0xfc, -0x03, -0x1b, -0xfe, -0x01, -0xfc, -0xe0, -0xff, -0x7b, -0x00, -0xc0, -0x7f, -0xe0, -0x1f, -0xdf, -0xf0, -0x0f, -0xe0, -0x00, -0xff, -0x81, -0x7f, -0x7f, -0xc3, -0x3f, -0x80, -0x01, -0xfc, -0x07, -0xfe, -0xfe, -0x0d, -0xff, -0x00, -0x00, -0xf0, -0xff, -0x3d, -0x0f, -0xe0, -0x3f, -0xf0, -0xf0, -0x6f, -0xf8, -0x07, -0x3f, -0x80, -0xff, -0xc0, -0xc0, -0xbf, -0xe1, -0x1f, -0xff, -0x00, -0xfe, -0x03, -0x00, -0xff, -0x86, -0x7f, -0x1e, -0x00, -0xf8, -0xff, -0xf8, -0x07, -0xf0, -0x1f, -0x03, -0xf8, -0x37, -0xfc, -0xe0, -0x1f, -0xc0, -0x7f, -0x0f, -0xe0, -0xdf, -0xf0, -0x81, -0x7f, -0x00, -0xff, -0x3f, -0x80, -0x7f, -0xc3, -0x7f, -0x0f, -0x00, -0xfc, -0x0f, -0xfc, -0x03, -0xf8, -0xfe, -0x01, -0xfc, -0x1b, -0x3f, -0xf0, -0x0f, -0xe0, -0xf8, -0x07, -0xf0, -0x6f, -0xff, -0xc0, -0x3f, -0x80, -0xe1, -0x1f, -0xc0, -0xbf, -0xfe, -0xbf, -0x07, -0x00, -0xfc, -0x07, -0xfe, -0x01, -0x0d, -0xff, -0x00, -0xfe, -0xf0, -0x1f, -0xf8, -0x07, -0x37, -0xfc, -0x03, -0xf8, -0xc0, -0x7f, -0xe0, -0x1f, -0xdf, -0xf0, -0x0f, -0xe0, -0x00, -0xff, -0xdf, -0x03, -0x00, -0xfe, -0x03, -0xff, -0xff, -0x86, -0x7f, -0x00, -0x03, -0xf8, -0x0f, -0xfc, -0xfc, -0x1b, -0xfe, -0x01, -0x0f, -0xe0, -0x3f, -0xf0, -0xf0, -0x6f, -0xf8, -0x07, -0x01, -0x80, -0xff, -0xef, -0x7f, -0x00, -0xff, -0x81, -0x80, -0x7f, -0xc3, -0x3f, -0xfe, -0x01, -0xfc, -0x07, -0x00, -0xfe, -0x0d, -0xff, -0xf8, -0x07, -0xf0, -0x1f, -0x03, -0xf8, -0x37, -0xfc, -0xd7, -0x00, -0x40, -0xf9, -0xc0, -0x3f, -0x80, -0xff, -0x1f, -0xc0, -0xbf, -0xe1, -0x03, -0xff, -0x00, -0xfe, -0x7f, -0x00, -0xff, -0x86, -0x0f, -0xfc, -0x03, -0xf8, -0xfe, -0x01, -0xfc, -0x1b, -0xfc, -0x6b, -0x00, -0x80, -0x7f, -0xe0, -0x1f, -0xc0, -0xf0, -0x0f, -0xe0, -0xdf, -0xff, -0x81, -0x7f, -0x00, -0xc3, -0x3f, -0x80, -0x7f, -0xfc, -0x07, -0xfe, -0x01, -0x0d, -0xff, -0x00, -0xfe, -0xf0, -0xff, -0x3d, -0x00, -0xe0, -0x3f, -0xf0, -0x0f, -0x6f, -0xf8, -0x07, -0xf0, -0x80, -0xff, -0xc0, -0x3f, -0xbf, -0xe1, -0x1f, -0xc0, -0x00, -0xfe, -0x03, -0xff, -0xff, -0x86, -0x7f, -0x00, -0x00, -0xf8, -0xff, -0x1e, -0x07, -0xf0, -0x1f, -0xf8, -0xf8, -0x37, -0xfc, -0x03, -0x1f, -0xc0, -0x7f, -0xe0, -0xe0, -0xdf, -0xf0, -0x0f, -0x7f, -0x00, -0xff, -0x81, -0x80, -0x7f, -0xc3, -0x3f, -0x0f, -0x00, -0xfc, -0x7f, -0xfc, -0x03, -0xf8, -0x0f, -0x01, -0xfc, -0x1b, -0xfe, -0xf0, -0x0f, -0xe0, -0x3f, -0x07, -0xf0, -0x6f, -0xf8, -0xc0, -0x3f, -0x80, -0xff, -0x1f, -0xc0, -0xbf, -0xe1, -0xbf, -0x07, -0x00, -0xfe, -0x07, -0xfe, -0x01, -0xfc, -0xff, -0x00, -0xfe, -0x0d, -0x1f, -0xf8, -0x07, -0xf0, -0xfc, -0x03, -0xf8, -0x37, -0x7f, -0xe0, -0x1f, -0xc0, -0xf0, -0x0f, -0xe0, -0xdf, -0xff, -0xdf, -0x03, -0x00, -0xfe, -0x03, -0xff, -0x00, -0x86, -0x7f, -0x00, -0xff, -0xf8, -0x0f, -0xfc, -0x03, -0x1b, -0xfe, -0x01, -0xfc, -0xe0, -0x3f, -0xf0, -0x0f, -0x6f, -0xf8, -0x07, -0xf0, -0x80, -0xff, -0xef, -0x01, -0x00, -0xff, -0x81, -0x7f, -0x7f, -0xc3, -0x3f, -0x80, -0x01, -0xfc, -0x07, -0xfe, -0xfe, -0x0d, -0xff, -0x00, -0x07, -0xf0, -0x1f, -0xf8, -0xf8, -0x37, -0xfc, -0x03, -0x00, -0xc0, -0xff, -0xf7, -0x3f, -0x80, -0xff, -0xc0, -0xc0, -0xbf, -0xe1, -0x1f, -0xff, -0x00, -0xfe, -0x03, -0x00, -0xff, -0x86, -0x7f, -0xfc, -0x03, -0xf8, -0x0f, -0x01, -0xfc, -0x1b, -0xfe, -0x7b, -0x00, -0xe0, -0xff, -0xe0, -0x1f, -0xc0, -0x7f, -0x0f, -0xe0, -0xdf, -0xf0, -0x81, -0x7f, -0x00, -0xff, -0x3f, -0x80, -0x7f, -0xc3, -0x07, -0xfe, -0x01, -0xfc, -0xff, -0x00, -0xfe, -0x0d, -0xff, -0x3d, -0x00, -0xf0, -0x3f, -0xf0, -0x0f, -0xe0, -0xf8, -0x07, -0xf0, -0x6f, -0xff, -0xc0, -0x3f, -0x80, -0xe1, -0x1f, -0xc0, -0xbf, -0xfe, -0x03, -0xff, -0x00, -0x86, -0x7f, -0x00, -0xff, -0xf8, -0xff, -0x1e, -0x00, -0xf0, -0x1f, -0xf8, -0x07, -0x37, -0xfc, -0x03, -0xf8, -0xc0, -0x7f, -0xe0, -0x1f, -0xdf, -0xf0, -0x0f, -0xe0, -0x00, -0xff, -0x81, -0x7f, -0x7f, -0xc3, -0x3f, -0x80, -0x00, -0xfc, -0x7f, -0x0f, -0x03, -0xf8, -0x0f, -0xfc, -0xfc, -0x1b, -0xfe, -0x01, -0x0f, -0xe0, -0x3f, -0xf0, -0xf0, -0x6f, -0xf8, -0x07, -0x3f, -0x80, -0xff, -0xc0, -0xc0, -0xbf, -0xe1, -0x1f, -0x07, -0x00, -0xfe, -0xbf, -0xfe, -0x01, -0xfc, -0x07, -0x00, -0xfe, -0x0d, -0xff, -0xf8, -0x07, -0xf0, -0x1f, -0x03, -0xf8, -0x37, -0xfc, -0xe0, -0x1f, -0xc0, -0x7f, -0x0f, -0xe0, -0xdf, -0xf0, -0xdf, -0x03, -0x00, -0xff, -0x03, -0xff, -0x00, -0xfe, -0x7f, -0x00, -0xff, -0x86, -0x0f, -0xfc, -0x03, -0xf8, -0xfe, -0x01, -0xfc, -0x1b, -0x3f, -0xf0, -0x0f, -0xe0, -0xf8, -0x07, -0xf0, -0x6f, -0xff, -0xef, -0x01, -0x80 -}}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c deleted file mode 100644 index c47c988494..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c +++ /dev/null @@ -1,1039 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Microcode patch. - * - * Fam10 Microcode Patch rev 010000D9 for 1081 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x10/RevD - * @e \$Revision: 60726 $ @e \$Date: 2011-10-20 17:08:02 -0600 (Thu, 20 Oct 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Patch code 010000d9 for 1081 and equivalent -CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000d9 = -{{ - 0x11, - 0x20, - 0x12, - 0x10, - 0xd9, - 0x00, - 0x00, - 0x01, - 0x00, - 0x80, - 0x20, - 0x00, - 0x6e, - 0x87, - 0xd2, - 0xea, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x81, - 0x10, - 0x00, - 0x00, - 0x00, - 0xaa, - 0xaa, - 0xaa, - 0xa7, - 0x0b, - 0x00, - 0x00, - 0x14, - 0x0c, - 0x00, - 0x00, - 0x55, - 0x03, - 0x00, - 0x00, - 0x08, - 0x0a, - 0x00, - 0x00, - 0x51, - 0x03, - 0x00, - 0x00, - 0x0c, - 0x0e, - 0x00, - 0x00, - 0xc4, - 0x07, - 0x00, - 0x00, - 0x9a, - 0x0b, - 0x00, - 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0x9f, - 0x87, - 0xff, - 0xff, - 0x77, - 0x79, - 0xfe, - 0x01, - 0x7e, - 0x1e, - 0xbf, - 0xbb, - 0x0f, - 0xf0, - 0xe8, - 0x97, - 0xf2, - 0x79, - 0xff, - 0xef, - 0x01, - 0x80, -}}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c deleted file mode 100644 index d16b4e749c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c +++ /dev/null @@ -1,516 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 RevD L3 dependent feature support functions. - * - * Provides the functions necessary to initialize L3 dependent feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 60552 $ @e \$Date: 2011-10-17 18:50:55 -0600 (Mon, 17 Oct 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "CommonReturns.h" -#include "cpuRegisters.h" -#include "cpuF10PowerMgmt.h" -#include "cpuLateInit.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuL3Features.h" -#include "F10PackageType.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDL3FEATURES_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/** - * The family 10h background scrubber context structure. - * - * These fields need to be saved, modified, then restored - * per die as part of HT Assist initialization. - */ -typedef struct { - UINT32 DramScrub:5; ///< DRAM scrub rate - UINT32 :3; ///< Reserved - UINT32 L3Scrub:5; ///< L3 scrub rate - UINT32 :3; ///< Reserved - UINT32 Redirect:1; ///< DRAM scrubber redirect enable - UINT32 :15; ///< Reserved -} F10_SCRUB_CONTEXT; - - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -F10IsNonOptimalConfig ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the input CPU supports L3 dependent features. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * - * @retval TRUE L3 dependent features are supported. - * @retval FALSE L3 dependent features are not supported. - * - */ -BOOLEAN -STATIC -F10IsL3FeatureSupported ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ) -{ - UINT32 Module; - UINT32 LocalPciRegister; - BOOLEAN IsSupported; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - IsSupported = FALSE; - - if (PlatformConfig->PlatformProfile.UseHtAssist) { - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((NB_CAPS_REGISTER *) &LocalPciRegister)->L3Capable == 1) { - IsSupported = TRUE; - } - break; - } - } - } - return IsSupported; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the input CPU supports HT Assist. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HT Assist is supported. - * @retval FALSE HT Assist cannot be enabled. - * - */ -BOOLEAN -STATIC -F10IsHtAssistSupported ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsSupported; - UINT32 CpuCount; - AP_MAILBOXES ApMailboxes; - - IsSupported = FALSE; - - if (PlatformConfig->PlatformProfile.UseHtAssist) { - CpuCount = GetNumberOfProcessors (StdHeader); - ASSERT (CpuCount != 0); - - if (CpuCount == 1) { - GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); - if (ApMailboxes.ApMailInfo.Fields.ModuleType != 0) { - IsSupported = TRUE; - } - } else if (CpuCount > 1) { - IsSupported = TRUE; - } - } - return IsSupported; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable the Probe filter feature. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F10HtAssistInit ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = L3_CACHE_PARAM_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((L3_CACHE_PARAM_REGISTER *) &LocalPciRegister)->L3TagInit = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - do { - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } while (((L3_CACHE_PARAM_REGISTER *) &LocalPciRegister)->L3TagInit != 0); - - PciAddress.Address.Register = PROBE_FILTER_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFMode = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - F10RevDProbeFilterCritical (PciAddress, LocalPciRegister); - - do { - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } while (((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFInitDone != 1); - IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Save the current settings of the scrubbers, and disabled them. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] ScrubSettings Location to store current L3 scrubber settings. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F10GetL3ScrubCtrl ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 ScrubCtrl; - UINT32 ScrubAddr; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - - ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader); - - PciAddress.Address.Register = SCRUB_RATE_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader); - - ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub = - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub; - ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub = - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub; - ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect = - ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn; - - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0; - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0; - ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader); - PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG; - LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Restore the initial settings for the scrubbers. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] ScrubSettings Location to store current L3 scrubber settings. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F10SetL3ScrubCtrl ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - - ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = SCRUB_RATE_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->DramScrub = - ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub; - ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->L3Scrub = - ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &LocalPciRegister)->ScrubReDirEn = - ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Set MSR bits required for L3 dependent features on each core. - * - * @param[in] L3FeatureServices L3 feature family services. - * @param[in] HtAssistEnabled Indicates whether Ht Assist is enabled. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F10HookDisableCache ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN BOOLEAN HtAssistEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - LibAmdMsrRead (MSR_BU_CFG2, &LocalMsrRegister, StdHeader); - LocalMsrRegister |= BIT42; - LibAmdMsrWrite (MSR_BU_CFG2, &LocalMsrRegister, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Hook before L3 features initialization sequence. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F10HookBeforeInit ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 LocalPciRegister; - UINT32 PfCtrlRegister; - PCI_ADDR PciAddress; - CPU_LOGICAL_ID LogicalId; - AGESA_STATUS IgnoredStatus; - UINT32 PackageType; - - GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader); - PackageType = LibAmdGetPackageType (StdHeader); - - LocalPciRegister = 0; - ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFWayNum = 2; - ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFSubCacheEn = 15; - ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFLoIndexHashEn = 1; - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PROBE_FILTER_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader); - ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFPreferredSORepl = - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - // Assumption: all socket use the same CPU package. - if (((LogicalId.Revision & AMD_F10_D0) != 0) && (PackageType == PACKAGE_TYPE_C32)) { - // Apply erratum #384 - // Set F2x11C[13:12] = 11b - PciAddress.Address.Function = FUNC_2; - PciAddress.Address.Register = 0x11C; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LocalPciRegister |= 0x3000; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the input CPU is running in the optimal configuration. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HT Assist is running sub-optimally. - * @retval FALSE HT Assist is running optimally. - * - */ -BOOLEAN -F10IsNonOptimalConfig ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsNonOptimal; - BOOLEAN IsMemoryPresent; - UINT32 Module; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - IsNonOptimal = FALSE; - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - IsMemoryPresent = FALSE; - PciAddress.Address.Function = FUNC_2; - PciAddress.Address.Register = DRAM_CFG_HI_REG0; - - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) { - IsMemoryPresent = TRUE; - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 4) { - IsNonOptimal = TRUE; - break; - } - } - - PciAddress.Address.Register = DRAM_CFG_HI_REG1; - - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) { - IsMemoryPresent = TRUE; - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 4) { - IsNonOptimal = TRUE; - break; - } - } - if (!IsMemoryPresent) { - IsNonOptimal = TRUE; - break; - } - } - } - return IsNonOptimal; -} - - -CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features = -{ - 0, - F10IsL3FeatureSupported, - F10GetL3ScrubCtrl, - F10SetL3ScrubCtrl, - F10HookBeforeInit, - (PF_L3_FEATURE_AFTER_INIT) CommonVoid, - F10HookDisableCache, - (PF_L3_FEATURE_ENABLE_CACHE) CommonVoid, - F10IsHtAssistSupported, - F10HtAssistInit, - F10IsNonOptimalConfig, - (PF_ATM_MODE_IS_SUPPORTED) CommonReturnFalse, - (PF_ATM_MODE_INIT) CommonVoid -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c deleted file mode 100644 index 1467537142..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 RevD Message-Based C1e feature support functions. - * - * Provides the functions necessary to initialize the message-based C1e feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuMsgBasedC1e.h" -#include "cpuApicUtilities.h" -#include "cpuF10PowerMgmt.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F10InitializeMsgBasedC1eOnCore ( - IN VOID *BmStsAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -STATIC -IsDramScrubberEnabled ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------*/ -/** - * Should message-based C1e be enabled - * - * @param[in] MsgBasedC1eServices Pointer to this CPU's HW C1e family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HW C1e is supported. - * - */ -BOOLEAN -STATIC -F10IsMsgBasedC1eSupported ( - IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader); - return ((BOOLEAN) (((LogicalId.Revision) & AMD_F10_GT_D0) != 0)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Core 0 task to enable message-based C1e on a family 10h CPU. - * - * @param[in] MsgBasedC1eServices Pointer to this CPU's HW C1e family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F10InitializeMsgBasedC1e ( - IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 AndMask; - UINT32 Core; - UINT32 Module; - UINT32 OrMask; - UINT32 LocalPciRegister; - UINT32 Socket; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { - // Note that this core 0 does NOT have the ability to launch - // any of its cores. Attempting to do so could lead to a system - // hang. - - // Set F3xA0[IdleExitEn] = 1 - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PW_CTL_MISC_REG; - AndMask = 0xFFFFFFFF; - OrMask = 0; - ((POWER_CTRL_MISC_REGISTER *) &OrMask)->IdleExitEn = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xA0 - - // Erratum #610, BIOS should set F3x1B8[5] - PciAddress.Address.Register = 0x1B8; - OrMask = 0x00000020; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x1B8 - - // Set F3x188[EnStpGntOnFlushMaskWakeup] = 1 - PciAddress.Address.Register = NB_EXT_CFG_LO_REG; - OrMask = 0; - ((NB_EXT_CFG_LO_REGISTER *) &OrMask)->EnStpGntOnFlushMaskWakeup = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x188 - - // Set F3xD4[MTC1eEn] = 1, F3xD4[CacheFlushImmOnAllHalt] = 1 - // Set F3xD4[StutterScrubEn] = 1 if scrubbing is enabled - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->StutterScrubEn = 0; - OrMask = 0; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->MTC1eEn = 1; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->CacheFlushImmOnAllHalt = 1; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - - for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC0_REG; - if (IsDramScrubberEnabled (PciAddress, StdHeader)) { - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 1; - } else { - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 0; - } - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LocalPciRegister &= AndMask; - LocalPciRegister |= OrMask; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } - - } else if (EntryPoint == CPU_FEAT_AFTER_PM_INIT) { - // At early, this core 0 can launch its subordinate cores. - TaskPtr.FuncAddress.PfApTaskI = F10InitializeMsgBasedC1eOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 1; - TaskPtr.DataTransfer.DataPtr = &PlatformConfig->C1ePlatformData; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable message-based C1e on a family 10h core. - * - * @param[in] BmStsAddress System I/O address of the bus master status bit. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F10InitializeMsgBasedC1eOnCore ( - IN VOID *BmStsAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - // Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0 - LibAmdMsrRead (MSR_INTPEND, &LocalMsrRegister, StdHeader); - ((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 0; - ((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 0; - ((INTPEND_MSR *) &LocalMsrRegister)->BmStsClrOnHltEn = 1; - ((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsgDis = 0; - ((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsg = 0; - ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress); - LibAmdMsrWrite (MSR_INTPEND, &LocalMsrRegister, StdHeader); - - // Set MSRC001_0015[HltXSpCycEn] = 1 - LibAmdMsrRead (MSR_HWCR, &LocalMsrRegister, StdHeader); - LocalMsrRegister |= BIT12; - LibAmdMsrWrite (MSR_HWCR, &LocalMsrRegister, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the DRAM background scrubbers are enabled or not. - * - * @param[in] PciAddress Address of F10 socket/module to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Memory scrubbers are enabled on the current node. - * @retval FALSE Memory scrubbers are disabled on the current node. - */ -BOOLEAN -STATIC -IsDramScrubberEnabled ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x58; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - return ((BOOLEAN) ((LocalPciRegister & 0x1F) != 0)); -} - - -CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e = -{ - 0, - F10IsMsgBasedC1eSupported, - F10InitializeMsgBasedC1e -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c deleted file mode 100644 index 2b1efc6cae..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c +++ /dev/null @@ -1,455 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 revision Dx specific utility functions. - * - * Provides numerous utility functions specific to family 10h rev D. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuF10PowerMgmt.h" -#include "GeneralServices.h" -#include "cpuEarlyInit.h" -#include "cpuRegisters.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -BOOLEAN -F10CommonRevDSetDownCoreRegister ( - IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, - IN UINT32 *Socket, - IN UINT32 *Module, - IN UINT32 *LeveledCores, - IN CORE_LEVELING_TYPE CoreLevelMode, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F10CommonRevDGetProcIddMax ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 Pstate, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F10CommonRevDGetNbCofVidUpdate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PCI_ADDR *PciAddress, - OUT BOOLEAN *NbVidUpdateAll, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F10CommonRevDGetNbPstateInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F10RevDGetMinMaxNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - OUT UINT32 *MinFreqInMHz, - OUT UINT32 *MaxFreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -F10CommonRevDGetNumberOfPhysicalCores ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Set down core register on a revision D processor. - * - * This function set F3x190 Downcore Control Register[5:0] - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Socket Socket ID. - * @param[in] Module Module ID in socket. - * @param[in] LeveledCores Number of core. - * @param[in] CoreLevelMode Core level mode. - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE Down Core register is updated. - * @retval FALSE Down Core register is not updated. - */ -BOOLEAN -F10CommonRevDSetDownCoreRegister ( - IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, - IN UINT32 *Socket, - IN UINT32 *Module, - IN UINT32 *LeveledCores, - IN CORE_LEVELING_TYPE CoreLevelMode, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempVar32_a; - UINT32 CoreDisableBits; - PCI_ADDR PciAddress; - BOOLEAN IsUpdated; - AGESA_STATUS AgesaStatus; - - IsUpdated = FALSE; - - switch (*LeveledCores) { - case 1: - CoreDisableBits = DOWNCORE_MASK_SINGLE; - break; - case 2: - CoreDisableBits = DOWNCORE_MASK_DUAL; - break; - case 3: - CoreDisableBits = DOWNCORE_MASK_TRI; - break; - case 4: - CoreDisableBits = DOWNCORE_MASK_FOUR; - break; - case 5: - CoreDisableBits = DOWNCORE_MASK_FIVE; - break; - default: - CoreDisableBits = 0; - break; - } - - if (CoreDisableBits != 0) { - if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG; - - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); - TempVar32_a = ((TempVar32_a >> 12) & 0x3) | ((TempVar32_a >> 13) & 0x4); - if (TempVar32_a == 0) { - CoreDisableBits &= 0x1; - } else if (TempVar32_a == 1) { - CoreDisableBits &= 0x3; - } else if (TempVar32_a == 2) { - CoreDisableBits &= 0x7; - } else if (TempVar32_a == 3) { - CoreDisableBits &= 0x0F; - } else if (TempVar32_a == 4) { - CoreDisableBits &= 0x1F; - } else if (TempVar32_a == 5) { - CoreDisableBits &= 0x3F; - } - PciAddress.Address.Register = DOWNCORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); - if ((TempVar32_a | CoreDisableBits) != TempVar32_a) { - TempVar32_a |= CoreDisableBits; - LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); - IsUpdated = TRUE; - } - } - } - - return IsUpdated; -} - - -CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling = -{ - 0, - F10CommonRevDSetDownCoreRegister -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * Get CPU pstate current on a revision D processor. - * - * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}. - * - * This function returns the ProcIddMax. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Pstate The P-state to check. - * @param[out] ProcIddMax P-state current in mA. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE P-state is enabled - * @retval FALSE P-state is disabled - */ -BOOLEAN -F10CommonRevDGetProcIddMax ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 Pstate, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 IddDiv; - UINT32 CmpCap; - UINT32 MultiNodeCpu; - UINT32 NbCaps; - UINT32 MsrAddress; - UINT64 PstateMsr; - BOOLEAN IsPstateEnabled; - PCI_ADDR PciAddress; - - IsPstateEnabled = FALSE; - - MsrAddress = (UINT32) (Pstate + PS_REG_BASE); - ASSERT (MsrAddress <= PS_MAX_REG); - - LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader); - if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) { - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); // F3xE8 - - switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) { - case 0: - IddDiv = 1000; - break; - case 1: - IddDiv = 100; - break; - case 2: - IddDiv = 10; - break; - default: // IddDiv = 3 is reserved. Use 10 - IddDiv = 10; - break; - } - MultiNodeCpu = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->MultiNodeCpu + 1); - CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapHi << 2); - CmpCap |= (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapLo); - CmpCap++; - *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap * MultiNodeCpu; - IsPstateEnabled = TRUE; - } - return IsPstateEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns whether or not BIOS is responsible for configuring the NB COFVID. - * - * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PciAddress The northbridge to query by pci base address. - * @param[out] NbVidUpdateAll Do all NbVids need to be updated - * @param[in] StdHeader Header for library and services - * - * @retval TRUE Perform northbridge frequency and voltage config. - * @retval FALSE Do not configure them. - */ -BOOLEAN -F10CommonRevDGetNbCofVidUpdate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PCI_ADDR *PciAddress, - OUT BOOLEAN *NbVidUpdateAll, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NbVidUpdateAll = FALSE; - return FALSE; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the NB clock on the desired node. - * - * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[in] NbPstate The NB P-state number to check. - * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. - * @param[out] FreqDivisor The desired node's frequency divisor. - * @param[out] VoltageInuV The desired node's voltage in microvolts. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE NbPstate is valid - * @retval FALSE NbPstate is disabled or invalid - */ -BOOLEAN -F10CommonRevDGetNbPstateInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - BOOLEAN PstateIsValid; - - PstateIsValid = FALSE; - if (NbPstate == 0) { - PciAddress->Address.Function = FUNC_3; - PciAddress->Address.Register = CPTC0_REG; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200); - *FreqDivisor = 1; - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbVid))); - PstateIsValid = TRUE; - } - return PstateIsValid; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the node's minimum and maximum northbridge frequency. - * - * @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[out] MinFreqInMHz The node's minimum northbridge frequency. - * @param[out] MaxFreqInMHz The node's maximum northbridge frequency. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_STATUS Northbridge frequency is valid - */ -AGESA_STATUS -F10RevDGetMinMaxNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - OUT UINT32 *MinFreqInMHz, - OUT UINT32 *MaxFreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - - PciAddress->Address.Function = FUNC_3; - PciAddress->Address.Register = CPTC0_REG; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - *MinFreqInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200); - *MaxFreqInMHz = *MinFreqInMHz; - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the number of physical cores of current processor. - * - * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The number of physical cores. - */ -UINT8 -F10CommonRevDGetNumberOfPhysicalCores ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CmpCap; - UINT32 CmpCapOnNode; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - CmpCap = 0; - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - CmpCapOnNode = (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapHi << 2); - CmpCapOnNode |= (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo); - CmpCapOnNode++; - CmpCap += CmpCapOnNode; - } - } - return ((UINT8) CmpCap); -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c deleted file mode 100644 index 1b4a1b82ed..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c +++ /dev/null @@ -1,114 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Hydra Equivalence Table related data - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -GetF10HyMicrocodeEquivalenceTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **HyEquivalenceTablePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -STATIC CONST UINT16 ROMDATA CpuF10HyMicrocodeEquivalenceTable[] = -{ - 0x1080, 0x1080, - 0x1081, 0x1081, - 0x1091, 0x1081 -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the appropriate microcode patch equivalent ID table. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] HyEquivalenceTablePtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF10HyMicrocodeEquivalenceTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **HyEquivalenceTablePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = ((sizeof (CpuF10HyMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); - *HyEquivalenceTablePtr = CpuF10HyMicrocodeEquivalenceTable; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c deleted file mode 100644 index 02f65c95cc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c +++ /dev/null @@ -1,1294 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Hydra Ht Phy tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// HT Phy T a b l e s -// ------------------------- -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyHtPhyRegisters[] = -{ -// 0x60:0x68 - { - HtPhyRangeRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_C0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_ALL, // - 0x60, 0x68, // Address - 0x00000040, // regData - 0x00000040, // regMask - }} - }, -// 0x70:0x78 - { - HtPhyRangeRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_C0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_ALL, // - 0x70, 0x78, // Address - 0x00000040, // regData - 0x00000040, // regMask - }} - }, -// 0xC0 - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_ALL, // - 0xC0, // Address - 0x40040000, // regData - 0xe01F0000, // regMask - }} - }, -// 0xD0 - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_ALL, // - 0xD0, // Address - 0x40040000, // regData - 0xe01F0000, // regMask - }} - }, -// 0xCF -// Default for HT3, unless overridden below. - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT3, // - 0xCF, // Address - 0x0000002A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// Default for HT3, unless overridden below. - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT3, // - 0xDF, // Address - 0x0000002A, // regData - 0x000000FF, // regMask - }} - }, - -// -// All the entries for XmtRdPtr 6 -// - -// 0xCF -// For HT frequencies 1200-1600 and NB Freq 1600, 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000006A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 1200-1600 and NB Freq 1600, 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000006A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 1800 and NB Freq 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000006A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 1800 and NB Freq 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000006A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 3200 and NB Freq 1600 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000006A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 3200 and NB Freq 1600 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000006A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 1200 and 1600 and NB Freq 1600 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK1), - 0xCF, // Address - 0x0000006A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 1200 and 1600 and NB Freq 1600 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK5), - 0xDF, // Address - 0x0000006A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 1200 and 1800 and NB Freq 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK1), - 0xCF, // Address - 0x0000006A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 1200 and 1800 and NB Freq 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK5), - 0xDF, // Address - 0x0000006A, // regData - 0x000000FF, // regMask - }} - }, - -// -// Entries for XmtRdPtr 5 -// - -// 0xCF -// For HT frequencies 1800-2600 and NB Freq 1600 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_2600M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000005A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 1800-2600 and NB Freq 1600 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_2600M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000005A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 2000 - 2800 and NB Freq 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2800M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000005A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 2000 - 2800 and NB Freq 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2800M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000005A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 1400 and 1800 and NB Freq 1600 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK1), - 0xCF, // Address - 0x0000005A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 1400 and 1800 and NB Freq 1600 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK5), - 0xDF, // Address - 0x0000005A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 1400 and 1600 and NB Freq 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK1), - 0xCF, // Address - 0x0000005A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 1400 and 1600 and NB Freq 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK5), - 0xDF, // Address - 0x0000005A, // regData - 0x000000FF, // regMask - }} - }, - -// -// Entries for XmtRdPtr 4 -// - -// 0xCF -// For HT frequencies 2800-3000 and NB Freq 1600 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2800M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000004A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 2800-3000 and NB Freq 1600 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2800M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000004A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 3000 - 3200 and NB Freq 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000004A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 3000 - 3200 and NB Freq 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000004A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 2000 - 2400 and 3200 and NB Freq 1600 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | FREQ_RANGE_1 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK1), - 0xCF, // Address - 0x0000004A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 2000 - 2400 and 3200 and NB Freq 1600 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | FREQ_RANGE_1 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK5), - 0xDF, // Address - 0x0000004A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 2000 - 2400 and NB Freq 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK1), - 0xCF, // Address - 0x0000004A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 2000 - 2400 and NB Freq 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK5), - 0xDF, // Address - 0x0000004A, // regData - 0x000000FF, // regMask - }} - }, - -// -// Entries for XmtRdPtr 3 -// - -// 0xCF -// For HT frequencies 2600-3000 and NB Freq 1600 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK1), - 0xCF, // Address - 0x0000003A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 2600-3000 and NB Freq 1600 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK5), - 0xDF, // Address - 0x0000003A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 2600 - 3200 and NB Freq 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK1), - 0xCF, // Address - 0x0000003A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 2600 - 3200 and NB Freq 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK5), - 0xDF, // Address - 0x0000003A, // regData - 0x000000FF, // regMask - }} - }, - -// -// Rev D0 fixups for Erratum 398. -// - -// 0xCF -// For HT frequencies 1800, 2200 and NB Freq 1400 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | FREQ_RANGE_1 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000000A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 1800, 2200 and NB Freq 1400 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | FREQ_RANGE_1 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000000A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 2600, 3000 and NB Freq 1400 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000000A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 2600, 3000 and NB Freq 1400 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000000A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 2200, 2600 and NB Freq 1600 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000003A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 2200, 2600 and NB Freq 1600 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000003A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 3000 and NB Freq 1600 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000002A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 3000 and NB Freq 1600 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000002A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 2200, 2600 and NB Freq 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000003A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 2200, 2600 and NB Freq 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000003A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 3000 and NB Freq 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000002A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 3000 and NB Freq 1800 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000002A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 1800 and NB Freq 1600 for all links - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), - 0xCF, // Address - 0x0000003A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 1800 and NB Freq 1600 for all links - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), - 0xDF, // Address - 0x0000003A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 2200 and NB Freq 1600, 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK1), - 0xCF, // Address - 0x0000002A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 2200 and NB Freq 1600, 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | COUNT_RANGE_NONE), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK5), - 0xDF, // Address - 0x0000002A, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// For HT frequencies 2600, 3000 and NB Freq 1600, 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL0_LINK1), - 0xCF, // Address - 0x0000001A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// For HT frequencies 2600, 3000 and NB Freq 1600, 1800 only for link 1 - { - HtPhyFreqRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)), - (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), - (HTPHY_LINKTYPE_SL1_LINK5), - 0xDF, // Address - 0x0000001A, // regData - 0x000000FF, // regMask - }} - }, - -// -// Deemphasis Settings for D1 processors. -// - -// For D1, also set [7]TxLs23ClkGateEn. -//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6] -// No deemphasis 00h 00h 00h 0 0 0 0 -// -3dB postcursor 12h 00h 00h 1 0 0 0 -// -6dB postcursor 1Fh 00h 00h 1 0 0 0 -// -8dB postcursor 1Fh 06h 00h 1 1 0 1 -// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1 -// -11dB postcursor with -// -8dB precursor 1Fh 06h 07h 1 1 1 1 - - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL_NONE, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0x00000080, // regData - 0xE01F1FDF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL_NONE, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0x00000080, // regData - 0xE01F1FDF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__3, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0x80120080, // regData - 0xE01F1FDF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__3, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0x80120080, // regData - 0xE01F1FDF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__6, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0x801F0080, // regData - 0xE01F1FDF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__6, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0x801F0080, // regData - 0xE01F1FDF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__8, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0xC01F06C0, // regData - 0xE01F1FDF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__8, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0xC01F06C0, // regData - 0xE01F1FDF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0xC01F0DC0, // regData - 0xE01F1FDF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0xC01F0DC0, // regData - 0xE01F1FDF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11_8, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0xE01F06C7, // regData - 0xE01F1FDF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11_8, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0xE01F06C7, // regData - 0xE01F1FDF, // regMask - }} - }, - -// 0x520A - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_ALL, // - 0x520A, // Address - 0x00004000, // regData - 0x00006000, // regMask - }} - }, -// 0x530A - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_HY_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_ALL, // - 0x530A, // Address - 0x00004000, // regData - 0x00006000, // regMask - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable = { - PrimaryCores, - (sizeof (F10HyHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F10HyHtPhyRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c deleted file mode 100644 index c5afa3ad26..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c +++ /dev/null @@ -1,144 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Implements the workaround for erratum 419. - * - * Returns the table of initialization steps to perform at - * AmdInitEarly. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x10/RevD/HY - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "F10PackageType.h" -#include "cpuEarlyInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -GetF10HyEarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly; -extern F_GET_EARLY_INIT_TABLE GetF10EarlyInitOnCoreTable; - -CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10HyC32D0EarlyInitOnCoreTable[] = -{ - {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {LoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET}, - {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {NULL, 0} -}; - -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that may be invoked at AmdCpuEarly to return the steps - * appropriate for the executing Rev D core. - * - * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[out] Table Table of appropriate init steps for the executing core. - * @param[in] EarlyParams Service Interface structure to initialize. - * @param[in] StdHeader Opaque handle to standard config header. - * - */ -VOID -GetF10HyEarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ProcessorPackageType; - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - ProcessorPackageType = LibAmdGetPackageType (StdHeader); - - // Check if this CPU is affected by erratum 419. - if (((LogicalId.Revision & AMD_F10_HY_SCM_D0) != 0) && ((ProcessorPackageType & (PACKAGE_TYPE_G34 | PACKAGE_TYPE_FR2_FR5_FR6)) == 0)) { - // Return initialization steps such that the microcode patch is applied before - // brand string determination is performed. - *Table = F10HyC32D0EarlyInitOnCoreTable; - } else { - // No workaround is necessary. Return the standard table. - GetF10EarlyInitOnCoreTable (FamilyServices, Table, EarlyParams, StdHeader); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c deleted file mode 100644 index 79339a8f56..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c +++ /dev/null @@ -1,116 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Hydra Logical ID Table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -GetF10HyLogicalIdAndRev ( - OUT CONST CPU_LOGICAL_ID_XLAT **HyIdPtr, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10HyLogicalIdAndRevArray[] = -{ - { - 0x1080, - AMD_F10_HY_SCM_D0 - }, - { - 0x1090, - AMD_F10_HY_MCM_D0 - }, - { - 0x1081, - AMD_F10_HY_SCM_D1 - }, - { - 0x1091, - AMD_F10_HY_MCM_D1 - } -}; - -VOID -GetF10HyLogicalIdAndRev ( - OUT CONST CPU_LOGICAL_ID_XLAT **HyIdPtr, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = (sizeof (CpuF10HyLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); - *HyIdPtr = CpuF10HyLogicalIdAndRevArray; - *LogicalFamily = AMD_FAMILY_10_HY; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c deleted file mode 100644 index a924bbd3e3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c +++ /dev/null @@ -1,114 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Hydra PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -extern CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[]; -extern CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -GetF10HyMicroCodePatchesStruct ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **HyUcodePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns a table containing the appropriate microcode patches. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] HyUcodePtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF10HyMicroCodePatchesStruct ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **HyUcodePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = CpuF10HyNumberOfMicrocodePatches; - *HyUcodePtr = &CpuF10HyMicroCodePatchArray[0]; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c deleted file mode 100644 index 83094bdf7a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c +++ /dev/null @@ -1,137 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 HY MSR tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] = -{ -// M S R T a b l e s -// ---------------------- - -// MSR_LS_CFG (0xC0011020) -// bit[1] = 0 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_B0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_LS_CFG, // MSR Address - 0x0000000000000000, // OR Mask - (1 << 1) // NAND Mask - }} - }, - -// MSR_BU_CFG (0xC0011023) -// bit[21] = 1 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_B0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_BU_CFG, // MSR Address - (1 << 21), // OR Mask - (1 << 21), // NAND Mask - }} - }, - -// MSR_BU_CFG2 (0xC001102A) -// bit[50] = 1 -// For GH rev C1 and later [RdMmExtCfgQwEn]=1 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_C0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_BU_CFG2, // MSR Address - 0x0004000000000000, // OR Mask - 0x0004000000000000, // NAND Mask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable = { - AllCores, - (sizeof (F10HyMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F10HyMsrRegisters, -}; - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c deleted file mode 100644 index d1fa49d2b7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c +++ /dev/null @@ -1,384 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Hydra PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyPciRegisters[] = -{ -// F0x68 - - // BufRelPri for rev D - // bits[14:13] BufRelPri = 1 - // bit [25] CHtExtAddrEn = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO(0, 0, 24, FUNC_0, 0x68), // Address - 0x02002000, // regData - 0x02006000, // regMask - }} - }, - // F0x[E4,A4,C4,84] Link Control Register - // bit [15] Addr64bitEn = 1 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - {AMD_PF_ALL}, - {{ - HT_HOST_FEAT_NONCOHERENT, - 0x4, - 0x00008000, - 0x00008000, - }} - }, -// F0x150 - Link Global Retry Control Register -// bit[18:16] TotalRetryAttempts = 7 -// bit[13] HtRetryCrcDatInsDynEn = 1 -// bit[12]HtRetryCrcCmdPackDynEn = 1 -// bit[11:9] HtRetryCrcDatIns = 0 -// bit[8] HtRetryCrcCmdPack = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address - 0x00073100, // regData - 0x00073F00, // regMask - }} - }, -// F0x16C - Link Global Extended Control Register -// bit[15:13] ForceFullT0 = 6 -// bit[5:0] T0Time = 0x26 - { - PciRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address - 0x0000C026, // regData - 0x0000E03F, // regMask - }} - }, -// F0x16C - Link Global Extended Control Register -// bit[9] RXCalEn = 1 - { - PciRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address - 0x00000200, // regData - 0x00000200, // regMask - }} - }, -// F0x16C - Link Global Extended Control Register -// bit[7:6] InLnSt = 01b (PHY_OFF) - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address - 0x00000040, // regData - 0x000000C0, // regMask - }} - }, -// F0x[18C:170] - Link Extended Control Register - All connected links. -// bit[8] LS2En = 1 - { - HtLinkPciRegister, - { - AMD_FAMILY_10_HY, // CpuFamily - AMD_F10_D1 // CpuRevision - }, - {AMD_PF_ALL}, // platform Features - {{ - HT_HOST_FEATURES_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F2x1B0 - Extended Memory Controller Configuration Low -// bits[10:8], CohPrefPrbLmt = 0 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, // Features - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address - 0x00000000, // regData - 0x00000700, // regMask - }} - }, -// Function 3 - Misc. Control -// F3x158 - Link to XCS Token Count -// bits[3:0] LnkToXcsDRToken = 3 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_A2 // CpuRevision - }, - {AMD_PF_UMA}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address - 0x00000003, // regData - 0x0000000F, // regMask - }} - }, - -// F3x80 - ACPI Power State Control -// ACPI State C2 -// bits[0] CpuPrbEn = 1 -// bits[1] NbLowPwrEn = 0 -// bits[2] NbGateEn = 0 -// bits[3] NbCofChg = 0 -// bits[4] AltVidEn = 0 -// bits[7:5] ClkDivisor = 1 -// ACPI State C3, C1E or Link init -// bits[0] CpuPrbEn = 0 -// bits[1] NbLowPwrEn = 1 -// bits[2] NbGateEn = 1 -// bits[3] NbCofChg = 0 -// bits[4] AltVidEn = 0 -// bits[7:5] ClkDivisor = 5 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address - 0x0000A681, // regData - 0x0000FFFF, // regMask - }} - }, - -// F3x80 - ACPI Power State Control -// ACPI State C3, C1E or Link init -// bits[0] CpuPrbEn = 0 -// bits[1] NbLowPwrEn = 1 -// bits[2] NbGateEn = 1 -// bits[3] NbCofChg = 0 -// bits[4] AltVidEn = 0 -// bits[7:5] ClkDivisor = 7 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address - 0x0000E600, // regData - 0x0000FF00, // regMask - }} - }, - -// F3xA0 - Power Control Miscellaneous -// bit[14] BpPinsTriEn = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address - 0x00004000, // regData - 0x00004000, // regMask - }} - }, - -// F3xD4 - Clock Power Timing Control 0 -// bits[15] StutterScrubEn = 0 -// bits[14] CacheFlushImmOnAllHalt = 0 -// bits[13] MTC1eEn = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address - 0x00000000, // regData - 0x0000E000, // regMask - }} - }, - -// F3x188 - NB Extended Configuration Low Register -// bit[27] = DisCpuWrSzDw64ReOrd - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address - 0x08000000, // regData - 0x08000000, // regMask - }} - }, - -// F3x1B8 - L3 Control -// bit[18] L3RdBufBypDis = 1, Erratum 374 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_D0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address - 0x00040000, // regData - 0x00040000, // regMask - }} - }, - -// F3x1B8 - L3 Control -// bit[23] L3BankSwapDis = 1, Erratum 385 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address - 0x00800000, // regData - 0x00800000, // regMask - }} - }, - -// F3x1D4 - Probe Filter Control Register -// bits[21:20] PFPreferedSORepl = 2 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_Dx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1D4), // Address - 0x00200000, // regData - 0x00300000, // regMask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable = { - PrimaryCores, - (sizeof (F10HyPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F10HyPciRegisters, -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/Makefile.inc deleted file mode 100644 index 4883524f4c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -libagesa-y += F10HyEquivalenceTable.c -libagesa-y += F10HyEquivalenceTable.c -libagesa-y += F10HyHtPhyTables.c -libagesa-y += F10HyHtPhyTables.c -libagesa-y += F10HyInitEarlyTable.c -libagesa-y += F10HyInitEarlyTable.c -libagesa-y += F10HyLogicalIdTables.c -libagesa-y += F10HyLogicalIdTables.c -libagesa-y += F10HyMicrocodePatchTables.c -libagesa-y += F10HyMicrocodePatchTables.c -libagesa-y += F10HyMsrTables.c -libagesa-y += F10HyMsrTables.c -libagesa-y += F10HyPciTables.c -libagesa-y += F10HyPciTables.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/Makefile.inc deleted file mode 100644 index 508a63152a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -libagesa-y += F10MicrocodePatch010000c5.c -libagesa-y += F10MicrocodePatch010000c5.c -libagesa-y += F10MicrocodePatch010000d9.c -libagesa-y += F10MicrocodePatch010000d9.c -libagesa-y += F10RevDL3Features.c -libagesa-y += F10RevDL3Features.c -libagesa-y += F10RevDMsgBasedC1e.c -libagesa-y += F10RevDMsgBasedC1e.c -libagesa-y += F10RevDUtilities.c -libagesa-y += F10RevDUtilities.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c deleted file mode 100644 index ea7f20a908..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c +++ /dev/null @@ -1,329 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 specific utility functions. - * - * Provides numerous utility functions specific to family 10h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuCommonF10Utilities.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/** - * Node ID MSR register fields. - * Provide the layout of fields in the Node ID MSR. - */ -typedef struct { - UINT64 NodeId:3; ///< The core is on the node with this node id. - UINT64 NodesPerProcessor:3; ///< The number of Nodes in this processor. - UINT64 HeapIndex:6; ///< The AP core heap index. - UINT64 :(63 - 11); ///< Reserved. -} NODE_ID_MSR_FIELDS; - -/// Node ID MSR. -typedef union { - NODE_ID_MSR_FIELDS Fields; ///< Access the register as individual fields - UINT64 Value; ///< Access the register value. -} NODE_ID_MSR; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Set warm reset status and count - * - * @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}. - * - * This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * @param[in] Request Indicate warm reset status - * - */ -VOID -F10SetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ) -{ - PCI_ADDR PciAddress; - UINT32 PciData; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - - // bit[5] - indicate a warm reset is or is not required - PciData &= ~(HT_INIT_BIOS_RST_DET_0); - PciData = PciData | (Request->RequestBit << 5); - - // bit[10,9] - indicate warm reset status and count - PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2); - PciData |= Request->StateBits << 9; - - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get warm reset status and count - * - * @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}. - * - * This function will bit9, and bit 10 of register F0x6C as a warm reset status and count. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Config handle for library and services - * @param[out] Request Indicate warm reset status - * - */ -VOID -F10GetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ) -{ - PCI_ADDR PciAddress; - UINT32 PciData; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - - // bit[5] - indicate a warm reset is or is not required - Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5); - // bit[10,9] - indicate warm reset status and count - Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Use the Mailbox Register to get the Ap Mailbox info for the current core. - * - * @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}. - * - * Access the mailbox register used with this NB family. This is valid until the - * point that some init code initializes the mailbox register for its normal use. - * The Machine Check Misc (Thresholding) register is available as both a PCI config - * register and a MSR, so it can be used as a mailbox from HT to other functions. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] ApMailboxInfo The AP Mailbox info - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F10GetApMailboxFromHardware ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MailboxInfo; - - LibAmdMsrRead (MSR_MC_MISC_LINK_THRESHOLD, &MailboxInfo, StdHeader); - // Mailbox info is in bits 32 thru 43, 12 bits. - ApMailboxInfo->ApMailInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF); - LibAmdMsrRead (MSR_MC_MISC_L3_THRESHOLD, &MailboxInfo, StdHeader); - // Mailbox info is in bits 32 thru 43, 12 bits. - ApMailboxInfo->ApMailExtInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Set the system AP core number in the AP's Mailbox. - * - * @CpuServiceMethod{::F_CPU_SET_AP_CORE_NUMBER}. - * - * Access the mailbox register used with this NB family. This is only intended to - * run on the BSC at the time of initial AP launch. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Socket The AP's socket - * @param[in] Module The AP's module - * @param[in] ApCoreNumber The AP's unique core number - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F10SetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 ApCoreNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x170; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((AP_MAIL_EXT_INFO *) &LocalPciRegister)->Fields.HeapIndex = ApCoreNumber; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Get this AP's system core number from hardware. - * - * @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}. - * - * Returns the system core number from the scratch MSR, where - * it was saved at heap initialization. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The AP's unique core number - */ -UINT32 -F10GetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - NODE_ID_MSR NodeIdMsr; - - LibAmdMsrRead (0xC001100C, &NodeIdMsr.Value, StdHeader); - return (UINT32) NodeIdMsr.Fields.HeapIndex; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Move the AP's core number from the mailbox to hardware. - * - * @CpuServiceMethod{::F_CPU_TRANSFER_AP_CORE_NUMBER}. - * - * Transfers this AP's system core number from the mailbox to - * the NodeId MSR and initializes the other NodeId fields. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F10TransferApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_MAILBOXES Mailboxes; - NODE_ID_MSR NodeIdMsr; - UINT64 ExtFeatures; - - NodeIdMsr.Value = 0; - FamilySpecificServices->GetApMailboxFromHardware (FamilySpecificServices, &Mailboxes, StdHeader); - NodeIdMsr.Fields.HeapIndex = Mailboxes.ApMailExtInfo.Fields.HeapIndex; - NodeIdMsr.Fields.NodeId = Mailboxes.ApMailInfo.Fields.Node; - NodeIdMsr.Fields.NodesPerProcessor = Mailboxes.ApMailInfo.Fields.ModuleType; - LibAmdMsrWrite (0xC001100C, &NodeIdMsr.Value, StdHeader); - - // Indicate that the NodeId MSR is supported. - LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader); - ExtFeatures = (ExtFeatures | BIT51); - LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Return a number zero or one, based on the Core ID position in the initial APIC Id. - * - * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval CoreIdPositionZero Core Id is not low - * @retval CoreIdPositionOne Core Id is low - */ -CORE_ID_POSITION -F10CpuAmdCoreIdPositionInInitialApicId ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 InitApicIdCpuIdLo; - - // Check bit_54 [InitApicIdCpuIdLo] to find core id position. - LibAmdMsrRead (MSR_NB_CFG, &InitApicIdCpuIdLo, StdHeader); - InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54); - return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h deleted file mode 100644 index a09feb1764..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 specific utility functions. - * - * Provides numerous utility functions specific to family 10h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: IDS - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_COMMON_F10_UTILITES_H_ -#define _CPU_COMMON_F10_UTILITES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F10GetApMailboxFromHardware ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -CORE_ID_POSITION -F10CpuAmdCoreIdPositionInInitialApicId ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F10SetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 ApCoreNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -F10GetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F10TransferApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F10SetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ); - -VOID -F10GetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ); - -#endif // _CPU_COMMON_F10_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c deleted file mode 100644 index edda5bcbba..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c +++ /dev/null @@ -1,160 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF10BrandIdString1 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString1Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetF10BrandIdString2 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString2Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -extern CPU_BRAND_TABLE *F10BrandIdString1Tables[]; -extern CPU_BRAND_TABLE *F10BrandIdString2Tables[]; -extern CONST UINT8 F10BrandIdString1TableCount; -extern CONST UINT8 F10BrandIdString2TableCount; - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns a table containing the appropriate beginnings of the CPU brandstring. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] BrandString1Ptr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF10BrandIdString1 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString1Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_BRAND_TABLE **TableEntryPtr; - - TableEntryPtr = &F10BrandIdString1Tables[0]; - *BrandString1Ptr = TableEntryPtr; - *NumberOfElements = F10BrandIdString1TableCount; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns a table containing the appropriate endings of the CPU brandstring. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] BrandString2Ptr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF10BrandIdString2 ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **BrandString2Ptr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_BRAND_TABLE **TableEntryPtr; - - TableEntryPtr = &F10BrandIdString2Tables[0]; - *BrandString2Ptr = TableEntryPtr; - *NumberOfElements = F10BrandIdString2TableCount; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c deleted file mode 100644 index 9aaf777ade..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c +++ /dev/null @@ -1,335 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures for socket Am3. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY - -// String1 -/*CHAR8 strEngSample[] = "AMD Engineering Sample"; -CHAR8 strTtkSample[] = "AMD Thermal Test Kit"; -CHAR8 strUnknown[] = "AMD Processor model unknown"; -*/ -//AM3 NC 0 -CONST CHAR8 ROMDATA str_F10_Am3_SC_AthlonLE[] = "AMD Athlon(tm) Processor LE-"; -CONST CHAR8 ROMDATA str_F10_Am3_SC_SempronLE[] = "AMD Sempron(tm) Processor LE-"; -CONST CHAR8 ROMDATA str_F10_Am3_SC_Sempron_1[] = "AMD Sempron(tm) 1"; -CONST CHAR8 ROMDATA str_F10_Am3_SC_Athlon_1[] = "AMD Athlon(tm) II 1"; - -//AM3 NC 1 -CONST CHAR8 ROMDATA str_F10_Am3_Athlon[] = "AMD Athlon(tm) "; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_XL_V[] = "AMD Athlon(tm) II XL V"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_XLT_V[] = "AMD Athlon(tm) II XLT V"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2_4[] = "AMD Athlon(tm) II X2 4"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2_2[] = "AMD Athlon(tm) II X2 2"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2_B[] = "AMD Athlon(tm) II X2 B"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2[] = "AMD Athlon(tm) II X2 "; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_Neo_X2[] = "AMD Athlon(tm) II Neo X2 "; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X2_5[] = "AMD Phenom(tm) II X2 5"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2_5[] = "AMD Athlon(tm) II X2 5"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2_3[] = "AMD Athlon(tm) II X2 3"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X2[] = "AMD Phenom(tm) II X2 "; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X2_B[] = "AMD Phenom(tm) II X2 B"; -CONST CHAR8 ROMDATA str_F10_Am3_DC_Opteron13[] = "Dual-Core AMD Opteron(tm) Processor 13"; -CONST CHAR8 ROMDATA str_F10_Am3_Sempron_X2_1[] = "AMD Sempron(tm) X2 1"; - -//AM3 NC2 -CONST CHAR8 ROMDATA str_F10_Am3_Phenom[] = "AMD Phenom(tm) "; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X3_5[] = "AMD Phenom(tm) II X3 5"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X3_4[] = "AMD Phenom(tm) II X3 4"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X3_B[] = "AMD Phenom(tm) II X3 B"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X3[] = "AMD Phenom(tm) II X3 "; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X3_3[] = "AMD Athlon(tm) II X3 3"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_Neo_X3[] = "AMD Athlon(tm) II Neo X3 "; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X3_4[] = "AMD Athlon(tm) II X3 4"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X3_7[] = "AMD Phenom(tm) II X3 7"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X3_B[] = "AMD Athlon(tm) II X3 B"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X3[] = "AMD Athlon(tm) II X3 "; - -//AM3 NC 3 -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_FX[] = "AMD Phenom(tm) FX-"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4_9[] = "AMD Phenom(tm) II X4 9"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4_8[] = "AMD Phenom(tm) II X4 8"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4_7[] = "AMD Phenom(tm) II X4 7"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4_6[] = "AMD Phenom(tm) II X4 6"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4_B[] = "AMD Phenom(tm) II X4 B"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4[] = "AMD Phenom(tm) II X4 "; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_Neo_X4[] = "AMD Phenom(tm) II Neo X4 "; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X4_6[] = "AMD Athlon(tm) II X4 6"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X4_5[] = "AMD Athlon(tm) II X4 5"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_Neo_X4[] = "AMD Athlon(tm) II Neo X4 "; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X4_B[] = "AMD Athlon(tm) II X4 B"; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II__FX[] = "AMD Phenom(tm) II FX-"; -CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X4[] = "AMD Athlon(tm) II X4 "; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II[] = "AMD Phenom(tm) II "; -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_XLT_Q[] = "AMD Phenom(tm) II XLT Q"; -CONST CHAR8 ROMDATA str_F10_Am3_QC_Opteron13[] = "Quad-Core AMD Opteron(tm) Processor 13"; - -//AM3 NC 5 -CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X6_1[] = "AMD Phenom(tm) II X6 1"; - -// String2 -CONST CHAR8 ROMDATA str2_F10_Am3_SE[] = " SE"; -CONST CHAR8 ROMDATA str2_F10_Am3_HE[] = " HE"; -CONST CHAR8 ROMDATA str2_F10_Am3_EE[] = " EE"; - -CONST CHAR8 ROMDATA str2_F10_Am3_QCP[] = " Quad-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_00[] = "00"; -CONST CHAR8 ROMDATA str2_F10_Am3_10[] = "10"; -CONST CHAR8 ROMDATA str2_F10_Am3_20[] = "20"; -CONST CHAR8 ROMDATA str2_F10_Am3_30[] = "30"; -CONST CHAR8 ROMDATA str2_F10_Am3_40[] = "40"; -CONST CHAR8 ROMDATA str2_F10_Am3_50[] = "50"; -CONST CHAR8 ROMDATA str2_F10_Am3_60[] = "60"; -CONST CHAR8 ROMDATA str2_F10_Am3_70[] = "70"; -CONST CHAR8 ROMDATA str2_F10_Am3_80[] = "80"; -CONST CHAR8 ROMDATA str2_F10_Am3_90[] = "90"; -CONST CHAR8 ROMDATA str2_F10_Am3_DC_00[] = "00 Dual-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_DC_00e[] = "00e Dual-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_DC_00B[] = "00B Dual-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_DC_50[] = "50 Dual-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_DC_50e[] = "50e Dual-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_DC_50B[] = "50B Dual-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_Processor[] = " Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_e_Processor[] = "e Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_B_Processor[] = "B Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_0e_Processor[] = "0e Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_u_Processor[] = "u Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_0_Processor[] = "0 Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_L_Processor[] = "L Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_C_Processor[] = "C Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_TWKR_Black_Edition[] = " TWKR Black Edition"; - -CONST CHAR8 ROMDATA str2_F10_Am3_TC_00[] = "00 Triple-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_TC_00e[] = "00e Triple-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_TC_00B[] = "00B Triple-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_TC_50[] = "50 Triple-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_TC_50e[] = "50e Triple-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_TC_50B[] = "50B Triple-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_QC_00[] = "00 Quad-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_QC_00e[] = "00e Quad-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_QC_00B[] = "00B Quad-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_QC_50[] = "50 Quad-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_QC_50e[] = "50e Quad-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_QC_50B[] = "50B Quad-Core Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_QC_T[] = "T Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_SC_0T[] = "0T Processor"; -CONST CHAR8 ROMDATA str2_F10_Am3_SC_5T[] = "5T Processor"; - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayAm3[] = -{ - // AM3 - {1, 0, 0, DR_SOCKET_AM3, str_F10_Am3_SC_AthlonLE, sizeof (str_F10_Am3_SC_AthlonLE)}, - {1, 0, 1, DR_SOCKET_AM3, str_F10_Am3_SC_SempronLE, sizeof (str_F10_Am3_SC_SempronLE)}, - {1, 0, 2, DR_SOCKET_AM3, str_F10_Am3_SC_Sempron_1, sizeof (str_F10_Am3_SC_Sempron_1)}, - {1, 0, 3, DR_SOCKET_AM3, str_F10_Am3_SC_Athlon_1, sizeof (str_F10_Am3_SC_Athlon_1)}, - - {2, 0, 0, DR_SOCKET_AM3, str_F10_Am3_DC_Opteron13, sizeof (str_F10_Am3_DC_Opteron13)}, - {2, 0, 1, DR_SOCKET_AM3, str_F10_Am3_Athlon, sizeof (str_F10_Am3_Athlon)}, - {2, 0, 2, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2_4, sizeof (str_F10_Am3_Athlon_II_X2_4)}, - {2, 0, 3, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2_2, sizeof (str_F10_Am3_Athlon_II_X2_2)}, - {2, 0, 4, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2_B, sizeof (str_F10_Am3_Athlon_II_X2_B)}, - {2, 0, 5, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2, sizeof (str_F10_Am3_Athlon_II_X2)}, - {2, 0, 6, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_Neo_X2, sizeof (str_F10_Am3_Athlon_II_Neo_X2)}, - {2, 0, 7, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X2_5, sizeof (str_F10_Am3_Phenom_II_X2_5)}, - {2, 0, 8, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2_5, sizeof (str_F10_Am3_Athlon_II_X2_5)}, - {2, 0, 9, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2_3, sizeof (str_F10_Am3_Athlon_II_X2_3)}, - {2, 0, 10, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X2, sizeof (str_F10_Am3_Phenom_II_X2)}, - {2, 0, 11, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X2_B, sizeof (str_F10_Am3_Phenom_II_X2_B)}, - {2, 0, 12, DR_SOCKET_AM3, str_F10_Am3_Sempron_X2_1, sizeof (str_F10_Am3_Sempron_X2_1)}, - {2, 1, 1, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_XLT_V, sizeof (str_F10_Am3_Athlon_II_XLT_V)}, - {2, 1, 2, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_XL_V, sizeof (str_F10_Am3_Athlon_II_XL_V)}, - - {3, 0, 0, DR_SOCKET_AM3, str_F10_Am3_Phenom, sizeof (str_F10_Am3_Phenom)}, - {3, 0, 1, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X3_5, sizeof (str_F10_Am3_Phenom_II_X3_5)}, - {3, 0, 2, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X3_4, sizeof (str_F10_Am3_Phenom_II_X3_4)}, - {3, 0, 3, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X3_B, sizeof (str_F10_Am3_Phenom_II_X3_B)}, - {3, 0, 4, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X3, sizeof (str_F10_Am3_Phenom_II_X3)}, - {3, 0, 5, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X3_3, sizeof (str_F10_Am3_Athlon_II_X3_3)}, - {3, 0, 6, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_Neo_X3, sizeof (str_F10_Am3_Athlon_II_Neo_X3)}, - {3, 0, 7, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X3_4, sizeof (str_F10_Am3_Athlon_II_X3_4)}, - {3, 0, 8, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X3_7, sizeof (str_F10_Am3_Phenom_II_X3_7)}, - {3, 0, 9, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X3_B, sizeof (str_F10_Am3_Athlon_II_X3_B)}, - {3, 0, 10, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X3, sizeof (str_F10_Am3_Athlon_II_X3)}, - - {4, 0, 0, DR_SOCKET_AM3, str_F10_Am3_QC_Opteron13, sizeof (str_F10_Am3_QC_Opteron13)}, - {4, 0, 1, DR_SOCKET_AM3, str_F10_Am3_Phenom_FX, sizeof (str_F10_Am3_Phenom_FX)}, - {4, 0, 2, DR_SOCKET_AM3, str_F10_Am3_Phenom, sizeof (str_F10_Am3_Phenom)}, - {4, 0, 3, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_9, sizeof (str_F10_Am3_Phenom_II_X4_9)}, - {4, 0, 4, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_8, sizeof (str_F10_Am3_Phenom_II_X4_8)}, - {4, 0, 5, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_7, sizeof (str_F10_Am3_Phenom_II_X4_7)}, - {4, 0, 6, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_6, sizeof (str_F10_Am3_Phenom_II_X4_6)}, - {4, 0, 7, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_B, sizeof (str_F10_Am3_Phenom_II_X4_B)}, - {4, 0, 8, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4, sizeof (str_F10_Am3_Phenom_II_X4)}, - {4, 0, 9, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_Neo_X4, sizeof (str_F10_Am3_Phenom_II_Neo_X4)}, - {4, 0, 10, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X4_6, sizeof (str_F10_Am3_Athlon_II_X4_6)}, - {4, 0, 11, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X4_5, sizeof (str_F10_Am3_Athlon_II_X4_5)}, - {4, 0, 12, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_Neo_X4, sizeof (str_F10_Am3_Athlon_II_Neo_X4)}, - {4, 0, 13, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X4_B, sizeof (str_F10_Am3_Athlon_II_X4_B)}, - {4, 0, 14, DR_SOCKET_AM3, str_F10_Am3_Phenom_II__FX, sizeof (str_F10_Am3_Phenom_II__FX)}, - {4, 0, 15, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X4, sizeof (str_F10_Am3_Athlon_II_X4)}, - {4, 1, 0, DR_SOCKET_AM3, str_F10_Am3_Phenom_II, sizeof (str_F10_Am3_Phenom_II)}, - {4, 1, 1, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_XLT_Q, sizeof (str_F10_Am3_Phenom_II_XLT_Q)}, - {4, 1, 2, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_9, sizeof (str_F10_Am3_Phenom_II_X4_9)}, - {4, 1, 3, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_8, sizeof (str_F10_Am3_Phenom_II_X4_8)}, - {4, 1, 4, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_6, sizeof (str_F10_Am3_Phenom_II_X4_6)}, - - {6, 0, 0, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X6_1, sizeof (str_F10_Am3_Phenom_II_X6_1)} -}; //Cores, page, index, socket, stringstart, stringlength - - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayAm3[] = -{ - // AM3 - {1, 0, 0x00, DR_SOCKET_AM3, str2_F10_Am3_00, sizeof (str2_F10_Am3_00)}, - {1, 0, 0x01, DR_SOCKET_AM3, str2_F10_Am3_10, sizeof (str2_F10_Am3_10)}, - {1, 0, 0x02, DR_SOCKET_AM3, str2_F10_Am3_20, sizeof (str2_F10_Am3_20)}, - {1, 0, 0x03, DR_SOCKET_AM3, str2_F10_Am3_30, sizeof (str2_F10_Am3_30)}, - {1, 0, 0x04, DR_SOCKET_AM3, str2_F10_Am3_40, sizeof (str2_F10_Am3_40)}, - {1, 0, 0x05, DR_SOCKET_AM3, str2_F10_Am3_50, sizeof (str2_F10_Am3_50)}, - {1, 0, 0x06, DR_SOCKET_AM3, str2_F10_Am3_60, sizeof (str2_F10_Am3_60)}, - {1, 0, 0x07, DR_SOCKET_AM3, str2_F10_Am3_70, sizeof (str2_F10_Am3_70)}, - {1, 0, 0x08, DR_SOCKET_AM3, str2_F10_Am3_80, sizeof (str2_F10_Am3_80)}, - {1, 0, 0x09, DR_SOCKET_AM3, str2_F10_Am3_90, sizeof (str2_F10_Am3_90)}, - {1, 0, 0x0A, DR_SOCKET_AM3, str2_F10_Am3_Processor, sizeof (str2_F10_Am3_Processor)}, - {1, 0, 0x0B, DR_SOCKET_AM3, str2_F10_Am3_u_Processor, sizeof (str2_F10_Am3_u_Processor)}, - {1, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, //Size 0 for no suffix - {2, 0, 0x00, DR_SOCKET_AM3, str2_F10_Am3_DC_00, sizeof (str2_F10_Am3_DC_00)}, - {2, 0, 0x01, DR_SOCKET_AM3, str2_F10_Am3_DC_00e, sizeof (str2_F10_Am3_DC_00e)}, - {2, 0, 0x02, DR_SOCKET_AM3, str2_F10_Am3_DC_00B, sizeof (str2_F10_Am3_DC_00B)}, - {2, 0, 0x03, DR_SOCKET_AM3, str2_F10_Am3_DC_50, sizeof (str2_F10_Am3_DC_50)}, - {2, 0, 0x04, DR_SOCKET_AM3, str2_F10_Am3_DC_50e, sizeof (str2_F10_Am3_DC_50e)}, - {2, 0, 0x05, DR_SOCKET_AM3, str2_F10_Am3_DC_50B, sizeof (str2_F10_Am3_DC_50B)}, - {2, 0, 0x06, DR_SOCKET_AM3, str2_F10_Am3_Processor, sizeof (str2_F10_Am3_Processor)}, - {2, 0, 0x07, DR_SOCKET_AM3, str2_F10_Am3_e_Processor, sizeof (str2_F10_Am3_e_Processor)}, - {2, 0, 0x08, DR_SOCKET_AM3, str2_F10_Am3_B_Processor, sizeof (str2_F10_Am3_B_Processor)}, - {2, 0, 0x09, DR_SOCKET_AM3, str2_F10_Am3_0_Processor, sizeof (str2_F10_Am3_0_Processor)}, - {2, 0, 0x0A, DR_SOCKET_AM3, str2_F10_Am3_0e_Processor, sizeof (str2_F10_Am3_0e_Processor)}, - {2, 0, 0x0B, DR_SOCKET_AM3, str2_F10_Am3_u_Processor, sizeof (str2_F10_Am3_u_Processor)}, - {2, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, // Size 0 for no suffix - {2, 1, 0x01, DR_SOCKET_AM3, str2_F10_Am3_L_Processor, sizeof (str2_F10_Am3_L_Processor)}, - {2, 1, 0x02, DR_SOCKET_AM3, str2_F10_Am3_C_Processor, sizeof (str2_F10_Am3_C_Processor)}, - {3, 0, 0x00, DR_SOCKET_AM3, str2_F10_Am3_TC_00, sizeof (str2_F10_Am3_TC_00)}, - {3, 0, 0x01, DR_SOCKET_AM3, str2_F10_Am3_TC_00e, sizeof (str2_F10_Am3_TC_00e)}, - {3, 0, 0x02, DR_SOCKET_AM3, str2_F10_Am3_TC_00B, sizeof (str2_F10_Am3_TC_00B)}, - {3, 0, 0x03, DR_SOCKET_AM3, str2_F10_Am3_TC_50, sizeof (str2_F10_Am3_TC_50)}, - {3, 0, 0x04, DR_SOCKET_AM3, str2_F10_Am3_TC_50e, sizeof (str2_F10_Am3_TC_50e)}, - {3, 0, 0x05, DR_SOCKET_AM3, str2_F10_Am3_TC_50B, sizeof (str2_F10_Am3_TC_50B)}, - {3, 0, 0x06, DR_SOCKET_AM3, str2_F10_Am3_Processor, sizeof (str2_F10_Am3_Processor)}, - {3, 0, 0x07, DR_SOCKET_AM3, str2_F10_Am3_e_Processor, sizeof (str2_F10_Am3_e_Processor)}, - {3, 0, 0x08, DR_SOCKET_AM3, str2_F10_Am3_B_Processor, sizeof (str2_F10_Am3_B_Processor)}, - {3, 0, 0x09, DR_SOCKET_AM3, str2_F10_Am3_0e_Processor, sizeof (str2_F10_Am3_0e_Processor)}, - {3, 0, 0x0A, DR_SOCKET_AM3, str2_F10_Am3_0_Processor, sizeof (str2_F10_Am3_0_Processor)}, - {3, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, //Size 0 for no suffix - {4, 0, 0x00, DR_SOCKET_AM3, str2_F10_Am3_QC_00, sizeof (str2_F10_Am3_QC_00)}, - {4, 0, 0x01, DR_SOCKET_AM3, str2_F10_Am3_QC_00e, sizeof (str2_F10_Am3_QC_00e)}, - {4, 0, 0x02, DR_SOCKET_AM3, str2_F10_Am3_QC_00B, sizeof (str2_F10_Am3_QC_00B)}, - {4, 0, 0x03, DR_SOCKET_AM3, str2_F10_Am3_QC_50, sizeof (str2_F10_Am3_QC_50)}, - {4, 0, 0x04, DR_SOCKET_AM3, str2_F10_Am3_QC_50e, sizeof (str2_F10_Am3_QC_50e)}, - {4, 0, 0x05, DR_SOCKET_AM3, str2_F10_Am3_QC_50B, sizeof (str2_F10_Am3_QC_50B)}, - {4, 0, 0x06, DR_SOCKET_AM3, str2_F10_Am3_Processor, sizeof (str2_F10_Am3_Processor)}, - {4, 0, 0x07, DR_SOCKET_AM3, str2_F10_Am3_e_Processor, sizeof (str2_F10_Am3_e_Processor)}, - {4, 0, 0x08, DR_SOCKET_AM3, str2_F10_Am3_B_Processor, sizeof (str2_F10_Am3_B_Processor)}, - {4, 0, 0x09, DR_SOCKET_AM3, str2_F10_Am3_0e_Processor, sizeof (str2_F10_Am3_0e_Processor)}, - {4, 0, 0x0A, DR_SOCKET_AM3, str2_F10_Am3_SE, sizeof (str2_F10_Am3_SE)}, - {4, 0, 0x0B, DR_SOCKET_AM3, str2_F10_Am3_HE, sizeof (str2_F10_Am3_HE)}, - {4, 0, 0x0C, DR_SOCKET_AM3, str2_F10_Am3_EE, sizeof (str2_F10_Am3_EE)}, - {4, 0, 0x0D, DR_SOCKET_AM3, str2_F10_Am3_QCP, sizeof (str2_F10_Am3_QCP)}, - {4, 0, 0x0E, DR_SOCKET_AM3, str2_F10_Am3_0_Processor, sizeof (str2_F10_Am3_0_Processor)}, - {4, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, //Size 0 for no suffix - {4, 1, 0x00, DR_SOCKET_AM3, str2_F10_Am3_TWKR_Black_Edition, sizeof (str2_F10_Am3_TWKR_Black_Edition)}, - {4, 1, 0x01, DR_SOCKET_AM3, str2_F10_Am3_L_Processor, sizeof (str2_F10_Am3_L_Processor)}, - {4, 1, 0x04, DR_SOCKET_AM3, str2_F10_Am3_QC_T, sizeof (str2_F10_Am3_QC_T)}, - {6, 0, 0x00, DR_SOCKET_AM3, str2_F10_Am3_SC_5T, sizeof (str2_F10_Am3_SC_5T)}, - {6, 0, 0x01, DR_SOCKET_AM3, str2_F10_Am3_SC_0T, sizeof (str2_F10_Am3_SC_0T)}, - {6, 0, 0x0F, DR_SOCKET_AM3, 0, 0} //Size 0 for no suffix -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3 = { - (sizeof (CpuF10BrandIdString1ArrayAm3) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString1ArrayAm3 -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3 = { - (sizeof (CpuF10BrandIdString2ArrayAm3) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString2ArrayAm3 -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c deleted file mode 100644 index 50e5d0397c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c +++ /dev/null @@ -1,136 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures for package ASB2. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// String1 -CONST CHAR8 ROMDATA str_F10_Asb2_AMD_V[] = "AMD V"; -CONST CHAR8 ROMDATA str_F10_Asb2_Athlon_II_Neo_K[] = "AMD Athlon(tm) II Neo K"; -CONST CHAR8 ROMDATA str_F10_Asb2_Athlon_II_Neo_N[] = "AMD Athlon(tm) II Neo N"; -CONST CHAR8 ROMDATA str_F10_Asb2_Athlon_II_Neo_R[] = "AMD Athlon(tm) II Neo R"; -CONST CHAR8 ROMDATA str_F10_Asb2_Turion_II_Neo_K[] = "AMD Turion(tm) II Neo K"; -CONST CHAR8 ROMDATA str_F10_Asb2_Turion_II_Neo_N[] = "AMD Turion(tm) II Neo N"; - -// String2 -CONST CHAR8 ROMDATA str_F10_Asb2_5_Processor[] = "5 Processor"; -CONST CHAR8 ROMDATA str_F10_Asb2_5_Dual_Core_Processor[] = "5 Dual-Core Processor"; -CONST CHAR8 ROMDATA str_F10_Asb2_L_Processor[] = "L Processor"; -CONST CHAR8 ROMDATA str_F10_Asb2_L_Dual_Core_Processor[] = "L Dual-Core Processor"; -CONST CHAR8 ROMDATA str_F10_Asb2_H_Dual_Core_Processor[] = "H Dual-Core Processor"; - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayAsb2[] = -{ - // ASB2 - {1, 0, 1, DR_SOCKET_ASB2, str_F10_Asb2_Athlon_II_Neo_K, sizeof (str_F10_Asb2_Athlon_II_Neo_K)}, - {1, 0, 2, DR_SOCKET_ASB2, str_F10_Asb2_AMD_V, sizeof (str_F10_Asb2_AMD_V)}, - {1, 0, 3, DR_SOCKET_ASB2, str_F10_Asb2_Athlon_II_Neo_R, sizeof (str_F10_Asb2_Athlon_II_Neo_R)}, - {2, 0, 1, DR_SOCKET_ASB2, str_F10_Asb2_Turion_II_Neo_K, sizeof (str_F10_Asb2_Turion_II_Neo_K)}, - {2, 0, 2, DR_SOCKET_ASB2, str_F10_Asb2_Athlon_II_Neo_K, sizeof (str_F10_Asb2_Athlon_II_Neo_K)}, - {2, 0, 3, DR_SOCKET_ASB2, str_F10_Asb2_AMD_V, sizeof (str_F10_Asb2_AMD_V)}, - {2, 0, 4, DR_SOCKET_ASB2, str_F10_Asb2_Turion_II_Neo_N, sizeof (str_F10_Asb2_Turion_II_Neo_N)}, - {2, 0, 5, DR_SOCKET_ASB2, str_F10_Asb2_Athlon_II_Neo_N, sizeof (str_F10_Asb2_Athlon_II_Neo_N)} -}; //Cores, page, index, socket, stringstart, stringlength - - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayAsb2[] = -{ - // ASB2 - {1, 0, 0x01, DR_SOCKET_ASB2, str_F10_Asb2_5_Processor, sizeof (str_F10_Asb2_5_Processor)}, - {1, 0, 0x02, DR_SOCKET_ASB2, str_F10_Asb2_L_Processor, sizeof (str_F10_Asb2_L_Processor)}, - {2, 0, 0x01, DR_SOCKET_ASB2, str_F10_Asb2_5_Dual_Core_Processor, sizeof (str_F10_Asb2_5_Dual_Core_Processor)}, - {2, 0, 0x02, DR_SOCKET_ASB2, str_F10_Asb2_L_Dual_Core_Processor, sizeof (str_F10_Asb2_L_Dual_Core_Processor)}, - {2, 0, 0x04, DR_SOCKET_ASB2, str_F10_Asb2_H_Dual_Core_Processor, sizeof (str_F10_Asb2_H_Dual_Core_Processor)}, - {1, 0, 0x0F, DR_SOCKET_ASB2, 0, 0}, //Size 0 for no suffix - {2, 0, 0x0F, DR_SOCKET_ASB2, 0, 0}, //Size 0 for no suffix -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2 = { - (sizeof (CpuF10BrandIdString1ArrayAsb2) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString1ArrayAsb2 -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2 = { - (sizeof (CpuF10BrandIdString2ArrayAsb2) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString2ArrayAsb2 -}; - - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c deleted file mode 100644 index c5a6fe19d6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c +++ /dev/null @@ -1,135 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures for socket C32. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY - -// String1 -CONST CHAR8 ROMDATA str_F10_C32_Opteron_41[] = "AMD Opteron(tm) Processor 41"; -CONST CHAR8 ROMDATA str_F10_C32_Embedded_Opteron[] = "Embedded AMD Opteron(tm) Processor "; - -// String2 -CONST CHAR8 ROMDATA str2_F10_C32_HE[] = " HE"; -CONST CHAR8 ROMDATA str2_F10_C32_EE[] = " EE"; -CONST CHAR8 ROMDATA str2_F10_C32_QS_HE[] = "QS HE"; -CONST CHAR8 ROMDATA str2_F10_C32_LE_HE[] = "LE HE"; -CONST CHAR8 ROMDATA str2_F10_C32_KX_HE[] = "KX HE"; -CONST CHAR8 ROMDATA str2_F10_C32_GL_EE[] = "GL EE"; -CONST CHAR8 ROMDATA str2_F10_C32_CL_EE[] = "CL EE"; - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayC32[] = -{ - // C32r1 string1: - {4, 0, 0x00, DR_SOCKET_C32, str_F10_C32_Opteron_41, sizeof (str_F10_C32_Opteron_41)}, - {4, 1, 0x01, DR_SOCKET_C32, str_F10_C32_Embedded_Opteron, sizeof (str_F10_C32_Embedded_Opteron)}, - {6, 0, 0x00, DR_SOCKET_C32, str_F10_C32_Opteron_41, sizeof (str_F10_C32_Opteron_41)}, - {6, 1, 0x01, DR_SOCKET_C32, str_F10_C32_Embedded_Opteron, sizeof (str_F10_C32_Embedded_Opteron)} -}; //Cores, page, index, socket, stringstart, stringlength - - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayC32[] = -{ - // C32r1 string2: - {4, 0, 0x00, DR_SOCKET_C32, str2_F10_C32_HE, sizeof (str2_F10_C32_HE)}, - {4, 0, 0x01, DR_SOCKET_C32, str2_F10_C32_EE, sizeof (str2_F10_C32_EE)}, - {4, 0, 0x0F, DR_SOCKET_C32, 0, 0}, //Size 0 for no suffix - {4, 1, 0x01, DR_SOCKET_C32, str2_F10_C32_QS_HE, sizeof (str2_F10_C32_QS_HE)}, - {4, 1, 0x02, DR_SOCKET_C32, str2_F10_C32_LE_HE, sizeof (str2_F10_C32_LE_HE)}, - {4, 1, 0x03, DR_SOCKET_C32, str2_F10_C32_CL_EE, sizeof (str2_F10_C32_CL_EE)}, - {6, 0, 0x00, DR_SOCKET_C32, str2_F10_C32_HE, sizeof (str2_F10_C32_HE)}, - {6, 0, 0x01, DR_SOCKET_C32, str2_F10_C32_EE, sizeof (str2_F10_C32_EE)}, - {6, 0, 0x0F, DR_SOCKET_C32, 0, 0}, //Size 0 for no suffix - {6, 1, 0x01, DR_SOCKET_C32, str2_F10_C32_KX_HE, sizeof (str2_F10_C32_KX_HE)}, - {6, 1, 0x02, DR_SOCKET_C32, str2_F10_C32_GL_EE, sizeof (str2_F10_C32_GL_EE)} -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32 = { - (sizeof (CpuF10BrandIdString1ArrayC32) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString1ArrayC32 -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32 = { - (sizeof (CpuF10BrandIdString2ArrayC32) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString2ArrayC32 -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c deleted file mode 100644 index 4c87430406..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c +++ /dev/null @@ -1,179 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures for socket Fr1207. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY - -// String1 -/*CHAR8 strEngSample[] = "AMD Engineering Sample"; -CHAR8 strTtkSample[] = "AMD Thermal Test Kit"; -CHAR8 strUnknown[] = "AMD Processor model unknown"; -*/ -CONST CHAR8 ROMDATA str_F10_Fr1207_DC_Opteron83[] = "Dual-Core AMD Opteron(tm) Processor 83"; -CONST CHAR8 ROMDATA str_F10_Fr1207_DC_Opteron23[] = "Dual-Core AMD Opteron(tm) Processor 23"; -CONST CHAR8 ROMDATA str_F10_Fr1207_QC_Opteron83[] = "Quad-Core AMD Opteron(tm) Processor 83"; -CONST CHAR8 ROMDATA str_F10_Fr1207_QC_Opteron23[] = "Quad-Core AMD Opteron(tm) Processor 23"; -CONST CHAR8 ROMDATA str_F10_Fr1207_eQC_Opteron83[] = "Embedded AMD Opteron(tm) Processor 83"; -CONST CHAR8 ROMDATA str_F10_Fr1207_eQC_Opteron23[] = "Embedded AMD Opteron(tm) Processor 23"; -CONST CHAR8 ROMDATA str_F10_Fr1207_eQC_Opteron13[] = "Embedded AMD Opteron(tm) Processor 13"; -CONST CHAR8 ROMDATA str_F10_Fr1207_Embedded_Opteron[] = "Embedded AMD Opteron(tm) Processor "; -CONST CHAR8 ROMDATA str_F10_Fr1207_SC_Opteron84[] = "Six-Core AMD Opteron(tm) Processor 84"; -CONST CHAR8 ROMDATA str_F10_Fr1207_SC_Opteron24[] = "Six-Core AMD Opteron(tm) Processor 24"; - -CONST CHAR8 ROMDATA str_F10_Fr1207_PhenomFX[] = "AMD Phenom(tm) FX-"; - - -// String2 -CONST CHAR8 ROMDATA str2_F10_Fr1207_SE[] = " SE"; -CONST CHAR8 ROMDATA str2_F10_Fr1207_HE[] = " HE"; -CONST CHAR8 ROMDATA str2_F10_Fr1207_EE[] = " EE"; -CONST CHAR8 ROMDATA str2_F10_Fr1207_VS[] = "VS"; -CONST CHAR8 ROMDATA str2_F10_Fr1207_QS[] = "QS"; - -CONST CHAR8 ROMDATA str2_F10_Fr1207_NP_HE[] = "NP HE"; -CONST CHAR8 ROMDATA str2_F10_Fr1207_GF_HE[] = "GF HE"; -CONST CHAR8 ROMDATA str2_F10_Fr1207_HF_HE[] = "HF HE"; -CONST CHAR8 ROMDATA str2_F10_Fr1207_QS_HE[] = "QS HE"; -CONST CHAR8 ROMDATA str2_F10_Fr1207_KH_HE[] = "KH HE"; -CONST CHAR8 ROMDATA str2_F10_Fr1207_KS_EE[] = "KS EE"; -CONST CHAR8 ROMDATA str2_F10_Fr1207_KS_HE[] = "KS HE"; - -CONST CHAR8 ROMDATA str2_F10_Fr1207_QCP[] = " Quad-Core Processor"; - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayFr1207[] = -{ - // FR2/FR4 1207 - {2, 0, 0, DR_SOCKET_1207, str_F10_Fr1207_DC_Opteron83, sizeof (str_F10_Fr1207_DC_Opteron83)}, - {2, 0, 1, DR_SOCKET_1207, str_F10_Fr1207_DC_Opteron23, sizeof (str_F10_Fr1207_DC_Opteron23)}, - {3, 0, 0, DR_SOCKET_1207, str_F10_Fr1207_Embedded_Opteron, sizeof (str_F10_Fr1207_Embedded_Opteron)}, - {4, 0, 0, DR_SOCKET_1207, str_F10_Fr1207_QC_Opteron83, sizeof (str_F10_Fr1207_QC_Opteron83)}, - {4, 0, 1, DR_SOCKET_1207, str_F10_Fr1207_QC_Opteron23, sizeof (str_F10_Fr1207_QC_Opteron23)}, - {4, 0, 2, DR_SOCKET_1207, str_F10_Fr1207_eQC_Opteron83, sizeof (str_F10_Fr1207_eQC_Opteron83)}, - {4, 0, 3, DR_SOCKET_1207, str_F10_Fr1207_eQC_Opteron23, sizeof (str_F10_Fr1207_eQC_Opteron23)}, - {4, 0, 4, DR_SOCKET_1207, str_F10_Fr1207_eQC_Opteron13, sizeof (str_F10_Fr1207_eQC_Opteron13)}, - {4, 0, 5, DR_SOCKET_1207, str_F10_Fr1207_PhenomFX, sizeof (str_F10_Fr1207_PhenomFX)}, - {4, 1, 1, DR_SOCKET_1207, str_F10_Fr1207_Embedded_Opteron, sizeof (str_F10_Fr1207_Embedded_Opteron)}, - {6, 0, 0, DR_SOCKET_1207, str_F10_Fr1207_SC_Opteron84, sizeof (str_F10_Fr1207_SC_Opteron84)}, - {6, 0, 1, DR_SOCKET_1207, str_F10_Fr1207_SC_Opteron24, sizeof (str_F10_Fr1207_SC_Opteron24)}, - {6, 1, 1, DR_SOCKET_1207, str_F10_Fr1207_Embedded_Opteron, sizeof (str_F10_Fr1207_Embedded_Opteron)}, -}; //Cores, page, index, socket, stringstart, stringlength - - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayFr1207[] = -{ - // FR2/FR4 1207 - {2, 0, 0x0A, DR_SOCKET_1207, str2_F10_Fr1207_SE, sizeof (str2_F10_Fr1207_SE)}, - {2, 0, 0x0B, DR_SOCKET_1207, str2_F10_Fr1207_HE, sizeof (str2_F10_Fr1207_HE)}, - {2, 0, 0x0C, DR_SOCKET_1207, str2_F10_Fr1207_EE, sizeof (str2_F10_Fr1207_EE)}, - {2, 0, 0x0F, DR_SOCKET_1207, 0, 0}, //Size 0 for no suffix - {3, 0, 0x00, DR_SOCKET_1207, str2_F10_Fr1207_NP_HE, sizeof (str2_F10_Fr1207_NP_HE)}, - {3, 0, 0x0F, DR_SOCKET_1207, 0, 0}, //Size 0 for no suffix - {4, 0, 0x0A, DR_SOCKET_1207, str2_F10_Fr1207_SE, sizeof (str2_F10_Fr1207_SE)}, - {4, 0, 0x0B, DR_SOCKET_1207, str2_F10_Fr1207_HE, sizeof (str2_F10_Fr1207_HE)}, - {4, 0, 0x0C, DR_SOCKET_1207, str2_F10_Fr1207_EE, sizeof (str2_F10_Fr1207_EE)}, - {4, 0, 0x0D, DR_SOCKET_1207, str2_F10_Fr1207_QCP, sizeof (str2_F10_Fr1207_QCP)}, - {4, 0, 0x0F, DR_SOCKET_1207, 0, 0}, //Size 0 for no suffix - {4, 1, 0x01, DR_SOCKET_1207, str2_F10_Fr1207_GF_HE, sizeof (str2_F10_Fr1207_GF_HE)}, - {4, 1, 0x02, DR_SOCKET_1207, str2_F10_Fr1207_HF_HE, sizeof (str2_F10_Fr1207_HF_HE)}, - {4, 1, 0x03, DR_SOCKET_1207, str2_F10_Fr1207_VS, sizeof (str2_F10_Fr1207_VS)}, - {4, 1, 0x04, DR_SOCKET_1207, str2_F10_Fr1207_QS_HE, sizeof (str2_F10_Fr1207_QS_HE)}, - {4, 1, 0x05, DR_SOCKET_1207, str2_F10_Fr1207_NP_HE, sizeof (str2_F10_Fr1207_NP_HE)}, - {4, 1, 0x06, DR_SOCKET_1207, str2_F10_Fr1207_KH_HE, sizeof (str2_F10_Fr1207_KH_HE)}, - {4, 1, 0x07, DR_SOCKET_1207, str2_F10_Fr1207_KS_EE, sizeof (str2_F10_Fr1207_KS_EE)}, - {6, 0, 0x00, DR_SOCKET_1207, str2_F10_Fr1207_SE, sizeof (str2_F10_Fr1207_SE)}, - {6, 0, 0x01, DR_SOCKET_1207, str2_F10_Fr1207_HE, sizeof (str2_F10_Fr1207_HE)}, - {6, 0, 0x02, DR_SOCKET_1207, str2_F10_Fr1207_EE, sizeof (str2_F10_Fr1207_EE)}, - {6, 0, 0x0F, DR_SOCKET_1207, 0, 0}, //Size 0 for no suffix - {6, 1, 0x01, DR_SOCKET_1207, str2_F10_Fr1207_QS, sizeof (str2_F10_Fr1207_QS)}, - {6, 1, 0x02, DR_SOCKET_1207, str2_F10_Fr1207_KS_HE, sizeof (str2_F10_Fr1207_KS_HE)}, -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayFr1207 = { - (sizeof (CpuF10BrandIdString1ArrayFr1207) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString1ArrayFr1207 -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayFr1207 = { - (sizeof (CpuF10BrandIdString2ArrayFr1207) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString2ArrayFr1207 -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c deleted file mode 100644 index 0df104e12d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c +++ /dev/null @@ -1,127 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures for socket G34. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY - -// String1 -CONST CHAR8 ROMDATA str_F10_G34_Opteron_61[] = "AMD Opteron(tm) Processor 61"; -CONST CHAR8 ROMDATA str_F10_G34_Embedded_Opteron[] = "Embedded AMD Opteron(tm) Processor "; - -// String2 -CONST CHAR8 ROMDATA str2_F10_G34_SE[] = " SE"; -CONST CHAR8 ROMDATA str2_F10_G34_HE[] = " HE"; -CONST CHAR8 ROMDATA str2_F10_G34_QS[] = "QS"; -CONST CHAR8 ROMDATA str2_F10_G34_KS[] = "KS"; - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayG34[] = -{ - // G34r1 string1: - {8, 0, 0x00, DR_SOCKET_G34, str_F10_G34_Opteron_61, sizeof (str_F10_G34_Opteron_61)}, - {8, 1, 0x01, DR_SOCKET_G34, str_F10_G34_Embedded_Opteron, sizeof (str_F10_G34_Embedded_Opteron)}, - {12, 0, 0x00, DR_SOCKET_G34, str_F10_G34_Opteron_61, sizeof (str_F10_G34_Opteron_61)} -}; //Cores, page, index, socket, stringstart, stringlength - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayG34[] = -{ - // G34r1 string2: - {8, 0, 0x00, DR_SOCKET_G34, str2_F10_G34_HE, sizeof (str2_F10_G34_HE)}, - {8, 0, 0x01, DR_SOCKET_G34, str2_F10_G34_SE, sizeof (str2_F10_G34_SE)}, - {8, 1, 0x01, DR_SOCKET_G34, str2_F10_G34_QS, sizeof (str2_F10_G34_QS)}, - {8, 1, 0x02, DR_SOCKET_G34, str2_F10_G34_KS, sizeof (str2_F10_G34_KS)}, - {8, 0, 0x0F, DR_SOCKET_G34, 0, 0}, //Size 0 for no suffix - {12, 0, 0x00, DR_SOCKET_G34, str2_F10_G34_HE, sizeof (str2_F10_G34_HE)}, - {12, 0, 0x01, DR_SOCKET_G34, str2_F10_G34_SE, sizeof (str2_F10_G34_SE)}, - {12, 0, 0x0F, DR_SOCKET_G34, 0, 0} //Size 0 for no suffix -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34 = { - (sizeof (CpuF10BrandIdString1ArrayG34) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString1ArrayG34 -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34 = { - (sizeof (CpuF10BrandIdString2ArrayG34) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString2ArrayG34 -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c deleted file mode 100644 index c2f8f6981a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c +++ /dev/null @@ -1,128 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures for socket S1g3. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY - -// String1 -/*CHAR8 strEngSample[] = "AMD Engineering Sample"; -CHAR8 strTtkSample[] = "AMD Thermal Test Kit"; -CHAR8 strUnknown[] = "AMD Processor model unknown"; -*/ -// S1g3 NC 0 -CONST CHAR8 ROMDATA str_F10_S1g3_Sempron_M1[] = "AMD Sempron(tm) M1"; - -// S1g3 NC 1 -CONST CHAR8 ROMDATA str_F10_S1g3_Turion_II_U_DC_M_M6[] = "AMD Turion(tm) II Ultra Dual-Core Mobile M6"; -CONST CHAR8 ROMDATA str_F10_S1g3_Turion_II_DC_M_M5[] = "AMD Turion(tm) II Dual-Core Mobile M5"; -CONST CHAR8 ROMDATA str_F10_S1g3_Athlon_II_DC_M3[] = "AMD Athlon(tm) II Dual-Core M3"; - -// String2 - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayS1g3[] = -{ - // S1g3 - {1, 0, 0, DR_SOCKET_S1G3, str_F10_S1g3_Sempron_M1, sizeof (str_F10_S1g3_Sempron_M1)}, - {2, 0, 0, DR_SOCKET_S1G3, str_F10_S1g3_Turion_II_U_DC_M_M6, sizeof (str_F10_S1g3_Turion_II_U_DC_M_M6)}, - {2, 0, 1, DR_SOCKET_S1G3, str_F10_S1g3_Turion_II_DC_M_M5, sizeof (str_F10_S1g3_Turion_II_DC_M_M5)}, - {2, 0, 2, DR_SOCKET_S1G3, str_F10_S1g3_Athlon_II_DC_M3, sizeof (str_F10_S1g3_Athlon_II_DC_M3)} -}; //Cores, page, index, socket, stringstart, stringlength - - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayS1g3[] = -{ - // S1g3 - {1, 0, 0x0F, DR_SOCKET_S1G3, 0, 0}, //Size 0 for no suffix - {2, 0, 0x0F, DR_SOCKET_S1G3, 0, 0} //Size 0 for no suffix -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3 = { - (sizeof (CpuF10BrandIdString1ArrayS1g3) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString1ArrayS1g3 -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3 = { - (sizeof (CpuF10BrandIdString2ArrayS1g3) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString2ArrayS1g3 -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c deleted file mode 100644 index 6ec940e147..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c +++ /dev/null @@ -1,142 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures for package S1g4. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// String1 -CONST CHAR8 ROMDATA str_F10_S1g4_AMD_V[] = "AMD V"; -CONST CHAR8 ROMDATA str_F10_S1g4_Turion_II_P[] = "AMD Turion(tm) II P"; -CONST CHAR8 ROMDATA str_F10_S1g4_Athlon_II_P[] = "AMD Athlon(tm) II P"; -CONST CHAR8 ROMDATA str_F10_S1g4_Phenom_II_X[] = "AMD Phenom(tm) II X"; -CONST CHAR8 ROMDATA str_F10_S1g4_Turion_II_N[] = "AMD Turion(tm) II N"; -CONST CHAR8 ROMDATA str_F10_S1g4_Athlon_II_N[] = "AMD Athlon(tm) II N"; -CONST CHAR8 ROMDATA str_F10_S1g4_Phenom_II_P[] = "AMD Phenom(tm) II P"; -CONST CHAR8 ROMDATA str_F10_S1g4_Phenom_II_N[] = "AMD Phenom(tm) II N"; - -// String2 -CONST CHAR8 ROMDATA str_F10_S1g4_0_Processor[] = "0 Processor"; -CONST CHAR8 ROMDATA str_F10_S1g4_0_Dual_Core_Processor[] = "0 Dual-Core Processor"; -CONST CHAR8 ROMDATA str_F10_S1g4_0_Triple_Core_Processor[] = "0 Triple-Core Processor"; -CONST CHAR8 ROMDATA str_F10_S1g4_0_Quad_Core_Processor[] = "0 Quad-Core Processor"; - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayS1g4[] = -{ - // S1g4 - {1, 0, 1, DR_SOCKET_S1G4, str_F10_S1g4_AMD_V, sizeof (str_F10_S1g4_AMD_V)}, - {2, 0, 3, DR_SOCKET_S1G4, str_F10_S1g4_Turion_II_P, sizeof (str_F10_S1g4_Turion_II_P)}, - {2, 0, 4, DR_SOCKET_S1G4, str_F10_S1g4_Athlon_II_P, sizeof (str_F10_S1g4_Athlon_II_P)}, - {2, 0, 5, DR_SOCKET_S1G4, str_F10_S1g4_Phenom_II_X, sizeof (str_F10_S1g4_Phenom_II_X)}, - {2, 0, 6, DR_SOCKET_S1G4, str_F10_S1g4_Phenom_II_N, sizeof (str_F10_S1g4_Phenom_II_N)}, - {2, 0, 7, DR_SOCKET_S1G4, str_F10_S1g4_Turion_II_N, sizeof (str_F10_S1g4_Turion_II_N)}, - {2, 0, 8, DR_SOCKET_S1G4, str_F10_S1g4_Athlon_II_N, sizeof (str_F10_S1g4_Athlon_II_N)}, - {2, 0, 9, DR_SOCKET_S1G4, str_F10_S1g4_Phenom_II_P, sizeof (str_F10_S1g4_Phenom_II_P)}, - {3, 0, 2, DR_SOCKET_S1G4, str_F10_S1g4_Phenom_II_P, sizeof (str_F10_S1g4_Phenom_II_P)}, - {3, 0, 3, DR_SOCKET_S1G4, str_F10_S1g4_Phenom_II_N, sizeof (str_F10_S1g4_Phenom_II_N)}, - {3, 0, 4, DR_SOCKET_S1G4, str_F10_S1g4_Phenom_II_X, sizeof (str_F10_S1g4_Phenom_II_X)}, - {4, 0, 1, DR_SOCKET_S1G4, str_F10_S1g4_Phenom_II_P, sizeof (str_F10_S1g4_Phenom_II_P)}, - {4, 0, 2, DR_SOCKET_S1G4, str_F10_S1g4_Phenom_II_X, sizeof (str_F10_S1g4_Phenom_II_X)}, - {4, 0, 3, DR_SOCKET_S1G4, str_F10_S1g4_Phenom_II_N, sizeof (str_F10_S1g4_Phenom_II_N)} -}; //Cores, page, index, socket, stringstart, stringlength - - -CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayS1g4[] = -{ - // S1g4 - {1, 0, 0x01, DR_SOCKET_S1G4, str_F10_S1g4_0_Processor, sizeof (str_F10_S1g4_0_Processor)}, - {2, 0, 0x02, DR_SOCKET_S1G4, str_F10_S1g4_0_Dual_Core_Processor, sizeof (str_F10_S1g4_0_Dual_Core_Processor)}, - {3, 0, 0x02, DR_SOCKET_S1G4, str_F10_S1g4_0_Triple_Core_Processor, sizeof (str_F10_S1g4_0_Triple_Core_Processor)}, - {4, 0, 0x01, DR_SOCKET_S1G4, str_F10_S1g4_0_Quad_Core_Processor, sizeof (str_F10_S1g4_0_Quad_Core_Processor)}, - {1, 0, 0x0F, DR_SOCKET_S1G4, 0, 0}, //Size 0 for no suffix - {2, 0, 0x0F, DR_SOCKET_S1G4, 0, 0}, //Size 0 for no suffix - {3, 0, 0x0F, DR_SOCKET_S1G4, 0, 0}, //Size 0 for no suffix - {4, 0, 0x0F, DR_SOCKET_S1G4, 0, 0} //Size 0 for no suffix -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4 = { - (sizeof (CpuF10BrandIdString1ArrayS1g4) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString1ArrayS1g4 -}; - - -CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4 = { - (sizeof (CpuF10BrandIdString2ArrayS1g4) / sizeof (AMD_CPU_BRAND)), - CpuF10BrandIdString2ArrayS1g4 -}; - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c deleted file mode 100644 index 6ba8ed8aa3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c +++ /dev/null @@ -1,131 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 ROM Execution Cache Defaults - * - * Contains default values for ROM execution cache setup - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuCacheInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -GetF10CacheInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **CacheInfoPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -#define MEM_TRAINING_BUFFER_SIZE 16384 -#define VAR_MTRR_MASK 0x0000FFFFFFFFFFFF -#define VAR_MTRR_MASK_CP VAR_MTRR_MASK - -#define HEAP_BASE_MASK 0x0000FFFFFFFFFFFF - -#define SHARED_MEM_SIZE 0 - -CONST CACHE_INFO ROMDATA CpuF10CacheInfo = -{ - BSP_STACK_SIZE_32K, - CORE0_STACK_SIZE, - CORE1_STACK_SIZE, - MEM_TRAINING_BUFFER_SIZE, - SHARED_MEM_SIZE, - VAR_MTRR_MASK, - VAR_MTRR_MASK, - HEAP_BASE_MASK, - LimitedByL2Size -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the family specific properties of the cache, and its usage. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] CacheInfoPtr Points to the cache info properties on exit. - * @param[out] NumberOfElements Will be one to indicate one entry. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF10CacheInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **CacheInfoPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = 1; - *CacheInfoPtr = &CpuF10CacheInfo; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c deleted file mode 100644 index f48932d7e3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c +++ /dev/null @@ -1,167 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Cache Flush On Halt Function. - * - * Contains code to initialize Cache Flush On Halt feature for Family 10h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - *---------------------------------------------------------------------------- - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuPostInit.h" -#include "cpuFeatures.h" -#include "OptionMultiSocket.h" -#include "cpuF10PowerMgmt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -SetF10CacheFlushOnHaltRegister ( - IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * Enable Cpu Cache Flush On Halt Function - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - */ -VOID -SetF10CacheFlushOnHaltRegister ( - IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 AndMask; - UINT32 OrMask; - UINT32 CoreCount; - UINT32 CpbControl; - CPU_LOGICAL_ID LogicalId; - PCI_ADDR PciAddress; - PCI_ADDR CpbCtrlRegister; - - if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { - // Initialize F3xDC - // bits[25:19] CacheFlushOnHaltTmr = 28h - // bits[18:16] CacheFlushOnHaltCtl = 111b - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG; - AndMask = 0xFC00FFFF; - OrMask = 0x01470000; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - if ((LogicalId.Revision & AMD_F10_C2) != 0) { - //For F10_C2 single Core, F3xDC[18:16] = 0 - GetActiveCoresInCurrentSocket (&CoreCount, StdHeader); - if (CoreCount == 1) { - OrMask = 0x01400000; - } - } - - if ((LogicalId.Revision & AMD_F10_PH_ALL) != 0) { - // If Revision E and CPB is enabled - // F3xDC[25:19] CacheFlushOnHaltTmr = Ch - CpbCtrlRegister.AddressValue = CPB_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, CpbCtrlRegister, &CpbControl, StdHeader); - - if (((CPB_CTRL_REGISTER *) (&CpbControl))->BoostSrc == 3) { - OrMask = 0x00670000; - } - } - - IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader); - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); //F3xDC - } -} - -CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt = -{ - 0, - SetF10CacheFlushOnHaltRegister -}; \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Cpb.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Cpb.c deleted file mode 100644 index f329b9b1a8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Cpb.c +++ /dev/null @@ -1,169 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 CPB Initialization - * - * Enables core performance boost. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF10PowerMgmt.h" -#include "cpuFeatures.h" -#include "cpuRegisters.h" -#include "cpuF10Utilities.h" -#include "cpuCpb.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * BSC entry point for checking whether or not CPB is supported. - * - * @param[in] CpbServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] Socket Zero based socket number to check. - * @param[in] StdHeader Config handle for library and services. - * - * @retval TRUE CPB is supported. - * @retval FALSE CPB is not supported. - * - */ -BOOLEAN -STATIC -F10IsCpbSupported ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - - NumBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader); - return (BOOLEAN) (NumBoostStates != 0); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * BSC entry point for for enabling Core Performance Boost. - * - * Set up F4x15C[BoostSrc] and start the PDMs according to the BKDG. - * - * @param[in] CpbServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] EntryPoint Current CPU feature dispatch point. - * @param[in] Socket Zero based socket number to check. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F10InitializeCpb ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT64 EntryPoint, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpbControl; - UINT32 Module; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) { - for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) { - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CPB_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); - ((CPB_CTRL_REGISTER *) (&CpbControl))->BoostSrc = 3; - IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl, StdHeader); - LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = POPUP_PSTATE_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); - ((POPUP_PSTATE_REGISTER *) (&CpbControl))->CacheFlushPopDownEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader); - } - } - return AGESA_SUCCESS; -} - -CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport = -{ - 0, - F10IsCpbSupported, - F10InitializeCpb -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c deleted file mode 100644 index 641b7e7fe3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c +++ /dev/null @@ -1,519 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD DMI Record Creation API, and related functions. - * - * Contains code that produce the DMI related information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 58105 $ @e \$Date: 2011-08-19 17:46:09 -0600 (Fri, 19 Aug 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuLateInit.h" -#include "cpuF10PowerMgmt.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuF10Utilities.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -DmiF10GetInfo ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -DmiF10GetVoltage ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT16 -DmiF10GetMaxSpeed ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT16 -DmiF10GetExtClock ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -DmiF10GetMemInfo ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F10Translate7BitVidTo6Bit ( - IN OUT UINT8 * MaxVidPtr - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF10GetInfo - * - * Get CPU type information - * - * @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct. - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF10GetInfo ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuId; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); - CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20 - CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16 - CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8 - CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4 - CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0 - - CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 - CpuInfoPtr->BrandId.Pg = (UINT8) (CpuId.EBX_Reg >> 15) & 0x1; // bit 15 - CpuInfoPtr->BrandId.String1 = (UINT8) (CpuId.EBX_Reg >> 11) & 0xF; // bit 14:11 - CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4 - CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0 - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader); - CpuInfoPtr->TotalCoreNumber--; - - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader); - CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0 - - switch (CpuInfoPtr->PackageType) { - case DR_SOCKET_1207: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_F1207; - break; - case DR_SOCKET_AM3: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_AM3; - break; - case DR_SOCKET_S1G3: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_S1GX; - break; - case DR_SOCKET_G34: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_G34; - break; - case DR_SOCKET_ASB2: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE; - break; - case DR_SOCKET_C32: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_C32; - break; - default: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN; - break; - } - - LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, StdHeader); - CpuInfoPtr->L1CacheSize = (UINT32) (((UINT8) (CpuId.ECX_Reg >> 24) + (UINT8) (CpuId.EDX_Reg >> 24)) * (CpuInfoPtr->EnabledCoreNumber + 1)); - - LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader); - CpuInfoPtr->L2CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfoPtr->EnabledCoreNumber + 1)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF10GetVoltage - * - * Get the voltage value according to SMBIOS SPEC's requirement. - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval Voltage - CPU Voltage. - * - */ -UINT8 -DmiF10GetVoltage ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxVid; - UINT8 Voltage; - UINT8 NumberBoostStates; - UINT32 Pvimode; - UINT32 CurrentNodeNum; - UINT64 MsrData; - PCI_ADDR TempAddr; - CPU_LOGICAL_ID CpuFamilyRevision; - CPB_CTRL_REGISTER CpbCtrl; - - // Voltage = 0x80 + (voltage at boot time * 10) - GetCurrentNodeNum (&CurrentNodeNum, StdHeader); - TempAddr.AddressValue = MAKE_SBDFO (0, 0, (24 + CurrentNodeNum), FUNC_3, PW_CTL_MISC_REG); - LibAmdPciReadBits (TempAddr, 8, 8, &Pvimode, (VOID *)StdHeader); - //Pvimode is a 1-bit register field: 1-PVI 0-SVI - - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - if ((CpuFamilyRevision.Revision & AMD_F10_PH_ALL) != 0) { - TempAddr.AddressValue = MAKE_SBDFO (0, 0, (24 + CurrentNodeNum), FUNC_4, CPB_CTRL_REG); - LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C - NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates; - } else { - NumberBoostStates = 0; - } - - LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); - MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); - - if (Pvimode) { - // PVI mode - F10Translate7BitVidTo6Bit (&MaxVid); - if (MaxVid >= 0x20) { - Voltage = (UINT8) ((7625 - (125 * (MaxVid - 0x20)) + 500) / 1000); - } else { - Voltage = (UINT8) ((1550 - (25 * MaxVid) + 50) / 100); - } - } else { - // is SVI mode - if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) { - Voltage = 0; - } else { - Voltage = (UINT8) ((15500 - (125 * MaxVid) + 500) / 1000); - } - } - - Voltage += 0x80; - return (Voltage); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF10GetMaxSpeed - * - * Get the Max Speed - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval MaxSpeed - CPU Max Speed. - * - */ -UINT16 -DmiF10GetMaxSpeed ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - UINT32 P0Frequency; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - NumBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader); - - FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader); - return ((UINT16) P0Frequency); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF10GetExtClock - * - * Get the external clock Speed - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval ExtClock - CPU external clock Speed. - * - */ -UINT16 -DmiF10GetExtClock ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (EXTERNAL_CLOCK_DFLT); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF10GetMemInfo - * - * Get memory information. - * - * @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct. - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF10GetMemInfo ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 PciData; - PCI_ADDR PciAddress; - - CpuGetMemInfoPtr->EccCapable = FALSE; - - // DCT 0 - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x90); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - // Check if F2x90[DimmEccEn] is set - if ((PciData & 0x00080000) != 0) { - CpuGetMemInfoPtr->EccCapable = TRUE; - } else { - // DCT 1 - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x190); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - // Check if F2x190[DimmEccEn] is set - if ((PciData & 0x00080000) != 0) { - CpuGetMemInfoPtr->EccCapable = TRUE; - } - } - - // Partition Row Position - 0 is for dual channel memory - CpuGetMemInfoPtr->PartitionRowPosition = 0; -} - -/*--------------------------------------------------------------------------------------- - * Processor Family Table - * - * Note: 'x' means we don't care this field - * 002h = "Unknown" - * 038h = "AMD Turion(TM) II Ultra Dual-Core Mobile M Processor Family" - * 039h = "AMD Turion(TM) II Dual-Core Mobile M Processor Family" - * 03Ah = "AMD Athlon(TM) II Dual-Core M Processor Family" - * 083h = "AMD Athlon(tm) 64 Processor Family" - * 084h = "AMD Opteron(TM) Processor Family" - * 085h = "AMD Sempron(tm) Processor Family" - * 087h = "Dual-Core AMD Opteron Processor Family" - * 08Ah = "Quad-Core AMD Opteron Processor Family" - * 08Ch = "AMD Phenom FX Quad-Core Processor Family" - * 08Dh = "AMD Phenom X4 Quad-Core Processor Family" - * 08Eh = "AMD Phenom X2 Dual-Core Processor Family" - * 08Fh = "AMD Athlon X2 Dual-Core Processor Family" - * 0E6h = "Embedded AMD Opteron Processor Family" - * 0E7h = "AMD Phenom Triple-Core Processor Family" - * 0ECh = "AMD Phenom(TM) II Processor Family" - * 0EDh = "AMD Athlon(TM) II Processor Family" - * 0EEh = "Six-Core AMD Opteron(TM) Processor Family" - * 0EFh = "AMD Sempron(TM) M Processor Family" - *-------------------------------------------------------------------------------------*/ -CONST DMI_BRAND_ENTRY ROMDATA Family10BrandList[] = -{ - // Brand --> DMI ID translation table - // PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable - // {'x', 'x', 'x', 'x', 0x02} MUST be the last one. - {0, 0, 1, 0, 0x87}, - {0, 0, 1, 1, 0x87}, - {0, 0, 2, 0, 0xE6}, - {0, 0, 3, 0, 0x8A}, - {0, 0, 3, 1, 0x8A}, - {0, 0, 3, 2, 0xE6}, - {0, 0, 3, 3, 0xE6}, - {0, 0, 3, 4, 0xE6}, - {0, 0, 3, 5, 0x8C}, - {0, 0, 5, 0, 0xEE}, - {0, 0, 5, 1, 0xEE}, - {0, 1, 3, 1, 0xE6}, - {0, 1, 5, 1, 0xE6}, - {1, 0, 0, 0, 0x83}, - {1, 0, 0, 1, 0x85}, - {1, 0, 0, 2, 0x85}, - {1, 0, 0, 3, 0xED}, - {1, 0, 1, 0, 0x87}, - {1, 0, 1, 1, 0x8F}, - {1, 0, 1, 2, 0xED}, - {1, 0, 1, 3, 0xED}, - {1, 0, 1, 4, 0xED}, - {1, 0, 1, 5, 0xED}, - {1, 0, 1, 6, 0xED}, - {1, 0, 1, 7, 0xEC}, - {1, 0, 1, 8, 0xED}, - {1, 0, 1, 9, 0xED}, - {1, 0, 1, 0xA, 0xEC}, - {1, 0, 1, 0xB, 0xEC}, - {1, 0, 1, 0xC, 0x85}, - {1, 0, 2, 0, 0xE7}, - {1, 0, 2, 1, 0xEC}, - {1, 0, 2, 2, 0xEC}, - {1, 0, 2, 3, 0xEC}, - {1, 0, 2, 4, 0xEC}, - {1, 0, 2, 5, 0xED}, - {1, 0, 2, 6, 0xED}, - {1, 0, 2, 7, 0xED}, - {1, 0, 2, 8, 0xEC}, - {1, 0, 2, 9, 0xED}, - {1, 0, 2, 0xA, 0xED}, - {1, 0, 3, 0, 0x8A}, - {1, 0, 3, 1, 0x8C}, - {1, 0, 3, 2, 0x8D}, - {1, 0, 3, 3, 0xEC}, - {1, 0, 3, 4, 0xEC}, - {1, 0, 3, 5, 0xEC}, - {1, 0, 3, 6, 0xEC}, - {1, 0, 3, 7, 0xEC}, - {1, 0, 3, 8, 0xEC}, - {1, 0, 3, 9, 0xEC}, - {1, 0, 3, 0xA, 0xED}, - {1, 0, 3, 0xB, 0xED}, - {1, 0, 3, 0xC, 0xED}, - {1, 0, 3, 0xD, 0xED}, - {1, 0, 3, 0xE, 0xEC}, - {1, 0, 3, 0xF, 0xED}, - {1, 0, 5, 0, 0xEC}, - {1, 1, 1, 1, 0xED}, - {1, 1, 1, 2, 0xED}, - {1, 1, 3, 0, 0xEC}, - {1, 1, 3, 1, 0xEC}, - {1, 1, 3, 2, 0xEC}, - {1, 1, 3, 3, 0xEC}, - {1, 1, 3, 4, 0xEC}, - {2, 0, 0, 0, 0xEF}, - {2, 0, 0, 1, 0xEF}, - {2, 0, 1, 0, 0x38}, - {2, 0, 1, 1, 0x39}, - {2, 0, 1, 2, 0x3A}, - {2, 0, 1, 3, 0x39}, - {2, 0, 1, 4, 0xED}, - {2, 0, 1, 5, 0xEC}, - {2, 0, 1, 6, 0xEC}, - {2, 0, 1, 7, 0x39}, - {2, 0, 1, 8, 0xED}, - {2, 0, 1, 9, 0xEC}, - {2, 0, 2, 2, 0xEC}, - {2, 0, 2, 3, 0xEC}, - {2, 0, 2, 4, 0xEC}, - {2, 0, 3, 1, 0xEC}, - {2, 0, 3, 2, 0xEC}, - {2, 0, 3, 3, 0xEC}, - {3, 0, 7, 0, 0x84}, - {3, 0, 0xB, 0, 0x84}, - {3, 1, 7, 1, 0xE6}, - {4, 0, 0, 1, 0xED}, - {4, 0, 0, 2, 0xEF}, - {4, 0, 0, 3, 0xED}, - {4, 0, 1, 1, 0x39}, - {4, 0, 1, 2, 0x3A}, - {4, 0, 1, 3, 0xEF}, - {4, 0, 1, 4, 0x39}, - {4, 0, 1, 5, 0x3A}, - {5, 0, 3, 0, 0x84}, - {5, 0, 5, 0, 0x84}, - {5, 1, 3, 1, 0xE6}, - {5, 1, 5, 1, 0xE6}, - {'x', 'x', 'x', 'x', P_FAMILY_UNKNOWN} - }; - -CONST PROC_FAMILY_TABLE ROMDATA ProcFamily10DmiTable = -{ -// This table is for Processor family 10h - AMD_FAMILY_10, // ID for Family 10h - DmiF10GetInfo, // Transfer vectors for family - DmiGetT4ProcFamilyFromBrandId, // Get type 4 processor family information from CPUID_8000_0001_EBX[BrandId] - DmiF10GetVoltage, // specific routines (above) - DmiF10GetMaxSpeed, - DmiF10GetExtClock, - DmiF10GetMemInfo, // Get memory information - (sizeof (Family10BrandList) / sizeof (Family10BrandList[0])), // Number of entries in following table - &Family10BrandList[0] -}; - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * F10Translate7BitVidTo6Bit - * - * translate 7 bit VID to 6 bit VID - * - * @param[in, out] MaxVidPtr - Pointer to MaxVid. - */ -VOID -STATIC -F10Translate7BitVidTo6Bit ( - IN OUT UINT8 * MaxVidPtr - ) -{ - if ((*MaxVidPtr >= 0x5E) && (*MaxVidPtr <= 0x7F)) { - *MaxVidPtr = 0x3F; - } else if ((*MaxVidPtr >= 0x3F) && (*MaxVidPtr <= 0x5D)) { - *MaxVidPtr = *MaxVidPtr - 0x1F; - } else if (*MaxVidPtr <= 0x3E) { - *MaxVidPtr = (*MaxVidPtr & 0x7E) >> 1; - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c deleted file mode 100644 index c7fb857e71..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c +++ /dev/null @@ -1,454 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 after warm reset sequence - * - * Performs the "CPU Core Minimum P-State Transition Sequence After Warm Reset" - * as described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuF10PowerMgmt.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "cpuF10Utilities.h" -#include "cpuF10EarlyInit.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/// Enum for handling code branching while transitioning to the -/// minimum P-state after a warm reset -typedef enum { - EXIT_SEQUENCE, ///< Exit the sequence - STEP7, ///< Go to step 7 - STEP17, ///< Go to step 17 - STEP20 ///< Go to step 20 -} GO_TO_STEP; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F10PmVoltageAlignmentAfterResetCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F10PmAfterResetCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -WaitForCpuFidAndDidToMatch ( - IN UINT32 PstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------*/ -/** - * Family 10h core 0 entry point for performing the necessary steps after - * a warm reset has occurred. - * - * The steps are as follows: - * 1. Modify F3xDC[PstateMaxVal] to reflect the lowest performance P-state - * supported, as indicated in MSRC001_00[68:64][PstateEn] - * 2. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis] - * 3. If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20 - * 4. If F3xDC[PstateMaxVal] = 0 or F3xDC[PstateMaxVal] != 4, go to step 7 - * 5. If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17 - * 6. Exit the sequence - * 7. Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state - * register pointed to by F3xDC[PstateMaxVal]+1 - * 8. Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal] - * 9. Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] - * 10. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state - * register pointed to by (the new) F3xDC[PstateMaxVal] - * 11. Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd] - * 12. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state - * register pointed to by (the new) F3xDC[PstateMaxVal]-1 - * 13. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis] - * 14. If required, transition the NB COF and VID to the NbDid and NbVid from the - * P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF - * and VID transition sequence after a warm reset - * 15. Write MSRC001_00[68:64][PstateEn]=0 for the P-state pointed to by F3xDC[PstateMaxVal] - * 16. Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal] and exit the sequence - * 17. Copy MSRC001_0061[PstateMaxVal] - 1 to MSRC001_0062[PstateCmd] - * 18. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state - * register pointed to by F3xDC[PstateMaxVal]-1 - * 19. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis] - * 20. Copy MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] - * 21. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state - * register pointed to by F3xDC[PstateMaxVal] - * 22. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis] - * 23. Issue an LDTSTOP assertion in the IO hub and exit sequence - * 24. If required, transition the NB COF and VID to the NbDid and NbVid from the - * P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID - * transition sequence after a warm reset - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F10PmAfterReset ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 PsMaxVal; - UINT32 MsrAddr; - UINT32 Core; - UINT32 AndMask; - UINT32 OrMask; - UINT32 CpbNum; - UINT64 LocalMsrRegister; - UINT64 CurrentStatus; - UINT64 TargetPsMsr; - PCI_ADDR PciAddress; - AP_TASK TaskPtr; - - GetCurrentCore (&Core, StdHeader); - ASSERT (Core == 0); - - // Core P-State Voltage Alignment After Warm Reset - CpbNum = F10GetNumberOfBoostedPstatesOnCore (StdHeader); - if (CpbNum == 1) { - // Step 1 Write MSRC001_0063[ CurPstate] to MSRC001_0062[ PstateCmd] on every core in the processor. - TaskPtr.FuncAddress.PfApTask = F10PmVoltageAlignmentAfterResetCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - - // Step 2 Wait for MSRC001_0071[ CurCpuVid] >= [CpuVid] from MSRC001_00[ 68:64] indexed by 4x15C[ NumBoost States] - // Get target P-state indexed by F4x15C[NumBoostStates] - LibAmdMsrRead ((MSR_PSTATE_0 + CpbNum), &TargetPsMsr, StdHeader); - do { - LibAmdMsrRead (MSR_COFVID_STS, &CurrentStatus, StdHeader); - } while (((COFVID_STS_MSR *) &CurrentStatus)->CurCpuVid < ((PSTATE_MSR *) &TargetPsMsr)->CpuVid); - } - - // Core Minimum P-State Transition Sequence After Warm Reset - // Step 1 Modify F3xDC[PstateMaxVal] to reflect the lowest performance - // P-state supported, as indicated in MSRC001_00[68:64][PstateEn] - for (MsrAddr = PS_MAX_REG; MsrAddr > PS_REG_BASE; --MsrAddr) { - LibAmdMsrRead (MsrAddr, &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - break; - } - } - PsMaxVal = MsrAddr - PS_REG_BASE; - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - AndMask = 0xFFFFFFFF; - OrMask = 0x00000000; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PsMaxVal; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - // Launch each local core to perform the remaining steps. - TaskPtr.FuncAddress.PfApTask = F10PmAfterResetCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); -} - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F10PmAfterReset to perform MSR initialization on all - * cores of a family 10h socket. - * - * This function implements steps 2 - 24 on each core. - * - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F10PmAfterResetCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 PsMaxVal; - UINT32 SwPsMaxVal; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - UINT64 SavedMsr; - UINT64 CurrentLimitMsr; - PCI_ADDR PciAddress; - GO_TO_STEP GoToStep; - CPU_LOGICAL_ID LogicalId; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - // Step 2 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis] - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - GetCpuServicesFromLogicalId (&LogicalId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 0) { - LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader); - LocalMsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader); - } - } - - GoToStep = EXIT_SEQUENCE; - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - PsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal; - - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &CurrentLimitMsr, StdHeader); - SwPsMaxVal = (UINT32) (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal); - - // Step 3 If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20 - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstate != PsMaxVal) { - GoToStep = STEP20; - } else { - // Step 4 If F3xDC[PstateMaxVal] = 0 || F3xDC[PstateMaxVal] != 4, go to step 7 - if ((PsMaxVal == 0) || (PsMaxVal != 4)) { - GoToStep = STEP7; - } else { - // Step 5 If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17 - if (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->CurPstateLimit <= (PsMaxVal - 1)) { - GoToStep = STEP17; - } - } - } - switch (GoToStep) { - default: - case EXIT_SEQUENCE: - // Step 6 Exit the sequence - break; - case STEP7: - // Workaround for S3 ----Save the value of [The PState[4:0] Registers] MSRC001_00[68:64] - // pointed to by F3xDC[PstateMaxVal] + 1 - LibAmdMsrRead ((MSR_PSTATE_0 + (PsMaxVal + 1)), &SavedMsr, StdHeader); - - // Step 7 Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state - // register pointed to by F3xDC[PstateMaxVal]+1 - LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &LocalMsrRegister, StdHeader); - LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &LocalMsrRegister, StdHeader); - - // Step 8 Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal] - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = PsMaxVal + 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - // Step 9 Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (PsMaxVal + 1), (BOOLEAN) FALSE, StdHeader); - - // Step 10 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state - // register pointed to by (the new) F3xDC[PstateMaxVal] - WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal + 1), StdHeader); - - // Step 11 Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd] - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) PsMaxVal, (BOOLEAN) FALSE, StdHeader); - - // Step 12 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state - // register pointed to by (the new) F3xDC[PstateMaxVal]-1 - WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader); - - // Step 13 If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis] - if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 1) { - LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader); - LocalMsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader); - } - } - - // Step 14 If required, transition the NB COF and VID to the NbDid and NbVid from the - // P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF - // and VID transition sequence after a warm reset - - // Step 15 Write 0 to PstateEn of the P-state register pointed to by (the new) F3xDC[PstateMaxVal] - // Workaround for S3----Restore the value of [The PState[4:0] Registers] MSRC001_00[68:64] - // pointed to by F3xDC[PstateMaxVal] + 1 - ((PSTATE_MSR *) &SavedMsr)->PsEnable = 0; - LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &SavedMsr, StdHeader); - - // Step 16 Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal] - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = PsMaxVal; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - break; - case STEP17: - // Step 17 Copy MSRC001_0061[PstateMaxVal]-1 to MSRC001_0062[PstateCmd] - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (SwPsMaxVal - 1), (BOOLEAN) FALSE, StdHeader); - - // Step 18 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state - // register pointed to by F3xDC[PstateMaxVal]-1 - WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal - 1), StdHeader); - - // Step 19 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis] - if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 0) { - LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader); - LocalMsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader); - } - } - - // Fall through from step 19 to step 20 - case STEP20: - // Step 20 Copy MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) SwPsMaxVal, (BOOLEAN) FALSE, StdHeader); - - // Step 21 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state - // register pointed to by F3xDC[PstateMaxVal] - WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader); - - // Step 22 If MSR C001_0071[CurNbDid] = 1, set MSR C001_001F[GfxNbPstateDis] and exit - // the sequence - if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 1) { - LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader); - LocalMsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader); - break; - } - } - - // Step 23 Issue an LDTSTOP and exit the sequence - - // Step 24 If required, transition the NB COF and VID to the NbDid and NbVid from the - // P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID - // transition sequence after a warm reset - break; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F10PmAfterResetCore to wait for Cpu FID and DID to - * match a specific P-state. - * - * This function implements steps 11, 13, 18, and 20 on each core as needed. - * - * @param[in] PstateNumber P-state settings to match - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -WaitForCpuFidAndDidToMatch ( - IN UINT32 PstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 TargetPsMsr; - UINT64 CurrentStatus; - - // Get target P-state settings - LibAmdMsrRead ((MSR_PSTATE_0 + PstateNumber), &TargetPsMsr, StdHeader); - - // Wait for current CPU FID/DID to match target FID/DID - do { - LibAmdMsrRead (MSR_COFVID_STS, &CurrentStatus, StdHeader); - } while ((((COFVID_STS_MSR *) &CurrentStatus)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) || - (((COFVID_STS_MSR *) &CurrentStatus)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F10PmAfterReset to Core P-State Voltage Alignment for CPB on all - * cores of a family 10h socket. - * - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F10PmVoltageAlignmentAfterResetCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 CurrentStatus; - - LibAmdMsrRead (MSR_PSTATE_STS, &CurrentStatus, StdHeader); - LibAmdMsrWrite (MSR_PSTATE_CTL, &CurrentStatus, StdHeader); -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.h deleted file mode 100644 index d031620c4a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Early Init related functions Prototypes. - * - * Contains code that provide power management functionality - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F10_EARLY_INIT_H_ -#define _CPU_F10_EARLY_INIT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F10PmAfterReset ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F10_EARLY_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c deleted file mode 100644 index a282fa69df..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c +++ /dev/null @@ -1,393 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 specific feature leveling functions. - * - * Provides feature leveling functions specific to family 10h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuPostInit.h" -#include "cpuF10FeatureLeveling.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -cpuFeatureListNeedUpdate ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ); - -VOID -STATIC -updateCpuFeatureList ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function get features which CPU supports. - * - * @CpuServiceMethod{::F_CPU_SAVE_FEATURES}. - * - * Read features from MSR_C0011004 and MSR_C0011005. - * - * @param[in] FamilySpecificServices - Pointer to CPU_SPECIFIC_SERVICES struct. - * @param[in,out] cpuFeatureList - Pointer to CPU_FEATURES_LIST struct. - * @param[in] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -F10SaveFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 CpuMsrData; - BOOLEAN *FirstTime; - BOOLEAN *NeedLeveling; - CPU_F10_FEATURES *CpuF10Features; - CPU_F10_EXT_FEATURES *CpuF10ExtFeatures; - CPU_FEATURES_LIST thisCoreCpuFeatureList; - - FirstTime = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST)); - NeedLeveling = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN)); - - LibAmdMemFill (&thisCoreCpuFeatureList, 0x0, sizeof (CPU_FEATURES_LIST), StdHeader); - LibAmdMsrRead (MSR_CPUID_FEATS, &CpuMsrData, StdHeader); - CpuF10Features = (CPU_F10_FEATURES *) &CpuMsrData; - - thisCoreCpuFeatureList.APIC = (UINT8) CpuF10Features->CpuF10FeaturesLo.APIC; - thisCoreCpuFeatureList.CLFSH = (UINT8) CpuF10Features->CpuF10FeaturesLo.CLFSH; - thisCoreCpuFeatureList.CMOV = (UINT8) CpuF10Features->CpuF10FeaturesLo.CMOV; - thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF10Features->CpuF10FeaturesLo.CMPXCHG8B; - thisCoreCpuFeatureList.DE = (UINT8) CpuF10Features->CpuF10FeaturesLo.DE; - thisCoreCpuFeatureList.FPU = (UINT8) CpuF10Features->CpuF10FeaturesLo.FPU; - thisCoreCpuFeatureList.FXSR = (UINT8) CpuF10Features->CpuF10FeaturesLo.FXSR; - thisCoreCpuFeatureList.HTT = (UINT8) CpuF10Features->CpuF10FeaturesLo.HTT; - thisCoreCpuFeatureList.MCA = (UINT8) CpuF10Features->CpuF10FeaturesLo.MCA; - thisCoreCpuFeatureList.MCE = (UINT8) CpuF10Features->CpuF10FeaturesLo.MCE; - thisCoreCpuFeatureList.MMX = (UINT8) CpuF10Features->CpuF10FeaturesLo.MMX; - thisCoreCpuFeatureList.MSR = (UINT8) CpuF10Features->CpuF10FeaturesLo.MSR; - thisCoreCpuFeatureList.MTRR = (UINT8) CpuF10Features->CpuF10FeaturesLo.MTRR; - thisCoreCpuFeatureList.PAE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PAE; - thisCoreCpuFeatureList.PAT = (UINT8) CpuF10Features->CpuF10FeaturesLo.PAT; - thisCoreCpuFeatureList.PGE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PGE; - thisCoreCpuFeatureList.PSE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PSE; - thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF10Features->CpuF10FeaturesLo.PSE36; - thisCoreCpuFeatureList.SSE = (UINT8) CpuF10Features->CpuF10FeaturesLo.SSE; - thisCoreCpuFeatureList.SSE2 = (UINT8) CpuF10Features->CpuF10FeaturesLo.SSE2; - thisCoreCpuFeatureList.SysEnterSysExit = (UINT8) CpuF10Features->CpuF10FeaturesLo.SysEnterSysExit; - thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF10Features->CpuF10FeaturesLo.TimeStampCounter; - thisCoreCpuFeatureList.VME = (UINT8) CpuF10Features->CpuF10FeaturesLo.VME; - - thisCoreCpuFeatureList.CMPXCHG16B = (UINT8) CpuF10Features->CpuF10FeaturesHi.CMPXCHG16B; - thisCoreCpuFeatureList.Monitor = (UINT8) CpuF10Features->CpuF10FeaturesHi.Monitor; - thisCoreCpuFeatureList.POPCNT = (UINT8) CpuF10Features->CpuF10FeaturesHi.POPCNT; - thisCoreCpuFeatureList.SSE3 = (UINT8) CpuF10Features->CpuF10FeaturesHi.SSE3; - - LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader); - CpuF10ExtFeatures = (CPU_F10_EXT_FEATURES *) &CpuMsrData; - - thisCoreCpuFeatureList.ThreeDNow = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNow; - thisCoreCpuFeatureList.ThreeDNowExt = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNowExt; - thisCoreCpuFeatureList.APIC = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.APIC; - thisCoreCpuFeatureList.CMOV = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMOV; - thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMPXCHG8B; - thisCoreCpuFeatureList.DE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.DE; - thisCoreCpuFeatureList.FFXSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FFXSR; - thisCoreCpuFeatureList.FPU = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FPU; - thisCoreCpuFeatureList.FXSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FXSR; - thisCoreCpuFeatureList.LM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.LM; - thisCoreCpuFeatureList.MCA = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCA; - thisCoreCpuFeatureList.MCE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCE; - thisCoreCpuFeatureList.MMX = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MMX; - thisCoreCpuFeatureList.MmxExt = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MmxExt; - thisCoreCpuFeatureList.MSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MSR; - thisCoreCpuFeatureList.MTRR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MTRR; - thisCoreCpuFeatureList.NX = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.NX; - thisCoreCpuFeatureList.PAE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAE; - thisCoreCpuFeatureList.Page1GB = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.Page1GB; - thisCoreCpuFeatureList.PAT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAT; - thisCoreCpuFeatureList.PGE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PGE; - thisCoreCpuFeatureList.PSE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE; - thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE36; - thisCoreCpuFeatureList.RDTSCP = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.RDTSCP; - thisCoreCpuFeatureList.SysCallSysRet = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.SysCallSysRet; - thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.TimeStampCounter; - thisCoreCpuFeatureList.VME = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.VME; - - thisCoreCpuFeatureList.ThreeDNowPrefetch = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ThreeDNowPrefetch; - thisCoreCpuFeatureList.ABM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ABM; - thisCoreCpuFeatureList.AltMovCr8 = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.AltMovCr8; - thisCoreCpuFeatureList.CmpLegacy = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.CmpLegacy; - thisCoreCpuFeatureList.ExtApicSpace = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ExtApicSpace; - thisCoreCpuFeatureList.IBS = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.IBS; - thisCoreCpuFeatureList.LahfSahf = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.LahfSahf; - thisCoreCpuFeatureList.MisAlignSse = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.MisAlignSse; - thisCoreCpuFeatureList.OSVW = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.OSVM; - thisCoreCpuFeatureList.SKINIT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SKINIT; - thisCoreCpuFeatureList.SSE4A = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SSE4A; - thisCoreCpuFeatureList.SVM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SVM; - thisCoreCpuFeatureList.WDT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.WDT; - thisCoreCpuFeatureList.NodeId = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.NodeId; - - if (*FirstTime) { - updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList); - *FirstTime = FALSE; - } else if (cpuFeatureListNeedUpdate (cpuFeatureList, &thisCoreCpuFeatureList)) { - updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList); - *NeedLeveling = TRUE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function set features which All CPUs support. - * - * @CpuServiceMethod{::F_CPU_WRITE_FEATURES}. - * - * Write least common features to MSR_C0011004 and MSR_C0011005. - * - * @param[in] FamilySpecificServices - Pointer to CPU_SPECIFIC_SERVICES struct. - * @param[in,out] cpuFeatureList - Pointer to CPU_FEATURES_LIST struct. - * @param[in] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -F10WriteFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 CpuMsrData; - CPU_F10_FEATURES *CpuF10Features; - CPU_F10_EXT_FEATURES *CpuF10ExtFeatures; - - CpuMsrData = 0; - CpuF10Features = (CPU_F10_FEATURES *) &CpuMsrData; - - CpuF10Features->CpuF10FeaturesLo.APIC = cpuFeatureList->APIC; - CpuF10Features->CpuF10FeaturesLo.CLFSH = cpuFeatureList->CLFSH; - CpuF10Features->CpuF10FeaturesLo.CMOV = cpuFeatureList->CMOV; - CpuF10Features->CpuF10FeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B; - CpuF10Features->CpuF10FeaturesLo.DE = cpuFeatureList->DE; - CpuF10Features->CpuF10FeaturesLo.FPU = cpuFeatureList->FPU; - CpuF10Features->CpuF10FeaturesLo.FXSR = cpuFeatureList->FXSR; - CpuF10Features->CpuF10FeaturesLo.HTT = cpuFeatureList->HTT; - CpuF10Features->CpuF10FeaturesLo.MCA = cpuFeatureList->MCA; - CpuF10Features->CpuF10FeaturesLo.MCE = cpuFeatureList->MCE; - CpuF10Features->CpuF10FeaturesLo.MMX = cpuFeatureList->MMX; - CpuF10Features->CpuF10FeaturesLo.MSR = cpuFeatureList->MSR; - CpuF10Features->CpuF10FeaturesLo.MTRR = cpuFeatureList->MTRR; - CpuF10Features->CpuF10FeaturesLo.PAE = cpuFeatureList->PAE; - CpuF10Features->CpuF10FeaturesLo.PAT = cpuFeatureList->PAT; - CpuF10Features->CpuF10FeaturesLo.PGE = cpuFeatureList->PGE; - CpuF10Features->CpuF10FeaturesLo.PSE = cpuFeatureList->PSE; - CpuF10Features->CpuF10FeaturesLo.PSE36 = cpuFeatureList->PSE36; - CpuF10Features->CpuF10FeaturesLo.SSE = cpuFeatureList->SSE; - CpuF10Features->CpuF10FeaturesLo.SSE2 = cpuFeatureList->SSE2; - CpuF10Features->CpuF10FeaturesLo.SysEnterSysExit = cpuFeatureList->SysEnterSysExit; - CpuF10Features->CpuF10FeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter; - CpuF10Features->CpuF10FeaturesLo.VME = cpuFeatureList->VME; - - CpuF10Features->CpuF10FeaturesHi.CMPXCHG16B = cpuFeatureList->CMPXCHG16B; - CpuF10Features->CpuF10FeaturesHi.Monitor = cpuFeatureList->Monitor; - CpuF10Features->CpuF10FeaturesHi.POPCNT = cpuFeatureList->POPCNT; - CpuF10Features->CpuF10FeaturesHi.SSE3 = cpuFeatureList->SSE3; - - LibAmdMsrWrite (MSR_CPUID_FEATS, &CpuMsrData, StdHeader); - - CpuMsrData = 0; - CpuF10ExtFeatures = (CPU_F10_EXT_FEATURES *) &CpuMsrData; - - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNow = cpuFeatureList->ThreeDNow; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNowExt = cpuFeatureList->ThreeDNowExt; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.APIC = cpuFeatureList->APIC; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMOV = cpuFeatureList->CMOV; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.DE = cpuFeatureList->DE; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FFXSR = cpuFeatureList->FFXSR; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FPU = cpuFeatureList->FPU; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FXSR = cpuFeatureList->FXSR; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.LM = cpuFeatureList->LM; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCA = cpuFeatureList->MCA; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCE = cpuFeatureList->MCE; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MMX = cpuFeatureList->MMX; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MmxExt = cpuFeatureList->MmxExt; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MSR = cpuFeatureList->MSR; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MTRR = cpuFeatureList->MTRR; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.NX = cpuFeatureList->NX; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAE = cpuFeatureList->PAE; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.Page1GB = cpuFeatureList->Page1GB; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAT = cpuFeatureList->PAT; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PGE = cpuFeatureList->PGE; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE = cpuFeatureList->PSE; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE36 = cpuFeatureList->PSE36; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.RDTSCP = cpuFeatureList->RDTSCP; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.SysCallSysRet = cpuFeatureList->SysCallSysRet; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter; - CpuF10ExtFeatures->CpuF10ExtFeaturesLo.VME = cpuFeatureList->VME; - - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ThreeDNowPrefetch = cpuFeatureList->ThreeDNowPrefetch; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ABM = cpuFeatureList->ABM; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.AltMovCr8 = cpuFeatureList->AltMovCr8; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.CmpLegacy = cpuFeatureList->CmpLegacy; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ExtApicSpace = cpuFeatureList->ExtApicSpace; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.IBS = cpuFeatureList->IBS; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.LahfSahf = cpuFeatureList->LahfSahf; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.MisAlignSse = cpuFeatureList->MisAlignSse; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.OSVM = cpuFeatureList->OSVW; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SKINIT = cpuFeatureList->SKINIT; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SSE4A = cpuFeatureList->SSE4A; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SVM = cpuFeatureList->SVM; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.WDT = cpuFeatureList->WDT; - CpuF10ExtFeatures->CpuF10ExtFeaturesHi.NodeId = cpuFeatureList->NodeId; - LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * cpuFeatureListNeedUpdate - * - * Compare global CPU feature list with this core feature list to see if global CPU feature list - * needs updated. - * - * @param[in] globalCpuFeatureList - Pointer to global CPU Feature List. - * @param[in] thisCoreCpuFeatureList - Pointer to this core CPU Feature List. - * - * @retval FALSE globalCpuFeatureList is equal to thisCoreCpuFeatureList - * @retval True globalCpuFeatureList is NOT equal to thisCoreCpuFeatureList - */ -BOOLEAN -STATIC -cpuFeatureListNeedUpdate ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ) -{ - BOOLEAN flag; - UINT8 *global; - UINT8 *thisCore; - UINT8 i; - - flag = FALSE; - global = (UINT8 *) globalCpuFeatureList; - thisCore = (UINT8 *) thisCoreCpuFeatureList; - - for (i = 0; i < sizeof (CPU_FEATURES_LIST); i++) { - if ((*global) != (*thisCore)) { - flag = TRUE; - break; - } - global++; - thisCore++; - } - return flag; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * updateCpuFeatureList - * - * Update global CPU feature list - * - * @param[in] globalCpuFeatureList - Pointer to global CPU Feature List. - * @param[in] thisCoreCpuFeatureList - Pointer to this core CPU Feature List. - * - */ -VOID -STATIC -updateCpuFeatureList ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ) -{ - UINT8 *globalFeatureList; - UINT8 *thisCoreFeatureList; - UINT32 sizeInByte; - - globalFeatureList = (UINT8 *) globalCpuFeatureList; - thisCoreFeatureList = (UINT8 *) thisCoreCpuFeatureList; - - for (sizeInByte = 0; sizeInByte < sizeof (CPU_FEATURES_LIST); sizeInByte++) { - *globalFeatureList &= *thisCoreFeatureList; - globalFeatureList++; - thisCoreFeatureList++; - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h deleted file mode 100644 index d62adcc2e5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h +++ /dev/null @@ -1,195 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 specific feature leveling functions. - * - * Provides feature leveling functions specific to family 10h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F10_FEATURE_LEVELING_H_ -#define _CPU_F10_FEATURE_LEVELING_H_ - -#include "cpuFamilyTranslation.h" -#include "cpuPostInit.h" -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/// F10 CPU Feature Low -typedef struct { - UINT32 FPU:1; ///< Bit0 - UINT32 VME:1; ///< Bit1 - UINT32 DE:1; ///< Bit2 - UINT32 PSE:1; ///< Bit3 - UINT32 TimeStampCounter:1; ///< Bit4 - UINT32 MSR:1; ///< Bit5 - UINT32 PAE:1; ///< Bit6 - UINT32 MCE:1; ///< Bit7 - UINT32 CMPXCHG8B:1; ///< Bit8 - UINT32 APIC:1; ///< Bit9 - UINT32 Reserved1:1; ///< Bit10 - UINT32 SysEnterSysExit:1; ///< Bit11 - UINT32 MTRR:1; ///< Bit12 - UINT32 PGE:1; ///< Bit13 - UINT32 MCA:1; ///< Bit14 - UINT32 CMOV:1; ///< Bit15 - UINT32 PAT:1; ///< Bit16 - UINT32 PSE36:1; ///< Bit17 - UINT32 Reserved2:1; ///< Bit18 - UINT32 CLFSH:1; ///< Bit19 - UINT32 Reserved3:3; ///< Bit20~22 - UINT32 MMX:1; ///< Bit23 - UINT32 FXSR:1; ///< Bit24 - UINT32 SSE:1; ///< Bit25 - UINT32 SSE2:1; ///< Bit26 - UINT32 Reserved4:1; ///< Bit27 - UINT32 HTT:1; ///< Bit28 - UINT32 Reserved5:3; ///< Bit29~31 -} CPU_F10_FEATURES_LO; - -/// F10 CPU Feature High -typedef struct { - UINT32 SSE3:1; ///< Bit0 - UINT32 Reserved1:2; ///< Bit1~2 - UINT32 Monitor:1; ///< Bit3 - UINT32 Reserved2:9; ///< Bit4~12 - UINT32 CMPXCHG16B:1; ///< Bit13 - UINT32 Reserved3:9; ///< Bit14~22 - UINT32 POPCNT:1; ///< Bit23 - UINT32 Reserved4:8; ///< Bit24~31 -} CPU_F10_FEATURES_HI; - -/// F10 CPU Feature -typedef struct { - CPU_F10_FEATURES_LO CpuF10FeaturesLo; ///< Low - CPU_F10_FEATURES_HI CpuF10FeaturesHi; ///< High -} CPU_F10_FEATURES; - -/// F10 CPU Extended Feature Low -typedef struct { - UINT32 FPU:1; ///< Bit0 - UINT32 VME:1; ///< Bit1 - UINT32 DE:1; ///< Bit2 - UINT32 PSE:1; ///< Bit3 - UINT32 TimeStampCounter:1; ///< Bit4 - UINT32 MSR:1; ///< Bit5 - UINT32 PAE:1; ///< Bit6 - UINT32 MCE:1; ///< Bit7 - UINT32 CMPXCHG8B:1; ///< Bit8 - UINT32 APIC:1; ///< Bit9 - UINT32 Reserved1:1; ///< Bit10 - UINT32 SysCallSysRet:1; ///< Bit11 - UINT32 MTRR:1; ///< Bit12 - UINT32 PGE:1; ///< Bit13 - UINT32 MCA:1; ///< Bit14 - UINT32 CMOV:1; ///< Bit15 - UINT32 PAT:1; ///< Bit16 - UINT32 PSE36:1; ///< Bit17 - UINT32 Reserved2:2; ///< Bit18~19 - UINT32 NX:1; ///< Bit20 - UINT32 Reserved3:1; ///< Bit21 - UINT32 MmxExt:1; ///< Bit22 - UINT32 MMX:1; ///< Bit23 - UINT32 FXSR:1; ///< Bit24 - UINT32 FFXSR:1; ///< Bit25 - UINT32 Page1GB:1; ///< Bit26 - UINT32 RDTSCP:1; ///< Bit27 - UINT32 Reserved4:1; ///< Bit28 - UINT32 LM:1; ///< Bit29 - UINT32 ThreeDNowExt:1; ///< Bit30 - UINT32 ThreeDNow:1; ///< Bit31 -} CPU_F10_EXT_FEATURES_LO; - -/// F10 CPU Extended Feature High -typedef struct { - UINT32 LahfSahf:1; ///< Bit0 - UINT32 CmpLegacy:1; ///< Bit1 - UINT32 SVM:1; ///< Bit2 - UINT32 ExtApicSpace:1; ///< Bit3 - UINT32 AltMovCr8:1; ///< Bit4 - UINT32 ABM:1; ///< Bit5 - UINT32 SSE4A:1; ///< Bit6 - UINT32 MisAlignSse:1; ///< Bit7 - UINT32 ThreeDNowPrefetch:1; ///< Bit8 - UINT32 OSVM:1; ///< Bit9 - UINT32 IBS:1; ///< Bit10 - UINT32 Reserved1:1; ///< Bit11 - UINT32 SKINIT:1; ///< Bit12 - UINT32 WDT:1; ///< Bit13 - UINT32 Reserved2:5; ///< Bit14~18 - UINT32 NodeId:1; ///< Bit19 - UINT32 Reserved3:12; ///< Bit20~31 -} CPU_F10_EXT_FEATURES_HI; - -/// F10 CPU Extended Feature -typedef struct { - CPU_F10_EXT_FEATURES_LO CpuF10ExtFeaturesLo; ///< Low - CPU_F10_EXT_FEATURES_HI CpuF10ExtFeaturesHi; ///< High -} CPU_F10_EXT_FEATURES; -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F10SaveFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F10WriteFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _CPU_F10_FEATURE_LEVELING_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c deleted file mode 100644 index 14ae439f24..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c +++ /dev/null @@ -1,751 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 DR PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// HT P C I T a b l e s -// ------------------------- -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HtPhyRegisters[] = -{ -// 0xCF -// HT_PHY_HT1_FIFO_PTR_OPT_VALUE - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0xCF, // Address - 0x0000006D, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// HT_PHY_HT1_FIFO_PTR_OPT_VALUE - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0xDF, // Address - 0x0000006D, // regData - 0x000000FF, // regMask - }} - }, -// 0xCF -// Default for HT3, unless overridden below. - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT3, // - 0xCF, // Address - 0x0000005A, // regData - 0x000000FF, // regMask - }} - }, -// 0xDF -// Default for HT3, unless overridden below. - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT3, // - 0xDF, // Address - 0x0000005A, // regData - 0x000000FF, // regMask - }} - }, -// 0xD1 -// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT3, // - 0xD1, // Address - 0x08040000, // regData - 0x3FFFC000, // regMask - }} - }, -// 0xC1 -// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT3, // - 0xC1, // Address - 0x08040000, // regData - 0x3FFFC000, // regMask - }} - }, -// 0xD1 -// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0xD1, // Address - 0x04020000, // regData - 0x3FFFC000, // regMask - }} - }, -// 0xC1 -// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0xC1, // Address - 0x04020000, // regData - 0x3FFFC000, // regMask - }} - }, -// -// Deemphasis Settings -// - -// HT1: clear any warm reset deemphasis settings. - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0xC5, // Address - 0x00000000, // regData - 0xE01F1FDF, // regMask - }} - }, - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0xD5, // Address - 0x00000000, // regData - 0xE01F1FDF, // regMask - }} - }, - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0xC4, // Address - 0x00000000, // regData - 0x0000FC00, // regMask - }} - }, - { - HtPhyRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0xD4, // Address - 0x00000000, // regData - 0x0000FC00, // regMask - }} - }, - -//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6] -// No deemphasis 00h 00h 00h 0 0 0 0 -// -3dB postcursor 12h 00h 00h 1 0 0 0 -// -6dB postcursor 1Fh 00h 00h 1 0 0 0 -// -8dB postcursor 1Fh 06h 00h 1 1 0 1 -// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1 -// -11dB postcursor with -// -8dB precursor 1Fh 06h 07h 1 1 1 1 - - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL_NONE, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0x00000000, // regData - 0xE01F1F5F, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL_NONE, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0x00000000, // regData - 0xE01F1F5F, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__3, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0x80120000, // regData - 0xE01F1F5F, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__3, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0x80120000, // regData - 0xE01F1F5F, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__6, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0x801F0000, // regData - 0xE01F1F5F, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__6, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0x801F0000, // regData - 0xE01F1F5F, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__8, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0xC01F0640, // regData - 0xE01F1F5F, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__8, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0xC01F0640, // regData - 0xE01F1F5F, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0xC01F0D40, // regData - 0xE01F1F5F, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0xC01F0D40, // regData - 0xE01F1F5F, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11_8, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC5, // Address - 0xE01F0647, // regData - 0xE01F1F5F, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11_8, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD5, // Address - 0xE01F0647, // regData - 0xE01F1F5F, // regMask - }} - }, - -// Far-device deemphasis setting DCV[15:10] -// No deemphasis 20h -// -2dB postcursor 19h -// -3dB postcursor 17h -// -5dB postcursor 11h -// -6dB postcursor 10h -// -7dB postcursor 0Eh -// -8dB postcursor 0Dh -// -9dB postcursor 0Bh -// -11dB postcursor 09h - - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL_NONE, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00008000, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL_NONE, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00008000, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__2, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00006400, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__2, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00006400, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__3, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00005C00, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__3, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00005C00, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__5, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00004400, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__5, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00004400, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__6, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00004000, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__6, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00004000, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__7, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00003800, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__7, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00003800, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__8, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00003400, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__8, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00003400, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__9, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00002C00, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__9, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00002C00, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__11, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00002400, // regData - 0x0000FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__11, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00002400, // regData - 0x0000FC00, // regMask - }} - }, - -}; - -CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable = { - PrimaryCores, - (sizeof (F10HtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F10HtPhyRegisters, -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10MsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10MsrTables.c deleted file mode 100644 index f4f9923562..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10MsrTables.c +++ /dev/null @@ -1,289 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 DR, MSR tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56307 $ @e \$Date: 2011-07-11 15:13:07 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10MsrRegisters[] = -{ -// M S R T a b l e s -// ---------------------- - -// MSR_TOM2 (0xC001001D) -// bits[63:0] - TOP_MEM2 = 0 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_TOM2, // MSR Address - 0x0000000000000000, // OR Mask - 0xFFFFFFFFFFFFFFFF, // NAND Mask - }} - }, -// MSR_SYS_CFG (0xC0010010) -// bit[21] = 1 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_SYS_CFG, // MSR Address - (1 << 21), // OR Mask - (1 << 21), // NAND Mask - }} - }, -// MSR_HWCR (0xC0010015) -// Do not set bit[24] = 1, it will be set in AmdInitPost. -// bit[4] = 1 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_HWCR, // MSR Address - 0x0000000000000010, // OR Mask - 0x0000000000000010, // NAND Mask - }} - }, -// MSR_MC4_CTL_MASK (0xC0010048) -// bit[10] = 1 -// bits[22:19] = 1111b - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_MC4_CTL_MASK, // MSR Address - 0x0000000000780400, // OR Mask - 0x0000000000780400, // NAND Mask - }} - }, -// MSR_DC_CFG (0xC0011022) -// bits[35:34] = 01 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - MSR_DC_CFG, // MSR Address - 0x0000000400000000, // OR Mask - 0x0000000C00000000, // NAND Mask - }} - }, -// MSR_NB_CFG (0xC001001F) -// bit[54] = 1 -// bit[52:51] = 11b for Erratum #372 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_NB_CFG, // MSR Address - 0x0058000000000000, // OR Mask - 0x0058000000000000, // NAND Mask - }} - }, -// MSR_LS_CFG (0xC0011020) -// bit[8] = 1 for Erratum #670 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_LS_CFG, // MSR Address - (1 << 8), // OR Mask - (1 << 8), // NAND Mask - }} - }, -// MSR_DC_CFG (0xC0011022) -// bit[24] = 1 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_DC_CFG, // MSR Address - (1 << 24), // OR Mask - (1 << 24), // NAND Mask - }} - }, -// MSR_CPUID_FEATS (0xC0011004) -// bit[28] = 1 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_MULTI_CORE | AMD_PF_DUAL_CORE) }, // platformFeatures - {{ - MSR_CPUID_FEATS, // MSR Address - (1 << 28), // OR Mask - (1 << 28), // NAND Mask - }} - }, -// MSR_CPUID_EXT_FEATS (0xC0011005) -// bit[33] = 1 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_DUAL_CORE}, // platformFeatures - {{ - MSR_CPUID_EXT_FEATS, // MSR Address - 0x0000000200000000, // OR Mask - 0x0000000200000000, // NAND Mask - }} - }, -// MSR_OSVW_ID_Length (0xC0010140) -// bit[15:0] = 4 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_OSVW_ID_Length, // MSR Address - 0x0000000000000004, // OR Mask - 0x000000000000FFFF, // NAND Mask - }} - }, -// MSR_OSVW_Status (0xC0010141) -// bit[3] = 1 for Erratum #383 -// bit[2] = 1 for Erratum #415 - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_OSVW_Status, // MSR Address - 0x000000000000000C, // OR Mask - 0x000000000000000C, // NAND Mask - }} - }, -// This MSR should be set after the code that most errata would be applied in -// MSR_MC0_CTL (0x00000400) -// bits[63:0] = 0xFFFFFFFFFFFFFFFF - { - MsrRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_MC0_CTL, // MSR Address - 0xFFFFFFFFFFFFFFFF, // OR Mask - 0xFFFFFFFFFFFFFFFF, // NAND Mask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable = { - AllCores, - (sizeof (F10MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *)F10MsrRegisters, -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PciTables.c deleted file mode 100644 index 5ed043f647..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PciTables.c +++ /dev/null @@ -1,772 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 DR PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10PciRegisters[] = -{ -// Function 0 - HT Config - -// F0x68 - Link Transaction Control -// bit[11] , RespPassPW = 1 -// bit[19:17], for 8bit APIC config -// bit[22:21], DsNpReqLmt = 10h - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x004E0800, // regData - 0x006E0800, // regMask - }} - }, -// F0x68 - Link Transaction Control -// For uni-processor systems (that is, single link package processors), single core, and no L3: -// [10, DisFillP] = 1b -// [3, DisWrDwP] = 1b -// [2, DisWrBP] = 1b -// [1, DisRdDwP] = 1b -// [0, DisRdBP] = 1b - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_CORE | AMD_PF_SINGLE_LINK) }, // platformFeatures - {{ - PERFORMANCE_NO_L3_CACHE, - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x0000040F, // regData - 0x0000040F, // regMask - }} - }, -// F0x[E4,C4,A4,84] - Link 0 Control Register -// bit[13] LdtStopTriEn = 1 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x04, // Address - 0x00002000, // regData - 0x00002000, // regMask - }} - }, -// F0x[E4,C4,A4,84] - Link 0 Control Register -// bit [12] IsocEn = 0 default - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_NFCM | AMD_PF_UMA) }, - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x04, // Address - 0x00000000, // regData - 0x00001000, // regMask - }} - }, -// F0x[E4,C4,A4,84] - Link 0 Control Register -// bit [12] IsocEn = 1 for Isochronous control flow modes. - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - { (AMD_PF_UMA_IFCM | AMD_PF_IFCM | AMD_PF_IOMMU) }, - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x04, // Address - 0x00001000, // regData - 0x00001000, // regMask - }} - }, -// F0x[F0,D0,B0,90] - Link Base Channel Buffer Count -// bit[31] LockBc = 1 - { - HtHostPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x10, // Address - 0x80000000, // regData - 0x80000000, // regMask - }} - }, -// F0x150 - Link Global Retry Control Register -// bit[18:16] TotalRetryAttempts = 7 -// bit[13] HtRetryCrcDatInsDynEn = 1 -// bit[12]HtRetryCrcCmdPackDynEn = 1 -// bit[11:9] HtRetryCrcDatIns = 4 -// bit[8] HtRetryCrcCmdPack = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address - 0x00073900, // regData - 0x00073F00, // regMask - }} - }, -// F0x16C - Link Global Extended Control Register -// bit[15:13] ForceFullT0 = 0 -// bit[5:0] T0Time = 0x14 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address - 0x00000014, // regData - 0x0000E03F, // regMask - }} - }, -// F0x16C - Link Global Extended Control Register -// bit[15:13] ForceFullT0 = 6 -// bit[5:0] T0Time = 0x26 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address - 0x0000C026, // regData - 0x0000E03F, // regMask - }} - }, -// F0x16C - Link Global Extended Control Register -// bit[22:17] FullT0Time = 0x33 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_C3 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address - 0x00660000, // regData - 0x007E0000, // regMask - }} - }, - -// Function 1 - Map Init - -// Before reading F1x114_x2 or F1x114_x3 software must initialize -// the registers or NB Array MCA errors may occur. BIOS should -// initialize index 0h of F1x114_x2 and F1x114_x3 to prevent reads -// from F1x114 from generating NB Array MCA errors. -// BKDG Doc #3116 Rev 1.07 - -// F1x110 - Extended Address Map - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_1, 0x110), // Address - 0x20000000, // regData - 0xFFFFFFFF, // regMask - }} - }, -// F1x114 - Extended Address Map - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_1, 0x114), // Address - 0x00000000, // regData - 0xFFFFFFFF, // regMask - }} - }, -// F1x110 - Extended Address Map - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_1, 0x110), // Address - 0x30000000, // regData - 0xFFFFFFFF, // regMask - }} - }, -// F1x114 - Extended Address Map - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_1, 0x114), // Address - 0x00000000, // regData - 0xFFFFFFFF, // regMask - }} - }, - -// F2x1B0 - Extended Memory Controller Configuration Low -// bits[10:8], CohPrefPrbLmt = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address - 0x00000100, // regData - 0x00000700, // regMask - }} - }, - -// Function 3 - Misc. Control -// F3x40 - MCA NB Control -// -// bit[8], MstrAbrtEn = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F3x44 - MCA NB Configuration -// bit[30] SyncOnDramAdrParErrEn = 1 -// bit[27] NB MCA to CPU0 Enable = 1 -// bit[25] DisPciCfgCpuErrRsp = 1 -// bit[21] SyncOnErr = 1 -// bit[20] SyncOnWDTEn = 1 -// bit[6] CpuErrDis = 1 -// bit[4] SyncPktPropDis = 1 -// bit[3] SyncPktGenDis = 1 -// bit[2] SyncOnUcEccEn = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address - 0x4A30005C, // regData - 0x4A30005C, // regMask - }} - }, -// F3x80 - ACPI Power State Control -// ACPI FIDVID Change -// bits[0] CpuPrbEn = 0 -// bits[1] NbLowPwrEn = 0 -// bits[2] NbGateEn = 0 -// bits[3] NbCofChg = 0 -// bits[4] AltVidEn = 0 -// bits[7:5] ClkDivisor = 0 -// ACPI State S1 -// bits[0] CpuPrbEn = 0 -// bits[1] NbLowPwrEn = 1 -// bits[2] NbGateEn = 1 -// bits[3] NbCofChg = 0 -// bits[4] AltVidEn = 0 -// bits[7:5] ClkDivisor = 7 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address - 0xE6000000, // regData - 0xFFFF0000, // regMask - }} - }, -// F3x80 - ACPI Power State Control -// ACPI FIDVID Change -// bits[0] CpuPrbEn = 1 -// bits[1] NbLowPwrEn = 1 -// bits[2] NbGateEn = 0 -// bits[3] NbCofChg = 1 -// bits[4] AltVidEn = 0 -// bits[7:5] ClkDivisor = 0 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_C3 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address - 0x000B0000, // regData - 0x00FF0000, // regMask - }} - }, -// F3x84 - ACPI Power State Control -// ACPI State S3 -// bits[0] CpuPrbEn = 0 -// bits[1] NbLowPwrEn = 1 -// bits[2] NbGateEn = 1 -// bits[3] NbCofChg = 0 -// bits[4] AltVidEn = 0 -// bits[7:5] ClkDivisor = 7 -// ACPI State Throttling -// bits[0] CpuPrbEn = 1 -// bits[1] NbLowPwrEn = 0 -// bits[2] NbGateEn = 0 -// bits[3] NbCofChg = 0 -// bits[4] AltVidEn = 0 -// bits[7:5] ClkDivisor = 2 -// ACPI State S4/S5 -// bits[0] CpuPrbEn = 0 -// bits[1] NbLowPwrEn = 1 -// bits[2] NbGateEn = 1 -// bits[3] NbCofChg = 0 -// bits[4] AltVidEn = 0 -// bits[7:5] ClkDivisor = 7 -// ACPI State C1 -// bits[0] CpuPrbEn = 0 -// bits[1] NbLowPwrEn = 0 -// bits[2] NbGateEn = 0 -// bits[3] NbCofChg = 0 -// bits[4] AltVidEn = 0 -// bits[7:5] ClkDivisor = 5 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address - 0x01E641E6, // regData - 0xFFFFFFFF, // regMask - }} - }, -// F3x84 - ACPI Power State Control -// ACPI State C1 -// bits[0] CpuPrbEn = 0 -// bits[1] NbLowPwrEn = 0 -// bits[2] NbGateEn = 0 -// bits[3] NbCofChg = 0 -// bits[4] AltVidEn = 0 -// bits[7:5] ClkDivisor = 4 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_C2 // CpuRevision - }, - {AMD_PF_SINGLE_CORE}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address - 0x80000000, // regData - 0xFF000000, // regMask - }} - }, -// F3x8C - NB Configuration High -// Errata 373, bits[25] DisFastTprWr = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address - 0x02000000, // regData - 0x02000000, // regMask - }} - }, -// F3x8C - NB Configuration High -// Clear errata 373, bits[25] DisFastTprWr = 0 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platform Features - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address - 0x00000000, // regData - 0x02000000, // regMask - }} - }, -// F3xA0 - Power Control Miscellaneous -// bits[13:11] PllLockTime = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_C0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address - 0x00000800, // regData - 0x00003800, // regMask - }} - }, -// F3xA0 - Power Control Miscellaneous -// bits[9] SviHighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_C3 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address - 0x00000200, // regData - 0x00000200, // regMask - }} - }, -// F3xA4 - Reported Temperature Control -// bits[12:8] PerStepTimeDn = 15 -// bits[7] TmpSlewDnEn = 1 -// bits[6:5] TmpMaxDiffUp = 3 -// bits[4:0] PerStepTimeUp = 15 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address - 0x00000FEF, // regData - 0x00001FFF, // regMask - }} - }, -// F3xD4 - Clock Power Timing Control 0 -// bits[11:8] ClkRampHystSel = 1 -// bits[30:28] NbClkDiv = 1 -// bits[31] NbClkDivApplyAll = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address - 0xC0010F00, // regData - 0xF0030F00, // regMask - }} - }, -// F3xD8 - Clock Power Timing Control 1 -// bits[2:0] VSSlamTime = 6 -// bits[6:4] VSRampTime = 1 -// bits[26:24] ReConDel = 3 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8), // Address - 0x03000016, // regData - 0x0F000077, // regMask - }} - }, -// F3xDC - Clock Power Timing Control 2 -// bits[14:12] NbsynPtrAdj = 6 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address - 0x00006000, // regData - 0x00007000, // regMask - }} - }, -// F3xDC - Clock Power Timing Control 2 -// bits[18:16] CacheFlushOnHaltCtl = 0 to ensure AP cache stability at Early - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_Bx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address - 0x00000000, // regData - 0x00070000, // regMask - }} - }, -// F3x180 - NB Extended Configuration -// bits[1] SyncFloodOnUsPwDataErr = 1 -// bits[5] DisPciCfgCpuMstAbtRsp = 1 -// bits[6] SyncFloodOnDatErr = 1 -// bits[7] SyncFloodOnTgtAbtErr = 1 -// bits[8] SyncOnProtEn = 1 -// bits[9] SyncOnUncNbAryEn = 1 -// bits[20] SyncFloodOnL3LeakErr = 1 -// bits[21] SyncFloodOnCpuLeakErr = 1 -// bits[22] SyncFloodOnTblWalkErr = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address - 0x007003E2, // regData - 0x007003E2, // regMask - }} - }, -// F3x188 - NB Extended Configuration Low Register -// bits[4] EnStpGntOnFlushMaskWakeup = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_C3 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address - 0x00000010, // regData - 0x00000010, // regMask - }} - }, -// F3x1A0 - L3 Buffer Count Register -// bits[14:12] L3ToSriReqCBC = 4, 4 or fewer cores with L3 cache is 4. - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, - (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE), // 4 or fewer cores. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address - 0x00004000, // regData - 0x00007000, // regMask - }} - }, -// F3x1A0 - L3 Buffer Count Register -// bits[14:12] L3ToSriReqCBC = 5, 5-core with L3 cache is 5. - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, - (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address - 0x00005000, // regData - 0x00007000, // regMask - }} - }, -// F3x1A0 - L3 Buffer Count Register -// bits[14:12] L3ToSriReqCBC = 6, 6-core with L3 cache is 6. - { - CoreCountsPciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, - (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core. - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address - 0x00006000, // regData - 0x00007000, // regMask - }} - }, -// F3x1B8 - L3 Control -// bits[12] L3PrivReplEn = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address - 0x00001000, // regData - 0x00001000, // regMask - }} - }, - // F4x1C4 - L3 Power Control Register - // bits[8] L3PwrSavEn = 1 - { - ProfileFixup, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F3x1CC - IBS Control -// bits[8] LvtOffsetVal = 1 - { - PciRegister, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_GT_A2 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F10PciRegisterTable = { - PrimaryCores, - (sizeof (F10PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F10PciRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c deleted file mode 100644 index b855b0b422..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c +++ /dev/null @@ -1,411 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 P-State power check - * - * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as - * described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuF10PowerMgmt.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "cpuF10PowerCheck.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuF10Utilities.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F10PmPwrCheckCore ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F10PmPwrChkCopyPstate ( - IN UINT8 Dest, - IN UINT8 Src, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------*/ -/** - * Family 10h core 0 entry point for performing the family 10h Processor- - * Systemboard Power Delivery Check. - * - * The steps are as follows: - * 1. Starting with P0, loop through all P-states until a passing state is - * found. A passing state is one in which the current required by the - * CPU is less than the maximum amount of current that the system can - * provide to the CPU. If P0 is under the limit, no further action is - * necessary. - * 2. If at least one P-State is under the limit & at least one P-State is - * over the limit, the BIOS must: - * a. If the processor's current P-State is disabled by the power check, - * then the BIOS must request a transition to an enabled P-state - * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] - * to reflect the new value. - * b. Copy the contents of the enabled P-state MSRs to the highest - * performance P-state locations. - * c. Request a P-state transition to the P-state MSR containing the - * COF/VID values currently applied. - * d. On revision E systems with CPUID Fn8000_0007[CPB]=1, if P0 is disabled then - * program F4x15C[BoostSrc]=0. This step uses hardware P-state numbering. - * e. Adjust the following P-state parameters affected by the P-state - * MSR copy by subtracting the number of P-states that are disabled - * by the power check. - * 1. F3x64[HtcPstateLimit] - * 2. F3x68[StcPstateLimit] - * 3. F3xDC[PstateMaxVal] - * 3. If all P-States are over the limit, the BIOS must: - * a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then - * write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for - * MSRC001_0063[CurPstate] to reflect the new value. - * b. If F3xDC[PstateMaxVal]!= 000b, copy the contents of the P-state - * MSR pointed to by F3xDC[PstateMaxVal] to MSRC001_0064 and set - * MSRC001_0064[PstateEn] - * c. Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063 - * [CurPstate] to reflect the new value. - * d. Adjust the following P-state parameters to zero on revision D and earlier processors. - * On revision E processors adjust the following fields to F4x15C[NumBoostStates]: - * 1. F3x64[HtcPstateLimit] - * 2. F3x68[StcPstateLimit] - * 3. F3xDC[PstateMaxVal] - * e. For revision E systems with CPUID Fn8000_0007[CPB]=1, program F4x15C[BoostSrc]=0. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F10PmPwrCheck ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 DisPsNum; - UINT8 PsMaxVal; - UINT8 Pstate; - UINT32 ProcIddMax; - UINT32 LocalPciRegister; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 AndMask; - UINT32 OrMask; - UINT32 PstateLimit; - PCI_ADDR PciAddress; - UINT64 LocalMsrRegister; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - PWRCHK_ERROR_DATA ErrorData; - - // get the socket number - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - ErrorData.SocketNumber = (UINT8)Socket; - - ASSERT (Core == 0); - - // get the Max P-state value - for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { - LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - break; - } - } - - ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1); - - DisPsNum = 0; - for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) { - if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) { - if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) { - // Add to event log the Pstate that exceeded the current limit - PutEventLog (AGESA_WARNING, - CPU_EVENT_PM_PSTATE_OVERCURRENT, - Socket, Pstate, 0, 0, StdHeader); - DisPsNum++; - } else { - break; - } - } - } - - // If all P-state registers are disabled, move P[PsMaxVal] to P0 - // and transition to P0, then wait for CurPstate = 0 - - ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum); - - // We only need to log this event on the BSC - if (ErrorData.AllowablePstateNumber == 0) { - PutEventLog (AGESA_FATAL, - CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT, - Socket, 0, 0, 0, StdHeader); - } - - if (DisPsNum != 0) { - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - // Check if CPB is supported. if yes, get the number of boost states. - ErrorData.NumberofBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader); - - TaskPtr.FuncAddress.PfApTaskI = F10PmPwrCheckCore; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA); - TaskPtr.DataTransfer.DataPtr = &ErrorData; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams); - - // Final Step 1 - // For revision E systems with CPUID Fn8000_0007[CPB]=1, if P0 is disabled then - // program F4x15C[BoostSrc]=0. This step uses hardware P-state numbering. - if (ErrorData.NumberofBoostStates == 1) { - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CPB_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->BoostSrc = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - // Final Step 2 - // F3x64[HtPstatelimit] -= disPsNum - // F3x68[StcPstateLimit]-= disPsNum - // F3xDC[PstateMaxVal]-= disPsNum - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = HTC_REG; - AndMask = 0xFFFFFFFF; - ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0; - OrMask = 0x00000000; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64 - PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit; - if (ErrorData.AllowablePstateNumber != 0) { - if (PstateLimit > DisPsNum) { - PstateLimit -= DisPsNum; - ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit; - } - } else { - ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = ErrorData.NumberofBoostStates; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); //F3x64 - - PciAddress.Address.Register = STC_REG; - AndMask = 0xFFFFFFFF; - ((STC_REGISTER *) &AndMask)->StcPstateLimit = 0; - OrMask = 0x00000000; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68 - PstateLimit = ((STC_REGISTER *) &LocalPciRegister)->StcPstateLimit; - if (ErrorData.AllowablePstateNumber != 0) { - if (PstateLimit > DisPsNum) { - PstateLimit -= DisPsNum; - ((STC_REGISTER *) &OrMask)->StcPstateLimit = PstateLimit; - } - } else { - ((STC_REGISTER *) &OrMask)->StcPstateLimit = ErrorData.NumberofBoostStates; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); //F3x68 - - PciAddress.Address.Register = CPTC2_REG; - AndMask = 0xFFFFFFFF; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0; - OrMask = 0x00000000; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC - PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal; - if (ErrorData.AllowablePstateNumber != 0) { - if (PstateLimit > DisPsNum) { - PstateLimit -= DisPsNum; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit; - } - } else { - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = ErrorData.NumberofBoostStates; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); //F3xDC - - // Now that P0 has changed, recalculate VSSlamTime - F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Core-level error handler called if any p-states were determined to be out - * of range for the mother board. - * - * This function implements steps 2a-c and 3a-c on each core. - * - * @param[in] ErrorData Details about the error condition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F10PmPwrCheckCore ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 PsMaxVal; - UINT8 DisPsNum; - UINT8 CurrentPs; - UINT8 EnBsNum; - UINT64 LocalMsrRegister; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); - DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - - ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber); - EnBsNum = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberofBoostStates; - - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate); - - if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) { - - // Step 1 - // Transition to Pstate Max if not there already - - if ((CurrentPs + EnBsNum) != PsMaxVal) { - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (PsMaxVal - EnBsNum), (BOOLEAN) TRUE, StdHeader); - } - - - // Step 2 - // If Pstate Max is not 000b, copy Pstate max contents to P0 and switch - // to P0. This step uses software P-state numbering - - if (PsMaxVal != 0) { - F10PmPwrChkCopyPstate (EnBsNum, PsMaxVal, StdHeader); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); - } - } else { - - // move remaining P-state register(s) up - // Step 1 - // Transition to a valid Pstate if current Pstate has been disabled - - if ((CurrentPs + EnBsNum) < DisPsNum) { - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (DisPsNum - EnBsNum), (BOOLEAN) TRUE, StdHeader); - CurrentPs = DisPsNum - EnBsNum; - } - - // Step 2 - // Move enabled Pstates up and disable the remainder. This step uses software P-state numbering. - if (DisPsNum > EnBsNum) { - for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) { - F10PmPwrChkCopyPstate ((i + EnBsNum), (i + DisPsNum), StdHeader); - } - } - // Step 3 - // Transition to current COF/VID at shifted location - - CurrentPs = ((CurrentPs + EnBsNum) - DisPsNum); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader); - } - i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber; - if (i == 0) { - ++i; - } - while (i <= PsMaxVal) { - FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader); - ++i; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Copies the contents of one P-State MSR to another. - * - * @param[in] Dest Destination p-state number - * @param[in] Src Source p-state number - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -F10PmPwrChkCopyPstate ( - IN UINT8 Dest, - IN UINT8 Src, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader); - LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader); -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.h deleted file mode 100644 index 7721a2866f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.h +++ /dev/null @@ -1,83 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Power related functions and structures - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F10_POWER_CHECK_H_ -#define _CPU_F10_POWER_CHECK_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/// Power Check Error Data -typedef struct { - UINT8 SocketNumber; ///< Socket Number - UINT8 HwPstateNumber; ///< Hardware P-state Number - UINT8 AllowablePstateNumber; ///< Allowable P-state Number - UINT8 NumberofBoostStates; ///< The Number of Boost States -} PWRCHK_ERROR_DATA; - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F10PmPwrCheck ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F10_POWER_CHECK_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h deleted file mode 100644 index 024e760b76..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h +++ /dev/null @@ -1,547 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Power Management related stuff - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPUF10POWERMGMT_H_ -#define _CPUF10POWERMGMT_H_ - -/* - * Family 10h CPU Power Management MSR definitions - * - */ - -/* Interrupt Pending and CMP-Halt MSR Register 0xC0010055 */ -#define MSR_INTPEND 0xC0010055 - -/// Interrupt Pending and CMP-Halt MSR Register -typedef struct { - UINT64 IoMsgAddr:16; ///< IO message address - UINT64 IoMsgData:8; ///< IO message data - UINT64 IntrPndMsgDis:1; ///< Interrupt pending message disable - UINT64 IntrPndMsg:1; ///< Interrupt pending message - UINT64 IoRd:1; ///< IO read - UINT64 SmiOnCmpHalt:1; ///< SMI on chip multi-processing halt - UINT64 C1eOnCmpHalt:1; ///< C1E on chip multi-processing halt - UINT64 BmStsClrOnHltEn:1; ///< Clear BM status bit on server C1e entry - UINT64 :34; ///< Reserved -} INTPEND_MSR; - - -/* P-state Current Limit Register 0xC0010061 */ -#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061 - -/// Pstate Current Limit MSR Register -typedef struct { - UINT64 CurPstateLimit:3; ///< Current Pstate Limit - UINT64 :1; ///< Reserved - UINT64 PstateMaxVal:3; ///< Pstate Max Value - UINT64 :57; ///< Reserved -} PSTATE_CURLIM_MSR; - - -/* P-state Control Register 0xC0010062 */ -#define MSR_PSTATE_CTL 0xC0010062 - -/// Pstate Control MSR Register -typedef struct { - UINT64 PstateCmd:3; ///< Pstate change command - UINT64 :61; ///< Reserved -} PSTATE_CTRL_MSR; - - -/* P-state Status Register 0xC0010063 */ -#define MSR_PSTATE_STS 0xC0010063 - -/// Pstate Status MSR Register -typedef struct { - UINT64 CurPstate:3; ///< Current Pstate - UINT64 :61; ///< Reserved -} PSTATE_STS_MSR; - - -/* P-state Registers 0xC001006[8:4] */ -#define MSR_PSTATE_0 0xC0010064 -#define MSR_PSTATE_1 0xC0010065 -#define MSR_PSTATE_2 0xC0010066 -#define MSR_PSTATE_3 0xC0010067 -#define MSR_PSTATE_4 0xC0010068 - -#define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */ -#define PS_MAX_REG MSR_PSTATE_4 /* Maximum P-State Register */ -#define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */ -#define NM_PS_REG 5 /* number of P-state MSR registers */ - -/// Pstate MSR -typedef struct { - UINT64 CpuFid:6; ///< CpuFid - UINT64 CpuDid:3; ///< CpuDid - UINT64 CpuVid:7; ///< CpuVid - UINT64 :6; ///< Reserved - UINT64 NbDid:1; ///< NbDid - UINT64 :2; ///< Reserved - UINT64 NbVid:7; ///< NbVid - UINT64 IddValue:8; ///< IddValue - UINT64 IddDiv:2; ///< IddDiv - UINT64 :21; ///< Reserved - UINT64 PsEnable:1; ///< Pstate Enable -} PSTATE_MSR; - - -/* COFVID Control Register 0xC0010070 */ -#define MSR_COFVID_CTL 0xC0010070 - -/// COFVID Control MSR Register -typedef struct { - UINT64 CpuFid:6; ///< CpuFid - UINT64 CpuDid:3; ///< CpuDid - UINT64 CpuVid:7; ///< CpuVid - UINT64 PstateId:3; ///< Pstate ID - UINT64 :3; ///< Reserved - UINT64 NbDid:1; ///< NbDid - UINT64 :2; ///< Reserved - UINT64 NbVid:7; ///< NbVid - UINT64 :32; ///< Reserved -} COFVID_CTRL_MSR; - - -/* COFVID Status Register 0xC0010071 */ -#define MSR_COFVID_STS 0xC0010071 - -/// COFVID Status MSR Register -typedef struct { - UINT64 CurCpuFid:6; ///< Current CpuFid - UINT64 CurCpuDid:3; ///< Current CpuDid - UINT64 CurCpuVid:7; ///< Current CpuVid - UINT64 CurPstate:3; ///< Current Pstate - UINT64 :3; ///< Reserved - UINT64 CurNbDid:1; ///< Current NbDid - UINT64 :2; ///< Reserved - UINT64 CurNbVid:7; ///< Current NbVid - UINT64 StartupPstate:3; ///< Startup Pstate - UINT64 MaxVid:7; ///< MaxVid - UINT64 MinVid:7; ///< MinVid - UINT64 MaxCpuCof:6; ///< MaxCpuCof - UINT64 :1; ///< Reserved - UINT64 CurPstateLimit:3; ///< Current Pstate Limit - UINT64 MaxNbFid:5; ///< MaxNbFid -} COFVID_STS_MSR; - -/* C-state Address Register 0xC0010073 */ -#define MSR_CSTATE_ADDRESS 0xC0010073 - -/// C-state Address MSR Register -typedef struct { - UINT64 CstateAddr:16; ///< C-state address - UINT64 :48; ///< Reserved -} CSTATE_ADDRESS_MSR; - -/* - * Family 10h CPU Power Management PCI definitions - * - */ - -/* DRAM Configuration High Register F2x[1,0]94 */ -#define DRAM_CFG_HI_REG0 0x94 -#define DRAM_CFG_HI_REG1 0x194 - -/// DRAM Configuration High PCI Register -typedef struct { - UINT32 MemClkFreq:3; ///< Memory clock frequency - UINT32 MemClkFreqVal:1; ///< Memory clock frequency valid - UINT32 :4; ///< Reserved - UINT32 Ddr3Mode:1; ///< DDR3 mode - UINT32 LegacyBiosMode:1; ///< Legacy BIOS mode - UINT32 ZqcsInterval:2; ///< ZQ calibration short interval - UINT32 RDqsEn:1; ///< Read DQS enable - UINT32 DisSimulRdWr:1; ///< Disable simultaneous read and write - UINT32 DisDramInterface:1; ///< Disable the DRAM interface - UINT32 PowerDownEn:1; ///< Power down mode enable - UINT32 PowerDownMode:1; ///< Power down mode - UINT32 :1; ///< Reserved - UINT32 FourRankRDimm:1; ///< Four rank registered DIMM connected - UINT32 DcqArbBypassEn:1; ///< DRAM controller arbiter bypass enable - UINT32 SlowAccessMode:1; ///< Slow access mode - UINT32 FreqChgInProg:1; ///< Frequency change in progress - UINT32 BankSwizzleMode:1; ///< Bank swizzle mode - UINT32 ProcOdtDis:1; ///< Processor on-die termination disable - UINT32 DcqBypassMax:4; ///< DRAM controller queue bypass maximum - UINT32 FourActWindow:4; ///< Four bank activate window -} DRAM_CFG_HI_REGISTER; - - -/* Extended Memory Controller Configuration Low Register F2x1B0 */ -#define EXT_MEMCTRL_CFG_LOW_REG 0x1B0 - -/// Extended Memory Controller Configuration Low PCI Register -typedef struct { - UINT32 AdapPrefMissRatio:2; ///< Adaptive prefetch miss ratio - UINT32 AdapPrefPositiveStep:2; ///< Adaptive prefetch positive step - UINT32 AdapPrefNegativeStep:2; ///< Adaptive prefetch negative step - UINT32 :2; ///< Reserved - UINT32 CohPrefPrbLmt:3; ///< Coherent prefetch probe limit - UINT32 DisIoCohPref:1; ///< Disable coherent prefetched for IO - UINT32 EnSplitDctLimits:1; ///< Split DCT write limits enable - UINT32 SpecPrefDis:1; ///< Speculative prefetch disable - UINT32 SpecPrefMis:1; ///< Speculative prefetch predict miss - UINT32 SpecPrefThreshold:3; ///< Speculative prefetch threshold - UINT32 :4; ///< Reserved - UINT32 PrefFourConf:3; ///< Prefetch four-ahead confidence - UINT32 PrefFiveConf:3; ///< Prefetch five-ahead confidence - UINT32 DcqBwThrotWm:4; ///< Dcq bandwidth throttle watermark -} EXT_MEMCTRL_CFG_LOW_REGISTER; - - -/* Scrub Rate Control Register F3x58 */ -#define SCRUB_RATE_CTRL_REG 0x58 - -/// Scrub Rate Control PCI Register -typedef struct { - UINT32 DramScrub:5; ///< DRAM scrub rate - UINT32 :3; ///< Reserved - UINT32 L2Scrub:5; ///< L2 cache scrub rate - UINT32 :3; ///< Reserved - UINT32 DcacheScrub:5; ///< Data cache scrub rate - UINT32 :3; ///< Reserved - UINT32 L3Scrub:5; ///< L3 cache scrub rate - UINT32 :3; ///< Reserved -} SCRUB_RATE_CTRL_REGISTER; - -/* DRAM Scrub Address Low Register F3x5C */ -#define DRAM_SCRUB_ADDR_LOW_REG 0x5C - -/// DRAM Scrub Address Low PCI Register -typedef struct { - UINT32 ScrubReDirEn:1; ///< DRAM scrubber redirect enable - UINT32 :5; ///< Reserved - UINT32 ScrubAddrLo:26; ///< DRAM scrubber address bits[31:6] -} DRAM_SCRUB_ADDR_LOW_REGISTER; - - -/* Hardware thermal control register F3x64 */ -#define HTC_REG 0x64 -#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG)) - -/// Hardware Thermal Control PCI Register -typedef struct { - UINT32 HtcEn:1; ///< HTC Enable - UINT32 :3; ///< Reserved - UINT32 HtcAct:1; ///< HTC Active State - UINT32 HtcActSts:1; ///< HTC Active Status - UINT32 PslApicHiEn:1; ///< P-state limit higher APIC int enable - UINT32 PslApicLoEn:1; ///< P-state limit lower APIC int enable - UINT32 :8; ///< Reserved - UINT32 HtcTmpLmt:7; ///< HTC temperature limit - UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select - UINT32 HtcHystLmt:4; ///< HTC hysteresis - UINT32 HtcPstateLimit:3; ///< HTC P-state limit select - UINT32 :1; ///< Reserved -} HTC_REGISTER; - - -/* Software thermal control register F3x68 */ -#define STC_REG 0x68 - -/// Software Thermal Control PCI Register -typedef struct { - UINT32 StcSbcTmpHiEn:1; ///< STC SBC temperature high enable - UINT32 StcSbcTmpLoEn:1; ///< STC SBC temperature low enable - UINT32 StcApcTmpHiEn:1; ///< STC APIC temperature high enable - UINT32 StcApcTmpLoEn:1; ///< STC APIC temperature low enable - UINT32 :1; ///< Reserved - UINT32 StcPstateEn:1; ///< STC P-state enable - UINT32 StcTmpHiSts:1; ///< STC temperature high status - UINT32 StcTmpLoSts:1; ///< STC temperature low status - UINT32 :8; ///< Reserved - UINT32 StcTmpLmt:7; ///< STC temperature limit - UINT32 StcSlewSel:1; ///< STC slew-controlled temp select - UINT32 StcHystLmt:4; ///< STC hysteresis - UINT32 StcPstateLimit:3; ///< STC P-state limit select - UINT32 :1; ///< Reserved -} STC_REGISTER; - -/* ACPI Power State Control Registers F3x84:80 */ - -/// System Management Action Field (SMAF) Register -typedef struct { - UINT8 CpuPrbEn:1; ///< CPU direct probe enable - UINT8 NbLowPwrEn:1; ///< Northbridge low-power enable - UINT8 NbGateEn:1; ///< Northbridge gate enable - UINT8 NbCofChg:1; ///< NbCofChg - UINT8 AltVidEn:1; ///< alternate VID enable - UINT8 ClkDivisor:3; ///< Clock divisor -} SMAF_REGISTER; - -/// union type for ACPI State SMAF setting -typedef union { - UINT8 SMAFValue; ///< SMAF raw value - SMAF_REGISTER SMAF; ///< SMAF structure -} ACPI_STATE_SMAF; - -/// ACPI Power State Control Register F3x80 -typedef struct { - ACPI_STATE_SMAF C2; ///< [7:0] SMAF Code 000b - C2 - ACPI_STATE_SMAF C3C1eLinkInit; ///< [15:8] SMAF Code 001b - C3, C1e or Link init - ACPI_STATE_SMAF FidVidChg; ///< [23:16] SMAF Code 010b - FIDVID Change - ACPI_STATE_SMAF S1; ///< [31:24] SMAF Code 011b - S1 -} ACPI_PSC_0_REGISTER; - -/// ACPI Power State Control Register F3x84 -typedef struct { - ACPI_STATE_SMAF S3; ///< [7:0] SMAF Code 100b - S3 - ACPI_STATE_SMAF Throttling; ///< [15:8] SMAF Code 101b - Throttling - ACPI_STATE_SMAF S4S5; ///< [23:16] SMAF Code 110b - S4/S5 - ACPI_STATE_SMAF C1; ///< [31:24] SMAF Code 111b - C1 -} ACPI_PSC_4_REGISTER; - - -/* Power Control Miscellaneous Register F3xA0 */ -#define PW_CTL_MISC_REG 0xA0 -#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG)) - -/// Power Control Miscellaneous PCI Register -typedef struct { - UINT32 PsiVid:7; ///< PSI_L VID threshold - UINT32 PsiVidEn:1; ///< PSI_L VID enable - UINT32 PviMode:1; ///< Parallel VID interface mode - UINT32 SviHighFreqSel:1; ///< SVI high frequency select - UINT32 IdleExitEn:1; ///< IDLEEXIT_L Enable - UINT32 PllLockTime:3; ///< PLL synchronization lock time - UINT32 BpPinsTriEn:1; ///< Breakpoint pins tristate enable - UINT32 :1; ///< Reserved - UINT32 PstateId:12; ///< Pstate ID - UINT32 :1; ///< Reserved - UINT32 SlamVidMode:1; ///< Slam voltage ID mode - UINT32 :1; ///< Reserved - UINT32 CofVidProg:1; ///< COF and VID of Pstate programmed -} POWER_CTRL_MISC_REGISTER; - -/* Popup P-state Register F3xA8 */ -#define POPUP_PSTATE_REG 0xA8 -#define POPUP_PSTATE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, POPUP_PSTATE_REG)) - -/// Popup P-state Register -typedef struct { - UINT32 PopupEn:1; ///< Popup enable - UINT32 :1; ///< Reserved - UINT32 PopupPstate:3; ///< Popup P-state - UINT32 PopupCpuVid:7; ///< Popup core VID - UINT32 PopupCpuFid:6; ///< Popup core FID - UINT32 PopupCpuDid:3; ///< Popup core DID - UINT32 :6; ///< Reserved - UINT32 CacheFlushPopDownEn:1; ///< Cache Flush PopDown P-state Enable - UINT32 :1; ///< Reserved - UINT32 PopDownPstate:3; ///< Pop-down P-state number -} POPUP_PSTATE_REGISTER; - -/* Clock Power/Timing Control 0 Register F3xD4 */ -#define CPTC0_REG 0xD4 - -/// Clock Power Timing Control PCI Register -typedef struct { - UINT32 NbFid:5; ///< NbFid - UINT32 NbFidEn:1; ///< NbFidEn - UINT32 :2; ///< Reserved - UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select - UINT32 ClkRampHystCtl:1; ///< Clock Ramp Hysteresis Control - UINT32 MTC1eEn:1; ///< Message Triggered C1e Enable - UINT32 CacheFlushImmOnAllHalt:1; ///< Cache Flush Immediate on All Halt - UINT32 StutterScrubEn:1; ///< Stutter Mode Scrub Enable - UINT32 LnkPllLock:2; ///< Link PLL Lock - UINT32 :2; ///< Reserved - UINT32 PowerStepDown:4; ///< Power Step Down - UINT32 PowerStepUp:4; ///< Power Step Up - UINT32 NbClkDiv:3; ///< NbClkDiv - UINT32 NbClkDivApplyAll:1; ///< NbClkDivApplyAll -} CLK_PWR_TIMING_CTRL_REGISTER; - - -/* Clock Power/Timing Control 1 Register F3xD8 */ -#define CPTC1_REG 0xD8 - -/// Clock Power Timing Control 1 PCI Register -typedef struct { - UINT32 VSSlamTime:3; ///< Voltage stabilization slam time - UINT32 :1; ///< Reserved - UINT32 VSRampTime:3; ///< Voltage stabilization ramp time - UINT32 :1; ///< Reserved - UINT32 TdpVid:7; ///< Thermal design power VID - UINT32 :1; ///< Reserved - UINT32 AltVidStart:7; ///< Alternate VID start limit - UINT32 :1; ///< Reserved - UINT32 ReConDel:4; ///< Link reconnect delay - UINT32 PwrPlanes:1; ///< Power planes - UINT32 :3; ///< Reserved -} CLK_PWR_TIMING_CTRL1_REGISTER; - - -/* Clock Power/Timing Control 2 Register F3xDC */ -#define CPTC2_REG 0xDC -#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG)) -/// Clock Power Timing Control 2 PCI Register -typedef struct { - UINT32 AltVid:7; ///< Alternate VID - UINT32 :1; ///< Reserved - UINT32 PstateMaxVal:3; ///< P-state maximum value - UINT32 :1; ///< Reserved - UINT32 NbsynPtrAdj:3; ///< NB/Core sync FIFO ptr adjust - UINT32 :1; ///< Reserved - UINT32 CacheFlushOnHaltCtl:3; ///< Cache flush on halt control - UINT32 CacheFlushOnHaltTmr:7; ///< Cache flush on halt timer - UINT32 :1; ///< Reserved - UINT32 SlamTimeMode:2; ///< Slam time mode - UINT32 AltvidVSSlamTime:3; ///< Altvid voltage stabilization slam time -} CLK_PWR_TIMING_CTRL2_REGISTER; - - -/* Northbridge Capabilities Register F3xE8 */ -#define NB_CAPS_REG 0xE8 - -/// Northbridge Capabilities PCI Register -typedef struct { - UINT32 DctDualCap:1; ///< Two-channel DRAM capable - UINT32 DualNodeCap:1; ///< Dual-node multi-processor capable - UINT32 EightNodeCap:1; ///< Eight-node multi-processor capable - UINT32 EccCapable:1; ///< ECC capable - UINT32 ChipkillCapable:1; ///< Chipkill ECC capable - UINT32 DdrMaxRate:3; ///< Maximum DRAM data rate - UINT32 MctCap:1; ///< Memory controller capable - UINT32 SvmCapable:1; ///< SVM capable - UINT32 HtcCapable:1; ///< HTC capable - UINT32 LnkRtryCap:1; ///< Link error-retry capable - UINT32 CmpCapLo:2; ///< CMP capable[1:0] - UINT32 MultiVidPlaneCap:1; ///< Multiple VID plane capable - UINT32 CmpCapHi:1; ///< CMP capable[2] - UINT32 MpCap:3; ///< MP capability - UINT32 :1; ///< Reserved - UINT32 UnGangEn:4; ///< Link unganging enabled - UINT32 :1; ///< Reserved - UINT32 L3Capable:1; ///< L3 capable - UINT32 HtAcCapable:1; ///< HT AC capable - UINT32 :2; ///< Reserved - UINT32 MultiNodeCpu:1; ///< Multinode processor - UINT32 IntNodeNum:2; ///< Internal node number -} NB_CAPS_REGISTER; - - -/* NB Extended Configuration Low Register F3x188 */ -#define NB_EXT_CFG_LO_REG 0x188 - -/// Northbridge Extended Configuration Low PCI Register -typedef struct { - UINT32 :4; ///< Reserved - UINT32 EnStpGntOnFlushMaskWakeup:1; ///< Enable stop grant on flush mask wakeup - UINT32 :27; ///< Reserved -} NB_EXT_CFG_LO_REGISTER; - - -/* L3 Cache Parameter Register F3x1C4 */ -#define L3_CACHE_PARAM_REG 0x1C4 - -/// L3 Cache Parameter PCI Register -typedef struct { - UINT32 L3SubcacheSize0:1; ///< L3 subcache size 0 - UINT32 :3; ///< Reserved - UINT32 L3SubcacheSize1:1; ///< L3 subcache size 1 - UINT32 :3; ///< Reserved - UINT32 L3SubcacheSize2:2; ///< L3 subcache size 2 - UINT32 :2; ///< Reserved - UINT32 L3SubcacheSize3:2; ///< L3 subcache size 3 - UINT32 :17; ///< Reserved - UINT32 L3TagInit:1; ///< L3 tag initialization -} L3_CACHE_PARAM_REGISTER; - - -/* Probe Filter Control Register F3x1D4 */ -#define PROBE_FILTER_CTRL_REG 0x1D4 - -/// Probe Filter Control PCI Register -typedef struct { - UINT32 PFMode:2; ///< Probe Filter Mode - UINT32 PFWayNum:2; ///< Probe Filter way number - UINT32 PFSubCacheSize0:2; ///< Probe filter subcache 0 size - UINT32 PFSubCacheSize1:2; ///< Probe filter subcache 1 size - UINT32 PFSubCacheSize2:2; ///< Probe filter subcache 2 size - UINT32 PFSubCacheSize3:2; ///< Probe filter subcache 3 size - UINT32 PFSubCacheEn:4; ///< Probe filter subcache enable - UINT32 :3; ///< Reserved - UINT32 PFInitDone:1; ///< Probe filter initialization done - UINT32 PFPreferredSORepl:2; ///< PF preferredSO replacement mode - UINT32 PFErrInt:2; ///< Probe filter error interrupt type - UINT32 PFErrIntLvtOff:4; ///< Probe filter error interrupt LVT offset - UINT32 PFEccError:1; ///< Probe filter ECC error - UINT32 PFLoIndexHashEn:1; ///< Probe filter low index hash enable - UINT32 :2; ///< Reserved -} PROBE_FILTER_CTRL_REGISTER; - - -/* Product Info Register F3x1FC */ -#define PRCT_INFO_REG 0x1FC -#define PRCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRCT_INFO_REG)) - -/// Product Information PCI Register -typedef struct { - UINT32 NbCofVidUpdate:1; ///< NbCofVidUpdate - UINT32 NbVidUpdateAll:1; ///< NbVidUpdateAll - UINT32 SinglePlaneNbFid:5; ///< SinglePlaneNbFid - UINT32 SinglePlaneNbVid:7; ///< SinglePlaneNbVid - UINT32 DualPlaneNbFidOff:3; ///< DualPlaneNbFidOff - UINT32 DualPlaneNbVidOff:5; ///< DualPlaneNbVidOff - UINT32 SinglePlaneNbIdd:4; ///< SinglePlaneNbIdd -} PRODUCT_INFO_REGISTER; - -/* Core Performance Boost Control Register D18F4x15C */ -#define CPB_CTRL_REG 0x15C -#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG)) - -/// Core Performance Boost Control Register -typedef struct { - UINT32 BoostSrc:2; ///< Boost source - UINT32 NumBoostStates:1; ///< Number of boosted states - UINT32 :27; ///< Reserved - UINT32 BoostLock:1; ///< Boost Lock -} CPB_CTRL_REGISTER; -#endif /* _CPUF10POWERMGMT_H */ - -/* Boost Offset Register F3x10C */ -#define F3x10C_REG 0x10C -#define F3x10C_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, F3x10C_REG)) - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c deleted file mode 100644 index 866c10bc80..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c +++ /dev/null @@ -1,182 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Power Management related stuff - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "cpuPowerMgmtSystemTables.h" -#include "cpuF10EarlyInit.h" -#include "cpuF10SoftwareThermal.h" -#include "cpuF10PowerPlane.h" -#include "cpuF10PowerCheck.h" -#include "F10PmNbCofVidInit.h" -#include "F10PmNbPstateInit.h" -#include "F10PmAsymBoostInit.h" -#include "F10PmDualPlaneOnlySupport.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -GetF10SysPmTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **SysPmTblPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* Family 10h Only Table */ -/* ---------------------- */ -CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] = -{ - IDS_INITIAL_F10_PM_STEP - - // Step 1 - Configure F3x[84:80]. Handled by PCI register table. - // Step 2 - Configure Northbridge COF and VID. - // Execute both cold & warm - { - 0, - F10PmNbCofVidInit - }, - - // Step 3 - Dual-plane Only Support. - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F10PmDualPlaneOnlySupport - }, - - // Step 4 - Asymmetric Boost. - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F10PmAsymBoostInit - }, - - // Step 5 - Configure Nb-Pstates. - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F10PmNbPstateInit - }, - // Step 6 - Power Plane Initialization - // Execute both cold & warm - { - 0, // ExeFlags - F10CpuAmdPmPwrPlaneInit // Function Pointer - }, - - // Step 7 - Pmin Transition After Reset - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F10PmAfterReset // Function Pointer - }, - - // Step 8 - Current Delivery Check - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F10PmPwrCheck // Function Pointer - }, - - // Step x - Software Thermal Control Init - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F10PmThermalInit // Function Pointer - }, -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the appropriate table of steps to perform to initialize the power management - * subsystem. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] SysPmTblPtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF10SysPmTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **SysPmTblPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = (sizeof (CpuF10SysPmTableArray) / sizeof (SYS_PM_TBL_STEP)); - *SysPmTblPtr = CpuF10SysPmTableArray; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.c deleted file mode 100644 index 39a17be7af..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.c +++ /dev/null @@ -1,485 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Power Plane Initialization - * - * Performs the "BIOS Requirements for Power Plane Initialization" as described - * in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuF10PowerMgmt.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF10Utilities.h" -#include "cpuF10PowerPlane.h" -#include "Table.h" -#include "F10PackageType.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -// Register encodings for F3xD4[PowerStepUp/PowerStepDown] -CONST UINT16 ROMDATA PowerStepEncodings[16] = -{ - 400, // 0000b: 400ns - 300, // 0001b: 300ns - 200, // 0010b: 200ns - 100, // 0011b: 100ns - 90, // 0100b: 90ns - 80, // 0101b: 80ns - 70, // 0110b: 70ns - 60, // 0111b: 60ns - 50, // 1000b: 50ns - 45, // 1001b: 45ns - 40, // 1010b: 40ns - 35, // 1011b: 35ns - 30, // 1100b: 30ns - 25, // 1101b: 25ns - 20, // 1110b: 20ns - 15 // 1111b: 15ns -}; - -// Register encodings for F3xDC[AltvidVSSlamTime] -CONST UINT32 ROMDATA AltvidSlamTime[8] = -{ - 0, // 000b: <1us - 10, // 001b: 10us - 20, // 010b: 20us - 40, // 011b: 40us - 50, // 100b: 50us - 70, // 101b: 70us - 80, // 110b: 80us - 90 // 111b: 90us -}; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F10PmPwrPlaneInitPviCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -STATIC -F10CalculateAltvidVSSlamTimeOnCore ( - IN BOOLEAN PviModeFlag, - IN PCI_ADDR *PciAddress, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F10PmVrmLowPowerModeEnable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------*/ -/** - * Family 10h core 0 entry point for performing power plane initialization. - * - * The steps are as follows: - * 1. If single plane, program lower VID code of CpuVid & NbVid for all - * enabled P-States. - * 2. Configure F3xA0[SlamMode] & F3xD8[VsRampTime & VsSlamTime] based on - * platform requirements. - * 3. Configure F3xD4[PowerStepUp & PowerStepDown] - * 4. Optionally configure F3xA0[PsiVidEn & PsiVid] - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F10CpuAmdPmPwrPlaneInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN PviModeFlag; - PCI_ADDR PciAddress; - UINT16 PowerStepTime; - UINT32 PowerStepEncoded; - UINT32 LocalPciRegister; - UINT32 VsSlamTime; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 NumOfCores; - UINT32 LowCore; - UINT32 AndMask; - UINT32 OrMask; - UINT32 ProcessorPackageType; - UINT64 LocalMsrRegister; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - PLATFORM_FEATS Features; - CPU_LOGICAL_ID LogicalId; - - // Initialize the union - Features.PlatformValue = 0; - GetPlatformFeatures (&Features, &CpuEarlyParams->PlatformConfig, StdHeader); - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - - ASSERT (Core == 0); - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - - // Set SlamVidMode - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PW_CTL_MISC_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - AndMask = 0xFFFFFFFF; - OrMask = 0x00000000; - if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 1) { - PviModeFlag = TRUE; - ((POWER_CTRL_MISC_REGISTER *) &AndMask)->SlamVidMode = 0; - - // Have all single plane cores adjust their NB and CPU VID fields - TaskPtr.FuncAddress.PfApTask = F10PmPwrPlaneInitPviCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams); - - } else { - PviModeFlag = FALSE; - ((POWER_CTRL_MISC_REGISTER *) &OrMask)->SlamVidMode = 1; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader); - - // Configure PowerStepUp/PowerStepDown - PciAddress.Address.Register = CPTC0_REG; - if ((Features.PlatformFeatures.PlatformSingleLink == 1) || - (Features.PlatformFeatures.PlatformUma == 1) || - (Features.PlatformFeatures.PlatformUmaIfcm == 1) || - (Features.PlatformFeatures.PlatformIfcm == 1) || - (Features.PlatformFeatures.PlatformIommu == 1)) { - PowerStepEncoded = 0x8; - } else { - GetGivenModuleCoreRange ((UINT32) Socket, - (UINT32) Module, - &LowCore, - &NumOfCores, - StdHeader); - NumOfCores = ((NumOfCores - LowCore) + 1); - PowerStepTime = (UINT16) (400 / NumOfCores); - for (PowerStepEncoded = 0xF; PowerStepEncoded > 0; PowerStepEncoded--) { - if (PowerStepTime <= PowerStepEncodings[PowerStepEncoded]) { - break; - } - } - } - AndMask = 0xFFFFFFFF; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepUp = 0; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepDown = 0; - OrMask = 0x00000000; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = PowerStepEncoded; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = PowerStepEncoded; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - if ((LogicalId.Revision & AMD_F10_C3) != 0) { - // Set up Pop up P-state register - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - AndMask = 0xFFFFFFFF; - ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupPstate = 0; - ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuVid = 0; - ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuFid = 0; - ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuDid = 0; - OrMask = 0x00000000; - ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0; - ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal; - LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal + PS_REG_BASE), &LocalMsrRegister, StdHeader); - ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->CpuVid; - ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid; - ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid; - PciAddress.Address.Register = POPUP_PSTATE_REG; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - // Set AltVidStart - PciAddress.Address.Register = CPTC1_REG; - AndMask = 0xFFFFFFFF; - ((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0; - OrMask = 0x00000000; - ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->CpuVid; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - // Set up Altvid slam time - ProcessorPackageType = LibAmdGetPackageType (StdHeader); - PciAddress.Address.Register = CPTC2_REG; - VsSlamTime = F10CalculateAltvidVSSlamTimeOnCore (PviModeFlag, &PciAddress, CpuEarlyParams, StdHeader); - AndMask = 0xFFFFFFFF; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->AltvidVSSlamTime = 0; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->SlamTimeMode = 0; - OrMask = 0x00000000; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->AltvidVSSlamTime = VsSlamTime; - if (ProcessorPackageType == PACKAGE_TYPE_S1G3_S1G4 || ProcessorPackageType == PACKAGE_TYPE_ASB2) { - // If CPUID Fn8000_0001_EBX[PkgType]=0010b or 0100b, BIOS should program this to 10b; - // else BIOS should leave this field at 00b. - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->SlamTimeMode = 2; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - } - - if (IsWarmReset (StdHeader) && !PviModeFlag) { - // Configure PsiVid - F10PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, PciAddress, StdHeader); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F10CpuAmdPmPwrPlaneInit. - * - * This function implements step 1 on each core. - * - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F10PmPwrPlaneInitPviCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MsrAddr; - UINT32 NbVid; - UINT32 CpuVid; - UINT64 LocalMsrRegister; - - for (MsrAddr = PS_REG_BASE; MsrAddr <= PS_MAX_REG; MsrAddr++) { - LibAmdMsrRead (MsrAddr, &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == (UINT64) 1) { - NbVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->NbVid); - CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid); - if (NbVid != CpuVid) { - if (NbVid > CpuVid) { - NbVid = CpuVid; - } - ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = NbVid; - ((PSTATE_MSR *) &LocalMsrRegister)->CpuVid = NbVid; - LibAmdMsrWrite (MsrAddr, &LocalMsrRegister, StdHeader); - } - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the encoded altvid voltage stabilization slam time for the executing - * family 10h core. - * - * This function calculates how much time it will take for the voltage to - * stabilize when transitioning from altvid to Pmin, and returns the necessary - * encoded value for the amount of time discovered. - * - * @param[in] PviModeFlag Whether or not the platform uses VRMs that - * employ the parallel VID interface. - * @param[in] PciAddress Full PCI address of the executing core's config space. - * @param[in] CpuEarlyParams Service parameters - * @param[in] StdHeader Config handle for library and services. - * - * @retval Encoded register value. - * - */ -UINT32 -STATIC -F10CalculateAltvidVSSlamTimeOnCore ( - IN BOOLEAN PviModeFlag, - IN PCI_ADDR *PciAddress, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NbVid; - UINT8 AltVidCode; - UINT8 PminVidCode; - UINT32 MsrAddr; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - PCI_ADDR LocalPciAddress; - - // Calculate Slam Time - // VSSlamTime = 0.4us/mV (or 0.2us/mV) * Vpmin - Altvid - // In our case, we will scale the values by 100 to avoid - // decimals. - - // Get Pmin's index - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal) + PS_REG_BASE); - - // Get Pmin's VID - LibAmdMsrRead (MsrAddr, &LocalMsrRegister, StdHeader); - PminVidCode = (UINT8) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid); - - // If SVI, we only care about CPU VID. - // If PVI, determine the higher voltage b/t NB and CPU - if (PviModeFlag) { - NbVid = (UINT8) (((PSTATE_MSR *) &LocalMsrRegister)->NbVid); - if (PminVidCode > NbVid) { - PminVidCode = NbVid; - } - } - - // Get Alt VID - LocalPciAddress.AddressValue = PciAddress->AddressValue; - LocalPciAddress.Address.Function = FUNC_3; - LocalPciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, LocalPciAddress, &LocalPciRegister, StdHeader); - AltVidCode = (UINT8) (((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->AltVid); - - return (F10GetSlamTimeEncoding (PminVidCode, AltVidCode, CpuEarlyParams, AltvidSlamTime, StdHeader)); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Sets up PSI_L operation. - * - * This function implements the LowPowerThreshold parameter. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Contains VrmLowPowerThreshold parameter. - * @param[in] PciAddress PCI address of the executing core's config space. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F10PmVrmLowPowerModeEnable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Pstate; - UINT32 PstateCurrent; - UINT32 NextPstateCurrent; - UINT32 AndMask; - UINT32 OrMask; - UINT32 PreviousVID; - UINT32 PstateVID; - UINT32 HwPsMaxVal; - UINT64 PstateMsr; - BOOLEAN EnablePsi; - - if (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold != 0) { - EnablePsi = FALSE; - PreviousVID = 0x7F; // Initialize to invalid zero volt VID code - PstateVID = 0x7F; - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader); - - for (Pstate = 0; Pstate <= (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal; Pstate++) { - if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader)) { - LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader); - PstateVID = (UINT32) (((PSTATE_MSR *) &PstateMsr)->CpuVid); - if ((Pstate + 1) > (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal) { - NextPstateCurrent = 0; - } else if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader)) { - NextPstateCurrent = CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].InrushCurrentLimit + NextPstateCurrent; - } - if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && (NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && (PstateVID != PreviousVID)) { - EnablePsi = TRUE; - break; - } - PreviousVID = PstateVID; - } - } - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PW_CTL_MISC_REG; - AndMask = 0xFFFFFFFF; - OrMask = 0x00000000; - ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVid = 0; - if (EnablePsi) { - ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVid = PstateVID; - ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVidEn = 1; - } else { - ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVidEn = 0; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.h deleted file mode 100644 index d909532cb0..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Power Plane related functions and structures - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F10_POWER_PLANE_H_ -#define _CPU_F10_POWER_PLANE_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F10CpuAmdPmPwrPlaneInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F10_POWER_PLANE_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c deleted file mode 100644 index c8b54e2e94..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c +++ /dev/null @@ -1,894 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Pstate feature support functions. - * - * Provides the functions necessary to initialize the Pstate feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuPstateTables.h" -#include "Table.h" -#include "cpuFamilyTranslation.h" -#include "cpuFamRegisters.h" -#include "cpuF10Utilities.h" -#include "cpuF10PowerMgmt.h" -#include "CommonReturns.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -F10GetPstateTransLatency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F10GetPstateFrequency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F10PstateLevelingCoreMsrModify ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F10GetPstatePower ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F10GetPstateMaxState ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F10GetPstateRegisterInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F10GetPowerStepValueInTime ( - IN OUT UINT32 *PowerStepPtr - ); - -VOID -STATIC -F10GetPllValueInTime ( - IN OUT UINT32 *PllLockTimePtr - ); - -AGESA_STATUS -STATIC -F10GetFrequencyXlatRegInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 PStateNumber, - IN UINT32 Frequency, - OUT UINT32 *CpuFidPtr, - OUT UINT32 *CpuDidPtr1, - OUT UINT32 *CpuDidPtr2, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if Pstate PSD is dependent. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE PSD is dependent. - * @retval FALSE PSD is independent. - * - */ -BOOLEAN -STATIC -F10IsPstatePsdDependent ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID CpuLogicalId; - PLATFORM_FEATS Features; - - // Initialize the union - Features.PlatformValue = 0; - GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader); - GetPlatformFeatures (&Features, PlatformConfig, StdHeader); - - // - // RevC and later Single link has PSD option, default is dependent. - // If multi-link, always return independent. - // - if ((Features.PlatformFeatures.PlatformSingleLink) && ((CpuLogicalId.Revision & AMD_F10_GT_Bx) != 0)) { - if (PlatformConfig->ForcePstateIndependent) { - return FALSE; - } - return TRUE; - } - return FALSE; -} - -/** - * Family specific call to set core TscFreqSel. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F10SetTscFreqSel ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrValue; - - LibAmdMsrRead (MSR_HWCR, &MsrValue, StdHeader); - if (UserOptions.OptionMultisocket) { - // - // If Agesa need to do p-state leveling on multi-socket, changing the P0 - // frequency after setting this bit has no effect on the TSC rate. - // - ASSERT ((MsrValue & BIT24) == 0); - } - MsrValue = MsrValue | BIT24; - LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get Pstate Transition Latency. - * - * Calculate TransitionLatency by power step value and pll value. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer - * @param[in] PciAddress Pci address - * @param[out] TransitionLatency The transition latency. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F10GetPstateTransLatency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempVar_b; - UINT32 TempVar_c; - UINT32 TempVar_d; - UINT32 TempVar8_a; - UINT32 TempVar8_b; - UINT32 Ignored; - UINT32 k; - UINT32 CpuFidSameFlag; - UINT8 PStateMaxValueOnCurrentCore; - UINT32 TransAndBusMastLatency; - - CpuFidSameFlag = 1; - - F10GetFrequencyXlatRegInfo ( - PstateCpuServices, - 0, - PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[0].CoreFreq, - &TempVar_b, - &TempVar_c, - &Ignored, - StdHeader - ); - - TempVar_d = TempVar_b; - PStateMaxValueOnCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue; - - // - //Check if MSRC001_00[68:64][CpuFid] is the same value for all P-states where - //MSRC001_00[68:64][PstateEn]=1 - // - for (k = 1; k <= PStateMaxValueOnCurrentCore; k++) { - if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) { - F10GetFrequencyXlatRegInfo ( - PstateCpuServices, - (UINT8) k, - PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq, - &TempVar_b, - &TempVar_c, - &Ignored, - StdHeader - ); - } - - if (TempVar_d != TempVar_b) { - CpuFidSameFlag = 0; - break; - } - } - - PciAddress->Address.Register = 0xD4; - PciAddress->Address.Function = FUNC_3; - LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader); - - // PowerStepDown - Bits 20:23 - TempVar8_a = (TempVar_d & 0x00F00000) >> 20; - - // PowerStepUp - Bits 24:27 - TempVar8_b = (TempVar_d & 0x0F000000) >> 24; - - // Convert the raw numbers in TempVar8_a and TempVar8_b into time - F10GetPowerStepValueInTime (&TempVar8_a); - F10GetPowerStepValueInTime (&TempVar8_b); - - // - //(12 * (F3xD4[PowerStepDown] + F3xD4[PowerStepUp]) /1000) us - // - TransAndBusMastLatency = - (12 * (TempVar8_a + TempVar8_b) + 999) / 1000; - - if (CpuFidSameFlag == 0) { - // - //+ F3xA0[PllLockTime] - // - PciAddress->Address.Register = 0xA0; - LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader); - - TempVar8_a = (0x00003800 & TempVar_d) >> 11; - F10GetPllValueInTime (&TempVar8_a); - TransAndBusMastLatency += TempVar8_a; - } - - *TransitionLatency = TransAndBusMastLatency; - - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to calculates the frequency in megahertz of the desired P-state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StateNumber The P-State to analyze. - * @param[out] FrequencyInMHz The P-State's frequency in MegaHertz - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always Succeeds. - */ -AGESA_STATUS -F10GetPstateFrequency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 TempValue; - UINT32 CpuDid; - UINT32 CpuFid; - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); - CpuDid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuDid); - CpuFid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuFid); - - switch (CpuDid) { - case 0: - TempValue = 1; - break; - case 1: - TempValue = 2; - break; - case 2: - TempValue = 4; - break; - case 3: - TempValue = 8; - break; - case 4: - TempValue = 16; - break; - default: - // CpuDid is set to an undefined value. This is due to either a misfused CPU, or - // an invalid P-state MSR write. - ASSERT (FALSE); - TempValue = 1; - break; - } - *FrequencyInMHz = (100 * (CpuFid + 0x10) / TempValue); - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to sets the Pstate MSR to each APs base on Pstate Buffer. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] CpuAmdPState Gathered P-state data structure for whole system. - * @param[in] StdHeader Config for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -F10PstateLevelingCoreMsrModify ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 Ignored; - UINT32 k; - UINT32 TempVar_d; - UINT32 TempVar_e; - UINT32 TempVar_f; - UINT32 LogicalSocketCount; - UINT32 LocalPciRegister; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT64 MsrValue; - AGESA_STATUS Status; - PSTATE_LEVELING *PStateBufferPtr; - PSTATE_LEVELING *PStateBufferPtrTmp; - S_CPU_AMD_PSTATE *CpuAmdPstatePtr; - PCI_ADDR PciAddress; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL); - - Ignored = 0; - CpuAmdPstatePtr = (S_CPU_AMD_PSTATE *) CpuAmdPState; - PStateBufferPtrTmp = CpuAmdPstatePtr->PStateLevelingStruc; - PStateBufferPtr = CpuAmdPstatePtr->PStateLevelingStruc; - LogicalSocketCount = CpuAmdPstatePtr->TotalSocketInSystem; - PciAddress.AddressValue = 0; - - // - //Try to find the Pstate buffer specific to this core(socket). - // - IdentifyCore (StdHeader, &Socket, &Module, &Core, &Status); - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, CpuAmdPstatePtr, i, StdHeader); - if (PStateBufferPtrTmp->SocketNumber == Socket) { - break; - } - } - - if (PStateBufferPtr[0].OnlyOneEnabledPState) { - // - //If all processors have only 1 enabled P-state, the following sequence should be performed on all cores: - // - - //1. Write the appropriate CpuFid value resulting from the matched CPU COF to MSRC001_0064[CpuFid]. - LibAmdMsrRead (MSR_PSTATE_0, &MsrValue, StdHeader); - Status = F10GetFrequencyXlatRegInfo (PstateCpuServices, 0, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader); - // Bits 5:0 - ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d; - // Bits 8:6 - ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e; - // Bits 39:32 - ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue; - // Bits 41:40 - ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv; - // Enable the P-State - ((PSTATE_MSR *) &MsrValue)->PsEnable = 1; - LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader); - - //2. Copy MSRC001_0064 to MSRC001_0065. - LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader); - - //3. Write 001b to F3xDC[PstatemaxVal]. - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Status); - PciAddress.Address.Register = CPTC2_REG; - PciAddress.Address.Function = FUNC_3; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - //4. Write 001b to MSRC001_0062[PstateCmd]. - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader); - - //5. Wait for MSRC001_0071[CurCpuFid] = MSRC001_0065[CpuFid]. - do { - LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader); - } while (((COFVID_STS_MSR *) &MsrValue)->CurCpuFid != TempVar_d); - - //6. Write 000b to MSRC001_0062[PstateCmd]. - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader); - - //7. Wait for MSRC001_0071[CurCpuFid] = MSRC001_0064[CpuFid]. - do { - LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader); - } while (((COFVID_STS_MSR *) &MsrValue)->CurCpuFid != TempVar_d); - - //8. Write 0b to MSRC001_0065[PstateEn]. - LibAmdMsrRead (MSR_PSTATE_1, &MsrValue, StdHeader); - ((PSTATE_MSR *) &MsrValue)->PsEnable = 0; - LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader); - - //9. Write 000b to F3xDC[PstateMaxVal] and exit the sequence (no further steps are required). - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - } else { - TempVar_f = MSR_PSTATE_0; - - for (k = 0; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++, TempVar_f++) { - // If pState is not disabled then do update - LibAmdMsrRead (TempVar_f, &MsrValue, StdHeader); - - if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable == 1) { - Status = F10GetFrequencyXlatRegInfo (PstateCpuServices, (UINT8) k, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader); - if (Status != AGESA_ERROR) { - // Bits 5:0 - ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d; - // Bits 8:6 - ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e; - } - - // Bits 39:32 - ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddValue; - // Bits 41:40 - ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddDiv; - // Enable the P-State - ((PSTATE_MSR *) &MsrValue)->PsEnable = 1; - LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader); - } else { - // Disable the P-State - ((PSTATE_MSR *) &MsrValue)->PsEnable = 0; - LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader); - } - } - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to calculates the power in milliWatts of the desired P-state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StateNumber Which P-state to analyze - * @param[out] PowerInMw The Power in milliWatts of that P-State - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F10GetPstatePower ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpuVid; - UINT32 IddValue; - UINT32 IddDiv; - BOOLEAN PviFlag; - UINT32 V_x10000; - UINT32 Power; - PCI_ADDR PciAddress; - UINT32 TempVar_a; - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); - CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid); - IddValue = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddValue); - IddDiv = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddDiv); - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = POWER_CTRL_MISCELLANEOUS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_a, StdHeader); - if ((TempVar_a & 0x00000100) != 0) { - PviFlag = TRUE; - } else { - PviFlag = FALSE; - } - if (PviFlag) { - // Set CpuVid value in case CPU is in PVI mode - if (CpuVid > 0x5D) { - CpuVid = 0x3F; - } else if (CpuVid > 0x3E) { - CpuVid = CpuVid - 0x1F; - } else { - CpuVid = (CpuVid >> 1); - } - - // PVI Encoding - if (CpuVid >= 0x20) { - V_x10000 = 7625L - (125L * (CpuVid - 0x20)); - } else { - V_x10000 = 15500L - (250L * CpuVid); - } - } else { - if (CpuVid >= 0x7C) { - V_x10000 = 0; - } else { - V_x10000 = 15500L - (125L * CpuVid); - } - } - - Power = V_x10000 * IddValue; - - switch (IddDiv) { - case 0: - *PowerInMw = Power / 10L; - break; - case 1: - *PowerInMw = Power / 100L; - break; - case 2: - *PowerInMw = Power / 1000L; - break; - default: - // IddDiv is set to an undefined value. This is due to either a misfused CPU, or - // an invalid P-state MSR write. - ASSERT (FALSE); - *PowerInMw = 0; - break; - } - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get CPU pstate max state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[out] MaxPStateNumber The max hw pstate value on the current socket. - * @param[out] NumberOfBoostStates The number of boosted P-states on the current socket. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F10GetPstateMaxState ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - UINT64 MsrValue; - - NumBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader); - // - // Read PstateMaxVal [6:4] from MSR C001_0061 - // So, we will know the max pstate state in this socket. - // - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader); - *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + (UINT32) (NumBoostStates); - *NumberOfBoostStates = NumBoostStates; - - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get CPU pstate register information. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] PState Input Pstate number for query. - * @param[out] PStateEnabled Boolean flag return pstate enable. - * @param[in,out] IddVal Pstate current value. - * @param[in,out] IddDiv Pstate current divisor. - * @param[out] SwPstateNumber Software P-state number. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F10GetPstateRegisterInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - UINT64 LocalMsrRegister; - - ASSERT (PState < NM_PS_REG); - - // Check if CPB is supported. if yes, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates]. - NumBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader); - - // Read PSTATE MSRs - LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrRegister, StdHeader); - - if (PState < NumBoostStates) { - *SwPstateNumber = 0; - *PStateEnabled = FALSE; - } else { - *SwPstateNumber = PState - NumBoostStates; - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - // PState enable = bit 63 - *PStateEnabled = TRUE; - } else { - *PStateEnabled = FALSE; - } - } - - // Bits 39:32 (high 32 bits [7:0]) - *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddValue; - // Bits 41:40 (high 32 bits [9:8]) - *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddDiv; - - return (AGESA_SUCCESS); -} - -CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices = -{ - 0, - (PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue, - F10IsPstatePsdDependent, - F10SetTscFreqSel, - F10GetPstateTransLatency, - F10GetPstateFrequency, - F10PstateLevelingCoreMsrModify, - F10GetPstatePower, - F10GetPstateMaxState, - F10GetPstateRegisterInfo -}; - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - - -/** - *--------------------------------------------------------------------------------------- - * - * F10GetPowerStepValueInTime - * - * Description: - * Convert power step value in time - * - * Parameters: - * @param[out] *PowerStepPtr - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -STATIC -F10GetPowerStepValueInTime ( - IN OUT UINT32 *PowerStepPtr - ) -{ - UINT32 TempVar_a; - - TempVar_a = *PowerStepPtr; - - if (TempVar_a < 0x4) { - *PowerStepPtr = 400 - (TempVar_a * 100); - } else if (TempVar_a < 0x9) { - *PowerStepPtr = 130 - (TempVar_a * 10); - } else { - *PowerStepPtr = 90 - (TempVar_a * 5); - } -} - - -/** - *--------------------------------------------------------------------------------------- - * - * F10GetPllValueInTime - * - * Description: - * Convert PLL Value in time - * - * Parameters: - * @param[out] *PllLockTimePtr - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -STATIC -F10GetPllValueInTime ( - IN OUT UINT32 *PllLockTimePtr - ) -{ - if (*PllLockTimePtr < 4) { - *PllLockTimePtr = *PllLockTimePtr + 1; - } else if (*PllLockTimePtr == 4) { - *PllLockTimePtr = 8; - } else if (*PllLockTimePtr == 5) { - *PllLockTimePtr = 16; - } else - *PllLockTimePtr = 0; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will return the CpuFid and CpuDid in MHz, using the formula - * described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0 - * - * @param[in] PstateCpuServices The current Family Specific Services. - * @param[in] PStateNumber P-state number to check. - * @param[in] Frequency Leveled target frequency for PStateNumber. - * @param[out] *CpuFidPtr New leveled FID. - * @param[out] *CpuDidPtr1 New leveled DID info 1. - * @param[out] *CpuDidPtr2 New leveled DID info 2. - * @param[in] *StdHeader Header for library and services. - * - * @retval AGESA_WARNING This P-State does not need to be modified. - * @retval AGESA_SUCCESS This P-State must be modified to be level. - */ -AGESA_STATUS -STATIC -F10GetFrequencyXlatRegInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 PStateNumber, - IN UINT32 Frequency, - OUT UINT32 *CpuFidPtr, - OUT UINT32 *CpuDidPtr1, - OUT UINT32 *CpuDidPtr2, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 j; - AGESA_STATUS Status; - UINT32 FrequencyInMHz; - - FrequencyInMHz = 0; - *CpuDidPtr2 = 0xFFFF; - - Status = AGESA_SUCCESS; - - PstateCpuServices->GetPstateFrequency (PstateCpuServices, PStateNumber, &FrequencyInMHz, StdHeader); - if (FrequencyInMHz == Frequency) { - Status |= AGESA_WARNING; - } - - // CPU Frequency = 100 MHz * (CpuFid + 10h) / (2^CpuDid) - // In this for loop i = 2^CpuDid - - - for (i = 1; i < 17; (i += i)) { - for (j = 0; j < 64; j++) { - if (Frequency == ((100 * (j + 0x10)) / i )) { - *CpuFidPtr = j; - if (i == 1) { - *CpuDidPtr1 = 0; - } else if (i == 2) { - *CpuDidPtr1 = 1; - } else if (i == 4) { - *CpuDidPtr1 = 2; - } else if (i == 8) { - *CpuDidPtr1 = 3; - } else if (i == 16) { - *CpuDidPtr1 = 4; - } else { - *CpuFidPtr = 0xFFFF; - *CpuDidPtr1 = 0xFFFF; - } - // Success - return Status; - } - } - } - - // Error Condition - *CpuFidPtr = 0x00FF; - *CpuDidPtr1 = 0x00FF; - *CpuDidPtr2 = 0x00FF; - - return AGESA_ERROR; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c deleted file mode 100644 index a983f089c8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c +++ /dev/null @@ -1,124 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 thermal initialization - * - * Performs processor thermal initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF10PowerMgmt.h" -#include "cpuF10SoftwareThermal.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Main entry point for initializing the Thermal Control - * safety net feature. - * - * This must be run by all Family 10h core 0s in the system. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service parameters. - * @param[in] StdHeader Config handle for library and services. - */ -VOID -F10PmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Core; - UINT32 Module; - UINT32 LocalPciRegister; - UINT32 Socket; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - ASSERT (Core == 0); - - if (GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) { - // Enable HTC - PciAddress.Address.Register = HTC_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((HTC_REGISTER *) &LocalPciRegister)->HtcSlewSel = 0; - ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h deleted file mode 100644 index 9dcc44e94c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 thermal initialization related functions and structures - * - * Performs processor thermal initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F10_SOFTWARE_THERMAL_H_ -#define _CPU_F10_SOFTWARE_THERMAL_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F10PmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F10_SOFTWARE_THERMAL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.c deleted file mode 100644 index ed2ff50186..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.c +++ /dev/null @@ -1,1176 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 specific utility functions. - * - * Provides numerous utility functions specific to family 10h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F10 - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuF10PowerMgmt.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuF10Utilities.h" -#include "cpuPostInit.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -// Register encodings for F3xD8[VSRampTime/VSSlamTime] -CONST UINT32 ROMDATA VSSlamTime[8] = -{ - 10, // 000b: 10us - 20, // 001b: 20us - 30, // 010b: 30us - 40, // 011b: 40us - 60, // 100b: 60us - 100, // 101b: 100us - 200, // 110b: 200us - 500 // 111b: 500us -}; - -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs the necessary steps for the 'Software Initiated CPU - * Voltage Transitions.' - * - * @param[in] VidCode VID code to transition to - * @param[in] StdHeader Header for library and services - * - */ -VOID -F10PmSwVoltageTransition ( - IN UINT32 VidCode, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - PCI_ADDR PciAddress; - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PW_CTL_MISC_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->SlamVidMode == 1) { - LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader); - ((COFVID_CTRL_MSR *) &LocalMsrRegister)->CpuVid = VidCode; - LibAmdMsrWrite (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader); - F10WaitOutVoltageTransition (TRUE, StdHeader); - } else - return; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs the necessary steps for the 'Software Initiated NB - * Voltage Transitions.' - * - * This can only be run by a local core 0. - * - * @param[in] VidCode VID code to transition to - * @param[in] SlamMode Whether voltage is to be slammed, or stepped - * @param[in] StdHeader Header for library and services - * - */ -VOID -F10PmSwVoltageTransitionServerNb ( - IN UINT32 VidCode, - IN BOOLEAN SlamMode, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Core; - UINT32 NbVidStatus; - UINT32 Socket; - UINT32 IgnoredModule; - UINT32 IgnoredCore; - UINT32 CoreNum; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - SW_VOLT_TRANS_NB RemoteInput; - - RemoteInput.VidCode = VidCode; - RemoteInput.SlamMode = SlamMode; - TaskPtr.FuncAddress.PfApTaskIO = F10SwVoltageTransitionServerNbCore; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (SW_VOLT_TRANS_NB); - TaskPtr.DataTransfer.DataPtr = &RemoteInput; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - - IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts); - GetActiveCoresInCurrentSocket (&CoreNum, StdHeader); - - do { - NbVidStatus = TaskPtr.FuncAddress.PfApTaskIO (&RemoteInput, StdHeader); - for (Core = 1; Core < (UINT8) CoreNum; Core++) { - NbVidStatus |= ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader); - } - F10WaitOutVoltageTransition (SlamMode, StdHeader); - } while (NbVidStatus != 0); - return; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns current VsSlamTime in microseconds. - * - * @param[out] VsTimeUsecs Provides the wait time needed for a Slam Voltage transition. - * @param[in] SlamMode Whether voltage is to be slammed, or stepped - * @param[in] StdHeader Header for library and services - * - */ -VOID -F10GetCurrentVsTimeInUsecs ( - OUT UINT32 *VsTimeUsecs, - IN BOOLEAN SlamMode, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 RegisterEncoding; - UINT32 LocalPciRegister; - CONST UINT16 SlamTimes[8] = {10, 20, 30, 40, 60, 100, 200, 500}; - PCI_ADDR PciAddress; - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC1_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - if (SlamMode) { - RegisterEncoding = (UINT8) ((CLK_PWR_TIMING_CTRL1_REGISTER *) &LocalPciRegister)->VSSlamTime; - } else { - RegisterEncoding = (UINT8) ((CLK_PWR_TIMING_CTRL1_REGISTER *) &LocalPciRegister)->VSRampTime; - } - - *VsTimeUsecs = (UINT32) SlamTimes[RegisterEncoding]; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Spins until VsSlamTime microseconds have expired. - * - * @param[in] SlamMode Whether voltage is to be slammed, or stepped - * @param[in] StdHeader Header for library and services - * - */ -VOID -F10WaitOutVoltageTransition ( - IN BOOLEAN SlamMode, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 VsTimeUsecs; - - F10GetCurrentVsTimeInUsecs (&VsTimeUsecs, SlamMode, StdHeader); - WaitMicroseconds (VsTimeUsecs, StdHeader); - return; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Code required to be run on every local core in order to perform - * the steps necessary for 'Software Initiated NB Voltage - * Transitions.' - * - * @param[out] InputData Family specific data needed to perform a Voltage transition. - * @param[in] StdHeader Header for library and services. - * - * @retval zero All Voltage Transitions are completed. - * @retval one There are Voltage transitions remaining to reach target. - * - */ -UINT32 -F10SwVoltageTransitionServerNbCore ( - IN VOID *InputData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 VidCode; - UINT64 LocalMsrRegister; - - if (((SW_VOLT_TRANS_NB *) InputData)->SlamMode) { - VidCode = ((SW_VOLT_TRANS_NB *) InputData)->VidCode; - } else { - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - VidCode = (UINT32) (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbVid); - if (VidCode > ((SW_VOLT_TRANS_NB *) InputData)->VidCode) { - --VidCode; - } else if (VidCode < ((SW_VOLT_TRANS_NB *) InputData)->VidCode) { - ++VidCode; - } - } - LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader); - ((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbVid = VidCode; - LibAmdMsrWrite (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader); - - if (VidCode == ((SW_VOLT_TRANS_NB *) InputData)->VidCode) { - return 0; - } else { - return 1; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Calculate and reprogram F3xD8[VSSlamTime] based on the algorithm in the BKDG. - * - * This function determines the largest voltage step that the core will have - * to make, calculates how much time it will take for the voltage to stabilize, - * and programs the necessary encoded value for the amount of time discovered. - * - * @param[in] PciAddress Segment/bus/device of a module on the socket - * to program. - * @param[in] CpuEarlyParams Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F10ProgramVSSlamTimeOnSocket ( - IN PCI_ADDR *PciAddress, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NbVid; - UINT8 P0VidCode; - UINT8 PminVidCode; - UINT32 AndMask; - UINT32 MsrAddr; - UINT32 OrMask; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - BOOLEAN IsPviMode; - PCI_ADDR LocalPciAddress; - - // Get F3xA0[PviMode] - LocalPciAddress.AddressValue = PciAddress->AddressValue; - LocalPciAddress.Address.Function = FUNC_3; - LocalPciAddress.Address.Register = PW_CTL_MISC_REG; - LibAmdPciRead (AccessWidth32, LocalPciAddress, &LocalPciRegister, StdHeader); - if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 1) { - IsPviMode = TRUE; - } else { - IsPviMode = FALSE; - } - - // Get P0's voltage - LibAmdMsrRead (PS_REG_BASE, &LocalMsrRegister, StdHeader); - P0VidCode = (UINT8) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid); - - // If SVI, we only care about CPU VID. - // If PVI, determine the higher voltage between NB and CPU - if (IsPviMode) { - NbVid = (UINT8) (((PSTATE_MSR *) &LocalMsrRegister)->NbVid); - if (P0VidCode > NbVid) { - P0VidCode = NbVid; - } - } - - // Get Pmin's index - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal) + PS_REG_BASE); - - // Get Pmin's VID - LibAmdMsrRead (MsrAddr, &LocalMsrRegister, StdHeader); - PminVidCode = (UINT8) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid); - - // If SVI, we only care about CPU VID. - // If PVI, determine the higher voltage b/t NB and CPU - if (IsPviMode) { - NbVid = (UINT8) (((PSTATE_MSR *) &LocalMsrRegister)->NbVid); - if (PminVidCode > NbVid) { - PminVidCode = NbVid; - } - } - - // Program F3xD8[VSSlamTime] - LocalPciAddress.Address.Register = CPTC1_REG; - AndMask = 0xFFFFFFFF; - ((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->VSSlamTime = 0; - OrMask = 0x00000000; - ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->VSSlamTime = - F10GetSlamTimeEncoding (P0VidCode, PminVidCode, CpuEarlyParams, VSSlamTime, StdHeader); - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&LocalPciAddress, AndMask, OrMask, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the encoded voltage stabilization slam time for the executing - * family 10h core. - * - * This function looks up the appropriate encoded value for the desired - * VID codes. - * - * @param[in] HighVoltageVid VID code of the higher voltage. - * @param[in] LowVoltageVid VID code of the lower voltage. - * @param[in] CpuEarlyParams Service parameters - * @param[in] SlamTimeTable Look-up table of slam times. - * @param[in] StdHeader Config handle for library and services. - * - * @retval Encoded register value. - * - */ -UINT32 -F10GetSlamTimeEncoding ( - IN UINT8 HighVoltageVid, - IN UINT8 LowVoltageVid, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN CONST UINT32 *SlamTimeTable, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 SlamTime; - UINT32 EncodedSlamTime; - UINT32 VoltageDifference; - - ASSERT (LowVoltageVid >= HighVoltageVid); - ASSERT (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate != 0); - - // Calculate Slam Time - // VSSlamTime = 0.4us/mV (or 0.2us/mV) * Vhigh - Vlow - // In our case, we will scale the values by 100 to avoid - // decimals. - - VoltageDifference = (UINT32) ((LowVoltageVid - HighVoltageVid) * 12500); - SlamTime = (VoltageDifference / CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate) + CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].AdditionalDelay; - if (VoltageDifference % CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate) { - SlamTime++; - } - - // Now round up to nearest register setting - for (EncodedSlamTime = 0; EncodedSlamTime < 8; EncodedSlamTime++) { - if (SlamTime <= SlamTimeTable[EncodedSlamTime]) { - break; - } - } - - if (EncodedSlamTime > 7) { - // The VRMs are too slow for this CPU. Set to max, and fire an error trap. - IDS_ERROR_TRAP; - EncodedSlamTime = 7; - } - - return (EncodedSlamTime); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Disables the desired P-state. - * - * @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The P-State to disable. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F10DisablePstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ((PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 0; - LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Transitions the executing core to the desired P-state. - * - * @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The new P-State to make effective. - * @param[in] WaitForTransition True if the caller wants the transition completed upon return. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always Succeeds - */ -AGESA_STATUS -F10TransitionPstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN BOOLEAN WaitForTransition, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal >= StateNumber); - LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) StateNumber; - LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - if (WaitForTransition) { - do { - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) StateNumber); - } - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the rate at which the executing core's time stamp counter is - * incrementing. - * - * @CpuServiceMethod{::F_CPU_GET_TSC_RATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FrequencyInMHz TSC actual frequency. - * @param[in] StdHeader Header for library and services. - * - * @return The most severe status of all called services - */ -AGESA_STATUS -F10GetTscRate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - LibAmdMsrRead (MSR_HWCR, &LocalMsrRegister, StdHeader); - if ((LocalMsrRegister & 0x01000000) != 0) { - return (FamilyServices->GetPstateFrequency (FamilyServices, F10GetNumberOfBoostedPstatesOnCore (StdHeader), FrequencyInMHz, StdHeader)); - } else { - return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader)); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the NB clock on the desired node. - * - * @CpuServiceMethod{::F_CPU_GET_NB_FREQ}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FrequencyInMHz Northbridge clock frequency in MHz. - * @param[in] StdHeader Header for library and services. - * - * @return AGESA_SUCCESS FrequencyInMHz is valid. - */ -AGESA_STATUS -F10GetCurrentNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbFid; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - PCI_ADDR PciAddress; - AGESA_STATUS ReturnCode; - - ReturnCode = AGESA_ERROR; - - if (OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader)) { - ReturnCode = AGESA_SUCCESS; - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC0_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid; - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 0) { - *FrequencyInMHz = ((NbFid + 4) * 200); - } else { - *FrequencyInMHz = (((NbFid + 4) * 200) / 2); - } - } - return ReturnCode; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Initially launches the desired core to run from the reset vector. - * - * @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] SocketNum The Processor on which the core is to be launched - * @param[in] ModuleNum The Module in that processor containing that core - * @param[in] CoreNum The Core to launch - * @param[in] PrimaryCoreNum The id of the module's primary core. - * @param[in] StdHeader Header for library and services - * - * @retval TRUE The core was launched - * @retval FALSE The core was previously launched - */ -BOOLEAN -F10LaunchApCore ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 SocketNum, - IN UINT32 ModuleNum, - IN UINT32 CoreNum, - IN UINT32 PrimaryCoreNum, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NodeRelativeCoreNum; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - BOOLEAN LaunchFlag; - AGESA_STATUS Ignored; - - // Code Start - LaunchFlag = FALSE; - NodeRelativeCoreNum = CoreNum - PrimaryCoreNum; - GetPciAddress (StdHeader, SocketNum, ModuleNum, &PciAddress, &Ignored); - PciAddress.Address.Function = FUNC_0; - - switch (NodeRelativeCoreNum) { - case 0: - PciAddress.Address.Register = HT_INIT_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & HT_INIT_CTRL_REQ_DIS) != 0) { - LocalPciRegister &= ~HT_INIT_CTRL_REQ_DIS; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 1: - PciAddress.Address.Register = HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) { - LocalPciRegister |= HT_TRANS_CTRL_CPU1_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 2: - PciAddress.Address.Register = ECS_HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - if ((LocalPciRegister & ECS_HT_TRANS_CTRL_CPU2_EN) == 0) { - LocalPciRegister |= ECS_HT_TRANS_CTRL_CPU2_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, - StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 3: - PciAddress.Address.Register = ECS_HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & ECS_HT_TRANS_CTRL_CPU3_EN) == 0) { - LocalPciRegister |= ECS_HT_TRANS_CTRL_CPU3_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 4: - PciAddress.Address.Register = ECS_HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & ECS_HT_TRANS_CTRL_CPU4_EN) == 0) { - LocalPciRegister |= ECS_HT_TRANS_CTRL_CPU4_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 5: - PciAddress.Address.Register = ECS_HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & ECS_HT_TRANS_CTRL_CPU5_EN) == 0) { - LocalPciRegister |= ECS_HT_TRANS_CTRL_CPU5_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - - default: - break; - } - - return (LaunchFlag); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get CPU Specific Platform Type Info. - * - * @CpuServiceMethod{::F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO}. - * - * This function returns Returns the platform features. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] Features The Features supported by this platform. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F10GetPlatformTypeSpecificInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PLATFORM_FEATS *Features, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Provide the features of the next HT link. - * - * @CpuServiceMethod{::F_GET_NEXT_HT_LINK_FEATURES}. - * - * This method is different than the HT Phy Features method, because for the phy registers - * sublink 1 matches and should be programmed if the link is ganged but for PCI config - * registers sublink 1 is reserved if the link is ganged. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] Link Initially zero, each call returns the link number; - * caller passes it back unmodified each call. - * @param[in,out] LinkBase Initially the PCI bus, device, function=0, offset=0; - * Each call returns the HT Host Capability function and offset; - * Caller may use it to access registers, but must @b not modify it; - * Each new call passes the previous value as input. - * @param[out] HtHostFeats The link's features. - * @param[in] StdHeader Standard Head Pointer - * - * @retval TRUE Valid link and features found. - * @retval FALSE No more links. - */ -BOOLEAN -F10GetNextHtLinkFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT UINTN *Link, - IN OUT PCI_ADDR *LinkBase, - OUT HT_HOST_FEATS *HtHostFeats, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - UINT32 RegValue; - UINT32 ExtendedFreq; - UINTN LinkOffset; - BOOLEAN Result; - - ASSERT (FamilySpecificServices != NULL); - - // No features present unless link is good and connected. - HtHostFeats->HtHostValue = 0; - - Result = TRUE; - - // Find next link. - if (LinkBase->Address.Register == 0) { - // Beginning iteration now. - LinkBase->Address.Register = HT_CAPABILITIES_POINTER; - LibAmdPciReadBits (*LinkBase, 7, 0, &RegValue, StdHeader); - } else { - // Get next link offset. - LibAmdPciReadBits (*LinkBase, 15, 8, &RegValue, StdHeader); - } - if (RegValue == 0) { - // Are we at the end? Check if we can move to another function. - if (LinkBase->Address.Function == 0) { - LinkBase->Address.Function = 4; - LinkBase->Address.Register = HT_CAPABILITIES_POINTER; - LibAmdPciReadBits (*LinkBase, 7, 0, &RegValue, StdHeader); - } - } - - if (RegValue != 0) { - // Not at end, process the found link. - LinkBase->Address.Register = RegValue; - // Compute link number - *Link = (((LinkBase->Address.Function == 4) ? 4 : 0) + ((LinkBase->Address.Register - 0x80) >> 5)); - - // Handle pending link power off, check End of Chain, Xmit Off. - PciAddress = *LinkBase; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET; - LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader); - if (RegValue == 0) { - // Check coherency (HTHOST_LINK_TYPE_REG = 0x18) - PciAddress = *LinkBase; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET; - LibAmdPciReadBits (PciAddress, 4, 0, &RegValue, StdHeader); - if (RegValue == 3) { - HtHostFeats->HtHostFeatures.Coherent = 1; - } else if (RegValue == 7) { - HtHostFeats->HtHostFeatures.NonCoherent = 1; - } - } - - // If link was not connected, don't check other attributes, make sure - // to return zero, no match. - if ((HtHostFeats->HtHostFeatures.Coherent == 1) || (HtHostFeats->HtHostFeatures.NonCoherent == 1)) { - // Check gen3 - PciAddress = *LinkBase; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ; - LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader); - PciAddress = *LinkBase; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8)); - if (RegValue > 6) { - HtHostFeats->HtHostFeatures.Ht3 = 1; - } else { - HtHostFeats->HtHostFeatures.Ht1 = 1; - } - // Check ganged. Must check the bit for sublink 0. - LinkOffset = (*Link > 3) ? ((*Link - 4) * 4) : (*Link * 4); - PciAddress = *LinkBase; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = ((UINT32)LinkOffset + 0x170); - LibAmdPciReadBits (PciAddress, 0, 0, &RegValue, StdHeader); - if (RegValue == 0) { - HtHostFeats->HtHostFeatures.UnGanged = 1; - } else { - if (*Link < 4) { - HtHostFeats->HtHostFeatures.Ganged = 1; - } else { - // If this is a sublink 1 but it will be ganged, clear all features. - HtHostFeats->HtHostValue = 0; - } - } - } - } else { - // End of links. - Result = FALSE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Checks to see if the HT phy register table entry should be applied - * - * @CpuServiceMethod{::F_NEXT_LINK_HAS_HTFPY_FEATS}. - * - * Find the next link which matches, if any. - * This method will match for sublink 1 if the link is ganged and sublink 0 matches. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] HtHostCapability Initially the PCI bus, device, function=0, offset=0; - * Each call returns the HT Host Capability function and offset; - * Caller may use it to access registers, but must @b not modify it; - * Each new call passes the previous value as input. - * @param[in,out] Link Initially zero, each call returns the link number; caller passes it back unmodified each call. - * @param[in] HtPhyLinkType Link type field from a register table entry to compare against - * @param[out] MatchedSublink1 TRUE: It is actually just sublink 1 that matches, FALSE: any other condition. - * @param[out] Frequency0 The frequency of sublink0 (200 MHz if not connected). - * @param[out] Frequency1 The frequency of sublink1 (200 MHz if not connected). - * @param[in] StdHeader Standard Head Pointer - * - * @retval TRUE Link matches - * @retval FALSE No more links - * - */ -BOOLEAN -F10NextLinkHasHtPhyFeats ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PCI_ADDR *HtHostCapability, - IN OUT UINT32 *Link, - IN HT_PHY_LINK_FEATS *HtPhyLinkType, - OUT BOOLEAN *MatchedSublink1, - OUT HT_FREQUENCIES *Frequency0, - OUT HT_FREQUENCIES *Frequency1, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RegValue; - UINT32 ExtendedFreq; - UINT32 InternalLinks; - UINT32 Width; - PCI_ADDR PciAddress; - PCI_ADDR SubLink1Address; - HT_PHY_LINK_FEATS LinkType; - BOOLEAN IsReallyCheckingBoth; - BOOLEAN IsFound; - BOOLEAN Result; - - ASSERT (*Link < 4); - ASSERT (HtPhyLinkType != NULL); - // error checks: No unknown link type bits set and not a "match none" - ASSERT ((HtPhyLinkType->HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL | HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) == 0); - ASSERT (HtPhyLinkType->HtPhyLinkValue != 0); - - Result = FALSE; - IsFound = FALSE; - while (!IsFound) { - *Frequency0 = 0; - *Frequency1 = 0; - IsReallyCheckingBoth = FALSE; - *MatchedSublink1 = FALSE; - LinkType.HtPhyLinkValue = 0; - - // Find next link. - PciAddress = *HtHostCapability; - if (PciAddress.Address.Register == 0) { - // Beginning iteration now. - PciAddress.Address.Register = HT_CAPABILITIES_POINTER; - LibAmdPciReadBits (PciAddress, 7, 0, &RegValue, StdHeader); - } else { - // Get next link offset. - LibAmdPciReadBits (PciAddress, 15, 8, &RegValue, StdHeader); - } - if (RegValue != 0) { - HtHostCapability->Address.Register = RegValue; - // Compute link number of this sublink pair (so we don't need to account for function). - *Link = ((HtHostCapability->Address.Register - 0x80) >> 5); - - // Set the link indicators. This assumes each sublink set is contiguous, that is, links 3, 2, 1, 0 and 7, 6, 5, 4. - LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL0_LINK0 << *Link); - LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL1_LINK4 << *Link); - - // Read IntLnkRoute from the Link Initialization Status register. - // (Note that this register field is not reserved prior to rev D, but should be zero.) - PciAddress = *HtHostCapability; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x1A0; - LibAmdPciReadBits (PciAddress, 23, 16, &InternalLinks, StdHeader); - - // if ganged, don't read sublink 1, but use sublink 0 to check. - SubLink1Address = *HtHostCapability; - - // Check ganged. Since we got called for sublink 0, sublink 1 is implemented also, - // but only access it if it is also unganged. - PciAddress = *HtHostCapability; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = ((*Link * 4) + 0x170); - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - RegValue = (RegValue & 0x01); - if (RegValue == 0) { - // Then really read sublink1, rather than using sublink0 - SubLink1Address.Address.Function = 4; - IsReallyCheckingBoth = TRUE; - } - - // Checks for Sublink 0 - - // Handle pending link power off, check End of Chain, Xmit Off. - PciAddress = *HtHostCapability; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET; - LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader); - if (RegValue == 0) { - // Check coherency (HTHOST_LINK_TYPE_REG = 0x18) - PciAddress = *HtHostCapability; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - if ((RegValue & 0x1F) == 3) { - LinkType.HtPhyLinkFeatures.HtPhySL0Coh = 1; - } else if ((RegValue & 0x1F) == 7) { - LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh = 1; - } - } - - // If link was not connected, don't check other attributes, make sure - // to return zero, no match. (Phy may be powered off.) - if ((LinkType.HtPhyLinkFeatures.HtPhySL0Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh)) { - // Check gen3 - PciAddress = *HtHostCapability; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ; - LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader); - PciAddress = *HtHostCapability; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8)); - *Frequency0 = RegValue; - if (RegValue > 6) { - LinkType.HtPhyLinkFeatures.HtPhySL0Ht3 = 1; - } else { - LinkType.HtPhyLinkFeatures.HtPhySL0Ht1 = 1; - } - // Check internal / external - if ((InternalLinks & (1 << *Link)) == 0) { - // External - LinkType.HtPhyLinkFeatures.HtPhySL0External = 1; - } else { - // Internal - LinkType.HtPhyLinkFeatures.HtPhySL0Internal = 1; - } - } else { - LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL0_ALL); - } - - // Checks for Sublink 1 - // Handle pending link power off, check End of Chain, Xmit Off. - PciAddress = SubLink1Address; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET; - LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader); - LibAmdPciReadBits (PciAddress, 31, 24, &Width, StdHeader); - if ((RegValue == 0) && (IsReallyCheckingBoth || (Width == 0x11))) { - // Check coherency (HTHOST_LINK_TYPE_REG = 0x18) - PciAddress = SubLink1Address; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - if ((RegValue & 0x1F) == 3) { - LinkType.HtPhyLinkFeatures.HtPhySL1Coh = 1; - } else if ((RegValue & 0x1F) == 7) { - LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh = 1; - } - } - - if ((LinkType.HtPhyLinkFeatures.HtPhySL1Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh)) { - // Check gen3 - PciAddress = SubLink1Address; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ; - LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader); - PciAddress = SubLink1Address; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8)); - *Frequency1 = RegValue; - if (RegValue > 6) { - LinkType.HtPhyLinkFeatures.HtPhySL1Ht3 = 1; - } else { - LinkType.HtPhyLinkFeatures.HtPhySL1Ht1 = 1; - } - // Check internal / external. Note that we do really check sublink 1 regardless of ganging. - if ((InternalLinks & (1 << (*Link + 4))) == 0) { - // External - LinkType.HtPhyLinkFeatures.HtPhySL1External = 1; - } else { - // Internal - LinkType.HtPhyLinkFeatures.HtPhySL1Internal = 1; - } - } else { - LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL1_ALL); - } - - // Determine if the link matches the entry criteria. - // For Deemphasis checking, indicate whether it was actually sublink 1 that matched. - // If the link is ganged or only sublink 0 matched, or the link features didn't match, this is false. - if (((HtPhyLinkType->HtPhyLinkValue & HTPHY_LINKTYPE_SL0_AND) == 0) && - ((HtPhyLinkType->HtPhyLinkValue & HTPHY_LINKTYPE_SL1_AND) == 0)) { - // Match if any feature matches (OR) - Result = (BOOLEAN) ((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) != 0); - } else { - // Match if all features match (AND) - Result = (BOOLEAN) ((HtPhyLinkType->HtPhyLinkValue & ~(HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) == - (LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue)); - } - if (Result) { - if (IsReallyCheckingBoth && - (((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) & (HTPHY_LINKTYPE_SL1_ALL)) != 0)) { - *MatchedSublink1 = TRUE; - } - IsFound = TRUE; - } else { - // Go to next link - } - } else { - // No more links - IsFound = TRUE; - } - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Applies an HT Phy read-modify-write based on an HT Phy register table entry. - * - * @CpuServiceMethod{::F_SET_HT_PHY_REGISTER}. - * - * This function performs the necessary sequence of PCI reads, writes, and waits - * necessary to program an HT Phy register. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] HtPhyEntry HT Phy register table entry to apply - * @param[in] CapabilitySet The link's HT Host base address. - * @param[in] Link Zero based, node, link number (not package link). - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -F10SetHtPhyRegister ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN HT_PHY_TYPE_ENTRY_DATA *HtPhyEntry, - IN PCI_ADDR CapabilitySet, - IN UINT32 Link, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Temp; - UINT32 PhyReg; - PCI_ADDR PhyBase; - - // Determine the PCI config address of the HT Phy portal - PhyBase = CapabilitySet; - PhyBase.Address.Function = FUNC_4; - PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180); - - LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader); - - // Handle direct map registers if needed - PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK); - if (HtPhyEntry->Address > 0x1FF) { - PhyReg |= HTPHY_DIRECT_MAP; - } - - PhyReg |= (HtPhyEntry->Address); - // Ask the portal to read the HT Phy Register contents - LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader); - do - { - LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); - } while (!(Temp & HTPHY_IS_COMPLETE_MASK)); - - // Get the current register contents and do the update requested by the table - PhyBase.AddressValue += 4; - LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); - Temp &= ~(HtPhyEntry->Mask); - Temp |= (HtPhyEntry->Data); - LibAmdPciWrite (AccessWidth32, PhyBase, &Temp, StdHeader); - - PhyBase.AddressValue -= 4; - // Ask the portal to write our updated value to the HT Phy - PhyReg |= HTPHY_WRITE_CMD; - LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader); - do - { - LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); - } while (!(Temp & HTPHY_IS_COMPLETE_MASK)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the number of core performance boost states. - * - * This function will return the number of boosted states present on - * the executing core. This is useful when trying to determine the - * "software P0" state. - * - * @param[in] StdHeader Config handle for library and services - * - * @return The number of boosted core P-states. - * - */ -UINT8 -F10GetNumberOfBoostedPstatesOnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - PCI_ADDR PciAddress; - UINT32 LocalPciRegister; - CPUID_DATA CpuidData; - - LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader); - if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) { - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CPB_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - NumBoostStates = (UINT8) (((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates); - } else { - NumBoostStates = 0; - } - - return NumBoostStates; -} - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.h deleted file mode 100644 index 73d9aa6b59..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Utilities.h +++ /dev/null @@ -1,206 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 specific utility functions. - * - * Provides numerous utility functions specific to family 10h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44702 $ @e \$Date: 2011-01-04 15:54:00 -0700 (Tue, 04 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F10_UTILITES_H_ -#define _CPU_F10_UTILITES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/// The structure for Software Initiated NB Voltage Transitions -typedef struct { - UINT32 VidCode; ///< VID code to transition to - BOOLEAN SlamMode; ///< Whether voltage is to be slammed, or stepped -} SW_VOLT_TRANS_NB; - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F10PmSwVoltageTransition ( - IN UINT32 VidCode, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F10PmSwVoltageTransitionServerNb ( - IN UINT32 VidCode, - IN BOOLEAN SlamMode, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -F10SwVoltageTransitionServerNbCore ( - IN VOID *InputData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F10WaitOutVoltageTransition ( - IN BOOLEAN SlamMode, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F10GetCurrentVsTimeInUsecs ( - OUT UINT32 *VsTimeUsecs, - IN BOOLEAN SlamMode, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F10ProgramVSSlamTimeOnSocket ( - IN PCI_ADDR *PciAddress, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -F10GetSlamTimeEncoding ( - IN UINT8 HighVoltageVid, - IN UINT8 LowVoltageVid, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN CONST UINT32 *SlamTimeTable, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F10DisablePstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F10TransitionPstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN BOOLEAN WaitForTransition, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F10GetTscRate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F10GetCurrentNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F10LaunchApCore ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 SocketNum, - IN UINT32 ModuleNum, - IN UINT32 CoreNum, - IN UINT32 PrimaryCoreNum, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F10GetPlatformTypeSpecificInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PLATFORM_FEATS *Features, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F10GetNextHtLinkFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT UINTN *Link, - IN OUT PCI_ADDR *LinkBase, - OUT HT_HOST_FEATS *HtHostFeats, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F10NextLinkHasHtPhyFeats ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PCI_ADDR *HtHostCapability, - IN OUT UINT32 *Link, - IN HT_PHY_LINK_FEATS *HtPhyLinkType, - OUT BOOLEAN *MatchedSublink1, - OUT HT_FREQUENCIES *Frequency0, - OUT HT_FREQUENCIES *Frequency1, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F10SetHtPhyRegister ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN HT_PHY_TYPE_ENTRY_DATA *HtPhyEntry, - IN PCI_ADDR CapabilitySet, - IN UINT32 Link, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -F10GetNumberOfBoostedPstatesOnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F10_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c deleted file mode 100644 index 393d3bfc97..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +++ /dev/null @@ -1,128 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 WHEA initial Data - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuLateInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -GetF10WheaInitData ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **F10WheaInitDataPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AMD_HEST_BANK_INIT_DATA F10HestBankInitData[] = { - {0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403}, - {0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407}, - {0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B}, - {0xFFFFFFFF,0xFFFFFFFF,0x40C,0x40D,0x40E,0x40F}, - {0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413}, - {0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417}, -}; - -AMD_WHEA_INIT_DATA F10WheaInitData = { - 0x000000000, // AmdGlobCapInitDataLsd - 0x000000000, // AmdGlobCapInitDataMsd - 0x00000003F, // AmdGlobCtrlInitDataLsd - 0x000000000, // AmdGlobCtrlInitDataMsd - 0x00, // AmdMcbClrStatusOnInit - 0x02, // AmdMcbStatusDataFormat - 0x00, // AmdMcbConfWriteEn - (sizeof (F10HestBankInitData) / sizeof (F10HestBankInitData[0])), // HestBankNum - &F10HestBankInitData[0] // Pointer to Initial data of HEST Bank -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the family specific WHEA table properties. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] F10WheaInitDataPtr Points to the family 10h WHEA properties. - * @param[out] NumberOfElements Will be one to indicate one structure. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF10WheaInitData ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **F10WheaInitDataPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = 1; - *F10WheaInitDataPtr = &F10WheaInitData; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c deleted file mode 100644 index b955c1f792..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c +++ /dev/null @@ -1,184 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_10 Family Specific Workaround table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x10 - * @e \$Revision: 57155 $ @e \$Date: 2011-07-28 02:27:47 -0600 (Thu, 28 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "Topology.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * A Family Specific Workaround method, to sync internal node 1 SbiAddr setting. - * - * @param[in] Data The table data value (unused in this routine) - * @param[in] StdHeader Config handle for library and services - * - *--------------------------------------------------------------------------------------- - **/ -VOID -STATIC -F10RevDSyncInternalNode1SbiAddr ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 DataOr; - UINT32 DataAnd; - UINT32 ModuleType; - PCI_ADDR PciAddress; - AGESA_STATUS AgesaStatus; - UINT32 SyncToModule; - AP_MAIL_INFO ApMailboxInfo; - UINT32 LocalPciRegister; - - ApMailboxInfo.Info = 0; - - GetApMailbox (&ApMailboxInfo.Info, StdHeader); - ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS); - ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES); - Socket = ApMailboxInfo.Fields.Socket; - Module = ApMailboxInfo.Fields.Module; - ModuleType = ApMailboxInfo.Fields.ModuleType; - - // sync is just needed on multinode cpu - if (ModuleType != 0) { - // check if it is internal node 0 of every socket - if (Module == 0) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x1E4; - // read internal node 0 F3x1E4[6:4] - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - DataOr = LocalPciRegister & ((UINT32) (7 << 4)); - DataAnd = ~(UINT32) (7 << 4); - for (SyncToModule = 1; SyncToModule < GetPlatformNumberOfModules (); SyncToModule++) { - if (GetPciAddress (StdHeader, Socket, SyncToModule, &PciAddress, &AgesaStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x1E4; - // sync the other internal node F3x1E4[6:4] - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LocalPciRegister &= DataAnd; - LocalPciRegister |= DataOr; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } - } - } - } -} - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// F a m i l y S p e c i f i c W o r k a r o u n d T a b l e s -// ----------------------------------------------------------------- - -STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F10Workarounds[] = -{ -// F0x6C - Link Initialization Control Register -// Request for warm reset in AmdInitEarly -// [5, BiosRstDet] = 1b - { - FamSpecificWorkaround, - { - AMD_FAMILY_10, // CpuFamily - AMD_F10_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - SetWarmResetAtEarly, // function call - 0x00000000, // data - }} - }, - // Internal Node 1 SbiAddr sync for RevD - { - FamSpecificWorkaround, - { - AMD_FAMILY_10_HY, - AMD_F10_HY_ALL - }, - {AMD_PF_ALL}, - {{ - F10RevDSyncInternalNode1SbiAddr, - 0x00000000 - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F10WorkaroundsTable = { - PrimaryCores, - (sizeof (F10Workarounds) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *)F10Workarounds, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/F15PackageType.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/F15PackageType.h deleted file mode 100644 index 5c67a23a6b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/F15PackageType.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Package Type Definitions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15F - * @e \$Revision: 59564 $ @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _F15_PACKAGE_TYPE_H_ -#define _F15_PACKAGE_TYPE_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - -// Below equates are defined to cooperate with LibAmdGetPackageType. -#define PACKAGE_TYPE_AM3r2 (1 << 1) -#define PACKAGE_TYPE_G34 (1 << 3) -#define PACKAGE_TYPE_C32 (1 << 5) - -#define PACKAGE_TYPE_SCM (PACKAGE_TYPE_AM3r2 | PACKAGE_TYPE_C32) -#define PACKAGE_TYPE_MCM (PACKAGE_TYPE_G34) - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -#endif // _F15_PACKAGE_TYPE_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/F15PstateHpcMode.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/F15PstateHpcMode.c deleted file mode 100644 index 043845918f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/F15PstateHpcMode.c +++ /dev/null @@ -1,208 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 P-state HPC mode Initialization - * - * Enables High performance Computing mode. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * @e \$Revision: 57421 $ @e \$Date: 2011-08-03 19:59:42 -0600 (Wed, 03 Aug 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "heapManager.h" -#include "cpuF15PowerMgmt.h" -#include "CommonReturns.h" -#include "cpuPstateHpcMode.h" -#include "cpuPstateTables.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_F15PSTATEHPCMODE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * entry point for enabling High Performance Computing. - * - * This function must be run after P-states initialization and before enabling low power P-states - * - * @param[in] PstateHpcModeServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15InitializePstateHpcMode ( - IN PSTATE_HPC_MODE_FAMILY_SERVICES *PstateHpcModeServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 OriginalPstate; - UINT8 X; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 SocketCount; - UINT32 i; - UINT64 MsrData; - PCI_ADDR PciAddr; - AGESA_STATUS IgnoredSts; - AGESA_STATUS Flag; - F15_CPB_CTRL_REGISTER CpbCtrl; - CLK_PWR_TIMING_CTRL2_REGISTER CPTC2; - HTC_REGISTER Htc; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - LOCATE_HEAP_PTR LocateHeapParams; - PSTATE_LEVELING *PStateLevelingBuffer; - PSTATE_LEVELING *PStateLevelingBufferTemp; - - Flag = AGESA_SUCCESS; - // Locate P-State data buffer - LocateHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE; - if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) { - Flag = AGESA_ERROR; - PStateLevelingBuffer = NULL; - SocketCount = 1; - } else { - PStateLevelingBuffer = ((S_CPU_AMD_PSTATE *) (LocateHeapParams.BufferPtr))->PStateLevelingStruc; - SocketCount = ((S_CPU_AMD_PSTATE *) (LocateHeapParams.BufferPtr))->TotalSocketInSystem; - } - - // Step1. Read MSRC001_0063[CurPstate] and store the value in OriginalPstate. - LibAmdMsrRead (MSR_PSTATE_STS, &MsrData, StdHeader); - OriginalPstate = (UINT8) (((PSTATE_STS_MSR *) &MsrData)->CurPstate); - // Step2. Write 0 to MSRC001_0062[PstateCmd]. - // Step3. Wait for MSRC001_0063[CurPstate] == 0. - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); - // Step4. If D18F4x15C[NumBoostStates] != D18F3xDC[PstateMaxVal], execute the following sequence - // 4.A Set X = D18F4x15C[NumBoostStates]. - // 4.B If X+1 == D18F3xDC[PstateMaxVal], go to step 5. - // 4.C Copy MSRC001_00[6B:64] indexed by P-state X to MSRC001_00[6B:64] indexed by P-state X+1. - // 4.D Write 0b to PstateEn from MSRC001_00[6B:64] indexed by P-state X+1. - // 4.E Set X = X+1 and go to step B. - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - GetPciAddress (StdHeader, Socket, Module, &PciAddr, &IgnoredSts); - PciAddr.Address.Function = FUNC_4; - PciAddr.Address.Register = CPB_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddr, &CpbCtrl, StdHeader); // F4x15C - - PciAddr.Address.Function = FUNC_3; - PciAddr.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddr, &CPTC2, StdHeader); // F3xDC - - // In case that F3xDC[PstateMaxVal] was increased by Low Power Pstate function during the first time of running that function. - // Get the real PstateMaxVal by checking C001_00[6B:64][PsEnable] - while (CPTC2.PstateMaxVal != 0) { - LibAmdMsrRead ((PS_REG_BASE + CPTC2.PstateMaxVal), &MsrData, StdHeader); - if ((MsrData & BIT63) == BIT63) { - break; - } - CPTC2.PstateMaxVal--; - } - - if (CpbCtrl.NumBoostStates != CPTC2.PstateMaxVal) { - X = (UINT8) CpbCtrl.NumBoostStates; - while ((X + 1) < (UINT8) CPTC2.PstateMaxVal) { - LibAmdMsrRead ((PS_REG_BASE + X), &MsrData, StdHeader); - MsrData &= ~BIT63; - LibAmdMsrWrite ((PS_REG_BASE + X + 1), &MsrData, StdHeader); - // Make sure Agesa doesn't declared the P-states modified by these algorithms to the OS - if (PStateLevelingBuffer != NULL) { - PStateLevelingBufferTemp = PStateLevelingBuffer; - for (i = 0; i < SocketCount; i++) { - PStateLevelingBufferTemp->PStateCoreStruct[0].PStateStruct[X + 1].PStateEnable = 0; - //Calculate next node buffer address - PStateLevelingBufferTemp = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferTemp + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferTemp->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); - } - } - X++; - } - } - // Step5. Write OriginalPstate to MSRC001_0062[PstateCmd]. - // Step6. Wait for MSRC001_0063[CurPstate] == OriginalPstate. - FamilySpecificServices->TransitionPstate (FamilySpecificServices, OriginalPstate, (BOOLEAN) TRUE, StdHeader); - // Step7. Write D18F3x64[HtcPstateLimit] with the value from D18F3xDC[PstateMaxVal] - PciAddr.Address.Register = HTC_REG; - LibAmdPciRead (AccessWidth32, PciAddr, &Htc, StdHeader); // F3x64 - Htc.HtcPstateLimit = CPTC2.PstateMaxVal; - LibAmdPciWrite (AccessWidth32, PciAddr, &Htc, StdHeader); // F3x64 - - return Flag; -} - - - -CONST PSTATE_HPC_MODE_FAMILY_SERVICES ROMDATA F15PstateHpcSupport = -{ - 0, - F15InitializePstateHpcMode -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/Makefile.inc deleted file mode 100644 index a08d8e426b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -libagesa-y += F15PstateHpcMode.c -libagesa-y += cpuCommonF15Utilities.c -libagesa-y += cpuF15Apm.c -libagesa-y += cpuF15BrandId.c -libagesa-y += cpuF15CacheDefaults.c -libagesa-y += cpuF15Dmi.c -libagesa-y += cpuF15MsrTables.c -libagesa-y += cpuF15PciTables.c -libagesa-y += cpuF15PowerCheck.c -libagesa-y += cpuF15Utilities.c -libagesa-y += cpuF15WheaInitDataTables.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c deleted file mode 100644 index 5863af857b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c +++ /dev/null @@ -1,186 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi C6 C-state feature support functions. - * - * Provides the functions necessary to initialize the C6 feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFeatures.h" -#include "cpuC6State.h" -#include "cpuApicUtilities.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "OptionFamily15hEarlySample.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORC6STATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F15_OR_ES_C6_SUPPORT F15OrEarlySampleC6Support; -extern F15_OR_ES_MCU_PATCH F15OrEarlySampleLoadMcuPatch; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -F15OrReloadMicrocodePatchAfterMemInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Is C6 supported on this CPU - * - * @param[in] C6Services Pointer to this CPU's C6 family services. - * @param[in] Socket This core's zero-based socket number. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE C6 state is supported. - * @retval FALSE C6 state is not supported. - * - */ -BOOLEAN -STATIC -F15OrIsC6Supported ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT32 Socket, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsEnabled; - - IsEnabled = TRUE; - IsEnabled = IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader); - - F15OrEarlySampleC6Support.F15OrIsC6SupportedHook (&IsEnabled, StdHeader); - - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable C6 on a family 15h CPU. - * - * @param[in] C6Services Pointer to this CPU's C6 family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15OrInitializeC6 ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - UINT32 PciMask; - PCI_ADDR PciAddress; - - if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { - // Initialize F4x118 - // bits[24] PwrGateEnCstAct1 = 1 - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CSTATE_CTRL1_REG; - LocalPciRegister = 0x01000000; - PciMask = 0xFFFFFFFF; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, PciMask, LocalPciRegister, StdHeader); - } - - return AGESA_SUCCESS; -} - -/** - * Reload microcode patch after memory is initialized. - * - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -F15OrReloadMicrocodePatchAfterMemInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - F15OrEarlySampleLoadMcuPatch.F15OrUpdateMcuPatchHook (StdHeader); -} - -CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support = -{ - 0, - F15OrIsC6Supported, - F15OrInitializeC6, - F15OrReloadMicrocodePatchAfterMemInit -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c deleted file mode 100644 index f6c9f5f0c1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c +++ /dev/null @@ -1,183 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 CPB Initialization - * - * Enables core performance boost. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F15/OR - * @e \$Revision: 54493 $ @e \$Date: 2011-06-08 15:21:06 -0600 (Wed, 08 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuFeatures.h" -#include "cpuCpb.h" -#include "F15PackageType.h" -#include "OptionFamily15hEarlySample.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORCPB_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F15_OR_ES_CPB_SUPPORT F15OrEarlySampleCpbSupport; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * BSC entry point for checking whether or not CPB is supported. - * - * @param[in] CpbServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] Socket Zero based socket number to check. - * @param[in] StdHeader Config handle for library and services. - * - * @retval TRUE CPB is supported. - * @retval FALSE CPB is not supported. - * - */ -BOOLEAN -STATIC -F15OrIsCpbSupported ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpbControl; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - BOOLEAN IsEnabled; - - IsEnabled = TRUE; - - GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts); - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CPB_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); - IsEnabled = (BOOLEAN) (((CPB_CTRL_REGISTER *) (&CpbControl))->NumBoostStates != 0); - - F15OrEarlySampleCpbSupport.F15OrIsCpbSupportedHook (&IsEnabled, StdHeader); - - return IsEnabled; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * BSC entry point for for enabling Core Performance Boost. - * - * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. - * - * @param[in] CpbServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] EntryPoint Current CPU feature dispatch point. - * @param[in] Socket Zero based socket number to check. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15OrInitializeCpb ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT64 EntryPoint, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpbControl; - UINT32 Module; - UINT32 PackageType; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - if ((EntryPoint & (CPU_FEAT_BEFORE_PM_INIT | CPU_FEAT_INIT_LATE_END | CPU_FEAT_S3_LATE_RESTORE_END)) != 0) { - for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) { - PackageType = LibAmdGetPackageType (StdHeader); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CPB_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); - if (PackageType == PACKAGE_TYPE_AM3r2) { - ((CPB_CTRL_REGISTER *) (&CpbControl))->BoostSrc = 1; - } else { - if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) { - ((CPB_CTRL_REGISTER *) (&CpbControl))->BoostSrc = 1; - } - } - LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader); - } - } - return AGESA_SUCCESS; -} - -CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport = -{ - 0, - F15OrIsCpbSupported, - F15OrInitializeCpb -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c deleted file mode 100644 index afcea1ddd8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c +++ /dev/null @@ -1,834 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 OR early sample support. - * - * Provides the code and data required to support pre-production silicon. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "F15OrUtilities.h" -#include "cpuF15Utilities.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "GeneralServices.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15OREARLYSAMPLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -typedef union { - UINT64 RawData; - PATCH_LOADER_MSR BitFields; -} PATCH_LOADER; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -BOOLEAN -F15OrEarlySamplesLoadMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrHtcInitEarlySampleHook ( - IN OUT UINT32 *HtcRegister, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrIsCpbDisabledEarlySample ( - IN OUT BOOLEAN *IsEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrIsC6DisabledEarlySample ( - IN OUT BOOLEAN *IsEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrEarlySamplesAvoidNbCyclesStart ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT UINT64 *SavedMsrValue - ); - -VOID -F15OrEarlySamplesAvoidNbCyclesEnd ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN UINT64 *SavedMsrValue - ); - -VOID -F15OrEarlySamplesAfterPatchLoaded ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN BOOLEAN IsPatchLoaded - ); - -BOOLEAN -F15OrEarlySamplesLoadMicrocodePatch ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - - - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -F15OrB0WeightsInit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * D A T A D E C L A R A T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------- - * Early Sample PCI registers - *----------------------------- - */ - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrEarlySamplePciRegisters[] = -{ -// F3x188 - NB Configuration 2 Register -// bit[30] Reserved = 1 Erratum #620, only on OR A0, A1 and B0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_LT_B1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address - 0x40000000, // regData - 0x40000000, // regMask - }} - }, -// F3x18C - Reserved -// bit[31] Reserved = 1 Erratum #603, only on OR A0, A1 and B0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_LT_B1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x18C), // Address - 0x80000000, // regData - 0x80000000, // regMask - }} - }, - -// F3x1B8 - L3 Control 1 -// bit[7] Reserved = 1, Erratum #574 -// bit[29] Reserved = 1, Erratum #574 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address - 0x20000080, // regData - 0x20000080, // regMask - }} - }, -// F4x110 - Sample and Residency Timers -// bits[20:13] MinResTmr = 0x64 - { - PciRegister, - { - AMD_FAMILY_15_OR, // CpuFamily - AMD_F15_OR_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x110), // Address - 0x000C8000, // regData - 0x001FE000, // regMask - }} - }, -// F4x1A0 - Reserved -// bits[31:0] Reserved = 4 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_A0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A0), // Address - 0x00000004, // regData - 0xFFFFFFFF, // regMask - }} - }, -// F4x1A4 - Reserved -// bits[31:0] Reserved = 0x24 Erratum #553 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_A0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A4), // Address - 0x00000024, // regData - 0xFFFFFFFF, // regMask - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrEarlySamplePciRegisterTable = { - PrimaryCores, - (sizeof (F15OrEarlySamplePciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F15OrEarlySamplePciRegisters, -}; - -/*----------------------------- - * Early Sample MSR registers - *----------------------------- - */ - -STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15OrEarlySampleMsrRegisters[] = -{ -// MSR_LS_CFG (0xC0011020) -// bit[0] = 1, Erratum #500 for OR-A0 only -// bit[4] = 1, Erratum #501 for OR-A0 only -// bit[28] DisSS = 1, Erratum #495, #496 for OR-A0 only -// bit[30] = 1, Erratum #544 for OR-A0 only -// bit[62] = 1, Erratum #494 for OR-A0 only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_A0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_LS_CFG, // MSR Address - 0x4000000050000011, // OR Mask - 0x4000000050000011, // NAND Mask - }} - }, -// MSR_DC_CFG (0xC0011022) -// bit[13] DisHwPf = 1, Erratum #498, OR-A0 only -// bit[10] = 1, Erratum #575, OR-A0 only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_A0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_DC_CFG, // MSR Address - 0x0000000000002400, // OR Mask - 0x0000000000002400, // NAND Mask - }} - }, -// MSR_DE_CFG (0xC0011029) -// bit[7:2] = 111111b, Erratum #497, OR-A0 only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_A0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_DE_CFG, // MSR Address - Shared - 0x00000000000000FC, // OR Mask - 0x00000000000000FC, // NAND Mask - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrEarlySampleMsrRegisterTable = { - AllCores, - (sizeof (F15OrEarlySampleMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrEarlySampleMsrRegisters, -}; - -/*----------------------------- - * Early Sample Shared MSR registers - *----------------------------- - */ - -STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15OrEarlySampleSharedMsrRegisters[] = -{ -// MSR_CU_CFG2 (0xC001102A) -// bit[27] = 1, Erratum #572, OR-Ax only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CU_CFG2, // MSR Address - Shared - 0x0000000008000000, // OR Mask - 0x0000000008000000, // NAND Mask - }} - }, - -// MSR_CU_CFG3 (0xC001102B) -// bit[34] Reserved = 1, Erratum #568, OR-Ax only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CU_CFG3, // MSR Address - 0x0000000400000000, // OR Mask - 0x0000000400000000, // NAND Mask - }} - }, -// MSR_C001_1070 -// bit[41] = 0, Erratum #597, OR-Ax only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_C001_1070, // MSR Address - Shared - 0x0000000000000000, // OR Mask - 0x0000020000000000, // NAND Mask - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrRegisterTable = { - CorePairPrimary, - (sizeof (F15OrEarlySampleSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrEarlySampleSharedMsrRegisters, -}; - -/*----------------------------- - * Early Sample Workarounds - *----------------------------- - */ - -STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15OrEarlySampleWorkarounds[] = -{ - // HT PHY DLL Compensation setting for Ax - { - FamSpecificWorkaround, - { - AMD_FAMILY_15, - AMD_F15_OR_Ax - }, - {AMD_PF_ALL}, - {{ - F15HtPhyOverrideDllCompensation, - 0x00000000 - }} - }, - // CPU TDP Limit 2 setting for Ax - { - FamSpecificWorkaround, - { - AMD_FAMILY_15, - AMD_F15_OR_Ax - }, - {AMD_PF_ALL}, - {{ - F15OrOverrideNodeTdpLimit, - 0x00000000 - }} - }, - // CPU Node TDP Accumulator Throttle Threshold setting for Ax - { - FamSpecificWorkaround, - { - AMD_FAMILY_15_OR, - AMD_F15_OR_Ax - }, - {AMD_PF_ALL}, - {{ - F15OrOverrideNodeTdpAccumulatorThrottleThreshold, - 0x00000000 - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrEarlySampleWorkaroundsTable = { - PrimaryCores, - (sizeof (F15OrEarlySampleWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *)F15OrEarlySampleWorkarounds, -}; - -/*----------------------------- - * Early Sample shared MSRs with Special Programming Requirements Table - *----------------------------- - */ - -STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15OrEarlySampleSharedMsrWorkarounds[] = -{ - // MSRC001_1072 - { - FamSpecificWorkaround, - { - AMD_FAMILY_15_OR, - AMD_F15_OR_B0 - }, - {AMD_PF_ALL}, - {{ - F15OrB0WeightsInit, - 0x00000000 - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrWorkaroundTable = { - CorePairPrimary, - (sizeof (F15OrEarlySampleSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrEarlySampleSharedMsrWorkarounds, -}; - - -CONST UINT32 ROMDATA F15OrB0WeightsTable [] = { - 0x1300005A, //MSRC001_1072_x00 - 0x10ABD100, //MSRC001_1072_x01 - 0xBF1A1A44, //MSRC001_1072_x02 - 0xC4DABEA4, //MSRC001_1072_x03 - 0x147B7B6A, //MSRC001_1072_x04 - 0x320C0C00, //MSRC001_1072_x05 - 0xE6D6C6DC, //MSRC001_1072_x06 - 0x00911C06, //MSRC001_1072_x07 - 0x1F473727, //MSRC001_1072_x08 - 0x9FA3A32B, //MSRC001_1072_x09 - 0xDFCFBFAF, //MSRC001_1072_x0A - 0xCFBFAF9F, //MSRC001_1072_x0B - 0x606060DF, //MSRC001_1072_x0C - 0x00000060, //MSRC001_1072_x0D - 0xBAAA9A00, //MSRC001_1072_x0E - 0xFF00DACA, //MSRC001_1072_x0F - 0xFEFEFF64, //MSRC001_1072_x10 - 0x41FCFEFE, //MSRC001_1072_x11 - 0xE14C2F0D, //MSRC001_1072_x12 - 0x95A371EA, //MSRC001_1072_x13 - 0x002EE260, //MSRC001_1072_x14 - 0x00F907D2, //MSRC001_1072_x15 - 0xF9F2A5A5, //MSRC001_1072_x16 - 0x97C100E3, //MSRC001_1072_x17 - 0x91C5B577, //MSRC001_1072_x18 - 0x95C1B1A1, //MSRC001_1072_x19 - 0x68584800, //MSRC001_1072_x1A - 0x67000000, //MSRC001_1072_x1B - 0xB2003109, //MSRC001_1072_x1C - 0x3F8DCDC4, //MSRC001_1072_x1D - 0xD2D4D409, //MSRC001_1072_x1E - 0x090000D2, //MSRC001_1072_x1F - 0x00160000, //MSRC001_1072_x20 - 0x0000E300 //MSRC001_1072_x21 -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Early sample hook point during HTC initialization - * - * @param[in,out] HtcRegister Value of F3x64 to be written. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F15OrHtcInitEarlySampleHook ( - IN OUT UINT32 *HtcRegister, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MsrAddr; - UINT64 Msr; - - if (((HTC_REGISTER *) HtcRegister)->HtcPstateLimit == 0) { - // HtcPstateLimit is set to Pb0. Reprogram it to the minimum enabled P-state with - // with NbPstate = 0 - for (MsrAddr = PS_MAX_REG; MsrAddr > PS_MIN_REG; MsrAddr--) { - LibAmdMsrRead (MsrAddr, &Msr, StdHeader); - if ((((PSTATE_MSR *) &Msr)->PsEnable == 1) && (((PSTATE_MSR *) &Msr)->NbPstate == 0)) { - break; - } - } - ((HTC_REGISTER *) HtcRegister)->HtcPstateLimit = (MsrAddr - PS_MIN_REG); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is CPB supported on this CPU - * - * @param[in,out] IsEnabled Whether or not CPB should be enabled. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -F15OrIsCpbDisabledEarlySample ( - IN OUT BOOLEAN *IsEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - // Check if this CPU is OR A0, then disable CPB support. - if ((LogicalId.Revision & AMD_F15_OR_A0) != 0) { - *IsEnabled = FALSE; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is C6 supported on this CPU - * - * @param[in,out] IsEnabled Whether or not C6 should be enabled. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -F15OrIsC6DisabledEarlySample ( - IN OUT BOOLEAN *IsEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - // Check if this CPU is OR A0, then disable C6 support. - if ((LogicalId.Revision & AMD_F15_OR_A0) != 0) { - *IsEnabled = FALSE; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Update the weights for affected OR B0 CPUs. - * - * This function implements a workaround for OR B0 when applicable. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrB0WeightsInit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 ProductInfo; - UINT64 LocalMsr; - PCI_ADDR PciAddress; - - if (IsWarmReset (StdHeader)) { - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PRCT_INFO_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &ProductInfo, StdHeader); - - if ((ProductInfo & BIT31) == 0) { - for (i = 0; i < ((sizeof F15OrB0WeightsTable) / (sizeof F15OrB0WeightsTable[0])); i++) { - LocalMsr = (((((UINT64) F15OrB0WeightsTable[i]) << 32) | i) | BIT14); - LibAmdMsrWrite (0xC0011072, &LocalMsr, StdHeader); - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * Workaround to avoid patch loading from causing NB cycles - * - * - * @param[in,out] StdHeader - Config handle for library and services. - * @param[in,out] SavedMsrValue - Saved a MSR value - * - */ -VOID -F15OrEarlySamplesAvoidNbCyclesStart ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT UINT64 *SavedMsrValue - ) -{ - UINT64 MsrValue; - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - // Check if this CPU is OR Ax, expected fix in OR-B0 - if ((LogicalId.Revision & AMD_F15_OR_Ax) != 0) { - // Workaround for F15 OR-Ax workaround to avoid patch loading from causing NB cycles - // Start - Set MSR C001_102A [8] - LibAmdMsrRead (MSR_BU_CFG2, SavedMsrValue, StdHeader); - MsrValue = *SavedMsrValue | BIT8; - LibAmdMsrWrite (MSR_BU_CFG2, &MsrValue, StdHeader); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * Workaround to avoid patch loading from causing NB cycles - * - * - * @param[in,out] StdHeader - Config handle for library and services. - * @param[in] SavedMsrValue - Saved a MSR value - * - */ -VOID -F15OrEarlySamplesAvoidNbCyclesEnd ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN UINT64 *SavedMsrValue - ) -{ - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - if ((LogicalId.Revision & AMD_F15_OR_Ax) != 0) { - // Restore Workaround for F15 OR-Ax workaround to avoid patch loading from causing NB cycles - // End - Restore MSR C001_102A - LibAmdMsrWrite (MSR_BU_CFG2, SavedMsrValue, StdHeader); - } - -} - -/* -----------------------------------------------------------------------------*/ -/** - * Workaround for Ax processors after patch is loaded. - * - * - * @param[in] StdHeader - Config handle for library and services. - * @param[in] IsPatchLoaded - Is patch loaded - * - */ -VOID -F15OrEarlySamplesAfterPatchLoaded ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN BOOLEAN IsPatchLoaded - ) -{ - UINT64 MsrValue; - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - - // MSR C001_1023[4:3] = 11b - // Erratum #502, OR-A0 only after microcode patch has been loaded - if (((LogicalId.Revision & AMD_F15_OR_A0) != 0) && (IsPatchLoaded)) { - LibAmdMsrRead (MSR_CU_CFG, &MsrValue, StdHeader); - MsrValue |= 0x18; - LibAmdMsrWrite (MSR_CU_CFG, &MsrValue, StdHeader); - } - - // Erratum #590, OR-A1 only, if any patch is applied - // MSR C001_0028 = 0x2E00_0080 - // MSR C001_0029 = 0xFE00_0080 - // MSR C001_002C = 0x0400_1029 - if (((LogicalId.Revision & AMD_F15_OR_A1) != 0) && (IsPatchLoaded)) { - MsrValue = 0x2E000080; - LibAmdMsrWrite (0xC0010028, &MsrValue, StdHeader); - - MsrValue = 0xFE000080; - LibAmdMsrWrite (0xC0010029, &MsrValue, StdHeader); - - MsrValue = 0x04001029; - LibAmdMsrWrite (0xC001002C, &MsrValue, StdHeader); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * Update microcode patch in current processor. - * - * Then reads the patch id, and compare it to the expected, in the Microprocessor - * patch block. - * - * @param[in] StdHeader - Config handle for library and services. - * - * @retval TRUE - Patch Loaded Successfully. - * @retval FALSE - Patch Did Not Get Loaded. - * - */ -BOOLEAN -F15OrEarlySamplesLoadMicrocodePatch ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PatchNumber; - UINT8 TotalPatches; - UINT16 ProcessorEquivalentId; - BOOLEAN Status; - MICROCODE_PATCH **MicrocodePatchPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - Status = FALSE; - - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - // Get the patch pointer - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (const VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader); - - IDS_OPTION_HOOK (IDS_UCODE, &TotalPatches, StdHeader); - - // Get the processor microcode path equivalent ID - if (GetPatchEquivalentId (&ProcessorEquivalentId, StdHeader)) { - // parse the patch table to see if we have one for the current cpu - for (PatchNumber = 0; PatchNumber < TotalPatches; PatchNumber++) { - if (ValidateMicrocode (MicrocodePatchPtr[PatchNumber], ProcessorEquivalentId, StdHeader)) { - if (F15OrEarlySamplesLoadMicrocode (MicrocodePatchPtr[PatchNumber], StdHeader)) { - Status = TRUE; - } else { - PutEventLog (AGESA_ERROR, - CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED, - 0, 0, 0, 0, StdHeader); - } - break; // Once we find a microcode patch that matches the processor, exit the for loop - } - } - } - } - return Status; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * F15OrEarlySamplesLoadMicrocode - * - * Update microcode patch in current processor, then reads the - * patch id, and compare it to the expected, in the Microprocessor - * patch block. - * - * Note: This is a special version of the normal LoadMicrocode() - * function which lives in cpuMicrocodePatch.c. This version - * implements a workaround (on Or-B0 only) before applying the - * microcode patch. - * - * @param[in] MicrocodePatchPtr - Pointer to Microcode Patch. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval TRUE - Patch Loaded Successfully. - * @retval FALSE - Patch Did Not Get Loaded. - * - */ -BOOLEAN -F15OrEarlySamplesLoadMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MicrocodeVersion; - UINT64 MsrData; - PATCH_LOADER PatchLoaderMsr; - CPU_LOGICAL_ID LogicalId; - - // Load microcode patch into CPU - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - PatchLoaderMsr.RawData = (UINT64)(intptr_t) MicrocodePatchPtr; - PatchLoaderMsr.BitFields.SBZ = 0; - // Check if this CPU is OR-B0, expected fix in OR-B1 - if ((LogicalId.Revision & AMD_F15_OR_B0) != 0) { - LibAmdMsrRead (MSR_BR_FROM, &MsrData, StdHeader); - } - - LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader); - - // Do ucode patch Authentication - // Read microcode version back from CPU, determine if - // it is the same patch level as contained in the source - // microprocessor patch block passed in - GetMicrocodeVersion (&MicrocodeVersion, StdHeader); - if (MicrocodeVersion == MicrocodePatchPtr->PatchID) { - return (TRUE); - } else { - return (FALSE); - } -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c deleted file mode 100644 index 78057a7847..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c +++ /dev/null @@ -1,135 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Bulldozer Equivalence Table related data - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "amdlib.h" -#include "cpuRegisters.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF15OrMicrocodeEquivalenceTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **OrEquivalenceTablePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -STATIC CONST UINT16 ROMDATA CpuF15OrMicrocodeEquivalenceTable[] = -{ - 0x6012, 0x6012, - 0x6011, 0x6011, - 0x6010, 0x6010, - 0x6001, 0x6001, - 0x6000, 0x6000 -}; - -// Unencrypted equivalent -STATIC CONST UINT16 ROMDATA CpuF15OrUnEncryptedMicrocodeEquivalenceTable[] = -{ - 0x6012, 0x6812, - 0x6011, 0x6811, - 0x6010, 0x6810, - 0x6001, 0x6801, - 0x6000, 0x6800 -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the appropriate microcode patch equivalent ID table. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] OrEquivalenceTablePtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF15OrMicrocodeEquivalenceTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **OrEquivalenceTablePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrDeCfg; - - LibAmdMsrRead (MSR_DE_CFG, &MsrDeCfg, StdHeader); - if ((MsrDeCfg & 0x80000) == 0) { - *NumberOfElements = ((sizeof (CpuF15OrUnEncryptedMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); - *OrEquivalenceTablePtr = CpuF15OrUnEncryptedMicrocodeEquivalenceTable; - } else { - *NumberOfElements = ((sizeof (CpuF15OrMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); - *OrEquivalenceTablePtr = CpuF15OrMicrocodeEquivalenceTable; - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c deleted file mode 100644 index 2129d59d07..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c +++ /dev/null @@ -1,833 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Ht Phy tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 53592 $ @e \$Date: 2011-05-23 00:27:15 -0600 (Mon, 23 May 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_REVD_HY_F15HYHTPHYTABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// HT Phy T a b l e s -// ------------------------- -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrHtPhyRegisters[] = -{ -// -// All the entries for XmtRdPtr -// -// 0xCF -// HT_PHY_HT1_FIFO_PTR_OPT_VALUE - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0xCF, // Address - 0x00000D4D, // regData - 0x0000FFFF, // regMask - }} - }, -// 0xDF -// HT_PHY_HT1_FIFO_PTR_OPT_VALUE - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0xDF, // Address - 0x00000D4D, // regData - 0x0000FFFF, // regMask - }} - }, -// 0xCF -// Default for HT3, unless overridden below. - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT3, // - 0xCF, // Address - 0x00000A2A, // regData - 0x0000FFFF, // regMask - }} - }, -// 0xDF -// Default for HT3, unless overridden below. - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT3, // - 0xDF, // Address - 0x00000A2A, // regData - 0x0000FFFF, // regMask - }} - }, -// 0xC1 -// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT3, // - 0xC1, // Address - 0x08040000, // regData - 0x3FFFC000, // regMask - }} - }, -// 0xD1 -// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT3, // - 0xD1, // Address - 0x08040000, // regData - 0x3FFFC000, // regMask - }} - }, -// 0xC1 -// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0xC1, // Address - 0x04020000, // regData - 0x3FFFC000, // regMask - }} - }, -// 0xD1 -// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0xD1, // Address - 0x04020000, // regData - 0x3FFFC000, // regMask - }} - }, -// 0xC5 -// [7] TxLs23ClkGateEn = 1 - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_ALL, // - 0xC5, // Address - 0x00000080, // regData - 0x00000080, // regMask - }} - }, -// 0xD5 -// [7] TxLs23ClkGateEn = 1 - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_ALL, // - 0xD5, // Address - 0x00000080, // regData - 0x00000080, // regMask - }} - }, - -// -// Deemphasis Settings -// -// HT1: clear any warm reset deemphasis settings. - - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0xC4, // Address - 0x00000000, // regData - 0x0003FC00, // regMask - }} - }, - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0xD4, // Address - 0x00000000, // regData - 0x0003FC00, // regMask - }} - }, - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0x720C, // Address - 0x00000000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0x730C, // Address - 0x00000000, // regData - 0xFFFFFFFF, // regMask - }} - }, - -//deemphasis level Post2[31, 24] Post1[23, 16] Pre1[15, 8] Margin[7, 0] -// No deemphasis 00h 00h 00h 00h -// -3dB postcursor 00h 26h 00h 00h -// -6dB postcursor 00h 40h 00h 00h -// -8dB postcursor 00h 4Dh 00h 00h -// -11dB postcursor 00h 5Ch 00h 00h -// 00h 4Dh 0Fh 00h -// -11dB postcursor with -8dB precursor - - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL_NONE, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x00000000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL_NONE, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x00000000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__3, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x00260000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__3, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x00260000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__6, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x00400000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__6, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x00400000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__8, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x004D0000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__8, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x004D0000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x005C0000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x005C0000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11_8, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x004D0F00, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11_8, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x004D0F00, // regData - 0xFFFFFFFF, // regMask - }} - }, - -// Far-device deemphasis setting DCV[15:10] -// No deemphasis 4Dh -// -2dB postcursor 3Dh -// -3dB postcursor 36h -// -5dB postcursor 2Bh -// -6dB postcursor 27h -// -7dB postcursor 22h -// -8dB postcursor 1Fh -// -9dB postcursor 1Bh -// -11dB postcursor 16h - - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL_NONE, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00013400, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL_NONE, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00013400, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__2, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x0000F400, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__2, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x0000F400, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__3, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x0000D800, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__3, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x0000D800, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__5, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x0000AC00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__5, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x0000AC00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__6, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00009C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__6, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00009C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__7, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00008800, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__7, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00008800, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__8, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00007C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__8, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00007C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__9, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00006C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__9, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00006C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__11, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00005800, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__11, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00005800, // regData - 0x0003FC00, // regMask - }} - }, -// 0x520A -// [14:13] AnalogWaitTime = 10b - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_ALL, // - 0x520A, // Address - 0x00004000, // regData - 0x00006000, // regMask - }} - }, -// 0x530A -// [14:13] AnalogWaitTime = 10b - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_ALL, // - 0x530A, // Address - 0x00004000, // regData - 0x00006000, // regMask - }} - }, -// 0xE3 -// [7] RoCalEn = 1b - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_ALL, // - 0xE3, // Address - 0x00000080, // regData - 0x00000080, // regMask - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable = { - PrimaryCores, - (sizeof (F15OrHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F15OrHtPhyRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c deleted file mode 100644 index 2f0f43e33a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c +++ /dev/null @@ -1,187 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize the Family 15h Orochi specific way of running early initialization. - * - * Returns the table of initialization steps to perform at - * AmdInitEarly. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "cpuEarlyInit.h" -#include "OptionFamily15hEarlySample.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORINITEARLYTABLE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -F15OrLoadMicrocodePatchAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetF15OrEarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE F15SetBrandIdRegistersAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; -extern F15_OR_ES_MCU_PATCH F15OrEarlySampleLoadMcuPatch; - -/*---------------------------------------------------------------------------------------- - * D A T A D E C L A R A T I O N S - *---------------------------------------------------------------------------------------- - */ -CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F15OrEarlyInitOnCoreTable[] = -{ - {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {F15SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {F15OrLoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET}, - {NULL, 0} -}; - -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a - * processor that uses the standard initialization steps should take. - * - * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[out] Table Table of appropriate init steps for the executing core. - * @param[in] EarlyParams Service Interface structure to initialize. - * @param[in] StdHeader Opaque handle to standard config header. - * - */ -VOID -GetF15OrEarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *Table = F15OrEarlyInitOnCoreTable; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Update microcode patch in current processor for Family15h OR. - * - * This function acts as a wrapper for calling the LoadMicrocodePatch - * routine at AmdInitEarly. - * - * This particualr version implements a workaround to a potential problem caused - * when upgrading the microcode on Orochi B1 processors. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrLoadMicrocodePatchAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrValue; - UINT64 BuCfg2MsrValue; - UINT64 CuCfgMsrValue; - BOOLEAN IsPatchLoaded; - - AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader); - - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - - F15OrEarlySampleLoadMcuPatch.F15OrESAvoidNbCyclesStart (StdHeader, &BuCfg2MsrValue); - - // Erratum #655 - // Set MSR C001_1023[1] = 1b, prior to writing to MSR C001_1020 - LibAmdMsrRead (MSR_CU_CFG, &CuCfgMsrValue, StdHeader); - MsrValue = CuCfgMsrValue | BIT1; - LibAmdMsrWrite (MSR_CU_CFG, &MsrValue, StdHeader); - - IsPatchLoaded = F15OrEarlySampleLoadMcuPatch.F15OrUpdateMcuPatchHook (StdHeader); - - // Erratum #655 - // Restore MSR C001_1023[1] = previous setting - LibAmdMsrWrite (MSR_CU_CFG, &CuCfgMsrValue, StdHeader); - - F15OrEarlySampleLoadMcuPatch.F15OrESAvoidNbCyclesEnd (StdHeader, &BuCfg2MsrValue); - F15OrEarlySampleLoadMcuPatch.F15OrESAfterPatchLoaded (StdHeader, IsPatchLoaded); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c deleted file mode 100644 index 6c94521624..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c +++ /dev/null @@ -1,377 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi IO C-state feature support functions. - * - * Provides the functions necessary to initialize the IO C-state feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFeatures.h" -#include "cpuIoCstate.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "CommonReturns.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORIOCSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrInitializeIoCstateOnCore ( - IN VOID *CstateBaseMsr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15OrIsCsdObjGenerated ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable IO Cstate on a family 15h Orochi CPU. - * Implement BIOS Requirements for Initialization of C-states - * - * @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15OrInitializeIoCstate ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - UINT32 PciMask; - UINT64 LocalMsrRegister; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - - if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { - // Initialize MSRC001_0073[CstateAddr] on each core to a region of - // the IO address map with 8 consecutive available addresses. - LocalMsrRegister = 0; - - ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress; - - TaskPtr.FuncAddress.PfApTaskI = F15OrInitializeIoCstateOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); - - // Initialize F4x128 - // bits[0] CoreCstateMode = 0 - // bits[1] CoreCstatePolicy = 0 - // bits[4:2] HaltCstateIndex = 0 - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CSTATE_POLICY_CTRL1_REG; - LocalPciRegister = 0x00000000; - PciMask = 0xFFFFFFE0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, PciMask, LocalPciRegister, StdHeader); - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable CState on a family 15h Orochi core. - * - * @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrInitializeIoCstateOnCore ( - IN VOID *CstateBaseMsr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Initialize MSRC001_0073[CstateAddr] on each core - LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the size of CST object - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data - * @param[in] StdHeader Config Handle for library, services. - * - * @retval CstObjSize Size of CST Object - * - */ -UINT32 -STATIC -F15OrGetAcpiCstObj ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN GenerateCsdObj; - UINT32 CStateAcpiObjSize; - IO_CSTATE_FAMILY_SERVICES *FamilyServices; - ACPI_CST_GET_INPUT CstGetInput; - - CstGetInput.IoCstateServices = IoCstateServices; - CstGetInput.PlatformConfig = PlatformConfig; - CstGetInput.CStateAcpiObjSizePtr = &CStateAcpiObjSize; - - IDS_SKIP_HOOK (IDS_CST_SIZE, &CstGetInput, StdHeader) { - CStateAcpiObjSize = CST_HEADER_SIZE + CST_BODY_SIZE; - - // If CSD Object is generated, add the size of CSD Object to the total size of - // CState ACPI Object size - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader); - - if (GenerateCsdObj) { - CStateAcpiObjSize += CSD_HEADER_SIZE + CSD_BODY_SIZE; - } - } - return CStateAcpiObjSize; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Routine to generate the C-State ACPI objects - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] LocalApicId Local Apic Id for each core. - * @param[in, out] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrCreateAcpiCstObj ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT8 LocalApicId, - IN OUT VOID **PstateAcpiBufferPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrData; - BOOLEAN GenerateCsdObj; - CST_HEADER_STRUCT *CstHeaderPtr; - CST_BODY_STRUCT *CstBodyPtr; - CSD_HEADER_STRUCT *CsdHeaderPtr; - CSD_BODY_STRUCT *CsdBodyPtr; - IO_CSTATE_FAMILY_SERVICES *FamilyServices; - ACPI_CST_CREATE_INPUT CstInput; - - CstInput.IoCstateServices = IoCstateServices; - CstInput.LocalApicId = LocalApicId; - CstInput.PstateAcpiBufferPtr = PstateAcpiBufferPtr; - - IDS_SKIP_HOOK (IDS_CST_CREATE, &CstInput, StdHeader) { - // Read from MSR C0010073 to obtain CstateAddr - LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader); - - // Typecast the pointer - CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr; - - // Set CST Header - CstHeaderPtr->NameOpcode = NAME_OPCODE; - CstHeaderPtr->CstName_a__ = CST_NAME__; - CstHeaderPtr->CstName_a_C = CST_NAME_C; - CstHeaderPtr->CstName_a_S = CST_NAME_S; - CstHeaderPtr->CstName_a_T = CST_NAME_T; - - // Typecast the pointer - CstHeaderPtr++; - CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr; - - // Set CST Body - CstBodyPtr->PkgOpcode = PACKAGE_OPCODE; - CstBodyPtr->PkgLength = CST_LENGTH; - CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS; - CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE; - CstBodyPtr->Count = CST_COUNT; - CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE; - CstBodyPtr->PkgLength2 = CST_PKG_LENGTH; - CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS; - CstBodyPtr->BufferOpcode = BUFFER_OPCODE; - CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH; - CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS; - CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE; - CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION; - CstBodyPtr->GdrLength = CST_GDR_LENGTH; - CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO; - CstBodyPtr->RegBitWidth = 0x08; - CstBodyPtr->RegBitOffset = 0x00; - CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS; - CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1; - CstBodyPtr->EndTag = 0x0079; - CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE; - CstBodyPtr->Type = CST_C2_TYPE; - CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE; - CstBodyPtr->Latency = 100; - CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE; - CstBodyPtr->Power = 0; - - CstBodyPtr++; - //Update the pointer - *PstateAcpiBufferPtr = CstBodyPtr; - - - // Check whether CSD object should be generated - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader); - - if (GenerateCsdObj) { - CsdHeaderPtr = (CSD_HEADER_STRUCT *) *PstateAcpiBufferPtr; - - // Set CSD Header - CsdHeaderPtr->NameOpcode = NAME_OPCODE; - CsdHeaderPtr->CsdName_a__ = CST_NAME__; - CsdHeaderPtr->CsdName_a_C = CST_NAME_C; - CsdHeaderPtr->CsdName_a_S = CST_NAME_S; - CsdHeaderPtr->CsdName_a_D = CSD_NAME_D; - - CsdHeaderPtr++; - CsdBodyPtr = (CSD_BODY_STRUCT *) CsdHeaderPtr; - - // Set CSD Body - CsdBodyPtr->PkgOpcode = PACKAGE_OPCODE; - CsdBodyPtr->PkgLength = CSD_BODY_SIZE - 1; - CsdBodyPtr->PkgElements = 1; - CsdBodyPtr->PkgOpcode2 = PACKAGE_OPCODE; - CsdBodyPtr->PkgLength2 = CSD_BODY_SIZE - 4; // CSD_BODY_SIZE - Package() - Package Opcode - CsdBodyPtr->PkgElements2 = 6; - CsdBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE; - CsdBodyPtr->NumEntries = 6; - CsdBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE; - CsdBodyPtr->Revision = 0; - CsdBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE; - CsdBodyPtr->Domain = (LocalApicId & 0xFE) >> 1; - CsdBodyPtr->DWordPrefix2 = DWORD_PREFIX_OPCODE; - CsdBodyPtr->CoordType = CSD_COORD_TYPE_HW_ALL; - CsdBodyPtr->DWordPrefix3 = DWORD_PREFIX_OPCODE; - CsdBodyPtr->NumProcessors = 0x2; - CsdBodyPtr->DWordPrefix4 = DWORD_PREFIX_OPCODE; - CsdBodyPtr->Index = 0x0; - - CsdBodyPtr++; - - // Update the pointer - *PstateAcpiBufferPtr = CsdBodyPtr; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Routine to check whether CSD object should be created. - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE CSD Object should be created. - * @retval FALSE CSD Object should not be created. - * - */ -BOOLEAN -F15OrIsCsdObjGenerated ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // CSD Object should only be created when there are two cores per compute unit - if (GetComputeUnitMapping (StdHeader) == EvenCoresMapping) { - return TRUE; - } - return FALSE; -} - -CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport = -{ - 0, - (PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue, - F15OrInitializeIoCstate, - F15OrGetAcpiCstObj, - F15OrCreateAcpiCstObj, - F15OrIsCsdObjGenerated -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c deleted file mode 100644 index 1c3b0bd100..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c +++ /dev/null @@ -1,549 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi L3 dependent feature support functions. - * - * Provides the functions necessary to initialize L3 dependent features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 60552 $ @e \$Date: 2011-10-17 18:50:55 -0600 (Mon, 17 Oct 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "CommonReturns.h" -#include "cpuRegisters.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuLateInit.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuL3Features.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORL3FEATURES_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define L3Cache8_0M 0xCCCC - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/** - * The family 15h background scrubber context structure. - * - * These fields need to be saved, modified, then restored - * per die as part of HT Assist initialization. - */ -typedef struct { - UINT32 DramScrub:5; ///< DRAM scrub rate - UINT32 :3; ///< Reserved - UINT32 L3Scrub:5; ///< L3 scrub rate - UINT32 :3; ///< Reserved - UINT32 Redirect:1; ///< DRAM scrubber redirect enable - UINT32 :15; ///< Reserved -} F15_SCRUB_CONTEXT; - - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -F15OrIsNonOptimalConfig ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the input CPU supports L3 dependent features. - * - * @param[in] L3FeatureServices L3 feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * - * @retval TRUE L3 dependent features are supported. - * @retval FALSE L3 dependent features are not supported. - * - */ -BOOLEAN -STATIC -F15OrIsL3FeatureSupported ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ) -{ - UINT32 Module; - UINT32 LocalPciRegister; - BOOLEAN IsSupported; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - IsSupported = FALSE; - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((NB_CAPS_REGISTER *) &LocalPciRegister)->L3Capable == 1) { - IsSupported = TRUE; - } - break; - } - } - return IsSupported; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable the Probe filter feature - * - * @param[in] L3FeatureServices L3 family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrHtAssistInit ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 L3CacheParamRegister; - UINT32 PfCtrlRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = L3_CACHE_PARAM_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &L3CacheParamRegister, StdHeader); - ((L3_CACHE_PARAM_REGISTER *) &L3CacheParamRegister)->L3TagInit = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &L3CacheParamRegister, StdHeader); - do { - LibAmdPciRead (AccessWidth32, PciAddress, &L3CacheParamRegister, StdHeader); - } while (((L3_CACHE_PARAM_REGISTER *) &L3CacheParamRegister)->L3TagInit != 0); - - PciAddress.Address.Register = PROBE_FILTER_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader); - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFWayHashEn = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFLoIndexHashEn = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFWayNum = 2; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheEn = 0xF; - if ((L3CacheParamRegister & 0xFFFF) == L3Cache8_0M) { - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize0 = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize1 = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize2 = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize3 = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFMode = 3; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl = 2; - } else { - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize0 = 0; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize1 = 0; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize2 = 0; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize3 = 0; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFMode = 2; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl = 0; - } - LibAmdPciWrite (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader); - - do { - LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader); - } while (((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFInitDone != 1); - IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable the ATM Mode feature. - * - * @param[in] L3FeatureServices L3 feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrAtmModeInit ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - PciAddress.Address.Function = FUNC_0; - PciAddress.Address.Register = LTC_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((LTC_REGISTER *) &LocalPciRegister)->ATMModeEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = L3_CONTROL_1_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((L3_CONTROL_1_REGISTER *) &LocalPciRegister)->L3ATMModeEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Save the current settings of the scrubbers, and disabled them. - * - * @param[in] L3FeatureServices L3 feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] ScrubSettings Location to store current L3 scrubber settings. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrGetL3ScrubCtrl ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 ScrubCtrl; - UINT32 ScrubAddr; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - - ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader); - - PciAddress.Address.Register = SCRUB_RATE_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader); - - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub = - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub; - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub = - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub; - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect = - ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn; - - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0; - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0; - ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader); - PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG; - LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Restore the initial settings for the scrubbers. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] ScrubSettings Location to store current L3 scrubber settings. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrSetL3ScrubCtrl ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - - ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = SCRUB_RATE_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->DramScrub = - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub; - ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->L3Scrub = - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &LocalPciRegister)->ScrubReDirEn = - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Set MSR bits required for L3 feature support on each core. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] HtAssistEnabled Indicates whether Ht Assist is enabled. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrHookDisableCache ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN BOOLEAN HtAssistEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - // This bit is set only if Probe Filter is enabled. - if (HtAssistEnabled) { - LibAmdMsrRead (MSR_BU_CFG2, &LocalMsrRegister, StdHeader); - LocalMsrRegister |= BIT42; - LibAmdMsrWrite (MSR_BU_CFG2, &LocalMsrRegister, StdHeader); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the input CPU is running in the optimal configuration. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HT Assist is running sub-optimally. - * @retval FALSE HT Assist is running optimally. - * - */ -BOOLEAN -F15OrIsNonOptimalConfig ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsNonOptimal; - BOOLEAN IsMemoryPresent; - UINT32 Module; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - IsNonOptimal = FALSE; - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - IsMemoryPresent = FALSE; - PciAddress.Address.Function = FUNC_2; - PciAddress.Address.Register = DRAM_CFG_HI_REG0; - - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) { - IsMemoryPresent = TRUE; - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 0x0a) { - IsNonOptimal = TRUE; - break; - } - } - - PciAddress.Address.Register = DRAM_CFG_HI_REG1; - - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) { - IsMemoryPresent = TRUE; - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 0x0a) { - IsNonOptimal = TRUE; - break; - } - } - if (!IsMemoryPresent) { - IsNonOptimal = TRUE; - break; - } - } - } - return IsNonOptimal; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the input CPU supports HT Assist. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HT Assist is supported. - * @retval FALSE HT Assist cannot be enabled. - * - */ -BOOLEAN -STATIC -F15OrIsHtAssistSupported ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsSupported; - UINT32 CpuCount; - AP_MAILBOXES ApMailboxes; - - IsSupported = FALSE; - - if (PlatformConfig->PlatformProfile.UseHtAssist) { - CpuCount = GetNumberOfProcessors (StdHeader); - ASSERT (CpuCount != 0); - - if (CpuCount == 1) { - GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); - if (ApMailboxes.ApMailInfo.Fields.ModuleType != 0) { - IsSupported = TRUE; - } - } else if (CpuCount > 1) { - IsSupported = TRUE; - } - } - return IsSupported; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the input CPU supports ATM Mode. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE ATM Mode is supported. - * @retval FALSE ATM Mode cannot be enabled. - * - */ -BOOLEAN -STATIC -F15OrIsAtmModeSupported ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsSupported; - - IsSupported = TRUE; - - if (!PlatformConfig->PlatformProfile.UseAtmMode) { - IsSupported = FALSE; - } - return IsSupported; -} - -CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features = -{ - 0, - F15OrIsL3FeatureSupported, - F15OrGetL3ScrubCtrl, - F15OrSetL3ScrubCtrl, - (PF_L3_FEATURE_BEFORE_INIT) CommonVoid, - (PF_L3_FEATURE_AFTER_INIT) CommonVoid, - F15OrHookDisableCache, - (PF_L3_FEATURE_ENABLE_CACHE) CommonVoid, - F15OrIsHtAssistSupported, - F15OrHtAssistInit, - F15OrIsNonOptimalConfig, - F15OrIsAtmModeSupported, - F15OrAtmModeInit, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c deleted file mode 100644 index 158cd8011d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Logical ID Table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF15OrLogicalIdAndRev ( - OUT CONST CPU_LOGICAL_ID_XLAT **OrIdPtr, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF15OrLogicalIdAndRevArray[] = -{ - { - 0x6012, - AMD_F15_OR_B2 - }, - { - 0x6011, - AMD_F15_OR_B1 - }, - { - 0x6010, - AMD_F15_OR_B0 - }, - { - 0x6001, - AMD_F15_OR_A1 - }, - { - 0x6000, - AMD_F15_OR_A0 - } -}; - -VOID -GetF15OrLogicalIdAndRev ( - OUT CONST CPU_LOGICAL_ID_XLAT **OrIdPtr, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = (sizeof (CpuF15OrLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); - *OrIdPtr = CpuF15OrLogicalIdAndRevArray; - *LogicalFamily = AMD_FAMILY_15_OR; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c deleted file mode 100644 index c2d8bb9a59..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c +++ /dev/null @@ -1,234 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Low Power P-state Initialization - * - * Enables Low Power P-state. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 54780 $ @e \$Date: 2011-06-12 21:25:20 -0600 (Sun, 12 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "CommonReturns.h" -#include "cpuLowPwrPstate.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORLOWPWRPSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * This routine will be run by every cores for enabling low power Pstate. - * - * This function must be run after P-states initialization and before creating ACPI objects - * - * @param[in] LowPwrPstateServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15OrInitializeLowPwrPstate ( - IN LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 OriginalPstate; - UINT8 PstateMaxVal; - UINT8 CurPstateLimit; - UINT8 PstateToWaitFor; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 PciData; - UINT64 LocalMsrRegister; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PCI_ADDR PciAddress; - PCI_ADDR IntNode0PciAddress; - AGESA_STATUS IgnoredSts; - - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - FamilySpecificServices = NULL; - OriginalPstate = 0; - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL); - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - - // Step 1 --- Read MSR_C001_0063[CurPstate] and store the value in OriginalPstate - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - OriginalPstate = (UINT8) ((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate; - - // Step 2 --- Write 0 to MSR_C001_0062[PstateCmd] - LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) 0; - LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - - // Step 3 --- Wait for MSR_C001_0063[CurPstate] == MSR_C001_0061[CurPstateLimit] - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - CurPstateLimit = (UINT8) ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->CurPstateLimit; - do { - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) CurPstateLimit); - - // Step 4 --- Copy MSR_C001_00[6B:64] pointed to by F3xDC[PstateMaxVal] to MSR_C001_00[6B:64] - // pointed to by F3xDC[PstateMaxVal]+1 - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - PstateMaxVal = (UINT8) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciData)->PstateMaxVal; - // In case that F3xDC[PstateMaxVal] was increased by step 5 during the first time of running this function. - // Get the real PstateMaxVal by checking C001_00[6B:64][PsEnable] - while (PstateMaxVal != 0) { - LibAmdMsrRead ((PS_REG_BASE + PstateMaxVal), &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - break; - } - PstateMaxVal--; - } - - LibAmdMsrRead ((PS_REG_BASE + PstateMaxVal), &LocalMsrRegister, StdHeader); - LibAmdMsrWrite ((PS_REG_BASE + PstateMaxVal + 1), &LocalMsrRegister, StdHeader); - - // Step 5 --- Increment the value in F3xDC[PstateMaxVal] by 1 - PstateMaxVal++; - if (Core == 0) { - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciData)->PstateMaxVal = PstateMaxVal; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, 0, PciData, StdHeader); - } - - // Step 6 --- Write 100b to CpuFid from MSR_C001_00[6B:64] indexed by F3xDC[PstateMaxVal] - // Step 7 --- Write 10b to CpuDid from MSR_C001_00[6B:64] indexed by F3xDC[PstateMaxVal] - // Step 8 --- Write 0b to PstateEn from MSR_C001_00[6B:64] indexed by F3xDC[PstateMaxVal] - LibAmdMsrRead ((PS_REG_BASE + PstateMaxVal), &LocalMsrRegister, StdHeader); - ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid = 4; - ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid = 2; - ((PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 0; - LibAmdMsrWrite ((PS_REG_BASE + PstateMaxVal), &LocalMsrRegister, StdHeader); - - // Step 9 --- If F3x64[HtcTmpLmt] == 0, write 7Fh to F3x64[HtcTmpLmt] - // Step 10 --- Write 1b to F3x64[HtcEn] - GetPciAddress (StdHeader, Socket, 0, &IntNode0PciAddress, &IgnoredSts); - if (Core == 0) { - IntNode0PciAddress.Address.Function = FUNC_3; - IntNode0PciAddress.Address.Register = HTC_REG; - LibAmdPciRead (AccessWidth32, IntNode0PciAddress, &PciData, StdHeader); - if (((HTC_REGISTER *) &PciData)->HtcTmpLmt == 0) { - ((HTC_REGISTER *) &PciData)->HtcTmpLmt = 0x7F; - } - ((HTC_REGISTER *) &PciData)->HtcEn = 1; - IDS_OPTION_HOOK (IDS_HTC_CTRL, &PciData, StdHeader); - LibAmdPciWrite (AccessWidth32, IntNode0PciAddress, &PciData, StdHeader); - } - - // Step 11 --- Write OriginalPstate to MSR_C001_0062[PstateCmd] - LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) OriginalPstate; - LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - - // Step 12 --- If (MSR_C001_0061[CurPstateLimit] > OriginalPstate) - // Wait for (MSR_C001_0063[CurPstate] == MSR_C001_0061[CurPstateLimit]) - // Else - // Wait for (MSR_C001_0063[CurPstate] == OriginalPstate - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - CurPstateLimit = (UINT8) ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->CurPstateLimit; - PstateToWaitFor = (CurPstateLimit > OriginalPstate) ? CurPstateLimit : OriginalPstate; - do { - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) PstateToWaitFor); - - // Step 13 --- Write F3x64[HtcPstateLimit] and F3xA8[PopDownPstate] with the value from - // F3xDC[PstateMaxVal] and exit the sequence - if (Core == 0) { - ((HTC_REGISTER *) &PciData)->HtcPstateLimit = PstateMaxVal; - LibAmdPciWrite (AccessWidth32, IntNode0PciAddress, &PciData, StdHeader); - PciAddress.Address.Register = POPUP_PSTATE_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - ((POPUP_PSTATE_REGISTER *) &PciData)->PopDownPstate = PstateMaxVal; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, 0, PciData, StdHeader); - } - } - return AGESA_SUCCESS; -} - - -CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport = -{ - 0, - (PF_LOW_PWR_PSTATE_IS_SUPPORTED) CommonReturnTrue, - F15OrInitializeLowPwrPstate -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c deleted file mode 100644 index f878acd0d6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c +++ /dev/null @@ -1,2673 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F15Or Microcode patch. - * - * F15Or Microcode Patch rev 06000425 for 6010 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x15/Or - * @e \$Revision: 53746 $ @e \$Date: 2011-05-24 23:08:53 -0600 (Tue, 24 May 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypted Patch code 06000425 for 6010 and equivalent -CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000425 [IDS_PAD_4K] = -{ - 0x11, - 0x20, - 0x08, - 0x04, - 0x25, - 0x04, - 0x00, - 0x06, - 0x02, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x10, - 0x60, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x55, - 0xbf, - 0xbd, - 0x55, - 0xea, - 0x96, - 0xd6, - 0xed, - 0x1a, - 0x82, - 0xda, - 0x4a, - 0xdc, - 0xc0, - 0x8a, - 0x21, - 0x02, - 0x4c, - 0x0f, - 0x68, - 0xc4, - 0x31, - 0x74, - 0xa8, - 0x32, - 0xfc, - 0xb3, - 0xad, - 0xbc, - 0x51, - 0x53, - 0x89, - 0x65, - 0xc5, - 0x49, - 0x28, - 0x9f, - 0x9c, - 0xe4, - 0xb8, - 0x90, - 0x02, - 0x27, - 0x30, - 0x5f, - 0x19, - 0xba, - 0x72, - 0x0b, - 0x8c, - 0x78, - 0xcb, - 0x2e, - 0x00, - 0x7c, - 0x2b, - 0x9b, - 0x0a, - 0xa2, - 0xd2, - 0x20, - 0x8b, - 0x6c, - 0xc0, - 0xce, - 0xae, - 0x0e, - 0x8f, - 0xe7, - 0xaf, - 0xc7, - 0x5d, - 0xf9, - 0xcb, - 0x35, - 0x79, - 0xc0, - 0x1e, - 0x33, - 0x5f, - 0x05, - 0x95, - 0x0c, - 0x6f, - 0x43, - 0xc7, - 0x85, - 0x52, - 0xd9, - 0x06, - 0x58, - 0xec, - 0xe7, - 0xdb, - 0x6d, - 0xba, - 0xb4, - 0x5b, - 0x32, - 0xeb, - 0xe4, - 0xb2, - 0xd5, - 0x77, - 0x1c, - 0xe6, - 0x84, - 0xaf, - 0x2c, - 0x12, - 0x18, - 0xf7, - 0x3c, - 0xbf, - 0xa8, - 0x90, - 0xcb, - 0x40, - 0x46, - 0xee, - 0x48, - 0x0c, - 0x53, - 0x80, - 0x9a, - 0x94, - 0x4d, - 0x73, - 0x3e, - 0x2f, - 0x98, - 0xc0, - 0x25, - 0x75, - 0xbd, - 0xe8, - 0x99, - 0x38, - 0xad, - 0xfa, - 0xda, - 0xcf, - 0x3f, - 0xe5, - 0x4b, - 0x38, - 0x76, - 0x3b, - 0xe5, - 0xa2, - 0xef, - 0x38, - 0x11, - 0xbd, - 0x8d, - 0x84, - 0x75, - 0x88, - 0x72, - 0xdd, - 0xd4, - 0xcd, - 0x85, - 0xcd, - 0xd1, - 0xc6, - 0xae, - 0xd1, - 0xc2, - 0xfa, - 0xb1, - 0xc4, - 0xc2, - 0xc9, - 0x35, - 0xc4, - 0xc1, - 0x3a, - 0xbe, - 0xcc, - 0x08, - 0x94, - 0xba, - 0x52, - 0x98, - 0xd6, - 0xd4, - 0x70, - 0x84, - 0x48, - 0x3b, - 0x9d, - 0xfd, - 0x24, - 0x81, - 0x50, - 0xbf, - 0xe2, - 0x2b, - 0xf5, - 0x5f, - 0x3b, - 0x99, - 0x76, - 0x98, - 0xc2, - 0xf2, - 0x36, - 0x1c, - 0x64, - 0xea, - 0xdc, - 0xd7, - 0x10, - 0x0f, - 0x76, - 0xcc, - 0x2c, - 0x9e, - 0x23, - 0x45, - 0x8b, - 0x0f, - 0x4e, - 0x4b, - 0x34, - 0x89, - 0x7d, - 0x5b, - 0x21, - 0x8a, - 0x25, - 0x5b, - 0x69, - 0xe3, - 0xde, - 0xb4, - 0xa9, - 0xf7, - 0x48, - 0x9a, - 0xea, - 0x40, - 0x3c, - 0x9c, - 0x41, - 0x8f, - 0x69, - 0x3c, - 0x10, - 0x6e, - 0xf8, - 0x11, - 0x7c, - 0x73, - 0xe9, - 0x96, - 0xed, - 0x90, - 0x9e, - 0x07, - 0x45, - 0x65, - 0x6b, - 0x68, - 0x5d, - 0x9d, - 0x72, - 0xdb, - 0xb2, - 0xbc, - 0x81, - 0x65, - 0xeb, - 0x84, - 0x33, - 0xdc, - 0xe9, - 0x0f, - 0xd5, - 0x0e, - 0xc8, - 0x5e, - 0x14, - 0x80, - 0x64, - 0x0b, - 0x9e, - 0x46, - 0xde, - 0xbe, - 0x9e, - 0x12, - 0xac, - 0x50, - 0xc4, - 0x33, - 0xce, - 0xf7, - 0xba, - 0xc7, - 0xdf, - 0x43, - 0x09, - 0x9b, - 0xa3, - 0x21, - 0xc5, - 0xe0, - 0x48, - 0xe6, - 0x19, - 0xd8, - 0xa6, - 0x6f, - 0x29, - 0xb3, - 0x0e, - 0xc4, - 0xc6, - 0xe6, - 0xdd, - 0x96, - 0xab, - 0x54, - 0xb9, - 0x80, - 0x73, - 0x61, - 0xe6, - 0x85, - 0x9b, - 0xe5, - 0x00, - 0xfa, - 0xe8, - 0x04, - 0xe5, - 0x33, - 0xfe, - 0x7e, - 0xae, - 0xe7, - 0x55, - 0x53, - 0xe4, - 0x63, - 0x6a, - 0xfa, - 0x76, - 0x9e, - 0x28, - 0x88, - 0xb8, - 0xc6, - 0x75, - 0x4c, - 0xa0, - 0x9f, - 0x01, - 0xf9, - 0x9e, - 0x89, - 0xf6, - 0xce, - 0x91, - 0xbf, - 0x4e, - 0xfe, - 0xbd, - 0x52, - 0xea, - 0xfe, - 0x06, - 0xc5, - 0xad, - 0xcf, - 0xb8, - 0xa0, - 0xec, - 0x78, - 0x4b, - 0xec, - 0x3b, - 0x80, - 0xf4, - 0x84, - 0xbe, - 0x69, - 0x5f, - 0x5e, - 0x7a, - 0x13, - 0x89, - 0x95, - 0x91, - 0x07, - 0x56, - 0xdb, - 0x5d, - 0xfa, - 0x10, - 0xfc, - 0x5d, - 0x99, - 0xb5, - 0xe8, - 0x59, - 0x96, - 0x15, - 0x56, - 0xe6, - 0x8d, - 0x06, - 0x7f, - 0x5e, - 0x1b, - 0xc6, - 0x4c, - 0xa6, - 0x73, - 0x28, - 0x6a, - 0xa5, - 0xf3, - 0xc1, - 0x45, - 0x86, - 0x8d, - 0x4a, - 0x88, - 0x94, - 0x4d, - 0x7f, - 0x15, - 0xe8, - 0x9f, - 0x19, - 0x25, - 0x86, - 0xdc, - 0x6b, - 0xbd, - 0x5d, - 0xe0, - 0x76, - 0xa5, - 0x2e, - 0x58, - 0xc2, - 0xb3, - 0xed, - 0x2d, - 0x7f, - 0xb5, - 0x83, - 0xf1, - 0xd5, - 0x79, - 0xb5, - 0x5b, - 0x55, - 0x94, - 0x18, - 0x44, - 0x43, - 0x42, - 0xe4, - 0xe5, - 0xbf, - 0x59, - 0xa2, - 0x33, - 0x05, - 0x16, - 0x2d, - 0x9e, - 0x01, - 0x12, - 0xd3, - 0x3d, - 0x29, - 0x97, - 0xaa, - 0x9c, - 0x63, - 0x17, - 0x5c, - 0x39, - 0xef, - 0xe9, - 0xa5, - 0x70, - 0x24, - 0xb7, - 0x31, - 0x97, - 0xab, - 0x18, - 0xae, - 0x9d, - 0xa0, - 0x12, - 0xde, - 0x36, - 0x7e, - 0x1d, - 0x91, - 0xbf, - 0x77, - 0x14, - 0xdf, - 0x6b, - 0xc6, - 0xb6, - 0x11, - 0x04, - 0x25, - 0xef, - 0x52, - 0x0b, - 0x42, - 0xff, - 0xc4, - 0x6b, - 0x19, - 0x44, - 0xcd, - 0xbd, - 0x38, - 0x02, - 0xa2, - 0x47, - 0x8f, - 0x95, - 0x37, - 0x9d, - 0x5b, - 0x32, - 0x37, - 0x08, - 0x4e, - 0x03, - 0x5f, - 0x18, - 0x03, - 0xa9, - 0xbe, - 0xe1, - 0x70, - 0x44, - 0xe0, - 0xc7, - 0xc6, - 0x76, - 0x19, - 0xe5, - 0x08, - 0x82, - 0xb2, - 0x07, - 0x96, - 0xa7, - 0xb5, - 0x07, - 0xfd, - 0x67, - 0x46, - 0x9d, - 0x87, - 0x77, - 0x9b, - 0xd1, - 0xaa, - 0x4d, - 0xc3, - 0x12, - 0x22, - 0xfd, - 0x61, - 0xee, - 0xe1, - 0xb6, - 0x71, - 0x83, - 0xc9, - 0x0d, - 0x57, - 0xf1, - 0xed, - 0xc2, - 0xdf, - 0xeb, - 0x3a, - 0x2a, - 0xf6, - 0xb7, - 0x24, - 0xac, - 0x1b, - 0x89, - 0xc8, - 0xdc, - 0x69, - 0x15, - 0xc4, - 0x20, - 0xe9, - 0x43, - 0x32, - 0xde, - 0xde, - 0xa8, - 0x81, - 0x1c, - 0x10, - 0x8f, - 0xf8, - 0x04, - 0xca, - 0x1f, - 0x98, - 0x13, - 0x9b, - 0xa5, - 0xa6, - 0x02, - 0x36, - 0xc7, - 0xd3, - 0x6c, - 0x49, - 0x60, - 0x37, - 0x25, - 0x9a, - 0xe0, - 0xea, - 0xf4, - 0xfd, - 0x93, - 0xdb, - 0xd8, - 0x78, - 0xb7, - 0xfe, - 0x40, - 0x74, - 0x99, - 0x80, - 0x9a, - 0x90, - 0x83, - 0x28, - 0x6d, - 0x01, - 0x61, - 0xd4, - 0x4f, - 0x1d, - 0x89, - 0x6e, - 0x95, - 0x77, - 0x24, - 0xd2, - 0xf1, - 0xbb, - 0x6f, - 0xd9, - 0xad, - 0x0f, - 0xde, - 0x63, - 0xf7, - 0xfa, - 0x22, - 0x6b, - 0x91, - 0x1e, - 0xf9, - 0xf9, - 0x01, - 0x51, - 0xde, - 0x79, - 0xec, - 0x9f, - 0x3f, - 0x28, - 0xdf, - 0x82, - 0x84, - 0xbd, - 0xa3, - 0x5e, - 0xb2, - 0xf8, - 0x8b, - 0x75, - 0xdc, - 0xf3, - 0x88, - 0x78, - 0x50, - 0xb6, - 0x87, - 0xa7, - 0x37, - 0x95, - 0xcb, - 0xb8, - 0xb3, - 0xa4, - 0x58, - 0xe2, - 0xf7, - 0x2c, - 0x95, - 0x9c, - 0x69, - 0x2e, - 0xe1, - 0xbd, - 0xc4, - 0x87, - 0x19, - 0x45, - 0x9b, - 0x3f, - 0x7e, - 0x40, - 0x8b, - 0xd4, - 0x40, - 0x1b, - 0x28, - 0xb2, - 0x61, - 0x6d, - 0x96, - 0x6d, - 0x56, - 0xae, - 0xec, - 0x06, - 0xe6, - 0x61, - 0x06, - 0x3a, - 0x0f, - 0x10, - 0x49, - 0xbd, - 0xd0, - 0x8f, - 0xd9, - 0xd3, - 0xa0, - 0x3c, - 0x1d, - 0x0d, - 0xef, - 0x64, - 0xb5, - 0xd4, - 0x08, - 0xa6, - 0x37, - 0x55, - 0x53, - 0xaa, - 0x98, - 0x94, - 0x41, - 0x7d, - 0x48, - 0x13, - 0x36, - 0xaa, - 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0x5f, - 0x24, - 0x7c, - 0xe8, - 0x9b, - 0x23, - 0x58, - 0xd1, - 0x10, - 0x45, - 0x19, - 0xce, - 0x32, - 0x7a, - 0x1e, - 0x8a, - 0xba, - 0x58, - 0x55, - 0x2a, - 0x46, - 0x4e, - 0xcf, - 0x82, - 0x5b, - 0xfe, - 0xed, - 0x83, - 0xbc, - 0xf7, - 0xf4, - 0x43, - 0x01, - 0x6d, - 0xaa, - 0x22, - 0xf3, - 0x1e, - 0x2a, - 0x4b, - 0x26, - 0xc7, - 0x3f, - 0xd7, - 0xe8, - 0xdc, - 0x2d, - 0x54, - 0xd1, - 0x40, - 0x5e, - 0xb2, - 0x89, - 0x16, - 0xb7, - 0xc8, - 0x6c, - 0x4e, - 0xeb, - 0x02, - 0x05, - 0xd3, - 0x83, - 0x98, - 0x69, - 0x2e, - 0x0a, - 0x50, - 0x51, - 0xf7, - 0xbc, - 0xcd, - 0x39, - 0xa3, - 0x15, - 0x2d, - 0xe9, - 0x9e, - 0xc4, - 0x1d, - 0x0d, - 0x36, - 0xdd, - 0xe2, - 0x7a, - 0x85, - 0x26, - 0xe3, - 0xcc, - 0x5a, - 0xc7, - 0xe4, - 0x8a, - 0xdb, - 0x28, - 0x51, - 0xb0, - 0xb2, - 0x7b, - 0x26, - 0xf8, - 0xb7, - 0x65, - 0x7e, - 0xd1, - 0x8b, - 0x39, - 0x52, - 0x7c, - 0x68, - 0x15, - 0x59, - 0xea, - 0x99, - 0xe9, - 0x3d, - 0x67, - 0xbf, - 0x5e, - 0x28, - 0xa7, - 0xa0, - 0xc2, - 0x75, - 0x14, - 0x76, - 0x97, - 0x62, - 0x52, - 0xe7, - 0xe7, - 0x27, - 0xde, - 0x8e, - 0x45, - 0x84, - 0xce, - 0x0f, - 0xad, - 0xc3, - 0x02, - 0x37, - 0x60, - 0xf5, - 0xb1, - 0x79, - 0x01, - 0x3c, - 0x9e, - 0xb8, - 0x50, - 0x87, - 0xb6, - 0x6f, - 0xb2, - 0x4d, - 0x99, - 0xee, - 0xea, - 0x2c, - 0xad, - 0x1b, - 0x62, - 0x5f, - 0x47, - 0xfb, - 0xf2, - 0xd8, - 0x0a, - 0x21, - 0x05, - 0x94, - 0x5d, - 0xc1, - 0xc3, - 0x3b, - 0x71, - 0xe7, - 0xa8, - 0xd4, - 0x61, - 0x80, - 0xf1, - 0x60, - 0xa2, - 0x99, - 0x0f, - 0xe0, - 0x0a, - 0xd7, - 0xbc, - 0x23, - 0x01, - 0xa6, - 0xf3, - 0xe7, - 0xa9, - 0xd1, - 0x66, - 0xd5, - 0x9e, - 0xd4, - 0xb9, - 0x61, - 0xe1, - 0xa4, - 0x47, - 0xae, - 0x12, - 0x0e, - 0x60, - 0x34, - 0x56, - 0x2d, - 0x28, - 0x6f, - 0x15, - 0xcd, - 0x13, - 0x8d, - 0xd5, - 0x9f, - 0xf7, - 0xf7, - 0x7f, - 0x4c, - 0x59, - 0xb8, - 0x5f, - 0x10, - 0x97, - 0xb6, - 0xd7, - 0x68, - 0x46, - 0x49, - 0xee, - 0xad, - 0x08, - 0x75, - 0x25, - 0xff, - 0x90, - 0x18, - 0xc6, - 0xaa, - 0x79, - 0x7e, - 0xd7, - 0x4d, - 0x83, - 0x1d, - 0x97, - 0x13, - 0x2e, - 0xef, - 0x4f, - 0x76, - 0x26, - 0xea, - 0x22, - 0x06, - 0xc5, - 0xd9, - 0xc0, - 0x62, - 0xce, - 0x68, - 0xde, - 0xc8, - 0xf3, - 0x2f, - 0xb7, - 0xae, - 0xdb, - 0xbc, - 0x37, - 0x8e, - 0x7c, - 0x3f, -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c deleted file mode 100644 index 918ef27412..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c +++ /dev/null @@ -1,2674 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F15Or Microcode patch. - * - * F15Or Microcode Patch rev 0600050D for 6011 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55872 $ @e \$Date: 2011-07-01 09:09:22 -0600 (Fri, 01 Jul 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypt Patch code 0600050D for 6011 and equivalent - -CONST UINT8 ROMDATA CpuF15OrMicrocodePatch0600050D_Enc [IDS_PAD_4K] = -{ - 0x11, - 0x20, - 0x27, - 0x06, - 0x0d, - 0x05, - 0x00, - 0x06, - 0x02, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x11, - 0x60, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x5b, - 0x94, - 0xa0, - 0x0d, - 0x78, - 0xaf, - 0xb3, - 0xa7, - 0x4b, - 0xbb, - 0x6b, - 0x18, - 0x7e, - 0xe0, - 0x91, - 0x2a, - 0x6e, - 0xb5, - 0x40, - 0x6e, - 0x39, - 0x62, - 0x3b, - 0x83, - 0xe9, - 0x47, - 0x50, - 0xba, - 0xb5, - 0x7d, - 0x40, - 0x26, - 0xf6, - 0x46, - 0xbc, - 0x45, - 0x3d, - 0xd6, - 0xa3, - 0xa8, - 0x94, - 0x33, - 0xb9, - 0xd3, - 0xa0, - 0xb5, - 0x50, - 0xe2, - 0x6d, - 0x90, - 0x1e, - 0xc9, - 0x30, - 0x91, - 0x70, - 0x3d, - 0xef, - 0x48, - 0xc1, - 0xc5, - 0x21, - 0x73, - 0x94, - 0x26, - 0xce, - 0x40, - 0xb6, - 0x24, - 0x2c, - 0x33, - 0xf9, - 0x64, - 0x2f, - 0xf7, - 0x6f, - 0xf0, - 0x38, - 0x02, - 0x2e, - 0x4d, - 0xfd, - 0x82, - 0x64, - 0x50, - 0x6d, - 0xf0, - 0xb5, - 0xed, - 0xff, - 0xb1, - 0xb9, - 0x8a, - 0xbc, - 0xab, - 0xf9, - 0x2c, - 0x9c, - 0x99, - 0x36, - 0x79, - 0x07, - 0x80, - 0xf8, - 0xa7, - 0x68, - 0xdd, - 0x06, - 0xbe, - 0xd7, - 0xa3, - 0xe0, - 0x74, - 0x25, - 0x9f, - 0xe5, - 0x9d, - 0xff, - 0xee, - 0x08, - 0x44, - 0x78, - 0x16, - 0x3f, - 0xbe, - 0xa9, - 0xf2, - 0xb1, - 0xd1, - 0x01, - 0x20, - 0x8f, - 0xa7, - 0x82, - 0x75, - 0x96, - 0xed, - 0xbe, - 0x6f, - 0xf4, - 0x76, - 0x4b, - 0xc5, - 0x87, - 0x72, - 0xde, - 0x21, - 0x9f, - 0x6c, - 0xa3, - 0x9f, - 0x37, - 0x9a, - 0xf0, - 0xbb, - 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0x65, - 0x6b, - 0x97, - 0x2c, - 0xd6, - 0x71, - 0xd8, - 0xeb, - 0xbb, - 0x77, - 0x7f, - 0xfe, - 0x7c, - 0xc9, - 0x95, - 0xbd, - 0xe0, - 0x0d, - 0x7c, - 0xea, - 0x13, - 0x8d, - 0xb4, - 0xbd, - 0x9f, - 0xa6, - 0x70, - 0x9a, - 0x72, - 0x67, - 0x21, - 0xe5, - 0xf5, - 0xb9, - 0x92, - 0x18, - 0xe6, - 0xd2, - 0x48, - 0xfb, - 0x9b, - 0xae, - 0xd9, - 0x2b, - 0x78, - 0x42, - 0xff, - 0x84, - 0x51, - 0x89, - 0x5c, - 0xab, - 0x46, - 0x8c, - 0x77, - 0x11, - 0x45, - 0x43, - 0x7d, - 0x17, - 0x2c, - 0x10, - 0xf6, - 0x81, - 0x28, - 0x1b, - 0xc4, - 0x4b, - 0x21, - 0xe1, - 0x75, - 0x22, - 0x80, - 0x74, - 0xe7, - 0x2b, - 0x7b, - 0x09, - 0xf6, - 0x64, - 0x05, - 0x24, - 0x87, - 0x4a, - 0xe5, - 0xa5, - 0x94, - 0x96, - 0x1d, - 0x16, - 0x2d, - 0xec, - 0x07, - 0x55, - 0x5e, - 0x0c, - 0xd5, - 0x89, - 0xb1, - 0xd5, - 0x85, - 0xe9, - 0x9d, - 0x85, - 0x68, - 0x3a, - 0x9d, - 0xc0, - 0x30, - 0xc0, - 0xcf, - 0x44, - 0xe0, - 0x3a, - 0x7f, - 0x4c, - 0xc7, - 0x9c, - 0x3e, - 0x1a, - 0x0f, - 0xfc, - 0x3e, - 0x46, - 0xd3, - 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0x02, - 0x2a, - 0x37, - 0xa9, - 0x65, - 0x53, - 0xd5, - 0x1b, - 0x09, - 0x09, - 0xc9, - 0xe1, - 0x3e, - 0x38, - 0xf2, - 0x17, - 0xba, - 0x99, - 0x65, - 0x61, - 0xb2, - 0xfd, - 0xbf, - 0xc4, - 0x25, - 0xf0, - 0x98, - 0xec, - 0xab, - 0xad, - 0x4d, -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c deleted file mode 100644 index 8c011ad785..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c +++ /dev/null @@ -1,2673 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F15Or Microcode patch. - * - * F15Or Microcode Patch rev 06000624 for 6012 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 60770 $ @e \$Date: 2011-10-21 15:51:10 -0600 (Fri, 21 Oct 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypt Patch code 06000624 for 6012 and equivalent - -CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000624_Enc [IDS_PAD_4K] = -{ - 0x11, - 0x20, - 0x21, - 0x10, - 0x24, - 0x06, - 0x00, - 0x06, - 0x02, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x12, - 0x60, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x53, - 0x66, - 0x89, - 0xc4, - 0x38, - 0x90, - 0x15, - 0xbf, - 0xec, - 0xee, - 0x70, - 0xc6, - 0xdb, - 0x18, - 0x66, - 0x84, - 0xa6, - 0x2f, - 0x3a, - 0xe5, - 0x2e, - 0x91, - 0x6c, - 0x46, - 0x2f, - 0x1a, - 0xdb, - 0x02, - 0xdc, - 0x29, - 0x17, - 0xbd, - 0x66, - 0x14, - 0x13, - 0x10, - 0xba, - 0x9a, - 0xa7, - 0x1d, - 0x79, - 0x73, - 0x29, - 0x07, - 0x12, - 0x9d, - 0xaf, - 0x3d, - 0xdd, - 0x7d, - 0xa5, - 0x44, - 0x88, - 0x88, - 0x5b, - 0x0b, - 0xfd, - 0x07, - 0xd1, - 0x94, - 0x4f, - 0xdf, - 0xa2, - 0x0c, - 0xa4, - 0x2d, - 0x61, - 0x77, - 0x3d, - 0x0b, - 0x37, - 0xb8, - 0x21, - 0x82, - 0xe4, - 0xdb, - 0x21, - 0xc7, - 0x10, - 0x67, - 0x4f, - 0x68, - 0x90, - 0xec, - 0x65, - 0xe5, - 0x0e, - 0x49, - 0x91, - 0x85, - 0xaa, - 0x07, - 0x98, - 0xbe, - 0x64, - 0xaf, - 0x48, - 0xb7, - 0x17, - 0x5f, - 0xcf, - 0x34, - 0x4b, - 0x2f, - 0x9f, - 0x9c, - 0xf0, - 0xcd, - 0xfa, - 0xb2, - 0x29, - 0x92, - 0xa0, - 0xc8, - 0x80, - 0xcf, - 0x03, - 0x69, - 0x8a, - 0xb0, - 0x70, - 0x8d, - 0x1a, - 0x9c, - 0xab, - 0xe9, - 0x0b, - 0x69, - 0x3d, - 0xc5, - 0x73, - 0x40, - 0xab, - 0x2c, - 0x50, - 0xeb, - 0x7c, - 0x66, - 0x4b, - 0x36, - 0x71, - 0x18, - 0x38, - 0xf3, - 0x02, - 0x87, - 0x89, - 0x92, - 0xc6, - 0xae, - 0x04, - 0x29, - 0xa9, - 0x26, - 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0x5c, - 0x9a, - 0x07, - 0xf1, - 0xec, - 0x96, - 0x9c, - 0xdd, - 0x0c, - 0x8e, - 0xd9, - 0x8a, - 0x81, - 0x5a, - 0xfd, - 0x8b, - 0x9c, - 0x2f, - 0xb3, - 0x29, - 0xd2, - 0x19, - 0x6f, - 0xfd, - 0x04, - 0x6d, - 0x75, - 0x3d, - 0x5e, - 0x4e, - 0x0a, -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c deleted file mode 100644 index 4173492b31..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c +++ /dev/null @@ -1,112 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -extern CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15OrMicroCodePatchArray[]; -extern CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF15OrMicroCodePatchesStruct ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **OrUcodePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns a table containing the appropriate microcode patches. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] OrUcodePtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF15OrMicroCodePatchesStruct ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **OrUcodePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = CpuF15OrNumberOfMicrocodePatches; - *OrUcodePtr = &CpuF15OrMicroCodePatchArray[0]; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c deleted file mode 100644 index f7e148d80b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c +++ /dev/null @@ -1,305 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Message-Based C1e feature support functions. - * - * Provides the functions necessary to initialize the message-based C1e feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 53157 $ @e \$Date: 2011-05-16 13:46:21 -0600 (Mon, 16 May 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuMsgBasedC1e.h" -#include "cpuApicUtilities.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "F15PackageType.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrInitializeMsgBasedC1eOnCore ( - IN VOID *BmStsAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -STATIC -IsDramScrubberEnabled ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Should message-based C1e be enabled - * - * @param[in] MsgBasedC1eServices Pointer to this CPU's Messsage based C1e family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Messsage based C1e is supported. - * - */ -BOOLEAN -STATIC -F15OrIsMsgBasedC1eSupported ( - IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader); - return ((BOOLEAN) ((LogicalId.Revision & AMD_F15_ALL) != 0)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Core 0 task to enable message-based C1e on a family 15h CPU. - * - * @param[in] MsgBasedC1eServices Pointer to this CPU's Messsage based C1e family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15OrInitializeMsgBasedC1e ( - IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 AndMask; - UINT32 Core; - UINT32 Module; - UINT32 OrMask; - UINT32 LocalPciRegister; - UINT32 Socket; - UINT32 PackageType; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { - PackageType = LibAmdGetPackageType (StdHeader); - // Note that this core 0 does NOT have the ability to launch - // any of its cores. Attempting to do so could lead to a system - // hang. - - // Set F3xA0[IdleExitEn] = 1 - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PW_CTL_MISC_REG; - AndMask = 0xFFFFFFFF; - OrMask = 0; - ((POWER_CTRL_MISC_REGISTER *) &OrMask)->IdleExitEn = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xA0 - - // Set F4x128[CstateMsgDis] = 0 - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CSTATE_POLICY_CTRL1_REG; - OrMask = 0; - ((CSTATE_POLICY_CTRL1_REGISTER *) &AndMask)->CstateMsgDis = 0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x128 - - // Read F4x128[CoreCstateMode] - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - AndMask = 0xFFFFFFFF; - OrMask = 0; - // Set D18F3xDC[CacheFlushOnHaltCtl] != 0 - if ((LocalPciRegister & 0x00000001) == 1) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->CacheFlushOnHaltCtl = 7; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC - } else { - // Set F4x118[CacheFlushEn] = 1 or 0 (if AM3r2) - // Set F4x11C[CacheFlushEn] = 1 - PciAddress.Address.Register = CSTATE_CTRL1_REG; - if (PackageType == PACKAGE_TYPE_AM3r2) { - ((CSTATE_CTRL1_REGISTER *) &AndMask)->CacheFlushEnCstAct0 = 0; - } else { - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushEnCstAct0 = 1; - } - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushEnCstAct1 = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x118 - } - - // Set F3xD4[MTC1eEn] = 1 - // Set F3xD4[StutterScrubEn] = 1 if scrubbing is enabled - // Set F3xD4[CacheFlushImmOnAllHalt] = 1 or 0 (if AM3r2) - AndMask = 0xFFFFFFFF; - OrMask = 0; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->StutterScrubEn = 0; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->MTC1eEn = 1; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->CacheFlushImmOnAllHalt = 0; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - - for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC0_REG; - if (IsDramScrubberEnabled (PciAddress, StdHeader)) { - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 1; - } else { - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 0; - } - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LocalPciRegister &= AndMask; - LocalPciRegister |= OrMask; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } - - } else if (EntryPoint == CPU_FEAT_AFTER_PM_INIT) { - // At early, this core 0 can launch its subordinate cores. - TaskPtr.FuncAddress.PfApTaskI = F15OrInitializeMsgBasedC1eOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 1; - TaskPtr.DataTransfer.DataPtr = &PlatformConfig->C1ePlatformData; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable message-based C1e on a family 15h Orochi core. - * - * @param[in] BmStsAddress System I/O address of the bus master status bit. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrInitializeMsgBasedC1eOnCore ( - IN VOID *BmStsAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - LibAmdMsrRead (MSR_INTPEND, &LocalMsrRegister, StdHeader); - ((INTPEND_MSR *) &LocalMsrRegister)->BmStsClrOnHltEn = 1; - ((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsgDis = 0; - ((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsg = 0; - ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress); - LibAmdMsrWrite (MSR_INTPEND, &LocalMsrRegister, StdHeader); - - // Set MSRC001_0015[HltXSpCycEn] = 1 - LibAmdMsrRead (MSR_HWCR, &LocalMsrRegister, StdHeader); - LocalMsrRegister |= BIT12; - LibAmdMsrWrite (MSR_HWCR, &LocalMsrRegister, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the DRAM background scrubbers are enabled or not. - * - * @param[in] PciAddress Address of F15 Orochi socket/module to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Memory scrubbers are enabled on the current node. - * @retval FALSE Memory scrubbers are disabled on the current node. - */ -BOOLEAN -STATIC -IsDramScrubberEnabled ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x58; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - return ((BOOLEAN) ((LocalPciRegister & 0x1F) != 0)); -} - - -CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e = -{ - 0, - F15OrIsMsgBasedC1eSupported, - F15OrInitializeMsgBasedC1e -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c deleted file mode 100644 index b1c09f26e4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c +++ /dev/null @@ -1,234 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi MSR tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 60740 $ @e \$Date: 2011-10-20 19:47:10 -0600 (Thu, 20 Oct 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "F15PackageType.h" -#include "cpuF15OrPowerMgmt.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -F15OrDisUcodeWorkaroundForErratum671 ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15OrMsrRegisters[] = -{ -// M S R T a b l e s -// ---------------------- - -// MSR_MC4_CTL_MASK (0xC0010048) -// bit[10] GartTblWkEn = 1 -// bits[22:19] RtryHtEn = 1111b - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_MC4_CTL_MASK, // MSR Address - 0x0000000000780400, // OR Mask - 0x0000000000780400, // NAND Mask - }} - }, -// MSR 0xC0011000 -// bit[16] = 1, Erratum #608 for all OR revisions - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - 0xC0011000, // MSR Address - 0x0000000000010000, // OR Mask - 0x0000000000010000, // NAND Mask - }} - }, -// MSR_CPUID_EXT_FEATS (0xC0011005) -// bit[56] PerfCtrExtNB = 1 -// bit[55] PerfCtrExtCore = 1 -// bit[51] NodeId = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CPUID_EXT_FEATS, // MSR Address - 0x0188000000000000, // OR Mask - 0x0188000000000000, // NAND Mask - }} - }, -// MSR_OSVW_ID_Length (0xC0010140) -// bit[15:0] = 4 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_OSVW_ID_Length, // MSR Address - 0x0000000000000004, // OR Mask - 0x000000000000FFFF, // NAND Mask - }} - }, -// MSR_IBS_OP_DATA3 (0xC0011037) -// bit[16] IbsDcMabHit = 0 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_IBS_OP_DATA3, // MSR Address - 0x0000000000000000, // OR Mask - 0x0000000000010000, // NAND Mask - }} - } -}; - -// MSRs with Special Programming Requirements Table - -STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15OrAM3MsrWorkarounds[] = -{ - // Disable Microcode workaround for Erratum #671 - { - FamSpecificWorkaround, - { - AMD_FAMILY_15_OR, - AMD_F15_OR_B2 - }, - {AMD_PF_ALL}, - {{ - F15OrDisUcodeWorkaroundForErratum671, - 0x00000000 - }} - }, -}; - - -CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable = { - AllCores, - (sizeof (F15OrMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrMsrRegisters, -}; - -CONST REGISTER_TABLE ROMDATA F15OrAM3MsrWorkaroundTable = { - AllCores, - (sizeof (F15OrAM3MsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrAM3MsrWorkarounds, -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * A Family Specific Workaround method, to disable the microcode workaround for Erratum #671 - * - * \@TableTypeFamSpecificInstances. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config params for library, services. - */ -VOID -F15OrDisUcodeWorkaroundForErratum671 ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrData; - UINT32 PackageType; - - // Is this processor AM3? - PackageType = LibAmdGetPackageType (StdHeader); - - if (PackageType == PACKAGE_TYPE_AM3r2) { - // Apply the enhancement. - LibAmdMsrRead (0xC0011000, &MsrData, StdHeader); - MsrData = (MsrData | BIT17); - LibAmdMsrWrite (0xC0011000, &MsrData, StdHeader); - } -} - - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c deleted file mode 100644 index 0c9290d709..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c +++ /dev/null @@ -1,749 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi PCI tables from Multi-Link BKDG paragraph recommended settings. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 41897 $ @e \$Date: 2010-11-12 12:39:18 +0800 (Fri, 12 Nov 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -#include "F15PackageType.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORMULTILINKPCITABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrMultiLinkPciRegisters[] = -{ - // Function 0 - -// F0x68 - Link Transaction Control -// bit[14:13], BufRelPri = 01h - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL, // CpuRevision rev C or less. - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x00002000, // regData - 0x00006000, // regMask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 3 - // 17:16 NpReqData: 3 - // 15:12 ProbeCmd: 8 - // 11:8 RspCmd: 9 - // 7:5 PReq: 2 - // 4:0 NpReqCmd: 4 -{ - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - HT_HOST_FEAT_COHERENT, // link features - 0x10, // address - 0x008F8944, // data - 0x0FFFFFFF // mask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 0 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 7 - // 4:0 NpReqCmd: 14 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), // link features - 0x10, // address - 0x008402EE, // data - 0x0FFFFFFF // mask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 3 - // 17:16 NpReqData: 3 - // 15:12 ProbeCmd: 4 - // 11:8 RspCmd: 9 - // 7:5 PReq: 2 - // 4:0 NpReqCmd: 8 - { - HtHostPerfPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, - HT_HOST_FEAT_COHERENT, // link features - 0x10, // address - 0x008F4948, // data - 0x0FFFFFFF // mask - }} - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - HT_HOST_FEAT_COHERENT, // link features - 0x14, // address - 0x00010000, // data - 0x1FFF0000 // mask - }} - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, - {{ - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), // Link Features - 0x14, // Address - 0x00010000, // Data - 0x1FFF0000 // Mask - }}, - }, - -// Function 3 - Misc. Control - -// NOTE: Order is important. Do not re-order -// the entries for F3x140. - -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 3 -// bits[23:20] FreeTok = 10 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // SCM - PACKAGE_TYPE_SCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00A00300, // regData - 0x00F00300, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 3 -// bits[23:20] FreeTok = 10 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h - PACKAGE_TYPE_MCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00A00300, // regData - 0x00F00300, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 3 -// bits[23:20] FreeTok = 9 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, - (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h - PACKAGE_TYPE_MCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00900300, // regData - 0x00F00300, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 1 -// bits[23:20] FreeTok = 11 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // MCM2 - PACKAGE_TYPE_MCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00B00100, // regData - 0x00F00300, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 3 -// bits[23:20] FreeTok = 10 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // MCM4h - PACKAGE_TYPE_MCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00A00300, // regData - 0x00F00300, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 1 -// bits[23:20] FreeTok = 9 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // MCM4 - PACKAGE_TYPE_MCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00900100, // regData - 0x00F00300, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 3 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), // SCM - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000C1AA, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h. - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x000001AA, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (IGNORE_PROCESSOR_0 | DEGREE_RANGE_1 (2, 3)), // MCM2 or MCM4h - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000016A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // MCM4 - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x00000196, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h. - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x00550155, // regData - 0xD5FFFFFF, // regMask - }} - }, - // F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h. - PERFORMANCE_PROBEFILTER, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x00550165, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 2 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 1 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (IGNORE_PROCESSOR_0 | DEGREE_RANGE_1 (3, 3)), // MCM2 - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x01558155, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 1 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 1 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (IGNORE_PROCESSOR_0 | DEGREE_RANGE_1 (2, 2)), // MCM4h - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x41550155, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 1 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // MCM4 - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x01550155, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 3 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), //SCM - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000C12A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE), // MCM1 or MCM2h or MCM2 or MCM4h - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000012A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 2 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // MCM4 - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x000002AA, // regData - 0xD5FFFFFF, // regMask - }} - }, - // F3x158 - Link to XCS Token Count Registers - // bits [3:0]LnkToXcsDRToken = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address - 0x00000000, - 0x0000000F - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrMultiLinkPciRegisterTable = { - PrimaryCores, - (sizeof (F15OrMultiLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F15OrMultiLinkPciRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c deleted file mode 100644 index ce07817575..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c +++ /dev/null @@ -1,962 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 59564 $ @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrPciRegisters[] = -{ -// F0x68 - Link Transaction Control -// bit[11] , RespPassPW = 1 -// bits[14:13], BufRelPri = 1 -// bit[19:17], for 8bit APIC config -// bit[22:21], DsNpReqLmt = 10b -// bit [25] CHtExtAddrEn = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x024E2800, // regData - 0x026E6800, // regMask - }} - }, -// F0x6C - Link Initialization Control -// bit[23] TxSSBusPwrSaveEn = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address - 0x00800000, // regData - 0x00800000, // regMask - }} - }, -// F0x[E4,A4,C4,84] Link Control Register -// bit [15] Addr64bitEn = 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, - {{ - HT_HOST_FEAT_NONCOHERENT, - 0x4, - 0x00008000, - 0x00008000, - }} - }, -// F0x[E4,C4,A4,84] - Link 0 Control Register -// bit[13] LdtStopTriEn = 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x04, // Address - 0x00002000, // regData - 0x00002000, // regMask - }} - }, -// F0x[E4,C4,A4,84] - Link 0 Control Register -// bit [12] IsocEn = 0 default - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_NFCM | AMD_PF_UMA) }, - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x04, // Address - 0x00000000, // regData - 0x00001000, // regMask - }} - }, -// F0x[E4,C4,A4,84] - Link 0 Control Register -// bit [12] IsocEn = 1 for Isochronous control flow modes. - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_UMA_IFCM | AMD_PF_IFCM | AMD_PF_IOMMU) }, - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x04, // Address - 0x00001000, // regData - 0x00001000, // regMask - }} - }, -// F0x[F0,D0,B0,90] - Link Base Channel Buffer Count -// bit[31] LockBc = 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x10, // Address - 0x80000000, // regData - 0x80000000, // regMask - }} - }, -// F0x150 - Link Global Retry Control Register -// bit[18:16] TotalRetryAttempts = 7 -// bit[13] HtRetryCrcDatInsDynEn = 1 -// bit[12]HtRetryCrcCmdPackDynEn = 1 -// bit[11:9] HtRetryCrcDatIns = leave default reset value (erratum #600) -// bit[8] HtRetryCrcCmdPack = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address - 0x00073100, // regData - 0x00073100, // regMask - }} - }, -// F0x16C - Link Global Extended Control Register -// bit[22:17] FullT0Time = 0x33 -// bit[15:13] ForceFullT0 = 7 -// bit[7:6] InLnSt = 01b (PHY_OFF) -// bit[5:0] T0Time = 0x26 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address - 0x0066E066, // regData - 0x007EE0FF, // regMask - }} - }, -// F0x[18C:170] - Link Extended Control Register - All connected links. -// bit[8] LS2En = 1 - { - HtLinkPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platform Features - {{ - HT_HOST_FEATURES_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F2x1B0 - Extended Memory Controller Configuration Low -// bits[10:8], CohPrefPrbLmt = 0 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, // Features - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address - 0x00000000, // regData - 0x00000700, // regMask - }} - }, -// Function 3 - Misc. Control - -// F3x40 - MCA NB Control -// -// bit[8], MstrAbrtEn = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F3x44 - MCA NB Configuration -// bit[30] SyncOnDramAdrParErrEn = 1 -// bit[27] NB MCA to Master CPU Enable = 1 -// bit[25] DisPciCfgCpuErrRsp = 1 -// bit[21] SyncFloodOnAnyUcErr = 1 -// bit[20] SyncOnWDTEn = 1 -// bit[6] CpuErrDis = 1 -// bit[4] SyncPktPropDis = 0 -// bit[3] SyncPktGenDis = 0 -// bit[2] SyncOnUcEccEn = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address - 0x4A300044, // regData - 0x4A30005C, // regMask - }} - }, -// F3x70 - SRI_to_XBAR Command Buffer Count -// bits[30:28] IsocRspCBC = 1 -// bits[26:24] IsocPreqCBC = 0 -// bits[22:20] IsocReqCBC = 1 -// bits[18:16] UpRspCBC = 7 -// bits[14:12] DnPreqCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[7:6] DnRspCBC = 1 -// bits[5:4] DnReqCBC = 1 -// bits[2:0] UpReqCBC = 5 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address - 0x10171155, // regData - 0x777777F7, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[31:28] DRReqCBC = 0 -// bits[26:24] IsocPreqCBC = 0 -// bits[23:20] IsocReqCBC = 1 -// bits[19:16] ProbeCBC = 7 -// bits[14:12] DnPreqCBC = 2 -// bits[10:8] UpPreqCBC = 1 -// bits[6:4] DnReqCBC = 1 -// bits[2:0] UpReqCBC = 1 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x00172111, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x78 - MCT to XBAR Buffer Count -// bits[12:8] ProbeCBC = 0Eh -// bits[4:0] RspCBC = 12h - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x78), // Address - 0x00000E12, // regData - 0x00001F1F, // regMask - }} - }, -// F3x78 - MCT to XBAR Buffer Count -// bits[12:8] ProbeCBC = 0Ch -// bits[4:0] RspCBC = 14h - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x78), // Address - 0x00000C14, // regData - 0x00001F1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[26:23] SrqExtFreeListBC = 8 -// bits[22:20] Sri2XbarFreeRspDBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 0xD -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[11:8] Sri2XbarFreeXreqCBC = 0xF - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x040D0F00, // regData - 0x07FFFF00, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 0x16 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00000016, // regData - 0x0000001F, // regMask - }} - }, -// F3x80 - ACPI Power State Control -// ACPI State C2 -// bit[0] CpuPrbEn = 1 -// bit[1] NbLowPwrEn = 0 -// bit[2] NbGateEn = 0 -// bits[7:5] ClkDivisor = 4 -// ACPI State C3, C1E or Link init -// bit[0] CpuPrbEn = 0 -// bit[1] NbLowPwrEn = 1 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 0 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 7 -// NB P-state changes -// bit[0] CpuPrbEn = 1 -// bit[1] NbLowPwrEn = 1 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 1 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 0 -// S1 -// bit[0] CpuPrbEn = 0 -// bit[1] NbLowPwrEn = 1 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 0 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 7 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address - 0xE20BE281, // regData - 0xFFFFFFE7, // regMask - }} - }, -// F3x84 - ACPI Power State Control -// ACPI State S3 -// bit[0] CpuPrbEn = 0 -// bit[1] NbLowPwrEn = 1 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 0 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 7 -// ACPI State S4/S5 -// bit[0] CpuPrbEn = 0 -// bit[1] NbLowPwrEn = 1 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 0 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 7 -// ACPI State C1 -// bit[0] CpuPrbEn = 0 -// bit[1] NbLowPwrEn = 0 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 0 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 7 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address - 0xE0E200E2, // regData - 0xEFFF00FF, // regMask - }} - }, -// F3x84 - ACPI Power State Control -// ACPI State C1 -// bits[0] CpuPrbEn = 0 -// bits[1] NbLowPwrEn = 0 -// bits[2] NbGateEn = 0 -// bits[7:5] ClkDivisor = 4 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_CORE}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address - 0x80000000, // regData - 0xE7000000, // regMask - }} - }, -// F3x90 - GART Aperture Control -// bit[6] = DisGartTblWlkPrb, Erratum 540 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x90), // Address - 0x00000040, // regData - 0x00000040, // regMask - }} - }, -// F3xA0 - Power Control Miscellaneous -// bit[9] SviHighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address - 0x00000200, // regData - 0x00000200, // regMask - }} - }, -// F3xD4 - Clock Power Timing Control 0 -// bits[11:8] ClkRampHystSel = 0xF -// bits[15] StutterScrubEn = 0 -// bits[14] CacheFlushImmOnAllHalt = 0 -// bits[13] MTC1eEn = 0 -// bits[17:16] LnkPllLock = 1 -// bits[30:28] NbClkDiv = 4 -// bits[31] NbClkDivApplyAll = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address - 0xC0010F00, // regData - 0xF003EF00, // regMask - }} - }, -// F3xD8 - Clock Power Timing Control 1 -// bits[6:4] VSRampSlamTime = 1 -// bits[27:24] ReConDel = 3 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8), // Address - 0x03000010, // regData - 0x0F000070, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 1 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTok = 1 -// bits[7:6] DnPreqTok = 1 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 1 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00011455, // regData - 0x0003FCFF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 5 -// bits[7:4] ProbeTok = 5 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000055, // regData - 0x000000FF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 8 -// bits[7:4] ProbeTok = 2 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000028, // regData - 0x000000FF, // regMask - }} - }, -// F3x160 - NB Machine Check Misc 0 -// bits[23:20] LvtOffset = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x160), // Address - 0x00100000, // regData - 0x00F00000, // regMask - }} - }, -// F3x168 - NB Machine Check Misc 1 -// bits[23:20] LvtOffset = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x168), // Address - 0x00100000, // regData - 0x00F00000, // regMask - }} - }, -// F3x170 - NB Machine Check Misc 2 -// bits[23:20] LvtOffset = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x170), // Address - 0x00100000, // regData - 0x00F00000, // regMask - }} - }, -// F3x180 - NB Extended Configuration -// bit[1] SyncFloodOnUsPwDatErr = 1 -// bit[5] DisPciCfgCpuMstAbtRsp = 1 -// bit[6] SyncFloodOnDatErr = 1 -// bit[7] SyncFloodOnTgtAbtErr = 1 -// bit[8] SyncFloodOnHtProtEn = 1 -// bit[9] SyncOnUCNbAryEn = 1 -// bit[20] SyncFloodOnL3LeakErr = 1 -// bit[21] SyncFloodOnCpuLeakErr = 1 -// bit[22] SyncFloodOnTblWalkErr = 1 -// bit[24] McaLogErrAddrWdtErr = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address - 0x017003E2, // regData - 0x017003E2, // regMask - }} - }, -// F3x188 - NB Configuration 2 Register -// bit[9] DisL3HiPriFreeListAlloc = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address - 0x00000200, // regData - 0x00000200, // regMask - }} - }, -// F3x1A0 - L3 Buffer Count -// bits[17:16] CpuToNbFreeBufCnt = 3 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address - 0x00030000, // regData - 0x00030000, // regMask - }} - }, -// F3x1B8 - L3 Control 1 -// bit[12] L3PrivReplEn = 1 -// bit[18] Reserved = 1, Erratum #504 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address - 0x00041000, // regData - 0x00041000, // regMask - }} - }, -// F3x1E4 - SBI Control -// bits[11:8] LvtOffset = 3 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1E4), // Address - 0x00000300, // regData - 0x00000F00, // regMask - }} - }, -// F4x104 - TDP Accumulator Divisor Control -// bits[1:0] TdpAccDivVal = 1 -// bits[13:2] TdpAccDivRate = 0x0C8 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x104), // Address - 0x00000321, // regData - 0x00003FFF, // regMask - }} - }, -// F4x110 - Sample and Residency Timer -// bits[11:0] CSampleTimer = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x110), // Address - 0x00000001, // regData - 0x00000FFF, // regMask - }} - }, -// F4x118 - C-state Control 1 -// bit [0] CpuPrbEnCstAct0 = 0 -// bit [1] CacheFlushEnCstAct0 = 0 -// bits[3:2] CacheFlushTmrSelCstAct0 = 0 -// bits[7:5] ClkDivisorCstAct0 = 0 -// bit [8] PwrGateEnCstAct0 = 0 -// bit [16] CpuPrbEnCstAct1 = 0 -// bit [17] CacheFlushEnCstAct1 = 0 -// bits[19:18] CacheFlushTmrSelCstAct1 = 0 -// bits[23:21] ClkDivisorCstAct1 = 0 -// bit [24] PwrGateEnCstAct1 = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address - 0x00000000, // regData - 0x01EF01EF, // regMask - }} - }, -// F4x11C - C-state Control 2 -// bit [0] CpuPrbEnCstAct2 = 0 -// bit [1] CacheFlushEnCstAct2 = 0 -// bits[3:2] CacheFlushTmrSelCstAct2 = 0 -// bits[7:5] ClkDivisorCstAct2 = 0 -// bit [8] PwrGateEnCstAct2 = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x11C), // Address - 0x00000000, // regData - 0x000001EF, // regMask - }} - }, -// F4x128 - C-state Policy Control 1 -// bits[20:18] CacheFlushSucMonThreshold = 4 -// bits[11:5] CacheFlushTmr = 0x28 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x128), // Address - 0x00100500, // regData - 0x001C0FE0, // regMask - }} - }, -// F4x16C - APM TDP Control -// bit[4] ApmTdpLimitIntEn = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x16C), // Address - 0x00000010, // regData - 0x00000010, // regMask - }} - }, -// F4x1C4 - L3 Power Control Register -// bits[8] L3PwrSavEn = 1 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F4x1CC - L3 Control 2 -// bit[4] ImplRdAnySubUnavail = 1 -// bits[8:6] ImplRdProjDelayThresh = 2 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1CC), // Address - 0x00000090, // regData - 0x000001D0, // regMask - }} - }, -// F5x88 - Northbridge Configuration 4 -// bit[5] Reserved, BIOS must set - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - 0x04, // Features - MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88), // Address - 0x00000020, // regData - 0x00000020, // regMask - }} - }, -// F5x88 - Northbridge Configuration 4 -// bit[14] Reserved, BIOS must set - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_Bx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88), // Address - 0x00004000, // regData - 0x00004000, // regMask - }} - }, -// F5xE0 - Processor TDP Running Average -// bits[3:0] RunAvgRange = 0xE - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_5, 0xE0), // Address - 0x0000000E, // regData - 0x0000000F, // regMask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable = { - PrimaryCores, - (sizeof (F15OrPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F15OrPciRegisters, -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c deleted file mode 100644 index b339d2d983..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c +++ /dev/null @@ -1,317 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi NB COF VID Initialization - * - * Performs the "BIOS Northbridge COF and VID Configuration" as - * described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 51891 $ @e \$Date: 2011-04-28 12:39:55 -0600 (Thu, 28 Apr 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuApicUtilities.h" -#include "OptionMultiSocket.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "F15OrPmNbCofVidInit.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORPMNBCOFVIDINIT_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrPmNbCofVidInitOnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 15h Orochi core 0 entry point for performing the "Mixed Northbridge Frequency - * Configuration Sequence" - * - * BIOS must match F5x1[6C:60][NbFid, NbDid, NbPstateEn] between all - * processors of a multi-socket system. The lowest setting from all - * processors is used as the common F5x1[6C:60][NbFid, NbDid]. All - * processors must have the same number of NB P-states. - * - * For each node in the system { - * For (i = 0; i <= F5x170[NbPstateMaxVal]; i++) { - * NewNbFreq = the lowest NBCOF from all processors for NB P-state i - * NewNbFid = F5x1[6C:60][NbFid] that corresponds to NewNbFreq - * NewNbDid = F5x1[6C:60][NbDid] that corresponds to NewNbFreq - * Write NewNbFid and NewNbDid to F5x1[6C:60][NbFid, NbDid] indexed - * by NB P-state i - * } - * If (F5x170[NbPstateMaxVal] == 0) { - * Save F5x170 and F5x1[6C:60] indexed by NB P-state 1 - * Copy F5x1[6C:60] indexed by NB P-state 0 to F5x1[6C:60] indexed by NB P-state 1 - * Write 1 to F5x170[NbPstateMaxVal, NbPstateLo] - * Write 0 to F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold] - * Wait for F5x174[CurNbPstate] = F5x170[NbPstateLo] and F5x174[CurNbFid, CurNb- - * Did]=[NbFid, NbDid] from F5x1[6C:60] indexed by F5x170[NbPstateLo] - * Restore F5x170 and F5x1[6C:60] indexed by NB P-state 1 - * Wait for F5x174[CurNbPstate] = F5x170[NbPstateHi] - * } - * } - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service related parameters (unused). - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrPmNbCofVidInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 i; - UINT32 NbFreq; - UINT32 NbDiv; - UINT32 LocalPciRegister; - UINT32 AndMask; - UINT32 OrMask; - UINT32 Ignored; - UINT32 NbPsCtrl; - UINT32 TaskedCore; - BOOLEAN PstateSettingsChanged; - BOOLEAN PstatesMatch; - BOOLEAN PstateEnabledAll; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - // Get the local node ID - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - - ASSERT (Core == 0); - - PstateSettingsChanged = FALSE; - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - for (i = 0; i <= ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal; i++) { - if (OptionMultiSocketConfiguration.GetSystemNbPstateSettings (i, &CpuEarlyParamsPtr->PlatformConfig, &NbFreq, &NbDiv, &PstatesMatch, &PstateEnabledAll, StdHeader)) { - if (PstateEnabledAll) { - // Valid system-wide NB P-state - if (!PstatesMatch) { - // Configure NbPstate[i] to match the slowest - PciAddress.Address.Register = (NB_PSTATE_0 + (4 * i)); - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - OrMask = 0x00000000; - ((NB_PSTATE_REGISTER *) &OrMask)->NbFid = ((NbFreq / 200) - 4); - ((NB_PSTATE_REGISTER *) &OrMask)->NbDid = (UINT32) LibAmdBitScanForward (NbDiv); - if ((((NB_PSTATE_REGISTER *) &OrMask)->NbFid != ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid) || - (((NB_PSTATE_REGISTER *) &OrMask)->NbDid != ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid)) { - AndMask = 0xFFFFFFFF; - ((NB_PSTATE_REGISTER *) &AndMask)->NbFid = 0; - ((NB_PSTATE_REGISTER *) &AndMask)->NbDid = 0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - PstateSettingsChanged = TRUE; - } - } - } else { - // At least one processor in the system does not have NbPstate[i] - PciAddress.Address.Register = NB_PSTATE_CTRL; - AndMask = 0xFFFFFFFF; - ((NB_PSTATE_CTRL_REGISTER *) &AndMask)->NbPstateMaxVal = 0; - OrMask = 0; - if (i != 0) { - ((NB_PSTATE_CTRL_REGISTER *) &OrMask)->NbPstateMaxVal = (i - 1); - } - // Modify NbPstateMaxVal to reflect the system value - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - // Disable this NB P-state - PciAddress.Address.Register = (NB_PSTATE_0 + (4 * i)); - AndMask = 0xFFFFFFFF; - ((NB_PSTATE_REGISTER *) &AndMask)->NbPstateEn = 0; - OrMask = 0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - // Log error for the invalid configuration - PutEventLog (AGESA_ERROR, - CPU_ERROR_PM_NB_PSTATE_MISMATCH, - Socket, i, 0, 0, StdHeader); - break; - } - } - } - - if (PstateSettingsChanged) { - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal == 0) { - // Launch one core per node. - TaskPtr.FuncAddress.PfApTask = F15OrPmNbCofVidInitOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) { - if (TaskedCore != 0) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader); - } - } - } - ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr); - } - } -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmNbCofVidInit to perform the actual NB P-state transition - * to the leveled NB P-state settings on one core of each die in a family 15h socket. - * - * The following steps are performed: - * 1. Save F5x170 and F5x1[6C:60] indexed by NB P-state 1 - * 2. Copy F5x1[6C:60] indexed by NB P-state 0 to F5x1[6C:60] indexed by NB P-state 1 - * 3, Write 1 to F5x170[NbPstateMaxVal, NbPstateLo] - * 4. Write 0 to F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold] - * 5. Wait for F5x174[CurNbPstate] = F5x170[NbPstateLo] and F5x174[CurNbFid, CurNb- - * Did]=[NbFid, NbDid] from F5x1[6C:60] indexed by F5x170[NbPstateLo] - * 6. Restore F5x170 and F5x1[6C:60] indexed by NB P-state 1 - * 7. Wait for F5x174[CurNbPstate] = F5x170[NbPstateHi] - * - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15OrPmNbCofVidInitOnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbPsCtrl; - UINT32 NbPs0; - UINT32 NbPs1; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - - // Save F5x170 and F5x164 - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - - PciAddress.Address.Register = NB_PSTATE_0; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPs0, StdHeader); - PciAddress.Address.Register = NB_PSTATE_1; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPs1, StdHeader); - - // Copy F5x160 to F5x164 - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPs0, StdHeader); - - // Write 1 to F5x170[NbPstateMaxVal, NbPstateLo] - PciAddress.Address.Register = NB_PSTATE_CTRL; - LocalPciRegister = NbPsCtrl; - ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal = 1; - ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateLo = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - // Write 0 to F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold] - ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->SwNbPstateLoDis = 0; - ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateDisOnP0 = 0; - ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateThreshold = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - // Wait for F5x174[CurNbPstate] = F5x170[NbPstateLo] (written to 1 above) and - // F5x174[CurNbFid, CurNbDid] = F5x164[NbFid, NbDid] - PciAddress.Address.Register = NB_PSTATE_STATUS; - do { - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } while ((((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbPstate != 1) && - (((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbFid != ((NB_PSTATE_REGISTER *) &NbPs0)->NbFid) && - (((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbDid != ((NB_PSTATE_REGISTER *) &NbPs0)->NbDid)); - - // Restore F5x170 and F5x164 - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - PciAddress.Address.Register = NB_PSTATE_1; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPs1, StdHeader); - - // Wait for F5x174[CurNbPstate] = F5x170[NbPstateHi] - PciAddress.Address.Register = NB_PSTATE_STATUS; - do { - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } while (((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbPstate != ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateHi); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.h deleted file mode 100644 index 69652474df..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi NB COF VID Initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_PM_NB_COF_VID_INIT_H_ -#define _CPU_F15_OR_PM_NB_COF_VID_INIT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrPmNbCofVidInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F15_OR_PM_NB_COF_VID_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c deleted file mode 100644 index 7cc2e82dce..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c +++ /dev/null @@ -1,177 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Models 0x00 - 0x0F Power Management related initialization table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "cpuPowerMgmtSystemTables.h" -#include "cpuF15OrCoreAfterReset.h" -#include "cpuF15OrNbAfterReset.h" -#include "cpuF15OrSoftwareThermal.h" -#include "F15OrPowerPlane.h" -#include "cpuF15PowerCheck.h" -#include "F15OrPmNbCofVidInit.h" -#include "F15OrUtilities.h" - -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORPOWERMGMTSYSTEMTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF15OrSysPmTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **SysPmTblPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* Family 15h Only Table */ -/* ---------------------- */ -CONST SYS_PM_TBL_STEP ROMDATA CpuF15OrSysPmTableArray[] = -{ - - IDS_INITIAL_F15_OR_PM_STEP - - // Step 1 - Configure F3x[84:80]. Handled by PCI register table. - // Step 2 - Power Plane Initialization - // Execute both cold & warm - { - 0, // ExeFlags - F15OrPmPwrPlaneInit // Function Pointer - }, - - // Step x - Disable NB Pstate, if required - // Execute both cold & warm - { - 0, // ExeFlags - F15OrNbPstateDis // Function Pointer - }, - - // Step 3 - Configure Northbridge COF and VID. - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F15OrPmNbCofVidInit // Function Pointer - }, - - // Step 4 - Core Minimum P-state Transition Sequence After Warm Reset - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F15OrPmCoreAfterReset // Function Pointer - }, - - // Step 5 - NB COF and VID Transition Sequence After Warm Reset - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F15OrPmNbAfterReset // Function Pointer - }, - - // Step 6 - Power Check - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F15PmPwrCheck // Function Pointer - }, - - // Step 7 - Software Thermal Control Init - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F15OrPmThermalInit // Function Pointer - } -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the appropriate table of steps to perform to initialize the power management - * subsystem. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] SysPmTblPtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF15OrSysPmTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **SysPmTblPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = (sizeof (CpuF15OrSysPmTableArray) / sizeof (SYS_PM_TBL_STEP)); - *SysPmTblPtr = CpuF15OrSysPmTableArray; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c deleted file mode 100644 index 317f9d62ad..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c +++ /dev/null @@ -1,236 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Models 0x00 - 0x0F Power Plane Initialization - * - * Performs the "BIOS Requirements for Power Plane Initialization" as described - * in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "Table.h" -#include "OptionMultiSocket.h" -#include "F15OrPowerPlane.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORPOWERPLANE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrPmVrmLowPowerModeEnable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 15h core 0 entry point for performing power plane initialization. - * - * The steps are as follows: - * 1. Configure D18F3xD8[VSRampSlamTime] based on platform - * requirements. - * 2. Configure F3xD4[PowerStepUp & PowerStepDown] - * 3. Optionally configure F3xA0[PsiVidEn & PsiVid] - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrPmPwrPlaneInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - UINT32 Core; - UINT32 LocalPciRegister; - UINT32 AndMask; - UINT32 OrMask; - PLATFORM_FEATS Features; - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - GetCurrentCore (&Core, StdHeader); - ASSERT (Core == 0); - - // Configure D18F3xD8[VSRampSlamTime] based on platform requirements. - // Before characterization has taken place, no calculations are necessary. - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC1_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - OrMask = 0x00000000; - AndMask = 0xFFFFFFFF; - ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->VSRampSlamTime = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - // Configure PowerStepUp/PowerStepDown - PciAddress.Address.Register = CPTC0_REG; - AndMask = 0xFFFFFFFF; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepUp = 0; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepDown = 0; - OrMask = 0x00000000; - Features.PlatformValue = 0; - GetPlatformFeatures (&Features, &CpuEarlyParams->PlatformConfig, StdHeader); - if (Features.PlatformFeatures.PlatformSingleLink == 1) { - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = 8; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = 8; - } else { - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = 3; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = 3; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - if (IsWarmReset (StdHeader)) { - // Configure PsiVid - F15OrPmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, PciAddress, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Sets up PSI_L operation. - * - * This function implements the LowPowerThreshold parameter. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Contains VrmLowPowerThreshold parameter. - * @param[in] PciAddress Segment, bus, device number of the node to transition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15OrPmVrmLowPowerModeEnable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Pstate; - UINT32 PstateCurrent; - UINT32 NextPstateCurrent; - UINT32 AndMask; - UINT32 OrMask; - UINT32 PreviousVID; - UINT32 PstateVID; - UINT32 HwPsMaxVal; - UINT64 PstateMsr; - BOOLEAN EnablePsi; - - if (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold != 0) { - EnablePsi = FALSE; - PreviousVID = 0x7F; // Initialize to invalid zero volt VID code - PstateVID = 0x7F; - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader); - - for (Pstate = 0; Pstate <= (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal; Pstate++) { - if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader)) { - LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader); - PstateVID = (UINT32) (((PSTATE_MSR *) &PstateMsr)->CpuVid); - if ((Pstate + 1) > (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal) { - NextPstateCurrent = 0; - } else if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader)) { - NextPstateCurrent = CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].InrushCurrentLimit + NextPstateCurrent; - } - if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && (NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && (PstateVID != PreviousVID)) { - EnablePsi = TRUE; - break; - } - PreviousVID = PstateVID; - } - } - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PW_CTL_MISC_REG; - OrMask = 0x00000000; - AndMask = 0xFFFFFFFF; - ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVid = 0; - if (EnablePsi) { - ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVid = PstateVID; - ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVidEn = 1; - } else { - ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVidEn = 0; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.h deleted file mode 100644 index 8396bf3146..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Models 0x00 - 0x0F Power Plane related functions and structures - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _F15_OR_POWER_PLANE_H_ -#define _F15_OR_POWER_PLANE_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrPmPwrPlaneInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _F15_OR_POWER_PLANE_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c deleted file mode 100644 index 311e210134..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c +++ /dev/null @@ -1,376 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Shared MSR table with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 53046 $ @e \$Date: 2011-05-13 20:20:37 -0600 (Fri, 13 May 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuF15OrPowerMgmt.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -F15OrFpCfgInit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15OrSharedMsrRegisters[] = -{ -// M S R T a b l e s -// ---------------------- - -// MSR_TOM2 (0xC001001D) -// bits[63:0] - TOP_MEM2 = 0 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_TOM2, // MSR Address - Shared - 0x0000000000000000, // OR Mask - 0xFFFFFFFFFFFFFFFF, // NAND Mask - }} - }, - -// MSR_SYS_CFG (0xC0010010) -// bit[21] MtrrTom2En = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_SYS_CFG, // MSR Address - Shared - (1 << 21), // OR Mask - (1 << 21), // NAND Mask - }} - }, - -// MSR_MC1_CTL_MASK (0xC0010045) -// bit[15] BSRP = 1, Erratum #593, OR-ALL -// bit[18] DEIBP = 1, Erratum #586, OR-ALL - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_MC1_CTL_MASK, // MSR Address - 0x0000000000048000, // OR Mask - 0x0000000000048000, // NAND Mask - }} - }, - -// MSR_CU_CFG (0xC0011023) -// bit[10] PbForceRespInOrder = 0 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CU_CFG, // MSR Address - Shared - 0, // OR Mask - 0x00000400, // NAND Mask - }} - }, - -// MSR_DE_CFG (0xC0011029) -// bit[10] ResyncPredSingleDispDis = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_DE_CFG, // MSR Address - Shared - 0x0000000000000400, // OR Mask - 0x0000000000000400, // NAND Mask - }} - }, - -// MSR_CU_CFG2 (0xC001102A) -// bit[50] = 1 -// bit[11] = 1, Erratum #503, OR-ALL -// bit[10] = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CU_CFG2, // MSR Address - Shared - 0x0004000000000C00, // OR Mask - 0x0004000000000C00, // NAND Mask - }} - }, - -// MSR_CU_CFG3 (0xC001102B) -// bit[42] PwcDisableWalkerSharing = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CU_CFG3, // MSR Address - 0x0000040000000000, // OR Mask - 0x0000040000000000, // NAND Mask - }} - }, -}; - - -// Compute Unit Count Dependent MSR Table - -STATIC CONST MSR_CU_TYPE_ENTRY_INITIALIZER ROMDATA F15OrSharedMsrCuRegisters[] = -{ -// M S R T a b l e s -// ---------------------- - - // MSR_CU_CFG2 (0xC001102A) - // bits[7:6] - ThrottleNbInterface[1:0] = 0 - // bits[37:36] - ThrottleNbInterface[3:2] = 0 - { - CompUnitCountsMsr, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - {(COMPUTE_UNIT_RANGE_0 (1, 1) | COUNT_RANGE_NONE)}, // 1 compute unit - { - MSR_CU_CFG2, // MSR Address - Shared - 0x0000000000000000, // OR Mask - 0x00000030000000C0, // NAND Mask - } - }} - }, - - // MSR_CU_CFG2 (0xC001102A) - // bits[7:6] - ThrottleNbInterface[1:0] = 1 - // bits[37:36] - ThrottleNbInterface[3:2] = 0 - { - CompUnitCountsMsr, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - {(COMPUTE_UNIT_RANGE_0 (2, 2) | COUNT_RANGE_NONE)}, // 2 compute units - { - MSR_CU_CFG2, // MSR Address - Shared - 0x0000000000000040, // OR Mask - 0x00000030000000C0, // NAND Mask - } - }} - }, - - // MSR_CU_CFG2 (0xC001102A) - // bits[7:6] - ThrottleNbInterface[1:0] = 2 - // bits[37:36] - ThrottleNbInterface[3:2] = 0 - { - CompUnitCountsMsr, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - {(COMPUTE_UNIT_RANGE_0 (3, 3) | COUNT_RANGE_NONE)}, // 3 compute units - { - MSR_CU_CFG2, // MSR Address - Shared - 0x0000000000000080, // OR Mask - 0x00000030000000C0, // NAND Mask - } - }} - }, - - // MSR_CU_CFG2 (0xC001102A) - // bits[7:6] - ThrottleNbInterface[1:0] = 3 - // bits[37:36] - ThrottleNbInterface[3:2] = 0 - { - CompUnitCountsMsr, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - {(COMPUTE_UNIT_RANGE_0 (4, 4) | COUNT_RANGE_NONE)}, // 4 compute units - { - MSR_CU_CFG2, // MSR Address - Shared - 0x00000000000000C0, // OR Mask - 0x00000030000000C0, // NAND Mask - } - }} - }, -}; - -// Shared MSRs with Special Programming Requirements Table - -STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15OrSharedMsrWorkarounds[] = -{ - // MSR_FP_CFG (0xC0011028) - // bit[16] - DiDtMode = F3x1FC[0] - // bits[22:18] - DiDtCfg0 = F3x1FC[5:1] - // bits[34:27] - DiDtCfg1 = F3x1FC[13:6] - { - FamSpecificWorkaround, - { - AMD_FAMILY_15_OR, - AMD_F15_OR_ALL - }, - {AMD_PF_ALL}, - {{ - F15OrFpCfgInit, - 0x00000000 - }} - }, -}; - - - -CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable = { - CorePairPrimary, - (sizeof (F15OrSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrSharedMsrRegisters, -}; - - -CONST REGISTER_TABLE ROMDATA F15OrSharedMsrCuRegisterTable = { - CorePairPrimary, - (sizeof (F15OrSharedMsrCuRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrSharedMsrCuRegisters, -}; - -CONST REGISTER_TABLE ROMDATA F15OrSharedMsrWorkaroundTable = { - CorePairPrimary, - (sizeof (F15OrSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrSharedMsrWorkarounds, -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Update the FP_CFG MSR in current processor for Family15h OR. - * - * This function satisfies the programming requirements for the FP_CFG MSR. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrFpCfgInit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ProductInfo; - UINT64 FpCfg; - PCI_ADDR PciAddress; - - if (IsWarmReset (StdHeader)) { - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PRCT_INFO_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &ProductInfo, StdHeader); - - LibAmdMsrRead (MSR_FP_CFG, &FpCfg, StdHeader); - ((FP_CFG_MSR *) &FpCfg)->DiDtMode = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtMode; - ((FP_CFG_MSR *) &FpCfg)->DiDtCfg0 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg0; - ((FP_CFG_MSR *) &FpCfg)->DiDtCfg1 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg1; - ((FP_CFG_MSR *) &FpCfg)->AlwaysOnThrottle = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->AlwaysOnThrottle; - ((FP_CFG_MSR *) &FpCfg)->Pipe3ThrottleDis = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->Pipe3ThrottleDis; - LibAmdMsrWrite (MSR_FP_CFG, &FpCfg, StdHeader); - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSingleLinkPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSingleLinkPciTables.c deleted file mode 100644 index 5df3ffa252..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSingleLinkPciTables.c +++ /dev/null @@ -1,321 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi PCI tables in Recommended Settings for Single Link Processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 41897 $ @e \$Date: 2010-11-12 12:39:18 +0800 (Fri, 12 Nov 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORSINGLELINKPCITABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrSingleLinkPciRegisters[] = -{ -// F0x68 - Link Transaction Control -// bit[14:13], BufPriRel = 01b - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x00002000, // regData - 0x00006000, // regMask - }} - }, -// F0x68 - Link Transaction Control -// bit[24], DispRefModeEn = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x00000000, // regData - 0x01000000, // regMask - }} - }, -// F0x68 - Link Transaction Control -// bit[24], DispRefModeEn = 1 for UMA, but can only set it on the warm reset. - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_UMA}, // platform Features - {{ - PERFORMANCE_IS_WARM_RESET, - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x01000000, // regData - 0x01000000, // regMask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 0 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 7 - // 4:0 NpReqCmd: 14 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, - {{ - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), // Link Features - 0x10, // Address - 0x008402EE, // Data - 0x0FFFFFFF // Mask - }}, - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, - {{ - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), // Link Features - 0x14, // Address - 0x00010000, // Data - 0x1FFF0000 // Mask - }}, - }, -// F0x170 - Link Extended Control Register - Link 0, sublink 0 -// bit[8] LS2En = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F2x118 - Memory Controller Configuration Low Register -// bits[13:12] MctPriIsoc = 10b -// bits[31:28] MctVarPriCntLmt = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_UMA | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address - 0x00002000, // regData - 0xF0003000, // regMask - }} - }, -// F2x118 - Memory Controller Configuration Low Register -// bits[13:12] MctPriIsoc = 11b -// bits[31:28] MctVarPriCntLmt = 1 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_UMA | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address - 0x10003000, // regData - 0xF0003000, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 3 -// bits[23:20] FreeTok = 10 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00A00300, // regData - 0x00F00300, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 3 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platformFeatures - {{ - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), //SCM - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000C12A, // regData - 0xD5FFFFFF, // regMask - }} - }, - // F3x158 - Link to XCS Token Count Registers - // bits [3:0]LnkToXcsDRToken = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address - 0x00000000, - 0x0000000F - }} - }, - // F3x158 - Link to XCS Token Count Registers - // bits [3:0]LnkToXcsDRToken = 3 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address - 0x00000003, - 0x0000000F - }} - }, - // F3x158 - Link to XCS Token Count Registers - // bits [3:0]LnkToXcsDRToken = 3 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address - 0x00000003, - 0x0000000F - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrSingleLinkPciRegisterTable = { - PrimaryCores, - (sizeof (F15OrSingleLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F15OrSingleLinkPciRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c deleted file mode 100644 index ed2e460516..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c +++ /dev/null @@ -1,939 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 models 0 - 0Fh specific utility functions. - * - * Provides numerous utility functions specific to family 15h OR. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 58928 $ @e \$Date: 2011-09-08 16:43:14 -0600 (Thu, 08 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "cpuEarlyInit.h" -#include "GeneralServices.h" -#include "OptionMultiSocket.h" -#include "F15OrUtilities.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORUTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/** - * Node ID MSR register fields. - * Provide the layout of fields in the Node ID MSR. - */ -typedef struct { - UINT64 NodeId:3; ///< The core is on the node with this node id. - UINT64 NodesPerProcessor:3; ///< The number of Nodes in this processor. - UINT64 BiosScratch:6; ///< BiosScratch, use as the AP core heap index. - UINT64 :(63 - 11); ///< Reserved. -} NODE_ID_MSR_FIELDS; - -/// Node ID MSR. -typedef union { - NODE_ID_MSR_FIELDS Fields; ///< Access the register as individual fields - UINT64 Value; ///< Access the register value. -} NODE_ID_MSR; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -STATIC -F15OrNbPstateDisCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15OrSetDownCoreRegister ( - IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, - IN UINT32 *Socket, - IN UINT32 *Module, - IN UINT32 *LeveledCores, - IN CORE_LEVELING_TYPE CoreLevelMode, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Get CPU pstate current. - * - * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}. - * - * This function returns the ProcIddMax. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Pstate The P-state to check. - * @param[out] ProcIddMax P-state current in mA. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE P-state is enabled - * @retval FALSE P-state is disabled - */ -BOOLEAN -F15OrGetProcIddMax ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 Pstate, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 IddDiv; - UINT32 NumberOfPhysicalCores; - UINT32 MsrAddress; - UINT64 PstateMsr; - BOOLEAN IsPstateEnabled; - CPUID_DATA CpuId; - - IsPstateEnabled = FALSE; - - MsrAddress = (UINT32) (Pstate + PS_REG_BASE); - ASSERT (MsrAddress <= PS_MAX_REG); - - LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader); - if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) { - switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) { - case 0: - IddDiv = 1000; - break; - case 1: - IddDiv = 100; - break; - case 2: - IddDiv = 10; - break; - default: // IddDiv = 3 is reserved. Use 10 - IddDiv = 10; - break; - } - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader); - NumberOfPhysicalCores = ((CpuId.ECX_Reg & 0xFF) + 1); - - *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * NumberOfPhysicalCores; - IsPstateEnabled = TRUE; - } - return IsPstateEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set down core register on Orochi - * - * This function set F3x190 Downcore Control Register[5:0] - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Socket Socket ID. - * @param[in] Module Module ID in socket. - * @param[in] LeveledCores Number of core. - * @param[in] CoreLevelMode Core level mode. - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE Down Core register is updated. - * @retval FALSE Down Core register is not updated. - */ -BOOLEAN -F15OrSetDownCoreRegister ( - IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, - IN UINT32 *Socket, - IN UINT32 *Module, - IN UINT32 *LeveledCores, - IN CORE_LEVELING_TYPE CoreLevelMode, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Xbar2SriFreeListCBC; - UINT8 L3FreeListCBC; - UINT32 TempVar32_a; - UINT32 CoreDisableBits; - UINT32 NumberOfEnabledCores; - UINT32 NumberOfEnabledCU; - PCI_ADDR PciAddress; - BOOLEAN IsUpdated; - AGESA_STATUS AgesaStatus; - NB_CAPS_REGISTER NbCaps; - FREE_LIST_BUFFER_COUNT_REGISTER FreeListBufferCount; - L3_BUFFER_COUNT_REGISTER L3BufferCnt; - - IsUpdated = FALSE; - - if (CoreLevelMode == CORE_LEVEL_COMPUTE_UNIT) { - switch (*LeveledCores) { - case 1: - CoreDisableBits = DOWNCORE_MASK_SINGLE; - break; - case 2: - CoreDisableBits = DOWNCORE_MASK_DUAL_COMPUTE_UNIT; - break; - case 3: - CoreDisableBits = DOWNCORE_MASK_TRI_COMPUTE_UNIT; - break; - case 4: - CoreDisableBits = DOWNCORE_MASK_FOUR_COMPUTE_UNIT; - break; - default: - CoreDisableBits = 0; - break; - } - - } else { - switch (*LeveledCores) { - case 1: - CoreDisableBits = DOWNCORE_MASK_SINGLE; - break; - case 2: - CoreDisableBits = DOWNCORE_MASK_DUAL; - break; - case 4: - CoreDisableBits = DOWNCORE_MASK_FOUR; - break; - case 6: - CoreDisableBits = DOWNCORE_MASK_SIX; - break; - default: - CoreDisableBits = 0; - break; - } - } - - if (CoreDisableBits != 0) { - if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) { - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); - TempVar32_a = (TempVar32_a & 0xFF) + 1; - TempVar32_a = (1 << TempVar32_a) - 1; - CoreDisableBits &= TempVar32_a; - NumberOfEnabledCores = ~(CoreDisableBits | ~(TempVar32_a)); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = DOWNCORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); - if ((TempVar32_a | CoreDisableBits) != TempVar32_a) { - TempVar32_a |= CoreDisableBits; - LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); - IsUpdated = TRUE; - - for (NumberOfEnabledCU = 0; NumberOfEnabledCores != 0; NumberOfEnabledCores >>= 2) { - NumberOfEnabledCU += ((NumberOfEnabledCores & 3) != 0) ? 1 : 0; - } - switch (NumberOfEnabledCU) { - case 1: - Xbar2SriFreeListCBC = 0x16; - L3FreeListCBC = 0x1C; - break; - case 2: - Xbar2SriFreeListCBC = 0x14; - L3FreeListCBC = 0x18; - break; - case 3: - Xbar2SriFreeListCBC = 0x12; - L3FreeListCBC = 0x14; - break; - case 4: - Xbar2SriFreeListCBC = 0x10; - L3FreeListCBC = 0x10; - break; - default: - Xbar2SriFreeListCBC = 0x16; - L3FreeListCBC = 0xE; - break; - } - //D18F3x1A0[8:4] L3FreeListCBC: - //BIOS: IF (NumOfCompUnitsOnNode==1) THEN 1Ch ELSEIF (NumOfCompUnitsOnNode==2) - //THEN 18h ELSEIF (NumOfCompUnitsOnNode==3) THEN 14h ELSEIF - //(NumOfCompUnitsOnNode==4) THEN 10h ELSEIF (NumOfCompUnitsOnNode==5) THEN 11h - //ELSE 0Eh ENDIF. - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = L3_BUFFER_COUNT_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &L3BufferCnt, StdHeader); - L3BufferCnt.L3FreeListCBC = L3FreeListCBC; - LibAmdPciWrite (AccessWidth32, PciAddress, &L3BufferCnt, StdHeader); - - //D18F3x7C[4:0]Xbar2SriFreeListCBC: - //BIOS: IF (L3Enabled) THEN 16h ELSEIF (D18F5x80[Enabled[3]]==1) THEN 10h ELSEIF - //(D18F5x80[Enabled[2]]==1) THEN 12h ELSEIF (D18F5x80[Enabled[1]]==1) THEN 14h ELSE 16h ENDIF. - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); - if (NbCaps.L3Capable == 0) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = FREE_LIST_BUFFER_COUNT_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &FreeListBufferCount, StdHeader); - FreeListBufferCount.Xbar2SriFreeListCBC = Xbar2SriFreeListCBC; - LibAmdPciWrite (AccessWidth32, PciAddress, &FreeListBufferCount, StdHeader); - } - } - } - } - - return IsUpdated; -} - - -CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling = -{ - 0, - F15OrSetDownCoreRegister -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the NB clock on the desired node. - * - * @CpuServiceMethod{::F_CPU_GET_NB_FREQ}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FrequencyInMHz Northbridge clock frequency in MHz. - * @param[in] StdHeader Header for library and services. - * - * @return AGESA_SUCCESS FrequencyInMHz is valid. - */ -AGESA_STATUS -F15OrGetCurrentNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbFid; - UINT32 NbDid; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - if (OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader)) { - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_STATUS; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - NbFid = ((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbFid; - NbDid = ((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbDid; - *FrequencyInMHz = (((NbFid + 4) * 200) / (1 << NbDid)); - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the node's minimum and maximum northbridge frequency. - * - * @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[out] MinFreqInMHz The node's minimum northbridge frequency. - * @param[out] MaxFreqInMHz The node's maximum northbridge frequency. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Northbridge frequency is valid - */ -AGESA_STATUS -F15OrGetMinMaxNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - OUT UINT32 *MinFreqInMHz, - OUT UINT32 *MaxFreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - INT8 NbPsMaxVal; - UINT32 LocalPciRegister; - UINT32 FreqNumerator; - UINT32 FreqDivisor; - BOOLEAN CustomNbPs; - AGESA_STATUS AgesaStatus; - - CustomNbPs = FALSE; - AgesaStatus = AGESA_ERROR; - - // Obtain the max NB frequency on the node - PciAddress->Address.Function = FUNC_5; - PciAddress->Address.Register = NB_PSTATE_0; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) { - FreqNumerator = ((((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200); - FreqDivisor = (1 << ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid); - - *MaxFreqInMHz = (FreqNumerator / FreqDivisor); - AgesaStatus = AGESA_SUCCESS; - } - - // If platform configuration disable NB P-states, return the NB P0 frequency - // as both the min and max frequency on the node. - if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) { - *MinFreqInMHz = *MaxFreqInMHz; - } else { - PciAddress->Address.Function = FUNC_5; - PciAddress->Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - NbPsMaxVal = (INT8) ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal; - - // Obtain the min NB frequency on the node, starting from NB Pmin - for (; NbPsMaxVal >= 0; NbPsMaxVal--) { - PciAddress->Address.Function = FUNC_5; - PciAddress->Address.Register = (NB_PSTATE_0 + (4 * NbPsMaxVal)); - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - - // Ensure that the NB Pstate is enabled - if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) { - FreqNumerator = ((((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200); - FreqDivisor = (1 << ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid); - - *MinFreqInMHz = (FreqNumerator / FreqDivisor); - AgesaStatus = AGESA_SUCCESS; - break; - } - } - } - IDS_OPTION_HOOK (IDS_NBPS_MIN_FREQ, MinFreqInMHz, StdHeader); - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the NB clock on the desired node. - * - * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[in] NbPstate The NB P-state number to check. - * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. - * @param[out] FreqDivisor The desired node's frequency divisor. - * @param[out] VoltageInuV The desired node's voltage in microvolts. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE NbPstate is valid - * @retval FALSE NbPstate is disabled or invalid - */ -BOOLEAN -F15OrGetNbPstateInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - BOOLEAN PstateIsValid; - - PstateIsValid = FALSE; - - // If NB P1, P2, or P3 is requested, make sure that NB Pstate is enabled - if ((NbPstate == 0) || (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) { - PciAddress->Address.Function = FUNC_5; - PciAddress->Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - - if (NbPstate <= ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal) { - PciAddress->Address.Register = (NB_PSTATE_0 + (4 * NbPstate)); - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - - // Ensure that requested NbPstate is enabled - if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) { - *FreqNumeratorInMHz = ((((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200); - *FreqDivisor = (1 << ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid); - *VoltageInuV = (1550000 - (12500 * (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbVid))); - PstateIsValid = TRUE; - } - } - } - return PstateIsValid; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the number of physical cores of current processor. - * - * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The number of physical cores. - */ -UINT8 -F15OrGetNumberOfPhysicalCores ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CmpCap; - UINT32 CmpCapOnNode; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - CmpCap = 0; - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) { - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - CmpCapOnNode = (UINT8) (LocalPciRegister & 0xFF); - CmpCapOnNode++; - CmpCap += CmpCapOnNode; - } - } - return ((UINT8) CmpCap); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Use the Mailbox Register to get the Ap Mailbox info for the current core. - * - * @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}. - * - * Access the mailbox register used with this NB family. This is valid until the - * point that some init code initializes the mailbox register for its normal use. - * The Machine Check Misc (Thresholding) register is available as both a PCI config - * register and a MSR, so it can be used as a mailbox from HT to other functions. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] ApMailboxInfo The AP Mailbox info - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F15OrGetApMailboxFromHardware ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MailboxInfo; - - LibAmdMsrRead (MSR_MC_MISC_LINK_THRESHOLD, &MailboxInfo, StdHeader); - // Mailbox info is in bits 32 thru 43, 12 bits. - ApMailboxInfo->ApMailInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF); - LibAmdMsrRead (MSR_MC_MISC_L3_THRESHOLD, &MailboxInfo, StdHeader); - // Mailbox info is in bits 32 thru 43, 12 bits. - ApMailboxInfo->ApMailExtInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Set the system AP core number in the AP's Mailbox. - * - * @CpuServiceMethod{::F_CPU_SET_AP_CORE_NUMBER}. - * - * Access the mailbox register used with this NB family. This is only intended to - * run on the BSC at the time of initial AP launch. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Socket The AP's socket - * @param[in] Module The AP's module - * @param[in] ApCoreNumber The AP's unique core number - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F15OrSetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 ApCoreNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x170; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((AP_MAIL_EXT_INFO *) &LocalPciRegister)->Fields.HeapIndex = ApCoreNumber; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Get this AP's system core number from hardware. - * - * @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}. - * - * Returns the system core number from the scratch MSR, where - * it was saved at heap initialization. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The AP's unique core number - */ -UINT32 -F15OrGetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - NODE_ID_MSR NodeIdMsr; - - LibAmdMsrRead (0xC001100C, &NodeIdMsr.Value, StdHeader); - return (UINT32) NodeIdMsr.Fields.BiosScratch; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Move the AP's core number from the mailbox to hardware. - * - * @CpuServiceMethod{::F_CPU_TRANSFER_AP_CORE_NUMBER}. - * - * Transfers this AP's system core number from the mailbox to - * the NodeId MSR and initializes the other NodeId fields. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F15OrTransferApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_MAILBOXES Mailboxes; - NODE_ID_MSR NodeIdMsr; - UINT64 ExtFeatures; - - NodeIdMsr.Value = 0; - FamilySpecificServices->GetApMailboxFromHardware (FamilySpecificServices, &Mailboxes, StdHeader); - NodeIdMsr.Fields.BiosScratch = Mailboxes.ApMailExtInfo.Fields.HeapIndex; - NodeIdMsr.Fields.NodeId = Mailboxes.ApMailInfo.Fields.Node; - NodeIdMsr.Fields.NodesPerProcessor = Mailboxes.ApMailInfo.Fields.ModuleType; - LibAmdMsrWrite (0xC001100C, &NodeIdMsr.Value, StdHeader); - - // Indicate that the NodeId MSR is supported. - LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader); - ExtFeatures = (ExtFeatures | BIT51); - LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Disable NB P-state. - * - clear F5x1[6C:64] - * - clear F5x170[NbPstateMaxVal] - * - set F5x170[SwNbPstateLoDis] - * - clear MSRC001_00[6B:64][NbPstate] - * - * @param[in] FamilySpecificServices The current Family Specific Services - * @param[in] CpuEarlyParamsPtr Service Parameters - * @param[in] StdHeader Handle of Header for calling lib functions and services. - */ -VOID -F15OrNbPstateDis ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 PciData; - UINT32 AndMask; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - - // Check whether NB P-state is disabled - if (!FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) { - - IDS_HDT_CONSOLE (CPU_TRACE, " NB Pstates disabled\n"); - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - - AndMask = 0x00000000; - // If NbPstateHi is not NB P0, get the Pstate pointed to by NbPstateHi and copy it's value to NB P0 - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - if (((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateHi != 0) { - PciAddress.Address.Register = NB_PSTATE_0 + (((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateHi * 4); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - PciAddress.Address.Register = NB_PSTATE_0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, PciData, StdHeader); - } - - // Clear F5x1[6C:64] - for (i = 1; i < NM_NB_PS_REG; i++) { - PciAddress.Address.Register = NB_PSTATE_0 + (i * 4); - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, AndMask, StdHeader); - } - - // Clear F5x170[NbPstateMaxVal] and set F5x170[SwNbPstateLoDis] - PciAddress.Address.Register = NB_PSTATE_CTRL; - AndMask = 0xFFFFFFFF; - PciData = 0x00000000; - ((NB_PSTATE_CTRL_REGISTER *) &AndMask)->NbPstateMaxVal = 0; - ((NB_PSTATE_CTRL_REGISTER *) &PciData)->SwNbPstateLoDis = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, PciData, StdHeader); - - // Clear MSRC001_00[6B:64][NbPstate] on cores - TaskPtr.FuncAddress.PfApTask = F15OrNbPstateDisCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.DataTransfer.DataPtr = NULL; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - - // Once we are done disabling NB Pstates, clear F5x170[SwNbPstateLoDis] - AndMask = 0xFFFFFFFF; - PciData = 0x00000000; - ((NB_PSTATE_CTRL_REGISTER *) &AndMask)->SwNbPstateLoDis = 0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, PciData, StdHeader); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Disable NB P-state on core. - * - clear MSRC001_00[6B:64][NbPstate]. - * - * @param[in] StdHeader Handle of Header for calling lib functions and services. - */ -VOID -STATIC -F15OrNbPstateDisCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT64 MsrData; - - // Only one core per compute unit needs to clear NbPstate in P-state MSRs - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - for (i = MSR_PSTATE_0; i <= MSR_PSTATE_7; i++) { - LibAmdMsrRead (i, &MsrData, StdHeader); - ((PSTATE_MSR *) &MsrData)->NbPstate = 0; - LibAmdMsrWrite (i, &MsrData, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * A Family Specific Workaround method, to override CPU TDP Limit 2 setting. - * - * \@TableTypeFamSpecificInstances. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config params for library, services. - */ -VOID -F15OrOverrideNodeTdpLimit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 OrMask; - UINT32 LocalPciRegister; - BOOLEAN IsMultiNodeCpu; - PCI_ADDR PciAddress; - - IsMultiNodeCpu = FALSE; - // check if it is MCM part - if (OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - IsMultiNodeCpu = (BOOLEAN) (((NB_CAPS_REGISTER *) &LocalPciRegister)->MultiNodeCpu == 1); - } - - if (IsMultiNodeCpu) { - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = 0x10C; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - // The correct value is the half of the fused value - OrMask = LocalPciRegister & 0xFFFFF000; - LocalPciRegister = ((LocalPciRegister & 0x00000FFF) >> 1) | OrMask; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * A Family Specific Workaround method, to override CPU Node TDP Accumulator Throttle Threshold setting. - * - * \@TableTypeFamSpecificInstances. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config params for library, services. - */ -VOID -F15OrOverrideNodeTdpAccumulatorThrottleThreshold ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 CmpCap; - UINT32 OrMask; - UINT32 CUStatus; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - if (OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader)) { - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = 0x84; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - CmpCap = (UINT8) (LocalPciRegister & 0x000000FF); - CmpCap++; - - // check if the part is fused with 1 core enabled per compute unit - PciAddress.Address.Register = 0x80; - LibAmdPciRead (AccessWidth32, PciAddress, &CUStatus, StdHeader); - if ((CUStatus & 0x000F0000) != 0) { - CmpCap = CmpCap >> 1; - } - - PciAddress.Address.Register = 0xBC; - LibAmdPciRead (AccessWidth32, PciAddress, &OrMask, StdHeader); - OrMask = (UINT32) ((OrMask & 0x000FFFFF) * CmpCap); - - PciAddress.Address.Register = 0xB4; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - // The correct value is F5xBC[CmpUnitTdpAccThrottleThreshold] x ((F5x84[CmpCap] + 1) / 2). - LocalPciRegister = (LocalPciRegister & 0xFFF00000) | (OrMask & 0x000FFFFF); - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * A Family Specific Workaround method, to sync internal node 1 SbiAddr setting. - * - * \@TableTypeFamSpecificInstances. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config params for library, services. - */ -VOID -F15OrSyncInternalNode1SbiAddr ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 DataOr; - UINT32 DataAnd; - UINT32 ModuleType; - PCI_ADDR PciAddress; - AGESA_STATUS AgesaStatus; - UINT32 SyncToModule; - AP_MAIL_INFO ApMailboxInfo; - UINT32 LocalPciRegister; - - ApMailboxInfo.Info = 0; - - GetApMailbox (&ApMailboxInfo.Info, StdHeader); - ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS); - ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES); - Socket = ApMailboxInfo.Fields.Socket; - Module = ApMailboxInfo.Fields.Module; - ModuleType = ApMailboxInfo.Fields.ModuleType; - - // sync is just needed on multinode cpu - if (ModuleType != 0) { - // check if it is internal node 0 of every socket - if (Module == 0) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x1E4; - // read internal node 0 F3x1E4[6:4] - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - DataOr = LocalPciRegister & ((UINT32) (7 << 4)); - DataAnd = ~(UINT32) (7 << 4); - for (SyncToModule = 1; SyncToModule < GetPlatformNumberOfModules (); SyncToModule++) { - if (GetPciAddress (StdHeader, Socket, SyncToModule, &PciAddress, &AgesaStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x1E4; - // sync the other internal node F3x1E4[6:4] - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LocalPciRegister &= DataAnd; - LocalPciRegister |= DataOr; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } - } - } - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.h deleted file mode 100644 index a52491a2b4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.h +++ /dev/null @@ -1,169 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi specific utility functions. - * - * Provides numerous utility functions specific to family 15h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 57155 $ @e \$Date: 2011-07-28 02:27:47 -0600 (Thu, 28 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _F15_OR_UTILITES_H_ -#define _F15_OR_UTILITES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -UINT8 -F15OrGetNumberOfPhysicalCores ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrGetApMailboxFromHardware ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrNbPstateDis ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15OrGetProcIddMax ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 Pstate, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetCurrentNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetMinMaxNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - OUT UINT32 *MinFreqInMHz, - OUT UINT32 *MaxFreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15OrGetNbPstateInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrSetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 ApCoreNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -F15OrGetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrTransferApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrOverrideNodeTdpLimit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrOverrideNodeTdpAccumulatorThrottleThreshold ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrSyncInternalNode1SbiAddr ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _F15_OR_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrWorkaroundsTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrWorkaroundsTable.c deleted file mode 100644 index 7ee0a2d32f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrWorkaroundsTable.c +++ /dev/null @@ -1,134 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Models 0x00 - 0x0F Specific Workaround table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x15/OR - * @e \$Revision: 57155 $ @e \$Date: 2011-07-28 02:27:47 -0600 (Thu, 28 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15Utilities.h" -#include "F15OrUtilities.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORWORKAROUNDSTABLE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// F a m i l y S p e c i f i c W o r k a r o u n d T a b l e s -// ----------------------------------------------------------------- - -STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15OrWorkarounds[] = -{ -// F0x6C - Link Initialization Control Register -// Request for warm reset in AmdInitEarly -// [5, BiosRstDet] = 1b - { - FamSpecificWorkaround, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - SetWarmResetAtEarly, // function call - 0x00000000, // data - }} - }, - // HT PHY DLL Compensation setting for rev B and later - { - FamSpecificWorkaround, - { - AMD_FAMILY_15, - AMD_F15_OR_GT_Ax - }, - {AMD_PF_ALL}, - {{ - F15HtPhyOverrideDllCompensation, - 0x00000001 - }} - }, - // Internal Node 1 SbiAddr sync for OR - { - FamSpecificWorkaround, - { - AMD_FAMILY_15_OR, - AMD_F15_OR_ALL - }, - {AMD_PF_ALL}, - {{ - F15OrSyncInternalNode1SbiAddr, - 0x00000000 - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrWorkaroundsTable = { - PrimaryCores, - (sizeof (F15OrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *)F15OrWorkarounds, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/Makefile.inc deleted file mode 100644 index f28c5f7d09..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/Makefile.inc +++ /dev/null @@ -1,32 +0,0 @@ -libagesa-y += F15OrC6State.c -libagesa-y += F15OrCpb.c -libagesa-y += F15OrEarlySamples.c -libagesa-y += F15OrEquivalenceTable.c -libagesa-y += F15OrHtPhyTables.c -libagesa-y += F15OrInitEarlyTable.c -libagesa-y += F15OrIoCstate.c -libagesa-y += F15OrL3Features.c -libagesa-y += F15OrLogicalIdTables.c -libagesa-y += F15OrLowPwrPstate.c -libagesa-y += F15OrMicrocodePatch06000425.c -libagesa-y += F15OrMicrocodePatch0600050D_Enc.c -libagesa-y += F15OrMicrocodePatch06000624_Enc.c -libagesa-y += F15OrMicrocodePatchTables.c -libagesa-y += F15OrMsgBasedC1e.c -libagesa-y += F15OrMsrTables.c -libagesa-y += F15OrMultiLinkPciTables.c -libagesa-y += F15OrPciTables.c -libagesa-y += F15OrPmNbCofVidInit.c -libagesa-y += F15OrPowerMgmtSystemTables.c -libagesa-y += F15OrPowerPlane.c -libagesa-y += F15OrSharedMsrTable.c -libagesa-y += F15OrSingleLinkPciTables.c -libagesa-y += F15OrUtilities.c -libagesa-y += F15OrWorkaroundsTable.c -libagesa-y += cpuF15OrCacheFlushOnHalt.c -libagesa-y += cpuF15OrCoreAfterReset.c -libagesa-y += cpuF15OrDmi.c -libagesa-y += cpuF15OrFeatureLeveling.c -libagesa-y += cpuF15OrNbAfterReset.c -libagesa-y += cpuF15OrPstate.c -libagesa-y += cpuF15OrSoftwareThermal.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c deleted file mode 100644 index 1692eb9d44..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c +++ /dev/null @@ -1,184 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Cache Flush On Halt Function for Family 15h Orochi. - * - * Contains code to initialize Cache Flush On Halt feature for Family 15h Orochi. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - *---------------------------------------------------------------------------- - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuPostInit.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuFeatures.h" -#include "F15PackageType.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORCACHEFLUSHONHALT_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -SetF15OrCacheFlushOnHaltRegister ( - IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * Enable Cpu Cache Flush On Halt Function - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - */ -VOID -SetF15OrCacheFlushOnHaltRegister ( - IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 AndMask; - UINT32 OrMask; - PCI_ADDR PciAddress; - - if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { - // Set D18F3xDC[CacheFlushOnHaltCtl] != 0 - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - OrMask = 0; - AndMask = 0xFC00FFFF; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->CacheFlushOnHaltCtl = 7; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->CacheFlushOnHaltTmr = 0x28; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC - - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CSTATE_CTRL1_REG; - OrMask = 0; - AndMask = 0xFF11FF11; - // D18F4x118[CpuPrbEnCstAct0] = 1 - // D18F4x118[CpuPrbEnCstAct1] = 1 - // D18F4x118[CacheFlushEnCstAct0] = 1 - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CpuPrbEnCstAct0 = 1; - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CpuPrbEnCstAct1 = 1; - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushEnCstAct0 = 1; - - // Set C-state Action Field 0 - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushTmrSelCstAct0 = 2; - // Set C-state Action Field 1 - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushEnCstAct1 = 1; - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushTmrSelCstAct1 = 1; - - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x118 - - // D18F4x128[CacheFlushSucMonThreshold] = 0 - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CSTATE_POLICY_CTRL1_REG; - OrMask = 0; - AndMask = 0xFFFFFFFF; - ((CSTATE_POLICY_CTRL1_REGISTER *) &AndMask)->CacheFlushSucMonThreshold = 0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x128 - - // D18F3x84[ClkDivisorSmafAct7] = 0 - // D18F3x84[CpuPrbEnSmafAct7] = 1 - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = ACPI_PWR_STATE_CTRL_HI_REG; - OrMask = 0; - AndMask = 0xFFFFFFFF; - ((ACPI_PWR_STATE_CTRL_HI_REGISTER *) &AndMask)->ClkDivisorSmafAct7 = 0; - ((ACPI_PWR_STATE_CTRL_HI_REGISTER *) &OrMask)->CpuPrbEnSmafAct7 = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x84 - - //Override the default setting - IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader); - } -} - -CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt = -{ - 0, - SetF15OrCacheFlushOnHaltRegister -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c deleted file mode 100644 index 4e763517e2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c +++ /dev/null @@ -1,250 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi after warm reset sequence for core P-states - * - * Performs the "Core Minimum P-State Transition Sequence After Warm Reset" - * as described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "OptionMultiSocket.h" -#include "cpuF15OrCoreAfterReset.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORCOREAFTERRESET_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrPmCoreAfterResetPhase1OnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F15OrPmCoreAfterResetPhase2OnCore ( - IN VOID *HwPsMaxVal, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------*/ -/** - * Family 15h Orochi core 0 entry point for performing the necessary steps for core - * P-states after a warm reset has occurred. - * - * The steps are as follows: - * 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. - * 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from - * MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit]. - * 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all - * cores in the processor. - * 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from - * MSRC001_00[6B:64] indexed by MSRC001_0061[PstateMaxVal]. - * 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for - * MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by - * MSRC001_0061[PstateMaxVal]. - * 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd]. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrPmCoreAfterReset ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Core; - UINT32 HwPsMaxVal; - PCI_ADDR PciAddress; - AP_TASK TaskPtr; - IDS_SKIP_HOOK (IDS_SKIP_PM_TRANSITION_STEP, CpuEarlyParamsPtr, StdHeader) { - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - GetCurrentCore (&Core, StdHeader); - ASSERT (Core == 0); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader); - HwPsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal; - - // Launch each local core to perform steps 1 through 3. - TaskPtr.FuncAddress.PfApTask = F15OrPmCoreAfterResetPhase1OnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - - // Launch each local core to perform steps 4 through 6. - TaskPtr.FuncAddress.PfApTaskI = F15OrPmCoreAfterResetPhase2OnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 1; - TaskPtr.DataTransfer.DataPtr = &HwPsMaxVal; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - } -} - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmCoreAfterReset to perform MSR initialization on all - * cores of a family 15h socket. - * - * This function implements steps 1 - 3 on each core. - * - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15OrPmCoreAfterResetPhase1OnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 CofvidSts; - UINT64 LocalMsrRegister; - UINT64 PstateCtrl; - - // 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. - PstateCtrl = 0; - LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); - - // 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from - // MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit]. - do { - LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader); - LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader); - } while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) || - (((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid)); - - // 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all - // cores in the processor. - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd = ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal; - LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmCoreAfterReset to perform MSR initialization on all - * cores of a family 15h socket. - * - * This function implements steps 4 - 6 on each core. - * - * @param[in] HwPsMaxVal Index of the highest enabled HW P-state. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15OrPmCoreAfterResetPhase2OnCore ( - IN VOID *HwPsMaxVal, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 TargetPsMsr; - UINT64 LocalMsrRegister; - UINT64 PstateCtrl; - - // 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from - // MSRC001_00[6B:64] indexed by D18F3xDC[PstateMaxVal]. - LibAmdMsrRead ((*(UINT32 *) HwPsMaxVal) + MSR_PSTATE_0, &TargetPsMsr, StdHeader); - do { - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - } while ((((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) || - (((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid)); - - // 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for - // MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by - // MSRC001_0061[PstateMaxVal]. - if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstateLimit != ((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstate) { - do { - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - } while ((((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuVid != ((PSTATE_MSR *) &TargetPsMsr)->CpuVid)); - } - - // 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd]. - LibAmdMsrRead (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); - do { - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.h deleted file mode 100644 index a2a3e748f0..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi after warm reset sequence for core P-states - * - * Contains code that provide power management functionality - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_CORE_AFTER_RESET_H_ -#define _CPU_F15_OR_CORE_AFTER_RESET_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrPmCoreAfterReset ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F15_OR_CORE_AFTER_RESET_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c deleted file mode 100644 index 838612acbd..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c +++ /dev/null @@ -1,422 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD DMI Record Creation API, and related functions for Fmaily15h Orichi. - * - * Contains code that produce the DMI related information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 58290 $ @e \$Date: 2011-08-25 00:02:47 -0600 (Thu, 25 Aug 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuLateInit.h" -#include "cpuF15Dmi.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuServices.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORDMI_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -CONST CHAR8 ROMDATA str_Opteron_62[] = "AMD Opteron(tm) Processor 62"; -CONST CHAR8 ROMDATA str_Opteron_63[] = "AMD Opteron(tm) Processor 63"; -CONST CHAR8 ROMDATA str_Opteron_42[] = "AMD Opteron(tm) Processor 42"; -CONST CHAR8 ROMDATA str_Opteron_3[] = "AMD Opteron(tm) Processor 3"; -CONST CHAR8 ROMDATA str_FX_AM3[] = "AMD FX(tm)-"; -/*--------------------------------------------------------------------------------------- - * Processor Family Table - * 03Dh = "AMD Opteron(TM) 6200 Processor Family" - * 04Dh = "AMD Opteron(TM) 6300 Processor Family" - * 03Eh = "AMD Opteron(TM) 4200 Processor Family" - * 03Fh = "AMD FX(TM) Series Processor" - *-------------------------------------------------------------------------------------*/ -CONST CPU_T4_PROC_FAMILY ROMDATA F15OrG34T4ProcFamily[] = -{ - {str_Opteron_62, 0x3D}, - {str_Opteron_63, 0x4D} -}; - -CONST CPU_T4_PROC_FAMILY ROMDATA F15OrC32T4ProcFamily[] = -{ - {str_Opteron_42, 0x3E} -}; - -CONST CPU_T4_PROC_FAMILY ROMDATA F15OrAM3T4ProcFamily[] = -{ - {str_FX_AM3, 0x3F}, - {str_Opteron_3, 0xE4} -}; -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -DmiF15OrGetInfo ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -DmiF15OrGetT4ProcFamily ( - IN OUT UINT8 *T4ProcFamily, - IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, - IN CPU_TYPE_INFO *CpuInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -DmiF15OrGetVoltage ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -DmiF15OrGetMemInfo ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT16 -DmiF15OrGetExtClock ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF15OrGetInfo - * - * Get CPU type information - * - * @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct. - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF15OrGetInfo ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumOfCoresPerCU; - CPUID_DATA CpuId; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); - CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20 - CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16 - CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8 - CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4 - CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0 - - CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 - // Family 15h Orochi doesn't have CPUID_8000_0001_EBX[BrandId] - CpuInfoPtr->BrandId.Pg = 0; - CpuInfoPtr->BrandId.String1 = 0; - CpuInfoPtr->BrandId.Model = 0; - CpuInfoPtr->BrandId.String2 = 0; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader); - CpuInfoPtr->TotalCoreNumber--; - - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader); - CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0 - - switch (CpuInfoPtr->PackageType) { - case OR_SOCKET_AM3: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_AM3; - break; - case OR_SOCKET_G34: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_G34; - break; - case OR_SOCKET_C32: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_C32; - break; - default: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN; - break; - } - - switch (GetComputeUnitMapping (StdHeader)) { - case AllCoresMapping: - NumOfCoresPerCU = 1; - break; - case EvenCoresMapping: - NumOfCoresPerCU = 2; - break; - default: - NumOfCoresPerCU = 2; - } - LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, StdHeader); - CpuInfoPtr->L1CacheSize = (UINT32) (((UINT8) ((CpuId.ECX_Reg >> 24) * NumOfCoresPerCU) + (UINT8) (CpuId.EDX_Reg >> 24)) * (CpuInfoPtr->EnabledCoreNumber + 1) / NumOfCoresPerCU); - - LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader); - CpuInfoPtr->L2CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfoPtr->EnabledCoreNumber + 1) / NumOfCoresPerCU); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF15OrGetT4ProcFamily - * - * Get type 4 processor family information - * - * @param[in,out] T4ProcFamily Pointer to type 4 processor family information. - * @param[in] *CpuDmiProcFamilyTable Pointer to DMI family special service - * @param[in] *CpuInfo Pointer to CPU_TYPE_INFO struct - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF15OrGetT4ProcFamily ( - IN OUT UINT8 *T4ProcFamily, - IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, - IN CPU_TYPE_INFO *CpuInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CHAR8 NameString[49]; - CONST CHAR8 *DmiString; - CONST VOID *DmiStringTable; - UINT8 NumberOfDmiString; - UINT8 i; - - // Get name string from MSR_C001_00[30:35] - GetNameString (NameString, StdHeader); - // Get DMI String - DmiStringTable = NULL; - switch (CpuInfo->PackageType) { - case OR_SOCKET_G34: - DmiStringTable = (CONST VOID *) &F15OrG34T4ProcFamily[0]; - NumberOfDmiString = sizeof (F15OrG34T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); - break; - case OR_SOCKET_C32: - DmiStringTable = (CONST VOID *) &F15OrC32T4ProcFamily[0]; - NumberOfDmiString = sizeof (F15OrC32T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); - break; - case OR_SOCKET_AM3: - DmiStringTable = (CONST VOID *) &F15OrAM3T4ProcFamily[0]; - NumberOfDmiString = sizeof (F15OrAM3T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); - break; - default: - DmiStringTable = NULL; - NumberOfDmiString = 0; - break; - } - - // Find out which DMI string matches currect processor's name string - *T4ProcFamily = P_FAMILY_UNKNOWN; - if ((DmiStringTable != NULL) && (NumberOfDmiString != 0)) { - for (i = 0; i < NumberOfDmiString; i++) { - DmiString = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).Stringstart; - if (IsSourceStrContainTargetStr (NameString, DmiString, StdHeader)) { - *T4ProcFamily = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).T4ProcFamilySetting; - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF15OrGetVoltage - * - * Get the voltage value according to SMBIOS SPEC's requirement. - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval Voltage - CPU Voltage. - * - */ -UINT8 -DmiF15OrGetVoltage ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxVid; - UINT8 Voltage; - UINT8 NumberBoostStates; - UINT32 CurrentNodeNum; - UINT64 MsrData; - PCI_ADDR TempAddr; - CPB_CTRL_REGISTER CpbCtrl; - - // Voltage = 0x80 + (voltage at boot time * 10) - GetCurrentNodeNum (&CurrentNodeNum, StdHeader); - TempAddr.AddressValue = MAKE_SBDFO (0, 0, (24 + CurrentNodeNum), FUNC_4, CPB_CTRL_REG); - LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C - NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates; - - LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); - MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); - - - if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) { - Voltage = 0; - } else { - Voltage = (UINT8) ((15500 - (125 * MaxVid) + 500) / 1000); - } - - Voltage += 0x80; - return (Voltage); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF15OrGetMemInfo - * - * Get memory information. - * - * @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct. - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF15OrGetMemInfo ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 PciData; - PCI_ADDR PciAddress; - - CpuGetMemInfoPtr->EccCapable = FALSE; - // Orochi uses the different way of access to each DCT - // - // Switch to DCT 0 - // - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_1, 0x10C); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - PciData &= 0xFFFFFFFE; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x90); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - // Check if F2x90[DimmEccEn] is set - if ((PciData & 0x00080000) != 0) { - CpuGetMemInfoPtr->EccCapable = TRUE; - } else { - // - // Switch to DCT 1 - // - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_1, 0x10C); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - PciData |= 0x00000001; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x90); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - // Check if F2x90[DimmEccEn] is set - if ((PciData & 0x00080000) != 0) { - CpuGetMemInfoPtr->EccCapable = TRUE; - } - } - // Errata #505 - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_1, 0x10C); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - PciData &= 0xFFFFFFFE; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); - // Partition Row Position - 0 is for dual channel memory - CpuGetMemInfoPtr->PartitionRowPosition = 0; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF15OrGetExtClock - * - * Get the external clock Speed - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval ExtClock - CPU external clock Speed. - * - */ -UINT16 -DmiF15OrGetExtClock ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (EXTERNAL_CLOCK_DFLT); -} - -CONST PROC_FAMILY_TABLE ROMDATA ProcFamily15OrDmiTable = -{ -// This table is for Processor family 15h Orochi - AMD_FAMILY_15_OR, // ID for Family 15h Orochi - DmiF15OrGetInfo, // Transfer vectors for family - DmiF15OrGetT4ProcFamily, // Get type 4 processor family information - DmiF15OrGetVoltage, // specific routines (above) - DmiF15GetMaxSpeed, - DmiF15OrGetExtClock, - DmiF15OrGetMemInfo, // Get memory information - 0, - NULL -}; - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c deleted file mode 100644 index b1aa42f173..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c +++ /dev/null @@ -1,422 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi specific feature leveling functions. - * - * Provides feature leveling functions specific to family 15h models 00h-0Fh. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 45341 $ @e \$Date: 2011-01-14 15:49:18 -0700 (Fri, 14 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuPostInit.h" -#include "cpuF15OrFeatureLeveling.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORFEATURELEVELING_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -cpuFeatureListNeedUpdate ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ); - -VOID -STATIC -updateCpuFeatureList ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function get features which CPU supports. - * - * @CpuServiceMethod{::F_CPU_SAVE_FEATURES}. - * - * Read features from MSR_C0011004 and MSR_C0011005. - * - * @param[in] FamilySpecificServices - Pointer to CPU_SPECIFIC_SERVICES struct. - * @param[in,out] cpuFeatureList - Pointer to CPU_FEATURES_LIST struct. - * @param[in] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -F15OrSaveFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 CpuMsrData; - BOOLEAN *FirstTime; - BOOLEAN *NeedLeveling; - CPU_F15_OR_FEATURES *CpuF15OrFeatures; - CPU_F15_OR_EXT_FEATURES *CpuF15OrExtFeatures; - CPU_FEATURES_LIST thisCoreCpuFeatureList; - - FirstTime = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST)); - NeedLeveling = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN)); - - LibAmdMemFill (&thisCoreCpuFeatureList, 0x0, sizeof (CPU_FEATURES_LIST), StdHeader); - LibAmdMsrRead (MSR_CPUID_FEATS, &CpuMsrData, StdHeader); - CpuF15OrFeatures = (CPU_F15_OR_FEATURES *) &CpuMsrData; - - thisCoreCpuFeatureList.APIC = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.APIC; - thisCoreCpuFeatureList.CLFSH = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.CLFSH; - thisCoreCpuFeatureList.CMOV = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.CMOV; - thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.CMPXCHG8B; - thisCoreCpuFeatureList.DE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.DE; - thisCoreCpuFeatureList.FPU = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.FPU; - thisCoreCpuFeatureList.FXSR = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.FXSR; - thisCoreCpuFeatureList.HTT = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.HTT; - thisCoreCpuFeatureList.MCA = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.MCA; - thisCoreCpuFeatureList.MCE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.MCE; - thisCoreCpuFeatureList.MMX = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.MMX; - thisCoreCpuFeatureList.MSR = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.MSR; - thisCoreCpuFeatureList.MTRR = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.MTRR; - thisCoreCpuFeatureList.PAE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.PAE; - thisCoreCpuFeatureList.PAT = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.PAT; - thisCoreCpuFeatureList.PGE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.PGE; - thisCoreCpuFeatureList.PSE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.PSE; - thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.PSE36; - thisCoreCpuFeatureList.SSE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.SSE; - thisCoreCpuFeatureList.SSE2 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.SSE2; - thisCoreCpuFeatureList.SysEnterSysExit = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.SysEnterSysExit; - thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.TimeStampCounter; - thisCoreCpuFeatureList.VME = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.VME; - - thisCoreCpuFeatureList.AES = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.AES; - thisCoreCpuFeatureList.AVX = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.AVX; - thisCoreCpuFeatureList.CMPXCHG16B = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.CMPXCHG16B; - thisCoreCpuFeatureList.Monitor = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.Monitor; - thisCoreCpuFeatureList.OSXSAVE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.OSXSAVE; - thisCoreCpuFeatureList.PCLMULQDQ = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.PCLMULQDQ; - thisCoreCpuFeatureList.POPCNT = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.POPCNT; - thisCoreCpuFeatureList.SSE3 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE3; - thisCoreCpuFeatureList.SSE41 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE41; - thisCoreCpuFeatureList.SSE42 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE42; - thisCoreCpuFeatureList.SSSE3 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.SSSE3; - thisCoreCpuFeatureList.X2APIC = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.X2APIC; - thisCoreCpuFeatureList.XSAVE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.XSAVE; - - LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader); - CpuF15OrExtFeatures = (CPU_F15_OR_EXT_FEATURES *) &CpuMsrData; - - thisCoreCpuFeatureList.ThreeDNow = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.ThreeDNow; - thisCoreCpuFeatureList.ThreeDNowExt = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.ThreeDNowExt; - thisCoreCpuFeatureList.APIC = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.APIC; - thisCoreCpuFeatureList.CMOV = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.CMOV; - thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.CMPXCHG8B; - thisCoreCpuFeatureList.DE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.DE; - thisCoreCpuFeatureList.FFXSR = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FFXSR; - thisCoreCpuFeatureList.FPU = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FPU; - thisCoreCpuFeatureList.FXSR = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FXSR; - thisCoreCpuFeatureList.LM = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.LM; - thisCoreCpuFeatureList.MCA = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MCA; - thisCoreCpuFeatureList.MCE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MCE; - thisCoreCpuFeatureList.MMX = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MMX; - thisCoreCpuFeatureList.MmxExt = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MmxExt; - thisCoreCpuFeatureList.MSR = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MSR; - thisCoreCpuFeatureList.MTRR = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MTRR; - thisCoreCpuFeatureList.NX = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.NX; - thisCoreCpuFeatureList.PAE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PAE; - thisCoreCpuFeatureList.Page1GB = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.Page1GB; - thisCoreCpuFeatureList.PAT = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PAT; - thisCoreCpuFeatureList.PGE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PGE; - thisCoreCpuFeatureList.PSE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PSE; - thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PSE36; - thisCoreCpuFeatureList.RDTSCP = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.RDTSCP; - thisCoreCpuFeatureList.SysCallSysRet = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.SysCallSysRet; - thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.TimeStampCounter; - thisCoreCpuFeatureList.VME = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.VME; - - thisCoreCpuFeatureList.ThreeDNowPrefetch = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ThreeDNowPrefetch; - thisCoreCpuFeatureList.ABM = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ABM; - thisCoreCpuFeatureList.AltMovCr8 = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.AltMovCr8; - thisCoreCpuFeatureList.CmpLegacy = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.CmpLegacy; - thisCoreCpuFeatureList.ExtApicSpace = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ExtApicSpace; - thisCoreCpuFeatureList.IBS = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.IBS; - thisCoreCpuFeatureList.LahfSahf = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.LahfSahf; - thisCoreCpuFeatureList.MisAlignSse = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.MisAlignSse; - thisCoreCpuFeatureList.OSVW = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.OSVM; - thisCoreCpuFeatureList.SKINIT = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SKINIT; - thisCoreCpuFeatureList.SSE4A = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SSE4A; - thisCoreCpuFeatureList.SVM = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SVM; - thisCoreCpuFeatureList.WDT = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.WDT; - thisCoreCpuFeatureList.NodeId = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.NodeId; - thisCoreCpuFeatureList.XOP = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.XOP; - thisCoreCpuFeatureList.TBM0 = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.TBM0; - thisCoreCpuFeatureList.LWP = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.LWP; - thisCoreCpuFeatureList.FMA4 = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.FMA4; - thisCoreCpuFeatureList.TCE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.TCE; - - if (*FirstTime) { - updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList); - *FirstTime = FALSE; - } else if (cpuFeatureListNeedUpdate (cpuFeatureList, &thisCoreCpuFeatureList)) { - updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList); - *NeedLeveling = TRUE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function set features which All CPUs support. - * - * @CpuServiceMethod{::F_CPU_WRITE_FEATURES}. - * - * Write least common features to MSR_C0011004 and MSR_C0011005. - * - * @param[in] FamilySpecificServices - Pointer to CPU_SPECIFIC_SERVICES struct. - * @param[in,out] cpuFeatureList - Pointer to CPU_FEATURES_LIST struct. - * @param[in] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -F15OrWriteFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 CpuMsrData; - CPU_F15_OR_FEATURES *CpuF15OrFeatures; - CPU_F15_OR_EXT_FEATURES *CpuF15OrExtFeatures; - - CpuMsrData = 0; - CpuF15OrFeatures = (CPU_F15_OR_FEATURES *) &CpuMsrData; - - CpuF15OrFeatures->CpuF15OrFeaturesLo.APIC = cpuFeatureList->APIC; - CpuF15OrFeatures->CpuF15OrFeaturesLo.CLFSH = cpuFeatureList->CLFSH; - CpuF15OrFeatures->CpuF15OrFeaturesLo.CMOV = cpuFeatureList->CMOV; - CpuF15OrFeatures->CpuF15OrFeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B; - CpuF15OrFeatures->CpuF15OrFeaturesLo.DE = cpuFeatureList->DE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.FPU = cpuFeatureList->FPU; - CpuF15OrFeatures->CpuF15OrFeaturesLo.FXSR = cpuFeatureList->FXSR; - CpuF15OrFeatures->CpuF15OrFeaturesLo.HTT = cpuFeatureList->HTT; - CpuF15OrFeatures->CpuF15OrFeaturesLo.MCA = cpuFeatureList->MCA; - CpuF15OrFeatures->CpuF15OrFeaturesLo.MCE = cpuFeatureList->MCE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.MMX = cpuFeatureList->MMX; - CpuF15OrFeatures->CpuF15OrFeaturesLo.MSR = cpuFeatureList->MSR; - CpuF15OrFeatures->CpuF15OrFeaturesLo.MTRR = cpuFeatureList->MTRR; - CpuF15OrFeatures->CpuF15OrFeaturesLo.PAE = cpuFeatureList->PAE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.PAT = cpuFeatureList->PAT; - CpuF15OrFeatures->CpuF15OrFeaturesLo.PGE = cpuFeatureList->PGE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.PSE = cpuFeatureList->PSE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.PSE36 = cpuFeatureList->PSE36; - CpuF15OrFeatures->CpuF15OrFeaturesLo.SSE = cpuFeatureList->SSE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.SSE2 = cpuFeatureList->SSE2; - CpuF15OrFeatures->CpuF15OrFeaturesLo.SysEnterSysExit = cpuFeatureList->SysEnterSysExit; - CpuF15OrFeatures->CpuF15OrFeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter; - CpuF15OrFeatures->CpuF15OrFeaturesLo.VME = cpuFeatureList->VME; - - CpuF15OrFeatures->CpuF15OrFeaturesHi.AES = cpuFeatureList->AES; - CpuF15OrFeatures->CpuF15OrFeaturesHi.AVX = cpuFeatureList->AVX; - CpuF15OrFeatures->CpuF15OrFeaturesHi.CMPXCHG16B = cpuFeatureList->CMPXCHG16B; - CpuF15OrFeatures->CpuF15OrFeaturesHi.Monitor = cpuFeatureList->Monitor; - CpuF15OrFeatures->CpuF15OrFeaturesHi.OSXSAVE = cpuFeatureList->OSXSAVE; - CpuF15OrFeatures->CpuF15OrFeaturesHi.PCLMULQDQ = cpuFeatureList->PCLMULQDQ; - CpuF15OrFeatures->CpuF15OrFeaturesHi.POPCNT = cpuFeatureList->POPCNT; - CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE3 = cpuFeatureList->SSE3; - CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE41 = cpuFeatureList->SSE41; - CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE42 = cpuFeatureList->SSE42; - CpuF15OrFeatures->CpuF15OrFeaturesHi.SSSE3 = cpuFeatureList->SSSE3; - CpuF15OrFeatures->CpuF15OrFeaturesHi.X2APIC = cpuFeatureList->X2APIC; - CpuF15OrFeatures->CpuF15OrFeaturesHi.XSAVE = cpuFeatureList->XSAVE; - - LibAmdMsrWrite (MSR_CPUID_FEATS, &CpuMsrData, StdHeader); - - CpuMsrData = 0; - CpuF15OrExtFeatures = (CPU_F15_OR_EXT_FEATURES *) &CpuMsrData; - - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.ThreeDNow = cpuFeatureList->ThreeDNow; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.ThreeDNowExt = cpuFeatureList->ThreeDNowExt; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.APIC = cpuFeatureList->APIC; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.CMOV = cpuFeatureList->CMOV; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.DE = cpuFeatureList->DE; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FFXSR = cpuFeatureList->FFXSR; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FPU = cpuFeatureList->FPU; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FXSR = cpuFeatureList->FXSR; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.LM = cpuFeatureList->LM; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MCA = cpuFeatureList->MCA; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MCE = cpuFeatureList->MCE; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MMX = cpuFeatureList->MMX; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MmxExt = cpuFeatureList->MmxExt; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MSR = cpuFeatureList->MSR; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MTRR = cpuFeatureList->MTRR; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.NX = cpuFeatureList->NX; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PAE = cpuFeatureList->PAE; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.Page1GB = cpuFeatureList->Page1GB; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PAT = cpuFeatureList->PAT; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PGE = cpuFeatureList->PGE; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PSE = cpuFeatureList->PSE; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PSE36 = cpuFeatureList->PSE36; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.RDTSCP = cpuFeatureList->RDTSCP; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.SysCallSysRet = cpuFeatureList->SysCallSysRet; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.VME = cpuFeatureList->VME; - - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ThreeDNowPrefetch = cpuFeatureList->ThreeDNowPrefetch; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ABM = cpuFeatureList->ABM; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.AltMovCr8 = cpuFeatureList->AltMovCr8; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.CmpLegacy = cpuFeatureList->CmpLegacy; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ExtApicSpace = cpuFeatureList->ExtApicSpace; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.IBS = cpuFeatureList->IBS; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.LahfSahf = cpuFeatureList->LahfSahf; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.MisAlignSse = cpuFeatureList->MisAlignSse; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.OSVM = cpuFeatureList->OSVW; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SKINIT = cpuFeatureList->SKINIT; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SSE4A = cpuFeatureList->SSE4A; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SVM = cpuFeatureList->SVM; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.WDT = cpuFeatureList->WDT; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.NodeId = cpuFeatureList->NodeId; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.XOP = cpuFeatureList->XOP; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.TBM0 = cpuFeatureList->TBM0; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.LWP = cpuFeatureList->LWP; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.FMA4 = cpuFeatureList->FMA4; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.TCE = cpuFeatureList->TCE; - - LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * cpuFeatureListNeedUpdate - * - * Compare global CPU feature list with this core feature list to see if global CPU feature list - * needs updated. - * - * @param[in] globalCpuFeatureList - Pointer to global CPU Feature List. - * @param[in] thisCoreCpuFeatureList - Pointer to this core CPU Feature List. - * - * @retval FALSE globalCpuFeatureList is equal to thisCoreCpuFeatureList - * @retval True globalCpuFeatureList is NOT equal to thisCoreCpuFeatureList - */ -BOOLEAN -STATIC -cpuFeatureListNeedUpdate ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ) -{ - BOOLEAN flag; - UINT8 *global; - UINT8 *thisCore; - UINT8 i; - - flag = FALSE; - global = (UINT8 *) globalCpuFeatureList; - thisCore = (UINT8 *) thisCoreCpuFeatureList; - - for (i = 0; i < sizeof (CPU_FEATURES_LIST); i++) { - if ((*global) != (*thisCore)) { - flag = TRUE; - break; - } - global++; - thisCore++; - } - return flag; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * updateCpuFeatureList - * - * Update global CPU feature list - * - * @param[in] globalCpuFeatureList - Pointer to global CPU Feature List. - * @param[in] thisCoreCpuFeatureList - Pointer to this core CPU Feature List. - * - */ -VOID -STATIC -updateCpuFeatureList ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ) -{ - UINT8 *globalFeatureList; - UINT8 *thisCoreFeatureList; - UINT32 sizeInByte; - - globalFeatureList = (UINT8 *) globalCpuFeatureList; - thisCoreFeatureList = (UINT8 *) thisCoreCpuFeatureList; - - for (sizeInByte = 0; sizeInByte < sizeof (CPU_FEATURES_LIST); sizeInByte++) { - *globalFeatureList &= *thisCoreFeatureList; - globalFeatureList++; - thisCoreFeatureList++; - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.h deleted file mode 100644 index dd644d6392..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.h +++ /dev/null @@ -1,211 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi specific feature leveling functions. - * - * Provides feature leveling functions specific to family 15h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 45341 $ @e \$Date: 2011-01-14 15:49:18 -0700 (Fri, 14 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_FEATURE_LEVELING_H_ -#define _CPU_F15_OR_FEATURE_LEVELING_H_ - -#include "cpuFamilyTranslation.h" -#include "cpuPostInit.h" -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/// F15 Orochi CPU Feature Low -typedef struct { - UINT32 FPU:1; ///< Bit0 - UINT32 VME:1; ///< Bit1 - UINT32 DE:1; ///< Bit2 - UINT32 PSE:1; ///< Bit3 - UINT32 TimeStampCounter:1; ///< Bit4 - UINT32 MSR:1; ///< Bit5 - UINT32 PAE:1; ///< Bit6 - UINT32 MCE:1; ///< Bit7 - UINT32 CMPXCHG8B:1; ///< Bit8 - UINT32 APIC:1; ///< Bit9 - UINT32 :1; ///< Bit10 - UINT32 SysEnterSysExit:1; ///< Bit11 - UINT32 MTRR:1; ///< Bit12 - UINT32 PGE:1; ///< Bit13 - UINT32 MCA:1; ///< Bit14 - UINT32 CMOV:1; ///< Bit15 - UINT32 PAT:1; ///< Bit16 - UINT32 PSE36:1; ///< Bit17 - UINT32 :1; ///< Bit18 - UINT32 CLFSH:1; ///< Bit19 - UINT32 :3; ///< Bit20~22 - UINT32 MMX:1; ///< Bit23 - UINT32 FXSR:1; ///< Bit24 - UINT32 SSE:1; ///< Bit25 - UINT32 SSE2:1; ///< Bit26 - UINT32 :1; ///< Bit27 - UINT32 HTT:1; ///< Bit28 - UINT32 :3; ///< Bit29~31 -} CPU_F15_OR_FEATURES_LO; - -/// F15 Orochi CPU Feature High -typedef struct { - UINT32 SSE3:1; ///< Bit0 - UINT32 PCLMULQDQ:1; ///< Bit1 - UINT32 :1; ///< Bit2 - UINT32 Monitor:1; ///< Bit3 - UINT32 :5; ///< Bit4~8 - UINT32 SSSE3:1; ///< Bit9 - UINT32 :3; ///< Bit10~12 - UINT32 CMPXCHG16B:1; ///< Bit13 - UINT32 :5; ///< Bit14~18 - UINT32 SSE41:1; ///< Bit19 - UINT32 SSE42:1; ///< Bit20 - UINT32 X2APIC:1; ///< Bit21 - UINT32 :1; ///< Bit22 - UINT32 POPCNT:1; ///< Bit23 - UINT32 :1; ///< Bit24 - UINT32 AES:1; ///< Bit25 - UINT32 XSAVE:1; ///< Bit26 - UINT32 OSXSAVE:1; ///< Bit27 - UINT32 AVX:1; ///< Bit28 - UINT32 :3; ///< Bit29~32 -} CPU_F15_OR_FEATURES_HI; - -/// F15 Orochi CPU Feature -typedef struct { - CPU_F15_OR_FEATURES_LO CpuF15OrFeaturesLo; ///< Low - CPU_F15_OR_FEATURES_HI CpuF15OrFeaturesHi; ///< High -} CPU_F15_OR_FEATURES; - -/// F15 Orochi CPU Extended Feature Low -typedef struct { - UINT32 FPU:1; ///< Bit0 - UINT32 VME:1; ///< Bit1 - UINT32 DE:1; ///< Bit2 - UINT32 PSE:1; ///< Bit3 - UINT32 TimeStampCounter:1; ///< Bit4 - UINT32 MSR:1; ///< Bit5 - UINT32 PAE:1; ///< Bit6 - UINT32 MCE:1; ///< Bit7 - UINT32 CMPXCHG8B:1; ///< Bit8 - UINT32 APIC:1; ///< Bit9 - UINT32 :1; ///< Bit10 - UINT32 SysCallSysRet:1; ///< Bit11 - UINT32 MTRR:1; ///< Bit12 - UINT32 PGE:1; ///< Bit13 - UINT32 MCA:1; ///< Bit14 - UINT32 CMOV:1; ///< Bit15 - UINT32 PAT:1; ///< Bit16 - UINT32 PSE36:1; ///< Bit17 - UINT32 :2; ///< Bit18~19 - UINT32 NX:1; ///< Bit20 - UINT32 :1; ///< Bit21 - UINT32 MmxExt:1; ///< Bit22 - UINT32 MMX:1; ///< Bit23 - UINT32 FXSR:1; ///< Bit24 - UINT32 FFXSR:1; ///< Bit25 - UINT32 Page1GB:1; ///< Bit26 - UINT32 RDTSCP:1; ///< Bit27 - UINT32 :1; ///< Bit28 - UINT32 LM:1; ///< Bit29 - UINT32 ThreeDNowExt:1; ///< Bit30 - UINT32 ThreeDNow:1; ///< Bit31 -} CPU_F15_OR_EXT_FEATURES_LO; - -/// F15 Orochi CPU Extended Feature High -typedef struct { - UINT32 LahfSahf:1; ///< Bit0 - UINT32 CmpLegacy:1; ///< Bit1 - UINT32 SVM:1; ///< Bit2 - UINT32 ExtApicSpace:1; ///< Bit3 - UINT32 AltMovCr8:1; ///< Bit4 - UINT32 ABM:1; ///< Bit5 - UINT32 SSE4A:1; ///< Bit6 - UINT32 MisAlignSse:1; ///< Bit7 - UINT32 ThreeDNowPrefetch:1; ///< Bit8 - UINT32 OSVM:1; ///< Bit9 - UINT32 IBS:1; ///< Bit10 - UINT32 XOP:1; ///< Bit11 - UINT32 SKINIT:1; ///< Bit12 - UINT32 WDT:1; ///< Bit13 - UINT32 TBM0:1; ///< Bit14 - UINT32 LWP:1; ///< Bit15 - UINT32 FMA4:1; ///< Bit16 - UINT32 TCE:1; ///< Bit17 - UINT32 :1; ///< Bit18 - UINT32 NodeId:1; ///< Bit19 - UINT32 :12; ///< Bit20~31 -} CPU_F15_OR_EXT_FEATURES_HI; - -/// F15 Orochi CPU Extended Feature -typedef struct { - CPU_F15_OR_EXT_FEATURES_LO CpuF15OrExtFeaturesLo; ///< Low - CPU_F15_OR_EXT_FEATURES_HI CpuF15OrExtFeaturesHi; ///< High -} CPU_F15_OR_EXT_FEATURES; -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrSaveFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrWriteFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _CPU_F15_OR_FEATURE_LEVELING_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c deleted file mode 100644 index 0d6b115b9d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c +++ /dev/null @@ -1,349 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi after warm reset sequence for NB P-states - * - * Performs the "NB COF and VID Transition Sequence After Warm Reset" - * as described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "OptionMultiSocket.h" -#include "cpuF15OrNbAfterReset.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORNBAFTERRESET_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrPmNbAfterResetOnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -TransitionToNbLow ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -TransitionToNbHigh ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -WaitForNbTransitionToComplete ( - IN PCI_ADDR PciAddress, - IN UINT32 PstateIndex, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 15h Orochi core 0 entry point for performing the necessary steps after - * a warm reset has occurred. - * - * The steps are as follows: - * 1. Temp1 = D18F5x170[SwNbPstateLoDis]. - * 2. Temp2 = D18F5x170[NbPstateDisOnP0]. - * 3. Temp3 = D18F5x170[NbPstateThreshold]. - * 4. If MSRC001_0070[NbPstate] = 1, go to step 9. - * 5. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. - * 6. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, - * CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. - * 7. Set D18F5x170[SwNbPstateLoDis] = 1. - * 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, - * CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. - * Go to step 13. - * 9. Set D18F5x170[SwNbPstateLoDis] = 1. - * 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, - * CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. - * 11. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. - * 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, - * CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. - * 13. Set D18F5x170[SwNbPstateLoDis] = Temp1, D18F5x170[NbPstateDisOnP0] = Temp2, and - * D18F5x170[NbPstateThreshold] = Temp3. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrPmNbAfterReset ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 TaskedCore; - UINT32 Ignored; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - - ASSERT (Core == 0); - - // Launch one core per node. - TaskPtr.FuncAddress.PfApTask = F15OrPmNbAfterResetOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) { - if (TaskedCore != 0) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader); - } - } - } - ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr); -} - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmNbAfterReset to perform MSR initialization on one - * core of each die in a family 15h socket. - * - * This function implements steps 1 - 13 on each core. - * - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15OrPmNbAfterResetOnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbPsCtrlOnEntry; - UINT32 NbPsCtrlOnExit; - UINT64 LocalMsrRegister; - PCI_ADDR PciAddress; - - // 1. Temp1 = D18F5x170[SwNbPstateLoDis]. - // 2. Temp2 = D18F5x170[NbPstateDisOnP0]. - // 3. Temp3 = D18F5x170[NbPstateThreshold]. - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader); - - // Check if NB P-states were disabled, and if so, prevent any changes from occurring. - if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateMaxVal != 0) { - // 4. If MSRC001_0070[NbPstate] = 1, go to step 9 - LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader); - if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) { - // 5. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. - // 6. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. - TransitionToNbLow (PciAddress, StdHeader); - - // 7. Set D18F5x170[SwNbPstateLoDis] = 1. - // 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. - // Go to step 13. - TransitionToNbHigh (PciAddress, StdHeader); - } else { - // 9. Set D18F5x170[SwNbPstateLoDis] = 1. - // 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. - TransitionToNbHigh (PciAddress, StdHeader); - - // 11. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. - // 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. - TransitionToNbLow (PciAddress, StdHeader); - } - - // 13. Set D18F5x170[SwNbPstateLoDis] = Temp1, D18F5x170[NbPstateDisOnP0] = Temp2, and - // D18F5x170[NbPstateThreshold] = Temp3. - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis; - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0; - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmNbAfterResetOnCore to transition to the low NB P-state. - * - * This function implements steps 5, 6, 11, and 12 as needed. - * - * @param[in] PciAddress Segment, bus, device number of the node to transition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -TransitionToNbLow ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbPsCtrl; - - // 5/11. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 0; - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateDisOnP0 = 0; - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateThreshold = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - - // 6/12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. - WaitForNbTransitionToComplete (PciAddress, ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmNbAfterResetOnCore to transition to the high NB P-state. - * - * This function implements steps 7, 8, 9, and 10 as needed. - * - * @param[in] PciAddress Segment, bus, device number of the node to transition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -TransitionToNbHigh ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbPsCtrl; - - // 7/9. Set D18F5x170[SwNbPstateLoDis] = 1. - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - - // 8/10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. - WaitForNbTransitionToComplete (PciAddress, ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateHi, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmAfterResetCore to wait for NB FID and DID to - * match a specific P-state. - * - * This function implements steps 6, 8, 10, and 12 as needed. - * - * @param[in] PciAddress Segment, bus, device number of the node to transition. - * @param[in] PstateIndex P-state settings to match. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -WaitForNbTransitionToComplete ( - IN PCI_ADDR PciAddress, - IN UINT32 PstateIndex, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TargetNbPs; - UINT32 NbPsSts; - - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_0 + (PstateIndex << 2); - LibAmdPciRead (AccessWidth32, PciAddress, &TargetNbPs, StdHeader); - PciAddress.Address.Register = NB_PSTATE_STATUS; - do { - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader); - } while ((((NB_PSTATE_STS_REGISTER *) &NbPsSts)->CurNbPstate != PstateIndex || - (((NB_PSTATE_STS_REGISTER *) &NbPsSts)->CurNbFid != ((NB_PSTATE_REGISTER *) &TargetNbPs)->NbFid)) || - (((NB_PSTATE_STS_REGISTER *) &NbPsSts)->CurNbDid != ((NB_PSTATE_REGISTER *) &TargetNbPs)->NbDid)); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.h deleted file mode 100644 index 710d43db4f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi after warm reset sequence for NB P-states - * - * Contains code that provide power management functionality - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_NB_AFTER_RESET_H_ -#define _CPU_F15_OR_NB_AFTER_RESET_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrPmNbAfterReset ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F15_OR_NB_AFTER_RESET_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPowerMgmt.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPowerMgmt.h deleted file mode 100644 index 5d66252c9b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPowerMgmt.h +++ /dev/null @@ -1,534 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Power Management related stuff - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 60669 $ @e \$Date: 2011-10-19 17:17:41 -0600 (Wed, 19 Oct 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_POWERMGMT_H_ -#define _CPU_F15_OR_POWERMGMT_H_ - -/* - * Family 15h Orochi CPU Power Management MSR definitions - * - */ - - -/* Interrupt Pending and CMP-Halt MSR Register 0xC0010055 */ -#define MSR_INTPEND 0xC0010055 - -/// Interrupt Pending and CMP-Halt MSR Register -typedef struct { - UINT64 IoMsgAddr:16; ///< IO message address - UINT64 IoMsgData:8; ///< IO message data - UINT64 IntrPndMsgDis:1; ///< Interrupt pending message disable - UINT64 IntrPndMsg:1; ///< Interrupt pending message - UINT64 IoRd:1; ///< IO read - UINT64 :2; ///< Reserved - UINT64 BmStsClrOnHltEn:1; ///< Clear BM status bit on server C1e entry - UINT64 :34; ///< Reserved -} INTPEND_MSR; - - -/* P-state Registers 0xC001006[B:4] */ - -/// P-state MSR -typedef struct { - UINT64 CpuFid:6; ///< CpuFid - UINT64 CpuDid:3; ///< CpuDid - UINT64 CpuVid:7; ///< CpuVid - UINT64 :6; ///< Reserved - UINT64 NbPstate:1; ///< NbPstate - UINT64 :9; ///< Reserved - UINT64 IddValue:8; ///< IddValue - UINT64 IddDiv:2; ///< IddDiv - UINT64 :21; ///< Reserved - UINT64 PsEnable:1; ///< Pstate Enable -} PSTATE_MSR; - - -/* COFVID Control Register 0xC0010070 */ -#define MSR_COFVID_CTL 0xC0010070 - -/// COFVID Control MSR Register -typedef struct { - UINT64 CpuFid:6; ///< CpuFid - UINT64 CpuDid:3; ///< CpuDid - UINT64 CpuVid:7; ///< CpuVid - UINT64 PstateId:3; ///< Pstate ID - UINT64 :3; ///< Reserved - UINT64 NbPstate:1; ///< Northbridge P-state - UINT64 :41; ///< Reserved -} COFVID_CTRL_MSR; - - -/* COFVID Status Register 0xC0010071 */ -#define MSR_COFVID_STS 0xC0010071 - -/// COFVID Status MSR Register -typedef struct { - UINT64 CurCpuFid:6; ///< Current CpuFid - UINT64 CurCpuDid:3; ///< Current CpuDid - UINT64 CurCpuVid:7; ///< Current CpuVid - UINT64 CurPstate:3; ///< Current Pstate - UINT64 :3; ///< Reserved - UINT64 CurNbDid:1; ///< Current NbDid - UINT64 :2; ///< Reserved - UINT64 CurNbVid:7; ///< Current NbVid - UINT64 StartupPstate:3; ///< Startup Pstate - UINT64 MaxVid:7; ///< MaxVid - UINT64 MinVid:7; ///< MinVid - UINT64 MaxCpuCof:6; ///< MaxCpuCof - UINT64 :1; ///< Reserved - UINT64 CurPstateLimit:3; ///< Current Pstate Limit - UINT64 MaxNbCof:5; ///< MaxNbCof -} COFVID_STS_MSR; - -/* Floating Point Configuration Register 0xC0011028 */ -#define MSR_FP_CFG 0xC0011028 - -/// Floating Point Configuration MSR Register -typedef struct { - UINT64 :16; ///< Reserved - UINT64 DiDtMode:1; ///< Di/Dt Mode - UINT64 :1; ///< Reserved - UINT64 DiDtCfg0:5; ///< Di/Dt Config 0 - UINT64 :2; ///< Reserved - UINT64 AlwaysOnThrottle:2; ///< AlwaysOnThrottle - UINT64 DiDtCfg1:8; ///< Di/Dt Config 1 - UINT64 :5; ///< Reserved - UINT64 Pipe3ThrottleDis:1; ///< Pipe3ThrottleDis - UINT64 :23; ///< Reserved -} FP_CFG_MSR; - -/* - * Family 15h Orochi CPU Power Management PCI definitions - * - */ - -/* Link transaction control register F0x68 */ -#define LTC_REG 0x68 - -/// Link Transaction Control Register -typedef struct { - UINT32 :12; ///< Reserved - UINT32 ATMModeEn:1; ///< Accelerated transition to modified mode enable - UINT32 :19; ///< Reserved -} LTC_REGISTER; - -/* DRAM Configuration High Register F2x[1,0]94 */ -#define DRAM_CFG_HI_REG0 0x94 -#define DRAM_CFG_HI_REG1 0x194 - -/// DRAM Configuration High PCI Register -typedef struct { - UINT32 MemClkFreq:5; ///< Memory clock frequency - UINT32 :2; ///< Reserved - UINT32 MemClkFreqVal:1; ///< Memory clock frequency valid - UINT32 :2; ///< Reserved - UINT32 ZqcsInterval:2; ///< ZQ calibration short interval - UINT32 :1; ///< Reserved - UINT32 DisSimulRdWr:1; ///< Disable simultaneous read and write - UINT32 DisDramInterface:1; ///< Disable the DRAM interface - UINT32 PowerDownEn:1; ///< Power down mode enable - UINT32 PowerDownMode:1; ///< Power down mode - UINT32 FourRankRDimm1:1; ///< Four rank registered DIMM 1 - UINT32 FourRankRDimm0:1; ///< Four rank registered DIMM 0 - UINT32 DcqArbBypassEn:1; ///< DRAM controller arbiter bypass enable - UINT32 SlowAccessMode:1; ///< Slow access mode - UINT32 FreqChgInProg:1; ///< Frequency change in progress - UINT32 BankSwizzleMode:1; ///< Bank swizzle mode - UINT32 ProcOdtDis:1; ///< Processor on-die termination disable - UINT32 DcqBypassMax:4; ///< DRAM controller queue bypass maximum - UINT32 :4; ///< Reserved -} DRAM_CFG_HI_REGISTER; - - -/* Scrub Rate Control Register F3x58 */ -#define SCRUB_RATE_CTRL_REG 0x58 - -/// Scrub Rate Control PCI Register -typedef struct { - UINT32 DramScrub:5; ///< DRAM scrub rate - UINT32 :19; ///< Reserved - UINT32 L3Scrub:5; ///< L3 cache scrub rate - UINT32 :3; ///< Reserved -} SCRUB_RATE_CTRL_REGISTER; - -/* DRAM Scrub Address Low Register F3x5C */ -#define DRAM_SCRUB_ADDR_LOW_REG 0x5C - -/// DRAM Scrub Address Low PCI Register -typedef struct { - UINT32 ScrubReDirEn:1; ///< DRAM scrubber redirect enable - UINT32 :5; ///< Reserved - UINT32 ScrubAddr:26; ///< DRAM scrubber address bits[31:6] -} DRAM_SCRUB_ADDR_LOW_REGISTER; - -/* Free List Buffer Count Register F3x7C */ -#define FREE_LIST_BUFFER_COUNT_REG 0x7C - -/// Free List Buffer Count PCI Register -typedef struct { - UINT32 Xbar2SriFreeListCBC:5; ///< XBAR to SRI free list command buffer count - UINT32 :3; ///< Reserved - UINT32 Sri2XbarFreeXreqCBC:4; ///< SRI to XBAR free request and posted request command buffer count - UINT32 Sri2XbarFreeRspCBC:4; ///< SRI to XBAR free response command buffer count - UINT32 Sri2XbarFreeXreqDBC:4; ///< SRI to XBAR free request and posted request data buffer count - UINT32 Sri2XbarFreeRspDBC:3; ///< SRI to XBAR free response data buffer count - UINT32 SrqExtFreeListBc:4; ///< extend SRQ freelist tokens - UINT32 :1; ///< Reserved - UINT32 Xbar2SriFreeListCbInc:3; ///< XBAR to SRI free list command buffer increment - UINT32 :1; ///< Reserved -} FREE_LIST_BUFFER_COUNT_REGISTER; - -/* ACPI Power State Control High F3x84 */ -#define ACPI_PWR_STATE_CTRL_HI_REG 0x84 - -/// ACPI Power State Control High PCI Register -typedef struct { - UINT32 CpuPrbEnSmafAct4:1; ///< CPU direct probe enable - UINT32 NbLowPwrEnSmafAct4:1; ///< NB low-power enable - UINT32 NbGateEnSmafAct4:1; ///< NB gate enable - UINT32 NbCofChgSmafAct4:1; ///< NB FID change - UINT32 :1; ///< Reserved - UINT32 ClkDivisorSmafAct4:3; ///< clock divisor - UINT32 :8; ///< Reserved - UINT32 CpuPrbEnSmafAct6:1; ///< CPU direct probe enable - UINT32 NbLowPwrEnSmafAct6:1; ///< NB low-power enable - UINT32 NbGateEnSmafAct6:1; ///< NB gate enable - UINT32 NbCofChgSmafAct6:1; ///< NB FID change - UINT32 :1; ///< Reserved - UINT32 ClkDivisorSmafAct6:3; ///< clock divisor - UINT32 CpuPrbEnSmafAct7:1; ///< CPU direct probe enable - UINT32 NbLowPwrEnSmafAct7:1; ///< NB low-power enable - UINT32 NbGateEnSmafAct7:1; ///< NB gate enable - UINT32 NbCofChgSmafAct7:1; ///< NB FID change - UINT32 :1; ///< Reserved - UINT32 ClkDivisorSmafAct7:3; ///< clock divisor -} ACPI_PWR_STATE_CTRL_HI_REGISTER; - -/* Power Control Miscellaneous Register F3xA0 */ -#define PW_CTL_MISC_REG 0xA0 - -/// Power Control Miscellaneous PCI Register -typedef struct { - UINT32 PsiVid:7; ///< PSI_L VID threshold - UINT32 PsiVidEn:1; ///< PSI_L VID enable - UINT32 :1; ///< Reserved - UINT32 SviHighFreqSel:1; ///< SVI high frequency select - UINT32 IdleExitEn:1; ///< IDLEEXIT_L Enable - UINT32 PllLockTime:3; ///< PLL synchronization lock time - UINT32 :2; ///< Reserved - UINT32 ConfigId:12; ///< Configuration ID - UINT32 NbPstateForce:1; ///< NB P-state force on next LDTSTOP assertion - UINT32 :2; ///< Reserved - UINT32 CofVidProg:1; ///< COF and VID of Pstate programmed -} POWER_CTRL_MISC_REGISTER; - - -/* Clock Power/Timing Control 0 Register F3xD4 */ -#define CPTC0_REG 0xD4 -#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG)) - -/// Clock Power Timing Control PCI Register -typedef struct { - UINT32 NbFid:5; ///< NbFid - UINT32 NbFidEn:1; ///< NbFidEn - UINT32 :2; ///< Reserved - UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select - UINT32 ClkRampHystCtl:1; ///< Clock Ramp Hysteresis Control - UINT32 MTC1eEn:1; ///< Message Triggered C1e Enable - UINT32 CacheFlushImmOnAllHalt:1; ///< Cache Flush Immediate on All Halt - UINT32 StutterScrubEn:1; ///< Stutter Mode Scrub Enable - UINT32 LnkPllLock:2; ///< Link PLL Lock - UINT32 :2; ///< Reserved - UINT32 PowerStepDown:4; ///< Power Step Down - UINT32 PowerStepUp:4; ///< Power Step Up - UINT32 NbClkDiv:3; ///< NbClkDiv - UINT32 NbClkDivApplyAll:1; ///< NbClkDivApplyAll -} CLK_PWR_TIMING_CTRL_REGISTER; - - -/* Clock Power/Timing Control 1 Register F3xD8 */ -#define CPTC1_REG 0xD8 -#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG)) - -/// Clock Power Timing Control 1 PCI Register -typedef struct { - UINT32 :4; ///< Reserved - UINT32 VSRampSlamTime:3; ///< Voltage stabilization ramp time - UINT32 :17; ///< Reserved - UINT32 ReConDel:4; ///< Link reconnect delay - UINT32 :4; ///< Reserved -} CLK_PWR_TIMING_CTRL1_REGISTER; - - -/* Northbridge Capabilities Register F3xE8 */ -#define NB_CAPS_REG 0xE8 - -/// Northbridge Capabilities PCI Register -typedef struct { - UINT32 :1; ///< Reserved - UINT32 DualNode:1; ///< Dual-node multi-processor capable - UINT32 EightNode:1; ///< Eight-node multi-processor capable - UINT32 Ecc:1; ///< ECC capable - UINT32 Chipkill:1; ///< Chipkill ECC capable - UINT32 :3; ///< Reserved - UINT32 MctCap:1; ///< Memory controller capable - UINT32 SvmCapable:1; ///< SVM capable - UINT32 HtcCapable:1; ///< HTC capable - UINT32 LnkRtryCap:1; ///< Link error-retry capable - UINT32 :2; ///< Reserved - UINT32 MultVidPlane:1; ///< Multiple VID plane capable - UINT32 :1; ///< Reserved - UINT32 MpCap:3; ///< MP capability - UINT32 x2Apic:1; ///< x2Apic capability - UINT32 UnGangEn:4; ///< Link unganging enabled - UINT32 :1; ///< Reserved - UINT32 L3Capable:1; ///< L3 capable - UINT32 :3; ///< Reserved - UINT32 MultiNodeCpu:1; ///< Multinode processor - UINT32 IntNodeNum:2; ///< Internal node number -} NB_CAPS_REGISTER; - -/* L3 Buffer Count */ -#define L3_BUFFER_COUNT_REG 0x1A0 - -/// L3 Buffer Count -typedef struct { - UINT32 CpuCmdBufCnt:3; ///< CPU to SRI command buffer count - UINT32 :1; ///< Reserved - UINT32 L3FreeListCBC:5; ///< L3 free list command buffer counter for compute unit requests - UINT32 :3; ///< Reserved - UINT32 L3ToSriReqCBC:3; ///< L3 cache to SRI request command buffer count - UINT32 :1; ///< Reserved - UINT32 CpuToNbFreeBufCnt:2; ///< Cpu to Nb free buffer count - UINT32 :14; ///< Reserved -} L3_BUFFER_COUNT_REGISTER; - -/* L3 Control 1 */ -#define L3_CONTROL_1_REG 0x1B8 - -/// L3 Control 1 Register -typedef struct { - UINT32 :27; ///< Reserved - UINT32 L3ATMModeEn:1; ///< Enable Accelerated Transition to Modified protocol in L3 - UINT32 :4; ///< Reserved -} L3_CONTROL_1_REGISTER; - -/* L3 Cache Parameter Register F3x1C4 */ -#define L3_CACHE_PARAM_REG 0x1C4 - -/// L3 Cache Parameter PCI Register -typedef struct { - UINT32 L3SubcacheSize0:4; ///< L3 subcache size 0 - UINT32 L3SubcacheSize1:4; ///< L3 subcache size 1 - UINT32 L3SubcacheSize2:4; ///< L3 subcache size 2 - UINT32 L3SubcacheSize3:4; ///< L3 subcache size 3 - UINT32 :15; ///< Reserved - UINT32 L3TagInit:1; ///< L3 tag initialization -} L3_CACHE_PARAM_REGISTER; - - -/* Probe Filter Control Register F3x1D4 */ -#define PROBE_FILTER_CTRL_REG 0x1D4 - -/// Probe Filter Control PCI Register -typedef struct { - UINT32 PFMode:2; ///< Probe Filter Mode - UINT32 PFWayNum:2; ///< Probe Filter way number - UINT32 PFSubCacheSize0:2; ///< Probe filter subcache 0 size - UINT32 PFSubCacheSize1:2; ///< Probe filter subcache 1 size - UINT32 PFSubCacheSize2:2; ///< Probe filter subcache 2 size - UINT32 PFSubCacheSize3:2; ///< Probe filter subcache 3 size - UINT32 PFSubCacheEn:4; ///< Probe filter subcache enable - UINT32 DisDirectedPrb:1; ///< Disable directed probes - UINT32 PFWayHashEn:1; ///< Probe filter cache way hash enable - UINT32 :1; ///< Reserved - UINT32 PFInitDone:1; ///< Probe filter initialization done - UINT32 PFPreferredSORepl:2; ///< PF preferredSO replacement mode - UINT32 PFErrInt:2; ///< Probe filter error interrupt type - UINT32 LvtOffset:4; ///< Probe filter error interrupt LVT offset - UINT32 PFEccError:1; ///< Probe filter ECC error - UINT32 PFLoIndexHashEn:1; ///< Probe filter low index hash enable - UINT32 DisPrbFilterInit:1; ///< Disable probe filter initialization - UINT32 SmallPFDirEn:1; ///< Small probe filter directory enable -} PROBE_FILTER_CTRL_REGISTER; - - -/* Product Info Register F3x1FC */ -#define PRCT_INFO_REG 0x1FC - -/// Product Information PCI Register -typedef struct { - UINT32 DiDtMode:1; ///< DiDtMode - UINT32 DiDtCfg0:5; ///< DiDtCfg0 - UINT32 DiDtCfg1:8; ///< DiDtCfg1 - UINT32 AlwaysOnThrottle:2; ///< AlwaysOnThrottle - UINT32 Pipe3ThrottleDis:1; ///< Pipe3ThrottleDis - UINT32 :15; ///< Reserved -} PRODUCT_INFO_REGISTER; - - -/* C-state Control 1 Register D18F4x118 */ -#define CSTATE_CTRL1_REG 0x118 -#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG)) - -/// C-state Control 1 Register -typedef struct { - UINT32 CpuPrbEnCstAct0:1; ///< Core direct probe enable - UINT32 CacheFlushEnCstAct0:1; ///< Cache flush enable - UINT32 CacheFlushTmrSelCstAct0:2; ///< Cache flush timer select - UINT32 :1; ///< Reserved - UINT32 ClkDivisorCstAct0:3; ///< Clock divisor - UINT32 PwrGateEnCstAct0:1; ///< Power gate enable - UINT32 :1; ///< Reserved - UINT32 :6; ///< Reserved - UINT32 CpuPrbEnCstAct1:1; ///< Core direct probe enable - UINT32 CacheFlushEnCstAct1:1; ///< Cache flush eable - UINT32 CacheFlushTmrSelCstAct1:2; ///< Cache flush timer select - UINT32 :1; ///< Reserved - UINT32 ClkDivisorCstAct1:3; ///< Clock divisor - UINT32 PwrGateEnCstAct1:1; ///< Power gate enable - UINT32 :1; ///< Reserved - UINT32 :6; ///< Reserved -} CSTATE_CTRL1_REGISTER; - - -/* C-state Control 2 Register D18F4x11C */ -#define CSTATE_CTRL2_REG 0x11C -#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG)) - -/// C-state Control 2 Register -typedef struct { - UINT32 CpuPrbEnCstAct2:1; ///< Core direct probe enable - UINT32 CacheFlushEnCstAct2:1; ///< Cache flush eable - UINT32 CacheFlushTmrSelCstAct2:2; ///< Cache flush timer select - UINT32 AltvidEnCstAct2:1; ///< Core altvid enable - UINT32 ClkDivisorCstAct2:3; ///< Clock divisor - UINT32 PwrGateEnCstAct2:1; ///< Power gate enable - UINT32 PwrOffEnCstAct2:1; ///< C-state action field 3 - UINT32 :22; ///< Reserved -} CSTATE_CTRL2_REGISTER; - - -/* Cstate Policy Control 1 Register D18F4x128 */ -#define CSTATE_POLICY_CTRL1_REG 0x128 -#define CSTATE_POLICY_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_POLICY_CTRL1_REG)) - -/// Cstate Policy Control 1 Register -typedef struct { - UINT32 CoreCStateMode:1; ///< Specifies C-State actions - UINT32 CoreCstatePolicy:1; ///< Specified processor arbitration of voltage and frequency - UINT32 HaltCstateIndex:3; ///< Specifies the IO-based C-state that is invoked by a HLT instruction - UINT32 CacheFlushTmr:7; ///< Cache flush timer - UINT32 CoreStateSaveDestnode:6; ///< Core state save destination node - UINT32 CacheFlushSucMonThreshold:3; ///< Cache flush success monitor threshold - UINT32 :10; ///< Reserved - UINT32 CstateMsgDis:1; ///< C-state messaging disable -} CSTATE_POLICY_CTRL1_REGISTER; - - -/* Core Performance Boost Control Register D18F4x15C */ - -/// Core Performance Boost Control Register -typedef struct { - UINT32 BoostSrc:2; ///< Boost source - UINT32 NumBoostStates:3; ///< Number of boosted states - UINT32 :2; ///< Reserved - UINT32 ApmMasterEn:1; ///< APM master enable - UINT32 :20; ///< Reserved - UINT32 TdpLimitPstate:3; ///< Highest performance pstate - UINT32 BoostLock:1; ///< -} CPB_CTRL_REGISTER; - - -/* Northbridge P-state [3:0] F5x1[6C:60] */ - -/// Northbridge P-state Register -typedef struct { - UINT32 NbPstateEn:1; ///< NB P-state enable - UINT32 NbFid:5; ///< NB frequency ID - UINT32 :1; ///< Reserved - UINT32 NbDid:1; ///< NB divisor ID - UINT32 :2; ///< Reserved - UINT32 NbVid:7; ///< NB VID - UINT32 :15; ///< Reserved -} NB_PSTATE_REGISTER; - - -/* Northbridge P-state Status */ -#define NB_PSTATE_CTRL 0x170 -#define NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_CTRL)) - -/// Northbridge P-state Control Register -typedef struct { - UINT32 NbPstateMaxVal:2; ///< NB P-state maximum value - UINT32 :1; ///< Reserved - UINT32 NbPstateLo:2; ///< NB P-state low - UINT32 :1; ///< Reserved - UINT32 NbPstateHi:2; ///< NB P-state high - UINT32 :1; ///< Reserved - UINT32 NbPstateThreshold:3; ///< NB P-state threshold - UINT32 :1; ///< Reserved - UINT32 NbPstateDisOnP0:1; ///< NB P-state disable on P0 - UINT32 SwNbPstateLoDis:1; ///< Software NB P-state low disable - UINT32 :17; ///< Reserved -} NB_PSTATE_CTRL_REGISTER; - - -/* Northbridge P-state Status */ -#define NB_PSTATE_STATUS 0x174 -#define NB_PSTATE_STATUS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_STATUS)) - -/// Northbridge P-state Status Register -typedef struct { - UINT32 NbPstateDis:1; ///< Nb pstate disable - UINT32 StartupNbPstate:2; ///< startup northbridge Pstate number - UINT32 CurNbFid:5; ///< Current NB FID - UINT32 :1; ///< Reserved - UINT32 CurNbDid:1; ///< Current NB DID - UINT32 :2; ///< Reserved - UINT32 CurNbVid:7; ///< Current NB VID - UINT32 CurNbPstate:2; ///< Current NB Pstate - UINT32 :11; ///< Reserved -} NB_PSTATE_STS_REGISTER; - -#endif /* _CPU_F15_OR_POWERMGMT_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c deleted file mode 100644 index 4a2251a4e4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c +++ /dev/null @@ -1,920 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Pstate feature support functions. - * - * Provides the functions necessary to initialize the Pstate feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuPstateTables.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "cpuFamilyTranslation.h" -#include "cpuFamRegisters.h" -#include "cpuF15Utilities.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORPSTATE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrGetPowerStepValueInTime ( - IN OUT UINT32 *PowerStepPtr - ); - -VOID -STATIC -F15OrGetPllValueInTime ( - IN OUT UINT32 *PllLockTimePtr - ); - -AGESA_STATUS -STATIC -F15OrGetFrequencyXlatRegInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 PStateNumber, - IN UINT32 Frequency, - OUT UINT32 *CpuFidPtr, - OUT UINT32 *CpuDidPtr1, - OUT UINT32 *CpuDidPtr2, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetPstateTransLatency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetPstateFrequency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrPstateLevelingCoreMsrModify ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetPstatePower ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetPstateMaxState ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetPstateRegisterInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if PSD need to be generated. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE PSD need to be generated - * @retval FALSE PSD does NOT need to be generated - * - */ -BOOLEAN -STATIC -F15OrIsPstatePsdNeeded ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - PLATFORM_FEATS Features; - - // Initialize the union - Features.PlatformValue = 0; - GetPlatformFeatures (&Features, PlatformConfig, StdHeader); - - // - // For Single link processor, PSD needs to be generated - // For other processor, if D18F5x80[DualCore][0]=0, the _PSD object does not need to be generated. - // - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Register = COMPUTE_UNIT_STATUS; - PciAddress.Address.Function = FUNC_5; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((!Features.PlatformFeatures.PlatformSingleLink) && ((LocalPciRegister & 0x10000) == 0)) { - return FALSE; - } - return TRUE; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if Pstate PSD is dependent. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE PSD is dependent. - * @retval FALSE PSD is independent. - * - */ -BOOLEAN -STATIC -F15OrIsPstatePsdDependent ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PLATFORM_FEATS Features; - - // Initialize the union - Features.PlatformValue = 0; - GetPlatformFeatures (&Features, PlatformConfig, StdHeader); - - // - // For Single link has PSD option, default is dependent. - // If multi-link, always return independent. - // - if (Features.PlatformFeatures.PlatformSingleLink) { - if (PlatformConfig->ForcePstateIndependent) { - return FALSE; - } - return TRUE; - } - return FALSE; -} - -/** - * Family specific call to set core TscFreqSel. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrSetTscFreqSel ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - //TscFreqSel: TSC frequency select. Read-only. Reset: 1. 1=The TSC increments at the P0 frequency. - //This field uses software P-state numbering. - return; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get Pstate Transition Latency. - * - * Calculate TransitionLatency by power step value and pll value. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer - * @param[in] PciAddress Pci address - * @param[out] TransitionLatency The transition latency. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F15OrGetPstateTransLatency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempVar_b; - UINT32 TempVar_c; - UINT32 TempVar_d; - UINT32 TempVar8_a; - UINT32 TempVar8_b; - UINT32 Ignored; - UINT32 k; - UINT32 CpuFidSameFlag; - UINT8 PStateMaxValueOnCurrentCore; - UINT32 TransAndBusMastLatency; - - CpuFidSameFlag = 1; - - F15OrGetFrequencyXlatRegInfo ( - PstateCpuServices, - 0, - PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[0].CoreFreq, - &TempVar_b, - &TempVar_c, - &Ignored, - StdHeader - ); - - TempVar_d = TempVar_b; - PStateMaxValueOnCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue; - - // - //Check if MSRC001_00[6B:64][CpuFid] is the same value for all P-states where - //MSRC001_00[6B:64][PstateEn]=1 - // - for (k = 1; k <= PStateMaxValueOnCurrentCore; k++) { - if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) { - F15OrGetFrequencyXlatRegInfo ( - PstateCpuServices, - (UINT8) k, - PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq, - &TempVar_b, - &TempVar_c, - &Ignored, - StdHeader - ); - } - - if (TempVar_d != TempVar_b) { - CpuFidSameFlag = 0; - break; - } - } - - PciAddress->Address.Register = 0xD4; - PciAddress->Address.Function = FUNC_3; - LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader); - - // PowerStepDown - Bits 20:23 - TempVar8_a = (TempVar_d & 0x00F00000) >> 20; - - // PowerStepUp - Bits 24:27 - TempVar8_b = (TempVar_d & 0x0F000000) >> 24; - - // Convert the raw numbers in TempVar8_a and TempVar8_b into time - F15OrGetPowerStepValueInTime (&TempVar8_a); - F15OrGetPowerStepValueInTime (&TempVar8_b); - - // - //(12 * (F3xD4[PowerStepDown] + F3xD4[PowerStepUp]) /1000) us - // - TransAndBusMastLatency = - (12 * (TempVar8_a + TempVar8_b) + 999) / 1000; - - if (CpuFidSameFlag == 0) { - // - //+ F3xA0[PllLockTime] - // - PciAddress->Address.Register = 0xA0; - LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader); - - TempVar8_a = (0x00003800 & TempVar_d) >> 11; - F15OrGetPllValueInTime (&TempVar8_a); - TransAndBusMastLatency += TempVar8_a; - } - - *TransitionLatency = TransAndBusMastLatency; - - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to calculates the frequency in megahertz of the desired P-state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StateNumber The hardware P-State to analyze. - * @param[out] FrequencyInMHz The P-State's frequency in MegaHertz - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always Succeeds. - */ -AGESA_STATUS -F15OrGetPstateFrequency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 TempValue; - UINT32 CpuDid; - UINT32 CpuFid; - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); - CpuDid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuDid); - CpuFid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuFid); - - switch (CpuDid) { - case 0: - TempValue = 1; - break; - case 1: - TempValue = 2; - break; - case 2: - TempValue = 4; - break; - case 3: - TempValue = 8; - break; - case 4: - TempValue = 16; - break; - default: - // CpuDid is set to an undefined value. This is due to either a misfused CPU, or - // an invalid P-state MSR write. - ASSERT (FALSE); - TempValue = 1; - break; - } - *FrequencyInMHz = (100 * (CpuFid + 0x10) / TempValue); - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to sets the Pstate MSR to each APs base on Pstate Buffer. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] CpuAmdPState Gathered P-state data structure for whole system. - * @param[in] StdHeader Config for library and services. - * - * @retval AGESA_STATUS AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -F15OrPstateLevelingCoreMsrModify ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 Ignored; - UINT32 k; - UINT32 TempVar_d; - UINT32 TempVar_e; - UINT32 TempVar_f; - UINT32 LogicalSocketCount; - UINT32 LocalPciRegister; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT8 SwP0; - UINT64 MsrValue; - AGESA_STATUS Status; - PSTATE_LEVELING *PStateBufferPtr; - PSTATE_LEVELING *PStateBufferPtrTmp; - S_CPU_AMD_PSTATE *CpuAmdPstatePtr; - PCI_ADDR PciAddress; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL); - - Ignored = 0; - CpuAmdPstatePtr = (S_CPU_AMD_PSTATE *) CpuAmdPState; - PStateBufferPtrTmp = CpuAmdPstatePtr->PStateLevelingStruc; - PStateBufferPtr = CpuAmdPstatePtr->PStateLevelingStruc; - LogicalSocketCount = CpuAmdPstatePtr->TotalSocketInSystem; - PciAddress.AddressValue = 0; - SwP0 = PStateBufferPtrTmp->PStateCoreStruct[0].NumberOfBoostedStates; - - // - //Try to find the Pstate buffer specific to this core(socket). - // - IdentifyCore (StdHeader, &Socket, &Module, &Core, &Status); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Status); - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, CpuAmdPstatePtr, i, StdHeader); - if (PStateBufferPtrTmp->SocketNumber == Socket) { - break; - } - } - - if (PStateBufferPtr[0].OnlyOneEnabledPState) { - // - //If all processors have only 1 enabled P-state, the following sequence should be performed on all cores: - // - - //1. Write the appropriate CpuFid value resulting from the matched CPU COF to 'software P0'. - LibAmdMsrRead (MSR_PSTATE_0 + (UINT32) SwP0, &MsrValue, StdHeader); - Status = F15OrGetFrequencyXlatRegInfo (PstateCpuServices, SwP0, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader); - // Bits 5:0 - ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d; - // Bits 8:6 - ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e; - // Bits 39:32 - ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue; - // Bits 41:40 - ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv; - // Enable the P-State - ((PSTATE_MSR *) &MsrValue)->PsEnable = 1; - LibAmdMsrWrite (MSR_PSTATE_0 + (UINT32) SwP0, &MsrValue, StdHeader); - - //2. Copy P0 to P1 - LibAmdMsrWrite (MSR_PSTATE_1 + (UINT32) SwP0, &MsrValue, StdHeader); - - //3. Increment F3xDC[PstatemaxVal] by 1. - PciAddress.Address.Register = CPTC2_REG; - PciAddress.Address.Function = FUNC_3; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal++; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - //4. Write 001b to MSRC001_0062[PstateCmd]. - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader); - - //5. Wait for MSRC001_0071[CurCpuFid] = P1[CpuFid]. - do { - LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader); - } while (((COFVID_STS_MSR *) &MsrValue)->CurCpuFid != TempVar_d); - - //6. Write 000b to MSRC001_0062[PstateCmd]. - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader); - - //7. Wait for MSRC001_0071[CurPstate] = MSRC001_0071[CurPstateLimit]. - do { - LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader); - } while (((COFVID_STS_MSR *) &MsrValue)->CurPstate != ((COFVID_STS_MSR *) &MsrValue)->CurPstateLimit); - - //8. Write 0b to P1[PstateEn]. - LibAmdMsrRead (MSR_PSTATE_1 + (UINT32) SwP0, &MsrValue, StdHeader); - ((PSTATE_MSR *) &MsrValue)->PsEnable = 0; - LibAmdMsrWrite (MSR_PSTATE_1 + (UINT32) SwP0, &MsrValue, StdHeader); - - //9. Decrement F3xDC[PstateMaxVal] by 1 and exit the sequence (no further steps are required). - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal--; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - } else { - - TempVar_f = MSR_PSTATE_0 + (UINT32) SwP0; - - for (k = SwP0; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++, TempVar_f++) { - // If pState is not disabled then do update - LibAmdMsrRead (TempVar_f, &MsrValue, StdHeader); - - if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable == 1) { - Status = F15OrGetFrequencyXlatRegInfo (PstateCpuServices, (UINT8) k, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader); - if (Status != AGESA_ERROR) { - // Bits 5:0 - ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d; - // Bits 8:6 - ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e; - } - - // Bits 39:32 - ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddValue; - // Bits 41:40 - ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddDiv; - // Enable the P-State - ((PSTATE_MSR *) &MsrValue)->PsEnable = 1; - LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader); - } else { - // Disable the P-State - ((PSTATE_MSR *) &MsrValue)->PsEnable = 0; - LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader); - } - } - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to calculates the power in milliWatts of the desired P-state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StateNumber Which P-state to analyze - * @param[out] PowerInMw The Power in milliWatts of that P-State - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F15OrGetPstatePower ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpuVid; - UINT32 IddValue; - UINT32 IddDiv; - UINT32 V_x10000; - UINT32 Power; - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); - CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid); - IddValue = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddValue); - IddDiv = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddDiv); - - if (CpuVid >= 0x7C) { - V_x10000 = 0; - } else { - V_x10000 = 15500L - (125L * CpuVid); - } - - Power = V_x10000 * IddValue; - - switch (IddDiv) { - case 0: - *PowerInMw = Power / 10L; - break; - case 1: - *PowerInMw = Power / 100L; - break; - case 2: - *PowerInMw = Power / 1000L; - break; - default: - // IddDiv is set to an undefined value. This is due to either a misfused CPU, or - // an invalid P-state MSR write. - ASSERT (FALSE); - *PowerInMw = 0; - break; - } - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get CPU pstate max state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[out] MaxPStateNumber The max hw pstate value on the current socket. - * @param[out] NumberOfBoostStates The number of boosted P-states on the current socket. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F15OrGetPstateMaxState ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NumBoostStates; - UINT64 MsrValue; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - LocalPciRegister = 0; - - // For F15 Orochi CPU, skip boosted p-state. The boosted p-state number = D[1F:18]F4x15C[NumBoostStates]. - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Register = CPB_CTRL_REG; - PciAddress.Address.Function = FUNC_4; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C - - NumBoostStates = ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - *NumberOfBoostStates = (UINT8) NumBoostStates; - - // - // Read PstateMaxVal [6:4] from MSR C001_0061 - // So, we will know the max pstate state in this socket. - // - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader); - *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + NumBoostStates; - - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get CPU pstate register information. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] PState Input Pstate number for query. - * @param[out] PStateEnabled Boolean flag return pstate enable. - * @param[in,out] IddVal Pstate current value. - * @param[in,out] IddDiv Pstate current divisor. - * @param[out] SwPstateNumber Software P-state number. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F15OrGetPstateRegisterInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - PCI_ADDR PciAddress; - - ASSERT (PState < NM_PS_REG); - - // For F15 Orochi CPU, skip boosted p-state. The boosted p-state number = D[1F:18]F4x15C[NumBoostStates]. - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Register = CPB_CTRL_REG; - PciAddress.Address.Function = FUNC_4; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C - - // Read PSTATE MSRs - LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrRegister, StdHeader); - - *SwPstateNumber = PState; - - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - // PState enable = bit 63 - *PStateEnabled = TRUE; - // - // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE. - // - if (PState < ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates) { - *PStateEnabled = FALSE; - } else { - *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - } - } else { - *PStateEnabled = FALSE; - } - - // Bits 39:32 (high 32 bits [7:0]) - *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddValue; - // Bits 41:40 (high 32 bits [9:8]) - *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddDiv; - - return (AGESA_SUCCESS); -} - - -CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices = -{ - 0, - F15OrIsPstatePsdNeeded, - F15OrIsPstatePsdDependent, - F15OrSetTscFreqSel, - F15OrGetPstateTransLatency, - F15OrGetPstateFrequency, - F15OrPstateLevelingCoreMsrModify, - F15OrGetPstatePower, - F15OrGetPstateMaxState, - F15OrGetPstateRegisterInfo -}; - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - - -/** - *--------------------------------------------------------------------------------------- - * - * F15OrGetPowerStepValueInTime - * - * Description: - * Convert power step value in time - * - * Parameters: - * @param[out] *PowerStepPtr - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -STATIC -F15OrGetPowerStepValueInTime ( - IN OUT UINT32 *PowerStepPtr - ) -{ - UINT32 TempVar_a; - - TempVar_a = *PowerStepPtr; - - if (TempVar_a < 0x4) { - *PowerStepPtr = 400 - (TempVar_a * 100); - } else if (TempVar_a < 0x9) { - *PowerStepPtr = 130 - (TempVar_a * 10); - } else { - *PowerStepPtr = 90 - (TempVar_a * 5); - } -} - -/** - *--------------------------------------------------------------------------------------- - * - * F15OrGetPllValueInTime - * - * Description: - * Convert PLL Value in time - * - * Parameters: - * @param[out] *PllLockTimePtr - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -STATIC -F15OrGetPllValueInTime ( - IN OUT UINT32 *PllLockTimePtr - ) -{ - if (*PllLockTimePtr < 4) { - *PllLockTimePtr = *PllLockTimePtr + 1; - } else if (*PllLockTimePtr == 4) { - *PllLockTimePtr = 8; - } else if (*PllLockTimePtr == 5) { - *PllLockTimePtr = 16; - } else - *PllLockTimePtr = 0; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will return the CpuFid and CpuDid in MHz, using the formula - * described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0 - * - * @param[in] PstateCpuServices The current Family Specific Services. - * @param[in] PStateNumber P-state number to check. - * @param[in] Frequency Leveled target frequency for PStateNumber. - * @param[out] *CpuFidPtr New leveled FID. - * @param[out] *CpuDidPtr1 New leveled DID info 1. - * @param[out] *CpuDidPtr2 New leveled DID info 2. - * @param[in] *StdHeader Header for library and services. - * - * @retval AGESA_WARNING This P-State does not need to be modified. - * @retval AGESA_SUCCESS This P-State must be modified to be level. - */ -AGESA_STATUS -STATIC -F15OrGetFrequencyXlatRegInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 PStateNumber, - IN UINT32 Frequency, - OUT UINT32 *CpuFidPtr, - OUT UINT32 *CpuDidPtr1, - OUT UINT32 *CpuDidPtr2, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 j; - AGESA_STATUS Status; - UINT32 FrequencyInMHz; - - FrequencyInMHz = 0; - *CpuDidPtr2 = 0xFFFF; - - Status = AGESA_SUCCESS; - - PstateCpuServices->GetPstateFrequency (PstateCpuServices, PStateNumber, &FrequencyInMHz, StdHeader); - if (FrequencyInMHz == Frequency) { - Status |= AGESA_WARNING; - } - - // CPU Frequency = 100 MHz * (CpuFid + 10h) / (2^CpuDid) - // In this for loop i = 2^CpuDid - - - for (i = 1; i < 17; (i += i)) { - for (j = 0; j < 64; j++) { - if (Frequency == ((100 * (j + 0x10)) / i )) { - *CpuFidPtr = j; - if (i == 1) { - *CpuDidPtr1 = 0; - } else if (i == 2) { - *CpuDidPtr1 = 1; - } else if (i == 4) { - *CpuDidPtr1 = 2; - } else if (i == 8) { - *CpuDidPtr1 = 3; - } else if (i == 16) { - *CpuDidPtr1 = 4; - } else { - *CpuFidPtr = 0xFFFF; - *CpuDidPtr1 = 0xFFFF; - } - // Success - return Status; - } - } - } - - // Error Condition - *CpuFidPtr = 0x00FF; - *CpuDidPtr1 = 0x00FF; - *CpuDidPtr2 = 0x00FF; - - return AGESA_ERROR; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c deleted file mode 100644 index cd0dc48249..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c +++ /dev/null @@ -1,128 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi thermal initialization - * - * Performs processor thermal initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "OptionFamily15hEarlySample.h" -#include "OptionMultiSocket.h" -#include "cpuF15OrSoftwareThermal.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORSOFTWARETHERMAL_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F15_OR_ES_CORE_SUPPORT F15OrEarlySampleCoreSupport; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Main entry point for initializing the Thermal Control - * safety net feature. - * - * This must be run by all Family 15h Orochi core 0s in the system. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service parameters. - * @param[in] StdHeader Config handle for library and services. - */ -VOID -F15OrPmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Core; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - if (OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader)) { - GetCurrentCore (&Core, StdHeader); - ASSERT (Core == 0); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) { - // Enable HTC - PciAddress.Address.Register = HTC_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((HTC_REGISTER *) &LocalPciRegister)->HtcSlewSel = 0; - ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1; - F15OrEarlySampleCoreSupport.F15OrHtcInitHook (&LocalPciRegister, StdHeader); - IDS_OPTION_HOOK (IDS_HTC_CTRL, &LocalPciRegister, StdHeader); - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.h deleted file mode 100644 index 130c73df1d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi thermal initialization related functions and structures - * - * Performs processor thermal initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 45341 $ @e \$Date: 2011-01-14 15:49:18 -0700 (Fri, 14 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_SOFTWARE_THERMAL_H_ -#define _CPU_F15_OR_SOFTWARE_THERMAL_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrPmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F15_OR_SOFTWARE_THERMAL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c deleted file mode 100644 index becfb3c687..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c +++ /dev/null @@ -1,179 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 specific utility functions. - * - * Provides numerous utility functions specific to family 15h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "cpuCommonF15Utilities.h" -#include "cpuF15PowerMgmt.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Set warm reset status and count - * - * @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}. - * - * This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * @param[in] Request Indicate warm reset status - * - */ -VOID -F15SetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ) -{ - PCI_ADDR PciAddress; - UINT32 PciData; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - - // bit[5] - indicate a warm reset is or is not required - PciData &= ~(HT_INIT_BIOS_RST_DET_0); - PciData = PciData | (Request->RequestBit << 5); - - // bit[10,9] - indicate warm reset status and count - PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2); - PciData |= Request->StateBits << 9; - - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get warm reset status and count - * - * @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}. - * - * This function will bit9, and bit 10 of register F0x6C as a warm reset status and count. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Config handle for library and services - * @param[out] Request Indicate warm reset status - * - */ -VOID -F15GetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ) -{ - PCI_ADDR PciAddress; - UINT32 PciData; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - - // bit[5] - indicate a warm reset is or is not required - Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5); - // bit[10,9] - indicate warm reset status and count - Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Return a number zero or one, based on the Core ID position in the initial APIC Id. - * - * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval CoreIdPositionZero Core Id is not low - * @retval CoreIdPositionOne Core Id is low - */ -CORE_ID_POSITION -F15CpuAmdCoreIdPositionInInitialApicId ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 InitApicIdCpuIdLo; - - // Check bit_54 [InitApicIdCpuIdLo] to find core id position. - LibAmdMsrRead (MSR_NB_CFG, &InitApicIdCpuIdLo, StdHeader); - InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54); - return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne); -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h deleted file mode 100644 index 80e8c99ead..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h +++ /dev/null @@ -1,90 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 specific utility functions. - * - * Provides numerous utility functions specific to family 15h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_COMMON_F15_UTILITES_H_ -#define _CPU_COMMON_F15_UTILITES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -CORE_ID_POSITION -F15CpuAmdCoreIdPositionInInitialApicId ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15SetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ); - -VOID -F15GetAgesaWarmResetFlag ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ); - -#endif // _CPU_COMMON_F15_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c deleted file mode 100644 index 020e159da9..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c +++ /dev/null @@ -1,124 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 APM Initialization - * - * Enables Application Power Management feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15PowerMgmt.h" -#include "CommonReturns.h" -#include "cpuApm.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------*/ -/** - * Entry point for enabling Application Power Management - * - * This function must be run after all P-State routines have been executed - * - * @param[in] ApmServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15InitializeApm ( - IN APM_FAMILY_SERVICES *ApmServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CPB_CTRL_REG; - LocalPciRegister = 0; - ((F15_CPB_CTRL_REGISTER *) (&LocalPciRegister))->ApmMasterEn = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, 0xFFFFFFFF, LocalPciRegister, StdHeader); - - return AGESA_SUCCESS; -} - - - -CONST APM_FAMILY_SERVICES ROMDATA F15ApmSupport = -{ - 0, - (PF_APM_IS_SUPPORTED) CommonReturnTrue, - F15InitializeApm -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c deleted file mode 100644 index 052ce94895..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c +++ /dev/null @@ -1,221 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions and structures. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuEarlyInit.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -#define NAME_STRING_ADDRESS_PORT 0x194 -#define NAME_STRING_DATA_PORT 0x198 - -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/// A structure containing brand string -typedef struct { - CONST CHAR8 *Stringstart; ///< The literal string -} CPU_F15_EXCEPTION_BRAND; - -/// FAM15_BRAND_STRING_MSR -typedef struct _PROCESSOR_NAME_STRING { - UINT32 lo; ///< lower 32-bits of 64-bit value - UINT32 hi; ///< highest 32-bits of 64-bit value -} PROCESSOR_NAME_STRING; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -IsException ( - OUT UINT32 *ExceptionId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15SetBrandIdRegistersAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -// This is an example, need to be updated once Processor Revision Guide define brand string exception -// Brand string is always 48 bytes -CONST CHAR8 ROMDATA str_Exception_0[48] = "AMD Phenom(tm) Octal-Core"; -CONST CHAR8 ROMDATA str_Unprogrammed_Sample[48] = "AMD Unprogrammed Engineering Sample"; -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -CONST CPU_F15_EXCEPTION_BRAND ROMDATA CpuF15ExceptionBrandIdString[] = -{ - {str_Exception_0} -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * Set the Processor Name String register based on F5x194/198 - * - * This function copies F5x198_x[B:0] to MSR_C001_00[35:30] - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15SetBrandIdRegistersAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 PciData; - UINT32 ExceptionId; - UINT32 MsrIndex; - UINT64 MsrData; - UINT64 *MsrNameStringPtrPtr; - PCI_ADDR PciAddress; - - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - if (IsException (&ExceptionId, StdHeader)) { - ASSERT (ExceptionId < (sizeof (CpuF15ExceptionBrandIdString) / sizeof (CpuF15ExceptionBrandIdString[0]))); - - MsrNameStringPtrPtr = (UINT64 *) CpuF15ExceptionBrandIdString[ExceptionId].Stringstart; - } else { - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT; - // check if D18F5x198_x0 is 00000000h. - PciData = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); - PciAddress.Address.Register = NAME_STRING_DATA_PORT; - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - if (PciData != 0) { - for (MsrIndex = 0; MsrIndex <= (MSR_CPUID_NAME_STRING5 - MSR_CPUID_NAME_STRING0); MsrIndex++) { - PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT; - PciData = MsrIndex * 2; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); - PciAddress.Address.Register = NAME_STRING_DATA_PORT; - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - ((PROCESSOR_NAME_STRING *) (&MsrData))->lo = PciData; - - PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT; - PciData = (MsrIndex * 2) + 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); - PciAddress.Address.Register = NAME_STRING_DATA_PORT; - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - ((PROCESSOR_NAME_STRING *) (&MsrData))->hi = PciData; - - LibAmdMsrWrite ((MsrIndex + MSR_CPUID_NAME_STRING0), &MsrData, StdHeader); - } - return; - } else { - // It is unprogrammed (unfused) parts and use a name string of "AMD Unprogrammed Engineering Sample" - MsrNameStringPtrPtr = (UINT64 *) str_Unprogrammed_Sample; - } - } - // Put values into name MSRs, Always write the full 48 bytes - for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) { - LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader); - MsrNameStringPtrPtr++; - } - } -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Check if it's an exception - * - * For family 15h, brand string is obtained from F5x198_x[B:0], but there may be exceptions. - * This function checks if it's an exception. - * - * @param[out] ExceptionId Id of exception - * @param[in] StdHeader Config handle for library and services. - * - * @retval TRUE It's an exception - * @retval FALSE It's NOT an exception - */ -BOOLEAN -STATIC -IsException ( - OUT UINT32 *ExceptionId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // This function will be updated, once Processor Revision Guide defines Fam15 brand string exception - *ExceptionId = 0xFFFF; - - return FALSE; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c deleted file mode 100644 index 59827789ad..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c +++ /dev/null @@ -1,196 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 ROM Execution Cache Defaults - * - * Contains default values for ROM execution cache setup - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuCacheInit.h" -#include "cpuFamilyTranslation.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF15CacheInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **CacheInfoPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -#define MEM_TRAINING_BUFFER_SIZE 16384 -#define VAR_MTRR_MASK 0x0000FFFFFFFFFFFFul -#define VAR_MTRR_MASK_CP 0x0000FFFFFFFEFFFFul - -#define HEAP_BASE_MASK_CP 0x0000FFFFFFFEFF00ul -#define HEAP_BASE_MASK 0x0000FFFFFFFFFFFFul - -#define SHARED_MEM_SIZE 0 - -CONST CACHE_INFO ROMDATA CpuF15CacheInfo = -{ - BSP_STACK_SIZE_64K, - CORE0_STACK_SIZE, - CORE1_STACK_SIZE, - MEM_TRAINING_BUFFER_SIZE, - SHARED_MEM_SIZE, - VAR_MTRR_MASK, - VAR_MTRR_MASK, - HEAP_BASE_MASK, - InfiniteExe -}; - -CONST CACHE_INFO ROMDATA CpuF15CacheInfoCP = -{ - BSP_STACK_SIZE_64K, - CORE0_STACK_SIZE, - CORE1_STACK_SIZE, - MEM_TRAINING_BUFFER_SIZE, - SHARED_MEM_SIZE, - VAR_MTRR_MASK, - VAR_MTRR_MASK_CP, - HEAP_BASE_MASK_CP, - InfiniteExe -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the family specific properties of the cache, and its usage. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] CacheInfoPtr Points to the cache info properties on exit. - * @param[out] NumberOfElements Will be one to indicate one entry. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF15CacheInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **CacheInfoPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Enabled; - UINT32 DualCore; - UINT32 Node; - PCI_ADDR PciAddress; - CPU_SPECIFIC_SERVICES *FamilyServices; - AP_MAILBOXES ApMailboxes; - CORE_PAIR_MAP *CorePairMap; - AGESA_STATUS IgnoredStatus; - - if (!IsBsp (StdHeader, &IgnoredStatus)) { - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader); - Node = ApMailboxes.ApMailInfo.Fields.Node; - - // Since pre-heap, get compute unit status from hardware, using mailbox info. - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - PciAddress.Address.Device = PciAddress.Address.Device + Node; - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = COMPUTE_UNIT_STATUS; - LibAmdPciReadBits (PciAddress, 3, 0, &Enabled, StdHeader); - LibAmdPciReadBits (PciAddress, 19, 16, &DualCore, StdHeader); - - // Find the core to compute unit mapping for this node. - CorePairMap = FamilyServices->CorePairMap; - if ((Enabled != 0) && (CorePairMap != NULL)) { - while (CorePairMap->Enabled != 0xFF) { - if ((Enabled == CorePairMap->Enabled) && (DualCore == CorePairMap->DualCore)) { - break; - } - CorePairMap++; - } - // The assert is for finding a processor configured in a way the core pair map doesn't support. - ASSERT (CorePairMap->Enabled != 0xFF); - switch (CorePairMap->Mapping) { - case AllCoresMapping: - // No cores are sharing a compute unit - *CacheInfoPtr = &CpuF15CacheInfo; - break; - case EvenCoresMapping: - // Cores are paired into compute units - *CacheInfoPtr = &CpuF15CacheInfoCP; - break; - default: - ASSERT (FALSE); - } - } - } else { - // the BSC is always just the first slice, we could return either one. Return the non for safest. - *CacheInfoPtr = &CpuF15CacheInfo; - } - *NumberOfElements = 1; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c deleted file mode 100644 index be2e263d55..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c +++ /dev/null @@ -1,122 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD DMI Record Creation API, and related functions for Family 15h. - * - * Contains code that produce the DMI related information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuLateInit.h" -#include "cpuF15PowerMgmt.h" -#include "cpuServices.h" -#include "cpuF15Dmi.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF15GetMaxSpeed - * - * Get the Max Speed - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval MaxSpeed - CPU Max Speed. - * - */ -UINT16 -DmiF15GetMaxSpeed ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - UINT32 P0Frequency; - UINT32 PciData; - PCI_ADDR PciAddress; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - NumBoostStates = (UINT8) ((PciData >> 2) & 7); - - FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader); - return ((UINT16) P0Frequency); -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.h deleted file mode 100644 index bf68ec0494..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.h +++ /dev/null @@ -1,75 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD DMI Record Creation API, and related functions for Family 15h. - * - * Contains code that produce the DMI related information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F15_DMI_H_ -#define _CPU_F15_DMI_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -UINT16 -DmiF15GetMaxSpeed ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F15_DMI_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15MsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15MsrTables.c deleted file mode 100644 index e91402940c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15MsrTables.c +++ /dev/null @@ -1,136 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 MSR tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * @e \$Revision: 54966 $ @e \$Date: 2011-06-14 23:46:12 -0600 (Tue, 14 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15MsrRegisters[] = -{ -// M S R T a b l e s -// ---------------------- - -// MSR_HWCR (0xC0010015) -// bit[4] = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_HWCR, // MSR Address - 0x0000000000000010, // OR Mask - 0x0000000000000010, // NAND Mask - }} - }, -// MSR_NB_CFG (0xC001001F) -// bit[23] = 1, erratum #663 -// bit[54] InitApicIdCpuIdLo = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_NB_CFG, // MSR Address - 0x0040000000800000, // OR Mask - 0x0040000000800000, // NAND Mask - }} - }, -// This MSR should be set after the code that most errata would be applied in -// MSR_MC0_CTL (0x00000400) -// bits[63:0] = 0xFFFFFFFFFFFFFFFF - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_MC0_CTL, // MSR Address - 0xFFFFFFFFFFFFFFFF, // OR Mask - 0xFFFFFFFFFFFFFFFF, // NAND Mask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable = { - AllCores, - (sizeof (F15MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *)F15MsrRegisters, -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PciTables.c deleted file mode 100644 index c0085c7d41..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PciTables.c +++ /dev/null @@ -1,206 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * @e \$Revision: 59440 $ @e \$Date: 2011-09-22 19:44:44 -0600 (Thu, 22 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15PciRegisters[] = -{ -// F2x1B0 - Extended Memory Controller Configuration Low -// bits[10:8], CohPrefPrbLmt = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address - 0x00000100, // regData - 0x00000700, // regMask - }} - }, - -// Function 3 - Misc. Control - -// F3x6C - Data Buffer Count -// bits[30:28] IsocRspDBC = 1 -// bits[18:16] UpRspDBC = 1 -// bits[7:6] DnRspDBC = 1 -// bits[5:4] DnReqDBC = 1 -// bits[2:0] UpReqDBC = 2 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address - 0x10010052, // regData - 0x700700F7, // regMask - }} - }, -// F3xA0 - Power Control Miscellaneous -// bits[13:11] PllLockTime = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address - 0x00000800, // regData - 0x00003800, // regMask - }} - }, -// F3xA4 - Reported Temperature Control -// bits[12:8] PerStepTimeDn = 0x0F -// bits[7] TmpSlewDnEn = 1 -// bits[6:5] TmpMaxDiffUp = 3 -// bits[4:0] PerStepTimeUp = 0x0F - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address - 0x00000FEF, // regData - 0x00001FFF, // regMask - }} - }, -// F3xDC - Clock Power Timing Control 2 -// bit [26] IgnCpuPrbEn = 1 -// bits[14:12] NbsynPtrAdj = 5 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address - 0x04005000, // regData - 0x04007000, // regMask - }} - }, -// F3x1CC - IBS Control -// bits[8] LvtOffsetVal = 1 -// bits[3:0] LvtOffset = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address - 0x00000100, // regData - 0x0000010F, // regMask - }} - }, -// F4x15C - Core Performance Boost Control -// bits[1:0] BoostSrc = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address - 0x00000000, // regData - 0x00000003, // regMask - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15PciRegisterTable = { - PrimaryCores, - (sizeof (F15PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F15PciRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c deleted file mode 100644 index 6242410a23..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c +++ /dev/null @@ -1,441 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 P-State power check - * - * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as - * described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * @e \$Revision: 56273 $ @e \$Date: 2011-07-11 12:53:52 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuF15PowerMgmt.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15PowerCheck.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15PwrCheckAllCoresGoToLegalPstate ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F15PwrCheckPrimaryCoresAdjustPstates ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F15PwrCheckAllCoresGoToCurrentPs ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F15PmPwrChkCopyPstate ( - IN UINT8 Dest, - IN UINT8 Src, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------*/ -/** - * Family 15h core 0 entry point for performing the family 15h Processor- - * Systemboard Power Delivery Check. - * - * The steps are as follows: - * 1. Starting with SW P0, loop through all P-states until a passing state - * is found. A passing state is one in which the current required by - * the CPU is less than the maximum amount of current that the system - * can provide to the CPU. If P0 is under the limit, no further action - * is necessary. - * 2. If at least one P-State is under the limit & at least one P-State is - * over the limit, the BIOS must: - * a. If the processor's current P-State is disabled by the power check, - * then the BIOS must request a transition to an enabled P-state - * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] - * to reflect the new value. - * b. Program D18F4x15C[BoostSrc] to zero. - * c. Copy the contents of the enabled P-state MSRs to the highest - * performance P-state locations. - * d. Request a P-state transition to the P-state MSR containing the - * COF/VID values currently applied. - * e. Adjust the following P-state parameters affected by the P-state - * MSR copy by subtracting the number of P-states that are disabled - * by the power check. - * 1. F3x64[HtcPstateLimit] - * 2. F3x68[SwPstateLimit] - * 3. F3xDC[PstateMaxVal] - * 3. If all P-States are over the limit, the BIOS must: - * a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then - * write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for - * MSRC001_0063[CurPstate] to reflect the new value. - * b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state - * MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR. - * Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063 - * [CurPstate] to reflect the new value. - * c. Adjust the following P-state parameters to zero: - * 1. F3x64[HtcPstateLimit] - * 2. F3x68[SwPstateLimit] - * 3. F3xDC[PstateMaxVal] - * d. Program D18F4x15C[BoostSrc] to zero. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15PmPwrCheck ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 DisPsNum; - UINT8 PsMaxVal; - UINT8 Pstate; - UINT32 ProcIddMax; - UINT32 LocalPciRegister; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 AndMask; - UINT32 OrMask; - UINT32 PstateLimit; - UINT32 HighCore; - UINT32 LowCore; - UINT32 ModuleIndex; - UINT64 LocalMsrRegister; - BOOLEAN AllPstatesDisabled; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - PWRCHK_ERROR_DATA ErrorData; - - // get the socket number - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - - ASSERT (Core == 0); - - // get the Max P-state value - for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { - LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader); - if (((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - break; - } - } - - ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CPB_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C - ErrorData.NumberOfBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - - // Starting with SW P0, loop through all P-states until a passing state - // is found. A passing state is one in which the current required by - // the CPU is less than the maximum amount of current that the system - // can provide to the CPU. If P0 is under the limit, no further action - // is necessary. - DisPsNum = 0; - AllPstatesDisabled = TRUE; - - for (Pstate = ErrorData.NumberOfBoostStates; Pstate < ErrorData.HwPstateNumber; Pstate++) { - if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) { - if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) { - // Add to event log the Pstate that exceeded the current limit - PutEventLog (AGESA_WARNING, - CPU_EVENT_PM_PSTATE_OVERCURRENT, - Socket, Pstate, 0, 0, StdHeader); - DisPsNum++; - } else { - AllPstatesDisabled = FALSE; - break; - } - } - } - - if (DisPsNum != 0) { - ErrorData.NumberOfSwPstatesDisabled = DisPsNum; - - if (AllPstatesDisabled) { - // All P-states are over the limit - PutEventLog (AGESA_FATAL, - CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT, - Socket, 0, 0, 0, StdHeader); - ErrorData.NumberOfSwPstatesDisabled--; - } - - // Launch APs to transition to a valid P-state - TaskPtr.FuncAddress.PfApTaskI = F15PwrCheckAllCoresGoToLegalPstate; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA); - TaskPtr.DataTransfer.DataPtr = &ErrorData; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams); - - // If any software P-states are disabled, then program D18F4x15C[BoostSrc] to zero. - AndMask = 0xFFFFFFFF; - ((F15_CPB_CTRL_REGISTER *) &AndMask)->BoostSrc = 0; - OrMask = 0x00000000; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x15C - - // Modify P-state MSRs on one core per die - TaskPtr.FuncAddress.PfApTaskI = F15PwrCheckPrimaryCoresAdjustPstates; - - for (ModuleIndex = 0; ModuleIndex < GetPlatformNumberOfModules (); ModuleIndex++) { - if (ModuleIndex != Module) { - if (GetGivenModuleCoreRange (Socket, ModuleIndex, &LowCore, &HighCore, StdHeader)) { - ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)LowCore, &TaskPtr, StdHeader); - } - } - } - F15PwrCheckPrimaryCoresAdjustPstates (&ErrorData, StdHeader); - - // Launch APs to transition to the current P-state at its new location - TaskPtr.FuncAddress.PfApTaskI = F15PwrCheckAllCoresGoToCurrentPs; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams); - - // Final Step - // F3x64[HtPstatelimit] -= disPsNum - // F3x68[SwPstateLimit] -= disPsNum - // F3xDC[PstateMaxVal] -= disPsNum - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = HTC_REG; - AndMask = 0xFFFFFFFF; - ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0; - OrMask = 0x00000000; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64 - PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit; - if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { - PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; - ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64 - - PciAddress.Address.Register = SW_PS_LIMIT_REG; - AndMask = 0xFFFFFFFF; - ((SW_PS_LIMIT_REGISTER *) &AndMask)->SwPstateLimit = 0; - OrMask = 0x00000000; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68 - PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit; - if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { - PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; - ((SW_PS_LIMIT_REGISTER *) &OrMask)->SwPstateLimit = PstateLimit; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68 - - PciAddress.Address.Register = CPTC2_REG; - AndMask = 0xFFFFFFFF; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0; - OrMask = 0x00000000; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC - PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal; - if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { - PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * First phase core-level error handler called if any p-states were determined - * to be out of range for the mother board. - * - * Transitions to a legal P-state if necessary (steps 2a and 3a) on each core. - * - * @param[in] ErrorData Details about the error condition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15PwrCheckAllCoresGoToLegalPstate ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 CurrentPs; - UINT64 LocalMsrRegister; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate); - - if (CurrentPs < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) { - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled, (BOOLEAN) TRUE, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Core-level error handler called if any p-states were determined to be out - * of range for the mother board. - * - * This function implements steps 2c and the first half of 3b on one core per die. - * - * @param[in] ErrorData Details about the error condition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15PwrCheckPrimaryCoresAdjustPstates ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 HwPsMaxVal; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - HwPsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); - for (i = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates; (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) <= HwPsMaxVal; i++) { - F15PmPwrChkCopyPstate (i, (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled), StdHeader); - } - - // Disable the appropriate P-states if any, starting from HW Pmin - for (i = 0; i < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled; i++) { - FamilySpecificServices->DisablePstate (FamilySpecificServices, (HwPsMaxVal - i), StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Second phase core-level error handler called if any p-states were determined - * to be out of range for the mother board. - * - * Transitions to the core's current P-state in its new location (steps 2d and - * the second half of 3b) on each core. - * - * @param[in] ErrorData Details about the error condition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15PwrCheckAllCoresGoToCurrentPs ( - IN VOID *ErrorData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 CurrentPs; - UINT64 LocalMsrRegister; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate) - ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled; - - FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Copies the contents of one P-State MSR to another. - * - * @param[in] Dest Destination p-state number - * @param[in] Src Source p-state number - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -F15PmPwrChkCopyPstate ( - IN UINT8 Dest, - IN UINT8 Src, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader); - LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader); -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.h deleted file mode 100644 index 3206fbf1da..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.h +++ /dev/null @@ -1,82 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Power related functions and structures - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F15_POWER_CHECK_H_ -#define _CPU_F15_POWER_CHECK_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/// Power Check Error Data -typedef struct { - UINT8 SocketNumber; ///< Socket Number - UINT8 HwPstateNumber; ///< Number of hardware P-states - UINT8 AllowablePstateNumber; ///< Number of allowable P-states - UINT8 NumberOfBoostStates; ///< Number of boosted P-states - UINT8 NumberOfSwPstatesDisabled; ///< Number of software P-states disabled -} PWRCHK_ERROR_DATA; - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15PmPwrCheck ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F15_POWER_CHECK_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h deleted file mode 100644 index 7b4125da11..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h +++ /dev/null @@ -1,292 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Power Management related registers defination - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPUF15POWERMGMT_H_ -#define _CPUF15POWERMGMT_H_ - -/* - * Family 15h CPU Power Management MSR definitions - * - */ - - -/* Last Branch From IP Register 0x000001DB */ -#define MSR_BR_FROM 0x000001DBul - -/* P-state Current Limit Register 0xC0010061 */ -#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061ul // F15 Shared - -/// Pstate Current Limit MSR Register -typedef struct { - UINT64 CurPstateLimit:3; ///< Current Pstate Limit - UINT64 :1; ///< Reserved - UINT64 PstateMaxVal:3; ///< Pstate Max Value - UINT64 :57; ///< Reserved -} PSTATE_CURLIM_MSR; - - -/* P-state Control Register 0xC0010062 */ -#define MSR_PSTATE_CTL 0xC0010062ul // F15 Shared - -/// Pstate Control MSR Register -typedef struct { - UINT64 PstateCmd:3; ///< Pstate change command - UINT64 :61; ///< Reserved -} PSTATE_CTRL_MSR; - - -/* P-state Status Register 0xC0010063 */ -#define MSR_PSTATE_STS 0xC0010063ul - -/// Pstate Status MSR Register -typedef struct { - UINT64 CurPstate:3; ///< Current Pstate - UINT64 :61; ///< Reserved -} PSTATE_STS_MSR; - - -/* P-state Registers 0xC001006[B:4] */ -#define MSR_PSTATE_0 0xC0010064ul -#define MSR_PSTATE_1 0xC0010065ul -#define MSR_PSTATE_2 0xC0010066ul -#define MSR_PSTATE_3 0xC0010067ul -#define MSR_PSTATE_4 0xC0010068ul -#define MSR_PSTATE_5 0xC0010069ul -#define MSR_PSTATE_6 0xC001006Aul -#define MSR_PSTATE_7 0xC001006Bul - -#define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */ -#define PS_MAX_REG MSR_PSTATE_7 /* Maximum P-State Register */ -#define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */ -#define NM_PS_REG 8 /* number of P-state MSR registers */ - -/// P-state MSR with common field -typedef struct { - UINT64 :63; ///< CpuFid - UINT64 PsEnable:1; ///< Pstate Enable -} F15_PSTATE_MSR; - - -/* C-state Address Register 0xC0010073 */ -#define MSR_CSTATE_ADDRESS 0xC0010073ul - -/// C-state Address MSR Register -typedef struct { - UINT64 CstateAddr:16; ///< C-state address - UINT64 :48; ///< Reserved -} CSTATE_ADDRESS_MSR; - - -/* - * Family 15h CPU Power Management PCI definitions - * - */ - -/* Extended Memory Controller Configuration Low Register F2x1B0 */ -#define EXT_MEMCTRL_CFG_LOW_REG 0x1B0 - -/// Extended Memory Controller Configuration Low PCI Register -typedef struct { - UINT32 AdapPrefMissRatio:2; ///< Adaptive prefetch miss ratio - UINT32 AdapPrefPositiveStep:2; ///< Adaptive prefetch positive step - UINT32 AdapPrefNegativeStep:2; ///< Adaptive prefetch negative step - UINT32 :2; ///< Reserved - UINT32 CohPrefPrbLmt:3; ///< Coherent prefetch probe limit - UINT32 DisIoCohPref:1; ///< Disable coherent prefetched for IO - UINT32 EnSplitDctLimits:1; ///< Split DCT write limits enable - UINT32 SpecPrefDis:1; ///< Speculative prefetch disable - UINT32 SpecPrefMis:1; ///< Speculative prefetch predict miss - UINT32 SpecPrefThreshold:3; ///< Speculative prefetch threshold - UINT32 :4; ///< Reserved - UINT32 PrefFourConf:3; ///< Prefetch four-ahead confidence - UINT32 PrefFiveConf:3; ///< Prefetch five-ahead confidence - UINT32 DcqBwThrotWm:4; ///< Dcq bandwidth throttle watermark -} EXT_MEMCTRL_CFG_LOW_REGISTER; - - -/* Hardware thermal control register F3x64 */ -#define HTC_REG 0x64 -#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG)) - -/// Hardware Thermal Control PCI Register -typedef struct { - UINT32 HtcEn:1; ///< HTC Enable - UINT32 :3; ///< Reserved - UINT32 HtcAct:1; ///< HTC Active State - UINT32 HtcActSts:1; ///< HTC Active Status - UINT32 PslApicHiEn:1; ///< P-state limit higher APIC interrupt enable - UINT32 PslApicLoEn:1; ///< P-state limit lower APIC interrupt enable - UINT32 :8; ///< Reserved - UINT32 HtcTmpLmt:7; ///< HTC temperature limit - UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select - UINT32 HtcHystLmt:4; ///< HTC hysteresis - UINT32 HtcPstateLimit:3; ///< HTC P-state limit select - UINT32 :1; ///< Reserved -} HTC_REGISTER; - - -/* Software P-state limit register F3x68 */ -#define SW_PS_LIMIT_REG 0x68 - -/// Software P-state Limit PCI Register -typedef struct { - UINT32 :5; ///< Reserved - UINT32 SwPstateLimitEn:1; ///< Software P-state limit enable - UINT32 :22; ///< Reserved - UINT32 SwPstateLimit:3; ///< HTC P-state limit select - UINT32 :1; ///< Reserved -} SW_PS_LIMIT_REGISTER; - -/* ACPI Power State Control Registers F3x84:80 */ - -/// System Management Action Field (SMAF) Register -typedef struct { - UINT8 CpuPrbEn:1; ///< CPU direct probe enable - UINT8 NbLowPwrEn:1; ///< Northbridge low-power enable - UINT8 NbGateEn:1; ///< Northbridge gate enable - UINT8 Reserved:2; ///< Reserved - UINT8 ClkDivisor:3; ///< Clock divisor -} SMAF_REGISTER; - -/// union type for ACPI State SMAF setting -typedef union { - UINT8 SMAFValue; ///< SMAF raw value - SMAF_REGISTER SMAF; ///< SMAF structure -} ACPI_STATE_SMAF; - -/// ACPI Power State Control Register F3x80 -typedef struct { - ACPI_STATE_SMAF C2; ///< [7:0] SMAF Code 000b - C2 - ACPI_STATE_SMAF C1eLinkInit; ///< [15:8] SMAF Code 001b - C1e or Link init - ACPI_STATE_SMAF SmafAct2; ///< [23:16] SMAF Code 010b - ACPI_STATE_SMAF S1; ///< [31:24] SMAF Code 011b - S1 -} ACPI_PSC_0_REGISTER; - -/// ACPI Power State Control Register F3x84 -typedef struct { - ACPI_STATE_SMAF S3; ///< [7:0] SMAF Code 100b - S3 - ACPI_STATE_SMAF Throttling; ///< [15:8] SMAF Code 101b - Throttling - ACPI_STATE_SMAF S4S5; ///< [23:16] SMAF Code 110b - S4/S5 - ACPI_STATE_SMAF C1; ///< [31:24] SMAF Code 111b - C1 -} ACPI_PSC_4_REGISTER; - - -/* Popup P-state Register F3xA8 */ -#define POPUP_PSTATE_REG 0xA8 -#define POPUP_PSTATE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, POPUP_PSTATE_REG)) - -/// Popup P-state Register -typedef struct { - UINT32 :29; ///< Reserved - UINT32 PopDownPstate:3; ///< PopDownPstate -} POPUP_PSTATE_REGISTER; - - -/* Clock Power/Timing Control 2 Register F3xDC */ -#define CPTC2_REG 0xDC -#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG)) - -/// Clock Power Timing Control 2 PCI Register -typedef struct { - UINT32 :8; ///< Reserved - UINT32 PstateMaxVal:3; ///< P-state maximum value - UINT32 :1; ///< Reserved - UINT32 NbsynPtrAdj:3; ///< NB/Core sync FIFO ptr adjust - UINT32 :1; ///< Reserved - UINT32 CacheFlushOnHaltCtl:3; ///< Cache flush on halt control - UINT32 CacheFlushOnHaltTmr:7; ///< Cache flush on halt timer - UINT32 IgnCpuPrbEn:1; ///< ignore CPU probe enable - UINT32 :5; ///< Reserved -} CLK_PWR_TIMING_CTRL2_REGISTER; - - -/* Core Performance Boost Control Register D18F4x15C */ -#define CPB_CTRL_REG 0x15C -#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG)) - -/// Core Performance Boost Control Register of Family 15h common aceess -typedef struct { - UINT32 BoostSrc:2; ///< Boost source - UINT32 NumBoostStates:3; ///< Number of boosted states - UINT32 :2; ///< Reserved - UINT32 ApmMasterEn:1; ///< APM master enable - UINT32 :23; ///< Reserved - UINT32 BoostLock:1; ///< -} F15_CPB_CTRL_REGISTER; - - -#define NM_NB_PS_REG 4 /* Number of NB P-state registers */ - -/* Northbridge P-state */ -#define NB_PSTATE_0 0x160 -#define NB_PSTATE_0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_0)) - -#define NB_PSTATE_1 0x164 -#define NB_PSTATE_1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_1)) - -#define NB_PSTATE_2 0x168 -#define NB_PSTATE_2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_2)) - -#define NB_PSTATE_3 0x16C -#define NB_PSTATE_3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_3)) - - -/* Northbridge P-state Status */ -#define F15_NB_PSTATE_CTRL 0x170 -#define F15_NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, F15_NB_PSTATE_CTRL)) - -/// Northbridge P-state Control Register -typedef struct { - UINT32 NbPstateMaxVal:2; ///< NB P-state maximum value - UINT32 :1; ///< Reserved - UINT32 NbPstateLo:2; ///< NB P-state low - UINT32 :1; ///< Reserved - UINT32 NbPstateHi:2; ///< NB P-state high - UINT32 :1; ///< Reserved - UINT32 NbPstateThreshold:3; ///< NB P-state threshold - UINT32 :1; ///< Reserved - UINT32 NbPstateDisOnP0:1; ///< NB P-state disable on P0 - UINT32 SwNbPstateLoDis:1; ///< Software NB P-state low disable - UINT32 :17; ///< Reserved -} F15_NB_PSTATE_CTRL_REGISTER; - - -#endif /* _CPUF15POWERMGMT_H */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c deleted file mode 100644 index a8d04a1c9c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c +++ /dev/null @@ -1,1176 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 specific utility functions. - * - * Provides numerous utility functions specific to family 15h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuF15PowerMgmt.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuF15Utilities.h" -#include "cpuEarlyInit.h" -#include "cpuPostInit.h" -#include "cpuFeatures.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -// HT Phy registers used in code. -#define HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL0 0x4011 -#define HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL1 0x4411 -#define HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_RD 0x400F -#define HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL0 0x520F -#define HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL1 0x530F - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/** - * HT PHY DLL Process Compensation Lookup Table. - * - * If the hardware provides compensation values, the value is provided by accessing the bitfield - * [HiBit:LoBit]. Otherwise, a default value will be used. - * - */ -typedef struct { - UINT32 DefaultComp; ///< The default compensation value if not provided by hardware. - UINT8 CtlIndexLoBit; ///< The low bit position of the compensation value. - UINT8 CtlIndexHiBit; ///< The high bit position of the compensation value. -} HT_PHY_DLL_COMP_LOOKUP_TABLE; - -/** - * Process Compensation Fuses for HT PHY, Link Phy Receiver Process Fuse Control Register. - */ -typedef struct { - UINT32 :11; - UINT32 DllProcessComp10:2; ///< [12:11] DLL Process Comp bits [1:0], this phy's adjustment. - UINT32 DllProcessComp2:1; ///< [13] DLL Process Comp bit 2, Increment or Decrement. - UINT32 : (31 - 13); -} LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL_FIELDS; - -/// Access register as fields or uint32 value. -typedef union { - UINT32 Value; ///< 32 bit value for register access - LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL_FIELDS Fields; ///< The register bit fields -} LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL; - -/** - * Link Phy Receiver Process DLL Control Register. - */ -typedef struct { - UINT32 DllProcessFreqCtlIndex2:4; ///< [3:0] The DLL Compensation override. - UINT32 : (12 - 4); - UINT32 DllProcessFreqCtlOverride:1; ///< [12] Enable DLL Compensation overriding. - UINT32 : (31 - 12); -} LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_FIELDS; - -/// Access register as fields or uint32 value. -typedef union { - UINT32 Value; ///< 32 bit value for register access - LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_FIELDS Fields; ///< The register bit fields -} LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL; - -/** - * Provide the HT PHY DLL compensation value for each HT Link frequency. - * - * The HT Frequency enum is not contiguous, there are skipped values. Rather than complicate - * index calculations, add Invalid entries here marked with an invalid compensation value (invalid - * because real compensation values are 0 .. 15). - */ -CONST STATIC HT_PHY_DLL_COMP_LOOKUP_TABLE ROMDATA HtPhyDllCompLookupTable[] = { - {0xAul, 0, 3}, // HT_FREQUENCY_1200M - {0xAul, 0, 3}, // HT_FREQUENCY_1400M - {0x7ul, 4, 7}, // HT_FREQUENCY_1600M - {0x7ul, 4, 7}, // HT_FREQUENCY_1800M - {0x5ul, 8, 11}, // HT_FREQUENCY_2000M - {0x5ul, 8, 11}, // HT_FREQUENCY_2200M - {0x4ul, 12, 15}, // HT_FREQUENCY_2400M - {0x3ul, 16, 19}, // HT_FREQUENCY_2600M - {0xFFFFFFFFul, 0, 0}, // Invalid - {0xFFFFFFFFul, 0, 0}, // Invalid - {0x3ul, 20, 23}, // HT_FREQUENCY_2800M - {0x2ul, 24, 27}, // HT_FREQUENCY_3000M - {0x2ul, 28, 31} // HT_FREQUENCY_3200M -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Disables the desired P-state. - * - * @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The P-State to disable. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F15DisablePstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 0; - LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Transitions the executing core to the desired P-state. - * - * @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The new P-State to make effective. - * @param[in] WaitForTransition True if the caller wants the transition completed upon return. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always Succeeds - */ -AGESA_STATUS -F15TransitionPstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN BOOLEAN WaitForTransition, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal >= StateNumber); - LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) StateNumber; - LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - if (WaitForTransition) { - do { - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) StateNumber); - } - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the rate at which the executing core's time stamp counter is - * incrementing. - * - * @CpuServiceMethod{::F_CPU_GET_TSC_RATE}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FrequencyInMHz TSC actual frequency. - * @param[in] StdHeader Header for library and services. - * - * @return The most severe status of all called services - */ -AGESA_STATUS -F15GetTscRate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumBoostStates; - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - PCI_ADDR PciAddress; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - LibAmdMsrRead (0xC0010015, &LocalMsrRegister, StdHeader); - if ((LocalMsrRegister & 0x01000000) != 0) { - FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CPB_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - NumBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - return (FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, FrequencyInMHz, StdHeader)); - } else { - return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader)); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Initially launches the desired core to run from the reset vector. - * - * @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] SocketNum The Processor on which the core is to be launched - * @param[in] ModuleNum The Module in that processor containing that core - * @param[in] CoreNum The Core to launch - * @param[in] PrimaryCoreNum The id of the module's primary core. - * @param[in] StdHeader Header for library and services - * - * @retval TRUE The core was launched - * @retval FALSE The core was previously launched - */ -BOOLEAN -F15LaunchApCore ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 SocketNum, - IN UINT32 ModuleNum, - IN UINT32 CoreNum, - IN UINT32 PrimaryCoreNum, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NodeRelativeCoreNum; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - BOOLEAN LaunchFlag; - AGESA_STATUS Ignored; - - // Code Start - LaunchFlag = FALSE; - NodeRelativeCoreNum = CoreNum - PrimaryCoreNum; - GetPciAddress (StdHeader, SocketNum, ModuleNum, &PciAddress, &Ignored); - PciAddress.Address.Function = FUNC_0; - - switch (NodeRelativeCoreNum) { - case 0: - PciAddress.Address.Register = HT_INIT_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & HT_INIT_CTRL_REQ_DIS) != 0) { - LocalPciRegister &= ~HT_INIT_CTRL_REQ_DIS; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 1: - PciAddress.Address.Register = CORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & CORE_CTRL_CORE1_EN) == 0) { - LocalPciRegister |= CORE_CTRL_CORE1_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 2: - PciAddress.Address.Register = CORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - if ((LocalPciRegister & CORE_CTRL_CORE2_EN) == 0) { - LocalPciRegister |= CORE_CTRL_CORE2_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, - StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 3: - PciAddress.Address.Register = CORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & CORE_CTRL_CORE3_EN) == 0) { - LocalPciRegister |= CORE_CTRL_CORE3_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 4: - PciAddress.Address.Register = CORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & CORE_CTRL_CORE4_EN) == 0) { - LocalPciRegister |= CORE_CTRL_CORE4_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 5: - PciAddress.Address.Register = CORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & CORE_CTRL_CORE5_EN) == 0) { - LocalPciRegister |= CORE_CTRL_CORE5_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 6: - PciAddress.Address.Register = CORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & CORE_CTRL_CORE6_EN) == 0) { - LocalPciRegister |= CORE_CTRL_CORE6_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 7: - PciAddress.Address.Register = CORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & CORE_CTRL_CORE7_EN) == 0) { - LocalPciRegister |= CORE_CTRL_CORE7_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 8: - PciAddress.Address.Register = CORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & CORE_CTRL_CORE8_EN) == 0) { - LocalPciRegister |= CORE_CTRL_CORE8_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - case 9: - PciAddress.Address.Register = CORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((LocalPciRegister & CORE_CTRL_CORE9_EN) == 0) { - LocalPciRegister |= CORE_CTRL_CORE9_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LaunchFlag = TRUE; - } else { - LaunchFlag = FALSE; - } - break; - - default: - break; - } - - return (LaunchFlag); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Provide the features of the next HT link. - * - * @CpuServiceMethod{::F_GET_NEXT_HT_LINK_FEATURES}. - * - * This method is different than the HT Phy Features method, because for the phy registers - * sublink 1 matches and should be programmed if the link is ganged but for PCI config - * registers sublink 1 is reserved if the link is ganged. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] Link Initially zero, each call returns the link number; - * caller passes it back unmodified each call. - * @param[in,out] LinkBase Initially the PCI bus, device, function=0, offset=0; - * Each call returns the HT Host Capability function and offset; - * Caller may use it to access registers, but must @b not modify it; - * Each new call passes the previous value as input. - * @param[out] HtHostFeats The link's features. - * @param[in] StdHeader Standard Head Pointer - * - * @retval TRUE Valid link and features found. - * @retval FALSE No more links. - */ -BOOLEAN -F15GetNextHtLinkFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT UINTN *Link, - IN OUT PCI_ADDR *LinkBase, - OUT HT_HOST_FEATS *HtHostFeats, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - UINT32 RegValue; - UINT32 ExtendedFreq; - UINTN LinkOffset; - BOOLEAN Result; - - ASSERT (FamilySpecificServices != NULL); - - // No features present unless link is good and connected. - HtHostFeats->HtHostValue = 0; - - Result = TRUE; - - // Find next link. - if (LinkBase->Address.Register == 0) { - // Beginning iteration now. - LinkBase->Address.Register = HT_CAPABILITIES_POINTER; - LibAmdPciReadBits (*LinkBase, 7, 0, &RegValue, StdHeader); - } else { - // Get next link offset. - LibAmdPciReadBits (*LinkBase, 15, 8, &RegValue, StdHeader); - } - if (RegValue == 0) { - // Are we at the end? Check if we can move to another function. - if (LinkBase->Address.Function == 0) { - LinkBase->Address.Function = 4; - LinkBase->Address.Register = HT_CAPABILITIES_POINTER; - LibAmdPciReadBits (*LinkBase, 7, 0, &RegValue, StdHeader); - } - } - - if (RegValue != 0) { - // Not at end, process the found link. - LinkBase->Address.Register = RegValue; - // Compute link number - *Link = (((LinkBase->Address.Function == 4) ? 4 : 0) + ((LinkBase->Address.Register - 0x80) >> 5)); - - // Handle pending link power off, check End of Chain, Xmit Off. - PciAddress = *LinkBase; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET; - LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader); - if (RegValue == 0) { - // Check coherency (HTHOST_LINK_TYPE_REG = 0x18) - PciAddress = *LinkBase; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET; - LibAmdPciReadBits (PciAddress, 4, 0, &RegValue, StdHeader); - if (RegValue == 3) { - HtHostFeats->HtHostFeatures.Coherent = 1; - } else if (RegValue == 7) { - HtHostFeats->HtHostFeatures.NonCoherent = 1; - } - } - - // If link was not connected, don't check other attributes, make sure - // to return zero, no match. - if ((HtHostFeats->HtHostFeatures.Coherent == 1) || (HtHostFeats->HtHostFeatures.NonCoherent == 1)) { - // Check gen3 - PciAddress = *LinkBase; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ; - LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader); - PciAddress = *LinkBase; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8)); - if (RegValue > 6) { - HtHostFeats->HtHostFeatures.Ht3 = 1; - } else { - HtHostFeats->HtHostFeatures.Ht1 = 1; - } - // Check ganged. Must check the bit for sublink 0. - LinkOffset = (*Link > 3) ? ((*Link - 4) * 4) : (*Link * 4); - PciAddress = *LinkBase; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = ((UINT32)LinkOffset + 0x170); - LibAmdPciReadBits (PciAddress, 0, 0, &RegValue, StdHeader); - if (RegValue == 0) { - HtHostFeats->HtHostFeatures.UnGanged = 1; - } else { - if (*Link < 4) { - HtHostFeats->HtHostFeatures.Ganged = 1; - } else { - // If this is a sublink 1 but it will be ganged, clear all features. - HtHostFeats->HtHostValue = 0; - } - } - } - } else { - // end of links. - Result = FALSE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Checks to see if the HT phy register table entry should be applied - * - * @CpuServiceMethod{::F_NEXT_LINK_HAS_HTFPY_FEATS}. - * - * Find the next link which matches, if any. - * This method will match for sublink 1 if the link is ganged and sublink 0 matches. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] HtHostCapability Initially the PCI bus, device, function=0, offset=0; - * Each call returns the HT Host Capability function and offset; - * Caller may use it to access registers, but must @b not modify it; - * Each new call passes the previous value as input. - * @param[in,out] Link Initially zero, each call returns the link number; caller passes it back unmodified each call. - * @param[in] HtPhyLinkType Link type field from a register table entry to compare against - * @param[out] MatchedSublink1 TRUE: It is actually just sublink 1 that matches, FALSE: any other condition. - * @param[out] Frequency0 The frequency of sublink0 (200 MHz if not connected). - * @param[out] Frequency1 The frequency of sublink1 (200 MHz if not connected). - * @param[in] StdHeader Standard Head Pointer - * - * @retval TRUE Link matches - * @retval FALSE No more links - * - */ -BOOLEAN -F15NextLinkHasHtPhyFeats ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PCI_ADDR *HtHostCapability, - IN OUT UINT32 *Link, - IN HT_PHY_LINK_FEATS *HtPhyLinkType, - OUT BOOLEAN *MatchedSublink1, - OUT HT_FREQUENCIES *Frequency0, - OUT HT_FREQUENCIES *Frequency1, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RegValue; - UINT32 ExtendedFreq; - UINT32 InternalLinks; - UINT32 Width; - PCI_ADDR PciAddress; - PCI_ADDR SubLink1Address; - HT_PHY_LINK_FEATS LinkType; - BOOLEAN IsReallyCheckingBoth; - BOOLEAN IsFound; - BOOLEAN Result; - - ASSERT (*Link < 4); - ASSERT (HtPhyLinkType != NULL); - // error checks: No unknown link type bits set and not a "match none" - ASSERT ((HtPhyLinkType->HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL | HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) == 0); - ASSERT (HtPhyLinkType->HtPhyLinkValue != 0); - - Result = FALSE; - IsFound = FALSE; - while (!IsFound) { - *Frequency0 = 0; - *Frequency1 = 0; - IsReallyCheckingBoth = FALSE; - *MatchedSublink1 = FALSE; - LinkType.HtPhyLinkValue = 0; - - // Find next link. - PciAddress = *HtHostCapability; - if (PciAddress.Address.Register == 0) { - // Beginning iteration now. - PciAddress.Address.Register = HT_CAPABILITIES_POINTER; - LibAmdPciReadBits (PciAddress, 7, 0, &RegValue, StdHeader); - } else { - // Get next link offset. - LibAmdPciReadBits (PciAddress, 15, 8, &RegValue, StdHeader); - } - if (RegValue != 0) { - HtHostCapability->Address.Register = RegValue; - // Compute link number of this sublink pair (so we don't need to account for function). - *Link = ((HtHostCapability->Address.Register - 0x80) >> 5); - - // Set the link indicators. This assumes each sublink set is contiguous, that is, links 3, 2, 1, 0 and 7, 6, 5, 4. - LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL0_LINK0 << *Link); - LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL1_LINK4 << *Link); - - // Read IntLnkRoute from the Link Initialization Status register. - PciAddress = *HtHostCapability; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x1A0; - LibAmdPciReadBits (PciAddress, 23, 16, &InternalLinks, StdHeader); - - // if ganged, don't read sublink 1, but use sublink 0 to check. - SubLink1Address = *HtHostCapability; - - // Check ganged. Since we got called for sublink 0, sublink 1 is implemented also, - // but only access it if it is also unganged. - PciAddress = *HtHostCapability; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = ((*Link * 4) + 0x170); - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - RegValue = (RegValue & 0x01); - if (RegValue == 0) { - // Then really read sublink1, rather than using sublink0 - SubLink1Address.Address.Function = 4; - IsReallyCheckingBoth = TRUE; - } - - // Checks for Sublink 0 - - // Handle pending link power off, check End of Chain, Xmit Off. - PciAddress = *HtHostCapability; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET; - LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader); - if (RegValue == 0) { - // Check coherency (HTHOST_LINK_TYPE_REG = 0x18) - PciAddress = *HtHostCapability; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - if ((RegValue & 0x1F) == 3) { - LinkType.HtPhyLinkFeatures.HtPhySL0Coh = 1; - } else if ((RegValue & 0x1F) == 7) { - LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh = 1; - } - } - - // If link was not connected, don't check other attributes, make sure - // to return zero, no match. (Phy may be powered off.) - if ((LinkType.HtPhyLinkFeatures.HtPhySL0Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh)) { - // Check gen3 - PciAddress = *HtHostCapability; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ; - LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader); - PciAddress = *HtHostCapability; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8)); - *Frequency0 = RegValue; - if (RegValue > 6) { - LinkType.HtPhyLinkFeatures.HtPhySL0Ht3 = 1; - } else { - LinkType.HtPhyLinkFeatures.HtPhySL0Ht1 = 1; - } - // Check internal / external - if ((InternalLinks & (1 << *Link)) == 0) { - // External - LinkType.HtPhyLinkFeatures.HtPhySL0External = 1; - } else { - // Internal - LinkType.HtPhyLinkFeatures.HtPhySL0Internal = 1; - } - } else { - LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL0_ALL); - } - - // Checks for Sublink 1 - // Handle pending link power off, check End of Chain, Xmit Off. - // Also, if the links are ganged but the width is not 16 bits, treat it is an inactive lane. - PciAddress = SubLink1Address; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET; - LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader); - LibAmdPciReadBits (PciAddress, 31, 24, &Width, StdHeader); - if ((RegValue == 0) && (IsReallyCheckingBoth || (Width == 0x11))) { - // Check coherency (HTHOST_LINK_TYPE_REG = 0x18) - PciAddress = SubLink1Address; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - if ((RegValue & 0x1F) == 3) { - LinkType.HtPhyLinkFeatures.HtPhySL1Coh = 1; - } else if ((RegValue & 0x1F) == 7) { - LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh = 1; - } - } - - if ((LinkType.HtPhyLinkFeatures.HtPhySL1Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh)) { - // Check gen3 - PciAddress = SubLink1Address; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ; - LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader); - PciAddress = SubLink1Address; - PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8)); - *Frequency1 = RegValue; - if (RegValue > 6) { - LinkType.HtPhyLinkFeatures.HtPhySL1Ht3 = 1; - } else { - LinkType.HtPhyLinkFeatures.HtPhySL1Ht1 = 1; - } - // Check internal / external. Note that we do really check sublink 1 regardless of ganging. - if ((InternalLinks & (1 << (*Link + 4))) == 0) { - // External - LinkType.HtPhyLinkFeatures.HtPhySL1External = 1; - } else { - // Internal - LinkType.HtPhyLinkFeatures.HtPhySL1Internal = 1; - } - } else { - LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL1_ALL); - } - - // Determine if the link matches the entry criteria. - // For Deemphasis checking, indicate whether it was actually sublink 1 that matched. - // If the link is ganged or only sublink 0 matched, or the link features didn't match, this is false. - if (((HtPhyLinkType->HtPhyLinkValue & HTPHY_LINKTYPE_SL0_AND) == 0) && - ((HtPhyLinkType->HtPhyLinkValue & HTPHY_LINKTYPE_SL1_AND) == 0)) { - // Match if any feature matches (OR) - Result = (BOOLEAN) ((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) != 0); - } else { - // Match if all features match (AND) - Result = (BOOLEAN) ((HtPhyLinkType->HtPhyLinkValue & ~(HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) == - (LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue)); - } - if (Result) { - if (IsReallyCheckingBoth && - (((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) & (HTPHY_LINKTYPE_SL1_ALL)) != 0)) { - *MatchedSublink1 = TRUE; - } - IsFound = TRUE; - } else { - // Go to next link - } - } else { - // No more links - IsFound = TRUE; - } - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Applies an HT Phy read-modify-write based on an HT Phy register table entry. - * - * @CpuServiceMethod{::F_SET_HT_PHY_REGISTER}. - * - * This function performs the necessary sequence of PCI reads, writes, and waits - * necessary to program an HT Phy register. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] HtPhyEntry HT Phy register table entry to apply - * @param[in] CapabilitySet The link's HT Host base address. - * @param[in] Link Zero based, node, link number (not package link). - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -F15SetHtPhyRegister ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN HT_PHY_TYPE_ENTRY_DATA *HtPhyEntry, - IN PCI_ADDR CapabilitySet, - IN UINT32 Link, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Temp; - UINT32 PhyReg; - PCI_ADDR PhyBase; - - // Determine the PCI config address of the HT Phy portal - PhyBase = CapabilitySet; - PhyBase.Address.Function = FUNC_4; - PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180); - - LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader); - - // Handle direct map registers if needed - PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK); - if ((HtPhyEntry->Address > 0x3FF) || ((HtPhyEntry->Address >= 0xE) && (HtPhyEntry->Address <= 0x11))) { - PhyReg |= HTPHY_DIRECT_MAP; - } - - PhyReg |= (HtPhyEntry->Address); - // Ask the portal to read the HT Phy Register contents - LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader); - do - { - LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); - } while (!(Temp & HTPHY_IS_COMPLETE_MASK)); - - // Get the current register contents and do the update requested by the table - PhyBase.AddressValue += 4; - LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); - Temp &= ~(HtPhyEntry->Mask); - Temp |= (HtPhyEntry->Data); - LibAmdPciWrite (AccessWidth32, PhyBase, &Temp, StdHeader); - - PhyBase.AddressValue -= 4; - // Ask the portal to write our updated value to the HT Phy - PhyReg |= HTPHY_WRITE_CMD; - LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader); - do - { - LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); - } while (!(Temp & HTPHY_IS_COMPLETE_MASK)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Applies an HT Phy write to a specified Phy register. - * - * @CpuServiceMethod{::F_SET_HT_PHY_REGISTER}. - * - * The caller is responsible for performing any read and modify steps. - * This function performs the necessary sequence of PCI reads, writes, and waits - * necessary to program an HT Phy register. - * - * @param[in] CapabilitySet The link's HT Host base address. - * @param[in] Link Zero based, node, link number (not package link). - * @param[in] Address The HT Phy register address - * @param[in] Data The data to write to the register - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -F15WriteOnlyHtPhyRegister ( - IN PCI_ADDR CapabilitySet, - IN UINT32 Link, - IN UINT32 Address, - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Temp; - UINT32 PhyReg; - PCI_ADDR PhyBase; - - // Determine the PCI config address of the HT Phy portal - PhyBase = CapabilitySet; - PhyBase.Address.Function = FUNC_4; - PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180); - - LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader); - - // Handle direct map registers if needed - PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK); - if ((Address > 0x3FF) || ((Address >= 0xE) && (Address <= 0x11))) { - PhyReg |= HTPHY_DIRECT_MAP; - } - - PhyReg |= (Address); - - // Get the current register contents and do the update requested by the table - PhyBase.AddressValue += 4; - LibAmdPciWrite (AccessWidth32, PhyBase, &Data, StdHeader); - - PhyBase.AddressValue -= 4; - // Ask the portal to write our updated value to the HT Phy - PhyReg |= HTPHY_WRITE_CMD; - LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader); - do - { - LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); - } while (!(Temp & HTPHY_IS_COMPLETE_MASK)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the value of an HT PHY register. - * - * Reading HT Phy registers is not generally useful, because they return the effective value, - * not the currently written value. So be warned, this function is dangerous if used to read - * a register that will be udpated subsequently elsewhere. - * - * This routine is useful for reading hardware status from the HT Phy that can be used to set - * other phy registers. - * - * @param[in] CapabilitySet The link's HT Host base address. - * @param[in] Link Zero based, node link number (not package link). - * @param[in] Address The HT Phy register address to read - * @param[in] StdHeader Config handle for library and services - * - * @return The register content (in most cases, the effective content not the pending content) - * - */ -UINT32 -STATIC -F15GetHtPhyRegister ( - IN PCI_ADDR CapabilitySet, - IN UINT32 Link, - IN UINT32 Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Temp; - UINT32 PhyReg; - PCI_ADDR PhyBase; - - // Determine the PCI config address of the HT Phy portal - PhyBase = CapabilitySet; - PhyBase.Address.Function = FUNC_4; - PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180); - - LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader); - - // Handle direct map registers if needed - PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK); - if ((Address > 0x3FF) || ((Address >= 0xE) && (Address <= 0x11))) { - PhyReg |= HTPHY_DIRECT_MAP; - } - - PhyReg |= Address; - // Ask the portal to read the HT Phy Register contents - LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader); - do - { - LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); - } while (!(Temp & HTPHY_IS_COMPLETE_MASK)); - - // Get the current register contents - PhyBase.AddressValue += 4; - LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); - - return Temp; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * A Family Specific Workaround method, to override HT DLL Compensation. - * - * \@TableTypeFamSpecificInstances. - * - * The Link Product Information register can be fused to contain an HT PHY DLL Compensation Override table. - * Based on link frequency, a compensation override can be selected from the value. - * To accomodate individual link differences in the package, each link can also have a DLL process compensation - * value set. This value can apply an adjustment to the compensation value. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config params for library, services. - */ -VOID -F15HtPhyOverrideDllCompensation ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ProductLinkInfo; - UINT32 Link; - CPU_LOGICAL_ID CpuFamilyRevision; - PCI_ADDR StartingCapabilitySet; - PCI_ADDR CapabilitySet; - PCI_ADDR PciAddress; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - BOOLEAN MatchedSublink1; - HT_FREQUENCIES Freq0; - HT_FREQUENCIES Freq1; - UINTN Sublink; - HT_PHY_LINK_FEATS DesiredLinkFeats; - BOOLEAN IsEarlyRevProcessor; - BOOLEAN IsHardwareReportingComp; - UINTN LinkFrequency; - UINT32 Compensation; - UINT32 Adjustment; - BOOLEAN IsIncrementAdjust; - LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL LinkPhyReceiverProcessFuseControl; - LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL LinkPhyReceiverProcessDllControl; - - OptionMultiSocketConfiguration.GetCurrPciAddr (&StartingCapabilitySet, StdHeader); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - // Check if the hardware reported any compensation values. - IsEarlyRevProcessor = (BOOLEAN) ((Data == 0) ? TRUE : FALSE); - PciAddress = StartingCapabilitySet; - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = 0x190; - LibAmdPciRead (AccessWidth32, PciAddress, &ProductLinkInfo, StdHeader); - IsHardwareReportingComp = (BOOLEAN) (ProductLinkInfo != 0); - - if (!IsEarlyRevProcessor || IsHardwareReportingComp) { - // Process all the sublink 0's and then all the sublink 1's that are at HT3 frequency. - for (Sublink = 0; Sublink < 2; Sublink++) { - CapabilitySet = StartingCapabilitySet; - Link = 0; - DesiredLinkFeats.HtPhyLinkValue = ((Sublink == 0) ? HTPHY_LINKTYPE_SL0_HT3 : HTPHY_LINKTYPE_SL0_HT3); - while (FamilySpecificServices->NextLinkHasHtPhyFeats ( - FamilySpecificServices, - &CapabilitySet, - &Link, - &DesiredLinkFeats, - &MatchedSublink1, - &Freq0, - &Freq1, - StdHeader)) { - - // Look up compensation value. Remember that we matched links which are at HT3 frequency, so Freq[1,0] - // should safely be greater than or equal to 1.2 GHz. - if (Sublink == 0) { - LinkFrequency = Freq0 - HT_FREQUENCY_1200M; - } else { - LinkFrequency = (MatchedSublink1 ? Freq1 : Freq0) - HT_FREQUENCY_1200M; - } - // This assert would catch frequencies higher than we know how to support, or any table overrun bug. - ASSERT (LinkFrequency < (sizeof (HtPhyDllCompLookupTable) / sizeof (HT_PHY_DLL_COMP_LOOKUP_TABLE))); - // Since there are invalid entries in the table, for frequency enum skipped values, ensure we did not - // pick one of those entries. This should be impossible from real hardware. - ASSERT (HtPhyDllCompLookupTable[LinkFrequency].DefaultComp != 0xFFFFFFFFul); - - if (IsHardwareReportingComp) { - LibAmdPciReadBits ( - PciAddress, - HtPhyDllCompLookupTable[LinkFrequency].CtlIndexHiBit, - HtPhyDllCompLookupTable[LinkFrequency].CtlIndexLoBit, - &Compensation, - StdHeader); - } else { - Compensation = HtPhyDllCompLookupTable[LinkFrequency].DefaultComp; - } - - // Apply any per PHY adjustment - LinkPhyReceiverProcessFuseControl.Value = F15GetHtPhyRegister ( - CapabilitySet, - Link, - ((Sublink == 0) ? HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL0 : HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL1), - StdHeader); - Adjustment = LinkPhyReceiverProcessFuseControl.Fields.DllProcessComp10; - IsIncrementAdjust = (BOOLEAN) ((LinkPhyReceiverProcessFuseControl.Fields.DllProcessComp2 == 0) ? TRUE : FALSE); - if (IsIncrementAdjust) { - Compensation = (((Compensation + Adjustment) > 0x000F) ? 0x000F : (Compensation + Adjustment)); - } else { - // decrement adjustment - Compensation = ((Compensation < Adjustment) ? 0 : (Compensation - Adjustment)); - } - - // Update the DLL Compensation - LinkPhyReceiverProcessDllControl.Value = F15GetHtPhyRegister ( - CapabilitySet, - Link, - HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_RD, - StdHeader); - LinkPhyReceiverProcessDllControl.Fields.DllProcessFreqCtlOverride = 1; - LinkPhyReceiverProcessDllControl.Fields.DllProcessFreqCtlIndex2 = Compensation; - F15WriteOnlyHtPhyRegister ( - CapabilitySet, - Link, - ((Sublink == 0) ? HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL0 : HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL1), - LinkPhyReceiverProcessDllControl.Value, - StdHeader); - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns whether or not BIOS is responsible for configuring the NB COFVID. - * - * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PciAddress The northbridge to query by pci base address. - * @param[out] NbVidUpdateAll Do all NbVids need to be updated - * @param[in] StdHeader Header for library and services - * - * @retval TRUE Perform northbridge frequency and voltage config. - * @retval FALSE Do not configure them. - */ -BOOLEAN -F15CommonGetNbCofVidUpdate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PCI_ADDR *PciAddress, - OUT BOOLEAN *NbVidUpdateAll, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NbVidUpdateAll = FALSE; - return FALSE; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is the Northbridge PState feature enabled? - * - * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The NB PState feature is enabled. - * @retval FALSE The NB PState feature is not enabled. - */ -BOOLEAN -F15IsNbPstateEnabled ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - BOOLEAN PowerMode; - BOOLEAN SkipHwCfg; - - SkipHwCfg = FALSE; - - IDS_OPTION_HOOK (IDS_NBPSDIS_OVERRIDE, &SkipHwCfg, StdHeader); - - // Defaults to Power Optimized Mode - PowerMode = TRUE; - - // If system is optimized for performance, disable NB P-States - if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) { - PowerMode = FALSE; - } - - PciAddress.AddressValue = F15_NB_PSTATE_CTRL_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((((((F15_NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal != 0) && - (!IsNonCoherentHt1 (StdHeader))) || SkipHwCfg) && (PowerMode)) { - return TRUE; - } - return FALSE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.h deleted file mode 100644 index f29201279a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.h +++ /dev/null @@ -1,158 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 specific utility functions. - * - * Provides numerous utility functions specific to family 15h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_F15_UTILITES_H_ -#define _CPU_F15_UTILITES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/// The structure for Software Initiated NB Voltage Transitions -typedef struct { - UINT32 VidCode; ///< VID code to transition to - BOOLEAN SlamMode; ///< Whether voltage is to be slammed, or stepped -} SW_VOLT_TRANS_NB; - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -F15DisablePstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15TransitionPstate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN BOOLEAN WaitForTransition, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15GetTscRate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15LaunchApCore ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 SocketNum, - IN UINT32 ModuleNum, - IN UINT32 CoreNum, - IN UINT32 PrimaryCoreNum, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15HtPhyOverrideDllCompensation ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15GetNextHtLinkFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT UINTN *Link, - IN OUT PCI_ADDR *LinkBase, - OUT HT_HOST_FEATS *HtHostFeats, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15NextLinkHasHtPhyFeats ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PCI_ADDR *HtHostCapability, - IN OUT UINT32 *Link, - IN HT_PHY_LINK_FEATS *HtPhyLinkType, - OUT BOOLEAN *MatchedSublink1, - OUT HT_FREQUENCIES *Frequency0, - OUT HT_FREQUENCIES *Frequency1, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15SetHtPhyRegister ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN HT_PHY_TYPE_ENTRY_DATA *HtPhyEntry, - IN PCI_ADDR CapabilitySet, - IN UINT32 Link, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15CommonGetNbCofVidUpdate ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PCI_ADDR *PciAddress, - OUT BOOLEAN *NbVidUpdateAll, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15IsNbPstateEnabled ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F15_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c deleted file mode 100644 index 5bf980a163..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c +++ /dev/null @@ -1,126 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 WHEA initial Data - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15 - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuLateInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF15WheaInitData ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **F15WheaInitDataPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AMD_HEST_BANK_INIT_DATA F15HestBankInitData[] = { - {0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403}, - {0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407}, - {0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B}, - {0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413}, - {0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417}, - {0xFFFFFFFF,0xFFFFFFFF,0x418,0x419,0x41A,0x41B}, -}; - -AMD_WHEA_INIT_DATA F15WheaInitData = { - 0x000000000, // AmdGlobCapInitDataLsd - 0x000000000, // AmdGlobCapInitDataMsd - 0x000000077, // AmdGlobCtrlInitDataLsd - 0x000000000, // AmdGlobCtrlInitDataMsd - 0x00, // AmdMcbClrStatusOnInit - 0x02, // AmdMcbStatusDataFormat - 0x00, // AmdMcbConfWriteEn - (sizeof (F15HestBankInitData) / sizeof (F15HestBankInitData[0])), // HestBankNum - &F15HestBankInitData[0] // Pointer to Initial data of HEST Bank -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the family specific WHEA table properties. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] F15WheaInitDataPtr Points to the family 15h WHEA properties. - * @param[out] NumberOfElements Will be one to indicate one structure. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF15WheaInitData ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **F15WheaInitDataPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = 1; - *F15WheaInitDataPtr = &F15WheaInitData; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/cpuFamRegisters.h deleted file mode 100644 index 4800a23895..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/cpuFamRegisters.h +++ /dev/null @@ -1,259 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Register Table Related Functions - * - * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 57647 $ @e \$Date: 2011-08-08 14:56:33 -0600 (Mon, 08 Aug 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_FAM_REGISTERS_H_ -#define _CPU_FAM_REGISTERS_H_ - -/* - *-------------------------------------------------------------- - * - * M O D U L E S U S E D - * - *--------------------------------------------------------------- - */ - -/* - *-------------------------------------------------------------- - * - * D E F I N I T I O N S / M A C R O S - * - *--------------------------------------------------------------- - */ - -// This define should be equal to the total number of families -// in the cpuFamily enum. -#define MAX_CPU_FAMILIES 64 -#define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family - -// CPU_LOGICAL_ID.Family equates -// Family 10h equates -#define AMD_FAMILY_10_RB 0x0000000000000001 -#define AMD_FAMILY_10_BL 0x0000000000000002 -#define AMD_FAMILY_10_DA 0x0000000000000004 -#define AMD_FAMILY_10_HY 0x0000000000000008 -#define AMD_FAMILY_10_PH 0x0000000000000010 -#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY - -#define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH) -#define AMD_FAMILY_GH (AMD_FAMILY_10) - -// Family 12h equates -#define AMD_FAMILY_12_LN 0x0000000000000020 -#define AMD_FAMILY_12 (AMD_FAMILY_12_LN) -#define AMD_FAMILY_LN (AMD_FAMILY_12_LN) - -// Family 14h equates -#define AMD_FAMILY_14_ON 0x0000000000000040 -#define AMD_FAMILY_ON (AMD_FAMILY_14_ON) -#define AMD_FAMILY_14_KR 0x0000000000000080 -#define AMD_FAMILY_KR (AMD_FAMILY_14_KR) -#define AMD_FAMILY_14 (AMD_FAMILY_14_ON | AMD_FAMILY_14_KR) - -// Family 15h equates -#define AMD_FAMILY_15_OR 0x0000000000000100 -#define AMD_FAMILY_OR (AMD_FAMILY_15_OR) -#define AMD_FAMILY_15_TN 0x0000000000000200 -#define AMD_FAMILY_TN (AMD_FAMILY_15_TN) -#define AMD_FAMILY_15_KM 0x0000000000000400 -#define AMD_FAMILY_KM (AMD_FAMILY_15_KM) -#define AMD_FAMILY_15 (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | AMD_FAMILY_15_KM) - -// Family 16h equates -#define AMD_FAMILY_16 0x0000000000000800 -#define AMD_FAMILY_WF (AMD_FAMILY_16) - -// Family Unknown -#define AMD_FAMILY_UNKNOWN 0x8000000000000000 - -// Family Group equates -#define AMD_FAMILY_GE_12 (AMD_FAMILY_12 | AMD_FAMILY_14 | AMD_FAMILY_15 | AMD_FAMILY_16) - -// Family 10h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - // Family 10h RB steppings -#define AMD_F10_RB_C0 0x0000000000000001 -#define AMD_F10_RB_C1 0x0000000000000002 -#define AMD_F10_RB_C2 0x0000000000000004 -#define AMD_F10_RB_C3 0x0000000000000008 - // Family 10h BL steppings -#define AMD_F10_BL_C2 0x0000000000000010 -#define AMD_F10_BL_C3 0x0000000000000020 - // Family 10h DA steppings -#define AMD_F10_DA_C2 0x0000000000000040 -#define AMD_F10_DA_C3 0x0000000000000080 - // Family 10h HY SCM steppings -#define AMD_F10_HY_SCM_D0 0x0000000000000100 -#define AMD_F10_HY_SCM_D1 0x0000000000000400 - // Family 10h HY MCM steppings -#define AMD_F10_HY_MCM_D0 0x0000000000000200 -#define AMD_F10_HY_MCM_D1 0x0000000000000800 - // Family 10h PH steppings -#define AMD_F10_PH_E0 0x0000000000001000 - // Family 10h Unknown stepping - // * This equate is used to ensure that unknown CPU revisions are * - // * identified as the last known revision of the silicon family: * - // * - Update AMD_F10_UNKNOWN whenever newer F10h steppings are added * -#define AMD_F10_UNKNOWN (AMD_FAMILY_UNKNOWN | AMD_F10_C3 | AMD_F10_D1 | AMD_F10_PH_E0) - - // Family 10h Miscellaneous equates -#define AMD_F10_C0 (AMD_F10_RB_C0) -#define AMD_F10_C1 (AMD_F10_RB_C1) -#define AMD_F10_C2 (AMD_F10_RB_C2 | AMD_F10_DA_C2 | AMD_F10_BL_C2) -#define AMD_F10_C3 (AMD_F10_RB_C3 | AMD_F10_DA_C3 | AMD_F10_BL_C3) -#define AMD_F10_Cx (AMD_F10_C0 | AMD_F10_C1 | AMD_F10_C2 | AMD_F10_C3) - -#define AMD_F10_RB_ALL (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2 | AMD_F10_RB_C3) - -#define AMD_F10_BL_ALL (AMD_F10_BL_C2 | AMD_F10_BL_C3) -#define AMD_F10_BL_Cx (AMD_F10_BL_C2 | AMD_F10_BL_C3) - -#define AMD_F10_DA_ALL (AMD_F10_DA_C2 | AMD_F10_DA_C3) -#define AMD_F10_DA_Cx (AMD_F10_DA_C2 | AMD_F10_DA_C3) - -#define AMD_F10_D0 (AMD_F10_HY_SCM_D0 | AMD_F10_HY_MCM_D0) -#define AMD_F10_D1 (AMD_F10_HY_SCM_D1 | AMD_F10_HY_MCM_D1) -#define AMD_F10_Dx (AMD_F10_D0 | AMD_F10_D1) - -#define AMD_F10_PH_ALL (AMD_F10_PH_E0) -#define AMD_F10_Ex (AMD_F10_PH_E0) - -#define AMD_F10_HY_ALL (AMD_F10_Dx) -#define AMD_F10_C32_ALL (AMD_F10_HY_SCM_D0 | AMD_F10_HY_SCM_D1) - -#define AMD_F10_GT_B0 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_Bx (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_A2 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_Ax (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_C0 ((AMD_F10_Cx & ~AMD_F10_C0) | AMD_F10_Dx | AMD_F10_Ex) -#define AMD_F10_GT_D0 ((AMD_F10_Dx & ~AMD_F10_D0) | AMD_F10_Ex) - -#define AMD_F10_ALL (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) - -// Family 12h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - - // Family 12h LN steppings -#define AMD_F12_LN_A0 0x0000000000000001 -#define AMD_F12_LN_A1 0x0000000000000002 -#define AMD_F12_LN_B0 0x0000000000000004 - // Family 12h Unknown stepping - // * This equate is used to ensure that unknown CPU revisions are * - // * identified as the last known revision of the silicon family: * - // * - Update AMD_F12_UNKNOWN whenever newer F12h steppings are added * -#define AMD_F12_UNKNOWN (AMD_FAMILY_UNKNOWN | AMD_F12_LN_B0) - -#define AMD_F12_LN_Ax (AMD_F12_LN_A0 | AMD_F12_LN_A1) -#define AMD_F12_LN_Bx (AMD_F12_LN_B0) - -#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx) - -// Family 14h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - - // Family 14h ON steppings -#define AMD_F14_ON_A0 0x0000000000000001 -#define AMD_F14_ON_A1 0x0000000000000002 -#define AMD_F14_ON_B0 0x0000000000000004 -#define AMD_F14_ON_C0 0x0000000000000008 - // Family 14h KR steppings -#define AMD_F14_KR_A0 0x0000000000000100 -#define AMD_F14_KR_A1 0x0000000000000200 -#define AMD_F14_KR_B0 0x0000000000000400 - // Family 14h Unknown stepping - // * This equate is used to ensure that unknown CPU revisions are * - // * identified as the last known revision of the silicon family: * - // * - Update AMD_F14_UNKNOWN whenever newer F14h steppings are added * -#define AMD_F14_UNKNOWN (AMD_FAMILY_UNKNOWN | AMD_F14_KR_B0 | AMD_F14_ON_C0) - -#define AMD_F14_ON_Ax (AMD_F14_ON_A0 | AMD_F14_ON_A1) -#define AMD_F14_ON_Bx (AMD_F14_ON_B0) -#define AMD_F14_ON_Cx (AMD_F14_ON_C0) -#define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx) - -#define AMD_F14_KR_Ax (AMD_F14_KR_A0 | AMD_F14_KR_A1) -#define AMD_F14_KR_Bx AMD_F14_KR_B0 -#define AMD_F14_KR_ALL (AMD_F14_KR_Ax | AMD_F14_KR_Bx) - -#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_KR_ALL) - -// Family 15h CPU_LOGICAL_ID.Revision equates -// ------------------------------------- - - // Family 15h OROCHI steppings -#define AMD_F15_OR_A0 0x0000000000000001 -#define AMD_F15_OR_A1 0x0000000000000002 -#define AMD_F15_OR_B0 0x0000000000000004 -#define AMD_F15_OR_B1 0x0000000000000008 -#define AMD_F15_OR_B2 0x0000000000000010 - // Family 15h TN steppings -#define AMD_F15_TN_A0 0x0000000000000100 - // Family 15h KM steppings -#define AMD_F15_KM_A0 0x0000000000010000 -#define AMD_F15_KM_A1 0x0000000000020000 - // Family 15h Unknown stepping - // * This equate is used to ensure that unknown CPU revisions are * - // * identified as the last known revision of the silicon family: * - // * - Update AMD_F15_UNKNOWN whenever newer F15h steppings are added * -#define AMD_F15_UNKNOWN (AMD_FAMILY_UNKNOWN | AMD_F15_OR_B2 | AMD_F15_TN_A0 | AMD_F15_KM_A1) - -#define AMD_F15_OR_Ax (AMD_F15_OR_A0 | AMD_F15_OR_A1) -#define AMD_F15_OR_Bx (AMD_F15_OR_B0 | AMD_F15_OR_B1 | AMD_F15_OR_B2) -#define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx) -#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0) -#define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx) - -#define AMD_F15_TN_Ax (AMD_F15_TN_A0) -#define AMD_F15_TN_ALL (AMD_F15_TN_Ax) - -#define AMD_F15_KM_Ax (AMD_F15_KM_A0 | AMD_F15_KM_A1) -#define AMD_F15_KM_ALL (AMD_F15_KM_Ax) - -#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_TN_ALL | AMD_F15_KM_ALL) - -// Family 16h CPU_LOGICAL_ID.Revision equates -// TBD - -#endif // _CPU_FAM_REGISTERS_H_ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/Makefile.inc deleted file mode 100644 index 0607c99c4d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/Makefile.inc +++ /dev/null @@ -1,23 +0,0 @@ -libagesa-y += PreserveMailbox.c -libagesa-y += cpuApm.c -libagesa-y += cpuC6State.c -libagesa-y += cpuCacheFlushOnHalt.c -libagesa-y += cpuCacheInit.c -libagesa-y += cpuCoreLeveling.c -libagesa-y += cpuCpb.c -libagesa-y += cpuDmi.c -libagesa-y += cpuFeatureLeveling.c -libagesa-y += cpuFeatures.c -libagesa-y += cpuHwC1e.c -libagesa-y += cpuIoCstate.c -libagesa-y += cpuL3Features.c -libagesa-y += cpuLowPwrPstate.c -libagesa-y += cpuMsgBasedC1e.c -libagesa-y += cpuPstateGather.c -libagesa-y += cpuPstateHpcMode.c -libagesa-y += cpuPstateLeveling.c -libagesa-y += cpuPstateTables.c -libagesa-y += cpuSlit.c -libagesa-y += cpuSrat.c -libagesa-y += cpuSwC1e.c -libagesa-y += cpuWhea.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/PreserveMailbox.c deleted file mode 100644 index c8e7c3aa20..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/PreserveMailbox.c +++ /dev/null @@ -1,219 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Preserve Registers used for AP Mailbox. - * - * Save and Restore the normal feature content of the registers being used for - * the AP Mailbox. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "GeneralServices.h" -#include "OptionMultiSocket.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "PreserveMailbox.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * The contents of the mailbox registers should always be preserved. - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Always TRUE - * - */ -BOOLEAN -STATIC -IsPreserveAroundMailboxEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return TRUE; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Save and Restore or Initialize the content of the mailbox registers. - * - * The registers used for AP mailbox should have the content related to their function - * preserved. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -PreserveMailboxes ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PRESERVE_MAILBOX_FAMILY_SERVICES *FamilySpecificServices; - UINT32 Socket; - UINT32 Module; - PCI_ADDR BaseAddress; - PCI_ADDR MailboxRegister; - PRESERVE_MAILBOX_FAMILY_REGISTER *NextRegister; - AGESA_STATUS IgnoredStatus; - AGESA_STATUS HeapStatus; - UINT32 Value; - ALLOCATE_HEAP_PARAMS AllocateParams; - LOCATE_HEAP_PTR LocateParams; - UINT32 RegisterEntryIndex; - - BaseAddress.AddressValue = ILLEGAL_SBDFO; - - if (EntryPoint == CPU_FEAT_AFTER_COHERENT_DISCOVERY) { - // The save step. Save either the register content or zero (for cold boot, if family specifies that). - AllocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE; - AllocateParams.RequestedBufferSize = (sizeof (UINT32) * (MAX_PRESERVE_REGISTER_ENTRIES * (MAX_SOCKETS * MAX_DIES))); - AllocateParams.Persist = HEAP_SYSTEM_MEM; - HeapStatus = HeapAllocateBuffer (&AllocateParams, StdHeader); - ASSERT ((HeapStatus == AGESA_SUCCESS) && (AllocateParams.BufferPtr != NULL)); - LibAmdMemFill (AllocateParams.BufferPtr, 0xFF, AllocateParams.RequestedBufferSize, StdHeader); - RegisterEntryIndex = 0; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) { - GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL); - NextRegister = FamilySpecificServices->RegisterList; - while (NextRegister->Register.AddressValue != ILLEGAL_SBDFO) { - ASSERT (RegisterEntryIndex < - (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ())); - if (FamilySpecificServices->IsZeroOnCold && (!IsWarmReset (StdHeader))) { - Value = 0; - } else { - MailboxRegister = BaseAddress; - MailboxRegister.Address.Function = NextRegister->Register.Address.Function; - MailboxRegister.Address.Register = NextRegister->Register.Address.Register; - LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader); - Value &= NextRegister->Mask; - } - (* (MAILBOX_REGISTER_SAVE_ENTRY) AllocateParams.BufferPtr) [RegisterEntryIndex] = Value; - RegisterEntryIndex++; - NextRegister++; - } - } - } - } - } else if ((EntryPoint == CPU_FEAT_INIT_LATE_END) || (EntryPoint == CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) { - // The restore step. Just write out the saved content in the buffer. - LocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE; - HeapStatus = HeapLocateBuffer (&LocateParams, StdHeader); - ASSERT ((HeapStatus == AGESA_SUCCESS) && (LocateParams.BufferPtr != NULL)); - RegisterEntryIndex = 0; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) { - GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader); - NextRegister = FamilySpecificServices->RegisterList; - while (NextRegister->Register.AddressValue != ILLEGAL_SBDFO) { - ASSERT (RegisterEntryIndex < - (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ())); - MailboxRegister = BaseAddress; - MailboxRegister.Address.Function = NextRegister->Register.Address.Function; - MailboxRegister.Address.Register = NextRegister->Register.Address.Register; - LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader); - Value = ((Value & ~NextRegister->Mask) | (* (MAILBOX_REGISTER_SAVE_ENTRY) LocateParams.BufferPtr) [RegisterEntryIndex]); - LibAmdPciWrite (AccessWidth32, MailboxRegister, &Value, StdHeader); - RegisterEntryIndex++; - NextRegister++; - } - } - } - } - HeapStatus = HeapDeallocateBuffer (PRESERVE_MAIL_BOX_HANDLE, StdHeader); - } - return AGESA_SUCCESS; -} - - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox = -{ - PreserveAroundMailbox, - (CPU_FEAT_AFTER_COHERENT_DISCOVERY | CPU_FEAT_INIT_LATE_END | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsPreserveAroundMailboxEnabled, - PreserveMailboxes -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/PreserveMailbox.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/PreserveMailbox.h deleted file mode 100644 index 5a1ba3e4a0..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/PreserveMailbox.h +++ /dev/null @@ -1,96 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Preserve Registers used for AP Mailbox. - * - * Save and Restore the normal feature content of the registers being used for - * the AP Mailbox. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _PRESERVE_MAILBOX_H_ -#define _PRESERVE_MAILBOX_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -#define MAX_PRESERVE_REGISTER_ENTRIES 2 ///< There is room on the heap for up to this per node. - -/// Reference to a save buffer. -typedef UINT32 (*MAILBOX_REGISTER_SAVE_ENTRY) [MAX_PRESERVE_REGISTER_ENTRIES]; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/** - * Family specific mailbox register descriptor. - * - * Describes a register and bits within the register used as the mailbox. - */ -typedef struct { - PCI_ADDR Register; ///< The PCI address of a mailbox register. - UINT32 Mask; ///< The mask of bits used in Register as the mailbox. -} PRESERVE_MAILBOX_FAMILY_REGISTER; - -/** - * Descriptor for family specific save-restore. - * - * Provide a list of the register offsets to save-restore on each node. Optionally, zero the - * register instead of restoring it. - */ -typedef struct { - UINT16 Revision; ///< Interface version - // Public Data. - BOOLEAN IsZeroOnCold; ///< On a cold boot, zero the register instead of restore. - PRESERVE_MAILBOX_FAMILY_REGISTER *RegisterList; ///< The list of registers, terminated by ILLEGAL_SBDFO. -} PRESERVE_MAILBOX_FAMILY_SERVICES; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _PRESERVE_MAILBOX_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.c deleted file mode 100644 index 733175d651..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.c +++ /dev/null @@ -1,205 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Application Power Management (APM) feature support code. - * - * Contains code that declares the AGESA CPU APM related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuApicUtilities.h" -#include "cpuFeatures.h" -#include "cpuApm.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUAPM_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -EnableApmOnSocket ( - IN VOID *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE ApmFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should Application Power Management (APM) be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE APM is supported. - * @retval FALSE APM cannot be enabled. - * - */ -BOOLEAN -STATIC -IsApmFeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - BOOLEAN IsEnabled; - APM_FAMILY_SERVICES *FamilyServices; - - IsEnabled = FALSE; - - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&ApmFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - if (FamilyServices->IsApmSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { - IsEnabled = TRUE; - break; - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable Application Power Management (APM) - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeApmFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 BscSocket; - UINT32 Ignored; - UINT32 Socket; - UINT32 NumberOfSockets; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - - IDS_HDT_CONSOLE (CPU_TRACE, " APM mode is enabled\n"); - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - TaskPtr.FuncAddress.PfApTaskI = EnableApmOnSocket; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = PlatformConfig; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - if (Socket != BscSocket) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, 0, &TaskPtr, StdHeader); - } - } - } - - EnableApmOnSocket (PlatformConfig, StdHeader); - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * AP task to enable APM - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -EnableApmOnSocket ( - IN VOID *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - APM_FAMILY_SERVICES *FamilyServices; - - GetFeatureServicesOfCurrentCore (&ApmFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - FamilyServices->EnableApmOnSocket (FamilyServices, - PlatformConfig, - StdHeader); -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm = -{ - CpuApm, - (CPU_FEAT_BEFORE_RELINQUISH_AP | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsApmFeatureEnabled, - InitializeApmFeature -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.h deleted file mode 100644 index d4d5751105..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuApm.h +++ /dev/null @@ -1,128 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Application Power Management (APM) Functions declarations. - * - * Contains code that declares the AGESA CPU APM related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_APM_H_ -#define _CPU_APM_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (APM_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if Application Power Management (APM) is supported. - * - * @param[in] ApmServices APM services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] Socket Zero-based socket number. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE APM is supported. - * @retval FALSE APM is not supported. - * - */ -typedef BOOLEAN F_APM_IS_SUPPORTED ( - IN APM_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_APM_IS_SUPPORTED *PF_APM_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable APM. - * - * @param[in] ApmServices APM services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_APM_INIT ( - IN APM_FAMILY_SERVICES *ApmServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_APM_INIT *PF_APM_INIT; - -/** - * Provide the interface to the APM Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _APM_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_APM_IS_SUPPORTED IsApmSupported; ///< Method: Family specific call to check if APM is supported. - PF_APM_INIT EnableApmOnSocket; ///< Method: Family specific call to enable APM. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_APM_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.c deleted file mode 100644 index 89426e4633..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.c +++ /dev/null @@ -1,261 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU C6 feature support code. - * - * Contains code that declares the AGESA CPU C6 related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "OptionMultiSocket.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "cpuFeatures.h" -#include "cpuC6State.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUC6STATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -EnableC6OnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should C6 be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE C6 is supported. - * @retval FALSE C6 cannot be enabled. - * - */ -BOOLEAN -STATIC -IsC6FeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - BOOLEAN IsEnabled; - C6_FAMILY_SERVICES *FamilyServices; - - IsEnabled = FALSE; - if (PlatformConfig->CStateMode == CStateModeC6) { - IsEnabled = TRUE; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); - if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, PlatformConfig, StdHeader)) { - IsEnabled = FALSE; - break; - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable the C6 C-state - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeC6Feature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AP_TASK TaskPtr; - AMD_CPU_EARLY_PARAMS CpuEarlyParams; - C6_FAMILY_SERVICES *C6FamilyServices; - AGESA_STATUS IgnoredSts; - - CpuEarlyParams.PlatformConfig = *PlatformConfig; - - TaskPtr.FuncAddress.PfApTaskIC = EnableC6OnSocket; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &EntryPoint; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); - - if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { - // Load any required microcode patches on both normal boot and resume from S3. - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, (CONST VOID **)&C6FamilyServices, StdHeader); - if (C6FamilyServices != NULL) { - C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader); - } - - // run code on all APs - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = 0; - - NumberOfSockets = GetPlatformNumberOfSockets (); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&C6FamilyServices, StdHeader); - if (C6FamilyServices != NULL) { - // run code on all APs - TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit; - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } - } - } - } - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * 'Local' core 0 task to enable C6 on it's socket. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] CpuEarlyParams Service parameters. - * - */ -VOID -STATIC -EnableC6OnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ) -{ - - C6_FAMILY_SERVICES *FamilyServices; - - IDS_HDT_CONSOLE (CPU_TRACE, " C6 is enabled\n"); - - GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - FamilyServices->InitializeC6 (FamilyServices, - *((UINT64 *) EntryPoint), - &CpuEarlyParams->PlatformConfig, - StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Reload microcode patch after memory is initialized. - * - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -ReloadMicrocodePatchAfterMemInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LoadMicrocodePatch (StdHeader); -} - - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State = -{ - C6Cstate, - (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsC6FeatureEnabled, - InitializeC6Feature -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.h deleted file mode 100644 index 7f048b28fb..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuC6State.h +++ /dev/null @@ -1,155 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU C6 Functions declarations. - * - * Contains code that declares the AGESA CPU C6 related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_C6_STATE_H_ -#define _CPU_C6_STATE_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (C6_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if C6 is supported. - * - * @param[in] C6Services C6 C-state services. - * @param[in] Socket Zero-based socket number. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE C6 is supported. - * @retval FALSE C6 is not supported. - * - */ -typedef BOOLEAN F_C6_IS_SUPPORTED ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT32 Socket, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable C6. - * - * @param[in] C6Services C6 services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_C6_INIT ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_C6_INIT *PF_C6_INIT; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to reload microcode patch after memory is initialized. - * - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT *PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT; - -/** - * Provide the interface to the C6 Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _C6_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_C6_IS_SUPPORTED IsC6Supported; ///< Method: Family specific call to check if C6 is supported. - PF_C6_INIT InitializeC6; ///< Method: Family specific call to enable C6. - PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT ReloadMicrocodePatchAfterMemInit; ///< Method: Family specific call to reload microcode patch after memory is initialized. -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * Reload microcode patch after memory is initialized. - * - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -ReloadMicrocodePatchAfterMemInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_C6_STATE_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheFlushOnHalt.c deleted file mode 100644 index 0eb4cfd7cb..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheFlushOnHalt.c +++ /dev/null @@ -1,198 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Cache Flush On Halt Function. - * - * Contains code to initialize Cache Flush On Halt feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - *---------------------------------------------------------------------------- - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuApicUtilities.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE CacheFlushOnHaltFamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -EnableCacheFlushOnHaltOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ); - -AGESA_STATUS -InitializeCacheFlushOnHaltFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Should cache flush on halt be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE core leveling is supported. - * @retval FALSE core leveling cannot be enabled. - * - */ -BOOLEAN -STATIC -IsCFOHEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (TRUE); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * InitializeCacheFlushOnHaltFeature - * - * CPU feature leveling. Enable Cpu Cache Flush On Halt Function - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in,out] StdHeader Pointer to AMD_CONFIG_PARAMS struct. - * - * @return The most severe status of any family specific service. - */ -AGESA_STATUS -InitializeCacheFlushOnHaltFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - - AP_TASK TaskPtr; - AMD_CPU_EARLY_PARAMS CpuEarlyParams; - - CpuEarlyParams.PlatformConfig = *PlatformConfig; - - IDS_HDT_CONSOLE (CPU_TRACE, " Cache flush on hlt feature is enabled\n"); - TaskPtr.FuncAddress.PfApTaskIC = EnableCacheFlushOnHaltOnSocket; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &EntryPoint; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * 'Local' core 0 task to enable Cache Flush On Halt on it's socket. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] CpuEarlyParams Service parameters. - * - */ -VOID -STATIC -EnableCacheFlushOnHaltOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ) -{ - CPU_CFOH_FAMILY_SERVICES *FamilyServices; - - GetFeatureServicesOfCurrentCore (&CacheFlushOnHaltFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - FamilyServices->SetCacheFlushOnHaltRegister (FamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader); - } -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt = -{ - CacheFlushOnHalt, - (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsCFOHEnabled, - InitializeCacheFlushOnHaltFeature -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c deleted file mode 100644 index 274844b7cd..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c +++ /dev/null @@ -1,752 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Execution Cache Allocation functions. - * - * Contains code for doing Execution Cache Allocation for ROM space - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Topology.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuCacheInit.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -// 4G - 1, ~max ROM space -#define SIZE_INFINITE_EXE_CACHE 0xFFFFFFFF - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * L2 cache Association to Way translation table - *---------------------------------------------------------------------------- - */ -CONST UINT8 ROMDATA L2AssocToL2WayTranslationTable[] = -{ - 0, - 1, - 2, - 0xFF, - 4, - 0xFF, - 8, - 0xFF, - 16, - 0xFF, - 32, - 48, - 64, - 96, - 128, - 0xFF, -}; - - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -UINT8 -STATIC -Ceiling ( - IN UINT32 Divisor, - IN UINT32 Dividend - ); - -UINT32 -STATIC -CalculateOccupiedExeCache ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -CompareRegions ( - IN EXECUTION_CACHE_REGION ARegion, - IN EXECUTION_CACHE_REGION BRegion, - IN OUT MERGED_CACHE_REGION *CRegion, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -STATIC -IsPowerOfTwo ( - IN UINT32 TestNumber - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will setup ROM execution cache. - * - * The execution cache regions are passed in, the max number of execution cache regions - * is three. Several rules are checked for compliance. If a rule test fails then one of - * these error suffixes will be added to the general CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR - * in the SubReason field - * -1 available cache size is less than requested, the ROM execution cache - * region has been reduced or eliminated. - * -2 at least one execution cache region crosses the 1MB line, the ROM execution - * cache size has been reduced. - * -3 at least one execution cache region crosses the 4GB line, the ROM execution - * cache size has been reduced. - * -4 the start address of a region is not at the boundary of cache size, - * the starting address has been adjusted downward - * -5 execution cache start address less than D0000, request is ignored - * -6 more than 2 execution cache regions are above 1MB, request is ignored - * If the start address of all three regions are zero, then no execution cache is allocated. - * - * @param[in] StdHeader Handle to config for library and services - * @param[in] AmdExeAddrMapPtr Pointer to the start of EXECUTION_CACHE_REGION array - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_WARNING AGESA_CACHE_SIZE_REDUCED; AGESA_CACHE_REGIONS_ACROSS_1MB; - * AGESA_CACHE_REGIONS_ACROSS_4GB; - * @retval AGESA_ERROR AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY; - * AGESA_CACHE_START_ADDRESS_LESS_D0000; - * AGESA_THREE_CACHE_REGIONS_ABOVE_1MB; - * - */ -AGESA_STATUS -AllocateExecutionCache ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ) -{ - AGESA_STATUS AgesaStatus; - AMD_GET_EXE_SIZE_PARAMS AmdGetExeSize; - UINT32 CurrentAllocatedExeCacheSize; - UINT32 RemainingExecutionCacheSize; - UINT64 MsrData; - UINT64 SecondMsrData; - UINT32 RequestStartAddr; - UINT32 RequestSize; - UINT32 StartFixMtrr; - UINT32 CurrentMtrr; - UINT32 EndFixMtrr; - UINT8 i; - UINT8 Ignored; - CACHE_INFO *CacheInfoPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - EXECUTION_CACHE_REGION MtrrV6; - EXECUTION_CACHE_REGION MtrrV7; - MERGED_CACHE_REGION Result; - - // - // If start addresses of all three regions are zero, then return early - // - if (AmdExeAddrMapPtr[0].ExeCacheStartAddr == 0) { - if (AmdExeAddrMapPtr[1].ExeCacheStartAddr == 0) { - if (AmdExeAddrMapPtr[2].ExeCacheStartAddr == 0) { - // No regions defined by the caller - return AGESA_SUCCESS; - } - } - } - - // Get available cache size for ROM execution - AmdGetExeSize.StdHeader = *StdHeader; - AgesaStatus = AmdGetAvailableExeCacheSize (&AmdGetExeSize); - CurrentAllocatedExeCacheSize = CalculateOccupiedExeCache (StdHeader); - ASSERT (CurrentAllocatedExeCacheSize <= AmdGetExeSize.AvailableExeCacheSize); - IDS_HDT_CONSOLE (CPU_TRACE, " Cache size available for execution cache: 0x%x\n", AmdGetExeSize.AvailableExeCacheSize); - RemainingExecutionCacheSize = AmdGetExeSize.AvailableExeCacheSize - CurrentAllocatedExeCacheSize; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); - - // Process each request entry 0 to 2 - for (i = 0; i < 3; i++) { - // Exit if no more cache available - if (RemainingExecutionCacheSize == 0) { - break; - } - - // Skip the region if ExeCacheSize = 0 - if (AmdExeAddrMapPtr[i].ExeCacheSize == 0) { - continue; - } - - // Align starting addresses on 32K boundary - AmdExeAddrMapPtr[i].ExeCacheStartAddr = - AmdExeAddrMapPtr[i].ExeCacheStartAddr & 0xFFFF8000; - - // Adjust size to multiple of 32K (rounding up) - if ((AmdExeAddrMapPtr[i].ExeCacheSize % 0x8000) != 0) { - AmdExeAddrMapPtr[i].ExeCacheSize = ((AmdExeAddrMapPtr[i].ExeCacheSize + 0x8000) & 0xFFFF8000); - } - - // Boundary alignment check and confirm size is an even power of two - if ( !IsPowerOfTwo (AmdExeAddrMapPtr[i].ExeCacheSize) || - ((AmdExeAddrMapPtr[i].ExeCacheStartAddr % AmdExeAddrMapPtr[i].ExeCacheSize) != 0) ) { - AgesaStatus = AGESA_ERROR; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY), - i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); - break; - } - - // Check start address boundary - if (AmdExeAddrMapPtr[i].ExeCacheStartAddr < 0xD0000) { - AgesaStatus = AGESA_ERROR; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_START_ADDRESS_LESS_D0000), - i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); - break; - } - - if (CacheInfoPtr->CarExeType == LimitedByL2Size) { - // Verify available execution cache size for region 0 to 2 request - if (RemainingExecutionCacheSize < AmdExeAddrMapPtr[i].ExeCacheSize) { - // Request is larger than available, reduce the allocation & report the change - AmdExeAddrMapPtr[i].ExeCacheSize = RemainingExecutionCacheSize; - RemainingExecutionCacheSize = 0; - AgesaStatus = AGESA_WARNING; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_SIZE_REDUCED), - i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); - } else { - RemainingExecutionCacheSize = RemainingExecutionCacheSize - AmdExeAddrMapPtr[i].ExeCacheSize; - } - } - IDS_HDT_CONSOLE (CPU_TRACE, " Exe cache allocated: Base 0x%x, Size 0x%x\n", AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize); - - RequestStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr; - RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; - - if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTRR region, - // turn on modification bit: MtrrFixDramModEn - LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); - MsrData |= 0x80000; - LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); - - - // Check for 1M boundary crossing - if ((RequestStartAddr + RequestSize) > 0x100000) { - // Request spans the 1M boundary, reduce the size & report the change - RequestSize = 0x100000 - RequestStartAddr; - AmdExeAddrMapPtr[i].ExeCacheSize = RequestSize; - AgesaStatus = AGESA_WARNING; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_REGIONS_ACROSS_1MB), - i, RequestStartAddr, RequestSize, 0, StdHeader); - } - - // Find start MTRR and end MTRR for the requested region - StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); - EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); - - // - //Check Mtrr before we use it, - // if Mtrr has been used, we need to recover the previously allocated size. - // (only work in blocks of 32K size - no splitting of ways) - for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) { - LibAmdMsrRead (CurrentMtrr, &MsrData, StdHeader); - if ((CacheInfoPtr->CarExeType == LimitedByL2Size) && (MsrData != 0)) { - // MTRR previously allocated, recover size - RemainingExecutionCacheSize = RemainingExecutionCacheSize + 0x8000; - } else { - // Allocate this MTRR - MsrData = WP_IO; - LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader); - } - } - // Turn off modification bit: MtrrFixDramModEn - LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); - MsrData &= 0xFFFFFFFFFFF7FFFFULL; - LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); - - - } else { - // Region above 1MB - Variable MTRR region - // Need to check both VarMTRRs for each requested region for match or overlap - // - - // Check for 4G boundary crossing (using size-1 to keep in 32bit math range) - if ((0xFFFFFFFFUL - RequestStartAddr) < (RequestSize - 1)) { - RequestSize = (0xFFFFFFFFUL - RequestStartAddr) + 1; - AgesaStatus = AGESA_WARNING; - AmdExeAddrMapPtr[i].ExeCacheSize = RequestSize; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_REGIONS_ACROSS_4GB), - i, RequestStartAddr, RequestSize, 0, StdHeader); - } - LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE6, &MsrData, StdHeader); - MtrrV6.ExeCacheStartAddr = ((UINT32) MsrData) & 0xFFFFF000UL; - LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE6 + 1, &MsrData, StdHeader); - MtrrV6.ExeCacheSize = (0xFFFFFFFFUL - (((UINT32) MsrData) & 0xFFFFF000UL)) + 1; - - LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE7, &MsrData, StdHeader); - MtrrV7.ExeCacheStartAddr = ((UINT32) MsrData) & 0xFFFFF000UL; - LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE7 + 1, &MsrData, StdHeader); - MtrrV7.ExeCacheSize = (0xFFFFFFFFUL - (((UINT32) MsrData) & 0xFFFFF000UL)) + 1; - - CompareRegions (AmdExeAddrMapPtr[i], MtrrV6, &Result, StdHeader); - if (Result.OverlapType == EmptySet) { - // MTRR6 is empty. Allocate request into MTRR6. - // Note: since all merges are moved down to MTRR6, if MTRR6 is empty so should MTRR7 also be empty - MtrrV6.ExeCacheStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr; - MtrrV6.ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize; - } else if ((Result.OverlapType == Disjoint) || - (Result.OverlapType == NotCombinable)) { - // MTRR6 is in use, and request does not overlap with MTRR6, check MTRR7 - CompareRegions (AmdExeAddrMapPtr[i], MtrrV7, &Result, StdHeader); - if (Result.OverlapType == EmptySet) { - // MTRR7 is empty. Allocate request into MTRR7. - MtrrV7.ExeCacheStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr; - MtrrV7.ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize; - } else if ((Result.OverlapType == Disjoint) || - (Result.OverlapType == NotCombinable)) { - // MTRR7 is also in use and request does not overlap - error: 3rd region above 1M - AgesaStatus = AGESA_ERROR; - PutEventLog (AgesaStatus, - (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_THREE_CACHE_REGIONS_ABOVE_1MB), - i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); - break; - } else { - // Merge request with MTRR7 - MtrrV7.ExeCacheStartAddr = Result.MergedStartAddr; - MtrrV7.ExeCacheSize = Result.MergedSize; - if (CacheInfoPtr->CarExeType == LimitedByL2Size) { - RemainingExecutionCacheSize += Result.OverlapAmount; - } - } - } else { - // Request overlaps with MTRR6, Merge request with MTRR6 - MtrrV6.ExeCacheStartAddr = Result.MergedStartAddr; - MtrrV6.ExeCacheSize = Result.MergedSize; - if (CacheInfoPtr->CarExeType == LimitedByL2Size) { - RemainingExecutionCacheSize += Result.OverlapAmount; - } - CompareRegions (MtrrV6, MtrrV7, &Result, StdHeader); - if ((Result.OverlapType != Disjoint) && - (Result.OverlapType != EmptySet) && - (Result.OverlapType != NotCombinable)) { - // MTRR6 and MTRR7 now overlap, merge them into MTRR6 - MtrrV6.ExeCacheStartAddr = Result.MergedStartAddr; - MtrrV6.ExeCacheSize = Result.MergedSize; - MtrrV7.ExeCacheStartAddr = 0; - MtrrV7.ExeCacheSize = 0; - if (CacheInfoPtr->CarExeType == LimitedByL2Size) { - RemainingExecutionCacheSize += Result.OverlapAmount; - } - } - } - - // Set the VarMTRRs. Base first, then size/mask; this allows for expanding the region safely. - if (MtrrV6.ExeCacheSize != 0) { - MsrData = (UINT64) ( 0xFFFFFFFF00000000ULL | ((0xFFFFFFFFUL - (MtrrV6.ExeCacheSize - 1)) | 0x0800UL)); - MsrData &= CacheInfoPtr->VariableMtrrMask; - SecondMsrData = (UINT64) ( MtrrV6.ExeCacheStartAddr | (WP_IO & 0xFULL)); - } else { - MsrData = 0; - SecondMsrData = 0; - } - LibAmdMsrWrite (AMD_MTRR_VARIABLE_BASE6, &SecondMsrData, StdHeader); - LibAmdMsrWrite ((AMD_MTRR_VARIABLE_BASE6 + 1), &MsrData, StdHeader); - - if (MtrrV7.ExeCacheSize != 0) { - MsrData = (UINT64) ( 0xFFFFFFFF00000000ULL | ((0xFFFFFFFFUL - (MtrrV7.ExeCacheSize - 1)) | 0x0800UL)); - MsrData &= CacheInfoPtr->VariableMtrrMask; - SecondMsrData = (UINT64) ( MtrrV7.ExeCacheStartAddr | (WP_IO & 0xFULL)); - } else { - MsrData = 0; - SecondMsrData = 0; - } - LibAmdMsrWrite (AMD_MTRR_VARIABLE_BASE7, &SecondMsrData, StdHeader); - LibAmdMsrWrite ((AMD_MTRR_VARIABLE_BASE7 + 1), &MsrData, StdHeader); - } // endif of MTRR region check - } // end of requests For loop - - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * This function calculates available L2 cache space for ROM execution. - * - * @param[in] AmdGetExeSizeParams Pointer to the start of AmdGetExeSizeParamsPtr structure - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_ALERT No cache available for execution cache. - * - */ -AGESA_STATUS -AmdGetAvailableExeCacheSize ( - IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams - ) -{ - UINT8 WayUsedForCar; - UINT8 L2Assoc; - UINT32 L2Size; - UINT32 L2WaySize; - UINT32 CurrentCoreNum; - UINT8 L2Ways; - UINT8 Ignored; - UINT32 DieNumber; - UINT32 TotalCores; - CPUID_DATA CpuIdDataStruct; - CACHE_INFO *CacheInfoPtr; - AP_MAIL_INFO ApMailboxInfo; - AGESA_STATUS IgnoredStatus; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader); - // CAR_EXE mode is either "Limited by L2 size" or "Infinite Execution space" - ASSERT (CacheInfoPtr->CarExeType < MaxCarExeMode); - if (CacheInfoPtr->CarExeType == InfiniteExe) { - AmdGetExeSizeParams->AvailableExeCacheSize = SIZE_INFINITE_EXE_CACHE; - return AGESA_SUCCESS; - } - - // EXE cache size is limited by size of the L2, minus previous allocations for stack, heap, etc. - // Check for L2 cache size and way size - LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuIdDataStruct, &AmdGetExeSizeParams->StdHeader); - L2Assoc = (UINT8) ((CpuIdDataStruct.ECX_Reg >> 12) & 0x0F); - - // get L2Ways from L2 Association to Way translation table - L2Ways = L2AssocToL2WayTranslationTable[L2Assoc]; - ASSERT (L2Ways != 0xFF); - - // get L2Size - L2Size = 1024 * ((CpuIdDataStruct.ECX_Reg >> 16) & 0xFFFF); - - // get each L2WaySize - L2WaySize = L2Size / L2Ways; - - // Determine the size for execution cache - if (IsBsp (&AmdGetExeSizeParams->StdHeader, &IgnoredStatus)) { - // BSC (Boot Strap Core) - WayUsedForCar = Ceiling (CacheInfoPtr->BspStackSize, L2WaySize) + - Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) + - Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) + - Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize); - } else { - // AP (Application Processor) - GetCurrentCore (&CurrentCoreNum, &AmdGetExeSizeParams->StdHeader); - - GetApMailbox (&ApMailboxInfo.Info, &AmdGetExeSizeParams->StdHeader); - DieNumber = (1 << ApMailboxInfo.Fields.ModuleType); - GetActiveCoresInCurrentSocket (&TotalCores, &AmdGetExeSizeParams->StdHeader); - ASSERT ((TotalCores % DieNumber) == 0); - if ((CurrentCoreNum % (TotalCores / DieNumber)) == 0) { - WayUsedForCar = Ceiling (CacheInfoPtr->Core0StackSize , L2WaySize) + - Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) + - Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) + - Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize); - } else { - WayUsedForCar = Ceiling (CacheInfoPtr->Core1StackSize , L2WaySize) + - Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) + - Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize); - } - } - - ASSERT (WayUsedForCar < L2Ways); - - if (WayUsedForCar < L2Ways) { - AmdGetExeSizeParams->AvailableExeCacheSize = L2WaySize * (L2Ways - WayUsedForCar); - return AGESA_SUCCESS; - } else { - AmdGetExeSizeParams->AvailableExeCacheSize = 0; - return AGESA_ALERT; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * This function rounds a quotient up if the remainder is not zero. - * - * @param[in] Divisor The divisor - * @param[in] Dividend The dividend - * - * @retval Value Rounded quotient - * - */ -UINT8 -STATIC -Ceiling ( - IN UINT32 Divisor, - IN UINT32 Dividend - ) -{ - if ((Divisor % Dividend) == 0) { - return (UINT8) (Divisor / Dividend); - } else { - return (UINT8) ((Divisor / Dividend) + 1); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * This function calculates the amount of cache that has already been allocated on the - * executing core. - * - * @param[in] StdHeader Handle to config for library and services - * - * @returns Allocated size in bytes - * - */ -UINT32 -STATIC -CalculateOccupiedExeCache ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 OccupExeCacheSize; - UINT64 MsrData; - UINT8 i; - - MsrData = 0; - OccupExeCacheSize = 0; - - // - //Calculate Variable MTRR base 6~7 - // - for (i = 0; i < 2; i++) { - LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i)), &MsrData, StdHeader); - if (MsrData != 0) { - LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i + 1)), &MsrData, StdHeader); - OccupExeCacheSize = OccupExeCacheSize + ((~((MsrData & (0xFFFF8000)) - 1))&0xFFFF8000); - } - } - - // - //Calculate Fixed MTRR base D0000~F8000 - // - for (i = 0; i < 6; i++) { - LibAmdMsrRead ((AMD_MTRR_FIX4K_BASE + 2 + i), &MsrData, StdHeader); - if (MsrData!= 0) { - OccupExeCacheSize = OccupExeCacheSize + 0x8000; - } - } - - return (UINT32)OccupExeCacheSize; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * This function compares two memory regions for overlap and returns the combined - * Base,Size to describe the new combined region. - * - * There are 13 cases for how two regions may overlap: key: [] region A, ** region B - * 1- [ ] *** 9- *** [ ] disjoint regions - * 2- [ ]*** 10- ***[ ] adjacent regions - * 3- [ ***] 11- **[**] common ending - * 4- [ *]** 12- *[** ] extending - * 5- [ ** ] 13- *[*]* contained - * 6- [*** ] common start, contained - * 7- [***] identity - * 8- [**]** common start, extending - * 0- one of the regions is empty (has base=0) - * - * @param[in] ARegion pointer to the base,size pair that describes region A - * @param[in] BRegion pointer to the base,size pair that describes region B - * @param[in,out] CRegion pointer to the base,size pair that describes region C This struct also has the - * overlap type and the amount of overlap between the regions. - * @param[in] StdHeader Handle to config for library and services - * - * @returns void, nothing - */ - -VOID -STATIC -CompareRegions ( - IN EXECUTION_CACHE_REGION ARegion, - IN EXECUTION_CACHE_REGION BRegion, - IN OUT MERGED_CACHE_REGION *CRegion, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Use Int64 to handle regions ending at or above the 4G boundary. - UINT64 EndOfA; - UINT64 EndOfB; - - - if ((BRegion.ExeCacheStartAddr == 0) || - (ARegion.ExeCacheStartAddr == 0)) { - CRegion->MergedStartAddr = - CRegion->MergedSize = - CRegion->OverlapAmount = 0; - CRegion->OverlapType = EmptySet; - return; - } - if (BRegion.ExeCacheStartAddr < ARegion.ExeCacheStartAddr) { - //swap regions A & B. this collapses types 9-13 onto 1-5 and reduces the number of tests - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = ARegion.ExeCacheSize; - ARegion = BRegion; - BRegion.ExeCacheStartAddr = CRegion->MergedStartAddr; - BRegion.ExeCacheSize = CRegion->MergedSize; - } - CRegion->MergedStartAddr = - CRegion->MergedSize = - CRegion->OverlapType = - CRegion->OverlapAmount = 0; - - if (ARegion.ExeCacheStartAddr == BRegion.ExeCacheStartAddr) { - // Common start, cases 6,7, or 8 - if (ARegion.ExeCacheSize == BRegion.ExeCacheSize) { - // case 7, identity. Need to recover the overlap size - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = ARegion.ExeCacheSize; - CRegion->OverlapAmount = ARegion.ExeCacheSize; - CRegion->OverlapType = Identity; - } else if (ARegion.ExeCacheSize < BRegion.ExeCacheSize) { - // case 8, common start extending - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = BRegion.ExeCacheSize; - CRegion->OverlapType = CommonStartExtending; - CRegion->OverlapAmount = ARegion.ExeCacheSize; - } else { - // case 6, common start contained - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = ARegion.ExeCacheSize; - CRegion->OverlapType = CommonStartContained; - CRegion->OverlapAmount = BRegion.ExeCacheSize; - } - } else { - // A_Base is less than B_Base. check for cases 1-5 - EndOfA = ((UINT64) ARegion.ExeCacheStartAddr) + ((UINT64) ARegion.ExeCacheSize); - - if (EndOfA < ((UINT64) BRegion.ExeCacheStartAddr)) { - // case 1, disjoint - CRegion->MergedStartAddr = - CRegion->MergedSize = - CRegion->OverlapAmount = 0; - CRegion->OverlapType = Disjoint; - - } else if (EndOfA == ((UINT64) BRegion.ExeCacheStartAddr)) { - // case 2, adjacent - CRegion->OverlapType = Adjacent; - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = ARegion.ExeCacheSize + BRegion.ExeCacheSize; - CRegion->OverlapAmount = 0; - } else { - // EndOfA is > B_Base. check for cases 3,4,5 - EndOfB = ((UINT64) BRegion.ExeCacheStartAddr) + ((UINT64) BRegion.ExeCacheSize); - - if ( EndOfA < EndOfB) { - // case 4, extending - CRegion->OverlapType = Extending; - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = (UINT32) (EndOfB - ((UINT64) ARegion.ExeCacheStartAddr)); - CRegion->OverlapAmount = (UINT32) (EndOfA - ((UINT64) BRegion.ExeCacheStartAddr)); - } else { - // case 3, same end; or case 5, contained - CRegion->OverlapType = Contained; - CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; - CRegion->MergedSize = ARegion.ExeCacheSize; - CRegion->OverlapAmount = BRegion.ExeCacheSize; - } - } - } // endif - // Once we have combined the regions, they must still obey the MTRR size and boundary rules - if ( CRegion->OverlapType != Disjoint ) { - if ((!(IsPowerOfTwo (CRegion->MergedSize))) || - ((CRegion->MergedStartAddr % CRegion->MergedSize) != 0) ) { - CRegion->OverlapType = NotCombinable; - } - } - -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * This local function tests the parameter for being an even power of two - * - * @param[in] TestNumber Number to check - * - * @retval TRUE - TestNumber is a power of two, - * @retval FALSE - TestNumber is not a power of two - * - */ -BOOLEAN -STATIC -IsPowerOfTwo ( - IN UINT32 TestNumber - ) -{ - UINT32 PowerTwo; - - ASSERT (TestNumber >= 0x8000UL); - PowerTwo = 0x8000UL; // Start at 32K - while ( TestNumber > PowerTwo ) { - PowerTwo = PowerTwo * 2; - } - return (((TestNumber % PowerTwo) == 0) ? TRUE: FALSE); -} - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.h deleted file mode 100644 index 1d2318c770..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.h +++ /dev/null @@ -1,139 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Execution Cache Allocation functions. - * - * Contains code for doing Execution Cache Allocation for ROM space - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 50472 $ @e \$Date: 2011-04-11 01:57:56 -0600 (Mon, 11 Apr 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_CACHE_INIT_H_ -#define _CPU_CACHE_INIT_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define BSP_STACK_SIZE_64K 65536 -#define BSP_STACK_SIZE_32K 32768 - -#define CORE0_STACK_SIZE 16384 -#define CORE1_STACK_SIZE 4096 - -#define AMD_MTRR_FIX4K_BASE 0x268 -#define AMD_MTRR_VARIABLE_BASE6 0x20C -#define AMD_MTRR_VARIABLE_BASE7 0x20E - -#define WP_IO 0x0505050505050505 - -#define AGESA_CACHE_SIZE_REDUCED 1 -#define AGESA_CACHE_REGIONS_ACROSS_1MB 2 -#define AGESA_CACHE_REGIONS_ACROSS_4GB 3 -#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4 -#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5 -#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6 -#define AGESA_DEALLOCATE_CACHE_REGIONS 7 - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ -/// Cache-As-Ram Executable region allocation modes -typedef enum { - LimitedByL2Size, ///< Execution space must be allocated from L2 - InfiniteExe, ///< Family can support unlimited Execution space - MaxCarExeMode ///< Used as limit or bounds check -} CAR_EXE_MODE; - -/// Cache Information -typedef struct { - IN UINT32 BspStackSize; ///< Stack size of BSP - IN UINT32 Core0StackSize; ///< Stack size of primary cores - IN UINT32 Core1StackSize; ///< Stack size of all non primary cores - IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size - IN UINT32 SharedMemSize; ///< Shared memory size - IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes - IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init. - IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings - IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space -} CACHE_INFO; - -/// Merged memory region overlap type -typedef enum { - EmptySet, ///< One of the regions is zero length - Disjoint, ///< The two regions do not touch - Adjacent, ///< one region is next to the other, no gap - CommonEnd, ///< regions overlap with a common end point - Extending, ///< the 2nd region is extending the size of the 1st - Contained, ///< the 2nd region is wholely contained inside the 1st - CommonStartContained, ///< the 2nd region is contained in the 1st with a common start - Identity, ///< the two regions are the same - CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size - NotCombinable ///< the combined regions do not follow the cache block rules -} OVERLAP_TYPE; - -/// Result of merging two memory regions for cache coverage -typedef struct { - IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions - IN OUT UINT32 MergedSize; ///< Size of the merged regions - OUT UINT32 OverlapAmount; ///< the size of the overlapping section - OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap -} MERGED_CACHE_REGION; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -AllocateExecutionCache ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ); - -#endif // _CPU_CACHE_INIT_H_ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c deleted file mode 100644 index ddfeb68fed..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c +++ /dev/null @@ -1,363 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Core Leveling Function. - * - * Contains code to Level the number of core in a multi-socket system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - *---------------------------------------------------------------------------- - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "AMD.h" -#include "Topology.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuEarlyInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE CoreLevelingFamilyServiceTable; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -CoreLevelingAtEarly ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Should core leveling be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE core leveling is supported. - * @retval FALSE core leveling cannot be enabled. - * - */ -BOOLEAN -STATIC -IsCoreLevelingEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CORE_LEVELING_TYPE CoreLevelMode; - - CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode; - if (CoreLevelMode != CORE_LEVEL_NONE) { - return (TRUE); - } else { - return (FALSE); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs core leveling for the system. - * - * This function implements the AMD_CPU_EARLY_PARAMS.CoreLevelingMode parameter. - * The possible modes are: - * -0 CORE_LEVEL_LOWEST Level to lowest common denominator - * -1 CORE_LEVEL_TWO Level to 2 cores - * -2 CORE_LEVEL_POWER_OF_TWO Level to 1,2,4 or 8 - * -3 CORE_LEVEL_NONE Do no leveling - * -4 CORE_LEVEL_COMPUTE_UNIT Level cores to one core per compute unit - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the leveling mode parameter - * @param[in] StdHeader Config handle for library and services - * - * @return The most severe status of any family specific service. - * - */ -AGESA_STATUS -CoreLevelingAtEarly ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CoreNumPerComputeUnit; - UINT32 MinNumOfComputeUnit; - UINT32 EnabledComputeUnit; - UINT32 Socket; - UINT32 Module; - UINT32 NumberOfSockets; - UINT32 NumberOfModules; - UINT32 MinCoreCountOnNode; - UINT32 MaxCoreCountOnNode; - UINT32 LowCore; - UINT32 HighCore; - UINT32 LeveledCores; - UINT32 RequestedCores; - UINT32 TotalEnabledCoresOnNode; - BOOLEAN RegUpdated; - AP_MAIL_INFO ApMailboxInfo; - CORE_LEVELING_TYPE CoreLevelMode; - CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices; - WARM_RESET_REQUEST Request; - - IDS_HDT_CONSOLE (CPU_TRACE, "CoreLevelingAtEarly\n CoreLevelMode: %d\n", PlatformConfig->CoreLevelingMode); - - MaxCoreCountOnNode = 0; - MinCoreCountOnNode = 0xFFFFFFFF; - LeveledCores = 0; - CoreNumPerComputeUnit = 1; - MinNumOfComputeUnit = 0xFF; - - ASSERT (PlatformConfig->CoreLevelingMode < CoreLevelModeMax); - - // Get OEM IO core level mode - CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode; - - // Get socket count - NumberOfSockets = GetPlatformNumberOfSockets (); - GetApMailbox (&ApMailboxInfo.Info, StdHeader); - NumberOfModules = ApMailboxInfo.Fields.ModuleType + 1; - - // Collect cpu core info - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - for (Module = 0; Module < NumberOfModules; Module++) { - if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) { - // Get the highest and lowest core count in all nodes - TotalEnabledCoresOnNode = HighCore - LowCore + 1; - if (TotalEnabledCoresOnNode < MinCoreCountOnNode) { - MinCoreCountOnNode = TotalEnabledCoresOnNode; - } - if (TotalEnabledCoresOnNode > MaxCoreCountOnNode) { - MaxCoreCountOnNode = TotalEnabledCoresOnNode; - } - EnabledComputeUnit = TotalEnabledCoresOnNode; - switch (GetComputeUnitMapping (StdHeader)) { - case AllCoresMapping: - // All cores are in their own compute unit. - break; - case EvenCoresMapping: - // Cores are paired in compute units. - CoreNumPerComputeUnit = 2; - EnabledComputeUnit = (TotalEnabledCoresOnNode / 2); - break; - default: - ASSERT (FALSE); - } - // Get minimum of compute unit. This will either be the minimum number of cores (AllCoresMapping), - // or less (EvenCoresMapping). - if (EnabledComputeUnit < MinNumOfComputeUnit) { - MinNumOfComputeUnit = EnabledComputeUnit; - } - IDS_HDT_CONSOLE (CPU_TRACE, " Socket %d Module %d MaxCoreCountOnNode %d MinCoreCountOnNode %d TotalEnabledCoresOnNode %d EnabledComputeUnit %d MinNumOfComputeUnit %d\n", \ - Socket, Module, MaxCoreCountOnNode, MinCoreCountOnNode, TotalEnabledCoresOnNode, EnabledComputeUnit, MinNumOfComputeUnit); - } - } - } - } - - // Get LeveledCores - switch (CoreLevelMode) { - case CORE_LEVEL_LOWEST: - if (MinCoreCountOnNode == MaxCoreCountOnNode) { - return (AGESA_SUCCESS); - } - LeveledCores = (MinCoreCountOnNode / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; - break; - case CORE_LEVEL_TWO: - LeveledCores = 2 / NumberOfModules; - if (LeveledCores != 0) { - LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode; - } else { - return (AGESA_WARNING); - } - if ((LeveledCores * NumberOfModules) != 2) { - PutEventLog ( - AGESA_WARNING, - CPU_WARNING_ADJUSTED_LEVELING_MODE, - 2, (LeveledCores * NumberOfModules), 0, 0, StdHeader - ); - } - break; - case CORE_LEVEL_POWER_OF_TWO: - // Level to power of 2 (1, 2, 4, 8...) - LeveledCores = 1; - while (MinCoreCountOnNode >= (LeveledCores * 2)) { - LeveledCores = LeveledCores * 2; - } - break; - case CORE_LEVEL_COMPUTE_UNIT: - // Level cores to one core per compute unit, with additional reduction to level - // all processors to match the processor with the minimum number of cores. - if (CoreNumPerComputeUnit == 1) { - // If there is one core per compute unit, this is the same as CORE_LEVEL_LOWEST. - if (MinCoreCountOnNode == MaxCoreCountOnNode) { - return (AGESA_SUCCESS); - } - LeveledCores = MinCoreCountOnNode; - } else { - // If there are more than one core per compute unit, level to the number of compute units. - LeveledCores = MinNumOfComputeUnit; - } - break; - case CORE_LEVEL_ONE: - LeveledCores = 1; - if (NumberOfModules > 1) { - PutEventLog ( - AGESA_WARNING, - CPU_WARNING_ADJUSTED_LEVELING_MODE, - 1, NumberOfModules, 0, 0, StdHeader - ); - } - break; - case CORE_LEVEL_THREE: - case CORE_LEVEL_FOUR: - case CORE_LEVEL_FIVE: - case CORE_LEVEL_SIX: - case CORE_LEVEL_SEVEN: - case CORE_LEVEL_EIGHT: - case CORE_LEVEL_NINE: - case CORE_LEVEL_TEN: - case CORE_LEVEL_ELEVEN: - case CORE_LEVEL_TWELVE: - case CORE_LEVEL_THIRTEEN: - case CORE_LEVEL_FOURTEEN: - case CORE_LEVEL_FIFTEEN: - // MCM processors can not have an odd number of cores. For an odd CORE_LEVEL_N, MCM processors will be - // leveled as though CORE_LEVEL_N+1 was chosen. - // Processors with compute units disable all cores in an entire compute unit at a time, or on an MCM processor, - // two compute units at a time. For example, on an SCM processor with two cores per compute unit, the effective - // explicit levels are CORE_LEVEL_ONE, CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_SIX, and - // CORE_LEVEL_EIGHT. The same example for an MCM processor with two cores per compute unit has effective - // explicit levels of CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_EIGHT, and CORE_LEVEL_TWELVE. - RequestedCores = CoreLevelMode - CORE_LEVEL_THREE + 3; - LeveledCores = (RequestedCores + NumberOfModules - 1) / NumberOfModules; - LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; - LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode; - if (LeveledCores != 1) { - LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; - } - if ((LeveledCores * NumberOfModules * CoreNumPerComputeUnit) != RequestedCores) { - PutEventLog ( - AGESA_WARNING, - CPU_WARNING_ADJUSTED_LEVELING_MODE, - RequestedCores, (LeveledCores * NumberOfModules * CoreNumPerComputeUnit), 0, 0, StdHeader - ); - } - break; - default: - ASSERT (FALSE); - } - - // Set down core register - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader); - if (FamilySpecificServices != NULL) { - for (Module = 0; Module < NumberOfModules; Module++) { - IDS_HDT_CONSOLE (CPU_TRACE, " SetDownCoreRegister: Socket %d Module %d LeveledCores %d CoreLevelMode %d\n", Socket, Module, LeveledCores, CoreLevelMode); - RegUpdated = FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &Socket, &Module, &LeveledCores, CoreLevelMode, StdHeader); - // If the down core register is updated, trigger a warm reset. - if (RegUpdated) { - GetWarmResetFlag (StdHeader, &Request); - Request.RequestBit = TRUE; - Request.StateBits = Request.PostStage - 1; - IDS_HDT_CONSOLE (CPU_TRACE, " Request a warm reset.\n"); - SetWarmResetFlag (StdHeader, &Request); - } - } - } - } - } - - return (AGESA_SUCCESS); -} - - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling = -{ - CoreLeveling, - (CPU_FEAT_AFTER_PM_INIT), - IsCoreLevelingEnabled, - CoreLevelingAtEarly -}; - -/*---------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.c deleted file mode 100644 index 1aa82e6c66..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.c +++ /dev/null @@ -1,176 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Core performance boost feature support code. - * - * Contains code that declares the AGESA CPU CPB related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuCpb.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUCPB_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE CpbFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should CPB be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE CPB is supported. - * @retval FALSE CPB cannot be enabled. - * - */ -BOOLEAN -STATIC -IsCpbFeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - BOOLEAN IsEnabled; - CPB_FAMILY_SERVICES *FamilyServices; - - IsEnabled = FALSE; - - ASSERT (PlatformConfig->CpbMode < MaxCpbMode); - - if (PlatformConfig->CpbMode == CpbModeAuto) { - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { - IsEnabled = TRUE; - break; - } - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable core performance boost - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeCpbFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - AGESA_STATUS AgesaStatus; - AGESA_STATUS CalledStatus; - CPB_FAMILY_SERVICES *FamilyServices; - - AgesaStatus = AGESA_SUCCESS; - CalledStatus = AGESA_SUCCESS; - - IDS_HDT_CONSOLE (CPU_TRACE, " Boost is enabled\n"); - - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { - CalledStatus = FamilyServices->EnableCpbOnSocket (FamilyServices, PlatformConfig, EntryPoint, Socket, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - } - } - } - } - - return AgesaStatus; -} - - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb = -{ - CoreBoost, - (CPU_FEAT_BEFORE_PM_INIT | CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_INIT_LATE_END | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_S3_LATE_RESTORE_END | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsCpbFeatureEnabled, - InitializeCpbFeature -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.h deleted file mode 100644 index 9660c400c4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCpb.h +++ /dev/null @@ -1,132 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Core Performance Boost Functions declarations. - * - * Contains code that declares the AGESA CPU CPB related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_CPB_H_ -#define _CPU_CPB_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (CPB_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if CPB is supported. - * - * @param[in] CpbServices Core Performance Boost services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] Socket Zero-based socket number. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE CPB is supported. - * @retval FALSE CPB is not supported. - * - */ -typedef BOOLEAN F_CPB_IS_SUPPORTED ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPB_IS_SUPPORTED *PF_CPB_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable CPB. - * - * @param[in] CpbServices Core Performance Boost services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] EntryPoint Timepoint designator. - * @param[in] Socket Zero-based socket number. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_CPB_INIT ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT64 EntryPoint, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPB_INIT *PF_CPB_INIT; - -/** - * Provide the interface to the CPB Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _CPB_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_CPB_IS_SUPPORTED IsCpbSupported; ///< Method: Family specific call to check if CPB is supported. - PF_CPB_INIT EnableCpbOnSocket; ///< Method: Family specific call to enable CPB. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_CPB_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c deleted file mode 100644 index 2385752e88..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c +++ /dev/null @@ -1,862 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD DMI Record Creation API, and related functions. - * - * Contains code that produce the DMI related information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 60539 $ @e \$Date: 2011-10-17 17:11:05 -0600 (Mon, 17 Oct 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionDmi.h" -#include "cpuLateInit.h" -#include "cpuServices.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "heapManager.h" -#include "Ids.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FEATURE_CPUDMI_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_DMI_CONFIGURATION OptionDmiConfiguration; // global user config record - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT16 -STATIC -AdjustGranularity ( - IN UINT32 *CacheSizePtr - ); - -VOID -STATIC -IntToString ( - IN OUT CHAR8 *String, - IN UINT8 *Integer, - IN UINT8 SizeInByte -); - -AGESA_STATUS -GetDmiInfoStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ); - -AGESA_STATUS -GetDmiInfoMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ); - -AGESA_STATUS -ReleaseDmiBufferStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -ReleaseDmiBuffer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * CreateDmiRecords - * - * Description: - * This function creates DMI/SMBios records pertinent to the processor - * SMBIOS type 4, type 7, and type 40. - * - * Parameters: - * @param[in, out] *StdHeader - * @param[in, out] **DmiTable - * - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -CreateDmiRecords ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ) -{ - AGESA_TESTPOINT (TpProcCpuEntryDmi, StdHeader); - return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * GetDmiInfoStub - * - * Description: - * This is the default routine for use when the DMI option is NOT requested. - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * Parameters: - * @param[in, out] *StdHeader - * @param[in, out] **DmiTable - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -GetDmiInfoStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ) -{ - return AGESA_UNSUPPORTED; -} - -/* -----------------------------------------------------------------------------*/ -/** - * GetDmiInfoMain - * - * Description: - * This is the common routine for getting Dmi type4 and type7 CPU related information. - * - * Parameters: - * @param[in, out] *StdHeader - * @param[in, out] **DmiTable - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -GetDmiInfoMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ) -{ - UINT8 Socket; - UINT8 Channel; - UINT8 Dimm; - UINT16 Index; - UINT16 DimmIndex; - UINT16 NumberOfDimm; - UINT32 MaxCapacity; - UINT64 MsrData; - UINT64 LocalMsrRegister; - BOOLEAN FamilyNotFound; - AGESA_STATUS Flag; - AGESA_STATUS CalledStatus; - AP_EXE_PARAMS ApParams; - MEM_DMI_INFO *MemInfo; - DMI_T17_MEMORY_TYPE MemType; - DMI_INFO *DmiBufferPtr; - ALLOCATE_HEAP_PARAMS AllocateHeapParams; - LOCATE_HEAP_PTR LocateHeapParams; - CPU_LOGICAL_ID LogicalId; - PROC_FAMILY_TABLE *ProcData; - CPU_GET_MEM_INFO CpuGetMemInfo; - - MsrData = 0; - Flag = AGESA_SUCCESS; - ProcData = NULL; - MemInfo = NULL; - DmiBufferPtr = *DmiTable; - FamilyNotFound = TRUE; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) { - ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]); - if ((ProcData->ProcessorFamily & LogicalId.Family) != 0) { - FamilyNotFound = FALSE; - break; - } - } - - if (FamilyNotFound) { - return AGESA_ERROR; - } - - if (DmiBufferPtr == NULL) { - // - // Allocate a buffer by heap function - // - AllocateHeapParams.BufferHandle = AMD_DMI_INFO_BUFFER_HANDLE; - AllocateHeapParams.RequestedBufferSize = sizeof (DMI_INFO); - AllocateHeapParams.Persist = HEAP_SYSTEM_MEM; - - if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - - DmiBufferPtr = (DMI_INFO *) AllocateHeapParams.BufferPtr; - *DmiTable = DmiBufferPtr; - } - - IDS_HDT_CONSOLE (CPU_TRACE, " DMI is enabled\n"); - - // Fill with 0x00 - LibAmdMemFill (DmiBufferPtr, 0x00, sizeof (DMI_INFO), StdHeader); - - // - // Get CPU information - // - - // Run GetType4Type7Info on all core0s. - ApParams.StdHeader = *StdHeader; - ApParams.FunctionNumber = AP_LATE_TASK_GET_TYPE4_TYPE7; - ApParams.RelatedDataBlock = (VOID *) DmiBufferPtr; - ApParams.RelatedBlockLength = sizeof (DMI_INFO); - CalledStatus = RunLateApTaskOnAllCore0s (&ApParams, StdHeader); - if (CalledStatus > Flag) { - Flag = CalledStatus; - } - CalledStatus = GetType4Type7Info (&ApParams); - if (CalledStatus > Flag) { - Flag = CalledStatus; - } - - //------------------------------ - // T Y P E 16 17 19 20 - //------------------------------ - - LocateHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE; - if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) { - if (Flag < AGESA_ERROR) { - Flag = AGESA_ERROR; - } - } else { - NumberOfDimm = *((UINT16 *) (LocateHeapParams.BufferPtr)); - MemType = *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 6)); - MemInfo = (MEM_DMI_INFO *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 6 + sizeof (DMI_T17_MEMORY_TYPE)); - // TYPE 16 - DmiBufferPtr->T16.Location = 0x03; - DmiBufferPtr->T16.Use = 0x03; - - // Gather memory information - ProcData->DmiGetMemInfo (&CpuGetMemInfo, StdHeader); - - if (CpuGetMemInfo.EccCapable) { - DmiBufferPtr->T16.MemoryErrorCorrection = Dmi16MultiBitEcc; - } else { - DmiBufferPtr->T16.MemoryErrorCorrection = Dmi16NoneErrCorrection; - } - - MaxCapacity = *((UINT32 *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 2)); - // For the total size >= 2TB case, we need leave MaximumCapacity (offset 07h) to 80000000h - // and fill the size in bytes into ExtMaxCapacity (offset 0Fh). - if (MaxCapacity < 0x200000) { - DmiBufferPtr->T16.MaximumCapacity = MaxCapacity << 10; - DmiBufferPtr->T16.ExtMaxCapacity = 0; - } else { - DmiBufferPtr->T16.MaximumCapacity = 0x80000000; - DmiBufferPtr->T16.ExtMaxCapacity = (UINT64) MaxCapacity << 20; - } - - DmiBufferPtr->T16.NumberOfMemoryDevices = NumberOfDimm; - - // TYPE 17 - for (DimmIndex = 0; DimmIndex < NumberOfDimm; DimmIndex++) { - Socket = (MemInfo + DimmIndex)->Socket; - Channel = (MemInfo + DimmIndex)->Channel; - Dimm = (MemInfo + DimmIndex)->Dimm; - - DmiBufferPtr->T17[Socket][Channel][Dimm].TotalWidth = (MemInfo + DimmIndex)->TotalWidth; - DmiBufferPtr->T17[Socket][Channel][Dimm].DataWidth = (MemInfo + DimmIndex)->DataWidth; - DmiBufferPtr->T17[Socket][Channel][Dimm].MemorySize = (MemInfo + DimmIndex)->MemorySize; - DmiBufferPtr->T17[Socket][Channel][Dimm].FormFactor = (MemInfo + DimmIndex)->FormFactor; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceSet = 0; - - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[0] = 'D'; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[1] = 'I'; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[2] = 'M'; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[3] = 'M'; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[4] = ' '; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[5] = Dimm + 0x30; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[6] = '\0'; - DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[7] = '\0'; - - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[0] = 'C'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[1] = 'H'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[2] = 'A'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[3] = 'N'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[4] = 'N'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[5] = 'E'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[6] = 'L'; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[7] = ' '; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[8] = Channel + 0x41; - DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[9] = '\0'; - - DmiBufferPtr->T17[Socket][Channel][Dimm].MemoryType = MemType; - DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Synchronous = 1; - DmiBufferPtr->T17[Socket][Channel][Dimm].Speed = (MemInfo + DimmIndex)->Speed; - - DmiBufferPtr->T17[Socket][Channel][Dimm].ManufacturerIdCode = (MemInfo + DimmIndex)->ManufacturerIdCode; - - IntToString (DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber, (MemInfo + DimmIndex)->SerialNumber, (sizeof DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber - 1) / 2); - - LibAmdMemCopy (&DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber, &(MemInfo + DimmIndex)->PartNumber, sizeof (DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber), StdHeader); - DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber[18] = 0; - - DmiBufferPtr->T17[Socket][Channel][Dimm].Attributes = (MemInfo + DimmIndex)->Attributes; - DmiBufferPtr->T17[Socket][Channel][Dimm].ExtSize = (MemInfo + DimmIndex)->ExtSize; - DmiBufferPtr->T17[Socket][Channel][Dimm].ConfigSpeed = (MemInfo + DimmIndex)->ConfigSpeed; - - //TYPE 20 - DmiBufferPtr->T20[Socket][Channel][Dimm].StartingAddr = (MemInfo + DimmIndex)->StartingAddr; - DmiBufferPtr->T20[Socket][Channel][Dimm].EndingAddr = (MemInfo + DimmIndex)->EndingAddr; - // Partition Row Position - 2 for single channel memory - // 0 for dual channel memory - DmiBufferPtr->T20[Socket][Channel][Dimm].PartitionRowPosition = CpuGetMemInfo.PartitionRowPosition; - DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavePosition = 0xFF; - DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavedDataDepth = 0xFF; - DmiBufferPtr->T20[Socket][Channel][Dimm].ExtStartingAddr = (MemInfo + DimmIndex)->ExtStartingAddr; - DmiBufferPtr->T20[Socket][Channel][Dimm].ExtEndingAddr = (MemInfo + DimmIndex)->ExtEndingAddr; - } - - // TYPE 19 - DmiBufferPtr->T19.StartingAddr = 0; - DmiBufferPtr->T19.ExtStartingAddr = 0; - DmiBufferPtr->T19.ExtEndingAddr = 0; - - // If Ending Address >= 0xFFFFFFFF, update Starting Address (offset 04h) & Ending Address (offset 08h) to 0xFFFFFFFF, - // and use the Extended Starting Address (offset 0Fh) & Extended Ending Address (offset 17h) instead. - LibAmdMsrRead (TOP_MEM2, &LocalMsrRegister, StdHeader); - if (LocalMsrRegister == 0) { - LibAmdMsrRead (TOP_MEM, &LocalMsrRegister, StdHeader); - DmiBufferPtr->T19.EndingAddr = (UINT32) (LocalMsrRegister >> 10); - } else { - if ((LocalMsrRegister >> 10) >= (UINT64) 0xFFFFFFFF) { - DmiBufferPtr->T19.StartingAddr = 0xFFFFFFFF; - DmiBufferPtr->T19.EndingAddr = 0xFFFFFFFF; - DmiBufferPtr->T19.ExtEndingAddr = LocalMsrRegister; - } else { - DmiBufferPtr->T19.EndingAddr = (UINT32) (LocalMsrRegister >> 10); - } - } - - DmiBufferPtr->T19.PartitionWidth = 0xFF; - } - return (Flag); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * GetType4Type7Info - * - * Description: - * This routine should be run on core 0 of every socket. It creates DMI type 4 and type 7 tables. - * - * Parameters: - * @param[in] ApExeParams Handle to config for library and services. - * - * @retval AGESA_STATUS - * - * Processing: - * - */ -AGESA_STATUS -GetType4Type7Info ( - IN AP_EXE_PARAMS *ApExeParams - ) -{ - UINT8 ByteIndexInUint64; - UINT16 Index; - UINT32 SocketNum; - UINT32 CacheSize; - UINT32 IgnoredModule; - UINT32 IgnoredCore; - UINT64 MsrData; - DMI_INFO *DmiBufferPtr; - AGESA_STATUS IgnoredSts; - AGESA_STATUS Flag; - BOOLEAN FamilyNotFound; - CPUID_DATA CpuId; - CPU_TYPE_INFO CpuInfo; - PROC_FAMILY_TABLE *ProcData; - CPU_LOGICAL_ID LogicalID; - UINT8 L3Associativity; - - Flag = AGESA_SUCCESS; - DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; - GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); - - ProcData = NULL; - FamilyNotFound = TRUE; - for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) { - ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]); - if ((ProcData->ProcessorFamily & LogicalID.Family) != 0) { - FamilyNotFound = FALSE; - break; - } - } - - if (FamilyNotFound) { - return AGESA_ERROR; - } - - ProcData->DmiGetCpuInfo (&CpuInfo, &ApExeParams->StdHeader); - - // ------------------------------ - // T Y P E 4 - // ------------------------------ - - IdentifyCore (&ApExeParams->StdHeader, &SocketNum, &IgnoredModule, &IgnoredCore, &IgnoredSts); - - // Type 4 Offset 0x05, Processor Type - DmiBufferPtr->T4[SocketNum].T4ProcType = CENTRAL_PROCESSOR; - - // Type 4 Offset 0x06, Processor Family - ProcData->DmiGetT4ProcFamily (&DmiBufferPtr->T4[SocketNum].T4ProcFamily, ProcData, &CpuInfo, &ApExeParams->StdHeader); - - if (DmiBufferPtr->T4[SocketNum].T4ProcFamily == P_UPGRADE_UNKNOWN) { - Flag = AGESA_ERROR; - } - - // Type4 Offset 0x08, Processor ID - LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, &ApExeParams->StdHeader); - DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdLsd = CpuId.EAX_Reg; - DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdMsd = CpuId.EDX_Reg; - - // Type4 Offset 0x11, Voltage - DmiBufferPtr->T4[SocketNum].T4Voltage = ProcData->DmiGetVoltage (&ApExeParams->StdHeader); - - // Type4 Offset 0x12, External Clock - DmiBufferPtr->T4[SocketNum].T4ExternalClock = ProcData->DmiGetExtClock (&ApExeParams->StdHeader); - - // Type4 Offset 0x14, Max Speed - DmiBufferPtr->T4[SocketNum].T4MaxSpeed = ProcData->DmiGetMaxSpeed (&ApExeParams->StdHeader); - - // Type4 Offset 0x16, Current Speed - DmiBufferPtr->T4[SocketNum].T4CurrentSpeed = DmiBufferPtr->T4[SocketNum].T4MaxSpeed; - - // Type4 Offset 0x18, Status - DmiBufferPtr->T4[SocketNum].T4Status = SOCKET_POPULATED | CPU_STATUS_ENABLED; - - // Type4 Offset 0x19, Processor Upgrade - DmiBufferPtr->T4[SocketNum].T4ProcUpgrade = CpuInfo.ProcUpgrade; - - // Type4 Offset 0x23, 0x24 and 0x25, Core Count, Core Enabled and Thread Count - DmiBufferPtr->T4[SocketNum].T4CoreCount = CpuInfo.TotalCoreNumber + 1; - DmiBufferPtr->T4[SocketNum].T4CoreEnabled = CpuInfo.EnabledCoreNumber + 1; - DmiBufferPtr->T4[SocketNum].T4ThreadCount = CpuInfo.EnabledCoreNumber + 1; - - // Type4 Offset 0x26, Processor Characteristics - DmiBufferPtr->T4[SocketNum].T4ProcCharacteristics = P_CHARACTERISTICS; - - // Type4 Offset 0x28, Processor Family 2 - DmiBufferPtr->T4[SocketNum].T4ProcFamily2 = DmiBufferPtr->T4[SocketNum].T4ProcFamily; - - // Type4 ProcVersion - for (Index = 0; Index <= 5; Index++) { - LibAmdMsrRead ((MSR_CPUID_NAME_STRING0 + Index), &MsrData, &ApExeParams->StdHeader); - for (ByteIndexInUint64 = 0; ByteIndexInUint64 <= 7; ByteIndexInUint64++) { - DmiBufferPtr->T4[SocketNum].T4ProcVersion[Index * 8 + ByteIndexInUint64] = (UINT8) (MsrData >> (8 * ByteIndexInUint64)); - } - } - - //------------------------------ - // T Y P E 7 - //------------------------------ - - // Type7 Offset 0x05, Cache Configuration - DmiBufferPtr->T7L1[SocketNum].T7CacheCfg = CACHE_CFG_L1; - DmiBufferPtr->T7L2[SocketNum].T7CacheCfg = CACHE_CFG_L2; - DmiBufferPtr->T7L3[SocketNum].T7CacheCfg = CACHE_CFG_L3; - - // Type7 Offset 0x07 and 09, Maximum Cache Size and Installed Size - - // Maximum L1 cache size - DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize = AdjustGranularity (&CpuInfo.L1CacheSize); - - // Installed L1 cache size - DmiBufferPtr->T7L1[SocketNum].T7InstallSize = DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize; - - // Maximum L2 cache size - DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize = AdjustGranularity (&CpuInfo.L2CacheSize); - - // Installed L2 cache size - DmiBufferPtr->T7L2[SocketNum].T7InstallSize = DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize; - - // Maximum L3 cache size - LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, &ApExeParams->StdHeader); - CacheSize = ((CpuId.EDX_Reg >> 18) & 0x3FFF) * 512; - DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize); - - // Installed L3 cache size - DmiBufferPtr->T7L3[SocketNum].T7InstallSize = DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize; - - // Type7 Offset 0x0B and 0D, Supported SRAM Type and Current SRAM Type - DmiBufferPtr->T7L1[SocketNum].T7SupportedSramType = SRAM_TYPE; - DmiBufferPtr->T7L1[SocketNum].T7CurrentSramType = SRAM_TYPE; - DmiBufferPtr->T7L2[SocketNum].T7SupportedSramType = SRAM_TYPE; - DmiBufferPtr->T7L2[SocketNum].T7CurrentSramType = SRAM_TYPE; - DmiBufferPtr->T7L3[SocketNum].T7SupportedSramType = SRAM_TYPE; - DmiBufferPtr->T7L3[SocketNum].T7CurrentSramType = SRAM_TYPE; - - // Type7 Offset 0x0F, Cache Speed - DmiBufferPtr->T7L1[SocketNum].T7CacheSpeed = 1; - DmiBufferPtr->T7L2[SocketNum].T7CacheSpeed = 1; - DmiBufferPtr->T7L3[SocketNum].T7CacheSpeed = 1; - - // Type7 Offset 0x10, Error Correction Type - DmiBufferPtr->T7L1[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE; - DmiBufferPtr->T7L2[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE; - DmiBufferPtr->T7L3[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE; - - // Type7 Offset 0x11, System Cache Type - DmiBufferPtr->T7L1[SocketNum].T7SystemCacheType = CACHE_TYPE; - DmiBufferPtr->T7L2[SocketNum].T7SystemCacheType = CACHE_TYPE; - DmiBufferPtr->T7L3[SocketNum].T7SystemCacheType = CACHE_TYPE; - - // Type7 Offset 0x12, Associativity - DmiBufferPtr->T7L1[SocketNum].T7Associativity = ASSOCIATIVE_2_WAY; - DmiBufferPtr->T7L2[SocketNum].T7Associativity = ASSOCIATIVE_16_WAY; - - L3Associativity = (UINT8) ((CpuId.EDX_Reg >> 12) & 0x0F); - - switch (L3Associativity) - { - case (CPUID_ASSOCIATIVITY_2_WAY): - DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_2_WAY; - break; - case (CPUID_ASSOCIATIVITY_4_WAY): - DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_4_WAY; - break; - case (CPUID_ASSOCIATIVITY_8_WAY): - DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_8_WAY; - break; - case (CPUID_ASSOCIATIVITY_16_WAY): - DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_16_WAY; - break; - case (CPUID_ASSOCIATIVITY_32_WAY): - DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_32_WAY; - break; - case (CPUID_ASSOCIATIVITY_48_WAY): - DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_48_WAY; - break; - case (CPUID_ASSOCIATIVITY_64_WAY): - DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_64_WAY; - break; - case (CPUID_ASSOCIATIVITY_96_WAY): - case (CPUID_ASSOCIATIVITY_128_WAY): - default: - DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_OTHER; - break; - } - - return (Flag); -} - -/* -----------------------------------------------------------------------------*/ -/** - * DmiGetT4ProcFamilyFromBrandId - * - * Description: - * This is the common routine for getting Type 4 processor family information from brand ID - * - * Parameters: - * @param[in, out] *T4ProcFamily Pointer to type 4 processor family information - * @param[in] *CpuDmiProcFamilyTable Pointer to DMI family special service - * @param[in] *CpuInfo Pointer to CPU_TYPE_INFO struct - * @param[in, out] *StdHeader Standard Head Pointer - * - * @retval AGESA_STATUS - * - */ -VOID -DmiGetT4ProcFamilyFromBrandId ( - IN OUT UINT8 *T4ProcFamily, - IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, - IN CPU_TYPE_INFO *CpuInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 Index; - *T4ProcFamily = P_UPGRADE_UNKNOWN; - if (CpuInfo->BrandId.Model != P_ENGINEERING_SAMPLE) { - for (Index = 0; Index < CpuDmiProcFamilyTable->LenBrandList; Index++) { - if ((CpuDmiProcFamilyTable->DmiBrandList[Index].PackageType == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].PackageType == CpuInfo->PackageType) && - (CpuDmiProcFamilyTable->DmiBrandList[Index].PgOfBrandId == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].PgOfBrandId == CpuInfo->BrandId.Pg) && - (CpuDmiProcFamilyTable->DmiBrandList[Index].NumberOfCores == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].NumberOfCores == CpuInfo->TotalCoreNumber) && - (CpuDmiProcFamilyTable->DmiBrandList[Index].String1ofBrandId == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].String1ofBrandId == CpuInfo->BrandId.String1)) { - *T4ProcFamily = CpuDmiProcFamilyTable->DmiBrandList[Index].ValueSetToDmiTable; - break; - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * GetNameString - * - * Description: - * Get name string from MSR_C001_00[35:30] - * - * Parameters: - * @param[in, out] *String Pointer to name string - * @param[in, out] *StdHeader - * - */ -VOID -GetNameString ( - IN OUT CHAR8 *String, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 StringIndex; - UINT8 MsrIndex; - UINT64 MsrData; - - StringIndex = 0; - for (MsrIndex = 0; MsrIndex <= 5; MsrIndex++) { - LibAmdMsrRead ((MSR_CPUID_NAME_STRING0 + MsrIndex), &MsrData, StdHeader); - for (i = 0; i < 8; i++) { - String[StringIndex] = (CHAR8) (MsrData >> (8 * i)); - StringIndex++; - } - } - String[StringIndex] = '\0'; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * IsSourceStrContainTargetStr - * - * Description: - * check if source string contains target string. - * - * Parameters: - * @param[in, out] *SourceStr Pointer to source CHAR array - * @param[in, out] *TargetStr Pointer to target CHAR array - * @param[in, out] *StdHeader - * - * @retval TRUE Target string is contained in the source string - * @retval FALSE Target string is not contained in the source string - */ -BOOLEAN -IsSourceStrContainTargetStr ( - IN OUT CHAR8 *SourceStr, - IN OUT CONST CHAR8 *TargetStr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsContained; - UINT32 SourceStrIndex; - UINT32 TargetStrIndex; - CHAR8 TargetChar; - - IsContained = FALSE; - if ((TargetStr != NULL) && (SourceStr != NULL)) { - for (SourceStrIndex = 0; SourceStr[SourceStrIndex] != '\0'; SourceStrIndex++) { - // Compare TrgString with SrcString from frist charactor to the '\0' - for (TargetStrIndex = 0; TargetStr[TargetStrIndex] != '\0'; TargetStrIndex++) { - if (TargetStr[TargetStrIndex] != SourceStr[SourceStrIndex + TargetStrIndex]) { - // if it's not match, try to check the upcase/lowcase - TargetChar = 0; - if (TargetStr[TargetStrIndex] >= 'a' && TargetStr[TargetStrIndex] <= 'z') { - TargetChar = TargetStr[TargetStrIndex] - ('a' - 'A'); - } else if (TargetStr[TargetStrIndex] >= 'A' && TargetStr[TargetStrIndex] <= 'Z') { - TargetChar = TargetStr[TargetStrIndex] + ('a' - 'A'); - } - // compare again - if (TargetChar != SourceStr[SourceStrIndex + TargetStrIndex]) { - break; - } - } - } - - if ((TargetStr[TargetStrIndex] == '\0') && (TargetStrIndex != 0)) { - IsContained = TRUE; - break; - } - } - } - return IsContained; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * AdjustGranularity - * - * Description: - * If cache size is greater than or equal to 32M, then set granularity - * to 64K. otherwise, set granularity to 1K - * - * Parameters: - * @param[in] *CacheSizePtr - * - * @retval CacheSize - * - * Processing: - * - */ -UINT16 -STATIC -AdjustGranularity ( - IN UINT32 *CacheSizePtr - ) -{ - UINT16 CacheSize; - - if (*CacheSizePtr >= 0x8000) { - CacheSize = (UINT16) (*CacheSizePtr / 64); - CacheSize |= 0x8000; - } else { - CacheSize = (UINT16) *CacheSizePtr; - } - - return (CacheSize); -} - -/* -----------------------------------------------------------------------------*/ -/** - * ReleaseDmiBufferStub - * - * Description: - * This is the default routine for use when the DMI option is NOT requested. - * - * Parameters: - * @param[in, out] *StdHeader - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -ReleaseDmiBufferStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_UNSUPPORTED; -} - -/* -----------------------------------------------------------------------------*/ -/** - * ReleaseDmiBuffer - * - * Description: - * Deallocate DMI buffer - * - * Parameters: - * @param[in, out] *StdHeader - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -ReleaseDmiBuffer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - HeapDeallocateBuffer ((UINT32) AMD_DMI_MEM_DEV_INFO_HANDLE, StdHeader); - - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * IntToString - * - * Description: - * Translate UINT array to CHAR array. - * - * Parameters: - * @param[in, out] *String Pointer to CHAR array - * @param[in] *Integer Pointer to UINT array - * @param[in] SizeInByte The size of UINT array - * - * Processing: - * - */ -VOID -STATIC -IntToString ( - IN OUT CHAR8 *String, - IN UINT8 *Integer, - IN UINT8 SizeInByte - ) -{ - UINT8 Index; - - for (Index = 0; Index < SizeInByte; Index++) { - *(String + Index * 2) = (*(Integer + Index) >> 4) & 0x0F; - *(String + Index * 2 + 1) = *(Integer + Index) & 0x0F; - } - for (Index = 0; Index < (SizeInByte * 2); Index++) { - if (*(String + Index) >= 0x0A) { - *(String + Index) += 0x37; - } else { - *(String + Index) += 0x30; - } - } - *(String + SizeInByte * 2) = 0x0; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c deleted file mode 100644 index 294a18d7e4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatureLeveling.c +++ /dev/null @@ -1,266 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Feature Leveling Function. - * - * Contains code to Level the Feature in a multi-socket system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - *---------------------------------------------------------------------------- - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuPostInit.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -SaveFeatures ( - IN OUT VOID *cpuFeatureListPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -WriteFeatures ( - IN OUT VOID *cpuFeatureListPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -GetGlobalCpuFeatureListAddress ( - OUT UINT64 **Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * FeatureLeveling - * - * CPU feature leveling. Set least common features set of all CPUs - * - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -FeatureLeveling ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Socket; - UINT32 Core; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - BOOLEAN *FirstTime; - BOOLEAN *NeedLeveling; - AGESA_STATUS IgnoredSts; - CPU_FEATURES_LIST *globalCpuFeatureList; - AP_TASK TaskPtr; - - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - GetGlobalCpuFeatureListAddress ((UINT64 **) &globalCpuFeatureList, StdHeader); - FirstTime = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST)); - NeedLeveling = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN)); - - *FirstTime = TRUE; - *NeedLeveling = FALSE; - - LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader); - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - TaskPtr.FuncAddress.PfApTaskI = SaveFeatures; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (CPU_FEATURES_LIST); - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataPtr = globalCpuFeatureList; - TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - if (Socket != BscSocket) { - ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader); - } - } - } - ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL); - - if (*NeedLeveling) { - TaskPtr.FuncAddress.PfApTaskI = WriteFeatures; - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader); - } - } - } - } - ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL); - } -} - -/*---------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * SaveFeatures - * - * save least common features set of all CPUs - * - * @param[in,out] cpuFeatureListPtr - Pointer to CPU Feature List. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -STATIC -SaveFeatures ( - IN OUT VOID *cpuFeatureListPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - FamilySpecificServices = NULL; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * WriteFeatures - * - * Write out least common features set of all CPUs - * - * @param[in,out] cpuFeatureListPtr - Pointer to CPU Feature List. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -STATIC -WriteFeatures ( - IN OUT VOID *cpuFeatureListPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - FamilySpecificServices = NULL; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * GetGlobalCpuFeatureListAddress - * - * Determines the address in system DRAM that should be used for CPU feature leveling. - * - * @param[out] Address Address to utilize - * @param[in] StdHeader Config handle for library and services - * - * - */ -VOID -STATIC -GetGlobalCpuFeatureListAddress ( - OUT UINT64 **Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 AddressValue; - - AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR; - - *Address = (UINT64 *) (intptr_t) (AddressValue); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.c deleted file mode 100644 index fa87380608..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.c +++ /dev/null @@ -1,199 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Implement general feature dispatcher. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "cpuFeatures.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_FEATURE_CPUFEATURES_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - External General Services API - *---------------------------------------------------------------------------------------- - */ -extern CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[]; - -/** - * Determines if a specific feature is or will be enabled. - * - * This code traverses the feature list until a match is - * found, then invokes the 'IsEnabled' function of the - * feature. - * - * @param[in] Feature Indicates the desired feature. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Standard AMD configuration parameters. - * - * @retval TRUE Feature is or will be enabled - * @retval FALSE Feature is not enabled - */ -BOOLEAN -IsFeatureEnabled ( - IN DISPATCHABLE_CPU_FEATURES Feature, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN i; - - ASSERT (Feature < MaxCpuFeature); - - for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) { - if (SupportedCpuFeatureList[i]->Feature == Feature) { - return (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)); - } - } - return FALSE; -} - -/** - * Dispatches all features needing to perform some initialization at - * this time point. - * - * This routine searches the feature table for features needing to - * run at this time point, and invokes them. - * - * @param[in] EntryPoint Timepoint designator - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Standard AMD configuration parameters. - * - * @return The most severe status of any called service. - */ -AGESA_STATUS -DispatchCpuFeatures ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN i; - AGESA_STATUS AgesaStatus; - AGESA_STATUS CalledStatus; - AGESA_STATUS IgnoredStatus; - - AgesaStatus = AGESA_SUCCESS; - - if (IsBsp (StdHeader, &IgnoredStatus)) { - for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) { - if ((SupportedCpuFeatureList[i]->EntryPoint & EntryPoint) != 0) { - IDS_SKIP_HOOK (IDS_CPU_FEAT, (CPU_FEATURE_DESCRIPTOR *) SupportedCpuFeatureList[i], StdHeader) { - if (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)) { - CalledStatus = SupportedCpuFeatureList[i]->InitializeFeature (EntryPoint, PlatformConfig, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - } - } - } - } - } - return AgesaStatus; -} - -/** - * This routine checks whether any non-coherent links in the system - * runs in HT1 mode; used to determine whether certain features - * should be disabled when this routine returns TRUE. - * - * @param[in] StdHeader Standard AMD configuration parameters. - * - * @retval TRUE One of the non-coherent links in the - * system runs in HT1 mode - * @retval FALSE None of the non-coherent links in the - * system is running in HT1 mode - */ -BOOLEAN -IsNonCoherentHt1 ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Link; - UINT32 Socket; - UINT32 Module; - PCI_ADDR PciAddress; - AGESA_STATUS AgesaStatus; - HT_HOST_FEATS HtHostFeats; - CPU_SPECIFIC_SERVICES *CpuServices; - - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&CpuServices, StdHeader); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { - HtHostFeats.HtHostValue = 0; - Link = 0; - while (CpuServices->GetNextHtLinkFeatures (CpuServices, &Link, &PciAddress, &HtHostFeats, StdHeader)) { - // Return TRUE and exit routine once we find a non-coherent link in HT1 - if ((HtHostFeats.HtHostFeatures.NonCoherent == 1) && (HtHostFeats.HtHostFeatures.Ht1 == 1)) { - return TRUE; - } - } - } - } - } - } - - return FALSE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.h deleted file mode 100644 index a94afe6711..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.h +++ /dev/null @@ -1,269 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Generic CPU feature dispatcher and related services. - * - * Provides a feature processing engine to handle feature in a - * more generic way. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_FEATURES_H_ -#define _CPU_FEATURES_H_ - -/** - * @page cpufeatimpl CPU Generic Feature Implementation Guide - * - * The CPU generic feature dispatcher provides services which can be used to implement a - * wide range of features in a manner that isolates calling code from knowledge about which - * families or features are supported in the current build. - * - * @par Determine if a New Feature is a Suitable Candidate - * - * A feature must meet the following requirements: - *
    - *
  • Any core in the system must be able to determine if the feature should be enabled or not. - * - *
      - *
    • MSRs cannot be read in multisocket systems in the 'IsEnabled' function. - * - *
    • Cores cannot be launched in the 'IsEnabled' function. - *
    - *
- * - * @par Determine the Time Point at which the Feature Should be Enabled - * - * Factors to consider in making this determination: - * - *
    - *
  • Determine if there are any dependencies on other settings that require strict ordering. - * - *
  • Consider the state of the APs that you will need. - * - *
  • Remember that features enabled during AmdInitEarly will automatically be restored on S3 resume. - *
- * - * @par Implementing a new feature - * - * Perform the following steps to implement a new feature: - * - *
    - *
  • Create a unique equate for your time point, @b if you cannot use an existing time point. - * - *
  • Create a new value in the DISPATCHABLE_CPU_FEATURES enum for your feature. - * - *
  • Add a new 'C' file to the Features folder for your feature. - * - *
      - *
    • The 'C' file must implement 2 functions -- 'IsEnabled' and 'Initialize' - * - *
    • The 'C' file must instantiate a CPU_FEATURE_DESCRIPTOR structure. - *
    - * - *
  • Add a new 'H' file to the Features folder for your feature. - * - *
      - *
    • The 'H' file declares whatever family specific functions required by the feature. - * - *
    • The 'H' file declares a structure containing all family specific functions. For a reference - * example, your feature API should have a set of conventions similar to cpu specific services, - * @ref cpuimplfss. - *
    - * - *
  • Create 'C' files in all applicable family folders. - * - *
      - *
    • Implement the required family specific functions. - * - *
    • Instantiate a family specific services structure. - *
    - * - *
  • Create \Install.h in the include folder. - * - *
      - *
    • Add logic to determine when your feature should be included in the build. - * - *
    • If the feature should be included, define OPTION_\ to the address of your - * CPU_FEATURE_DESCRIPTOR instantiation. If not, define OPTION_\ to be blank. - * - *
    • Create a family translation table pointing to all applicable instantiations of - * family specific function structures. - *
    - * - *
  • Modify OptionCpuFeaturesInstall.h in the include folder. - * - *
      - *
    • Include \Install.h. - * - *
    • Add OPTION_\ to the SupportedCpuFeatureList array. - *
    - * - *
  • If a new time point was created, add a call to DispatchCpuFeatures at the desired location, - * passing your new time point equate. - *
- * - */ - - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ -#define CPU_FEAT_BEFORE_PM_INIT (0x0000000000000001ull) -#define CPU_FEAT_AFTER_PM_INIT (0x0000000000000002ull) -#define CPU_FEAT_AFTER_POST_MTRR_SYNC (0x0000000000000004ull) -#define CPU_FEAT_INIT_MID_END (0x0000000000000008ull) -#define CPU_FEAT_INIT_LATE_END (0x0000000000000010ull) -#define CPU_FEAT_S3_LATE_RESTORE_END (0x0000000000000020ull) -#define CPU_FEAT_AFTER_RESUME_MTRR_SYNC (0x0000000000000040ull) -#define CPU_FEAT_AFTER_COHERENT_DISCOVERY (0x0000000000000080ull) -#define CPU_FEAT_BEFORE_RELINQUISH_AP (0x0000000000000100ull) -/** - * Enumerated list of supported features. - */ -typedef enum { - HardwareC1e, ///< Hardware C1e - L3Features, ///< L3 dependent features - MsgBasedC1e, ///< Message-based C1e - SoftwareC1e, ///< Software C1e - CoreLeveling, ///< Core Leveling - C6Cstate, ///< C6 C-state - IoCstate, ///< IO C-state - CacheFlushOnHalt, ///< Cache Flush On Halt - PreserveAroundMailbox, ///< Save-Restore the registers used for AP mailbox, to preserve their normal function. - CoreBoost, ///< Core Performance Boost (CPB) - LowPwrPstate, ///< 500 MHz Low Power P-state - PstateHpcMode, ///< High performance computing mode - CpuApm, ///< Application Power Management - CpuPsi, ///< Power Status Indicator - CpuHtc, ///< Hardware Thermal Control - MaxCpuFeature ///< Not a valid value, used for verifying input -} DISPATCHABLE_CPU_FEATURES; - -/*---------------------------------------------------------------------------------------*/ -/** - * Feature specific call to check if it is supported by the system. - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Feature is supported. - * @retval FALSE Feature is not supported. - * - */ -typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED; - -/*---------------------------------------------------------------------------------------*/ -/** - * The feature's main entry point for enablement. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_CPU_FEATURE_INITIALIZE ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_FEATURE_INITIALIZE *PF_CPU_FEATURE_INITIALIZE; - - -/** - * Generic feature descriptor - */ -typedef struct { - DISPATCHABLE_CPU_FEATURES Feature; ///< Enumerated feature ID - UINT64 EntryPoint; ///< Timepoint designator - PF_CPU_FEATURE_IS_ENABLED IsEnabled; ///< Pointer to the function that checks if the feature is supported - PF_CPU_FEATURE_INITIALIZE InitializeFeature; ///< Pointer to the function that enables the feature -} CPU_FEATURE_DESCRIPTOR; - -/** - * Table descriptor for the installed features. - */ -typedef struct { - UINT8 NumberOfFeats; ///< Number of valid entries in the table. - CPU_FEATURE_DESCRIPTOR *FeatureList; ///< Pointer to the first element in the array. -} CPU_FEATURE_TABLE; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -BOOLEAN -IsFeatureEnabled ( - IN DISPATCHABLE_CPU_FEATURES Feature, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -DispatchCpuFeatures ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -IsNonCoherentHt1 ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_FEATURES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.c deleted file mode 100644 index ab9a46ef8b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.c +++ /dev/null @@ -1,181 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU HW C1e feature support code. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "Topology.h" -#include "cpuFeatures.h" -#include "cpuHwC1e.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUHWC1E_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should hardware C1e be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HW C1e is supported. - * @retval FALSE HW C1e cannot be enabled. - * - */ -BOOLEAN -STATIC -IsHwC1eFeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 C1eData; - BOOLEAN IsEnabled; - AP_MAILBOXES ApMailboxes; - HW_C1E_FAMILY_SERVICES *FamilyServices; - - ASSERT (PlatformConfig->C1eMode < MaxC1eMode); - IsEnabled = FALSE; - C1eData = PlatformConfig->C1ePlatformData; - if ((PlatformConfig->C1eMode == C1eModeHardware) || (PlatformConfig->C1eMode == C1eModeHardwareSoftwareDeprecated) || - (PlatformConfig->C1eMode == C1eModeAuto)) { - // If C1eMode is Auto, C1ePlatformData3 specifies the P_LVL3 I/O port of the platform for HW C1e - if (PlatformConfig->C1eMode == C1eModeAuto) { - C1eData = PlatformConfig->C1ePlatformData3; - } - ASSERT (C1eData < 0x10000); - ASSERT (C1eData != 0); - if ((C1eData != 0) && (C1eData < 0xFFFE)) { - if (!IsNonCoherentHt1 (StdHeader)) { - if (GetNumberOfProcessors (StdHeader) == 1) { - GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); - if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) { - GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - IsEnabled = FamilyServices->IsHwC1eSupported (FamilyServices, StdHeader); - } - } - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable Hardware C1e - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return The most severe status of any family specific service. - * - */ -AGESA_STATUS -STATIC -InitializeHwC1eFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS CalledStatus; - AGESA_STATUS AgesaStatus; - HW_C1E_FAMILY_SERVICES *FamilyServices; - - AgesaStatus = AGESA_SUCCESS; - - IDS_HDT_CONSOLE (CPU_TRACE, " HW C1e is enabled\n"); - - if (IsWarmReset (StdHeader)) { - GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - CalledStatus = FamilyServices->InitializeHwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - } - return AgesaStatus; -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e = -{ - HardwareC1e, - CPU_FEAT_AFTER_PM_INIT, - IsHwC1eFeatureEnabled, - InitializeHwC1eFeature -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.h deleted file mode 100644 index 0d2d708e50..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.h +++ /dev/null @@ -1,124 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU HW C1e Functions declarations. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_HW_C1E_H_ -#define _CPU_HW_C1E_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (HW_C1E_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if hardware C1e is supported. - * - * @param[in] HwC1eServices Hardware C1e services. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HW C1e is supported. - * @retval FALSE HW C1e is not supported. - * - */ -typedef BOOLEAN F_HW_C1E_IS_SUPPORTED ( - IN HW_C1E_FAMILY_SERVICES *HwC1eServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable hardware C1e. - * - * @param[in] HwC1eServices Hardware C1e services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_HW_C1E_INIT ( - IN HW_C1E_FAMILY_SERVICES *HwC1eServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_HW_C1E_INIT *PF_HW_C1E_INIT; - -/** - * Provide the interface to the hardware C1e Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _HW_C1E_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_HW_C1E_IS_SUPPORTED IsHwC1eSupported; ///< Method: Family specific call to check if hardware C1e is supported. - PF_HW_C1E_INIT InitializeHwC1e; ///< Method: Family specific call to enable hardware C1e. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_HW_C1E_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.c deleted file mode 100644 index ff5d4424fc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.c +++ /dev/null @@ -1,208 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU IO Cstate function declarations. - * - * Contains code that declares the AGESA CPU IO Cstate related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "cpuFeatures.h" -#include "cpuIoCstate.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuApicUtilities.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -STATIC -EnableIoCstateOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ); -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should IO Cstate be enabled - * If all processors support IO Cstate, return TRUE. Otherwise, return FALSE - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE IO Cstate is supported. - * @retval FALSE IO Cstate cannot be enabled. - * - */ -BOOLEAN -STATIC -IsIoCstateFeatureSupported ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - BOOLEAN IsSupported; - IO_CSTATE_FAMILY_SERVICES *IoCstateServices; - - IsSupported = FALSE; - if ((PlatformConfig->CStateIoBaseAddress != 0) && (PlatformConfig->CStateIoBaseAddress <= 0xFFF8)) { - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, (CONST VOID **)&IoCstateServices, StdHeader); - if (IoCstateServices != NULL) { - if (IoCstateServices->IsIoCstateSupported (IoCstateServices, Socket, StdHeader)) { - IsSupported = TRUE; - } else { - // Stop checking remaining socket(s) once we find one that does not support IO Cstates - IsSupported = FALSE; - break; - } - } else { - // Exit the for loop if we found a socket that does not have the IO Cstates feature installed - IsSupported = FALSE; - break; - } - } - } - } - return IsSupported; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable IO Cstate feature - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeIoCstateFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - AMD_CPU_EARLY_PARAMS CpuEarlyParams; - - IDS_HDT_CONSOLE (CPU_TRACE, " IO C-state is enabled\n"); - - CpuEarlyParams.PlatformConfig = *PlatformConfig; - - TaskPtr.FuncAddress.PfApTaskIC = EnableIoCstateOnSocket; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &EntryPoint; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * 'Local' core 0 task to enable IO Cstate on it's socket. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] CpuEarlyParams Service parameters. - * - */ -VOID -STATIC -EnableIoCstateOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ) -{ - IO_CSTATE_FAMILY_SERVICES *FamilyServices; - - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - FamilyServices->InitializeIoCstate (FamilyServices, - *((UINT64 *) EntryPoint), - &CpuEarlyParams->PlatformConfig, - StdHeader); -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate = -{ - IoCstate, - (CPU_FEAT_AFTER_PM_INIT), - IsIoCstateFeatureSupported, - InitializeIoCstateFeature -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.h deleted file mode 100644 index ae2c853502..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU IO Cstate feature support code. - * - * Contains code that declares the AGESA CPU IO Cstate related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_IO_CSTATE_H_ -#define _CPU_IO_CSTATE_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (IO_CSTATE_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -// Defines for ACPI C-State Objects -#define CST_NAME__ '_' -#define CST_NAME_C 'C' -#define CST_NAME_S 'S' -#define CST_NAME_T 'T' -#define CST_LENGTH (CST_BODY_SIZE - 1) -#define CST_NUM_OF_ELEMENTS 0x02 -#define CST_COUNT 0x01 -#define CST_PKG_LENGTH (CST_BODY_SIZE - 6) // CST_BODY_SIZE - PkgHeader - Count Buffer -#define CST_PKG_ELEMENTS 0x04 -#define CST_SUBPKG_LENGTH 0x14 -#define CST_SUBPKG_ELEMENTS 0x0A -#define CST_GDR_LENGTH 0x000C -#define CST_C1_TYPE 0x01 -#define CST_C2_TYPE 0x02 - -#define CSD_NAME_D 'D' -#define CSD_COORD_TYPE_HW_ALL 0xFE - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/* AML code definition */ - -/// CST Header -typedef struct _CST_HEADER_STRUCT { - UINT8 NameOpcode; ///< Name Opcode - UINT8 CstName_a__; ///< String "_" - UINT8 CstName_a_C; ///< String "C" - UINT8 CstName_a_S; ///< String "S" - UINT8 CstName_a_T; ///< String "T" -} CST_HEADER_STRUCT; -#define CST_HEADER_SIZE 5 - -/// CST Body -typedef struct _CST_BODY_STRUCT { - UINT8 PkgOpcode; ///< Package Opcode - UINT8 PkgLength; ///< Package Length - UINT8 PkgElements; ///< Number of Elements - UINT8 BytePrefix; ///< Byte Prefix Opcode - UINT8 Count; ///< Number of Cstate info packages - UINT8 PkgOpcode2; ///< Package Opcode - UINT8 PkgLength2; ///< Package Length - UINT8 PkgElements2; ///< Number of Elements - UINT8 BufferOpcode; ///< Buffer Opcode - UINT8 BufferLength; ///< Buffer Length - UINT8 BufferElements; ///< Number of Elements - UINT8 BufferOpcode2; ///< Buffer Opcode - UINT8 GdrOpcode; ///< Generic Register Descriptor Opcode - UINT16 GdrLength; ///< Descriptor Length - UINT8 AddrSpaceId; ///< Address Space ID - UINT8 RegBitWidth; ///< Register Bit Width - UINT8 RegBitOffset; ///< Register Bit Offset - UINT8 AddressSize; ///< Address Size - UINT64 RegisterAddr; ///< Register Address - UINT16 EndTag; ///< End Tag Descriptor - UINT8 BytePrefix2; ///< Byte Prefix Opcode - UINT8 Type; ///< Type - UINT8 WordPrefix; ///< Word Prefix Opcode - UINT16 Latency; ///< Latency - UINT8 DWordPrefix; ///< Dword Prefix Opcode - UINT32 Power; ///< Power -} CST_BODY_STRUCT; -#define CST_BODY_SIZE 39 - -/// CSD Header -typedef struct _CSD_HEADER_STRUCT { - UINT8 NameOpcode; ///< Name Opcode - UINT8 CsdName_a__; ///< String "_" - UINT8 CsdName_a_C; ///< String "C" - UINT8 CsdName_a_S; ///< String "S" - UINT8 CsdName_a_D; ///< String "D" -} CSD_HEADER_STRUCT; -#define CSD_HEADER_SIZE 5 - -/// CSD Body -typedef struct _CSD_BODY_STRUCT { - UINT8 PkgOpcode; ///< Package Opcode - UINT8 PkgLength; ///< Package Length - UINT8 PkgElements; ///< Number of Elements - UINT8 PkgOpcode2; ///< Package Opcode - UINT8 PkgLength2; ///< Package Length - UINT8 PkgElements2; ///< Number of Elements - UINT8 BytePrefix; ///< Byte Prefix Opcode - UINT8 NumEntries; ///< Number of Entries - UINT8 BytePrefix2; ///< Byte Prefix Opcode - UINT8 Revision; ///< Revision - UINT8 DWordPrefix; ///< DWord Prefix Opcode - UINT32 Domain; ///< Dependency Domain Number - UINT8 DWordPrefix2; ///< DWord Prefix Opcode - UINT32 CoordType; ///< Coordination Type - UINT8 DWordPrefix3; ///< Dword Prefix Opcode - UINT32 NumProcessors; ///< Number of Processors in the Domain - UINT8 DWordPrefix4; ///< Dword Prefix Opcode - UINT32 Index; ///< Index of C-State entry for which dependency applies -} CSD_BODY_STRUCT; -#define CSD_BODY_SIZE 30 - -/// input for create _CST -typedef struct _ACPI_CST_CREATE_INPUT { - IO_CSTATE_FAMILY_SERVICES *IoCstateServices; ///< Family service of IoCstate - UINT8 LocalApicId; ///< Local Apic for create _CST - VOID **PstateAcpiBufferPtr; ///< buffer for fill _CST -} ACPI_CST_CREATE_INPUT ; - -/// input for get _CST -typedef struct _ACPI_CST_GET_INPUT { - IO_CSTATE_FAMILY_SERVICES *IoCstateServices; ///< Family service of IoCstate - PLATFORM_CONFIGURATION *PlatformConfig; ///< platform config - UINT32 *CStateAcpiObjSizePtr; ///< Point to size of _CST -} ACPI_CST_GET_INPUT ; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if IO Cstate is supported. - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] Socket Zero-based socket number. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE IO Cstate is supported. - * @retval FALSE IO Cstate is not supported. - * - */ -typedef BOOLEAN F_IO_CSTATE_IS_SUPPORTED ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable IO Cstate. - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_IO_CSTATE_INIT ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to return the size of ACPI C-State Objects - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data - * @param[in] StdHeader Config Handle for library, services. - * - * @retval Size of ACPI C-State Objects - * - */ -typedef UINT32 F_IO_CSTATE_GET_CST_SIZE ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to create ACPI C-State Objects - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] LocalApicId Local Apic Id - * @param[in, out] PstateAcpiBufferPtr Pointer to Pstate data buffer - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_IO_CSTATE_CREATE_CST ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT8 LocalApicId, - IN OUT VOID **PstateAcpiBufferPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check whether CSD object should be created. - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE CSD Object should be created. - * @retval FALSE CSD Object should not be created. - * - */ -typedef BOOLEAN F_IO_CSTATE_IS_CSD_GENERATED ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method -typedef F_IO_CSTATE_IS_SUPPORTED *PF_IO_CSTATE_IS_SUPPORTED; -typedef F_IO_CSTATE_INIT *PF_IO_CSTATE_INIT; -typedef F_IO_CSTATE_GET_CST_SIZE *PF_IO_CSTATE_GET_CST_SIZE; -typedef F_IO_CSTATE_CREATE_CST *PF_IO_CSTATE_CREATE_CST; -typedef F_IO_CSTATE_IS_CSD_GENERATED *PF_IO_CSTATE_IS_CSD_GENERATED; - -/** - * Provide the interface to the IO Cstate Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _IO_CSTATE_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_IO_CSTATE_IS_SUPPORTED IsIoCstateSupported; ///< Method: Family specific call to check if IO Cstate is supported. - PF_IO_CSTATE_INIT InitializeIoCstate; ///< Method: Family specific call to enable IO Cstate - PF_IO_CSTATE_GET_CST_SIZE GetAcpiCstObj; ///< Method: Family specific call to return the size of ACPI CST objects. - PF_IO_CSTATE_CREATE_CST CreateAcpiCstObj; ///< Method: Family specific call to create ACPI CST object - PF_IO_CSTATE_IS_CSD_GENERATED IsCsdObjGenerated; ///< Method: Family specific call to check whether CSD Object should be created. -}; - -#endif // _CPU_IO_CSTATE_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.c deleted file mode 100644 index 8096e2b3ee..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.c +++ /dev/null @@ -1,350 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU L3 Features Initialization functions. - * - * Contains code for initializing L3 features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 60552 $ @e \$Date: 2011-10-17 18:50:55 -0600 (Mon, 17 Oct 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuLateInit.h" -#include "cpuFamilyTranslation.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFeatures.h" -#include "cpuL3Features.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should L3 features be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE L3 Features are supported - * @retval FALSE L3 Features are not supported - * - */ -BOOLEAN -STATIC -IsL3FeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsEnabled; - UINT32 Socket; - L3_FEATURE_FAMILY_SERVICES *FamilyServices; - - IsEnabled = FALSE; - if (PlatformConfig->PlatformProfile.UseHtAssist || - PlatformConfig->PlatformProfile.UseAtmMode) { - IsEnabled = TRUE; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); - if ((FamilyServices == NULL) || !FamilyServices->IsL3FeatureSupported (FamilyServices, Socket, StdHeader, PlatformConfig)) { - IsEnabled = FALSE; - break; - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable L3 dependent features. - * - * L3 features initialization requires the following series of steps. - * 1. Disable L3 and DRAM scrubbers on all nodes - * 2. Wait 40us for outstanding scrub results to complete - * 3. Disable all cache activity in the system - * 4. Issue WBINVD on all active cores - * 5. Initialize Probe Filter, if supported - * 6. Initialize ATM Mode, if supported - * 7. Enable all cache activity in the system - * 8. Restore L3 and DRAM scrubber register values - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeL3Feature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpuCount; - UINT32 Socket; - BOOLEAN HtAssistEnabled; - BOOLEAN AtmModeEnabled; - AGESA_STATUS AgesaStatus; - AP_MAILBOXES ApMailboxes; - AP_EXE_PARAMS ApParams; - UINT32 Scrubbers[MAX_SOCKETS_SUPPORTED][L3_SCRUBBER_CONTEXT_ARRAY_SIZE]; - L3_FEATURE_FAMILY_SERVICES *FamilyServices[MAX_SOCKETS_SUPPORTED]; - - AgesaStatus = AGESA_SUCCESS; - HtAssistEnabled = TRUE; - AtmModeEnabled = TRUE; - - IDS_HDT_CONSOLE (CPU_TRACE, " Enabling L3 dependent features\n"); - - // There are many family service call outs. Initialize the family service array while - // cache is still enabled. - for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices[Socket], StdHeader); - } else { - FamilyServices[Socket] = NULL; - } - } - - if (EntryPoint == CPU_FEAT_AFTER_POST_MTRR_SYNC) { - // Check for optimal settings - GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); - CpuCount = GetNumberOfProcessors (StdHeader); - if (((CpuCount == 1) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 1)) || - ((CpuCount == 2) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 0))) { - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - // Only check for non-optimal HT Assist setting is if's supported. - if ((FamilyServices[Socket] != NULL) && - (FamilyServices[Socket]->IsHtAssistSupported (FamilyServices[Socket], PlatformConfig, StdHeader))) { - if (FamilyServices[Socket]->IsNonOptimalConfig (FamilyServices[Socket], Socket, StdHeader)) { - // Non-optimal settings. Log an event. - AgesaStatus = AGESA_WARNING; - PutEventLog (AgesaStatus, CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG, 0, 0, 0, 0, StdHeader); - break; - } - } - } - } - } else { - // Disable the scrubbers. - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (FamilyServices[Socket] != NULL) { - FamilyServices[Socket]->GetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader); - - // If any node in the system does not support Probe Filter, disable it on the system - if (!FamilyServices[Socket]->IsHtAssistSupported (FamilyServices[Socket], PlatformConfig, StdHeader)) { - HtAssistEnabled = FALSE; - } - // If any node in the system does not support ATM mode, disable it on the system - if (!FamilyServices[Socket]->IsAtmModeSupported (FamilyServices[Socket], PlatformConfig, StdHeader)) { - AtmModeEnabled = FALSE; - } - } - } - - // Wait for 40us - WaitMicroseconds ((UINT32) 40, StdHeader); - - // Run DisableAllCaches on AP cores. - ApParams.StdHeader = *StdHeader; - ApParams.FunctionNumber = AP_LATE_TASK_DISABLE_CACHE; - ApParams.RelatedDataBlock = (VOID *) &HtAssistEnabled; - ApParams.RelatedBlockLength = sizeof (BOOLEAN); - RunLateApTaskOnAllAPs (&ApParams, StdHeader); - - // Run DisableAllCaches on core 0. - DisableAllCaches (&ApParams); - - // Family hook before initialization. - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (FamilyServices[Socket] != NULL) { - FamilyServices[Socket]->HookBeforeInit (FamilyServices[Socket], Socket, StdHeader); - } - } - - // Activate Probe Filter & ATM mode. - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (FamilyServices[Socket] != NULL) { - if (HtAssistEnabled) { - FamilyServices[Socket]->HtAssistInit (FamilyServices[Socket], Socket, StdHeader); - } - if (AtmModeEnabled) { - FamilyServices[Socket]->AtmModeInit (FamilyServices[Socket], Socket, StdHeader); - } - } - } - - // Family hook after initialization. - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (FamilyServices[Socket] != NULL) { - FamilyServices[Socket]->HookAfterInit (FamilyServices[Socket], Socket, StdHeader); - } - } - - // Run EnableAllCaches on core 0. - EnableAllCaches (&ApParams); - - // Run EnableAllCaches on every core. - ApParams.FunctionNumber = AP_LATE_TASK_ENABLE_CACHE; - RunLateApTaskOnAllAPs (&ApParams, StdHeader); - - // Restore the scrubbers. - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (FamilyServices[Socket] != NULL) { - FamilyServices[Socket]->SetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader); - } - } - } - - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Disable all the caches on current core. - * - * @param[in] ApExeParams Handle to config for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -DisableAllCaches ( - IN AP_EXE_PARAMS *ApExeParams - ) -{ - UINT32 CR0Data; - L3_FEATURE_FAMILY_SERVICES *FamilyServices; - - // Disable cache through CR0. - LibAmdReadCpuReg (0, &CR0Data); - CR0Data |= (0x60000000); - LibAmdWriteCpuReg (0, CR0Data); - - // Execute wbinvd - LibAmdWriteBackInvalidateCache (); - - GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (CONST VOID **)&FamilyServices, &ApExeParams->StdHeader); - - FamilyServices->HookDisableCache (FamilyServices, *(BOOLEAN *) ApExeParams->RelatedDataBlock, &ApExeParams->StdHeader); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Enable all the caches on current core. - * - * @param[in] ApExeParams Handle to config for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -EnableAllCaches ( - IN AP_EXE_PARAMS *ApExeParams - ) -{ - UINT32 CR0Data; - L3_FEATURE_FAMILY_SERVICES *FamilyServices; - - // Enable cache through CR0. - LibAmdReadCpuReg (0, &CR0Data); - CR0Data &= ~(0x60000000); - LibAmdWriteCpuReg (0, CR0Data); - - GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (CONST VOID **)&FamilyServices, &ApExeParams->StdHeader); - - FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader); - - return AGESA_SUCCESS; -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features = -{ - L3Features, - (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_INIT_MID_END | CPU_FEAT_S3_LATE_RESTORE_END), - IsL3FeatureEnabled, - InitializeL3Feature -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h deleted file mode 100644 index ff75b191df..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h +++ /dev/null @@ -1,361 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU L3 Features Initialization functions. - * - * Contains code that declares the AGESA CPU L3 dependent feature related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 60552 $ @e \$Date: 2011-10-17 18:50:55 -0600 (Mon, 17 Oct 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_L3_FEATURES_H_ -#define _CPU_L3_FEATURES_H_ - -#include "Filecode.h" -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (L3_FEATURE_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -#define AP_LATE_TASK_DISABLE_CACHE (0x00000000 | PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE) -#define AP_LATE_TASK_ENABLE_CACHE (0x00010000 | PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE) - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4 - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if L3 Features are supported. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * - * @retval TRUE L3 dependent features are supported - * @retval FALSE L3 dependent features are not supported - * - */ -typedef BOOLEAN F_L3_FEATURE_IS_SUPPORTED ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_IS_SUPPORTED *PF_L3_FEATURE_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific hook before L3 features are initialized. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_BEFORE_INIT ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_BEFORE_INIT *PF_L3_FEATURE_BEFORE_INIT; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to disable cache. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] HtAssistEnabled Indicates whether Ht Assist is enabled. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_DISABLE_CACHE ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN BOOLEAN HtAssistEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_DISABLE_CACHE *PF_L3_FEATURE_DISABLE_CACHE; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to disable cache. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef VOID F_L3_FEATURE_ENABLE_CACHE ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_ENABLE_CACHE *PF_L3_FEATURE_ENABLE_CACHE; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to Initialize L3 Features - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to enable. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_INIT ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_INIT *PF_L3_FEATURE_INIT; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific hook after L3 Features are initialized. - * - * @param[in] L3FeatureServices L3 Features family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_AFTER_INIT ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_AFTER_INIT *PF_L3_FEATURE_AFTER_INIT; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to save the L3 scrubber. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] ScrubSettings Location to store current L3 scrubber settings. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_GET_L3_SCRUB_CTRL ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_GET_L3_SCRUB_CTRL *PF_L3_FEATURE_GET_L3_SCRUB_CTRL; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to restore the L3 scrubber. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] ScrubSettings Contains L3 scrubber settings to restore. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_L3_FEATURE_SET_L3_SCRUB_CTRL ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_L3_FEATURE_SET_L3_SCRUB_CTRL *PF_L3_FEATURE_SET_L3_SCRUB_CTRL; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if HT Assist is supported. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HT Assist is supported. - * @retval FALSE HT Assist is not supported. - * - */ -typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to Initialize HT Assist - * - * @param[in] L3FeatureServices L3 Features family services. - * @param[in] Socket Processor socket to enable. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_HT_ASSIST_INIT ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to provide non_optimal HT Assist support - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @return TRUE The system may be running with non-optimal settings. - * @return FALSE The system may is running optimally. - * - */ -typedef BOOLEAN F_HT_ASSIST_IS_NONOPTIMAL ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_HT_ASSIST_IS_NONOPTIMAL *PF_HT_ASSIST_IS_NONOPTIMAL; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if ATM Mode is supported. - * - * @param[in] L3FeatureServices L3 Features family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE ATM Mode is supported. - * @retval FALSE ATM Mode is not supported. - * - */ -typedef BOOLEAN F_ATM_MODE_IS_SUPPORTED ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_ATM_MODE_IS_SUPPORTED *PF_ATM_MODE_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to Initialize ATM mode - * - * @param[in] L3FeatureServices L3 Features family services. - * @param[in] Socket Processor socket to enable. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_ATM_MODE_INIT ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_ATM_MODE_INIT *PF_ATM_MODE_INIT; - -/** - * Provide the interface to the L3 dependent features Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _L3_FEATURE_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_L3_FEATURE_IS_SUPPORTED IsL3FeatureSupported; ///< Method: Check if L3 dependent features are supported. - PF_L3_FEATURE_GET_L3_SCRUB_CTRL GetL3ScrubCtrl; ///< Method: Save/disable the L3 scrubber. - PF_L3_FEATURE_SET_L3_SCRUB_CTRL SetL3ScrubCtrl; ///< Method: Restore the L3 scrubber. - PF_L3_FEATURE_BEFORE_INIT HookBeforeInit; ///< Method: Hook before enabling L3 dependent features. - PF_L3_FEATURE_AFTER_INIT HookAfterInit; ///< Method: Hook after enabling L3 dependent features. - PF_L3_FEATURE_DISABLE_CACHE HookDisableCache; ///< Method: Core hook just before disabling cache. - PF_L3_FEATURE_ENABLE_CACHE HookEnableCache; ///< Method: Core hook just after enabling cache. - PF_HT_ASSIST_IS_SUPPORTED IsHtAssistSupported; ///< Method: Check if HT Assist is supported. - PF_HT_ASSIST_INIT HtAssistInit; ///< Method: Enable HT Assist. - PF_HT_ASSIST_IS_NONOPTIMAL IsNonOptimalConfig; ///< Method: Check if HT Assist is running optimally. - PF_ATM_MODE_IS_SUPPORTED IsAtmModeSupported; ///< Method: Check if ATM Mode is supported. - PF_ATM_MODE_INIT AtmModeInit; ///< Method: Enable ATM Mode. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -DisableAllCaches ( - IN AP_EXE_PARAMS *ApExeParams - ); - -AGESA_STATUS -EnableAllCaches ( - IN AP_EXE_PARAMS *ApExeParams - ); - -#endif // _CPU_L3_FEATURES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.c deleted file mode 100644 index 8d835cfcb5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.c +++ /dev/null @@ -1,224 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU create low power P-state for PROCHOT_L throttling support code. - * - * Contains code that declares the AGESA CPU low power P-state related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 58314 $ @e \$Date: 2011-08-25 10:15:35 -0600 (Thu, 25 Aug 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuApicUtilities.h" -#include "OptionMultiSocket.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFeatures.h" -#include "cpuLowPwrPstate.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -EnableLowPwrPstateOnCore ( - IN VOID *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE LowPwrPstateFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should Low Power P-state be enabled - * If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Low Power P-state is supported. - * @retval FALSE Low Power P-state cannot be enabled. - * - */ -BOOLEAN -STATIC -IsLowPwrPstateFeatureSupported ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - BOOLEAN IsSupported; - LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices; - - IsSupported = FALSE; - if (PlatformConfig->LowPowerPstateForProcHot == LOW_POWER_PSTATE_FOR_PROCHOT_AUTO) { - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - if (FamilyServices->IsLowPwrPstateSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { - IsSupported = TRUE; - } else { - IsSupported = FALSE; - break; - } - } else { - IsSupported = FALSE; - break; - } - } - } - } - IDS_OPTION_HOOK (IDS_LOW_POWER_PSTATE, &IsSupported, StdHeader); - return IsSupported; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable low power P-state - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeLowPwrPstateFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - - if (!IsWarmReset (StdHeader)) { - IDS_HDT_CONSOLE (CPU_TRACE, " Low pwr P-state is enabled\n"); - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - TaskPtr.FuncAddress.PfApTaskI = EnableLowPwrPstateOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = PlatformConfig; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = NumberOfCores; Core != 0; Core--) { - if ((Socket != BscSocket) || ((Core - 1) != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) (Core - 1), &TaskPtr, StdHeader); - } - } - } - } - - EnableLowPwrPstateOnCore (PlatformConfig, StdHeader); - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * 'Local' core 0 task to enable low power P-state - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -EnableLowPwrPstateOnCore ( - IN VOID *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices; - - GetFeatureServicesOfCurrentCore (&LowPwrPstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - FamilyServices->EnableLowPwrPstate (FamilyServices, - PlatformConfig, - StdHeader); -} - - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate = -{ - LowPwrPstate, - (CPU_FEAT_BEFORE_RELINQUISH_AP | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsLowPwrPstateFeatureSupported, - InitializeLowPwrPstateFeature -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.h deleted file mode 100644 index 06b20d6db0..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.h +++ /dev/null @@ -1,128 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU create low power P-state for PROCHOT_L throttling Functions declarations. - * - * Contains code that declares the AGESA CPU low power P-state related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_LOW_PWR_PSTATE_H_ -#define _CPU_LOW_PWR_PSTATE_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (LOW_PWR_PSTATE_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if Low Power P-state is supported. - * - * @param[in] LowPwrPstateService Low Power P-state services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] Socket Zero-based socket number. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Low Power P-state is supported. - * @retval FALSE Low Power P-state is not supported. - * - */ -typedef BOOLEAN F_LOW_PWR_PSTATE_IS_SUPPORTED ( - IN LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateService, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_LOW_PWR_PSTATE_IS_SUPPORTED *PF_LOW_PWR_PSTATE_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable Low Power P-state - * - * @param[in] LowPwrPstateService Low Power P-state services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_LOW_PWR_PSTATE_INIT ( - IN LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateService, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_LOW_PWR_PSTATE_INIT *PF_LOW_PWR_PSTATE_INIT; - -/** - * Provide the interface to the Low Power P-state Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _LOW_PWR_PSTATE_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_LOW_PWR_PSTATE_IS_SUPPORTED IsLowPwrPstateSupported; ///< Method: Family specific call to check if Low Power P-state is supported. - PF_LOW_PWR_PSTATE_INIT EnableLowPwrPstate; ///< Method: Family specific call to enable Low Power P-state. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_LOW_PWR_PSTATE_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.c deleted file mode 100644 index cf938fc2e5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.c +++ /dev/null @@ -1,212 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Message-based C1e feature support code. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMultiSocket.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuMsgBasedC1e.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -EnableMsgC1eOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should message-based C1e be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Message-based C1e is supported. - * @retval FALSE Message-based C1e cannot be enabled. - * - */ -BOOLEAN -STATIC -IsMsgBasedC1eFeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsEnabled; - UINT32 Socket; - MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices; - - ASSERT (PlatformConfig->C1eMode < MaxC1eMode); - - IsEnabled = FALSE; - if ((PlatformConfig->C1eMode == C1eModeMsgBased) || (PlatformConfig->C1eMode == C1eModeAuto)) { - ASSERT (PlatformConfig->C1ePlatformData < 0x10000); - ASSERT (PlatformConfig->C1ePlatformData != 0); - if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) { - IsEnabled = TRUE; - if (IsNonCoherentHt1 (StdHeader)) { - IsEnabled = FALSE; - } else { - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); - if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) { - IsEnabled = FALSE; - break; - } - } - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable Message-based C1e - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializeMsgBasedC1eFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - AMD_CPU_EARLY_PARAMS CpuEarlyParams; - - IDS_HDT_CONSOLE (CPU_TRACE, " MT C1e is enabled\n"); - - if ((EntryPoint != CPU_FEAT_AFTER_PM_INIT) || (IsWarmReset (StdHeader))) { - CpuEarlyParams.PlatformConfig = *PlatformConfig; - - TaskPtr.FuncAddress.PfApTaskIC = EnableMsgC1eOnSocket; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &EntryPoint; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); - } - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * 'Local' core 0 task to enable message-based C1e on it's socket. - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] CpuEarlyParams Service parameters. - * - */ -VOID -STATIC -EnableMsgC1eOnSocket ( - IN VOID *EntryPoint, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ) -{ - MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices; - - GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - FamilyServices->InitializeMsgBasedC1e (FamilyServices, - *((UINT64 *) EntryPoint), - &CpuEarlyParams->PlatformConfig, - StdHeader); -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e = -{ - MsgBasedC1e, - (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsMsgBasedC1eFeatureEnabled, - InitializeMsgBasedC1eFeature -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.h deleted file mode 100644 index 492a49993a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.h +++ /dev/null @@ -1,126 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Message-based C1e Functions declarations. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_MSG_BASED_C1E_H_ -#define _CPU_MSG_BASED_C1E_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (MSG_BASED_C1E_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if message-based C1e is supported. - * - * @param[in] MsgBasedC1eServices Contains the runtime modifiable feature input data. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Message-based C1e is supported. - * @retval FALSE Message-based C1e is not supported. - * - */ -typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED ( - IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable hardware C1e. - * - * @param[in] MsgBasedC1eServices Hardware C1e services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_MSG_BASED_C1E_INIT ( - IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_MSG_BASED_C1E_INIT *PF_MSG_BASED_C1E_INIT; - -/** - * Provide the interface to the hardware C1e Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _MSG_BASED_C1E_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_MSG_BASED_C1E_IS_SUPPORTED IsMsgBasedC1eSupported; ///< Method: Family specific call to check if hardware C1e is supported. - PF_MSG_BASED_C1E_INIT InitializeMsgBasedC1e; ///< Method: Family specific call to enable hardware C1e. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_MSG_BASED_C1E_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateGather.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateGather.c deleted file mode 100644 index e5749a9421..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateGather.c +++ /dev/null @@ -1,411 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Pstate Data Gather Function. - * - * Contains code to collect all the Pstate related information from MSRs, and PCI registers. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionPstate.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuPostInit.h" -#include "Ids.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuApicUtilities.h" -#include "cpuFeatures.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration; // global user config record -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -PStateGatherStub ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr - ); - -AGESA_STATUS -PStateGatherMain ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr - ); - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -PStateGather ( - IN OUT VOID *PStateBuffer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - *--------------------------------------------------------------------------------------- - * - * PStateGatherData - * - * Description: - * This function will gather PState information from the MSRs and fill up the - * pStateBuf. This buffer will be used by the PState Leveling, and PState Table - * generation code later. - * - * Parameters: - * @param[in] *PlatformConfig - * @param[in, out] *PStateStrucPtr - * @param[in] *StdHeader - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateGatherData ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - - AGESA_STATUS AgesaStatus; - - AGESA_TESTPOINT (TpProcCpuEntryPstateGather, StdHeader); - AgesaStatus = AGESA_SUCCESS; - - // Gather data for ACPI Tables if ACPI P-States/C-States object generation is enabled. - if ((PlatformConfig->UserOptionPState) || (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader))) { - AgesaStatus = (*(OptionPstatePostConfiguration.PstateGather)) (StdHeader, PStateStrucPtr); - // Note: Split config struct into PEI/DXE halves. This one is PEI. - } - - return AgesaStatus; -} - -/**-------------------------------------------------------------------------------------- - * - * PStateGatherStub - * - * Description: - * This is the default routine for use when the PState option is NOT requested. - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * Parameters: - * @param[in] *StdHeader - * @param[in, out] *PStateStrucPtr - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateGatherStub ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr - ) -{ - return AGESA_UNSUPPORTED; -} - -/**-------------------------------------------------------------------------------------- - * - * PStateGatherMain - * - * Description: - * This is the common routine for BSP gathering the Pstate data. - * - * Parameters: - * @param[in] *StdHeader - * @param[in, out] *PStateStrucPtr - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateGatherMain ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr - ) -{ - AP_TASK TaskPtr; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 PopulatedSockets; - UINT32 NumberOfSockets; - UINT32 Socket; - AGESA_STATUS IgnoredSts; - PSTATE_LEVELING *PStateBufferPtr; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - UINT32 MaxState; - UINT8 IgnoredByte; - - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - PopulatedSockets = 1; - PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc; - - NumberOfSockets = GetPlatformNumberOfSockets (); - IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts); - - PStateStrucPtr->SizeOfBytes = sizeof (S_CPU_AMD_PSTATE); - - MaxState = 0; - FamilyServices->GetPstateMaxState (FamilyServices, &MaxState, &IgnoredByte, StdHeader); - - TaskPtr.FuncAddress.PfApTaskI = PStateGather; - // - // Calculate max buffer size in dwords that need to pass to ap task. - // - TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((MaxState + 1) * (SIZE_IN_DWORDS (S_PSTATE_VALUES))); - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataPtr = PStateBufferPtr; - TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; - - // - //Get P-States and fill the PStateBufferPtr for BSP - // - ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL); - - // - //Calculate next node buffer address - // - PStateBufferPtr->SocketNumber = (UINT8) BscSocket; - PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); - PStateStrucPtr->SizeOfBytes += (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)); - PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); - CpuGetPStateLevelStructure (&PStateBufferPtr, PStateStrucPtr, 1, StdHeader); - // - //Get CPU P-States and fill the PStateBufferPtr for each node(BSC) - // - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (Socket != BscSocket) { - if (IsProcessorPresent (Socket, StdHeader)) { - PopulatedSockets++; - LibAmdMemFill (PStateBufferPtr, 0, sizeof (PSTATE_LEVELING), StdHeader); - TaskPtr.DataTransfer.DataPtr = PStateBufferPtr; - ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader); - PStateBufferPtr->SocketNumber = (UINT8) Socket; - // - //Calculate next node buffer address - // - PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); - PStateStrucPtr->SizeOfBytes += PStateBufferPtr->PStateLevelingSizeOfBytes; - PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); - } - } - } - PStateStrucPtr->TotalSocketInSystem = PopulatedSockets; - - return AGESA_SUCCESS; -} -/**-------------------------------------------------------------------------------------- - * - * PStateGather - * - * Description: - * This is the common routine run on each BSC for gathering Pstate data. - * - * Parameters: - * @param[in,out] *PStateBuffer - * @param[in] *StdHeader - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -PStateGather ( - IN OUT VOID *PStateBuffer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 k; - UINT32 IddVal; - UINT32 IddDiv; - UINT32 NodeNum; - UINT32 CoreNum; - UINT32 TempVar_c; - UINT32 TotalEnabledPStates; - UINT32 SwPstate; - UINT8 BoostStates; - PCI_ADDR PciAddress; - PSTATE_LEVELING *PStateBufferPtr; - BOOLEAN PStateEnabled; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - UINT32 Socket; - AGESA_STATUS IgnoredSts; - CPUID_DATA CpuId; - - PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer; - TotalEnabledPStates = 0; - FamilyServices = NULL; - PStateEnabled = FALSE; - - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - // - /// Sockets number: code looking at PStateBufferPtr->TotalCoresInNode - /// needs to know it is Processor (or socket) core count and NOT a Node Core count. - GetActiveCoresInCurrentSocket (&CoreNum, StdHeader); - PStateBufferPtr->TotalCoresInNode = (UINT8) CoreNum; - - // - // Assume current CoreNum always zero.(BSC) - // - GetCurrentNodeAndCore (&NodeNum, &CoreNum, StdHeader); - - PStateBufferPtr->CreateAcpiTables = 1; - - // - // We need to know the max pstate state in this socket. - // - FamilyServices->GetPstateMaxState (FamilyServices, &TempVar_c, &BoostStates, StdHeader); - PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue = (UINT8) TempVar_c; - PStateBufferPtr->PStateCoreStruct[0].NumberOfBoostedStates = BoostStates; - - for (k = 0; k <= TempVar_c; k++) { - // Check if PState is enabled - FamilyServices->GetPstateRegisterInfo ( FamilyServices, - k, - &PStateEnabled, - &IddVal, - &IddDiv, - &SwPstate, - StdHeader); - - LibAmdMemFill (&(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k]), 0, sizeof (S_PSTATE_VALUES), StdHeader); - - if (PStateEnabled) { - FamilyServices->GetPstateFrequency ( - FamilyServices, - (UINT8) k, - &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq), - StdHeader); - - FamilyServices->GetPstatePower ( - FamilyServices, - (UINT8) k, - &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].Power), - StdHeader); - - PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddValue = IddVal; - PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddDiv = IddDiv; - PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber = SwPstate; - - PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 1; - TotalEnabledPStates++; - } - } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++) - - // Don't create ACPI Tables if there is one or less than one PState is enabled - if (TotalEnabledPStates <= 1) { - PStateBufferPtr[0].CreateAcpiTables = 0; - } - - //--------------------Check Again-------------------------------- - - IdentifyCore (StdHeader, &Socket, &NodeNum, &CoreNum, &IgnoredSts); - // Get the PCI address of internal die 0 as it is the only die programmed. - GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG; - TempVar_c = 0; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader); - PStateBufferPtr->PStateCoreStruct[0].HtcCapable = - (UINT8) ((TempVar_c & 0x00000400) >> 10); // Bit 10 - - TempVar_c = 0; - PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader); - PStateBufferPtr->PStateCoreStruct[0].HtcPstateLimit = - (UINT8) ((TempVar_c & 0x70000000) >> 28); // Bits 30:28 - - // Get LocalApicId from CPUID Fn0000_0001_EBX - LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader); - PStateBufferPtr->PStateCoreStruct[0].LocalApicId = (UINT8) ((CpuId.EBX_Reg & 0xFF000000) >> 24); -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.c deleted file mode 100644 index beab9905e1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.c +++ /dev/null @@ -1,221 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU create Pstate HPC mode support code. - * - * Contains code that declares the AGESA CPU Pstate HPC mode related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuApicUtilities.h" -#include "OptionMultiSocket.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFeatures.h" -#include "cpuPstateHpcMode.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUPSTATEHPCMODE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -EnablePstateHpcModeOnAps ( - IN VOID *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE PstateHpcModeFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should P-state HPC mode be enabled - * If PlatformConfig->PStatesInHpcMode is TRUE, return TRUE, otherwise reture FALSE - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE P-state HPC mode is supported. - * @retval FALSE P-state HPC mode cannot be enabled. - * - */ -BOOLEAN -STATIC -IsPstateHpcModeFeatureSupported ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsEnabled; - UINT32 Socket; - PSTATE_HPC_MODE_FAMILY_SERVICES *FamilyServices; - - IsEnabled = TRUE; - - if (PlatformConfig->PStatesInHpcMode) { - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&PstateHpcModeFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); - if (FamilyServices == NULL) { - IsEnabled = FALSE; - break; - } - } - } - } else { - IsEnabled = FALSE; - } - return IsEnabled; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable high performance computing (HPC mode) - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -InitializePstateHpcModeFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - - if (!IsWarmReset (StdHeader)) { - IDS_HDT_CONSOLE (CPU_TRACE, " P-state HPC mode is enabled\n"); - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - TaskPtr.FuncAddress.PfApTaskI = EnablePstateHpcModeOnAps; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = PlatformConfig; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } - - EnablePstateHpcModeOnAps (PlatformConfig, StdHeader); - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * AP task to enable Pstate HPC mode - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -EnablePstateHpcModeOnAps ( - IN VOID *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PSTATE_HPC_MODE_FAMILY_SERVICES *FamilyServices; - - GetFeatureServicesOfCurrentCore (&PstateHpcModeFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - FamilyServices->EnablePstateHpcMode (FamilyServices, - PlatformConfig, - StdHeader); - -} - - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePstateHpcMode = -{ - PstateHpcMode, - (CPU_FEAT_BEFORE_RELINQUISH_AP | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), - IsPstateHpcModeFeatureSupported, - InitializePstateHpcModeFeature -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.h deleted file mode 100644 index d5998061c9..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.h +++ /dev/null @@ -1,99 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Pstate HPC mode Functions declarations. - * - * Contains code that declares the AGESA CPU Pstate HPC mode related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_PSTATE_HPC_MODE_H_ -#define _CPU_PSTATE_HPC_MODE_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -AGESA_FORWARD_DECLARATION (PSTATE_HPC_MODE_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable P-state HPC mode - * - * @param[in] PstateHpcModeService P-state HPC mode services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_PSTATE_HPC_MODE_INIT ( - IN PSTATE_HPC_MODE_FAMILY_SERVICES *PstateHpcModeService, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_PSTATE_HPC_MODE_INIT *PF_PSTATE_HPC_MODE_INIT; - -/** - * Provide the interface to the P-state HPC mode Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _PSTATE_HPC_MODE_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_PSTATE_HPC_MODE_INIT EnablePstateHpcMode; ///< Method: Family specific call to enable P-state HPC mode. -}; -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _CPU_PSTATE_HPC_MODE_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateLeveling.c deleted file mode 100644 index 3c2d7cde33..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateLeveling.c +++ /dev/null @@ -1,1099 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Pstate Leveling Function. - * - * Contains code to level the Pstates in a multi-socket system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - *---------------------------------------------------------------------------- - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionPstate.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "cpuPostInit.h" -#include "Ids.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration; // global user config record -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -PutAllCoreInPState0 ( - IN OUT PSTATE_LEVELING *PStateBufferPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -StartPstateMsrModify ( - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -PutCoreInPState0 ( - IN VOID *PStateBuffer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PStateLevelingStub ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PStateLevelingMain ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -CorePstateRegModify ( - IN VOID *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - - -/** - *--------------------------------------------------------------------------------------- - * - * PStateLeveling - * - * Description: - * This function will populate the PStateBuffer, after doing the PState Leveling - * Note: This function should be called for every core in the system. - * - * Parameters: - * @param[in,out] *PStateStrucPtr - * @param[in] *StdHeader - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateLeveling ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_TESTPOINT (TpProcCpuEntryPstateLeveling, StdHeader); - return ((*(OptionPstatePostConfiguration.PstateLeveling)) (PStateStrucPtr, StdHeader)); - // Note: Split config struct into PEI/DXE halves. This one is PEI. -} - -/**-------------------------------------------------------------------------------------- - * - * PStateLevelingStub - * - * Description: - * This is the default routine for use when the PState option is NOT requested. - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * Parameters: - * @param[in,out] *PStateStrucPtr - * @param[in] *StdHeader - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateLevelingStub ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_UNSUPPORTED; -} - -/**-------------------------------------------------------------------------------------- - * - * PStateLevelingMain - * - * Description: - * This is the common routine for creating the ACPI information tables. - * - * Parameters: - * @param[in,out] *PStateStrucPtr - * @param[in] *StdHeader - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PStateLevelingMain ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 k; - UINT32 m; - UINT32 TotalIterations; - UINT32 LogicalSocketCount; - UINT32 TempVar_a; - UINT32 TempVar_b; - UINT32 TempVar_c; - UINT32 TempVar_d; - UINT32 TempVar_e; - UINT32 TempVar_f; - PCI_ADDR PciAddress; - - UINT32 TempFreqArray[20]; - UINT32 TempPowerArray[20]; - UINT32 TempIddValueArray[20]; - UINT32 TempIddDivArray[20]; - UINT32 TempSocketPiArray[20]; - UINT32 TempSwP0Array[MAX_SOCKETS_SUPPORTED]; - - BOOLEAN TempFlag1; - BOOLEAN TempFlag2; - BOOLEAN TempFlag3; - BOOLEAN TempFlag4; - BOOLEAN AllCoresHaveHtcCapEquToZeroFlag; - BOOLEAN AllCoreHaveMaxOnePStateFlag; - BOOLEAN PstateMaxValEquToPstateHtcLimitFlag; - BOOLEAN AtLeastOneCoreHasPstateHtcLimitEquToOneFlag; - BOOLEAN PstateMaxValMinusHtcPstateLimitLessThan2Flag; - PSTATE_LEVELING *PStateBufferPtr; - PSTATE_LEVELING *PStateBufferPtrTmp; - UINT32 MaxPstateInNode; - AGESA_STATUS Status; - - TempFlag1 = FALSE; - TempFlag2 = FALSE; - TempFlag3 = FALSE; - TempFlag4 = FALSE; - AllCoresHaveHtcCapEquToZeroFlag = FALSE; - AllCoreHaveMaxOnePStateFlag = FALSE; - PstateMaxValEquToPstateHtcLimitFlag = FALSE; - AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = FALSE; - PstateMaxValMinusHtcPstateLimitLessThan2Flag = FALSE; - PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc; - Status = AGESA_SUCCESS; - - if (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1) { - PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE; - PStateBufferPtr[0].InitStruct = 1; - return AGESA_UNSUPPORTED; - } - - LogicalSocketCount = PStateStrucPtr->TotalSocketInSystem; - ASSERT (LogicalSocketCount <= MAX_SOCKETS_SUPPORTED); - - // This section of code will execute only for "core 0" i.e. BSP - // Read P-States of all the cores. - if (PStateBufferPtr[0].InitStruct == 0) { - // Determine 'software' P0 indices for each socket - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempSwP0Array[i] = (UINT32) (PStateBufferPtrTmp->PStateCoreStruct[0].NumberOfBoostedStates); - } - - // Check if core frequency and power are same across all sockets. - TempFlag1 = FALSE; - for (i = 1; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue != PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue)) { - TempFlag1 = TRUE; - break; - } - MaxPstateInNode = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; - for (k = TempSwP0Array[i]; k <= MaxPstateInNode; k++) { - if ((PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].CoreFreq != - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq) || - (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].Power != - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].Power)) { - TempFlag1 = TRUE; - break; // Come out of the inner FOR loop - } - } - if (TempFlag1) { - break; // Come out of the outer FOR loop - } - } - - if (!TempFlag1) { - // No need to do pStateLeveling, or writing to pState MSR registers - // if all CPUs have Identical PStates - PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE; - PStateBufferPtr[0].InitStruct = 1; - PutAllCoreInPState0 (PStateBufferPtr, StdHeader); - return AGESA_UNSUPPORTED; - } else { - PStateBufferPtr[0].AllCpusHaveIdenticalPStates = FALSE; - } - - // 1_b) & 1_c) - TempFlag1 = FALSE; - TempFlag2 = FALSE; - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == TempSwP0Array[i]) { - TempFlag1 = TRUE; - } else { - TempFlag2 = TRUE; - } - if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcCapable == 0) { - TempFlag3 = TRUE; - } else { - TempFlag4 = TRUE; - } - - if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - - PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) < 2) { - PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE; - } - - if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == - PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) { - PstateMaxValEquToPstateHtcLimitFlag = TRUE; - } - - if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) { - AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE; - } - } - - // Do general setup of flags, that we may use later - // Implementation of (1_b) - if (TempFlag1 && TempFlag2) { - // - //Processors with only one enabled P-state (F3xDC[PstateMaxVal]=000b) cannot be mixed in a system with - //processors with more than one enabled P-state (F3xDC[PstateMaxVal]!=000b). - // - PStateBufferPtr[0].InitStruct = 1; - PStateBufferPtr[0].CreateAcpiTables = 0; - PutAllCoreInPState0 (PStateBufferPtr, StdHeader); - return AGESA_UNSUPPORTED; - } else if (TempFlag1 && !TempFlag2) { - // - //all processors have only 1 enabled P-state - // - AllCoreHaveMaxOnePStateFlag = TRUE; - PStateBufferPtr[0].OnlyOneEnabledPState = TRUE; - } - - // Processors with F3xE8[HTC_CAPABLE] = 1 can not be - // mixed in system with processors with F3xE8[HTC_CAPABLE] = 0. - if (TempFlag3 && TempFlag4) { - PStateBufferPtr[0].InitStruct = 1; - PStateBufferPtr[0].CreateAcpiTables = 0; - PutAllCoreInPState0 (PStateBufferPtr, StdHeader); - return AGESA_UNSUPPORTED; - } - - if (TempFlag3) { - // - //If code run to here means that all processors do not have HTC_CAPABLE. - // - AllCoresHaveHtcCapEquToZeroFlag = TRUE; - } - - //-------------------------------------------------------------------------------- - // S T E P - 2 - //-------------------------------------------------------------------------------- - // Now run the PState Leveling Algorithm which will create mixed CPU P-State - // Tables. - // Follow the algorithm in the latest BKDG - // ------------------------------------------------------------------------------- - // Match P0 CPU COF for all CPU cores to the lowest P0 CPU COF value in the - // coherent fabric, and match P0 power for all CPU cores to the highest P0 power - // value in the coherent fabric. - // 2_a) If all processors have only 1 enabled P-State BIOS must write the - // appropriate CpuFid value resulting from the matched CPU COF to all - // copies of MSRC001_0070[CpuFid], and exit the sequence (No further - // steps are executed) - //-------------------------------------------------------------------------------- - // Identify the lowest P0 Frequency and maximum P0 Power - TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].CoreFreq; - TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].Power; - TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].IddValue; - TempVar_b = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].IddDiv; - - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq) { - TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq; - } - - if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power) { - TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power; - TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddValue; - TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddDiv; - } - } - - // Set P0 Frequency and Power for all CPUs - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq = TempVar_d; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power = TempVar_e; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddValue = TempVar_a; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddDiv = TempVar_b; - } - - // 2_a) - if (!AllCoreHaveMaxOnePStateFlag) { - //-------------------------------------------------------------------------- - // STEP - 3 - //-------------------------------------------------------------------------- - // Match the CPU COF and power for P-states used by HTC. Skip to step 4 - // is any processor reports F3xE8[HTC_Capable] = 0; - // 3_a) Set F3x64[HtcPstateLimit] = 001b and F3x68[StcPstateLimit] = 001b for - // processors with F3x64[HtcPstateLimit] = 000b. - // 3_b) Identify the lowest CPU COF for all processors in the P-state - // pointed to by [The Hardware Thermal Control (HTC) Register] - // F3x64[HtcPstateLimit] - // 3_c) Modify the CPU COF pointed to by [The Hardware Thermal Control - // (HTC) Register] F3x64[HtcPstateLimit] for all processors to the - // previously identified lowest CPU COF value. - // 3_d) Identify the highest power for all processors in the P-state - // pointed to by [The Hardware Thermal Control (HTC) Register] - // F3x64[HtcPstateLimit]. - // 3_e) Modify the power pointed to by [The Hardware Thermal Control (HTC) - // Register] F3x64[HtcPstateLimit] to the previously identified - // highest power value. - if (!AllCoresHaveHtcCapEquToZeroFlag) { - // 3_a) - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 0) { - // To Be Done (Set Htc and Stc PstateLimit values) - // for this CPU (using PCI address space) - for (k = 0; k < (UINT8)GetPlatformNumberOfModules (); k++) { - if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, k, &PciAddress, &Status)) { - // Set F3x64[HtcPstateLimit] = 001b - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - // Bits 30:28 - TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - - // Set F3x68[StcPstateLimit] = 001b - PciAddress.Address.Register = SOFTWARE_THERMAL_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - // Bits 28:30 - TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - } - } - // Set LocalBuffer - PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit = 1; - if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1) < 2) { - PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE; - } - - if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == 1) { - PstateMaxValEquToPstateHtcLimitFlag = TRUE; - } - } - - if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) { - AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE; - } - } - - // 3_b) and 3_d) - TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit; - TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq; - TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power; - TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue; - TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv; - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - for (k = 0; k < 1; k++) { - TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; - if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) { - TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq; - } - - if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) { - TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power; - TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue; - TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv; - } - } - } - - // 3_c) and 3_e) - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c; - } - } // if(AllCoresHaveHtcCapEquToZeroFlag) - - - //-------------------------------------------------------------------------- - // STEP - 4 - //-------------------------------------------------------------------------- - // Match the CPU COF and power for the lowest performance P-state: - // 4_a) If F3xDC[PstateMaxVal] = F3x64[HtcPstateLimit] for any processor, - // set PstateEn = 0 for all the P-states greater than - // F3x64[HtcPstateLimit] for all processors. - // 4_b) Identify the lowest CPU COF for all processors in the P-state - // pointed to by F3xDC[PstateMaxVal]. - // 4_c) Modify the CPU COF for all processors in the P-state pointed to by - // F3xDC[PstateMaxVal] to the previously identified lowest CPU COF - // value. - // 4_d) Identify the highest power for all processors in the P-state - // pointed to by F3xDC[PstateMaxVal]. - // 4_e) Modify the power for all processors in the P-state pointed to by - // F3xDC[PstateMaxVal] to the previously identified highest power - // value. - - // 4_a) - if (PstateMaxValEquToPstateHtcLimitFlag) { - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit + 1; - for (k = TempVar_b; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++) { - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; - } - //-------------------------------------------------------------------------- - // STEP - 5 - //-------------------------------------------------------------------------- - // 5_a) Modify F3xDC[PstateMaxVal] to indicate the lowest performance - // P-state with PstateEn set for each processor (Step 4 can disable - // P-states pointed to by F3xDC[PstateMaxVal]) - - // Use this value of HtcPstateLimit to program the - // F3xDC[pStateMaxValue] - TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; - TempVar_e <<= 8; - // Bits 10:8 - - for (m = 0; m < (UINT8)GetPlatformNumberOfModules (); m++) { - if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, m, &PciAddress, &Status)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - TempVar_d = (TempVar_d & 0xFFFFF8FF) | TempVar_e; - LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader); - } - }//End of step 5 - } - }// End of 4_a) - - // 4_b) and 4_d) - TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue; - TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq; - TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power; - TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue; - TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv; - - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; - if (TempVar_d > - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) { - TempVar_d = - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq; - } - - if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) { - TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power; - TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue; - TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv; - } - } - - // 4_c) and 4_e) - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c; - } - - - //-------------------------------------------------------------------------- - // STEP - 6 - //-------------------------------------------------------------------------- - // Match the CPU COF and power for upper intermediate performance - // P-state(s): - // Upper intermediate PStates = PStates between (Not including) P0 and - // F3x64[HtcPstateLimit] - // 6_a) If F3x64[HtcPstateLimit] = 001b for any processor, set PstateEn = 0 - // for enabled upper intermediate P-states for all processors with - // F3x64[HtcPstateLimit] > 001b and skip the remaining actions for - // this numbered step. - // 6_b) Define each of the available upper intermediate P-states; for each - // processor concurrently evaluate the following loop; when any - // processor falls out of the loop (runs out of available upper - // intermediate Pstates) all other processors have their remaining - // upper intermediate P-states invalidated (PstateEn = 0); - // for (i = F3x64[HtcPstateLimit] - 1; i > 0; i--) - // - Identify the lowest CPU COF for P(i). - // - Identify the highest power for P(i). - // - Modify P(i) CPU COF for all processors to the previously - // identified lowest CPU COF value. - // - Modify P(i) power for all processors to the previously - // identified highest power value. - - // 6_a) - if (AtLeastOneCoreHasPstateHtcLimitEquToOneFlag) { - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - for (k = TempSwP0Array[i] + 1; k < (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit); k++) { - if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit > 1) { - // Make a function call to clear the - // structure values - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; - } - } - } - } - // 6_b) - else { - // Identify Lowest Frequency and Highest Power - TotalIterations = 0; - TempFlag1 = TRUE; - - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit - 1; - } - - do { - //For first socket, try to find a candidate - if (TempSocketPiArray[0] != TempSwP0Array[0]) { - while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) { - TempSocketPiArray[0] = TempSocketPiArray[0] - 1; - if (TempSocketPiArray[0] == TempSwP0Array[0]) { - TempFlag1 = FALSE; - break; - } - } - } else { - TempFlag1 = FALSE; - } - if (TempFlag1) { - TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq; - TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power; - TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue; - TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv; - - //Try to find next candidate - for (i = 1; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (TempSocketPiArray[i] != TempSwP0Array[i]) { - while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) { - TempSocketPiArray[i]--; - if (TempSocketPiArray[i] == TempSwP0Array[i]) { - TempFlag1 = FALSE; - break; - } - }//end while - } else { - TempFlag1 = FALSE; - } - - } //end for LogicalSocketCount - } - - if (TempFlag1) { - for (i = 0; i < LogicalSocketCount; i++) { - // - //Compare - // - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) { - TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq; - } - - if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) { - TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power; - TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue; - TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv; - } - } - // Modify (Pi) CPU COF and Power for all the CPUs - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power = TempPowerArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv = TempIddDivArray[TotalIterations]; - TempSocketPiArray[i] = TempSocketPiArray[i] - 1; - } - } else { - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - for (m = TempSocketPiArray[i]; m > TempSwP0Array[i]; m--) { - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0; - } - } - } - - TotalIterations++; - } while (TempFlag1); - - } // else - - //-------------------------------------------------------------------------- - // STEP - 7 - //-------------------------------------------------------------------------- - // Match the CPU COF and power for lower intermediate performance P - state(s) - // Lower Intermediate Pstates = Pstates between (not including) - // F3x64[HtcPstateLimit] and F3xDC[PstateMaxVal] - // 7_a) If F3xDC[PstateMaxVal] - F3x64[HtcPstateLimit] < 2 for any - // processor, set PstateEn = 0 for enabled lower intermediate P - states - // for all processors with (F3xDC[PstateMaxVal] - - // F3x64[HtcPstateLimit] > 1) and skip the remaining actions for this - // numbered step. - // 7_b) Define each of the available lower intermediate P-states; for each - // processor concurrently evaluate the following loop; when any - // processor falls out of the loop (runs out of available lower - // intermediate Pstates) all other processors have their remaining - // lower intermediate P-states invalidated (PstateEn = 0); - // for (i = F3xDC[PstateMaxVal]-1; i > F3x64[HtcPstateLimit]; i--) - // - Identify the lowest CPU COF for P-states between - // (not including) F3x64[HtcPstateLimit] and P(i). - // - Identify the highest power for P-states between - // (not including) F3x64[HtcPstateLimit] and P(i). - // - Modify P(i) CPU COF for all processors to the previously - // identified lowest CPU COF value. - // - Modify P(i) power for all processors to the previously - // identified highest power value. - - - // 7_a) - if (PstateMaxValMinusHtcPstateLimitLessThan2Flag) { - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - - for (k = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1; - k > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; - k--) { - if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - - PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) > 1) { - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; - } - } - } - } - - // 7_b) - else { - // Identify Lowest Frequency and Highest Power - - TotalIterations = 0; - TempFlag1 = TRUE; - - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1; - } - - do { - //For first socket, try to find a candidate - if (TempSocketPiArray[0] != PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) { - while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) { - TempSocketPiArray[0] = TempSocketPiArray[0] - 1; - if (TempSocketPiArray[0] == PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) { - TempFlag1 = FALSE; - break; - } - } - } else { - TempFlag1 = FALSE; - } - if (TempFlag1) { - TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq; - TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power; - TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue; - TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv; - - //Try to find next candidate - for (i = 1; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (TempSocketPiArray[i] != PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) { - while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) { - TempSocketPiArray[i]--; - if (TempSocketPiArray[i] == PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) { - TempFlag1 = FALSE; - break; - } - }//end while - } else { - TempFlag1 = FALSE; - } - } //end for LogicalSocketCount - } - - if (TempFlag1) { - for (i = 0; i < LogicalSocketCount; i++) { - // - //Compare - // - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) { - TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq; - } - if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) { - TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power; - TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue; - TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv; - } - } - // Modify (Pi) CPU COF and Power for all the CPUs - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power = TempPowerArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations]; - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv = TempIddDivArray[TotalIterations]; - TempSocketPiArray[i] = TempSocketPiArray[i] - 1; - } - } else { - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); - for (m = TempSocketPiArray[i]; m > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; m--) { - PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0; - } - } - } - TotalIterations++; - } while (TempFlag1); - } // else - } // if(!AllCoreHaveMaxOnePStateFlag) - - PStateBufferPtr[0].InitStruct = 1; - } // CurrentCore - - - // Update the pState MSRs - // This can be done only by individual core - StartPstateMsrModify (PStateStrucPtr, StdHeader); - - //---------------------------------------------------------------------------------- - // STEP - 8 - //---------------------------------------------------------------------------------- - // Place all cores into a valid COF and VID configuration corresponding to an - // enabled P-state: - // 8_a) Select an enabled P-state != to the P-state pointed to by - // MSRC001_0063[CurPstate] for each core. - // 8_b) Transition all cores to the selected P-states by writing the Control value - // from the_PSS object corresponding to the selected P-state to - // MSRC001_0062[PstateCmd]. - // 8_c) Wait for all cores to report the Status value from the _PSS object - // corresponding to the selected P-state in MSRC001_0063[CurPstate]. - // - PutAllCoreInPState0 (PStateBufferPtr, StdHeader); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/** - *--------------------------------------------------------------------------------------- - * - * PutAllCoreInPState0 - * - * Description: - * This function will put core pstate to p0. - * - * Parameters: - * @param[in,out] *PStateBufferPtr - * @param[in] *StdHeader - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -PutAllCoreInPState0 ( - IN OUT PSTATE_LEVELING *PStateBufferPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AGESA_STATUS IgnoredSts; - - TaskPtr.FuncAddress.PfApTaskI = PutCoreInPState0; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PSTATE_LEVELING); - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataPtr = PStateBufferPtr; - TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - PutCoreInPState0 (PStateBufferPtr, StdHeader); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } - - return AGESA_SUCCESS; -} - -/** - *--------------------------------------------------------------------------------------- - * - * CorePstateRegModify - * - * Description: - * This function will setting the Pstate MSR to each APs base on Pstate Buffer. - * Note: This function should be called for every core in the system. - * - * Parameters: - * @param[in,out] *CpuAmdPState - * @param[in] *StdHeader - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -CorePstateRegModify ( - IN VOID *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PSTATE_CPU_FAMILY_SERVICES *FamilySpecificServices; - FamilySpecificServices = NULL; - - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL) - FamilySpecificServices->SetPStateLevelReg (FamilySpecificServices, (S_CPU_AMD_PSTATE *) CpuAmdPState, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will set msr on all cores of all nodes. - * - * @param[in] CpuAmdPState Pointer to S_CPU_AMD_PSTATE. - * @param[in] StdHeader Header for library and services. - * - * @retval AGESA_SUCCESS Always succeeds - * - */ -AGESA_STATUS -StartPstateMsrModify ( - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AGESA_STATUS IgnoredSts; - - TaskPtr.FuncAddress.PfApTaskI = CorePstateRegModify; - TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) (CpuAmdPState->SizeOfBytes / 4 + 1); - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataPtr = CpuAmdPState; - TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - CorePstateRegModify (CpuAmdPState, StdHeader); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } - - return AGESA_SUCCESS; -} - - -/** - *--------------------------------------------------------------------------------------- - * - * CpuGetPStateLevelStructure - * - * Description: - * Based on the LogicalSocketNumber, this function will return a pointer - * point to the accurate offset of the PSTATE_LEVELING structure. - * - * Parameters: - * @param[in,out] *PStateBufferPtr - * @param[in] *CpuAmdPState - * @param[in] LogicalSocketNumber - * @param[in] *StdHeader - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -CpuGetPStateLevelStructure ( - OUT PSTATE_LEVELING **PStateBufferPtr, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN UINT32 LogicalSocketNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PSTATE_LEVELING *PStateBufferPtrTmp; - UINT32 i; - - if (LogicalSocketNumber > CpuAmdPState->TotalSocketInSystem) { - return AGESA_UNSUPPORTED; - } - - PStateBufferPtrTmp = CpuAmdPState->PStateLevelingStruc; - - for (i = 1; i <= LogicalSocketNumber; i++) { - PStateBufferPtrTmp = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtrTmp + ((UINTN) PStateBufferPtrTmp->PStateLevelingSizeOfBytes)); - } - - *PStateBufferPtr = PStateBufferPtrTmp; - - return AGESA_SUCCESS; -} - - -/** - *--------------------------------------------------------------------------------------- - * - * PutCoreInPState0 - * - * Description: - * This function will take the CPU core into P0 - * - * Parameters: - * @param[in] *PStateBuffer - * @param[in] *StdHeader - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -STATIC -PutCoreInPState0 ( - IN VOID *PStateBuffer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PSTATE_LEVELING *PStateBufferPtr; - - PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer; - - if ((PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1 ) || - (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_2)) { - return; - } - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateTables.c deleted file mode 100644 index a1af313963..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateTables.c +++ /dev/null @@ -1,889 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD PSTATE, ACPI table related API functions. - * - * Contains code that generates the _PSS, _PCT, and other ACPI tables. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionPstate.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "heapManager.h" -#include "Ids.h" -#include "Filecode.h" -#include "GeneralServices.h" -#include "cpuPstateTables.h" -#include "cpuFeatures.h" -#include "cpuIoCstate.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration; // global user config record -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; -extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; - -STATIC ACPI_TABLE_HEADER ROMDATA CpuSsdtHdrStruct = -{ - {'S','S','D','T'}, - 0, - 1, - 0, - {'A','M','D',' ',' ',' '}, - {'P','O','W','E','R','N','O','W'}, - 1, - {'A','M','D',' '}, - 1 -}; - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -UINT32 -STATIC -CalAcpiTablesSize ( - IN S_CPU_AMD_PSTATE *AmdPstatePtr, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GenerateSsdtStub ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SsdtPtr - ); - -UINT32 -CreateAcpiTablesStub ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -CreatePStateAcpiTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -CreateCStateAcpiTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GenerateSsdt ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SsdtPtr - ); - -/** - *--------------------------------------------------------------------------------------- - * - * CalAcpiTablesSize - * - * Description: - * This function will calculate the size of ACPI PState tables - * - * Parameters: - * @param[in] *AmdPstatePtr - * @param[in] *PlatformConfig - * @param[in] *StdHeader - * - * @retval UINT32 - * - *--------------------------------------------------------------------------------------- - */ -UINT32 -STATIC -CalAcpiTablesSize ( - IN S_CPU_AMD_PSTATE *AmdPstatePtr, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ScopeSize; - UINT32 CoreCount; - UINT32 SocketCount; - UINT32 MaxCoreNumberInCurrentSocket; - UINT32 MaxSocketNumberInSystem; - UINT32 MaxPstateNumberInCurrentCore; - UINT32 CstateAcpiObjSize; - PSTATE_LEVELING *PStateLevelingBufferStructPtr; - IO_CSTATE_FAMILY_SERVICES *IoCstateFamilyServices; - - ScopeSize = sizeof (ACPI_TABLE_HEADER); - CstateAcpiObjSize = 0; - IoCstateFamilyServices = NULL; - - PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc; - MaxSocketNumberInSystem = AmdPstatePtr->TotalSocketInSystem; - - if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) { - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&IoCstateFamilyServices, StdHeader); - // If we're supporting multiple families, only proceed when IO Cstate family services are available - if (IoCstateFamilyServices != NULL) { - CstateAcpiObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader); - } - } - - for (SocketCount = 0; SocketCount < MaxSocketNumberInSystem; SocketCount++) { - MaxCoreNumberInCurrentSocket = PStateLevelingBufferStructPtr->TotalCoresInNode; - for (CoreCount = 0; CoreCount < MaxCoreNumberInCurrentSocket; CoreCount++) { - MaxPstateNumberInCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue + 1; - - ScopeSize += (SCOPE_STRUCT_SIZE - 1); // Scope size per core - ScopeSize += CstateAcpiObjSize; // C-State ACPI objects size per core - - // Add P-State ACPI Objects size per core - if ((PStateLevelingBufferStructPtr[0].CreateAcpiTables != 0) && (PlatformConfig->UserOptionPState)) { - ScopeSize += (PCT_STRUCT_SIZE + - PSS_HEADER_STRUCT_SIZE + - (MaxPstateNumberInCurrentCore * PSS_BODY_STRUCT_SIZE) + - XPSS_HEADER_STRUCT_SIZE + - (MaxPstateNumberInCurrentCore * XPSS_BODY_STRUCT_SIZE) + - PSD_HEADER_STRUCT_SIZE + - PSD_BODY_STRUCT_SIZE + - PPC_HEADER_BODY_STRUCT_SIZE); - } - } - ScopeSize += MaxCoreNumberInCurrentSocket; - PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); - } - AmdPstatePtr->SizeOfBytes = ScopeSize; - - return ScopeSize; -} - -/**-------------------------------------------------------------------------------------- - * - * GenerateSsdtStub - * - * Description: - * This is the default routine for use when both PState and CState option is NOT - * requested. The option install process will create and fill the transfer vector - * with the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * Parameters: - * @param[in] StdHeader Handle to config for library and services - * @param[in] PlatformConfig Contains the power cap parameter - * @param[in,out] SsdtPtr ACPI SSDT table pointer - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -GenerateSsdtStub ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SsdtPtr - ) -{ - return AGESA_UNSUPPORTED; -} - -/** - *--------------------------------------------------------------------------------------- - * - * GenerateSsdt - * - * Description: - * This function will populate the SSDT with ACPI P-States and C-States Objects, whenever - * necessary - * This function should be called only from BSP - * - * Parameters: - * @param[in] StdHeader Handle to config for library and services - * @param[in] PlatformConfig Contains the power cap parameter - * @param[in,out] SsdtPtr ACPI SSDT pointer - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GenerateSsdt ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SsdtPtr - ) -{ - UINT32 i; - UINT32 j; - UINT32 TempVar8_a; - UINT32 CurrSize; - UINT32 TempVar_a; - UINT32 TempVar_b; - UINT32 ScopeSize; - UINT32 CoreCount; - UINT32 SocketCount; - UINT32 MaxCorePerNode; - UINT8 LocalApicId; - UINT8 *IntermediatePtr; - AGESA_STATUS AgesaStatus; - LOCATE_HEAP_PTR LocateHeapParams; - ALLOCATE_HEAP_PARAMS AllocateHeapParams; - S_CPU_AMD_PSTATE *AmdPstatePtr; - PSTATE_LEVELING *PStateLevelingBufferStructPtr; - SCOPE *ScopeAcpiTablesStructPtr; - SCOPE *ScopeAcpiTablesStructPtrTemp; - - AGESA_TESTPOINT (TpProcCpuEntryPstate, StdHeader); - - ASSERT (IsBsp (StdHeader, &AgesaStatus)); - - // If P-State and C-State ACPI tables do not need to be generated, exit this routine - if ((!PlatformConfig->UserOptionPState) && (!IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader))) { - AgesaStatus = AGESA_UNSUPPORTED; - return AgesaStatus; - } - - // Initialize data variables - ScopeSize = 0; - CoreCount = 0; - LocalApicId = 0; - CurrSize = 0; - - // Locate P-State data buffer - LocateHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE; - AGESA_TESTPOINT (TpProcCpuBeforeLocateSsdtBuffer, StdHeader); - if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpProcCpuAfterLocateSsdtBuffer, StdHeader); - - AmdPstatePtr = (S_CPU_AMD_PSTATE *) LocateHeapParams.BufferPtr; - PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc; - - // Allocate rough buffer for AcpiTable, if SsdtPtr is NULL - if (*SsdtPtr == NULL) { - //Do not know the actual size.. pre-calculate it. - AllocateHeapParams.RequestedBufferSize = CalAcpiTablesSize (AmdPstatePtr, PlatformConfig, StdHeader); - AllocateHeapParams.BufferHandle = AMD_PSTATE_ACPI_BUFFER_HANDLE; - AllocateHeapParams.Persist = HEAP_SYSTEM_MEM; - - AGESA_TESTPOINT (TpProcCpuBeforeAllocateSsdtBuffer, StdHeader); - if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpProcCpuAfterAllocateSsdtBuffer, StdHeader); - *SsdtPtr = AllocateHeapParams.BufferPtr; - } - - IDS_HDT_CONSOLE (CPU_TRACE, " SSDT is created\n"); - - // Copy SSDT header into allocated buffer - LibAmdMemCopy (*SsdtPtr, (VOID *) &CpuSsdtHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader); - IntermediatePtr = (UINT8 *) *SsdtPtr; - ScopeAcpiTablesStructPtr = (SCOPE *) &IntermediatePtr[sizeof (ACPI_TABLE_HEADER)]; - - SocketCount = AmdPstatePtr->TotalSocketInSystem; - - // Generate name scope and ACPI objects for every core in the system - for (i = 0; i < SocketCount; i++) { - MaxCorePerNode = PStateLevelingBufferStructPtr->TotalCoresInNode; - for (j = 0; j < MaxCorePerNode; j++) { - CoreCount++; - // Set Name Scope for CPU0, 1, 2, ..... n - // CPU0 to CPUn will name as C000 to Cnnn - // ----------------------------------------- - ScopeAcpiTablesStructPtr->ScopeOpcode = SCOPE_OPCODE; - // This value will be filled at the end of this function - // Since at this time, we don't know how many Pstates we - // would have - ScopeAcpiTablesStructPtr->ScopeLength = 0; - ScopeAcpiTablesStructPtr->ScopeValue1 = SCOPE_VALUE1; - ScopeAcpiTablesStructPtr->ScopeValue2 = SCOPE_VALUE2; - ScopeAcpiTablesStructPtr->ScopeNamePt1a__ = SCOPE_NAME__; - if (PlatformConfig->ProcessorScopeInSb) { - ScopeAcpiTablesStructPtr->ScopeNamePt1a_P = SCOPE_NAME_S; - ScopeAcpiTablesStructPtr->ScopeNamePt1a_R = SCOPE_NAME_B; - } else { - ScopeAcpiTablesStructPtr->ScopeNamePt1a_P = SCOPE_NAME_P; - ScopeAcpiTablesStructPtr->ScopeNamePt1a_R = SCOPE_NAME_R; - } - ScopeAcpiTablesStructPtr->ScopeNamePt1b__ = SCOPE_NAME__; - ASSERT ((PlatformConfig->ProcessorScopeName0 >= 'A') && (PlatformConfig->ProcessorScopeName0 <= 'Z')) - ASSERT (((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z')) || \ - ((PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9')) || \ - (PlatformConfig->ProcessorScopeName1 == '_')) - - ScopeAcpiTablesStructPtr->ScopeNamePt2a_C = PlatformConfig->ProcessorScopeName0; - ScopeAcpiTablesStructPtr->ScopeNamePt2a_P = PlatformConfig->ProcessorScopeName1; - - TempVar8_a = ((CoreCount - 1) >> 4) & 0x0F; - ScopeAcpiTablesStructPtr->ScopeNamePt2a_U = (UINT8) (SCOPE_NAME_0 + TempVar8_a); - - TempVar8_a = (CoreCount - 1) & 0x0F; - if (TempVar8_a < 0xA) { - ScopeAcpiTablesStructPtr->ScopeNamePt2a_0 = (UINT8) (SCOPE_NAME_0 + TempVar8_a); - } else { - ScopeAcpiTablesStructPtr->ScopeNamePt2a_0 = (UINT8) (SCOPE_NAME_A + TempVar8_a - 0xA); - } - // Increment and typecast the pointer - ScopeAcpiTablesStructPtrTemp = ScopeAcpiTablesStructPtr; - ScopeAcpiTablesStructPtrTemp++; - - // Get the Local Apic Id for each core - LocalApicId = PStateLevelingBufferStructPtr->PStateCoreStruct[0].LocalApicId + (UINT8) j; - - // Create P-State ACPI Objects - CurrSize += ((*(OptionPstateLateConfiguration.PstateFeature)) (PlatformConfig, PStateLevelingBufferStructPtr, (VOID *) &ScopeAcpiTablesStructPtrTemp, LocalApicId, StdHeader)); - - // Create C-State ACPI Objects - CurrSize += ((*(OptionPstateLateConfiguration.CstateFeature)) (PlatformConfig, PStateLevelingBufferStructPtr, (VOID *) &ScopeAcpiTablesStructPtrTemp, LocalApicId, StdHeader)); - - // Now update the SCOPE Length field - { - CurrSize += (SCOPE_STRUCT_SIZE - 1); - ScopeSize += CurrSize; - - TempVar_b = ((CurrSize << 4) & 0x0000FF00); - TempVar_b |= ((CurrSize & 0x0000000F) | 0x00000040); - TempVar_a = TempVar_b; - ScopeAcpiTablesStructPtr->ScopeLength = (UINT16) TempVar_a; - CurrSize = 0; - } - - ScopeAcpiTablesStructPtr = ScopeAcpiTablesStructPtrTemp; - } - //Calculate next node buffer address - PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); - } - //Update SSDT header Checksum - ((ACPI_TABLE_HEADER *) *SsdtPtr)->TableLength = (ScopeSize + CoreCount + sizeof (ACPI_TABLE_HEADER)); - ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SsdtPtr, StdHeader); - - return AGESA_SUCCESS; -} - -/**-------------------------------------------------------------------------------------- - * - * CreateAcpiTablesStub - * - * Description: - * This is the default routine for use when the P-State or C-State option is NOT - * requested. The option install process will create and fill the transfer vector - * with the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * Parameters: - * @param[in] PlatformConfig Platform operational characteristics; power cap - * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information - * @param[in,out] SsdtPtr ACPI SSDT table pointer - * @param[in] LocalApicId Local Apic Id - * @param[in] StdHeader Handle to config for library and services - * - * @retval Size of generated ACPI objects - * - *--------------------------------------------------------------------------------------- - **/ -UINT32 -CreateAcpiTablesStub ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return 0; -} - - -/**-------------------------------------------------------------------------------------- - * - * CreatePStateAcpiTables - * - * Description: - * This is the common routine for creating ACPI P-State objects - * - * Parameters: - * @param[in] PlatformConfig Platform operational characteristics; power cap - * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information - * @param[in,out] SsdtPtr ACPI SSDT table pointer - * @param[in] LocalApicId Local Apic Id - * @param[in] StdHeader Handle to config for library and services - * - * @retval Size of generated ACPI P-States objects - * - *--------------------------------------------------------------------------------------- - **/ -UINT32 -CreatePStateAcpiTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PstateCapLevelSupport; - UINT8 PStateMaxValueOnCurrentCore; - BOOLEAN PstateCapEnable; - BOOLEAN PstateCapLevelSupportDetermined; - BOOLEAN IsPsdDependent; - UINT32 k; - UINT32 TempVar_a; - UINT32 TempVar_b; - UINT32 TempVar_c; - UINT32 PstateCapInputMilliWatts; - UINT32 CurrSize; - UINT32 PstateCount; - UINT32 CoreCount1; - UINT32 TransAndBusMastLatency; - AGESA_STATUS IgnoredStatus; - PCI_ADDR PciAddress; - PCT_HEADER_BODY *pPctAcpiTables; - PSS_HEADER *pPssHeaderAcpiTables; - PSS_BODY *pPssBodyAcpiTables; - XPSS_HEADER *pXpssHeaderAcpiTables; - XPSS_BODY *pXpssBodyAcpiTables; - PSD_HEADER *pPsdHeaderAcpiTables; - PSD_BODY *pPsdBodyAcpiTables; - PPC_HEADER_BODY *pPpcAcpiTables; - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - CurrSize = 0; - PstateCount = 0; - PstateCapEnable = FALSE; - PstateCapLevelSupport = DEFAULT_PERF_PRESENT_CAP; - PstateCapLevelSupportDetermined = TRUE; - PstateCapInputMilliWatts = PlatformConfig->PowerCeiling; - IsPsdDependent = !(PlatformConfig->ForcePstateIndependent); - TransAndBusMastLatency = 0; - - if ((PStateLevelingBuffer[0].CreateAcpiTables != 0) && (PlatformConfig->UserOptionPState)) { - pPctAcpiTables = (PCT_HEADER_BODY *) *SsdtPtr; - - //Check Pstate Capability - if (PstateCapInputMilliWatts != 0) { - PstateCapEnable = TRUE; - PstateCapLevelSupportDetermined = FALSE; - } - - PStateMaxValueOnCurrentCore = PStateLevelingBuffer->PStateCoreStruct[0].PStateMaxValue; - if (OptionPstateLateConfiguration.CfgPstatePct) { - // Set _PCT Table - // -------------- - pPctAcpiTables->NameOpcode = NAME_OPCODE; - pPctAcpiTables->PctName_a__ = PCT_NAME__; - pPctAcpiTables->PctName_a_P = PCT_NAME_P; - pPctAcpiTables->PctName_a_C = PCT_NAME_C; - pPctAcpiTables->PctName_a_T = PCT_NAME_T; - pPctAcpiTables->Value1 = PCT_VALUE1; - pPctAcpiTables->Value2 = PCT_VALUE2; - pPctAcpiTables->Value3 = PCT_VALUE3; - pPctAcpiTables->GenericRegDescription1 = GENERIC_REG_DESCRIPTION; - pPctAcpiTables->Length1 = PCT_LENGTH; - pPctAcpiTables->AddressSpaceId1 = PCT_ADDRESS_SPACE_ID; - pPctAcpiTables->RegisterBitWidth1 = PCT_REGISTER_BIT_WIDTH; - pPctAcpiTables->RegisterBitOffset1 = PCT_REGISTER_BIT_OFFSET; - pPctAcpiTables->Reserved1 = PCT_RESERVED; - pPctAcpiTables->ControlRegAddressLo = PCT_CONTROL_REG_LO; - pPctAcpiTables->ControlRegAddressHi = PCT_CONTROL_REG_HI; - pPctAcpiTables->Value4 = PCT_VALUE4; - pPctAcpiTables->Value5 = PCT_VALUE5; - pPctAcpiTables->GenericRegDescription2 = GENERIC_REG_DESCRIPTION; - pPctAcpiTables->Length2 = PCT_LENGTH; - pPctAcpiTables->AddressSpaceId2 = PCT_ADDRESS_SPACE_ID; - pPctAcpiTables->RegisterBitWidth2 = PCT_REGISTER_BIT_WIDTH; - pPctAcpiTables->RegisterBitOffset2 = PCT_REGISTER_BIT_OFFSET; - pPctAcpiTables->Reserved2 = PCT_RESERVED; - pPctAcpiTables->StatusRegAddressLo = PCT_STATUS_REG_LO; - pPctAcpiTables->StatusRegAddressHi = PCT_STATUS_REG_HI; - pPctAcpiTables->Value6 = PCT_VALUE6; - - // Increment and then typecast the pointer - pPctAcpiTables++; - CurrSize += PCT_STRUCT_SIZE; - - *SsdtPtr = pPctAcpiTables; - } // end of OptionPstateLateConfiguration.CfgPstatePct - - pPssHeaderAcpiTables = (PSS_HEADER *) pPctAcpiTables; - pPssBodyAcpiTables = (PSS_BODY *) pPctAcpiTables; - if (OptionPstateLateConfiguration.CfgPstatePss) { - // Set _PSS Header - // Note: Set pssLength and numOfItemsInPss later - //--------------------------------------------------- - pPssHeaderAcpiTables->NameOpcode = NAME_OPCODE; - pPssHeaderAcpiTables->PssName_a__ = PSS_NAME__; - pPssHeaderAcpiTables->PssName_a_P = PSS_NAME_P; - pPssHeaderAcpiTables->PssName_a_S = PSS_NAME_S; - pPssHeaderAcpiTables->PssName_b_S = PSS_NAME_S; - pPssHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE; - - pPssHeaderAcpiTables++; - pPssBodyAcpiTables = (PSS_BODY *) pPssHeaderAcpiTables; - // Restore the pPssHeaderAcpiTables - pPssHeaderAcpiTables--; - - // Set _PSS Body - //--------------- - PstateCount = 0; - - // Calculate PCI address for socket only - GetPciAddress (StdHeader, (UINT32) PStateLevelingBuffer->SocketNumber, 0, &PciAddress, &IgnoredStatus); - TransAndBusMastLatency = 0; - GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL) - FamilyServices->GetPstateLatency ( FamilyServices, - PStateLevelingBuffer, - &PciAddress, - &TransAndBusMastLatency, - StdHeader); - - for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) { - if (PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) { - pPssBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE; - pPssBodyAcpiTables->PkgLength = PSS_PKG_LENGTH; - pPssBodyAcpiTables->NumOfElements = PSS_NUM_OF_ELEMENTS; - pPssBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->Frequency = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].CoreFreq; - pPssBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->Power = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].Power; - - if (PstateCapEnable && (!PstateCapLevelSupportDetermined) && (PstateCapInputMilliWatts >= pPssBodyAcpiTables->Power)) { - PstateCapLevelSupport = (UINT8) PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; - PstateCapLevelSupportDetermined = TRUE; - } - - pPssBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->TransitionLatency = TransAndBusMastLatency; - pPssBodyAcpiTables->DwordPrefixOpcode4 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->BusMasterLatency = TransAndBusMastLatency; - pPssBodyAcpiTables->DwordPrefixOpcode5 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->Control = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; - pPssBodyAcpiTables->DwordPrefixOpcode6 = DWORD_PREFIX_OPCODE; - pPssBodyAcpiTables->Status = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; - - pPssBodyAcpiTables++; - PstateCount++; - } - } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++) - - if (PstateCapEnable && (!PstateCapLevelSupportDetermined)) { - PstateCapLevelSupport = PStateMaxValueOnCurrentCore; - } - - // Set _PSS Header again - // Now Set pssLength and numOfItemsInPss - //--------------------------------------- - TempVar_a = (PstateCount * PSS_BODY_STRUCT_SIZE) + 3; - TempVar_b = TempVar_a; - TempVar_c = ((TempVar_b << 4) & 0x0000FF00); - TempVar_c = TempVar_c | ((TempVar_b & 0x0000000F) | 0x00000040); - TempVar_a = (UINT16) TempVar_c; - - pPssHeaderAcpiTables->PssLength = (UINT16) TempVar_a; - pPssHeaderAcpiTables->NumOfItemsInPss = (UINT8) PstateCount; - CurrSize += (PSS_HEADER_STRUCT_SIZE + (PstateCount * PSS_BODY_STRUCT_SIZE)); - - *SsdtPtr = pPssBodyAcpiTables; - } // end of PSS Body if OptionPstateLateConfiguration.CfgPstatePss - - // Set XPSS Table - //--------------- - // Typecast the pointer - pXpssHeaderAcpiTables = (XPSS_HEADER *) pPssBodyAcpiTables; - pXpssBodyAcpiTables = (XPSS_BODY *) pPssBodyAcpiTables; - if (OptionPstateLateConfiguration.CfgPstateXpss) { - // Set XPSS Header - // Note: Set the pssLength and numOfItemsInPss later - //--------------------------------------------------- - pXpssHeaderAcpiTables->NameOpcode = NAME_OPCODE; - pXpssHeaderAcpiTables->XpssName_a_X = PSS_NAME_X; - pXpssHeaderAcpiTables->XpssName_a_P = PSS_NAME_P; - pXpssHeaderAcpiTables->XpssName_a_S = PSS_NAME_S; - pXpssHeaderAcpiTables->XpssName_b_S = PSS_NAME_S; - pXpssHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE; - - // Increment and then typecast the pointer - pXpssHeaderAcpiTables++; - pXpssBodyAcpiTables = (XPSS_BODY *) pXpssHeaderAcpiTables; - // Restore the pXpssHeaderAcpiTables - pXpssHeaderAcpiTables--; - - // Set XPSS Body - //--------------- - for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) { - if (PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) { - pXpssBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE; - pXpssBodyAcpiTables->PkgLength = XPSS_PKG_LENGTH; - pXpssBodyAcpiTables->NumOfElements = XPSS_NUM_OF_ELEMENTS; - pXpssBodyAcpiTables->XpssValueTbd = 04; - pXpssBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE; - pXpssBodyAcpiTables->Frequency = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].CoreFreq; - pXpssBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE; - pXpssBodyAcpiTables->Power = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].Power; - pXpssBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE; - pXpssBodyAcpiTables->TransitionLatency = TransAndBusMastLatency; - pXpssBodyAcpiTables->DwordPrefixOpcode4 = DWORD_PREFIX_OPCODE; - pXpssBodyAcpiTables->BusMasterLatency = TransAndBusMastLatency; - pXpssBodyAcpiTables->ControlBuffer = XPSS_ACPI_BUFFER; - pXpssBodyAcpiTables->ControlLo = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; - pXpssBodyAcpiTables->ControlHi = 0; - pXpssBodyAcpiTables->StatusBuffer = XPSS_ACPI_BUFFER; - pXpssBodyAcpiTables->StatusLo = - PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; - pXpssBodyAcpiTables->StatusHi = 0; - pXpssBodyAcpiTables->ControlMaskBuffer = XPSS_ACPI_BUFFER; - pXpssBodyAcpiTables->ControlMaskLo = 0; - pXpssBodyAcpiTables->ControlMaskHi = 0; - pXpssBodyAcpiTables->StatusMaskBuffer = XPSS_ACPI_BUFFER; - pXpssBodyAcpiTables->StatusMaskLo = 0; - pXpssBodyAcpiTables->StatusMaskHi = 0; - - pXpssBodyAcpiTables++; - } - } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++) - - // Set XPSS Header again - // Now set pssLength and numOfItemsInPss - //--------------------------------------- - TempVar_a = (PstateCount * XPSS_BODY_STRUCT_SIZE) + 3; - TempVar_b = TempVar_a; - TempVar_c = ((TempVar_b << 4) & 0x0000FF00); - TempVar_c = TempVar_c | ((TempVar_b & 0x0000000F) | 0x00000040); - TempVar_a = (UINT16) TempVar_c; - - pXpssHeaderAcpiTables->XpssLength = (UINT16) TempVar_a; - pXpssHeaderAcpiTables->NumOfItemsInXpss = (UINT8) PstateCount; - CurrSize += (XPSS_HEADER_STRUCT_SIZE + (PstateCount * XPSS_BODY_STRUCT_SIZE)); - - *SsdtPtr = pXpssBodyAcpiTables; - } //end of XPSS Body OptionPstateLateConfiguration.CfgPstateXpss - - // Set _PSD Table - //--------------- - // Typecast the pointer - pPsdHeaderAcpiTables = (PSD_HEADER *) pXpssBodyAcpiTables; - pPsdBodyAcpiTables = (PSD_BODY *) pXpssBodyAcpiTables; - // Get Total Cores Per Node - if (GetActiveCoresInGivenSocket ((UINT32) PStateLevelingBuffer->SocketNumber, &CoreCount1, StdHeader)) { - GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL) - if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd) && - FamilyServices->IsPstatePsdNeeded (FamilyServices, PlatformConfig, StdHeader)) { - // Set _PSD Header - //---------------- - pPsdHeaderAcpiTables->NameOpcode = NAME_OPCODE; - pPsdHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE; - pPsdHeaderAcpiTables->PsdLength = PSD_HEADER_LENGTH; - pPsdHeaderAcpiTables->Value1 = PSD_VALUE1; - pPsdHeaderAcpiTables->PsdName_a__ = PSD_NAME__; - pPsdHeaderAcpiTables->PsdName_a_P = PSD_NAME_P; - pPsdHeaderAcpiTables->PsdName_a_S = PSD_NAME_S; - pPsdHeaderAcpiTables->PsdName_a_D = PSD_NAME_D; - - // Typecast the pointer - pPsdHeaderAcpiTables++; - CurrSize += PSD_HEADER_STRUCT_SIZE; - pPsdBodyAcpiTables = (PSD_BODY *) pPsdHeaderAcpiTables; - - pPsdHeaderAcpiTables--; - // Set _PSD Body - //-------------- - pPsdBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE; - pPsdBodyAcpiTables->PkgLength = PSD_PKG_LENGTH; - pPsdBodyAcpiTables->NumOfEntries = NUM_OF_ENTRIES; - pPsdBodyAcpiTables->BytePrefixOpcode1 = BYTE_PREFIX_OPCODE; - pPsdBodyAcpiTables->PsdNumOfEntries = PSD_NUM_OF_ENTRIES; - pPsdBodyAcpiTables->BytePrefixOpcode2 = BYTE_PREFIX_OPCODE; - pPsdBodyAcpiTables->PsdRevision = PSD_REVISION; - pPsdBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE; - - IsPsdDependent = FamilyServices->IsPstatePsdDependent (FamilyServices, PlatformConfig, StdHeader); - - if (IsPsdDependent) { - pPsdBodyAcpiTables->DependencyDomain = PSD_DEPENDENCY_DOMAIN; - pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_SW_ALL; - pPsdBodyAcpiTables->NumOfProcessors = CoreCount1; - } else { - switch (GetComputeUnitMapping (StdHeader)) { - case AllCoresMapping: - // All cores are in their own compute unit. - pPsdBodyAcpiTables->DependencyDomain = LocalApicId; - pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_SW_ANY; - pPsdBodyAcpiTables->NumOfProcessors = PSD_NUM_OF_PROCESSORS; - break; - case EvenCoresMapping: - // Cores are paired in compute units. - pPsdBodyAcpiTables->DependencyDomain = (LocalApicId >> 1) & PSD_DOMAIN_COMPUTE_UNIT_MASK; - pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_HW_ALL; - pPsdBodyAcpiTables->NumOfProcessors = PSD_CORE_NUM_PER_COMPUTE_UNIT; - break; - default: - ASSERT (FALSE); - } - } - pPsdBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE; - pPsdBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE; - - pPsdBodyAcpiTables++; - *SsdtPtr = pPsdBodyAcpiTables; - CurrSize += PSD_BODY_STRUCT_SIZE; - } - }// end of PSD Body if (CoreCount1 != 1) || (OptionPstateLateConfiguration.CfgPstatePsd) - // Typecast the pointer - - pPpcAcpiTables = (PPC_HEADER_BODY *) pPsdBodyAcpiTables; - - // Set _PPC Table - //--------------- - if (OptionPstateLateConfiguration.CfgPstatePpc) { - // Name (PPCV, value) - pPpcAcpiTables->NameOpcode = NAME_OPCODE; - pPpcAcpiTables->PpcName_a_P = PPC_NAME_P; - pPpcAcpiTables->PpcName_b_P = PPC_NAME_P; - pPpcAcpiTables->PpcName_a_C = PPC_NAME_C; - pPpcAcpiTables->PpcName_a_V = PPC_NAME_V; - pPpcAcpiTables->Value1 = PPC_VALUE1; - pPpcAcpiTables->DefaultPerfPresentCap = PstateCapLevelSupport; - // Method (_PPC) { return (PPCV) } - pPpcAcpiTables->MethodOpcode = METHOD_OPCODE; - pPpcAcpiTables->PpcLength = PPC_METHOD_LENGTH; - pPpcAcpiTables->PpcName_a__ = PPC_NAME__; - pPpcAcpiTables->PpcName_c_P = PPC_NAME_P; - pPpcAcpiTables->PpcName_d_P = PPC_NAME_P; - pPpcAcpiTables->PpcName_b_C = PPC_NAME_C; - pPpcAcpiTables->MethodFlags = PPC_METHOD_FLAGS; - pPpcAcpiTables->ReturnOpcode = RETURN_OPCODE; - pPpcAcpiTables->PpcName_e_P = PPC_NAME_P; - pPpcAcpiTables->PpcName_f_P = PPC_NAME_P; - pPpcAcpiTables->PpcName_c_C = PPC_NAME_C; - pPpcAcpiTables->PpcName_b_V = PPC_NAME_V; - - CurrSize += PPC_HEADER_BODY_STRUCT_SIZE; - // Increment and typecast the pointer - pPpcAcpiTables++; - *SsdtPtr = pPpcAcpiTables; - }// end of OptionPstateLateConfiguration.CfgPstatePpc - } - return CurrSize; -} - -/**-------------------------------------------------------------------------------------- - * - * CreateCStateAcpiTables - * - * Description: - * This is the common routine for creating ACPI C-State objects - * - * Parameters: - * @param[in] PlatformConfig Platform operational characteristics; power cap - * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information - * @param[in,out] SsdtPtr ACPI SSDT table pointer - * @param[in] LocalApicId Local Apic Id - * @param[in] StdHeader Handle to config for library and services - * - * @retval Size of ACPI C-States objects generated - * - *--------------------------------------------------------------------------------------- - **/ -UINT32 -CreateCStateAcpiTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **SsdtPtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ObjSize; - IO_CSTATE_FAMILY_SERVICES *IoCstateFamilyServices; - - ObjSize = 0; - - if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) { - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&IoCstateFamilyServices, StdHeader); - // If we're supporting multiple families, only proceed when IO Cstate family services are available - if (IoCstateFamilyServices != NULL) { - IoCstateFamilyServices->CreateAcpiCstObj (IoCstateFamilyServices, LocalApicId, SsdtPtr, StdHeader); - ObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader); - } - } - return ObjSize; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateTables.h deleted file mode 100644 index e77a4f10f2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuPstateTables.h +++ /dev/null @@ -1,329 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU Pstate Table Functions declarations. - * - * Contains code that declares the AGESA CPU _PSS related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_PSTATE_TABLES_H_ -#define _CPU_PSTATE_TABLES_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (PSTATE_CPU_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/// P-state structure for each state -typedef struct { - IN OUT UINT32 PStateEnable; ///< Pstate enable - IN OUT UINT32 CoreFreq; ///< MHz - IN OUT UINT32 Power; ///< milliWatts - IN OUT UINT32 IddValue; ///< Current value field - IN OUT UINT32 IddDiv; ///< Current divisor field - IN OUT UINT32 SwPstateNumber; ///< Software P-state number -} S_PSTATE_VALUES; - -/// P-state structure for each core -typedef struct { - IN OUT UINT8 PStateMaxValue; ///< Max p-state number in this core - IN OUT UINT8 HtcPstateLimit; ///< Htc limit - IN OUT UINT8 HtcCapable; ///< Htc capable - IN OUT UINT8 LocalApicId; ///< Local Apic Id - IN OUT UINT8 NumberOfBoostedStates; ///< Number of boost P-states - IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc -} S_PSTATE; - -/// P-state structure for each node -typedef struct { - IN UINT8 SetPState0; ///< If value = 0x55 (Don't set PState0) - IN UINT8 TotalCoresInNode; ///< core number per node - IN UINT16 PStateLevelingSizeOfBytes; ///< Size - IN BOOLEAN OnlyOneEnabledPState; ///< Only P0 - IN UINT8 InitStruct; ///< Init struc - IN BOOLEAN AllCpusHaveIdenticalPStates; ///< Have Identical p state - IN UINT8 CreateAcpiTables; ///< Create table flag - IN UINT8 SocketNumber; ///< Physical socket number of this socket - IN UINT8 Reserved[2]; ///< Reserved. - IN OUT S_PSTATE PStateCoreStruct[1]; ///< P state core struc -} PSTATE_LEVELING; - -/// P-state structure for whole system -typedef struct { - IN OUT UINT32 TotalSocketInSystem; ///< Total node number in system - IN OUT UINT32 SizeOfBytes; ///< Structure size - IN OUT PSTATE_LEVELING PStateLevelingStruc[1]; ///< P state level structure -} S_CPU_AMD_PSTATE; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if PSD need to be generated. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE PSD need to be generated - * @retval FALSE PSD does NOT need to be generated - * - */ -typedef BOOLEAN F_PSTATE_PSD_IS_NEEDED ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_PSTATE_PSD_IS_NEEDED *PF_PSTATE_PSD_IS_NEEDED; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if Pstate PSD is dependent. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE PSD is dependent. - * @retval FALSE PSD is independent. - * - */ -typedef BOOLEAN F_PSTATE_PSD_IS_DEPENDENT ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_PSTATE_PSD_IS_DEPENDENT *PF_PSTATE_PSD_IS_DEPENDENT; - -/** - * Family specific call to set core TscFreqSel. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] StdHeader Config Handle for library, services. - * - */ -typedef VOID F_PSTATE_SET_TSC_FREQ_SEL ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_PSTATE_SET_TSC_FREQ_SEL *PF_PSTATE_SET_TSC_FREQ_SEL; - -/** - * Family specific call to get CPU pstate transition latency for current socket. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer. - * @param[in] PciAddress Pci address struct. - * @param[out] TransitionLatency Pstate Transition latency result. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_PSTATE_TRANSITION_LATENCY ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_PSTATE_TRANSITION_LATENCY *PF_CPU_PSTATE_TRANSITION_LATENCY; - -/** - * Family specific call to get the desired P-state's frequency in megahertz. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] StateNumber P-state number. - * @param[out] PowerInMw P-state frequency in megahertz. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_PSTATE_FREQ ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_PSTATE_FREQ *PF_CPU_GET_PSTATE_FREQ; - -/** - * Family specific call to set the system wide P-state settings on the current core. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] CpuAmdPState The current core's P-state data. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_SET_PSTATE_LEVELING_REG ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_SET_PSTATE_LEVELING_REG *PF_CPU_SET_PSTATE_LEVELING_REG; - -/** - * Family specific call to get the desired P-state's rated power in milliwatts. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] StateNumber P-state number. - * @param[out] PowerInMw P-state power in milliwatts. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_PSTATE_POWER ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_PSTATE_POWER *PF_CPU_GET_PSTATE_POWER; - -/** - * Family specific call to get CPU Pstate Max State. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[out] MaxPStateNumber The max hw pstate value on the current socket. - * @param[out] NumberOfBoostStates The number of boosted P-states on the current socket. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_PSTATE_MAX_STATE ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_PSTATE_MAX_STATE *PF_CPU_GET_PSTATE_MAX_STATE; - -/** - * Family specific call to get CPU pstate register information. - * - * @param[in] PstateCpuFamilyServices Pstate CPU services. - * @param[in] PState Input hardware Pstate number for query. - * @param[out] PStateEnabled Boolean flag return pstate enable. - * @param[in,out] IddVal Pstate current value. - * @param[in,out] IddDiv Pstate current divisor. - * @param[out] SwPstateNumber Software P-state number. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_PSTATE_REGISTER_INFO ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_PSTATE_REGISTER_INFO *PF_CPU_GET_PSTATE_REGISTER_INFO; - -/** - * Provide the interface to the Pstate dependent Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _PSTATE_CPU_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_PSTATE_PSD_IS_NEEDED IsPstatePsdNeeded; ///< Method: Family specific call to check if PSD need to be generated. - PF_PSTATE_PSD_IS_DEPENDENT IsPstatePsdDependent; ///< Method: Family specific call to check if PSD is dependent. - PF_PSTATE_SET_TSC_FREQ_SEL CpuSetTscFreqSel; ///< Method: Family specific call to set core TscFreqSel. - PF_CPU_PSTATE_TRANSITION_LATENCY GetPstateLatency; ///< Method: Family specific call to get pstate transition latency. - PF_CPU_GET_PSTATE_FREQ GetPstateFrequency; ///< Method: Family specific call to get the desired P-state's frequency in megahertz. - PF_CPU_SET_PSTATE_LEVELING_REG SetPStateLevelReg; ///< Method: Family specific call to set the system wide P-state settings on the current core. - PF_CPU_GET_PSTATE_POWER GetPstatePower; ///< Method: Family specific call to get the desired P-state's rated power in milliwatts. - PF_CPU_GET_PSTATE_MAX_STATE GetPstateMaxState; ///< Method: Family specific call to get pstate max state number. - PF_CPU_GET_PSTATE_REGISTER_INFO GetPstateRegisterInfo; ///< Method: Family specific call to get pstate register information. -}; - - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N S P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -PStateGatherData ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PStateLeveling ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -CpuGetPStateLevelStructure ( - OUT PSTATE_LEVELING **PStateBufferPtr, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN UINT32 LogicalSocketNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_PSTATE_TABLES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSlit.c deleted file mode 100644 index 2642a1f8c2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSlit.c +++ /dev/null @@ -1,397 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD SLIT, ACPI table related API functions. - * - * Contains code that generates the SLIT table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 54901 $ @e \$Date: 2011-06-13 21:51:47 -0600 (Mon, 13 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------- - * This file provides functions, that will generate SLIT tables - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionSlit.h" -#include "heapManager.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "Ids.h" -#include "cpuFeatures.h" -#include "cpuFamilyTranslation.h" -#include "cpuL3Features.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FEATURE_CPUSLIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration; // global user config record - -STATIC ACPI_TABLE_HEADER ROMDATA CpuSlitHdrStruct = -{ - {'S','L','I','T'}, - 0, - 1, - 0, - {'A','M','D',' ',' ',' '}, - {'A','G','E','S','A',' ',' ',' '}, - 1, - {'A','M','D',' '}, - 1 -}; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -AcpiSlitHBufferFind ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN UINT8 **SocketTopologyPtr - ); - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GetAcpiSlitStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ); - -AGESA_STATUS -GetAcpiSlitMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ); - -AGESA_STATUS -ReleaseSlitBufferStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -ReleaseSlitBuffer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function generates a complete SLIT table into a memory buffer. - * After completion, this table must be set by the system BIOS into its - * internal ACPI namespace, and linked into the RSDT/XSDT - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length - * - * @retval UINT32 AGESA_STATUS - */ -AGESA_STATUS -CreateAcpiSlit ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ) -{ - AGESA_TESTPOINT (TpProcCpuEntrySlit, StdHeader); - return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This is the default routine for use when the SLIT option is NOT requested. - * - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length - * - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GetAcpiSlitStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ) -{ - return AGESA_UNSUPPORTED; -} -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function generates a complete SLIT table into a memory buffer. - * After completion, this table must be set by the system BIOS into its - * internal ACPI namespace, and linked into the RSDT/XSDT - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length - * - * @retval UINT32 AGESA_STATUS - */ -AGESA_STATUS -GetAcpiSlitMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ) -{ - UINT8 MaxHops; - UINT8 SocketNum; - UINT8 i; - UINT8 j; - UINT8 *BufferPtr; - UINT8 *SocketTopologyDataPtr; - UINT8 *SocketTopologyPtr; - UINT32 Socket; - BOOLEAN IsProbeFilterEnabled; - ACPI_TABLE_HEADER *CpuSlitHeaderStructPtr; - AGESA_STATUS Flag; - ALLOCATE_HEAP_PARAMS AllocStruct; - L3_FEATURE_FAMILY_SERVICES *FamilyServices; - - MaxHops = 0; - SocketTopologyPtr = NULL; - Flag = AGESA_ERROR; - IsProbeFilterEnabled = FALSE; - - // find out the pointer to the BufferHandle which contains - // Node Topology information - AcpiSlitHBufferFind (StdHeader, &SocketTopologyPtr); - if (SocketTopologyPtr == 0) { - return (Flag); - } - - SocketNum = *SocketTopologyPtr; - - IDS_HDT_CONSOLE (CPU_TRACE, " SLIT is created\n"); - - // create a buffer by calling IBV callout routine - AllocStruct.RequestedBufferSize = (SocketNum * SocketNum) + AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + sizeof (ACPI_TABLE_HEADER); - AllocStruct.BufferHandle = AMD_ACPI_SLIT_BUFFER_HANDLE; - AllocStruct.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocStruct, StdHeader) != AGESA_SUCCESS) { - return (Flag); - } - *SlitPtr = AllocStruct.BufferPtr; - - //SLIT header - LibAmdMemCopy (*SlitPtr, (VOID *) &CpuSlitHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader); - CpuSlitHeaderStructPtr = (ACPI_TABLE_HEADER *) *SlitPtr; - CpuSlitHeaderStructPtr->TableLength = (UINT32) AllocStruct.RequestedBufferSize; - BufferPtr = *SlitPtr; - - Flag = AGESA_SUCCESS; - // SLIT body - // Check if Probe Filter is enabled - if (IsFeatureEnabled (L3Features, PlatformConfig, StdHeader)) { - IsProbeFilterEnabled = TRUE; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); - if ((FamilyServices == NULL) || (!FamilyServices->IsHtAssistSupported (FamilyServices, PlatformConfig, StdHeader))) { - IsProbeFilterEnabled = FALSE; - break; - } - } - } - } - - - if (!IsProbeFilterEnabled) { - // probe filter is disabled - // get MaxHops - SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum); - for (i = 0; i < SocketNum; i++) { - for (j = 0; j < SocketNum; j++) { - if (*SocketTopologyDataPtr > MaxHops) { - MaxHops = *SocketTopologyDataPtr; - } - SocketTopologyDataPtr++; - } - } - - // the Max hop entries have a value of 13 - // and all other entries have 10. - SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum); - for (i = 0; i < SocketNum; i++) { - for (j = 0; j < SocketNum; j++) { - if (*SocketTopologyDataPtr++ == MaxHops) { - *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + - AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 13; - } else { - *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + - AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 10; - } - } - } - } else { - // probe filter is enabled - // formula : num_hops * 6 + 10 - SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum); - for (i = 0; i < SocketNum; i++) { - for (j = 0; j < SocketNum; j++) { - *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + - AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = - ((*SocketTopologyDataPtr++) * 6) + 10; - } - } - } - - BufferPtr += sizeof (ACPI_TABLE_HEADER); - *((UINT64 *) BufferPtr) = (UINT64) SocketNum; - - //Update SLIT header Checksum - ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SlitPtr, StdHeader); - - return (Flag); -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Find out the pointer to the BufferHandle which contains - * Node Topology information - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in] SocketTopologyPtr Point to the address of Socket Topology - * - */ -VOID -STATIC -AcpiSlitHBufferFind ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN UINT8 **SocketTopologyPtr - ) -{ - LOCATE_HEAP_PTR LocateBuffer; - - LocateBuffer.BufferHandle = HOP_COUNT_TABLE_HANDLE; - if (HeapLocateBuffer (&LocateBuffer, StdHeader) == AGESA_SUCCESS) { - *SocketTopologyPtr = (UINT8 *) LocateBuffer.BufferPtr; - } - - return; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * ReleaseSlitBufferStub - * - * Description: - * This is the default routine for use when the SLIT option is NOT requested. - * - * Parameters: - * @param[in, out] *StdHeader - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -ReleaseSlitBufferStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_UNSUPPORTED; -} - -/* -----------------------------------------------------------------------------*/ -/** - * ReleaseSlitBuffer - * - * Description: - * Deallocate SLIT buffer - * - * Parameters: - * @param[in, out] *StdHeader - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -ReleaseSlitBuffer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - HeapDeallocateBuffer ((UINT32) HOP_COUNT_TABLE_HANDLE, StdHeader); - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c deleted file mode 100644 index b4d0e0f1d6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c +++ /dev/null @@ -1,617 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD SRAT, ACPI table related API functions. - * - * Contains code that Create the APCI SRAT Table after early reset. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 54901 $ @e \$Date: 2011-06-13 21:51:47 -0600 (Mon, 13 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - -/*---------------------------------------------------------------------------- - * This file provides functions, that will generate SRAT tables - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuServices.h" -#include "OptionSrat.h" -#include "heapManager.h" -#include "cpuRegisters.h" -#include "cpuLateInit.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FEATURE_CPUSRAT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_SRAT_CONFIGURATION OptionSratConfiguration; // global user config record - -#define NodeID 0x60 -#define FOURGB 0x010000 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -GetAcpiSratStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ); - -AGESA_STATUS -GetAcpiSratMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ); - -/*---------------------------------------------------------------------------- - * All of the DATA should be defined in _CODE segment. - * Use ROMDATA to specify that it belongs to _CODE. - *---------------------------------------------------------------------------- - */ -STATIC CPU_SRAT_HEADER ROMDATA CpuSratHdrStruct = -{ - {'S','R','A','T'}, - 0, - 2, - 0, - {'A','M','D',' ',' ',' '}, - {'A','G','E','S','A',' ',' ',' '}, - 1, - {'A','M','D',' '}, - 1, - 1, - {0, 0, 0, 0, 0, 0, 0, 0} -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT8 -STATIC -*MakeApicEntry ( - IN UINT8 ApicId, - IN UINT8 Domain, - IN UINT8 *BufferLocPtr - ); - -UINT8 -STATIC -*FillMemoryForCurrentNode ( - IN UINT8 *PDomain, - IN OUT UINT8 *PDomainForBase640K, - IN UINT8 Node, - IN OUT UINT8 *BufferLocPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -STATIC -*MakeMemEntry ( - IN UINT8 PDomain, - IN UINT8 Node, - IN UINT32 Base, - IN UINT32 Size, - IN UINT8 *BufferLocPtr - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function will generate a complete Static Resource Affinity Table - * i.e. SRAT into a memory buffer. After completion, this table must be set - * by the system BIOS into its internal ACPI name space. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] SratPtr Point to Srat Struct including buffer address and length - * - * @retval AGESA_STATUS - */ - -AGESA_STATUS -CreateAcpiSrat ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ) -{ - AGESA_TESTPOINT (TpProcCpuEntrySrat, StdHeader); - return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This is the default routine for use when the SRAT option is NOT requested. - * - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] SratPtr Point to Srat Struct including buffer address and length - * - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GetAcpiSratStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ) -{ - return AGESA_UNSUPPORTED; -} -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function will generate a complete Static Resource Affinity Table - * i.e. SRAT into a memory buffer. After completion, this table must be set - * by the system BIOS into its internal ACPI name space. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] SratPtr Point to Srat Struct including buffer address and length - * - * @retval AGESA_STATUS - */ -AGESA_STATUS -GetAcpiSratMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ) -{ - UINT8 *BufferPtr; - UINT8 NodeNum; - UINT8 NodeCount; - UINT8 PDomain; - UINT8 PDomainForBase640K; - UINT32 Socket; - UINT32 Module; - UINT32 LowCore; - UINT32 HighCore; - UINT32 CoreNum; - UINT32 RegVal; - UINT32 tempVar_32; - AMD_APIC_PARAMS ApicParams; - PCI_ADDR PciAddress; - CPU_SRAT_HEADER *CpuSratHeaderStructPtr; - ALLOCATE_HEAP_PARAMS AllocParams; - - // Get Node count - PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, NodeID); - LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader); - NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1); - - // The worst-case buffer size to request is for the SRAT table header, one - // entree for special region (base 640k block), two memory - // regions per node, and APIC entries for each core in the system. - tempVar_32 = (sizeof (CPU_SRAT_HEADER)) + (sizeof (CPU_SRAT_MEMORY_ENTRY)) - + ((UINT32) NodeCount * (2 * (sizeof (CPU_SRAT_MEMORY_ENTRY)) - + ((UINT32) GetActiveCoresInCurrentModule (StdHeader) * sizeof (CPU_SRAT_APIC_ENTRY)))); - - if (*SratPtr == NULL) { - // - // Allocate a buffer - // - AllocParams.RequestedBufferSize = tempVar_32; - AllocParams.BufferHandle = AMD_SRAT_INFO_BUFFER_HANDLE; - AllocParams.Persist = HEAP_SYSTEM_MEM; - - AGESA_TESTPOINT (TpProcCpuBeforeAllocateSratBuffer, StdHeader); - if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpProcCpuAfterAllocateSratBuffer, StdHeader); - - *SratPtr = AllocParams.BufferPtr; - } - - IDS_HDT_CONSOLE (CPU_TRACE, " SRAT is created\n"); - - CpuSratHeaderStructPtr = (CPU_SRAT_HEADER *) *SratPtr; - BufferPtr = (UINT8 *) *SratPtr; - - // Copy acpiSRATHeader -> data buffer - LibAmdMemCopy (*SratPtr, (VOID *) &CpuSratHdrStruct, (UINTN) (sizeof (CPU_SRAT_HEADER)), StdHeader); - - BufferPtr += sizeof (CPU_SRAT_HEADER); - - // Place all memory and IO affinity entries - NodeNum = 0; - PDomain = 0; - PDomainForBase640K = 0xFF; - ApicParams.StdHeader = *StdHeader; - while (NodeNum < NodeCount) { - GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader); - GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); - BufferPtr = FillMemoryForCurrentNode (&PDomain, &PDomainForBase640K, NodeNum, BufferPtr, StdHeader); - for (CoreNum = LowCore; CoreNum <= HighCore; CoreNum++) { - ApicParams.Socket = (UINT8) Socket; - ApicParams.Core = (UINT8) CoreNum; - AmdGetApicId (&ApicParams); - if (ApicParams.IsPresent) { - BufferPtr = MakeApicEntry (ApicParams.ApicAddress, PDomain, BufferPtr); - } - } - - NodeNum++; - PDomain = NodeNum; - } - - // Store size in table (current buffer offset - buffer start offset) - CpuSratHeaderStructPtr->TableLength = (UINT32) (BufferPtr - (UINT8 *) CpuSratHeaderStructPtr); - - //Update SSDT header Checksum - ChecksumAcpiTable ((ACPI_TABLE_HEADER *) CpuSratHeaderStructPtr, StdHeader); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function will build Memory entry for current node. - * Note that we only create a memory affinity entry if we find one - * that matches the current node. This makes an easier to read table - * though it is not necessary. - * - * @param[in] PDomain Proximity Domain - * @param[in, out] PDomainForBase640K The PDomain for Base 640K - * @param[in] Node The number of Node - * @param[in, out] BufferLocPtr Point to the address of buffer - * @param[in, out] StdHeader Standard Head Pointer - * - * @retval UINT8 *(New buffer location ptr) - */ -UINT8 -STATIC -*FillMemoryForCurrentNode ( - IN UINT8 *PDomain, - IN OUT UINT8 *PDomainForBase640K, - IN UINT8 Node, - IN OUT UINT8 *BufferLocPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ValueLimit; - UINT32 ValueTOM; - BOOLEAN isModified; - UINT8 Domain; - UINT32 RegVal; - UINT32 DramLeng; - UINT32 DramBase; - UINT32 DramLimit; - UINT32 OffsetRegs; - PCI_ADDR PciAddress; - UINT64 MsrValue; - UINT32 TopOfMemoryAbove4Gb; - - Domain = *PDomain; - - PciAddress.Address.Segment = 0; - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = LOW_NODE_DEVICEID; - PciAddress.Address.Function = FUNC_1; - - for (OffsetRegs = DRAMBase0; OffsetRegs < MMIOBase0; OffsetRegs += 8) { - isModified = FALSE; // FALSE means normal update procedure - // Get DRAM Base Address - PciAddress.Address.Register = OffsetRegs; - LibAmdPciRead (AccessWidth32, PciAddress, &DramBase, StdHeader); - if ((DramBase & 3) != 3) { - // 0:1 set if memory range enabled - // Not set, so we don't have an enabled range - continue; // Proceed to next Base register - } - - // Get DRAM Limit - PciAddress.Address.Register = OffsetRegs + 4; - LibAmdPciRead (AccessWidth32, PciAddress, &DramLimit, StdHeader); - if (DramLimit == 0xFFFFFFFF) { - // Node not installed(all FF's)? - continue; // Proceed to next Base register - } - - if ((DramLimit & 0xFF) != Node) { - // Check if Destination Node ID is current node - continue; // Proceed to next Base register - } - - // We only add an entry now if detected range belongs to current node/PDomain - PciAddress.Address.Register = OffsetRegs + 0x104; - LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader); - - DramLimit = (((RegVal & 0xFF) << 16) | (DramLimit >> 16)); // Get DRAM Limit addr [47:24] - DramLimit++; // Add 1 for potential length - DramLimit <<= 8; - - // Get DRAM Base Address - PciAddress.Address.Register = OffsetRegs + 0x100; - LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader); - DramBase = ((((RegVal & 0xFF) << 24) | (DramBase >> 8)) & 0xFFFFFF00); // Get DRAM Base Base value [47:24] - DramLeng = DramLimit - DramBase; // Subtract base from limit to get length - - // Leave hole for conventional memory (Less than 640K). It must be on CPU 0. - if (DramBase == 0) { - if (*PDomainForBase640K == 0xFF) { - // It is the first time that the range start at 0. - // If Yes, then Place 1MB memory gap and save Domain to PDomainForBase640K - BufferLocPtr = MakeMemEntry ( - Domain, - Node, - 0, // Base = 0 - 0xA0000 >> 16, // Put it into format used in DRAM regs.. - BufferLocPtr - ); - DramBase += 0x10; // Add 1MB, so range = 1MB to Top of Region - DramLeng -= 0x10; // Also subtract 1MB from the length - *PDomainForBase640K = Domain; // Save Domain number for memory Less than 640K - } else { - // If No, there are more than one memory range less than 640K, it should that - // node interleaving is enabled. All nodes have the same memory ranges - // and all cores in these nodes belong to the same domain. - *PDomain = *PDomainForBase640K; - return (BufferLocPtr); - } - } - LibAmdMsrRead (TOP_MEM, &MsrValue, StdHeader); - ValueTOM = (UINT32) MsrValue >> 16; // Save it in 39:24 format - ValueLimit = DramBase + DramLeng; // We need to know how large region is - - LibAmdMsrRead (SYS_CFG, &MsrValue, StdHeader); - if ((MsrValue & BIT21) != 0) { - LibAmdMsrRead (TOP_MEM2, &MsrValue, StdHeader); - TopOfMemoryAbove4Gb = (UINT32) (MsrValue >> 16); // Save it in 47:16 format - } else { - TopOfMemoryAbove4Gb = 0xFFFFFFFF; - } - - // SPECIAL CASES: - // - // Several conditions require that we process the values of the memory range differently. - // Here are descriptions of the corner cases. - // - // 1. TRUNCATE LOW - Memory range starts below TOM, ends in TOM (memory hole). For this case, - // the range must be truncated to end at TOM. - // ******************************* ******************************* - // * * * -> * * - // ******************************* ******************************* - // 2 TOM 4 2 TOM - // - // 2. TRUNCATE HIGH - Memory range starts below 4GB, ends above 4GB. This is handled by changing the - // start base to 4GB. - // **************** ********** - // * * * -> * * - // **************** ********** - // TOM 3.8 4 6 TOM 3.8 4 6 - // - // 3. Memory range starts below TOM, ends above 4GB. For this case, the range must be truncated - // to end at TOM. Note that this scenario creates two ranges, as the second comparison below - // will find that it ends above 4GB since base and limit have been restored after first truncation, - // and a second range will be written based at 4GB ending at original end address. - // ******************************* **************** ********** - // * * * * -> * * * * - // ******************************* **************** ********** - // 2 TOM 4 6 2 TOM 4 6 - // - // 4. Memory range starts above TOM, ends below or equal to 4GB. This invalid range should simply - // be ignored. - // ******* - // * * -> < NULL > - // ******* - // TOM 3.8 4 - // - // 5. Memory range starts below TOM2, and ends beyond TOM2. This range must be truncated to TOM2. - // ************************ ******************************* - // * * * -> * * - // ************************ ******************************* - // 768 TOM2 1024 768 TOM2 - // - // 6. Memory range starts above TOM2. This invalid range should simply be ignored. - // ******************** - // * * -> < NULL > - // ******************** - // TOM2 1024 1280 - - if (((DramBase < ValueTOM) && (ValueLimit <= FOURGB) && (ValueLimit > ValueTOM)) - || ((DramBase < ValueTOM) && (ValueLimit > FOURGB))) { - // TRUNCATE LOW!!! Shrink entry below TOM... - // Base = DramBase, Size = TOM - DramBase - BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (ValueTOM - DramBase), BufferLocPtr); - isModified = TRUE; - } - - if ((ValueLimit > FOURGB) && (DramBase < FOURGB)) { - // TRUNCATE HIGH!!! Shrink entry above 4GB... - // Size = Base + Size - 4GB, Base = 4GB - BufferLocPtr = MakeMemEntry (Domain, Node, FOURGB, (DramLeng + DramBase - FOURGB), BufferLocPtr); - isModified = TRUE; - } - - if ((DramBase >= ValueTOM) && (ValueLimit <= FOURGB)) { - // IGNORE!!! Entry located entirely within memory hole - isModified = TRUE; - } - - if ((DramBase < TopOfMemoryAbove4Gb) && (ValueLimit > TopOfMemoryAbove4Gb)) { - // Truncate to TOM2 - // Base = DramBase, Size = TOM2 - DramBase - BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (TopOfMemoryAbove4Gb - DramBase), BufferLocPtr); - isModified = TRUE; - } - - if (DramBase >= TopOfMemoryAbove4Gb) { - // IGNORE!!! Entry located entirely above TOM2 - isModified = TRUE; - } - - // If special range(isModified), we are done. - // If not, finally write the memory entry. - if (isModified == FALSE) { - // Finally write the memory entry. - BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, DramLeng, BufferLocPtr); - } - - } // for ( OffsetRegs = DRAMBase0; ... ) - - return (BufferLocPtr); -} // FillMemoryForCurrentNode() - - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will add APIC entry. - * - * @param[in] ApicId APIC ID number - * @param[in] Domain Domain number - * @param[in] BufferLocPtr Point to the address of buffer - * - * @retval UINT8 *(New buffer location ptr) - */ -UINT8 -STATIC -*MakeApicEntry ( - IN UINT8 ApicId, - IN UINT8 Domain, - IN UINT8 *BufferLocPtr - ) -{ - CPU_SRAT_APIC_ENTRY *psSratApicEntry; - UINT8 ReservedBytes; - - psSratApicEntry = (CPU_SRAT_APIC_ENTRY *)BufferLocPtr; - - psSratApicEntry->Type = AE_APIC; - psSratApicEntry->Length = (UINT8)sizeof (CPU_SRAT_APIC_ENTRY); - psSratApicEntry->Domain = Domain; - psSratApicEntry->ApicId = ApicId; - psSratApicEntry->Flags = ENABLED; - psSratApicEntry->LSApicEid = 0; - for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratApicEntry->Reserved); ReservedBytes++) { - psSratApicEntry->Reserved[ReservedBytes] = 0; - } - return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_APIC_ENTRY)); -} // MakeApicEntry - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function will add Memory entry. - * - * Parameters: - * @param[in] PDomain Proximity Domain - * @param[in] Node The number of Node - * @param[in] Base Memory Base - * @param[in] Size Memory Size - * @param[in] BufferLocPtr Point to the address of buffer - * - * @retval UINT8 * (new buffer location ptr) - */ -UINT8 -STATIC -*MakeMemEntry ( - IN UINT8 PDomain, - IN UINT8 Node, - IN UINT32 Base, - IN UINT32 Size, - IN UINT8 *BufferLocPtr - ) -{ - CPU_SRAT_MEMORY_ENTRY *psSratMemEntry; - UINT8 ReservedBytes; - - psSratMemEntry = (CPU_SRAT_MEMORY_ENTRY *)BufferLocPtr; - - psSratMemEntry->Type = AE_MEMORY; // [0] = Memory Entry - psSratMemEntry->Length = (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY); // [1] = 40 - psSratMemEntry->Domain = PDomain; // [2] = Proximity Domain - - // [6-7] = Reserved - for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved1); ReservedBytes++) { - psSratMemEntry->Reserved1[ReservedBytes] = 0; - } - - // [8-11] = Keep 31:0 of address only -> Base Addr Low - psSratMemEntry->BaseAddrLow = Base << 16; - - // [12-15] = Keep 39:32 of address only -> Base Addr High - psSratMemEntry->BaseAddrHigh = Base >> 16; - - // [16-19] = Keep 31:0 of address only -> Length Low - psSratMemEntry->LengthAddrLow = Size << 16; - - // [20-23] = Keep 39:32 of address only -> Length High - psSratMemEntry->LengthAddrHigh = Size >> 16; - - // [24-27] = Reserved - for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved2); ReservedBytes++) { - psSratMemEntry->Reserved2[ReservedBytes] = 0; - } - - // [28-31] = Flags - psSratMemEntry->Flags = ENABLED; - - // [32-40] = Reserved - for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved3); ReservedBytes++) { - psSratMemEntry->Reserved3[ReservedBytes] = 0; - } - return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY)); -} // MakeMemEntry() - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.c deleted file mode 100644 index f791e1a523..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.c +++ /dev/null @@ -1,178 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU SW C1e feature support code. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "Topology.h" -#include "cpuFeatures.h" -#include "cpuSwC1e.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FEATURE_CPUSWC1E_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE SwC1eFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * Should software C1e be enabled - * - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE SW C1e is supported. - * @retval FALSE SW C1e not supported. - * - */ -BOOLEAN -STATIC -IsSwC1eFeatureEnabled ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsEnabled; - BOOLEAN IsOtherC1eEnabled; - AP_MAILBOXES ApMailboxes; - SW_C1E_FAMILY_SERVICES *SwFamilyServices; - - ASSERT (PlatformConfig->C1eMode < MaxC1eMode); - IsEnabled = FALSE; - - // Check whether software C1e is enabled only if other C1e methods is/are not supported - // or if the platform specifically uses C1eModeSoftwareDeprecated. - IsOtherC1eEnabled = (IsFeatureEnabled (HardwareC1e, PlatformConfig, StdHeader) || - IsFeatureEnabled (MsgBasedC1e, PlatformConfig, StdHeader)); - if ((PlatformConfig->C1eMode == C1eModeSoftwareDeprecated) || - ((!IsOtherC1eEnabled) && ((PlatformConfig->C1eMode == C1eModeHardwareSoftwareDeprecated) || (PlatformConfig->C1eMode == C1eModeAuto)))) { - ASSERT ((PlatformConfig->C1ePlatformData1 < 0x10000) && (PlatformConfig->C1ePlatformData1 != 0)); - ASSERT (PlatformConfig->C1ePlatformData2 < 0x100); - if ((PlatformConfig->C1ePlatformData1 != 0) && (PlatformConfig->C1ePlatformData1 < 0xFFFE) && (PlatformConfig->C1ePlatformData2 < 0xFF)) { - if (!IsNonCoherentHt1 (StdHeader)) { - if (GetNumberOfProcessors (StdHeader) == 1) { - GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); - if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) { - GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (CONST VOID **)&SwFamilyServices, StdHeader); - if (SwFamilyServices != NULL) { - IsEnabled = SwFamilyServices->IsSwC1eSupported (SwFamilyServices, StdHeader); - } - } - } - } - } - } - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable Software C1e - * - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return The most severe status of any family specific service. - * - */ -AGESA_STATUS -STATIC -InitializeSwC1eFeature ( - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - SW_C1E_FAMILY_SERVICES *FamilyServices; - - AgesaStatus = AGESA_SUCCESS; - - IDS_HDT_CONSOLE (CPU_TRACE, " SW C1e is enabled\n"); - - if (IsWarmReset (StdHeader)) { - GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - AgesaStatus = FamilyServices->InitializeSwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader); - } - - return AgesaStatus; -} - -CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e = -{ - SoftwareC1e, - CPU_FEAT_AFTER_PM_INIT, - IsSwC1eFeatureEnabled, - InitializeSwC1eFeature -}; \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.h deleted file mode 100644 index 7de107f83b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.h +++ /dev/null @@ -1,118 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA CPU SW C1e Functions declarations. - * - * Contains code that declares the AGESA CPU C1e related APIs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Feature - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_SW_C1E_H_ -#define _CPU_SW_C1E_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (SW_C1E_FAMILY_SERVICES); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if software C1e is supported. - * - * @param[in] SwC1eServices Software C1e services. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE SW C1e is supported. - * @retval FALSE SW C1e is not supported. - * - */ -typedef BOOLEAN F_SW_C1E_IS_SUPPORTED ( - IN SW_C1E_FAMILY_SERVICES *SwC1eServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method -typedef F_SW_C1E_IS_SUPPORTED *PF_SW_C1E_IS_SUPPORTED; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to enable software C1e. - * - * @param[in] SwC1eServices Software C1e services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return Family specific error value. - * - */ -typedef AGESA_STATUS F_SW_C1E_INIT ( - IN SW_C1E_FAMILY_SERVICES *SwC1eServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method -typedef F_SW_C1E_INIT *PF_SW_C1E_INIT; - -/** - * Provide the interface to the software C1e Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _SW_C1E_FAMILY_SERVICES { - UINT16 Revision; ///< Interface version - // Public Methods. - PF_SW_C1E_IS_SUPPORTED IsSwC1eSupported; ///< Method: Family specific call to check if software C1e is supported. - PF_SW_C1E_INIT InitializeSwC1e; ///< Method: Family specific call to enable software C1e. -}; - -#endif // _CPU_SW_C1E_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c deleted file mode 100644 index e3f2eb0a42..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD WHEA Table Creation API, and related functions. - * - * Contains code that produce the ACPI WHEA related information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionWhea.h" -#include "cpuLateInit.h" -#include "heapManager.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FEATURE_CPUWHEA_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - -extern OPTION_WHEA_CONFIGURATION OptionWheaConfiguration; // global user config record - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -CreateHestBank ( - IN AMD_HEST_BANK *HestBankPtr, - IN UINT8 BankNum, - IN AMD_WHEA_INIT_DATA *WheaInitDataPtr - ); - -AGESA_STATUS -GetAcpiWheaStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ); - -AGESA_STATUS -GetAcpiWheaMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------*/ -/** - * - * It will create the ACPI table of WHEA and return the pointer to the table. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] WheaMcePtr Point to Whea Hest Mce table - * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table - * - * @retval AGESA_STATUS - */ -AGESA_STATUS -CreateAcpiWhea ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ) -{ - AGESA_TESTPOINT (TpProcCpuEntryWhea, StdHeader); - return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This is the default routine for use when the WHEA option is NOT requested. - * - * The option install process will create and fill the transfer vector with - * the address of the proper routine (Main or Stub). The link optimizer will - * strip out of the .DLL the routine that is not used. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] WheaMcePtr Point to Whea Hest Mce table - * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table - * - * @retval AGESA_STATUS - */ - -AGESA_STATUS -GetAcpiWheaStub ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ) -{ - return AGESA_UNSUPPORTED; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * It will create the ACPI tale of WHEA and return the pointer to the table. - * - * @param[in, out] StdHeader Standard Head Pointer - * @param[in, out] WheaMcePtr Point to Whea Hest Mce table - * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table - * - * @retval UINT32 AGESA_STATUS - */ -AGESA_STATUS -GetAcpiWheaMain ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ) -{ - UINT8 BankNum; - UINT8 Entries; - UINT16 HestMceTableSize; - UINT16 HestCmcTableSize; - UINT64 MsrData; - AMD_HEST_MCE_TABLE *HestMceTablePtr; - AMD_HEST_CMC_TABLE *HestCmcTablePtr; - AMD_HEST_BANK *HestBankPtr; - AMD_WHEA_INIT_DATA *WheaInitDataPtr; - ALLOCATE_HEAP_PARAMS AllocParams; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - FamilySpecificServices = NULL; - - IDS_HDT_CONSOLE (CPU_TRACE, " WHEA is created\n"); - - // step 1: calculate Hest table size - LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader); - BankNum = (UINT8) (((MSR_MCG_CAP_STRUCT *) (&MsrData))->Count); - if (BankNum == 0) { - return AGESA_ERROR; - } - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetWheaInitData (FamilySpecificServices, (CONST VOID **) &WheaInitDataPtr, &Entries, StdHeader); - - ASSERT (WheaInitDataPtr->HestBankNum <= BankNum); - - HestMceTableSize = sizeof (AMD_HEST_MCE_TABLE) + WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK); - HestCmcTableSize = sizeof (AMD_HEST_CMC_TABLE) + WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK); - - HestMceTablePtr = (AMD_HEST_MCE_TABLE *) *WheaMcePtr; - HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) *WheaCmcPtr; - - // step 2: allocate a buffer by callback function - if ((HestMceTablePtr == NULL) || (HestCmcTablePtr == NULL)) { - AllocParams.RequestedBufferSize = (UINT32) (HestMceTableSize + HestCmcTableSize); - AllocParams.BufferHandle = AMD_WHEA_BUFFER_HANDLE; - AllocParams.Persist = HEAP_SYSTEM_MEM; - - AGESA_TESTPOINT (TpProcCpuBeforeAllocateWheaBuffer, StdHeader); - if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpProcCpuAfterAllocateWheaBuffer, StdHeader); - - HestMceTablePtr = (AMD_HEST_MCE_TABLE *) AllocParams.BufferPtr; - HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) ((UINT8 *) (HestMceTablePtr + 1) + (WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK))); - } - - // step 3: fill in Hest MCE table - HestMceTablePtr->TblLength = HestMceTableSize; - HestMceTablePtr->GlobCapInitDataLSD = WheaInitDataPtr->GlobCapInitDataLSD; - HestMceTablePtr->GlobCapInitDataMSD = WheaInitDataPtr->GlobCapInitDataMSD; - HestMceTablePtr->GlobCtrlInitDataLSD = WheaInitDataPtr->GlobCtrlInitDataLSD; - HestMceTablePtr->GlobCtrlInitDataMSD = WheaInitDataPtr->GlobCtrlInitDataMSD; - HestMceTablePtr->NumHWBanks = WheaInitDataPtr->HestBankNum; - - HestBankPtr = (AMD_HEST_BANK *) (HestMceTablePtr + 1); - CreateHestBank (HestBankPtr, WheaInitDataPtr->HestBankNum, WheaInitDataPtr); - - // step 4: fill in Hest CMC table - HestCmcTablePtr->NumHWBanks = WheaInitDataPtr->HestBankNum; - HestCmcTablePtr->TblLength = HestCmcTableSize; - - HestBankPtr = (AMD_HEST_BANK *) (HestCmcTablePtr + 1); - CreateHestBank (HestBankPtr, WheaInitDataPtr->HestBankNum, WheaInitDataPtr); - - // step 5: fill in the incoming structure - *WheaMcePtr = HestMceTablePtr; - *WheaCmcPtr = HestCmcTablePtr; - - return (AGESA_SUCCESS); -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * - * It will create Bank structure for Hest table - * - * @param[in] HestBankPtr Pointer to the Hest Back structure - * @param[in] BankNum The number of Bank - * @param[in] WheaInitDataPtr Pointer to the AMD_WHEA_INIT_DATA structure - * - */ -VOID -STATIC -CreateHestBank ( - IN AMD_HEST_BANK *HestBankPtr, - IN UINT8 BankNum, - IN AMD_WHEA_INIT_DATA *WheaInitDataPtr - ) -{ - UINT8 BankIndex; - for (BankIndex = 0; BankIndex < BankNum; BankIndex++) { - HestBankPtr->BankNum = BankIndex; - HestBankPtr->ClrStatusOnInit = WheaInitDataPtr->ClrStatusOnInit; - HestBankPtr->StatusDataFormat = WheaInitDataPtr->StatusDataFormat; - HestBankPtr->ConfWriteEn = WheaInitDataPtr->ConfWriteEn; - HestBankPtr->CtrlRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlRegMSRAddr; - HestBankPtr->CtrlInitDataLSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataLSD; - HestBankPtr->CtrlInitDataMSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataMSD; - HestBankPtr->StatRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].StatRegMSRAddr; - HestBankPtr->AddrRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].AddrRegMSRAddr; - HestBankPtr->MiscRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].MiscRegMSRAddr; - HestBankPtr++; - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/CPU/Makefile.inc deleted file mode 100644 index 239af76e98..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -libagesa-y += S3.c -libagesa-y += Table.c -libagesa-y += cahalt.c -libagesa-y += cahaltasm.S -libagesa-y += cpuApicUtilities.c -libagesa-y += cpuBist.c -libagesa-y += cpuBrandId.c -libagesa-y += cpuEarlyInit.c -libagesa-y += cpuEventLog.c -libagesa-y += cpuFamilyTranslation.c -libagesa-y += cpuGeneralServices.c -libagesa-y += cpuInitEarlyTable.c -libagesa-y += cpuLateInit.c -libagesa-y += cpuMicrocodePatch.c -libagesa-y += cpuPostInit.c -libagesa-y += cpuPowerMgmt.c -libagesa-y += cpuPowerMgmtMultiSocket.c -libagesa-y += cpuPowerMgmtSingleSocket.c -libagesa-y += cpuWarmReset.c -libagesa-y += heapManager.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c deleted file mode 100644 index c055f5b545..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c +++ /dev/null @@ -1,1233 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * ACPI S3 Support routines - * - * Contains routines needed for supporting resume from the ACPI S3 sleep state. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_S3_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -SaveDeviceContext ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN CALL_POINTS CallPoint, - OUT UINT32 *ActualBufferSize, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SavePciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ); - -VOID -SaveConditionalPciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ); - -VOID -SaveMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ); - -VOID -SaveConditionalMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ); - -VOID -RestorePciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ); - -VOID -RestoreConditionalPciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ); - -VOID -RestoreMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ); - -VOID -RestoreConditionalMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves all devices in the given device list. - * - * This traverses the entire device list twice. In the first pass, we save - * all devices identified as Pre ESR. In the second pass, we save devices - * marked as post ESR. - * - * @param[in] DeviceList Beginning of the device list to save. - * @param[in] Storage Beginning of the context buffer. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[out] ActualBufferSize Actual size used in saving the device list. - * @param[in] StdHeader AMD standard header config param. - * - */ -VOID -SaveDeviceListContext ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - OUT UINT32 *ActualBufferSize, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Copy device list over - LibAmdMemCopy (Storage, - DeviceList, - (UINTN) DeviceList->RelativeOrMaskOffset, - StdHeader); - SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves all devices in the given device list. - * - * This traverses the entire device list twice. In the first pass, we save - * all devices identified as Pre ESR. In the second pass, we save devices - * marked as post ESR. - * - * @param[in,out] DeviceList Beginning of the device list to save. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[out] ActualBufferSize Actual size used in saving the device list. - * @param[in] StdHeader AMD standard header config param. - * - */ -VOID -SaveDeviceContext ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN CALL_POINTS CallPoint, - OUT UINT32 *ActualBufferSize, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - DEVICE_DESCRIPTORS Device; - UINT16 i; - UINT64 StartAddress; - UINT64 EndAddress; - VOID *OrMask; - - StartAddress = (UINT64)(intptr_t)DeviceList; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; - - // Process Pre ESR List - for (i = 0; i < DeviceList->NumDevices; i++) { - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI_PRE_ESR: - SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context - case DEV_TYPE_PCI: - Device.PciDevice++; - break; - case DEV_TYPE_CPCI_PRE_ESR: - SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context - case DEV_TYPE_CPCI: - Device.CPciDevice++; - break; - case DEV_TYPE_MSR_PRE_ESR: - SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context - case DEV_TYPE_MSR: - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR_PRE_ESR: - SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context - case DEV_TYPE_CMSR: - Device.CMsrDevice++; - break; - } - } - - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - // Process Post ESR List - for (i = 0; i < DeviceList->NumDevices; i++) { - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI: - SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context - case DEV_TYPE_PCI_PRE_ESR: - Device.PciDevice++; - break; - case DEV_TYPE_CPCI: - SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context - case DEV_TYPE_CPCI_PRE_ESR: - Device.CPciDevice++; - break; - case DEV_TYPE_MSR: - SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context - case DEV_TYPE_MSR_PRE_ESR: - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR: - SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context - case DEV_TYPE_CMSR_PRE_ESR: - Device.CMsrDevice++; - break; - } - } - EndAddress = (UINT64)(intptr_t)OrMask; - *ActualBufferSize = (UINT32) (EndAddress - StartAddress); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves the context of a PCI device. - * - * This traverses the provided register list saving PCI registers. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device PCI device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -SavePciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ) -{ - UINT8 RegSizeInBytes; - UINT8 SpecialCaseIndex; - UINT8 *IntermediatePtr; - UINT16 i; - UINT32 Socket; - UINT32 Module; - UINT32 AndMask; - ACCESS_WIDTH AccessWidth; - AGESA_STATUS IgnoredSts; - PCI_ADDR PciAddress; - PCI_REGISTER_BLOCK_HEADER *RegisterHdr; - - GetSocketModuleOfNode ((UINT32) Device->Node, - &Socket, - &Module, - StdHeader); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - - if (CallPoint == INIT_RESUME) { - MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; - PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; - RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; - switch (RegSizeInBytes) { - case 1: - AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); - AccessWidth = AccessS3SaveWidth8; - break; - case 2: - AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); - AccessWidth = AccessS3SaveWidth16; - break; - case 3: - // In this case, we don't need to save a register. We just need to call a special - // function to do certain things in the save and resume sequence. - // This should not be used in a non-special case. - AndMask = 0; - RegSizeInBytes = 0; - AccessWidth = 0; - break; - default: - AndMask = RegisterHdr->RegisterList[i].AndMask; - RegSizeInBytes = 4; - AccessWidth = AccessS3SaveWidth32; - break; - } - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0)); - LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader); - } - if (AndMask != 0) { - // If AndMask is 0, then it is a not-care. Don't need to apply it to the OrMask - **((UINT32 **) OrMask) &= AndMask; - } - if ((RegSizeInBytes == 0) && (**((UINT32 **) OrMask) == RESTART_FROM_BEGINNING_LIST)) { - // Restart from the beginning of the register list - i = 0xFFFF; - } - IntermediatePtr = (UINT8 *) *OrMask; - *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves the context of a 'conditional' PCI device. - * - * This traverses the provided register list saving PCI registers when appropriate. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device 'conditional' PCI device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -SaveConditionalPciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ) -{ - UINT8 RegSizeInBytes; - UINT8 SpecialCaseIndex; - UINT8 *IntermediatePtr; - UINT16 i; - UINT32 Socket; - UINT32 Module; - UINT32 AndMask; - ACCESS_WIDTH AccessWidth; - AGESA_STATUS IgnoredSts; - PCI_ADDR PciAddress; - CPCI_REGISTER_BLOCK_HEADER *RegisterHdr; - - GetSocketModuleOfNode ((UINT32) Device->Node, - &Socket, - &Module, - StdHeader); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - - if (CallPoint == INIT_RESUME) { - MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && - ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { - PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; - PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; - RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; - switch (RegSizeInBytes) { - case 1: - AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); - AccessWidth = AccessS3SaveWidth8; - break; - case 2: - AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); - AccessWidth = AccessS3SaveWidth16; - break; - case 3: - // In this case, we don't need to save a register. We just need to call a special - // function to do certain things in the save and resume sequence. - // This should not be used in a non-special case. - AndMask = 0; - RegSizeInBytes = 0; - AccessWidth = 0; - break; - default: - AndMask = RegisterHdr->RegisterList[i].AndMask; - RegSizeInBytes = 4; - AccessWidth = AccessS3SaveWidth32; - break; - } - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0)); - LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader); - } - if (AndMask != 0) { - // If AndMask is 0, then it is a not-care. Don't need to apply it to the OrMask - **((UINT32 **) OrMask) &= AndMask; - } - if ((RegSizeInBytes == 0) && (**((UINT32 **) OrMask) == RESTART_FROM_BEGINNING_LIST)) { - // Restart from the beginning of the register list - i = 0xFFFF; - } - IntermediatePtr = (UINT8 *) *OrMask; - *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves the context of an MSR device. - * - * This traverses the provided register list saving MSRs. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device MSR device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -SaveMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ) -{ - UINT8 SpecialCaseIndex; - UINT16 i; - MSR_REGISTER_BLOCK_HEADER *RegisterHdr; - - if (CallPoint == INIT_RESUME) { - MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader); - } - **OrMask &= RegisterHdr->RegisterList[i].AndMask; - (*OrMask)++; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Saves the context of a 'conditional' MSR device. - * - * This traverses the provided register list saving MSRs when appropriate. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device 'conditional' MSR device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -SaveConditionalMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ) -{ - UINT8 SpecialCaseIndex; - UINT16 i; - CMSR_REGISTER_BLOCK_HEADER *RegisterHdr; - - if (CallPoint == INIT_RESUME) { - MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && - ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader); - } - **OrMask &= RegisterHdr->RegisterList[i].AndMask; - (*OrMask)++; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the maximum amount of space required to store all raw register - * values for the given device list. - * - * This traverses the entire device list, and calculates the worst case size - * of each device in the device list. - * - * @param[in] DeviceList Beginning of the device list. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in] StdHeader AMD standard header config param. - * - * @retval Size in bytes required for storing all registers. - */ -UINT32 -GetWorstCaseContextSize ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 WorstCaseSize; - DEVICE_DESCRIPTORS Device; - UINT16 i; - REGISTER_BLOCK_HEADERS RegisterHdr; - - WorstCaseSize = DeviceList->RelativeOrMaskOffset; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - - // Process Device List - for (i = 0; i < DeviceList->NumDevices; i++) { - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI_PRE_ESR: - // PRE_ESR and post ESR take the same amount of space - case DEV_TYPE_PCI: - if (CallPoint == INIT_RESUME) { - MemFS3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader); - } else { - S3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader); - } - WorstCaseSize += (RegisterHdr.PciRegisters->NumRegisters * 4); - Device.PciDevice++; - break; - case DEV_TYPE_CPCI_PRE_ESR: - // PRE_ESR and post ESR take the same amount of space - case DEV_TYPE_CPCI: - if (CallPoint == INIT_RESUME) { - MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader); - } else { - S3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader); - } - WorstCaseSize += (RegisterHdr.CPciRegisters->NumRegisters * 4); - Device.CPciDevice++; - break; - case DEV_TYPE_MSR_PRE_ESR: - // PRE_ESR and post ESR take the same amount of space - case DEV_TYPE_MSR: - if (CallPoint == INIT_RESUME) { - MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader); - } else { - S3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader); - } - WorstCaseSize += (RegisterHdr.MsrRegisters->NumRegisters * 8); - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR_PRE_ESR: - // PRE_ESR and post ESR take the same amount of space - case DEV_TYPE_CMSR: - if (CallPoint == INIT_RESUME) { - MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader); - } else { - S3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader); - } - WorstCaseSize += (RegisterHdr.CMsrRegisters->NumRegisters * 8); - Device.CMsrDevice++; - break; - default: - ASSERT (FALSE); - } - } - return (WorstCaseSize); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores all devices marked as 'before exiting self-refresh.' - * - * This traverses the entire device list, restoring all devices identified - * as Pre ESR. - * - * @param[in,out] OrMaskPtr Current buffer pointer of raw register values. - * @param[in] Storage Beginning of the device list. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in] StdHeader AMD standard header config param. - * - */ -VOID -RestorePreESRContext ( - OUT VOID **OrMaskPtr, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - DEVICE_DESCRIPTORS Device; - UINT16 i; - DEVICE_BLOCK_HEADER *DeviceList; - - DeviceList = (DEVICE_BLOCK_HEADER *) Storage; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - *OrMaskPtr = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; - - // Process Pre ESR List - for (i = 0; i < DeviceList->NumDevices; i++) { - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI_PRE_ESR: - RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, OrMaskPtr); - // Fall through to advance the pointer after restoring context - case DEV_TYPE_PCI: - Device.PciDevice++; - break; - case DEV_TYPE_CPCI_PRE_ESR: - RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, OrMaskPtr); - // Fall through to advance the pointer after restoring context - case DEV_TYPE_CPCI: - Device.CPciDevice++; - break; - case DEV_TYPE_MSR_PRE_ESR: - RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // Fall through to advance the pointer after restoring context - case DEV_TYPE_MSR: - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR_PRE_ESR: - RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // Fall through to advance the pointer after restoring context - case DEV_TYPE_CMSR: - Device.CMsrDevice++; - break; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores all devices marked as 'after exiting self-refresh.' - * - * This traverses the entire device list, restoring all devices identified - * as Post ESR. - * - * @param[in] OrMaskPtr Current buffer pointer of raw register values. - * @param[in] Storage Beginning of the device list. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in] StdHeader AMD standard header config param. - * - */ -VOID -RestorePostESRContext ( - IN VOID *OrMaskPtr, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - DEVICE_DESCRIPTORS Device; - UINT16 i; - DEVICE_BLOCK_HEADER *DeviceList; - - DeviceList = (DEVICE_BLOCK_HEADER *) Storage; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - - // Process Pre ESR List - for (i = 0; i < DeviceList->NumDevices; i++) { - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI: - RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMaskPtr); - // Fall through to advance the pointer after restoring context - case DEV_TYPE_PCI_PRE_ESR: - Device.PciDevice++; - break; - case DEV_TYPE_CPCI: - RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMaskPtr); - // Fall through to advance the pointer after restoring context - case DEV_TYPE_CPCI_PRE_ESR: - Device.CPciDevice++; - break; - case DEV_TYPE_MSR: - RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // Fall through to advance the pointer after restoring context - case DEV_TYPE_MSR_PRE_ESR: - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR: - RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // Fall through to advance the pointer after restoring context - case DEV_TYPE_CMSR_PRE_ESR: - Device.CMsrDevice++; - break; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores the context of a PCI device. - * - * This traverses the provided register list restoring PCI registers. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device 'conditional' PCI device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -RestorePciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ) -{ - UINT8 RegSizeInBytes; - UINT8 SpecialCaseIndex; - UINT8 *IntermediatePtr; - UINT16 i; - UINT32 Socket; - UINT32 Module; - UINT32 AndMask; - UINT32 RegValueRead; - UINT32 RegValueWrite; - ACCESS_WIDTH AccessWidth; - AGESA_STATUS IgnoredSts; - PCI_ADDR PciAddress; - PCI_REGISTER_BLOCK_HEADER *RegisterHdr; - - GetSocketModuleOfNode ((UINT32) Device->Node, - &Socket, - &Module, - StdHeader); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - - if (CallPoint == INIT_RESUME) { - MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; - PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; - RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; - switch (RegSizeInBytes) { - case 1: - AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); - RegValueWrite = **(UINT8 **)OrMask; - AccessWidth = AccessS3SaveWidth8; - break; - case 2: - AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); - RegValueWrite = **(UINT16 **)OrMask; - AccessWidth = AccessS3SaveWidth16; - break; - case 3: - // In this case, we don't need to restore a register. We just need to call a special - // function to do certain things in the save and resume sequence. - // This should not be used in a non-special case. - AndMask = 0; - RegValueWrite = 0; - RegSizeInBytes = 0; - AccessWidth = 0; - break; - default: - AndMask = RegisterHdr->RegisterList[i].AndMask; - RegSizeInBytes = 4; - RegValueWrite = **(UINT32 **)OrMask; - AccessWidth = AccessS3SaveWidth32; - break; - } - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0)); - LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader); - RegValueWrite |= RegValueRead & (~AndMask); - LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - if (AndMask != 0) { - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, - PciAddress, - &RegValueRead, - StdHeader); - RegValueWrite |= RegValueRead & (~AndMask); - } - RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth, - PciAddress, - &RegValueWrite, - StdHeader); - } - IntermediatePtr = (UINT8 *) *OrMask; - *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes; - if ((RegSizeInBytes == 0) && (RegValueWrite == RESTART_FROM_BEGINNING_LIST)) { - // Restart from the beginning of the register list - i = 0xFFFF; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores the context of a 'conditional' PCI device. - * - * This traverses the provided register list restoring PCI registers when appropriate. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device 'conditional' PCI device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -RestoreConditionalPciDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT VOID **OrMask - ) -{ - UINT8 RegSizeInBytes; - UINT8 SpecialCaseIndex; - UINT8 *IntermediatePtr; - UINT16 i; - UINT32 Socket; - UINT32 Module; - UINT32 RegValueRead; - UINT32 RegValueWrite; - UINT32 AndMask; - ACCESS_WIDTH AccessWidth; - AGESA_STATUS IgnoredSts; - PCI_ADDR PciAddress; - CPCI_REGISTER_BLOCK_HEADER *RegisterHdr; - - GetSocketModuleOfNode ((UINT32) Device->Node, - &Socket, - &Module, - StdHeader); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - - if (CallPoint == INIT_RESUME) { - MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && - ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { - PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; - PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; - RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; - switch (RegSizeInBytes) { - case 1: - AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); - RegValueWrite = **(UINT8 **)OrMask; - AccessWidth = AccessS3SaveWidth8; - break; - case 2: - AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); - RegValueWrite = **(UINT16 **)OrMask; - AccessWidth = AccessS3SaveWidth16; - break; - case 3: - // In this case, we don't need to restore a register. We just need to call a special - // function to do certain things in the save and resume sequence. - // This should not be used in a non-special case. - AndMask = 0; - RegValueWrite = 0; - RegSizeInBytes = 0; - AccessWidth = 0; - break; - default: - AndMask = RegisterHdr->RegisterList[i].AndMask; - RegSizeInBytes = 4; - RegValueWrite = **(UINT32 **)OrMask; - AccessWidth = AccessS3SaveWidth32; - break; - } - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader); - RegValueWrite |= RegValueRead & (~AndMask); - LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - if (AndMask != 0) { - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, - PciAddress, - &RegValueRead, - StdHeader); - RegValueWrite |= RegValueRead & (~AndMask); - } - RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth, - PciAddress, - &RegValueWrite, - StdHeader); - } - IntermediatePtr = (UINT8 *) *OrMask; - *OrMask = &IntermediatePtr[RegSizeInBytes]; - if ((RegSizeInBytes == 0) && (RegValueWrite == RESTART_FROM_BEGINNING_LIST)) { - // Restart from the beginning of the register list - i = 0xFFFF; - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores the context of an MSR device. - * - * This traverses the provided register list restoring MSRs. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device MSR device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -RestoreMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ) -{ - UINT8 SpecialCaseIndex; - UINT16 i; - UINT64 RegValueRead; - UINT64 RegValueWrite; - MSR_REGISTER_BLOCK_HEADER *RegisterHdr; - - if (CallPoint == INIT_RESUME) { - MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - RegValueWrite = **OrMask; - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader); - RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); - LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, - &RegValueRead, - StdHeader); - RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); - RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address, - &RegValueWrite, - StdHeader); - } - (*OrMask)++; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores the context of a 'conditional' MSR device. - * - * This traverses the provided register list restoring MSRs when appropriate. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in] Device 'conditional' MSR device to restore. - * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or - * AMD_S3LATE_RESTORE. - * @param[in,out] OrMask Current buffer pointer of raw register values. - * - */ -VOID -RestoreConditionalMsrDevice ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - IN CALL_POINTS CallPoint, - IN OUT UINT64 **OrMask - ) -{ - UINT8 SpecialCaseIndex; - UINT16 i; - UINT64 RegValueRead; - UINT64 RegValueWrite; - CMSR_REGISTER_BLOCK_HEADER *RegisterHdr; - - if (CallPoint == INIT_RESUME) { - MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } else { - S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); - } - - for (i = 0; i < RegisterHdr->NumRegisters; i++) { - if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && - ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { - RegValueWrite = **OrMask; - if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { - LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader); - RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); - LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader); - } else { - SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; - RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, - &RegValueRead, - StdHeader); - RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); - RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address, - &RegValueWrite, - StdHeader); - } - (*OrMask)++; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Unique device ID to PCI register list translator. - * - * This translates the given device header in storage to the appropriate list - * of registers in the AGESA image. - * - * @param[out] NonMemoryRelatedDeviceList List of devices to save and restore - * during S3LateRestore. - * @param[in] StdHeader AMD standard header config param. - * - */ -VOID -GetNonMemoryRelatedDeviceList ( - OUT DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NonMemoryRelatedDeviceList = NULL; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Unique device ID to PCI register list translator. - * - * This translates the given device header in storage to the appropriate list - * of registers in the AGESA image. - * - * @param[in] Device Device header containing the unique ID. - * @param[out] RegisterHdr Output PCI register list pointer. - * @param[in] StdHeader AMD standard header config param. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -S3GetPciDeviceRegisterList ( - IN PCI_DEVICE_DESCRIPTOR *Device, - OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *RegisterHdr = NULL; - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Unique device ID to 'conditional' PCI register list translator. - * - * This translates the given device header in storage to the appropriate list - * of registers in the AGESA image. - * - * @param[in] Device Device header containing the unique ID. - * @param[out] RegisterHdr Output 'conditional' PCI register list pointer. - * @param[in] StdHeader AMD standard header config param. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -S3GetCPciDeviceRegisterList ( - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *RegisterHdr = NULL; - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Unique device ID to MSR register list translator. - * - * This translates the given device header in storage to the appropriate list - * of registers in the AGESA image. - * - * @param[in] Device Device header containing the unique ID. - * @param[out] RegisterHdr Output MSR register list pointer. - * @param[in] StdHeader AMD standard header config param. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -S3GetMsrDeviceRegisterList ( - IN MSR_DEVICE_DESCRIPTOR *Device, - OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *RegisterHdr = NULL; - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Unique device ID to 'conditional' MSR register list translator. - * - * This translates the given device header in storage to the appropriate list - * of registers in the AGESA image. - * - * @param[in] Device Device header containing the unique ID. - * @param[out] RegisterHdr Output 'conditional' MSR register list pointer. - * @param[in] StdHeader AMD standard header config param. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -S3GetCMsrDeviceRegisterList ( - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *RegisterHdr = NULL; - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Constructor for the AMD_S3_PARAMS structure. - * - * This routine initializes failsafe values for the AMD_S3_PARAMS structure - * to be used by the AMD_INIT_RESUME, AMD_S3_SAVE, and AMD_S3LATE_RESTORE - * entry points. - * - * @param[in,out] S3Params Required input parameter for the AMD_S3_SAVE, - * AMD_INIT_RESUME, and AMD_S3_SAVE entry points. - * - */ -VOID -AmdS3ParamsInitializer ( - OUT AMD_S3_PARAMS *S3Params - ) -{ - S3Params->Signature = 0x52545341; - S3Params->Version = 0x0000; - S3Params->VolatileStorage = NULL; - S3Params->VolatileStorageSize = 0x00000000; - S3Params->Flags = 0x00000000; - S3Params->NvStorage = NULL; - S3Params->NvStorageSize = 0x00000000; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.h deleted file mode 100644 index decac8a777..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/S3.h +++ /dev/null @@ -1,395 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * ACPI S3 support definitions. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 49927 $ @e \$Date: 2011-03-30 11:27:42 -0600 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _S3_H_ -#define _S3_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -#define RESTART_FROM_BEGINNING_LIST 0xFFFFFFFF - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -/* Device related definitions */ - -/// Header at the beginning of a context save buffer. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumDevices; ///< Number of devices in the list - UINT16 RelativeOrMaskOffset; ///< Size of device list + header -} DEVICE_BLOCK_HEADER; - -/// S3 device types -typedef enum { - DEV_TYPE_PCI_PRE_ESR, ///< PCI device before exiting self-refresh - DEV_TYPE_PCI, ///< PCI device after exiting self-refresh - DEV_TYPE_CPCI_PRE_ESR, ///< 'conditional' PCI device before exiting self-refresh - DEV_TYPE_CPCI, ///< 'conditional' PCI device after exiting self-refresh - DEV_TYPE_MSR_PRE_ESR, ///< MSR device before exiting self-refresh - DEV_TYPE_MSR, ///< MSR device after exiting self-refresh - DEV_TYPE_CMSR_PRE_ESR, ///< 'conditional' MSR device before exiting self-refresh - DEV_TYPE_CMSR ///< 'conditional' MSR device after exiting self-refresh -} S3_DEVICE_TYPES; - -/// S3 restoration call points -typedef enum { - INIT_RESUME, ///< AMD_INIT_RESUME - S3_LATE_RESTORE ///< AMD_S3LATE_RESTORE -} CALL_POINTS; - -/// S3 device common header -typedef struct { - UINT32 RegisterListID; ///< Unique ID of this device - UINT8 Type; ///< Appropriate S3_DEVICE_TYPES type -} DEVICE_DESCRIPTOR; - -/// S3 PCI device header -typedef struct { - UINT32 RegisterListID; ///< Unique ID of this device - UINT8 Type; ///< DEV_TYPE_PCI / DEV_TYPE_PCI_PRE_ESR - UINT8 Node; ///< Zero-based node number -} PCI_DEVICE_DESCRIPTOR; - -/// S3 'conditional' PCI device header -typedef struct { - UINT32 RegisterListID; ///< Unique ID of this device - UINT8 Type; ///< DEV_TYPE_CPCI / DEV_TYPE_CPCI_PRE_ESR - UINT8 Node; ///< Zero-based node number - UINT8 Mask1; ///< Conditional mask 1 - UINT8 Mask2; ///< Conditional mask 2 -} CONDITIONAL_PCI_DEVICE_DESCRIPTOR; - -/// S3 MSR device header -typedef struct { - UINT32 RegisterListID; ///< Unique ID of this device - UINT8 Type; ///< DEV_TYPE_MSR / DEV_TYPE_MSR_PRE_ESR -} MSR_DEVICE_DESCRIPTOR; - -/// S3 'conditional' MSR device header -typedef struct { - UINT32 RegisterListID; ///< Unique ID of this device - UINT8 Type; ///< DEV_TYPE_CMSR / DEV_TYPE_CMSR_PRE_ESR - UINT8 Mask1; ///< Conditional mask 1 - UINT8 Mask2; ///< Conditional mask 2 -} CONDITIONAL_MSR_DEVICE_DESCRIPTOR; - -/* Special case related definitions */ - -/** - * PCI special case save handler - * - * @param[in] AccessWidth 8, 16, or 32 bit wide access - * @param[in] Address full PCI address of the register to save - * @param[out] Value Value read from the register - * @param[in] ConfigPtr AMD standard header config parameter - * - */ -typedef VOID (*PF_S3_SPECIAL_PCI_SAVE) ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - OUT VOID *Value, - IN VOID *ConfigPtr - ); - -/** - * PCI special case restore handler - * - * @param[in] AccessWidth 8, 16, or 32 bit wide access - * @param[in] Address full PCI address of the register to save - * @param[in] Value Value to write to the register - * @param[in] ConfigPtr AMD standard header config parameter - * - */ -typedef VOID (*PF_S3_SPECIAL_PCI_RESTORE) ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR PciAddress, - IN VOID *Value, - IN VOID *StdHeader - ); - -/** - * MSR special case save handler - * - * @param[in] MsrAddress Address of model specific register to save - * @param[out] Value Value read from the register - * @param[in] ConfigPtr AMD standard header config parameter - * - */ -typedef VOID (*PF_S3_SPECIAL_MSR_SAVE) ( - IN UINT32 MsrAddress, - OUT UINT64 *Value, - IN VOID *StdHeader - ); - -/** - * MSR special case restore handler - * - * @param[in] MsrAddress Address of model specific register to restore - * @param[in] Value Value to write to the register - * @param[in] ConfigPtr AMD standard header config parameter - * - */ -typedef VOID (*PF_S3_SPECIAL_MSR_RESTORE) ( - IN UINT32 MsrAddress, - IN UINT64 *Value, - IN VOID *StdHeader - ); - -/// PCI special case save/restore structure. -typedef struct { - PF_S3_SPECIAL_PCI_SAVE Save; ///< Save routine - PF_S3_SPECIAL_PCI_RESTORE Restore; ///< Restore routine -} PCI_SPECIAL_CASE; - -/// MSR special case save/restore structure. -typedef struct { - PF_S3_SPECIAL_MSR_SAVE Save; ///< Save routine - PF_S3_SPECIAL_MSR_RESTORE Restore; ///< Restore routine -} MSR_SPECIAL_CASE; - -/* Register related definitions */ -/// S3 register type bit fields -typedef struct { - UINT8 SpecialCaseIndex:4; ///< Special Case array index - UINT8 RegisterSize:3; ///< For PCI, 1 = byte, 2 = word, else = dword. - ///< For MSR, don't care - UINT8 SpecialCaseFlag:1; ///< Indicates special case -} S3_REGISTER_TYPE; - -/// S3 PCI register descriptor. -typedef struct { - S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, - ///< Type[6:3] = register size in bytes, - ///< Type[2:0] = special case index - UINT8 Function; ///< PCI function of the register - UINT16 Offset; ///< PCI offset of the register - UINT32 AndMask; ///< AND mask to be applied to the value before saving -} PCI_REG_DESCRIPTOR; - -/// S3 'conditional' PCI register descriptor. -typedef struct { - S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, - ///< Type[6:3] = register size in bytes, - ///< Type[2:0] = special case index - UINT8 Function; ///< PCI function of the register - UINT16 Offset; ///< PCI offset of the register - UINT32 AndMask; ///< AND mask to be applied to the value before saving - UINT8 Mask1; ///< conditional mask 1 - UINT8 Mask2; ///< conditional mask 2 -} CONDITIONAL_PCI_REG_DESCRIPTOR; - -/// S3 MSR register descriptor. -typedef struct { - S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, - ///< Type[6:3] = reserved, - ///< Type[2:0] = special case index - UINT32 Address; ///< MSR address - UINT64 AndMask; ///< AND mask to be applied to the value before saving -} MSR_REG_DESCRIPTOR; - -/// S3 'conditional' MSR register descriptor. -typedef struct { - S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, - ///< Type[6:3] = reserved, - ///< Type[2:0] = special case index - UINT32 Address; ///< MSR address - UINT64 AndMask; ///< AND mask to be applied to the value before saving - UINT8 Mask1; ///< conditional mask 1 - UINT8 Mask2; ///< conditional mask 2 -} CONDITIONAL_MSR_REG_DESCRIPTOR; - -/// Common header at the beginning of an S3 register list. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumRegisters; ///< Number of registers in the list -} REGISTER_BLOCK_HEADER; - -/// S3 PCI register list header. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumRegisters; ///< Number of registers in the list - PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers -} PCI_REGISTER_BLOCK_HEADER; - -/// S3 'conditional' PCI register list header. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumRegisters; ///< Number of registers in the list - CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers -} CPCI_REGISTER_BLOCK_HEADER; - -/// S3 MSR register list header. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumRegisters; ///< Number of registers in the list - MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers -} MSR_REGISTER_BLOCK_HEADER; - -/// S3 'conditional' MSR register list header. -typedef struct { - UINT16 Version; ///< Version of header - UINT16 NumRegisters; ///< Number of registers in the list - CONDITIONAL_MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers -} CMSR_REGISTER_BLOCK_HEADER; - -/// S3 device descriptor pointers for ease of proper pointer advancement. -typedef union { - DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header - PCI_DEVICE_DESCRIPTOR *PciDevice; ///< PCI header - CONDITIONAL_PCI_DEVICE_DESCRIPTOR *CPciDevice; ///< 'conditional' PCI header - MSR_DEVICE_DESCRIPTOR *MsrDevice; ///< MSR header - CONDITIONAL_MSR_DEVICE_DESCRIPTOR *CMsrDevice; ///< 'conditional' MSR header -} DEVICE_DESCRIPTORS; - -/// S3 register list header pointers for ease of proper pointer advancement. -typedef union { - DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header - PCI_REGISTER_BLOCK_HEADER *PciRegisters; ///< PCI header - CPCI_REGISTER_BLOCK_HEADER *CPciRegisters; ///< 'conditional' PCI header - MSR_REGISTER_BLOCK_HEADER *MsrRegisters; ///< MSR header - CMSR_REGISTER_BLOCK_HEADER *CMsrRegisters; ///< 'conditional' MSR header -} REGISTER_BLOCK_HEADERS; - -/// S3 Volatile Storage Header -typedef struct { - UINT32 HeapOffset; ///< Offset to beginning of heap data - UINT32 HeapSize; ///< Size of the heap data - UINT32 RegisterDataOffset; ///< Offset to beginning of raw save data - UINT32 RegisterDataSize; ///< Size of raw save data -} S3_VOLATILE_STORAGE_HEADER; - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -UINT32 -GetWorstCaseContextSize ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SaveDeviceListContext ( - IN DEVICE_BLOCK_HEADER *DeviceList, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - OUT UINT32 *ActualBufferSize, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -RestorePreESRContext ( - OUT VOID **OrMaskPtr, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -RestorePostESRContext ( - IN VOID *OrMaskPtr, - IN VOID *Storage, - IN CALL_POINTS CallPoint, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -AmdS3ParamsInitializer ( - OUT AMD_S3_PARAMS *S3Params - ); - -VOID -GetNonMemoryRelatedDeviceList ( - OUT DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -S3GetPciDeviceRegisterList ( - IN PCI_DEVICE_DESCRIPTOR *Device, - OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -S3GetCPciDeviceRegisterList ( - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -S3GetMsrDeviceRegisterList ( - IN MSR_DEVICE_DESCRIPTOR *Device, - OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -S3GetCMsrDeviceRegisterList ( - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -#endif // _S3_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.c deleted file mode 100644 index c1b25cb953..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.c +++ /dev/null @@ -1,1734 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Register Table Related Functions - * - * Set registers according to a set of register tables - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 59564 $ @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "OptionMultiSocket.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Table.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuFeatures.h" -#include "CommonReturns.h" -#include "cpuL3Features.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_TABLE_FILECODE - -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -SetRegistersFromTablesAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; -extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * An iterator for all the Family and Model Register Tables. - * - * RegisterTableHandle should be set to NULL to begin iteration, the first time the method is - * invoked. Register tables can be processed, until this method returns NULL. RegisterTableHandle - * should simply be passed back to the method without modification or use by the caller. - * The table selector allows the relevant tables for different cores to be iterated, if the family separates - * tables. For example, MSRs can be in a table processed by all cores and PCI registers in a table processed by - * primary cores. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Selector Select whether to iterate over tables for either all cores, primary cores, bsp, .... - * @param[in,out] RegisterTableHandle IN: The handle of the current register table, or NULL if Begin. - * OUT: The handle of the next register table, if not End. - * @param[out] NumberOfEntries The number of entries in the table returned, if not End. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The pointer to the next Register Table, or NULL if End. - */ -TABLE_ENTRY_FIELDS -STATIC -*GetNextRegisterTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN TABLE_CORE_SELECTOR Selector, - IN OUT REGISTER_TABLE ***RegisterTableHandle, - OUT UINTN *NumberOfEntries, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - REGISTER_TABLE **NextTable; - TABLE_ENTRY_FIELDS *Entries; - - ASSERT ((FamilySpecificServices != NULL) && (StdHeader != NULL)); - ASSERT (Selector < TableCoreSelectorMax); - - NextTable = *RegisterTableHandle; - if (NextTable == NULL) { - // Begin - NextTable = FamilySpecificServices->RegisterTableList; - IDS_OPTION_HOOK (IDS_REG_TABLE, &NextTable, StdHeader); - } else { - NextTable++; - } - // skip if not selected - while ((*NextTable != NULL) && (*NextTable)->Selector != Selector) { - NextTable++; - } - if (*NextTable == NULL) { - // End - *RegisterTableHandle = NULL; - Entries = NULL; - } else { - // Iterate next table - *RegisterTableHandle = NextTable; - *NumberOfEntries = (*NextTable)->NumberOfEntries; - Entries = (TABLE_ENTRY_FIELDS *) (*NextTable)->Table; - } - return Entries; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Compare counts to a pair of ranges. - * - * @param[in] FirstCount The actual count to be compared to the first range. - * @param[in] SecondCount The actual count to be compared to the second range. - * @param[in] Ranges The ranges which the counts are compared to. - * - * @retval TRUE Either one, or both, of the counts is in the range given. - * @retval FALSE Neither count is in the range given. - */ -BOOLEAN -IsEitherCountInRange ( - IN UINTN FirstCount, - IN UINTN SecondCount, - IN COUNT_RANGE_FEATURE Ranges - ) -{ - // Errors: Entire Range value is zero, Min and Max reversed or not <=, ranges overlap (OK if first range is all), - // the real counts are too big. - ASSERT ((Ranges.Range0Min <= Ranges.Range0Max) && - (Ranges.Range1Min <= Ranges.Range1Max) && - (Ranges.Range0Max != 0) && - (Ranges.Range1Max != 0) && - ((Ranges.Range0Max == COUNT_RANGE_HIGH) || (Ranges.Range0Max < Ranges.Range1Min)) && - ((FirstCount < COUNT_RANGE_HIGH) && (SecondCount < COUNT_RANGE_HIGH))); - - return (BOOLEAN) (((FirstCount <= Ranges.Range0Max) && (FirstCount >= Ranges.Range0Min)) || - ((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min))); -} - -/*-------------------------------------------------------------------------------------*/ -/** - * Returns the performance profile features list of the currently running processor core. - * - * @param[out] Features The performance profile features supported by this platform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Header for library and services - * - */ -VOID -GetPerformanceFeatures ( - OUT PERFORMANCE_PROFILE_FEATS *Features, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuidDataStruct; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - L3_FEATURE_FAMILY_SERVICES *FeatureFamilyServices; - - Features->PerformanceProfileValue = 0; - // Reflect Probe Filter Configuration. - Features->PerformanceProfileFeatures.ProbeFilter = 0; - if (IsFeatureEnabled (L3Features, PlatformConfig, StdHeader)) { - GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (CONST VOID **)&FeatureFamilyServices, StdHeader); - if ((FeatureFamilyServices != NULL) && - (FeatureFamilyServices->IsHtAssistSupported (FeatureFamilyServices, PlatformConfig, StdHeader))) { - Features->PerformanceProfileFeatures.ProbeFilter = 1; - } - } - - // Reflect Display Refresh Requests use 32 bytes Configuration. - Features->PerformanceProfileFeatures.RefreshRequest32Byte = 0; - if (PlatformConfig->PlatformProfile.Use32ByteRefresh) { - Features->PerformanceProfileFeatures.RefreshRequest32Byte = 1; - } - // Reflect Mct Isoc Read Priority set to variable Configuration. - Features->PerformanceProfileFeatures.MctIsocVariable = 0; - if (PlatformConfig->PlatformProfile.UseVariableMctIsocPriority) { - Features->PerformanceProfileFeatures.MctIsocVariable = 1; - } - // Indicate if this boot is a warm reset. - Features->PerformanceProfileFeatures.IsWarmReset = 0; - if (IsWarmReset (StdHeader)) { - Features->PerformanceProfileFeatures.IsWarmReset = 1; - } - - // Get L3 Cache present as indicated by CPUID - Features->PerformanceProfileFeatures.L3Cache = 0; - Features->PerformanceProfileFeatures.NoL3Cache = 1; - LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuidDataStruct, StdHeader); - if (((CpuidDataStruct.EDX_Reg & 0xFFFC0000) >> 18) != 0) { - Features->PerformanceProfileFeatures.L3Cache = 1; - Features->PerformanceProfileFeatures.NoL3Cache = 0; - } - - // Get VRM select high speed from build option. - Features->PerformanceProfileFeatures.VrmHighSpeed = 0; - if (PlatformConfig->VrmProperties[CoreVrm].HiSpeedEnable) { - Features->PerformanceProfileFeatures.VrmHighSpeed = 1; - } - - // Get some family, model specific performance type info. - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL); - - // Is the Northbridge P-State feature enabled - Features->PerformanceProfileFeatures.NbPstates = 0; - if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader)) { - Features->PerformanceProfileFeatures.NbPstates = 1; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the MSR Register Entry. - * - * @TableEntryTypeMethod{::MsrRegister}. - * - * Read - Modify - Write the MSR, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The MSR register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForMsrEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrData; - - // Even for only single bit fields, use those in the mask. "Mask nothing" is a bug, even if just by policy. - ASSERT (Entry->MsrEntry.Mask != 0); - - LibAmdMsrRead (Entry->MsrEntry.Address, &MsrData, StdHeader); - MsrData = MsrData & (~(Entry->MsrEntry.Mask)); - MsrData = MsrData | Entry->MsrEntry.Data; - LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the PCI Register Entry. - * - * @TableEntryTypeMethod{::PciRegister}. - * - * Make the current core's PCI address with the function and register for the entry. - * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempVar32_a; - UINT32 MySocket; - UINT32 MyModule; - UINT32 Ignored; - PCI_ADDR MyPciAddress; - AGESA_STATUS IgnoredSts; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - // Even for only single bit fields, use those in the mask. "Mask nothing" is a bug, even if just by policy. - ASSERT ((Entry->InitialValues[4] == 0) && - (Entry->InitialValues[3] == 0) && - (Entry->PciEntry.Mask != 0)); - - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->PciEntry; - - IDS_OPTION_HOOK (IDS_SET_PCI_REGISTER_ENTRY, &PciEntry, StdHeader); - - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredSts); - GetPciAddress (StdHeader, MySocket, MyModule, &MyPciAddress, &IgnoredSts); - MyPciAddress.Address.Function = PciEntry.PciEntry.Address.Address.Function; - MyPciAddress.Address.Register = PciEntry.PciEntry.Address.Address.Register; - LibAmdPciRead (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader); - TempVar32_a = TempVar32_a & (~(PciEntry.PciEntry.Mask)); - TempVar32_a = TempVar32_a | PciEntry.PciEntry.Data; - LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Family Specific Workaround Register Entry. - * - * @TableEntryTypeMethod{::FamSpecificWorkaround}. - * - * Call the function, passing the data. - * - * See if you can use the other entries or make an entry that covers the fix. - * After all, the purpose of having a table entry is to @b NOT have code which - * isn't generic feature code, but is family/model code specific to one case. - * - * @param[in] Entry The Family Specific Workaround register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForFamSpecificWorkaroundEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - ASSERT (Entry->FamSpecificEntry.DoAction != NULL); - - Entry->FamSpecificEntry.DoAction (Entry->FamSpecificEntry.Data, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Program HT Phy PCI registers using BKDG values. - * - * @TableEntryTypeMethod{::HtPhyRegister}. - * - * - * @param[in] Entry The type specific entry data to be implemented (that is written). - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config params for library, services. - * - */ -VOID -SetRegisterForHtPhyEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - PCI_ADDR CapabilitySet; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - BOOLEAN MatchedSublink1; - HT_FREQUENCIES Freq0; - HT_FREQUENCIES Freq1; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT ((Entry->InitialValues[4] == 0) && - ((Entry->HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL | HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) == 0) && - (Entry->HtPhyEntry.Address < HTPHY_REGISTER_MAX)); - - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - Link = 0; - while (FamilySpecificServices->NextLinkHasHtPhyFeats ( - FamilySpecificServices, - &CapabilitySet, - &Link, - &Entry->HtPhyEntry.TypeFeats, - &MatchedSublink1, - &Freq0, - &Freq1, - StdHeader)) { - FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &Entry->HtPhyEntry, CapabilitySet, Link, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Program a range of HT Phy PCI registers using BKDG values. - * - * @TableEntryTypeMethod{::HtPhyRangeRegister}. - * - * - * @param[in] Entry The type specific entry data to be implemented (that is written). - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config params for library, services. - * - */ -VOID -SetRegisterForHtPhyRangeEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - PCI_ADDR CapabilitySet; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - HT_PHY_TYPE_ENTRY_DATA CurrentHtPhyRegister; - BOOLEAN MatchedSublink1; - HT_FREQUENCIES Freq0; - HT_FREQUENCIES Freq1; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->HtPhyRangeEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) && - (Entry->HtPhyRangeEntry.LowAddress <= Entry->HtPhyRangeEntry.HighAddress) && - (Entry->HtPhyRangeEntry.HighAddress < HTPHY_REGISTER_MAX) && - (Entry->HtPhyRangeEntry.HighAddress != 0)); - - CurrentHtPhyRegister.Mask = Entry->HtPhyRangeEntry.Mask; - CurrentHtPhyRegister.Data = Entry->HtPhyRangeEntry.Data; - CurrentHtPhyRegister.TypeFeats = Entry->HtPhyRangeEntry.TypeFeats; - - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - Link = 0; - while (FamilySpecificServices->NextLinkHasHtPhyFeats ( - FamilySpecificServices, - &CapabilitySet, - &Link, - &Entry->HtPhyRangeEntry.TypeFeats, - &MatchedSublink1, - &Freq0, - &Freq1, - StdHeader)) { - for (CurrentHtPhyRegister.Address = Entry->HtPhyRangeEntry.LowAddress; - CurrentHtPhyRegister.Address <= Entry->HtPhyRangeEntry.HighAddress; - CurrentHtPhyRegister.Address++) { - FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &CurrentHtPhyRegister, CapabilitySet, Link, StdHeader); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Is PackageLink an Internal Link? - * - * This is a test for the logical link match codes in the user interface, not a test for - * the actual northbridge links. - * - * @param[in] PackageLink The link - * - * @retval TRUE This is an internal link - * @retval FALSE This is not an internal link - */ -BOOLEAN -STATIC -IsDeemphasisLinkInternal ( - IN UINT32 PackageLink - ) -{ - return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the Package Link number, for the current node and real link number. - * - * Based on the link to package link mapping from BKDG, look up package link for - * the input link on the internal node number corresponding to the current core's node. - * For single module processors, the northbridge link and package link are the same. - * - * @param[in] Link the link on the current node. - * @param[in] FamilySpecificServices CPU specific support interface. - * @param[in] StdHeader Config params for library, services. - * - * @return the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link. - * - */ -UINT32 -STATIC -LookupPackageLink ( - IN UINT32 Link, - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 PackageLinkMapItem; - UINT32 PackageLink; - AP_MAIL_INFO ApMailbox; - - PackageLink = HT_LIST_TERMINAL; - - GetApMailbox (&ApMailbox.Info, StdHeader); - - if (ApMailbox.Fields.ModuleType != 0) { - ASSERT (FamilySpecificServices->PackageLinkMap != NULL); - // Use table to find this module's package link - PackageLinkMapItem = 0; - while ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) { - if (((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Module == ApMailbox.Fields.Module) && - ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link == Link)) { - PackageLink = (*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].PackageLink; - break; - } - PackageLinkMapItem++; - } - } else { - PackageLink = Link; - } - return PackageLink; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the platform's specified deemphasis levels for the current link. - * - * Search the platform's list for a match to the current link and also matching frequency. - * If a match is found, use the specified deemphasis levels. - * - * @param[in] Socket The current Socket. - * @param[in] Link The link on that socket. - * @param[in] Frequency The frequency the link is set to. - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] FamilySpecificServices CPU specific support interface. - * @param[in] StdHeader Config params for library, services. - * - * @return The Deemphasis values for the link. - */ -UINT32 -STATIC -GetLinkDeemphasis ( - IN UINT32 Socket, - IN UINT32 Link, - IN HT_FREQUENCIES Frequency, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Result; - CPU_HT_DEEMPHASIS_LEVEL *Match; - UINT32 PackageLink; - - PackageLink = LookupPackageLink (Link, FamilySpecificServices, StdHeader); - // All External and Internal links have deemphasis level none as the default. - // However, it is expected that the platform BIOS will provide deemphasis levels for the external links. - Result = ((DCV_LEVEL_NONE) | (DEEMPHASIS_LEVEL_NONE)); - - if (PlatformConfig->PlatformDeemphasisList != NULL) { - Match = PlatformConfig->PlatformDeemphasisList; - while (Match->Socket != HT_LIST_TERMINAL) { - if (((Match->Socket == Socket) || (Match->Socket == HT_LIST_MATCH_ANY)) && - ((Match->Link == PackageLink) || - ((Match->Link == HT_LIST_MATCH_ANY) && (!IsDeemphasisLinkInternal (PackageLink))) || - ((Match->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsDeemphasisLinkInternal (PackageLink)))) && - ((Match->LoFreq <= Frequency) && (Match->HighFreq >= Frequency))) { - // Found a match, get the deemphasis value. - ASSERT ((MaxPlatformDeemphasisLevel > Match->DcvDeemphasis) | (MaxPlatformDeemphasisLevel > Match->ReceiverDeemphasis)); - Result = ((1 << Match->DcvDeemphasis) | (1 << Match->ReceiverDeemphasis)); - break; - } else { - Match++; - } - } - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Program Deemphasis registers using BKDG values, for the platform specified levels. - * - * @TableEntryTypeMethod{::DeemphasisRegister}. - * - * - * @param[in] Entry The type specific entry data to be implemented (that is written). - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config params for library, services. - * - */ -VOID -SetRegisterForDeemphasisEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - PCI_ADDR CapabilitySet; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - BOOLEAN MatchedSublink1; - HT_FREQUENCIES Freq0; - HT_FREQUENCIES Freq1; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->DeemphasisEntry.Levels.DeemphasisValues & ~(VALID_DEEMPHASIS_LEVELS)) == 0) && - ((Entry->DeemphasisEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) && - (Entry->DeemphasisEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX)); - - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - Link = 0; - while (FamilySpecificServices->NextLinkHasHtPhyFeats ( - FamilySpecificServices, - &CapabilitySet, - &Link, - &Entry->DeemphasisEntry.HtPhyEntry.TypeFeats, - &MatchedSublink1, - &Freq0, - &Freq1, - StdHeader)) { - if (DoesEntryTypeSpecificInfoMatch ( - GetLinkDeemphasis ( - MySocket, - (MatchedSublink1 ? (Link + 4) : Link), - (MatchedSublink1 ? Freq1 : Freq0), - PlatformConfig, - FamilySpecificServices, - StdHeader), - Entry->DeemphasisEntry.Levels.DeemphasisValues)) { - FamilySpecificServices->SetHtPhyRegister ( - FamilySpecificServices, - &Entry->DeemphasisEntry.HtPhyEntry, - CapabilitySet, - Link, - StdHeader - ); - IDS_HDT_CONSOLE (HT_TRACE, "Socket %d Module %d Sub-link %1d :\n ----> running on HT3, %s Level is %s\n", - MySocket, MyModule, - ((Entry->DeemphasisEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & HTPHY_LINKTYPE_SL0_ALL) != 0) ? Link : (Link + 4), - ((Entry->DeemphasisEntry.Levels.DeemphasisValues & DCV_LEVELS_ALL) != 0) ? "DCV" : "Deemphasis", - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL_NONE) ? " 0 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__3) ? " - 3 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__6) ? " - 6 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__6) ? " - 6 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__8) ? " - 8 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__11) ? " - 11 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__11_8) ? " - 11 dB postcursor with - 8 dB precursor" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL_NONE) ? " 0 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__2) ? " - 2 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__3) ? " - 3 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__5) ? " - 5 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__6) ? " - 6 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__7) ? " - 7 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__8) ? " - 8 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__9) ? " - 9 dB" : - (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__11) ? " - 11 dB" : "Undefined"); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Program HT Phy PCI registers which have complex frequency dependencies. - * - * @TableEntryTypeMethod{::HtPhyFreqRegister}. - * - * After matching a link for HT Features, check if the HT frequency matches the given range. - * If it does, get the northbridge frequency limits for implemented NB P-states and check if - * each matches the given range - range 0 and range 1 for each NB frequency, respectively. - * If all matches, apply the entry. - * - * @param[in] Entry The type specific entry data to be implemented (that is written). - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config params for library, services. - * - */ -VOID -SetRegisterForHtPhyFreqEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - PCI_ADDR CapabilitySet; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - BOOLEAN MatchedSublink1; - HT_FREQUENCIES Freq0; - HT_FREQUENCIES Freq1; - BOOLEAN Temp1; - BOOLEAN Temp2; - UINT32 NbFreq0; - UINT32 NbFreq1; - UINT32 NbDivisor0; - UINT32 NbDivisor1; - - // Errors: extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) && - (Entry->HtPhyFreqEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX)); - - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - Link = 0; - while (FamilySpecificServices->NextLinkHasHtPhyFeats ( - FamilySpecificServices, - &CapabilitySet, - &Link, - &Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats, - &MatchedSublink1, - &Freq0, - &Freq1, - StdHeader)) { - // Check the HT Frequency for match to the range. - if (IsEitherCountInRange ( - (MatchedSublink1 ? Freq1 : Freq0), - (MatchedSublink1 ? Freq1 : Freq0), - Entry->HtPhyFreqEntry.HtFreqCounts.HtFreqCountRanges)) { - // Get the NB Frequency, convert to 100's of MHz, then convert to equivalent HT encoding. This supports - // NB frequencies from 800 MHz to 2600 MHz, which is currently greater than any processor supports. - OptionMultiSocketConfiguration.GetSystemNbPstateSettings ( - (UINT32) 0, - PlatformConfig, - &NbFreq0, - &NbDivisor0, - &Temp1, - &Temp2, - StdHeader); - - if (OptionMultiSocketConfiguration.GetSystemNbPstateSettings ( - (UINT32) 1, - PlatformConfig, - &NbFreq1, - &NbDivisor1, - &Temp1, - &Temp2, - StdHeader)) { - ASSERT (NbDivisor1 != 0); - NbFreq1 = (NbFreq1 / NbDivisor1); - NbFreq1 = (NbFreq1 / 100); - NbFreq1 = (NbFreq1 / 2) + 1; - } else { - NbFreq1 = 0; - } - - ASSERT (NbDivisor0 != 0); - NbFreq0 = (NbFreq0 / NbDivisor0); - NbFreq0 = (NbFreq0 / 100); - NbFreq0 = (NbFreq0 / 2) + 1; - if (IsEitherCountInRange (NbFreq0, NbFreq1, Entry->HtPhyFreqEntry.NbFreqCounts.HtFreqCountRanges)) { - FamilySpecificServices->SetHtPhyRegister ( - FamilySpecificServices, - &Entry->HtPhyFreqEntry.HtPhyEntry, - CapabilitySet, - Link, - StdHeader); - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Performance Profile PCI Register Entry. - * - * @TableEntryTypeMethod{::ProfileFixup}. - * - * Check the entry's performance profile features to the platform's and do the - * PCI register entry if they match. - * - * @param[in] Entry The Performance Profile register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForPerformanceProfileEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) && - (Entry->InitialValues[4] == 0)); - - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, - Entry->FixupEntry.TypeFeats.PerformanceProfileValue)) { - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->FixupEntry.PciEntry; - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the HT Phy Performance Profile Register Entry. - * - * @TableEntryTypeMethod{::HtPhyProfileRegister}. - * - * @param[in] Entry The HT Phy register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtPhyProfileEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - TABLE_ENTRY_DATA HtPhyEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) && - (Entry->InitialValues[5] == 0)); - - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch ( - PlatformProfile.PerformanceProfileValue, - Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue)) { - LibAmdMemFill (&HtPhyEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - HtPhyEntry.HtPhyEntry = Entry->HtPhyProfileEntry.HtPhyEntry; - SetRegisterForHtPhyEntry (&HtPhyEntry, PlatformConfig, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the HT Host PCI Register Entry. - * - * @TableEntryTypeMethod{::HtHostPciRegister}. - * - * Make the current core's PCI address with the function and register for the entry. - * For all HT links, check the link's feature set for a match to the entry. - * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtHostEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PCI_ADDR CapabilitySet; - PCI_ADDR PciAddress; - HT_HOST_FEATS HtHostFeats; - UINT32 RegisterData; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT ((Entry->InitialValues[4] == 0) && - ((Entry->HtHostEntry.TypeFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) && - (Entry->HtHostEntry.Address.Address.Register < HT_LINK_HOST_CAP_MAX)); - - HtHostFeats.HtHostValue = 0; - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - Link = 0; - while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { - if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtHostEntry.TypeFeats.HtHostValue)) { - // Do the HT Host PCI register update. - PciAddress = CapabilitySet; - PciAddress.Address.Register += Entry->HtHostEntry.Address.Address.Register; - LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader); - RegisterData = RegisterData & (~(Entry->HtHostEntry.Mask)); - RegisterData = RegisterData | Entry->HtHostEntry.Data; - LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the HT Host Performance PCI Register Entry. - * - * @TableEntryTypeMethod{::HtHostPerfPciRegister}. - * - * Make the current core's PCI address with the function and register for the entry. - * For all HT links, check the link's feature set for a match to the entry. - * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtHostPerfEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - TABLE_ENTRY_DATA HtHostPciTypeEntryData; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT ((Entry->InitialValues[5] == 0) && - ((Entry->HtHostEntry.TypeFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) && - (Entry->HtHostEntry.Address.Address.Register < HT_LINK_HOST_CAP_MAX)); - - // Check for any performance profile features. - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, - Entry->HtHostPerfEntry.PerformanceFeats.PerformanceProfileValue)) { - // Perform HT Host entry process. - LibAmdMemFill (&HtHostPciTypeEntryData, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - HtHostPciTypeEntryData.HtHostEntry = Entry->HtHostPerfEntry.HtHostEntry; - SetRegisterForHtHostEntry (&HtHostPciTypeEntryData, PlatformConfig, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set the HT Link Token Count registers. - * - * @TableEntryTypeMethod{::HtTokenPciRegister}. - * - * Make the current core's PCI address with the function and register for the entry. - * Check the performance profile features. - * For all HT links, check the link's feature set for a match to the entry. - * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The Link Token register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtLinkTokenEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PCI_ADDR CapabilitySet; - HT_HOST_FEATS HtHostFeats; - PERFORMANCE_PROFILE_FEATS PlatformProfile; - UINTN ProcessorCount; - UINTN SystemDegree; - UINT32 RegisterData; - PCI_ADDR PciAddress; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->HtTokenEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) && - ((Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) && - (Entry->HtTokenEntry.Mask != 0)); - - HtHostFeats.HtHostValue = 0; - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - // Check if the actual processor count and SystemDegree are in either range. - ProcessorCount = GetNumberOfProcessors (StdHeader); - SystemDegree = GetSystemDegree (StdHeader); - if (IsEitherCountInRange (ProcessorCount, SystemDegree, Entry->HtTokenEntry.ConnectivityCount.ConnectivityCountRanges)) { - // Check for any performance profile features. - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, - Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue)) { - // Check the link features. - Link = 0; - while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { - if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtTokenEntry.LinkFeats.HtHostValue)) { - // Do the HT Host PCI register update. Token register are four registers, sublink 0 and 1 share fields. - // If sublink 0 is unconnected, we should let sublink 1 match. If the links are ganged, of course only sublink 0 matches. - // If the links are unganged and both connected, the BKDG settings are for both coherent. - PciAddress = CapabilitySet; - PciAddress.Address.Register = Entry->HtTokenEntry.Address.Address.Register + - ((Link > 3) ? (((UINT32)Link - 4) * 4) : ((UINT32)Link * 4)); - PciAddress.Address.Function = Entry->HtTokenEntry.Address.Address.Function; - LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader); - RegisterData = RegisterData & (~(Entry->HtTokenEntry.Mask)); - RegisterData = RegisterData | Entry->HtTokenEntry.Data; - LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader); - } - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Core Counts Performance PCI Register Entry. - * - * @TableEntryTypeMethod{::CoreCountsPciRegister}. - * - * Check the performance profile. - * Check the actual core count to the range pair given, and apply if matched. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForCoreCountsPerformanceEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - UINTN ActualCoreCount; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); - - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue)) { - ActualCoreCount = GetActiveCoresInCurrentModule (StdHeader); - // Check if the actual core count is in either range. - if (IsEitherCountInRange (ActualCoreCount, ActualCoreCount, Entry->CoreCountEntry.CoreCounts.CoreRanges)) { - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->CoreCountEntry.PciEntry; - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Processor Counts PCI Register Entry. - * - * @TableEntryTypeMethod{::ProcCountsPciRegister}. - * - * Check the performance profile. - * Check the actual processor count (not node count!) to the range pair given, and apply if matched. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForProcessorCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - UINTN ProcessorCount; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); - - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue)) { - ProcessorCount = GetNumberOfProcessors (StdHeader); - // Check if the actual processor count is in either range. - if (IsEitherCountInRange (ProcessorCount, ProcessorCount, Entry->ProcCountEntry.ProcessorCounts.ProcessorCountRanges)) { - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->ProcCountEntry.PciEntry; - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Compute Unit Counts PCI Register Entry. - * - * @TableEntryTypeMethod{::CompUnitCountsPciRegister}. - * - * Check the entry's performance profile features and the compute unit count - * to the platform's and do the PCI register entry if they match. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForComputeUnitCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - UINTN ComputeUnitCount; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT (((Entry->CompUnitCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); - - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->CompUnitCountEntry.TypeFeats.PerformanceProfileValue)) { - ComputeUnitCount = GetNumberOfCompUnitsInCurrentModule (StdHeader); - // Check if the actual compute unit count is in either range. - if (IsEitherCountInRange (ComputeUnitCount, ComputeUnitCount, Entry->CompUnitCountEntry.ComputeUnitCounts.ComputeUnitRanges)) { - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->CompUnitCountEntry.PciEntry; - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Compute Unit Counts MSR Register Entry. - * - * @TableEntryTypeMethod{::CompUnitCountsMsr}. - * - * Check the entry's compute unit count to the platform's and do the - * MSR entry if they match. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetMsrForComputeUnitCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN ComputeUnitCount; - TABLE_ENTRY_DATA MsrEntry; - - ComputeUnitCount = GetNumberOfCompUnitsInCurrentModule (StdHeader); - // Check if the actual compute unit count is in either range. - if (IsEitherCountInRange (ComputeUnitCount, ComputeUnitCount, Entry->CompUnitCountMsrEntry.ComputeUnitCounts.ComputeUnitRanges)) { - LibAmdMemFill (&MsrEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - MsrEntry.MsrEntry = Entry->CompUnitCountMsrEntry.MsrEntry; - SetRegisterForMsrEntry (&MsrEntry, PlatformConfig, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the Processor Token Counts PCI Register Entry. - * - * @TableEntryTypeMethod{::TokenPciRegister}. - * - * The table criteria then translate as: - * - 2 Socket, half populated == Degree 1 - * - 4 Socket, half populated == Degree 2 - * - 2 Socket, fully populated == Degree 3 - * - 4 Socket, fully populated == Degree > 3. (4 or 5 if 3P, 6 if 4P) - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForTokenPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PERFORMANCE_PROFILE_FEATS PlatformProfile; - UINTN SystemDegree; - UINT32 ProcessorPackageType; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT ((Entry->TokenPciEntry.PackageType.PackageTypeValue & ~(PACKAGE_TYPE_ALL)) == 0); - ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); - - ProcessorPackageType = LibAmdGetPackageType (StdHeader); - if (DoesEntryTypeSpecificInfoMatch (ProcessorPackageType, Entry->TokenPciEntry.PackageType.PackageTypeValue)) { - GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); - if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue)) { - SystemDegree = GetSystemDegree (StdHeader); - // Check if the system degree is in the range. - if (IsEitherCountInRange (SystemDegree, SystemDegree, Entry->TokenPciEntry.ConnectivityCount.ConnectivityCountRanges)) { - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->TokenPciEntry.PciEntry; - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the HT Link Feature PCI Register Entry. - * - * @TableEntryTypeMethod{::HtFeatPciRegister}. - * - * Set a single field (that is, the register field is not in HT Host capability or a - * set of per link registers) in PCI config, based on HT link features and package type. - * This code is used for two cases: single link processors and multilink processors. - * For single link cases, the link will be tested for a match to the HT Features for the link. - * For multilink processors, the entry will match if @b any link is found which matches. - * For example, a setting can be applied based on coherent HT3 by matching coherent AND HT3. - * - * Make the core's PCI address. Check the package type (currently more important to the single link case), - * and if matching, iterate through all links checking for an HT feature match until found or exhausted. - * If a match was found, pass the PCI entry data to the implementer for writing for the current core. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtFeaturePciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PCI_ADDR CapabilitySet; - HT_HOST_FEATS HtHostFeats; - UINT32 ProcessorPackageType; - BOOLEAN IsMatch; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT ((Entry->HtFeatPciEntry.PciEntry.Mask != 0) && - ((Entry->HtFeatPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0)); - - HtHostFeats.HtHostValue = 0; - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->HtFeatPciEntry.PciEntry; - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - ASSERT ((Entry->HtFeatPciEntry.PackageType.PackageTypeValue & ~(PACKAGE_TYPE_ALL)) == 0); - - ProcessorPackageType = LibAmdGetPackageType (StdHeader); - if (DoesEntryTypeSpecificInfoMatch (ProcessorPackageType, Entry->HtFeatPciEntry.PackageType.PackageTypeValue)) { - IsMatch = FALSE; - while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { - if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtFeatPciEntry.LinkFeats.HtHostValue)) { - IsMatch = TRUE; - break; - } - } - if (IsMatch) { - // Do the PCI register update. - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the HT Link PCI Register Entry. - * - * @TableEntryTypeMethod{::HtLinkPciRegister}. - * - * Make the current core's PCI address with the function and register for the entry. - * Registers are processed for match per link, assuming sequential PCI address per link. - * Read - Modify - Write each matching link's PCI register, clearing masked bits, and setting the data bits. - * - * @param[in] Entry The PCI register entry to perform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegisterForHtLinkPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Link; - UINT32 MySocket; - UINT32 MyModule; - AGESA_STATUS IgnoredStatus; - UINT32 Ignored; - CPU_LOGICAL_ID CpuFamilyRevision; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PCI_ADDR CapabilitySet; - HT_HOST_FEATS HtHostFeats; - TABLE_ENTRY_DATA PciEntry; - - // Errors: Possible values in unused entry space, extra type features, value range checks. - // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. - ASSERT ((Entry->HtLinkPciEntry.PciEntry.Mask != 0) && - ((Entry->HtLinkPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0)); - - HtHostFeats.HtHostValue = 0; - LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); - PciEntry.PciEntry = Entry->HtLinkPciEntry.PciEntry; - IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); - GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - Link = 0; - while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { - if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtLinkPciEntry.LinkFeats.HtHostValue)) { - // Do the update to the link's non-Host PCI register, based on the entry address. - PciEntry.PciEntry.Address = Entry->HtLinkPciEntry.PciEntry.Address; - PciEntry.PciEntry.Address.Address.Register = PciEntry.PciEntry.Address.Address.Register + ((UINT32)Link * 4); - SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * Returns the platform features list of the currently running processor core. - * - * @param[out] Features The Features supported by this platform - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Header for library and services - * - */ -VOID -GetPlatformFeatures ( - OUT PLATFORM_FEATS *Features, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - UINT32 CapabilityReg; - UINT32 Link; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - UINT32 CoreCount; - - // Start with none. - Features->PlatformValue = 0; - - switch (PlatformConfig->PlatformProfile.PlatformControlFlowMode) { - case Nfcm: - Features->PlatformFeatures.PlatformNfcm = 1; - break; - case UmaDr: - Features->PlatformFeatures.PlatformUma = 1; - break; - case UmaIfcm: - Features->PlatformFeatures.PlatformUmaIfcm = 1; - break; - case Ifcm: - Features->PlatformFeatures.PlatformIfcm = 1; - break; - case Iommu: - Features->PlatformFeatures.PlatformIommu = 1; - break; - default: - ASSERT (FALSE); - } - // Check - Single Link? - // This is based on the implemented links on the package regardless of their - // connection status. All processors must match the BSP, so we only check it and - // not the current node. We don't care exactly how many links there are, as soon - // as we find more than one we are done. - Link = 0; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, FUNC_0, 0); - // Until either all capabilities are done or until the desired link is found, - // keep looking for HT Host Capabilities. - while (Link < 2) { - LibAmdPciFindNextCap (&PciAddress, StdHeader); - if (PciAddress.AddressValue != ILLEGAL_SBDFO) { - LibAmdPciRead (AccessWidth32, PciAddress, &CapabilityReg, StdHeader); - if ((CapabilityReg & 0xE00000FF) == 0x20000008) { - Link++; - } - // A capability other than an HT capability, keep looking. - } else { - // end of capabilities - break; - } - } - if (Link < 2) { - Features->PlatformFeatures.PlatformSingleLink = 1; - } else { - Features->PlatformFeatures.PlatformMultiLink = 1; - } - - // Set the legacy core count bits. - GetActiveCoresInCurrentSocket (&CoreCount, StdHeader); - switch (CoreCount) { - case 1: - Features->PlatformFeatures.PlatformSingleCore = 1; - break; - case 2: - Features->PlatformFeatures.PlatformDualCore = 1; - break; - default: - Features->PlatformFeatures.PlatformMultiCore = 1; - } - - // - // Get some specific platform type info, VC...etc. - // - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL); - FamilySpecificServices->GetPlatformTypeSpecificInfo (FamilySpecificServices, Features, StdHeader); - -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Checks if a register table entry applies to the executing core. - * - * This function uses a combination of logical ID and platform features to - * determine whether or not a register table entry applies to the executing core. - * - * @param[in] CoreCpuRevision The current core's logical ID - * @param[in] EntryCpuRevision The entry's desired logical IDs - * @param[in] PlatformFeatures The platform features - * @param[in] EntryFeatures The entry's desired platform features - * - * @retval TRUE This entry should be applied - * @retval FALSE This entry does not apply - * - */ -BOOLEAN -STATIC -DoesEntryMatchPlatform ( - IN CPU_LOGICAL_ID CoreCpuRevision, - IN CPU_LOGICAL_ID EntryCpuRevision, - IN PLATFORM_FEATS PlatformFeatures, - IN PLATFORM_FEATS EntryFeatures - ) -{ - BOOLEAN Result; - - Result = FALSE; - - if (((CoreCpuRevision.Family & EntryCpuRevision.Family) != 0) && - ((CoreCpuRevision.Revision & EntryCpuRevision.Revision) != 0)) { - if (EntryFeatures.PlatformFeatures.AndPlatformFeats == 0) { - // Match if ANY entry feats match a platform feat (an OR test) - if ((EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue) != 0) { - Result = TRUE; - } - } else { - // Match if ALL entry feats match a platform feat (an AND test) - if ((EntryFeatures.PlatformValue & ~(AMD_PF_AND)) == - (EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue)) { - Result = TRUE; - } - } - } - - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Checks register table entry type specific criteria to the platform. - * - * Entry Data Type implementer methods can use this generically to check their own - * specific criteria. The method collects the actual platform characteristics and - * provides them along with the table entry's criteria to this service. - * - * There are a couple considerations for any implementer method using this service. - * The criteria value has to be representable as a UINT32. The MSB, Bit 31, has to - * be used as a AND test request if set in the entry. (The platform value should never - * have that bit set.) - * - * @param[in] PlatformTypeSpecificFeatures The platform features - * @param[in] EntryTypeFeatures The entry's desired platform features - * - * @retval TRUE This entry should be applied - * @retval FALSE This entry does not apply - * - */ -BOOLEAN -DoesEntryTypeSpecificInfoMatch ( - IN UINT32 PlatformTypeSpecificFeatures, - IN UINT32 EntryTypeFeatures - ) -{ - BOOLEAN Result; - - Result = FALSE; - - if ((EntryTypeFeatures & BIT31) == 0) { - // Match if ANY entry feats match a platform feat (an OR test) - if ((EntryTypeFeatures & PlatformTypeSpecificFeatures) != 0) { - Result = TRUE; - } - } else { - // Match if ALL entry feats match a platform feat (an AND test) - if ((EntryTypeFeatures & ~(BIT31)) == (EntryTypeFeatures & PlatformTypeSpecificFeatures)) { - Result = TRUE; - } - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determine this core's Selector matches. - * - * @param[in] Selector Is the current core this selector type? - * @param[in] StdHeader Config handle for library and services. - * - * @retval TRUE Yes, it is. - * @retval FALSE No, it is not. - */ -BOOLEAN -STATIC -IsCoreSelector ( - IN TABLE_CORE_SELECTOR Selector, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Result; - AGESA_STATUS CalledStatus; - - Result = TRUE; - ASSERT (Selector < TableCoreSelectorMax); - - if ((Selector == PrimaryCores) && !IsCurrentCorePrimary (StdHeader)) { - Result = FALSE; - } - if ((Selector == CorePairPrimary) && !IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - Result = FALSE; - } - if ((Selector == BscCore) && (!IsBsp (StdHeader, &CalledStatus))) { - Result = FALSE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set the registers for this core based on entries in a list of Register Tables. - * - * Determine the platform features and this core's logical id. Get the specific table - * entry type implementations for the logical model, which may be either generic (the ones - * in this file) or specific. - * - * Scan the tables starting the with ones for all cores and progressively narrowing the selection - * based on this core's role (ex. primary core). For a selected table, check for each entry - * matching the current core and platform, and call the implementer method to perform the - * register set operation if it matches. - * - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegistersFromTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID CpuLogicalId; - PLATFORM_FEATS PlatformFeatures; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - TABLE_ENTRY_FIELDS *Entries; - TABLE_CORE_SELECTOR Selector; - TABLE_ENTRY_TYPE EntryType; - REGISTER_TABLE **TableHandle; - UINTN NumberOfEntries; - UINTN CurrentEntryCount; - TABLE_ENTRY_TYPE_DESCRIPTOR *TypeImplementer; - PF_DO_TABLE_ENTRY DoTableEntry[TableEntryTypeMax]; - - // Did you really mean to increase the size of ALL table entries??!! - // While it is not necessarily a bug to increase the size of table entries: - // - Is this warning a surprise? Please fix it. - // - If expected, is this really a feature which is worth the increase? Then let other entries also use the space. - ASSERT (sizeof (TABLE_ENTRY_DATA) == (MAX_ENTRY_TYPE_ITEMS32 * sizeof (UINT32))); - - PlatformFeatures.PlatformValue = 0; - GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader); - GetPlatformFeatures (&PlatformFeatures, PlatformConfig, StdHeader); - GetCpuServicesFromLogicalId (&CpuLogicalId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - // Build a non-sparse table of implementer methods, so we don't have to keep searching. - // It is a bug to not include a descriptor for a type that is in the table (but the - // descriptor can point to a non-assert stub). - // Also, it is not a bug to have no register table implementations, but it is a bug to have none and call this routine. - for (EntryType = MsrRegister; EntryType < TableEntryTypeMax; EntryType++) { - DoTableEntry[EntryType] = (PF_DO_TABLE_ENTRY)CommonAssert; - } - TypeImplementer = FamilySpecificServices->TableEntryTypeDescriptors; - ASSERT (TypeImplementer != NULL); - while (TypeImplementer->EntryType < TableEntryTypeMax) { - DoTableEntry[TypeImplementer->EntryType] = TypeImplementer->DoTableEntry; - TypeImplementer++; - } - - for (Selector = AllCores; Selector < TableCoreSelectorMax; Selector++) { - if (IsCoreSelector (Selector, StdHeader)) { - // If the current core is the selected type of core, work the table list for tables for that type of core. - TableHandle = NULL; - Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader); - while (Entries != NULL) { - for (CurrentEntryCount = 0; CurrentEntryCount < NumberOfEntries; CurrentEntryCount++, Entries++) { - if (DoesEntryMatchPlatform (CpuLogicalId, Entries->CpuRevision, PlatformFeatures, Entries->Features)) { - // The entry matches this config, Do It! - // Find the implementer for this entry type and pass the entry data to it. - ASSERT (Entries->EntryType < TableEntryTypeMax); - DoTableEntry[Entries->EntryType] (&Entries->Entry, PlatformConfig, StdHeader); - } - } - Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader); - } - } else { - // Once a selector does not match the current core, quit looking. - break; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set the registers for this core based on entries in a list of Register Tables. - * - * This function acts as a wrapper for calling the SetRegistersFromTables - * routine at AmdInitEarly. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetRegistersFromTablesAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_TESTPOINT (TpProcCpuProcessRegisterTables, StdHeader); - SetRegistersFromTables (&EarlyParams->PlatformConfig, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h deleted file mode 100644 index 16c3baa67b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h +++ /dev/null @@ -1,1296 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Register Table Related Functions - * - * Contains code to initialize the CPU MSRs and PCI registers with BKDG recommended values - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 59564 $ @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_TABLE_H_ -#define _CPU_TABLE_H_ - -#define MAX_ENTRY_TYPE_ITEMS32 6 // The maximum number of initializer items for UINT32 entry data types. - -/** - * @page regtableimpl Register Table Implementation Guide - * - * This register table implementation is modular and extensible, so that support code as - * well as table data can be family specific or built out if not needed, and new types - * of table entries can be added with low overhead. Because many aspects are now generic, - * there can be common implementations for CPU revision and platform feature matching and for - * finding and iterating tables. - * - * @par Adding a new table entry type. - * - * To add a new table entry type follow these steps. - *
    - *
  • Add a member to the enum TABLE_ENTRY_TYPE which is a descriptive name of the entry's purpose - * or distinct characteristics. - * - *
  • Create an entry data struct with the customized data needed. For example, custom register designations, - * data and mask sizes, or feature comparisons. Name your struct by adding "_" and upper-casing the enum name - * and adding "_TYPE_ENTRY_DATA" at the end. - * - *
  • Add the entry data type as a member of the TABLE_ENTRY_DATA union. Be aware of the size of your - * entry data struct; all table entries in all tables will share any size increase you introduce! - * - *
  • If your data entry contains any member types except for UINT32, you can't use the generic first union member - * for the initializers that make up the actual tables (it's just UINT32's). The generic MSR entry is - * an example. Follow the steps below: - * - *
      - *
    • Make a union which has your entry data type as the first member. Use TABLE_ENTRY_DATA as the - * second member. Name this with your register followed by "_DATA_INITIALIZER". - * - *
    • Make a copy of TABLE_ENTRY_FIELDS, and rename it your register "_TYPE_ENTRY_INITIALIZER". Rename - * the TABLE_ENTRY_DATA member of that struct to have the type you created in the previous step. - * This type can be used to declare an array of entries and make a register table in some family specific - * file. - *
    - * - *
  • Add the descriptor that will link table entries of your data type to an implementation for it. - *
      - *
    • Find the options file which instantiates the CPU_SPECIFIC_SERVICES for each logical model that will - * support the new entry type. - * - *
    • From there find the instantiation of its TABLE_ENTRY_TYPE_DESCRIPTOR. Add a descriptor to the - * to the list for your new type. Provide the name of a function which will implement the - * entry data. The function name should reflect that it implements the action for the entry type. - * The function must be an instance of F_DO_TABLE_ENTRY. - *
    - * - *
  • Implement the function for your entry type data. (If parts of it are family specific add methods to - * CPU_SPECIFIC_SERVICES for that and implement them for each family or model required.) @n - * The definition of the function must conform to F_DO_TABLE_ENTRY. - * In the function preamble, include a cross reference to the entry enum: - * @code - * * - * * @TableEntryTypeMethod{::MyRegister} - * * - * @endcode - * - *
- * - * @par Adding a new Register Table - * - * To add a new register table for a logical CPU model follow the steps below. - * - *
    - *
  • Find the options file which instantiates the CPU_SPECIFIC_SERVICES for the logical model that - * should include the table. - * - *
  • From there find the instantiation of its REGISTER_TABLE list. Add the name of the new register table. - *
- * - */ - -/*------------------------------------------------------------------------------------------*/ -/* - * Define the supported table entries. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * These are the available types of table entries. - * - * Each type corresponds to: - * - a semantics for the type specific data, for example semantics for a Register value, - * Data value, and Mask value. - * - optionally, including a method for type specific matching criteria - * - a method for writing the desired update to the hardware. - * - * All types share in common a method to match CPU Family and Model and a method to match - * platform feature set. - * - */ -typedef enum { - MsrRegister, ///< Processor MSR registers. - PciRegister, ///< Processor Config Space registers. - FamSpecificWorkaround, ///< Processor Family Specific Workarounds which are @b not practical using the other types. - HtPhyRegister, ///< Processor HT Phy registers. - HtPhyRangeRegister, ///< Processor HT Phy range of contiguous registers (ex. 40h:48h). - DeemphasisRegister, ///< Processor Deemphasis register (HT Phy special case). - HtPhyFreqRegister, ///< Processor Frequency dependent HT Phy settings. - ProfileFixup, ///< Processor Performance Profile fixups to PCI Config Registers. - HtHostPciRegister, ///< Processor Ht Host capability registers (PCI Config). - HtHostPerfPciRegister, ///< Processor Ht Host capability registers which depend on performance features. - HtTokenPciRegister, ///< Processor Ht Link Token count registers. - CoreCountsPciRegister, ///< Processor PCI Config Registers which depend on core counts. - ProcCountsPciRegister, ///< Processor PCI Config Registers which depend on processor counts. - CompUnitCountsPciRegister, ///< Processor PCI Config Registers which depend on compute unit counts. - TokenPciRegister, ///< Processor northbridge Token Count register which may be dependent on connectivity. - HtFeatPciRegister, ///< Processor HT Link feature dependant PCI Config Registers. - HtPhyProfileRegister, ///< Processor HT Phy registers which depend on performance features. - HtLinkPciRegister, ///< Processor HT Link registers (one per link) not part of HT Host capability. - CompUnitCountsMsr, ///< Processor MSRs which depend on compute unit counts. - TableEntryTypeMax ///< Not a valid entry type, use for limit checking. -} TABLE_ENTRY_TYPE; - -/*------------------------------------------------------------------------------------------*/ -/* - * Useful types and defines: Selectors, Platform Features, and type specific features. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * Select tables for the current core. - * - * This allows more efficient register table processing, by allowing cores to skip - * redundantly setting PCI registers, for example. This feature is not intended to - * be relied on for function: it is valid to have a single register table with all settings - * processed by every core; it's just slower. - * - */ -typedef enum { - AllCores, ///< Select only tables which apply to all cores. - CorePairPrimary, ///< Select tables which apply to the primary core of a compute unit (SharedC, SharedNc). - PrimaryCores, ///< Select tables which apply to primary cores. - BscCore, ///< Select tables which apply to the boot core. - TableCoreSelectorMax ///< Not a valid selector, use for limit checking. -} TABLE_CORE_SELECTOR; - -// Initializer bit pattern values for platform features. -// Keep in synch with the PLATFORM_FEATURES struct! - -// The 5 control flow modes. -#define AMD_PF_NFCM BIT0 -#define AMD_PF_UMA BIT1 // UMA_DR -#define AMD_PF_UMA_IFCM BIT2 -#define AMD_PF_IFCM BIT3 -#define AMD_PF_IOMMU BIT4 -// Degree of HT connectivity possible. -#define AMD_PF_SINGLE_LINK BIT5 -#define AMD_PF_MULTI_LINK BIT6 -// For some legacy MSRs, define a couple core count bits. Do not continue adding -// core counts to the platform feats, if you need more than this design a table entry type. -// Here, provide exactly 1, exactly 2, or anything else. -#define AMD_PF_SINGLE_CORE BIT7 -#define AMD_PF_DUAL_CORE BIT8 -#define AMD_PF_MULTI_CORE BIT9 - -// Not a platform type, but treat all others as AND -#define AMD_PF_AND BIT31 - -#define AMD_PF_ALL (AMD_PF_NFCM | \ - AMD_PF_UMA | \ - AMD_PF_UMA_IFCM | \ - AMD_PF_IFCM | \ - AMD_PF_IOMMU | \ - AMD_PF_SINGLE_LINK | \ - AMD_PF_MULTI_LINK | \ - AMD_PF_SINGLE_CORE | \ - AMD_PF_DUAL_CORE | \ - AMD_PF_MULTI_CORE) -// Do not include AMD_PF_AND in AMD_PF_ALL ! - -/** - * The current platform features. - * - * Keep this in sync with defines above that are used in the initializers! - * - * The comments with the bit number are useful for the computing the reserved member size, but - * do not write code that assumes you know what bit number one of these members is. - * - * These platform features are standard for all logical families and models. - */ -typedef struct { - UINT32 PlatformNfcm:1; ///< BIT_0 Normal Flow Control Mode. - UINT32 PlatformUma:1; ///< BIT_1 UMA (Display Refresh) Flow Control. - UINT32 PlatformUmaIfcm:1; ///< BIT_2 UMA using Isochronous Flow Control. - UINT32 PlatformIfcm:1; ///< BIT_3 Isochronous Flow Control Mode (not UMA). - UINT32 PlatformIommu:1; ///< BIT_4 IOMMU (a special case Isochronous mode). - UINT32 PlatformSingleLink:1; ///< BIT_5 The processor is in a package which implements only a single HT Link. - UINT32 PlatformMultiLink:1; ///< BIT_6 The processor is in a package which implements more than one HT Link. - UINT32 PlatformSingleCore:1; ///< BIT_7 Single Core processor, for legacy entries. - UINT32 PlatformDualCore:1; ///< BIT_8 Dual Core processor, for legacy entries. - UINT32 PlatformMultiCore:1; ///< BIT_9 More than dual Core processor, for legacy entries. - UINT32 :(30 - 9); ///< The possibilities are (not quite) endless. - UINT32 AndPlatformFeats:1; ///< BIT_31 -} PLATFORM_FEATURES; - -/** - * Platform Features - */ -typedef union { - UINT32 PlatformValue; ///< Describe Platform Features in UINT32. - ///< This one goes first, because then initializers use it automatically for the union. - PLATFORM_FEATURES PlatformFeatures; ///< Describe Platform Features in structure -} PLATFORM_FEATS; - -// Sublink Types are defined so they can match each attribute against either -// sublink zero or one. The table entry must contain the correct matching -// values based on the register. This is available in the BKDG, for each register -// which sublink it controls. If the register is independent of sublink, OR values -// together or use HT_LINKTYPE_ALL to match if either sublink matches (ex. E0 - E5). -// Sublink 0 types, bits 0 thru 14 -#define HTPHY_LINKTYPE_SL0_HT3 BIT0 -#define HTPHY_LINKTYPE_SL0_HT1 BIT1 -#define HTPHY_LINKTYPE_SL0_COHERENT BIT2 -#define HTPHY_LINKTYPE_SL0_NONCOHERENT BIT3 -#define HTPHY_LINKTYPE_SL0_LINK0 BIT4 -#define HTPHY_LINKTYPE_SL0_LINK1 BIT5 -#define HTPHY_LINKTYPE_SL0_LINK2 BIT6 -#define HTPHY_LINKTYPE_SL0_LINK3 BIT7 -#define HTPHY_LINKTYPE_SL0_INTERNAL BIT8 -#define HTPHY_LINKTYPE_SL0_EXTERNAL BIT9 -#define HTPHY_LINKTYPE_SL0_AND BIT15 - -// SubLink 1 types, bits 16 thru 30 -#define HTPHY_LINKTYPE_SL1_HT3 BIT16 -#define HTPHY_LINKTYPE_SL1_HT1 BIT17 -#define HTPHY_LINKTYPE_SL1_COHERENT BIT18 -#define HTPHY_LINKTYPE_SL1_NONCOHERENT BIT19 -#define HTPHY_LINKTYPE_SL1_LINK4 BIT20 -#define HTPHY_LINKTYPE_SL1_LINK5 BIT21 -#define HTPHY_LINKTYPE_SL1_LINK6 BIT22 -#define HTPHY_LINKTYPE_SL1_LINK7 BIT23 -#define HTPHY_LINKTYPE_SL1_INTERNAL BIT24 -#define HTPHY_LINKTYPE_SL1_EXTERNAL BIT25 -#define HTPHY_LINKTYPE_SL1_AND BIT31 - -#define HTPHY_LINKTYPE_SL0_ALL (HTPHY_LINKTYPE_SL0_HT3 | \ - HTPHY_LINKTYPE_SL0_HT1 | \ - HTPHY_LINKTYPE_SL0_COHERENT | \ - HTPHY_LINKTYPE_SL0_NONCOHERENT | \ - HTPHY_LINKTYPE_SL0_LINK0 | \ - HTPHY_LINKTYPE_SL0_LINK1 | \ - HTPHY_LINKTYPE_SL0_LINK2 | \ - HTPHY_LINKTYPE_SL0_LINK3 | \ - HTPHY_LINKTYPE_SL0_INTERNAL | \ - HTPHY_LINKTYPE_SL0_EXTERNAL) -#define HTPHY_LINKTYPE_SL1_ALL (HTPHY_LINKTYPE_SL1_HT3 | \ - HTPHY_LINKTYPE_SL1_HT1 | \ - HTPHY_LINKTYPE_SL1_COHERENT | \ - HTPHY_LINKTYPE_SL1_NONCOHERENT | \ - HTPHY_LINKTYPE_SL1_LINK4 | \ - HTPHY_LINKTYPE_SL1_LINK5 | \ - HTPHY_LINKTYPE_SL1_LINK6 | \ - HTPHY_LINKTYPE_SL1_LINK7 | \ - HTPHY_LINKTYPE_SL1_INTERNAL | \ - HTPHY_LINKTYPE_SL1_EXTERNAL) -#define HTPHY_LINKTYPE_ALL (HTPHY_LINKTYPE_SL0_ALL | HTPHY_LINKTYPE_SL1_ALL) - -#define HTPHY_REGISTER_MAX 0x0000FFFFul -/** - * HT PHY Link Features - */ -typedef struct { - UINT32 HtPhySL0Ht3:1; ///< Ht Phy Sub-link 0 Ht3 - UINT32 HtPhySL0Ht1:1; ///< Ht Phy Sub-link 0 Ht1 - UINT32 HtPhySL0Coh:1; ///< Ht Phy Sub-link 0 Coherent - UINT32 HtPhySL0NonCoh:1; ///< Ht Phy Sub-link 0 NonCoherent - UINT32 HtPhySL0Link0:1; ///< Ht Phy Sub-link 0 specifically for node link 0. - UINT32 HtPhySL0Link1:1; ///< Ht Phy Sub-link 0 specifically for node link 1. - UINT32 HtPhySL0Link2:1; ///< Ht Phy Sub-link 0 specifically for node link 2. - UINT32 HtPhySL0Link3:1; ///< Ht Phy Sub-link 0 specifically for node link 3. - UINT32 HtPhySL0Internal:1; ///< Ht Phy Sub-link 0 is internal link. Intended for IDS support. - UINT32 HtPhySL0External:1; ///< Ht Phy Sub-link 0 is external link. Intended for IDS support. - UINT32 :(14 - 9); ///< Ht Phy Sub-link 0 Pad - UINT32 HtPhySL0And:1; ///< Ht Phy feature match should match all selected features, for sub-link 0. - UINT32 HtPhySL1Ht3:1; ///< Ht Phy Sub-link 1 Ht3 - UINT32 HtPhySL1Ht1:1; ///< Ht Phy Sub-link 1 Ht1 - UINT32 HtPhySL1Coh:1; ///< Ht Phy Sub-link 1 Coherent - UINT32 HtPhySL1NonCoh:1; ///< Ht Phy Sub-link 1 NonCoherent - UINT32 HtPhySL1Link4:1; ///< Ht Phy Sub-link 1 specifically for node link 4. - UINT32 HtPhySL1Link5:1; ///< Ht Phy Sub-link 1 specifically for node link 5. - UINT32 HtPhySL1Link6:1; ///< Ht Phy Sub-link 1 specifically for node link 6. - UINT32 HtPhySL1Link7:1; ///< Ht Phy Sub-link 1 specifically for node link 7. - UINT32 HtPhySL1Internal:1; ///< Ht Phy Sub-link 1 is internal link. Intended for IDS support. - UINT32 HtPhySL1External:1; ///< Ht Phy Sub-link 1 is external link. Intended for IDS support. - UINT32 :(30 - 25); ///< Ht Phy Sub-link 1 Pad - UINT32 HtPhySL1And:1; ///< Ht Phy feature match should match all selected features, for sub-link 1. -} HT_PHY_LINK_FEATURES; - -/** - * Ht Phy Link Features - */ -typedef union { - UINT32 HtPhyLinkValue; ///< Describe HY Phy Features in UINT32. - ///< This one goes first, because then initializers use it automatically for the union. - HT_PHY_LINK_FEATURES HtPhyLinkFeatures; ///< Describe HT Phy Features in structure. -} HT_PHY_LINK_FEATS; - -// DB Level for initializing Deemphasis -// This must be in sync with DEEMPHASIS_FEATURES and PLATFORM_DEEMPHASIS_LEVEL (agesa.h) -#define DEEMPHASIS_LEVEL_NONE BIT0 -#define DEEMPHASIS_LEVEL__3 BIT1 -#define DEEMPHASIS_LEVEL__6 BIT2 -#define DEEMPHASIS_LEVEL__8 BIT3 -#define DEEMPHASIS_LEVEL__11 BIT4 -#define DEEMPHASIS_LEVEL__11_8 BIT5 -#define DCV_LEVEL_NONE BIT16 -#define DCV_LEVEL__2 BIT17 -#define DCV_LEVEL__3 BIT18 -#define DCV_LEVEL__5 BIT19 -#define DCV_LEVEL__6 BIT20 -#define DCV_LEVEL__7 BIT21 -#define DCV_LEVEL__8 BIT22 -#define DCV_LEVEL__9 BIT23 -#define DCV_LEVEL__11 BIT24 -// Note that an "AND" feature doesn't make any sense, levels are mutually exclusive. - -// An error check value. -#define DEEMPHASIS_LEVELS_ALL (DEEMPHASIS_LEVEL_NONE | \ - DEEMPHASIS_LEVEL__3 | \ - DEEMPHASIS_LEVEL__6 | \ - DEEMPHASIS_LEVEL__8 | \ - DEEMPHASIS_LEVEL__11 | \ - DEEMPHASIS_LEVEL__11_8) - -#define DCV_LEVELS_ALL (DCV_LEVEL_NONE | \ - DCV_LEVEL__2 | \ - DCV_LEVEL__3 | \ - DCV_LEVEL__5 | \ - DCV_LEVEL__6 | \ - DCV_LEVEL__7 | \ - DCV_LEVEL__8 | \ - DCV_LEVEL__9 | \ - DCV_LEVEL__11) - -#define VALID_DEEMPHASIS_LEVELS (DEEMPHASIS_LEVELS_ALL | DCV_LEVELS_ALL) - -/** - * Deemphasis Ht Phy Link Deemphasis. - * - * This must be in sync with defines above and ::PLATFORM_DEEMPHASIS_LEVEL (agesa.h) - */ -typedef struct { - UINT32 DeemphasisLevelNone:1; ///< The deemphasis level None. - UINT32 DeemphasisLevelMinus3:1; ///< The deemphasis level minus 3 db. - UINT32 DeemphasisLevelMinus6:1; ///< The deemphasis level minus 6 db. - UINT32 DeemphasisLevelMinus8:1; ///< The deemphasis level minus 8 db. - UINT32 DeemphasisLevelMinus11:1; ///< The deemphasis level minus 11 db. - UINT32 DeemphasisLevelMinus11w8:1; ///< The deemphasis level minus 11 db, minus 8 precursor. - UINT32 :(15 - 5); ///< reserved. - UINT32 DcvLevelNone:1; ///< The level for DCV None. - UINT32 DcvLevelMinus2:1; ///< The level for DCV minus 2 db. - UINT32 DcvLevelMinus3:1; ///< The level for DCV minus 3 db. - UINT32 DcvLevelMinus5:1; ///< The level for DCV minus 5 db. - UINT32 DcvLevelMinus6:1; ///< The level for DCV minus 6 db. - UINT32 DcvLevelMinus7:1; ///< The level for DCV minus 7 db. - UINT32 DcvLevelMinus8:1; ///< The level for DCV minus 8 db. - UINT32 DcvLevelMinus9:1; ///< The level for DCV minus 9 db. - UINT32 DcvLevelMinus11:1; ///< The level for DCV minus 11 db. - UINT32 :(15 - 8); ///< reserved. -} DEEMPHASIS_FEATURES; - -/** - * Deemphasis Ht Phy Link Features. - */ -typedef union { - UINT32 DeemphasisValues; ///< Initialize HT Deemphasis in UINT32. - DEEMPHASIS_FEATURES DeemphasisLevels; ///< HT Deemphasis levels. -} DEEMPHASIS_FEATS; - -// Initializer bit patterns for PERFORMANCE_PROFILE_FEATS. -#define PERFORMANCE_REFRESH_REQUEST_32B BIT0 -#define PERFORMANCE_PROBEFILTER BIT1 -#define PERFORMANCE_L3_CACHE BIT2 -#define PERFORMANCE_NO_L3_CACHE BIT3 -#define PERFORMANCE_MCT_ISOC_VARIABLE BIT4 -#define PERFORMANCE_IS_WARM_RESET BIT5 -#define PERFORMANCE_VRM_HIGH_SPEED_ENABLE BIT6 -#define PERFORMANCE_NB_PSTATES_ENABLE BIT7 -#define PERFORMANCE_AND BIT31 - -#define PERFORMANCE_PROFILE_ALL (PERFORMANCE_REFRESH_REQUEST_32B | \ - PERFORMANCE_PROBEFILTER | \ - PERFORMANCE_L3_CACHE | \ - PERFORMANCE_NO_L3_CACHE | \ - PERFORMANCE_MCT_ISOC_VARIABLE | \ - PERFORMANCE_IS_WARM_RESET | \ - PERFORMANCE_VRM_HIGH_SPEED_ENABLE | \ - PERFORMANCE_NB_PSTATES_ENABLE) - -/** - * Performance Profile specific Type Features. - * - * Register settings for the different control flow modes can have additional dependencies - */ -typedef struct { - UINT32 RefreshRequest32Byte:1; ///< BIT_0. Display Refresh Requests use 32 bytes (32BE). - UINT32 ProbeFilter:1; ///< BIT_1 Probe Filter will be enabled. - UINT32 L3Cache:1; ///< BIT_2 L3 Cache is present. - UINT32 NoL3Cache:1; ///< BIT_3 L3 Cache is NOT present. - UINT32 MctIsocVariable:1; ///< BIT_4 Mct Isoc Read Priority set to variable. - UINT32 IsWarmReset:1; ///< BIT_5 This boot is on a warm reset, cold reset pass is already completed. - UINT32 VrmHighSpeed:1; ///< BIT_6 Select high speed VRM. - UINT32 NbPstates:1; ///< BIT_7 Northbridge PStates are enabled - UINT32 :(30 - 7); ///< available for future expansion. - UINT32 AndPerformanceFeats:1; ///< BIT_31. AND other selected features. -} PERFORMANCE_PROFILE_FEATURES; - -/** - * Performance Profile features. - */ -typedef union { - UINT32 PerformanceProfileValue; ///< Initializer value. - PERFORMANCE_PROFILE_FEATURES PerformanceProfileFeatures; ///< The performance profile features. -} PERFORMANCE_PROFILE_FEATS; - -/** - * Package Type Features - * - */ -typedef struct { - UINT32 PkgType0:1; ///< Package Type 0 - UINT32 PkgType1:1; ///< Package Type 1 - UINT32 PkgType2:1; ///< Package Type 2 - UINT32 PkgType3:1; ///< Package Type 3 - UINT32 PkgType4:1; ///< Package Type 4 - UINT32 PkgType5:1; ///< Package Type 5 - UINT32 PkgType6:1; ///< Package Type 6 - UINT32 PkgType7:1; ///< Package Type 7 - UINT32 PkgType8:1; ///< Package Type 8 - UINT32 PkgType9:1; ///< Package Type 9 - UINT32 PkgType10:1; ///< Package Type 10 - UINT32 PkgType11:1; ///< Package Type 11 - UINT32 PkgType12:1; ///< Package Type 12 - UINT32 PkgType13:1; ///< Package Type 13 - UINT32 PkgType14:1; ///< Package Type 14 - UINT32 PkgType15:1; ///< Package Type 15 - UINT32 Reserved:15; ///< Package Type Reserved - UINT32 ReservedAndFeats:1; ///< BIT_31. AND other selected features. Always zero here. -} PACKAGE_TYPE_FEATURES; - -// Initializer Values for Package Type -#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages - -// Initializer Values for Ht Host Pci Config Registers -#define HT_HOST_FEAT_COHERENT BIT0 -#define HT_HOST_FEAT_NONCOHERENT BIT1 -#define HT_HOST_FEAT_GANGED BIT2 -#define HT_HOST_FEAT_UNGANGED BIT3 -#define HT_HOST_FEAT_HT3 BIT4 -#define HT_HOST_FEAT_HT1 BIT5 -#define HT_HOST_AND BIT31 - -#define HT_HOST_FEATURES_ALL (HT_HOST_FEAT_COHERENT | \ - HT_HOST_FEAT_NONCOHERENT | \ - HT_HOST_FEAT_GANGED | \ - HT_HOST_FEAT_UNGANGED | \ - HT_HOST_FEAT_HT3 | \ - HT_HOST_FEAT_HT1) - -/** - * HT Host PCI register features. - * - * Links which are not connected do not match any of these features. - */ -typedef struct { - UINT32 Coherent:1; ///< BIT_0 Apply to links with a coherent connection. - UINT32 NonCoherent:1; ///< BIT_1 Apply to links with a non-coherent connection. - UINT32 Ganged:1; ///< BIT_2 Apply to links with a ganged connection. - UINT32 UnGanged:1; ///< BIT_3 Apply to links with a unganged connection. - UINT32 Ht3:1; ///< BIT_4 Apply to links with HT3 frequency (> 1000 MHz) - UINT32 Ht1:1; ///< BIT_5 Apply to links with HT1 frequency (< 1200 MHz) - UINT32 :(30 - 5); ///< Future expansion. - UINT32 AndHtHostFeats:1; ///< BIT_31. AND other selected features. -} HT_HOST_FEATURES; - -/** - * HT Host features for table data. - */ -typedef union { - UINT32 HtHostValue; ///< Initializer value. - HT_HOST_FEATURES HtHostFeatures; ///< The HT Host Features. -} HT_HOST_FEATS; - -// Core Range Initializer values. -#define COUNT_RANGE_LOW 0ul -#define COUNT_RANGE_HIGH 0xFFul - -// A count range matching none is often useful as the second range, matching will then be -// based on the first range. A count range all is provided as a first range for default settings. -#define COUNT_RANGE_NONE ((((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) << 16) -#define COUNT_RANGE_ALL (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_LOW)) -#define IGNORE_FREQ_0 (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) -#define IGNORE_PROCESSOR_0 (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) - -#define CORE_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) -#define CORE_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) -#define PROCESSOR_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) -#define PROCESSOR_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) -#define DEGREE_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) -#define DEGREE_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) -#define FREQ_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) -#define FREQ_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) -#define COMPUTE_UNIT_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) -#define COMPUTE_UNIT_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) - -/** - * Count Range Feature, two count ranges for core counts, processor counts, or node counts. - */ -typedef struct { - UINT32 Range0Min:8; ///< The minimum of the first count range. - UINT32 Range0Max:8; ///< The maximum of the first count range. - UINT32 Range1Min:8; ///< The minimum of the second count range. - UINT32 Range1Max:8; ///< The maximum of the second count range. -} COUNT_RANGE_FEATURE; - -/** - * Core Count Ranges for table data. - * - * Provide a pair of core count ranges. If the actual core count is included in either range (OR), - * the feature should be considered a match. - */ -typedef union { - UINT32 CoreRangeValue; ///< Initializer value. - COUNT_RANGE_FEATURE CoreRanges; ///< The Core Counts. -} CORE_COUNT_RANGES; - -/** - * Processor count ranges for table data. - * - * Provide a pair of processor count ranges. If the actual counts are included in either range (OR), - * the feature should be considered a match. - */ -typedef union { - UINT32 ProcessorCountRangeValue; ///< Initializer value. - COUNT_RANGE_FEATURE ProcessorCountRanges; ///< The Processor and Node Counts. -} PROCESSOR_COUNTS; - -/** - * Compute unit count ranges for table data. - * - * Provide a pair of compute unit count ranges. If the actual counts are included in either ranges (OR), - * the feature should be considered a match. - */ -typedef union { - UINT32 ComputeUnitRangeValue; ///< Initializer value. - COUNT_RANGE_FEATURE ComputeUnitRanges; ///< The Processor and Node Counts. -} COMPUTE_UNIT_COUNTS; - -/** - * Connectivity count ranges for table data. - * - * Provide a processor count range and a system degree range. The degree of a system is - * the maximum degree of any node. The degree of a node is the number of nodes to which - * it is directly connected (not considering width or redundant links). If both the actual - * counts are included in each range (AND), the feature should be considered a match. - */ -typedef union { - UINT32 ConnectivityCountRangeValue; ///< Initializer value. - COUNT_RANGE_FEATURE ConnectivityCountRanges; ///< The Processor and Degree Counts. -} CONNECTIVITY_COUNT; - -/** - * HT Frequency Count Range. - * - * Provide a pair of Frequency count ranges, with the frequency encoded as an HT Frequency value - * (such as would be programmed into the HT Host Link Frequency register). By converting a NB freq, - * the same count can be applied for it. If the actual value is included in either range - */ -typedef union { - UINT32 HtFreqCountRangeValue; ///< Initializer value. - COUNT_RANGE_FEATURE HtFreqCountRanges; ///< The HT Freq counts. -} HT_FREQ_COUNTS; - -/*------------------------------------------------------------------------------------------*/ -/* - * The specific data for each table entry. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * Make an extra type so we can use compilers that don't support designated initializers. - * - * All the entry type unions are no more than 5 UINT32's in size. For entry types which are a struct of UINT32's, - * this type can be used so that initializers can be declared TABLE_ENTRY_FIELDS, instead of a special non-union type. - * A non-union type then has to be cast back to TABLE_ENTRY_FIELDS in order to process the table, and you can't mix - * entry types with non-union initializers in the same table with any other type. - * - * If the entry type contains anything but UINT32's, then it must have a non-union initializer type for creating the - * actual tables. For example, MSR entry has UINT64 and workaround entry has a function pointer. - */ -typedef UINT32 GENERIC_TYPE_ENTRY_INITIALIZER[MAX_ENTRY_TYPE_ITEMS32]; - -/** - * Table Entry Data for MSR Registers. - * - * Apply data to register after mask, for MSRs. - */ -typedef struct { - UINT32 Address; ///< MSR address - UINT64 Data; ///< Data to set in the MSR - UINT64 Mask; ///< Mask to be applied to the MSR. Set every bit of all updated fields. -} MSR_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for PCI Registers. - * - * Apply data to register after mask, for PCI Config registers. - */ -typedef struct { - PCI_ADDR Address; ///< Address should contain Function, Offset only. It will apply to all CPUs - UINT32 Data; ///< Data to be written into PCI device - UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. -} PCI_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for HT Phy Registers. - * - * Apply data to register after mask, for HT Phy registers, repeated for all active links. - */ -typedef struct { - HT_PHY_LINK_FEATS TypeFeats; ///< HT Phy Link Features - UINT32 Address; ///< Address of Ht Phy Register - UINT32 Data; ///< Data to be written into PCI device - UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. -} HT_PHY_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for HT Phy Register Ranges. - * - * Apply data to register after mask, for a range of HT Phy registers, repeated for all active links. - */ -typedef struct { - HT_PHY_LINK_FEATS TypeFeats; ///< HT Phy Link Features - UINT32 LowAddress; ///< Low address of Ht Phy Register range. - UINT32 HighAddress; ///< High address of register range. - UINT32 Data; ///< Data to be written into PCI device. - UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. -} HT_PHY_RANGE_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for HT Phy Deemphasis Registers. - * - * Apply data to register after mask, for HT Phy registers, repeated for all active links. - */ -typedef struct { - DEEMPHASIS_FEATS Levels; ///< The DCV and Deemphasis levels to match - HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy Entry to set the deemphasis values -} DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA; - -/** - * Table Entry Date for HT Phy Frequency Count Register updates. - * - * Compare the NB freq to a range, the HT freq to a range, the link features. - * Apply data to register after mask, if all three matched. - */ -typedef struct { - HT_FREQ_COUNTS HtFreqCounts; ///< Specify the HT Frequency range. - HT_FREQ_COUNTS NbFreqCounts; ///< Specify the NB Frequency range. - HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy register update to perform. -} HT_PHY_FREQ_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for Profile Fixup Registers. - * - * If TypeFeats matches current config, apply data to register after mask for PCI Config registers. - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} PROFILE_FIXUP_TYPE_ENTRY_DATA; - -/** - * A variation of PCI register for the HT Host registers. - * - * A setting to the HT Host buffer counts needs to be made to all the registers for - * all the links. There are also link specific criteria to check. - */ -typedef struct { - HT_HOST_FEATS TypeFeats; ///< Link Features. - PCI_ADDR Address; ///< Address of PCI Register to Fixed Up. - UINT32 Data; ///< Data to be written into PCI device - UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. -} HT_HOST_PCI_TYPE_ENTRY_DATA; - -/** - * A variation of PCI register for the HT Host performance registers. - * - * A setting to the HT Host buffer counts needs to be made to all the registers for - * all the links. There are also link specific criteria to check. - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS PerformanceFeats; ///< Performance Profile features. - HT_HOST_PCI_TYPE_ENTRY_DATA HtHostEntry; ///< Link Features. -} HT_HOST_PERFORMANCE_PCI_TYPE_ENTRY_DATA; - -/** - * A variation of HT Host PCI register for the Link Token registers. - * - * Use Link Features, Performance Fixup features, and processor counts to match entries. - * Link Features are iterated through the connected links. All the matching Link Token count - * registers are updated. - */ -typedef struct { - CONNECTIVITY_COUNT ConnectivityCount; ///< Specify Processor count and Degree count range. - PERFORMANCE_PROFILE_FEATS PerformanceFeats; ///< Performance Profile features. - HT_HOST_FEATS LinkFeats; ///< Link Features. - PCI_ADDR Address; ///< Address of PCI Register to Fixed Up. - UINT32 Data; ///< Data to be written into PCI device - UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. -} HT_TOKEN_PCI_REGISTER; - -/** - * Core Count dependent PCI registers. - * - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - CORE_COUNT_RANGES CoreCounts; ///< Specify up to two core count ranges to match. - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} CORE_COUNTS_PCI_TYPE_ENTRY_DATA; - -/** - * Processor Count dependent PCI registers. - * - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - PROCESSOR_COUNTS ProcessorCounts; ///< Specify a processor count range. - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA; - -/** - * Compute Unit Count dependent PCI registers. - * - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - COMPUTE_UNIT_COUNTS ComputeUnitCounts; ///< Specify a compute unit count range. - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} COMPUTE_UNIT_COUNTS_PCI_TYPE_ENTRY_DATA; - -/** - * Compute Unit Count dependent MSR registers. - * - */ -typedef struct { - COMPUTE_UNIT_COUNTS ComputeUnitCounts; ///< Specify a compute unit count range. - MSR_TYPE_ENTRY_DATA MsrEntry; ///< The MSR Register entry data. -} COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA; - -/** - * Package Type Features - * - * FamilyPackageType are various among CPU families. - * - */ -typedef union { - UINT32 PackageTypeValue; ///< Package Type - PACKAGE_TYPE_FEATURES FamilyPackageType; ///< Package Type of CPU family -} PACKAGE_TYPE_FEATS; - -/** - * System connectivity dependent PCI registers. - * - * The topology specific recommended settings are based on the different connectivity of nodes - * in each configuration: the more connections, the fewer resources each connection gets. - * The connectivity criteria translate as: - * - 2 Socket, half populated == Degree 1 - * - 4 Socket, half populated == Degree 2 - * - 2 Socket, fully populated == Degree 3 - * - 4 Socket, fully populated == Degree > 3. (4 or 5 if 3P, 6 if 4P) - * - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - CONNECTIVITY_COUNT ConnectivityCount; ///< Specify a system degree range. - PACKAGE_TYPE_FEATS PackageType; ///< Package Type - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA; - -/** - * A Family Specific Workaround method. - * - * \@TableTypeFamSpecificInstances. - * - * When called, the entry's CPU Logical ID and Platform Features matched the current config. - * The method must implement any specific criteria checking for the workaround. - * - * See if you can use the other entries or make an entry specifically for the fix. - * After all, the purpose of having a table entry is to @b NOT have code which - * isn't generic feature code, but is family/model specific. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config params for library, services. - */ -typedef VOID F_FAM_SPECIFIC_WORKAROUND ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a method. -typedef F_FAM_SPECIFIC_WORKAROUND *PF_FAM_SPECIFIC_WORKAROUND; - -/** - * Table Entry Data for Family Specific Workarounds. - * - * See if you can use the other entries or make an entry specifically for the fix. - * After all, the purpose of having a table entry is to @b NOT have code which - * isn't generic feature code, but is family/model specific. - * - * Call DoAction passing Data. - */ -typedef struct { - PF_FAM_SPECIFIC_WORKAROUND DoAction; ///< A function implementing the workaround. - UINT32 Data; ///< This data is passed to DoAction(). -} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA; - -/** - * HT Features dependent Global PCI registers. - * - */ -typedef struct { - HT_HOST_FEATS LinkFeats; ///< Link Features. - PACKAGE_TYPE_FEATS PackageType; ///< Package Type - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} HT_FEATURES_PCI_TYPE_ENTRY_DATA; - -/** - * Table Entry Data for HT Phy Registers which depend on performance profile features. - * - * Match performance profile features and link features. - * Apply data to register after mask, for HT Phy registers, repeated for all active links. - */ -typedef struct { - PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. - HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy Entry to set the deemphasis values -} PROFILE_HT_PHY_TYPE_ENTRY_DATA; - -/** - * HT Link PCI registers that are not in the HT Host capability. - * - * Some HT Link registers have an instance per link, but are just sequential. Specify the base register - * in the table register address (link 0 sublink 0). - */ -typedef struct { - HT_HOST_FEATS LinkFeats; ///< Link Features. - PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. -} HT_LINK_PCI_TYPE_ENTRY_DATA; - -/*------------------------------------------------------------------------------------------*/ -/* - * A complete register table and table entries. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * All the available entry data types. - */ -typedef union { - GENERIC_TYPE_ENTRY_INITIALIZER InitialValues; ///< Not a valid entry type; as the first union item, - ///< it can be used with initializers. - MSR_TYPE_ENTRY_DATA MsrEntry; ///< Msr entry. - PCI_TYPE_ENTRY_DATA PciEntry; ///< PCI entry. - FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA FamSpecificEntry; ///< Family Specific Workaround entry. - HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< HT Phy entry. - HT_PHY_RANGE_TYPE_ENTRY_DATA HtPhyRangeEntry; ///< A range of Ht Phy Registers - DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA DeemphasisEntry; ///< A HT Deemphasis level's settings. - HT_PHY_FREQ_TYPE_ENTRY_DATA HtPhyFreqEntry; ///< A frequency dependent Ht Phy Register setting. - PROFILE_FIXUP_TYPE_ENTRY_DATA FixupEntry; ///< Profile Fixup entry. - HT_HOST_PCI_TYPE_ENTRY_DATA HtHostEntry; ///< HT Host PCI entry. - HT_HOST_PERFORMANCE_PCI_TYPE_ENTRY_DATA HtHostPerfEntry; ///< HT Host Performance PCI entry - HT_TOKEN_PCI_REGISTER HtTokenEntry; ///< HT Link Token Count entry. - CORE_COUNTS_PCI_TYPE_ENTRY_DATA CoreCountEntry; ///< Core count dependent settings. - PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA ProcCountEntry; ///< Processor count entry. - COMPUTE_UNIT_COUNTS_PCI_TYPE_ENTRY_DATA CompUnitCountEntry; ///< Compute unit count dependent entry. - CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA TokenPciEntry; ///< System connectivity dependent Token register. - HT_FEATURES_PCI_TYPE_ENTRY_DATA HtFeatPciEntry; ///< HT Features PCI entry. - PROFILE_HT_PHY_TYPE_ENTRY_DATA HtPhyProfileEntry; ///< Performance dependent HT Phy register. - HT_LINK_PCI_TYPE_ENTRY_DATA HtLinkPciEntry; ///< Per Link, non HT Host, PCI registers. - COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA CompUnitCountMsrEntry; ///< Compute unit count dependent MSR entry. -} TABLE_ENTRY_DATA; - -/** - * Register Table Entry common fields. - * - * All the various types of register table entries are subclasses of this object. - */ -typedef struct { - TABLE_ENTRY_TYPE EntryType; ///< The type of table entry this is. - CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. - PLATFORM_FEATS Features; ///< Common Platform Features match criteria. - TABLE_ENTRY_DATA Entry; ///< The type dependent entry data (ex. register, data, mask). -} TABLE_ENTRY_FIELDS; - -/** - * An entire register table. - */ -typedef struct { - TABLE_CORE_SELECTOR Selector; ///< For efficiency, these cores should process this table - UINTN NumberOfEntries; ///< The number of entries in the table. - CONST TABLE_ENTRY_FIELDS *Table; ///< The table entries. -} REGISTER_TABLE; - -/*------------------------------------------------------------------------------------------*/ -/* - * Describe implementers for table entries. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * Implement the semantics of a Table Entry Type. - * - * @TableEntryTypeInstances. - * - * @param[in] CurrentEntry The type specific entry data to be implemented (that is written). - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in] StdHeader Config params for library, services. - */ -typedef VOID F_DO_TABLE_ENTRY ( - IN TABLE_ENTRY_DATA *CurrentEntry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a method -typedef F_DO_TABLE_ENTRY *PF_DO_TABLE_ENTRY; - -/** - * Describe the attributes of a Table Entry Type. - */ -typedef struct { - TABLE_ENTRY_TYPE EntryType; ///< The type of table entry this describes. - PF_DO_TABLE_ENTRY DoTableEntry; ///< Provide all semantics associated with TABLE_ENTRY_DATA -} TABLE_ENTRY_TYPE_DESCRIPTOR; - -/*------------------------------------------------------------------------------------------*/ -/* - * Non-union initializers for entry data which is not just UINT32. - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * A union of data types, that can be initialized with MSR data. - * - * This ensures the entry data is the same size as TABLE_ENTRY_DATA. - */ -typedef union { - MSR_TYPE_ENTRY_DATA MsrInitializer; ///< The data in the table initializer is assigned to this member. - TABLE_ENTRY_DATA Reserved; ///< Make sure the size is the same as the real union. -} MSR_DATA_INITIALIZER; - -/** - * A type suitable for an initializer for MSR Table entries. - */ -typedef struct { - TABLE_ENTRY_TYPE Type; ///< The type of table entry this is. - CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. - PLATFORM_FEATS Features; ///< Common Platform Features match criteria. - MSR_DATA_INITIALIZER EntryData; ///< The special union which accepts msr data initializer. -} MSR_TYPE_ENTRY_INITIALIZER; - -/** - * A union of data types, that can be initialized with MSR CU data. - * - * This ensures the entry data is the same size as TABLE_ENTRY_DATA. - */ -typedef union { - COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA MsrInitializer; ///< The data in the table initializer is assigned to this member. - TABLE_ENTRY_DATA Reserved; ///< Make sure the size is the same as the real union. -} MSR_CU_DATA_INITIALIZER; - -/** - * A type suitable for an initializer for MSR CU count Table entries. - */ -typedef struct { - TABLE_ENTRY_TYPE Type; ///< The type of table entry this is. - CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. - PLATFORM_FEATS Features; ///< Common Platform Features match criteria. - MSR_CU_DATA_INITIALIZER EntryData; ///< The special union which accepts msr data initializer. -} MSR_CU_TYPE_ENTRY_INITIALIZER; - -/** - * A union of data types, that can be initialized with Family Specific Workaround data. - * - * This ensures the entry data is the same size as TABLE_ENTRY_DATA. - */ -typedef union { - FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA FamSpecificInitializer; ///< The data in the table initializer is assigned to this member. - TABLE_ENTRY_DATA Reserved; ///< Make sure the size is the same as the real union. -} FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER; - -/** - * A type suitable for an initializer for Family Specific Workaround Table entries. - */ -typedef struct { - TABLE_ENTRY_TYPE Type; ///< The type of table entry this is. - CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. - PLATFORM_FEATS Features; ///< Common Platform Features match criteria. - FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER EntryData; ///< Special union accepts family specific workaround data initializer. -} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER; - -/*------------------------------------------------------------------------------------------*/ -/* - * Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method). - */ -/*------------------------------------------------------------------------------------------*/ - -/** - * Set the registers for this core based on entries in a list of Register Tables. - */ -VOID SetRegistersFromTables ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Find the features of the running platform. - */ -VOID -GetPlatformFeatures ( - OUT PLATFORM_FEATS *Features, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Checks register table entry type specific criteria to the platform. - */ -BOOLEAN -DoesEntryTypeSpecificInfoMatch ( - IN UINT32 PlatformTypeSpecificFeatures, - IN UINT32 EntryTypeFeatures - ); - -/** - * Perform the MSR Register Entry. - */ -VOID -SetRegisterForMsrEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the PCI Register Entry. - */ -VOID -SetRegisterForPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Performance Profile PCI Register Entry. - */ -VOID -SetRegisterForPerformanceProfileEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the HT Host PCI Register Entry. - */ -VOID -SetRegisterForHtHostEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the HT Host Performance PCI Register Entry. - */ -VOID -SetRegisterForHtHostPerfEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Set the HT Link Token Count registers. - */ -VOID -SetRegisterForHtLinkTokenEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Core Counts Performance PCI Register Entry. - */ -VOID -SetRegisterForCoreCountsPerformanceEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Processor Counts PCI Register Entry. - */ -VOID -SetRegisterForProcessorCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Compute Unit Counts PCI Register Entry. - */ -VOID -SetRegisterForComputeUnitCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Compute Unit Counts MSR Register Entry. - */ -VOID -SetMsrForComputeUnitCountsEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Family Specific Workaround Register Entry. - */ -VOID -SetRegisterForFamSpecificWorkaroundEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Program HT Phy PCI registers. - */ -VOID -SetRegisterForHtPhyEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Program a range of HT Phy PCI registers. - */ -VOID -SetRegisterForHtPhyRangeEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Program Deemphasis registers, for the platform specified levels. - */ -VOID -SetRegisterForDeemphasisEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Program HT Phy PCI registers which have complex frequency dependencies. - */ -VOID -SetRegisterForHtPhyFreqEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the Processor Token Counts PCI Register Entry. - */ -VOID -SetRegisterForTokenPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the HT Link Feature PCI Register Entry. - */ -VOID -SetRegisterForHtFeaturePciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the HT Phy Performance Profile Register Entry. - */ -VOID -SetRegisterForHtPhyProfileEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Perform the HT Link PCI Register Entry. - */ -VOID -SetRegisterForHtLinkPciEntry ( - IN TABLE_ENTRY_DATA *Entry, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Compare counts to a pair of ranges. - */ -BOOLEAN -IsEitherCountInRange ( - IN UINTN FirstCount, - IN UINTN SecondCount, - IN COUNT_RANGE_FEATURE Ranges - ); - -/** - * Returns the performance profile features list of the currently running processor core. - */ -VOID -GetPerformanceFeatures ( - OUT PERFORMANCE_PROFILE_FEATS *Features, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_TABLE_H_ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c deleted file mode 100644 index 68ca2727a5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HyperTransport features and sequence implementation. - * - * Implements the external AmdHtInitialize entry point. - * Contains routines for directing the sequence of available features. - * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be - * contained in this file, and not in the feature code. - * - * From a build option perspective, it may be that a few lines could be removed - * from compilation in this file for certain options. It is considered that - * the code savings from this are too small to be of concern and this file - * should not have any explicit build option implementation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "Filecode.h" - - /*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -// typedef unsigned int uintptr_t; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, - IN AP_MTRR_SETTINGS *ApMtrrSettingsList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -NmiHandler ( - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ); - -VOID -ExecuteHltInstruction ( - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ); - -VOID -ExecuteWbinvdInstruction ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - - /*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/// Structure needed to load the IDTR using the lidt instruction - -VOID -SetIdtr ( - IN IDT_BASE_LIMIT *IdtInfo, - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ) -{ - __lidt (IdtInfo); -} - -//---------------------------------------------------------------------------- - -VOID -GetCsSelector ( - IN UINT16 *Selector, - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ) -{ - static const UINT8 opcode [] = {0x8C, 0xC8, 0xC3}; // mov eax, cs; ret - *Selector = ((UINT16 (*)(void)) (size_t) opcode) (); -} - -//---------------------------------------------------------------------------- - -VOID -NmiHandler ( - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ) -{ - static const UINT8 opcode [] = {0xCF}; // iret - ((void (*)(void)) (size_t) opcode) (); -} - -//---------------------------------------------------------------------------- - -VOID -ExecuteHltInstruction ( - IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr - ) -{ - _disable (); - __halt (); -} - -//--------------------------------------------------------------------------- - -VOID -ExecuteWbinvdInstruction ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - __wbinvd (); -} - -//---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S deleted file mode 100644 index 012c4f750b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -.include "src/vendorcode/amd/agesa/f15/gcccar.inc" - -.code32 -.align 4 -.globl ExecuteFinalHltInstruction - .type ExecuteFinalHltInstruction, @function -/* ExecuteFinalHltInstruction ( - IN UINT32 HaltFlags, - IN AP_MTRR_SETTINGS *ApMtrrSettingsList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -*/ - -/* This function disables CAR. We don't care about the stack on this CPU */ -ExecuteFinalHltInstruction: - movl 4(%esp), %esi /* HaltFlags*/ - movl 8(%esp), %edi /* ApMtrrSettingList */ -//1: jmp 1b //good -/* Do these special steps in case if the core is part of a compute unit - * Note: The following bits are family specific flags, that gets set during build time, - * and indicates things like "family cache control methodology", etc. - * esi bit0 = 0 -> not a Primary core - * esi bit0 = 1 -> Primary core - * esi bit1 = 0 -> Cache disable - * esi bit1 = 1 -> Cache enable - */ - - bt $1, %esi /* .if (esi & 2h) */ - jz 0f - /* Set CombineCr0Cd bit */ - movl $CU_CFG3, %ecx - rdmsr - bts $(COMBINE_CR0_CD - 32), %edx - wrmsr - /* Clear the CR0.CD bit */ - movl %cr0, %eax /* Make sure cache is enabled for all APs */ - btr $CR0_CD, %eax - btr $CR0_NW, %eax - mov %eax, %cr0 /* Write back to CR0 */ - jmp 1f /* .else */ -0: - movl %cr0, %eax /* Make sure cache is disabled for all APs */ - bts $CR0_CD, %eax /* Disable cache */ - bts $CR0_NW, %eax - movl %eax, %cr0 /* Write back to CR0 */ -1: /* .endif */ - -// jmp 1b - bt $0, %esi /* .if (esi & 1h) */ - jz 2f - /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ - movl %edi, %esi /* Get ApMtrrSettingList */ - - /* Configure the MTRRs on the AP so - * when it runs remote code it will execute - * out of RAM instead of ROM. - */ - - /* Disable MTRRs and turn on modification enable bit */ - movl $MTRR_SYS_CFG, %ecx - rdmsr - /* TODO: why comment this? */ - //btr $MTRR_VAR_DRAM_EN, %eax /* Disable */ - bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */ - btr $MTRR_FIX_DRAM_EN, %eax /* Disable */ - //bts $SYS_UC_LOCK_EN, %eax - wrmsr - - /* Setup default values for Fixed-Sized MTRRs */ - /* Set 7FFFh-00000h as WB */ - movl $AMD_AP_MTRR_FIX64k_00000, %ecx - movl $0x1E1E1E1E, %eax - movl %eax, %edx - wrmsr - - /* Set 9FFFFh-80000h also as WB */ - movl $AMD_AP_MTRR_FIX16k_80000, %ecx - wrmsr - - /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */ - movl $AMD_AP_MTRR_FIX16k_A0000, %ecx - xorl %eax, %eax - xorl %edx, %edx - wrmsr - - /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */ - xorl %eax, %eax - xorl %edx, %edx - movl $AMD_AP_MTRR_FIX4k_C0000, %ecx - -CDLoop: - wrmsr - inc %ecx - cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx - jbe CDLoop - - /* Set FFFFFh-E0000h as Uncacheable Memory */ - movl $0x18181818, %eax - movl %eax, %edx - - mov $AMD_AP_MTRR_FIX4k_E0000, %ecx - -EFLoop: - wrmsr - inc %ecx - cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx - jbe EFLoop - - /* If IBV provided settings for Fixed-Sized MTRRs, - * overwrite the default settings. */ - cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */ - jz 4f - cmp $0xFFFFFFFF, %esi - jz 4f - 5: - mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */ - /* While we are not at the end of the list */ - cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/ - je 4f - /* TODO - coreboot isn't checking for valid data. - * Ensure that the MSR address is valid for Fixed-Sized MTRRs */ - /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ - (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \ - (ecx == AMD_AP_MTRR_FIX16k_A0000)) - */ - mov 4(%esi), %eax /* MsrData */ - mov 8(%esi), %edx /* MsrData */ - wrmsr - /* .endif */ - add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */ - jmp 5b /* .endw */ - 4: /* .endif */ - - /* Enable fixed-range and variable-range MTRRs */ - mov $AMD_MTRR_DEFTYPE, %ecx - rdmsr - bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */ - bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */ - wrmsr - - /* Enable Top-of-Memory setting */ - /* Enable use of RdMem/WrMem bits attributes */ - mov $MTRR_SYS_CFG, %ecx - rdmsr - /* TODO: */ - //bts $MTRR_VAR_DRAM_EN, %eax /* Enable */ - btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */ - bts $MTRR_FIX_DRAM_EN, %eax /* Enable */ - wrmsr - - bts $FLAG_IS_PRIMARY, %esi - jmp 3f /* .else ; end if primary core */ - 2: - xor %esi, %esi - 3: /* .endif*/ - -//8: jmp 8b //bad - /* Make sure not to touch any Shared MSR from this point on */ - - AMD_DISABLE_STACK_FAMILY_HOOK - - /* restore variable MTRR6 and MTRR7 to default states */ - bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ - jz 6f - movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ - xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ - xor %edx, %edx - cmp $AMD_MTRR_VARIABLE_BASE6, %ecx /* .while (cl < 010h) */ - jl 6f - wrmsr - dec %ecx - 6: /* .endw */ - - xor %eax, %eax - -7: - cli - hlt - jmp 7b /* ExecuteHltInstruction */ - - .size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c deleted file mode 100644 index f6d452e63b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c +++ /dev/null @@ -1,1443 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU APIC related utility functions. - * - * Contains code that provides mechanism to invoke and control APIC communication. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuCacheInit.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_CPUAPICUTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -/* ApFlags bits */ -#define AP_TASK_HAS_INPUT 0x00000001ul -#define AP_TASK_HAS_OUTPUT 0x00000002ul -#define AP_RETURN_PARAMS 0x00000004ul -#define AP_END_AT_HLT 0x00000008ul -#define AP_PASS_EARLY_PARAMS 0x00000010ul - -#define XFER_ELEMENT_SIZE sizeof (UINT32) - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -typedef VOID F_CPU_AMD_NMI_HANDLER ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -typedef F_CPU_AMD_NMI_HANDLER *PF_CPU_AMD_NMI_HANDLER; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -ApUtilSetupIdtForHlt ( - IN IDT_DESCRIPTOR *NmiIdtDescPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -STATIC -ApUtilRemoteRead ( - IN UINT32 TargetApicId, - IN UINT8 RegAddr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -ApUtilLocalWrite ( - IN UINT32 RegAddr, - IN UINT32 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -STATIC -ApUtilLocalRead ( - IN UINT32 RegAddr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -ApUtilGetLocalApicBase ( - OUT UINT64 *ApicBase, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -STATIC -ApUtilCalculateUniqueId ( - IN UINT8 Socket, - IN UINT8 Core, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -ApUtilFireDirectedNmi ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -ApUtilReceivePointer ( - IN UINT32 TargetApicId, - OUT VOID **ReturnPointer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -ApUtilTransmitPointer ( - IN UINT32 TargetApicId, - IN VOID **Pointer, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -PerformFinalHalt ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LocalApicInitialization ( - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LocalApicInitializationAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern -VOID -ExecuteHltInstruction ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -extern -VOID -NmiHandler ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -extern -VOID -ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, - IN AP_MTRR_SETTINGS *ApMtrrSettingsList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------*/ -/** - * Initialize the Local APIC. - * - * This function determines and programs the appropriate APIC ID value - * for the executing core. This code must be run after HT initialization - * is complete. - * - * @param[in] CpuEarlyParamsPtr Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -LocalApicInitialization ( - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CurrentCore; - UINT32 CurrentNodeNum; - UINT32 CoreIdBits; - UINT32 Mnc; - UINT32 ProcessorCount; - UINT32 ProcessorApicIndex; - UINT32 IoApicNum; - UINT32 StartLocalApicId; - UINT64 LocalApicBase; - UINT32 TempVar_a; - UINT64 MsrData; - UINT64 Address; - CPUID_DATA CpuidData; - - // Local variables default values - IoApicNum = CpuEarlyParamsPtr->PlatformConfig.NumberOfIoApics; - - GetCurrentCore (&CurrentCore, StdHeader); - GetCurrentNodeNum (&CurrentNodeNum, StdHeader); - - // Get Mnc - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader); - CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12; - Mnc = 1 << (CoreIdBits & 0x000F); - - // Get ProcessorCount in the system - ProcessorCount = GetNumberOfProcessors (StdHeader); - - // Get the APIC Index of this processor. - ProcessorApicIndex = GetProcessorApicIndex (CurrentNodeNum, StdHeader); - - TempVar_a = (Mnc * ProcessorCount) + IoApicNum; - ASSERT (TempVar_a < 255); - - // Apply apic enumeration rules - // For systems with >= 16 APICs, put the IO-APICs at 0..n and - // put the local-APICs at m..z - // For systems with < 16 APICs, put the Local-APICs at 0..n and - // put the IO-APICs at (n + 1)..z - // This is needed because many IO-APIC devices only have 4 bits - // for their APIC id and therefore must reside at 0..15 - StartLocalApicId = 0; - if (TempVar_a >= 16) { - if (IoApicNum >= 1) { - StartLocalApicId = (IoApicNum - 1) / Mnc; - StartLocalApicId = (StartLocalApicId + 1) * Mnc; - } - } - - // Set local apic id - TempVar_a = (ProcessorApicIndex * Mnc) + CurrentCore + StartLocalApicId; - IDS_HDT_CONSOLE (CPU_TRACE, " Node %d core %d APIC ID = 0x%x\n", CurrentNodeNum, CurrentCore, TempVar_a); - TempVar_a = TempVar_a << APIC20_ApicId; - - // Enable local apic id - LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader); - MsrData |= APIC_ENABLE_BIT; - LibAmdMsrWrite (MSR_APIC_BAR, &MsrData, StdHeader); - - // Get local apic base Address - ApUtilGetLocalApicBase (&LocalApicBase, StdHeader); - - Address = LocalApicBase + APIC_ID_REG; - LibAmdMemWrite (AccessWidth32, Address, &TempVar_a, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Initialize the Local APIC at the AmdInitEarly entry point. - * - * This function acts as a wrapper for calling the LocalApicInitialization - * routine at AmdInitEarly. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -LocalApicInitializationAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_TESTPOINT (TpProcCpuLocalApicInit, StdHeader); - LocalApicInitialization (EarlyParams, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for all APs in the system. - * - * This routine puts the AP cores in an infinite loop in which the cores - * will poll their masters, waiting to be told to perform a task. At early, - * all socket-relative core zeros will receive their tasks from the BSC. - * All others will receive their tasks from the core zero of their local - * processor. At the end of AmdInitEarly, all cores will switch to receiving - * their tasks from the BSC. - * - * @param[in] StdHeader Handle to config for library and services. - * @param[in] CpuEarlyParams AMD_CPU_EARLY_PARAMS pointer. - * - */ -VOID -ApEntry ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ) -{ - UINT8 RemoteCmd; - UINT8 SourceSocket; - UINT8 CommandStart; - UINT32 ApFlags; - UINT32 FuncType; - UINT32 ReturnCode; - UINT32 CurrentSocket; - UINT32 CurrentCore; - UINT32 *InputDataPtr; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 TargetApicId; - AP_FUNCTION_PTR FuncAddress; - IDT_DESCRIPTOR IdtDesc[32]; - AP_DATA_TRANSFER DataTransferInfo; - AGESA_STATUS IgnoredSts; - - ASSERT (!IsBsp (StdHeader, &IgnoredSts)); - - // Initialize local variables - ReturnCode = 0; - DataTransferInfo.DataTransferFlags = 0; - InputDataPtr = NULL; - - // Determine the executing core's socket and core numbers - IdentifyCore (StdHeader, &CurrentSocket, &Ignored, &CurrentCore, &IgnoredSts); - - IDS_HDT_CONSOLE (CPU_TRACE, " Socket %d core %d begin AP tasking engine\n", CurrentSocket, CurrentCore); - - // Determine the BSC's socket number - GetSocketModuleOfNode ((UINT32) 0x00000000, &BscSocket, &Ignored, StdHeader); - - // Setup Interrupt Descriptor Table for sleep mode - ApUtilSetupIdtForHlt (&IdtDesc[2], StdHeader); - - // Indicate to the BSC that we have reached the tasking engine - ApUtilWriteControlByte (CORE_IDLE, StdHeader); - - if (CurrentCore == 0) { - // Core 0s receive their tasks from the BSC - SourceSocket = (UINT8) BscSocket; - } else { - // All non-zero cores receive their tasks from the core 0 of their socket - SourceSocket = (UINT8) CurrentSocket; - } - - GetLocalApicIdForCore (SourceSocket, 0, &TargetApicId, StdHeader); - - // Determine the unique value that the master will write when it has a task - // for this core to perform. - CommandStart = ApUtilCalculateUniqueId ( - (UINT8)CurrentSocket, - (UINT8)CurrentCore, - StdHeader - ); - for (;;) { - RemoteCmd = ApUtilReadRemoteControlByte (TargetApicId, StdHeader); - if (RemoteCmd == CommandStart) { - ApFlags = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - - ApUtilReceivePointer (TargetApicId, (VOID **) &FuncAddress, StdHeader); - - FuncType = ApFlags & (UINT32) (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS); - if ((ApFlags & AP_TASK_HAS_INPUT) != 0) { - DataTransferInfo.DataSizeInDwords = 0; - DataTransferInfo.DataPtr = NULL; - DataTransferInfo.DataTransferFlags = 0; - if (ApUtilReceiveBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader) == AGESA_ERROR) { - // There is not enough space to put the input data on the heap. Undefined behavior is about - // to result. - IDS_ERROR_TRAP; - } - InputDataPtr = (UINT32 *) DataTransferInfo.DataPtr; - } - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); - switch (FuncType) { - case 0: - FuncAddress.PfApTask (StdHeader); - break; - case AP_TASK_HAS_INPUT: - FuncAddress.PfApTaskI (InputDataPtr, StdHeader); - break; - case AP_PASS_EARLY_PARAMS: - FuncAddress.PfApTaskC (StdHeader, CpuEarlyParams); - break; - case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS): - FuncAddress.PfApTaskIC (InputDataPtr, StdHeader, CpuEarlyParams); - break; - case AP_TASK_HAS_OUTPUT: - ReturnCode = FuncAddress.PfApTaskO (StdHeader); - break; - case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT): - ReturnCode = FuncAddress.PfApTaskIO (InputDataPtr, StdHeader); - break; - case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): - ReturnCode = FuncAddress.PfApTaskOC (StdHeader, CpuEarlyParams); - break; - case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): - ReturnCode = FuncAddress.PfApTaskIOC (InputDataPtr, StdHeader, CpuEarlyParams); - break; - default: - ReturnCode = 0; - break; - } - if (((ApFlags & AP_RETURN_PARAMS) != 0)) { - ApUtilTransmitBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader); - } - if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) { - ApUtilWriteDataDword (ReturnCode, StdHeader); - } - if ((ApFlags & AP_END_AT_HLT) != 0) { - RemoteCmd = CORE_IDLE_HLT; - } else { - ApUtilWriteControlByte (CORE_IDLE, StdHeader); - } - } - if (RemoteCmd == CORE_IDLE_HLT) { - SourceSocket = (UINT8) BscSocket; - GetLocalApicIdForCore (SourceSocket, 0, &TargetApicId, StdHeader); - ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader); - ExecuteHltInstruction (StdHeader); - ApUtilWriteControlByte (CORE_IDLE, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Reads the 'control byte' on the designated remote core. - * - * This function will read the current contents of the control byte - * on the designated core using the APIC remote read inter- - * processor interrupt sequence. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[in] StdHeader Configuration parameters pointer - * - * @return The current value of the remote cores control byte - * - */ -UINT8 -ApUtilReadRemoteControlByte ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 ControlByte; - UINT32 ApicRegister; - - ApicRegister = ApUtilRemoteRead (TargetApicId, APIC_CTRL_DWORD, StdHeader); - ControlByte = (UINT8) ((ApicRegister & APIC_CTRL_MASK) >> APIC_CTRL_SHIFT); - return (ControlByte); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Writes the 'control byte' on the executing core. - * - * This function writes data to a local APIC offset used in inter- - * processor communication. - * - * @param[in] Value - * @param[in] StdHeader - * - */ -VOID -ApUtilWriteControlByte ( - IN UINT8 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ApicRegister; - - ApicRegister = ApUtilLocalRead (APIC_CTRL_REG, StdHeader); - ApicRegister = ((ApicRegister & ~APIC_CTRL_MASK) | (UINT32) (Value << APIC_CTRL_SHIFT)); - ApUtilLocalWrite (APIC_CTRL_REG, ApicRegister, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Reads the 'data dword' on the designated remote core. - * - * This function will read the current contents of the data dword - * on the designated core using the APIC remote read inter- - * processor interrupt sequence. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[in] StdHeader Configuration parameters pointer - * - * @return The current value of the remote core's data dword - * - */ -UINT32 -ApUtilReadRemoteDataDword ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (ApUtilRemoteRead (TargetApicId, APIC_DATA_DWORD, StdHeader)); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Writes the 'data dword' on the executing core. - * - * This function writes data to a local APIC offset used in inter- - * processor communication. - * - * @param[in] Value Value to write - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -ApUtilWriteDataDword ( - IN UINT32 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - ApUtilLocalWrite (APIC_DATA_REG, Value, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Runs the given task on the specified local core. - * - * This function is used to invoke an AP to run a specified AGESA - * procedure. It can only be called by cores that have subordinate - * APs -- the BSC at POST, or any socket-relative core 0s at Early. - * - * @param[in] Socket Socket number of the target core - * @param[in] Core Core number of the target core - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Configuration parameters pointer - * - * @return Return value of the task that the AP core ran, - * or zero if the task was VOID. - * - */ -UINT32 -ApUtilRunCodeOnSocketCore ( - IN UINT8 Socket, - IN UINT8 Core, - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 CoreId; - UINT8 CurrentStatus; - UINT8 WaitStatus[3]; - UINT32 ApFlags; - UINT32 ReturnCode; - UINT32 TargetApicId; - AP_WAIT_FOR_STATUS WaitForStatus; - - ApFlags = 0; - ReturnCode = 0; - - CoreId = ApUtilCalculateUniqueId (Socket, Core, StdHeader); - - GetLocalApicIdForCore (Socket, Core, &TargetApicId, StdHeader); - - if (TaskPtr->DataTransfer.DataSizeInDwords != 0) { - ApFlags |= AP_TASK_HAS_INPUT; - if (((TaskPtr->ExeFlags & RETURN_PARAMS) != 0) && - ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) { - ApFlags |= AP_RETURN_PARAMS; - } - } - - if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) { - ApFlags |= AP_TASK_HAS_OUTPUT; - } - - if ((TaskPtr->ExeFlags & END_AT_HLT) != 0) { - ApFlags |= AP_END_AT_HLT; - } - - if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) { - ApFlags |= AP_PASS_EARLY_PARAMS; - } - - WaitStatus[0] = CORE_IDLE; - WaitStatus[1] = CORE_IDLE_HLT; - WaitStatus[2] = CORE_UNAVAILABLE; - WaitForStatus.Status = WaitStatus; - WaitForStatus.NumberOfElements = 3; - WaitForStatus.RetryCount = WAIT_INFINITELY; - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - CurrentStatus = ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - - if (CurrentStatus != CORE_UNAVAILABLE) { - ApUtilWriteDataDword (ApFlags, StdHeader); - ApUtilWriteControlByte (CoreId, StdHeader); - - if (CurrentStatus == CORE_IDLE_HLT) { - ApUtilFireDirectedNmi (TargetApicId, StdHeader); - } - - ApUtilTransmitPointer (TargetApicId, (VOID **) &TaskPtr->FuncAddress, StdHeader); - - if ((ApFlags & AP_TASK_HAS_INPUT) != 0) { - ApUtilTransmitBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader); - } - - if ((TaskPtr->ExeFlags & WAIT_FOR_CORE) != 0) { - if (((ApFlags & AP_TASK_HAS_INPUT) != 0) && - ((ApFlags & AP_RETURN_PARAMS) != 0) && - ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) { - if (ApUtilReceiveBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader) == AGESA_ERROR) { - // There is not enough space to put the return data. This should never occur. If it - // does, this would point to strange heap corruption. - IDS_ERROR_TRAP; - } - } - - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) { - ReturnCode = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - } - } - } else { - ReturnCode = 0; - } - return (ReturnCode); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Waits for a remote core's control byte value to either be equal or - * not equal to any number of specified values. - * - * This function will loop doing remote read IPIs until the remote core's - * control byte becomes one of the values in the input array if the input - * flags are set for equality. Otherwise, the loop will continue until - * the control byte value is not equal to one of the elements in the - * array. The caller can also specify an iteration count for timeout - * purposes. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[in] WaitParamsPtr Wait parameter structure - * @param[in] StdHeader Configuration parameteres pointer - * - * @return The current value of the remote core's control byte - * - */ -UINT8 -ApUtilWaitForCoreStatus ( - IN UINT32 TargetApicId, - IN AP_WAIT_FOR_STATUS *WaitParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsEqual; - UINT8 CoreStatus; - UINT8 i; - UINT8 j; - - CoreStatus = 0; - for (i = 0; (WaitParamsPtr->RetryCount == WAIT_INFINITELY) || - (i < WaitParamsPtr->RetryCount); ++i) { - CoreStatus = ApUtilReadRemoteControlByte (TargetApicId, StdHeader); - // Determine whether or not the current remote status is equal - // to an element in the array. - IsEqual = FALSE; - for (j = 0; !IsEqual && j < WaitParamsPtr->NumberOfElements; ++j) { - if (CoreStatus == WaitParamsPtr->Status[j]) { - IsEqual = TRUE; - } - } - if ((((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) != 0) && IsEqual) || - (((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) == 0) && !IsEqual)) { - break; - } - } - return (CoreStatus); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Runs the AP task on the executing core. - * - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Configuration parameters pointer - * @param[in] ConfigParams Entry point CPU parameters pointer - * - * @return Return value of the task, or zero if the task - * was VOID. - * - */ -UINT32 -ApUtilTaskOnExecutingCore ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ) -{ - UINT32 InvocationOptions; - UINT32 ReturnCode; - - ReturnCode = 0; - InvocationOptions = 0; - - if (TaskPtr->DataTransfer.DataSizeInDwords != 0) { - InvocationOptions |= AP_TASK_HAS_INPUT; - } - if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) { - InvocationOptions |= AP_TASK_HAS_OUTPUT; - } - if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) { - InvocationOptions |= AP_PASS_EARLY_PARAMS; - } - - switch (InvocationOptions) { - case 0: - TaskPtr->FuncAddress.PfApTask (StdHeader); - break; - case AP_TASK_HAS_INPUT: - TaskPtr->FuncAddress.PfApTaskI (TaskPtr->DataTransfer.DataPtr, StdHeader); - break; - case AP_PASS_EARLY_PARAMS: - TaskPtr->FuncAddress.PfApTaskC (StdHeader, ConfigParams); - break; - case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS): - TaskPtr->FuncAddress.PfApTaskIC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams); - break; - case AP_TASK_HAS_OUTPUT: - ReturnCode = TaskPtr->FuncAddress.PfApTaskO (StdHeader); - break; - case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT): - ReturnCode = TaskPtr->FuncAddress.PfApTaskIO (TaskPtr->DataTransfer.DataPtr, StdHeader); - break; - case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): - ReturnCode = TaskPtr->FuncAddress.PfApTaskOC (StdHeader, ConfigParams); - break; - case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): - ReturnCode = TaskPtr->FuncAddress.PfApTaskIOC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams); - break; - default: - ReturnCode = 0; - break; - } - return (ReturnCode); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Sets up the AP's IDT with NMI (INT2) being the only valid descriptor - * - * This function prepares the executing AP core for recovering from a hlt - * instruction by initializing its IDTR. - * - * @param[in] NmiIdtDescPtr Pointer to a writable IDT entry to - * be used for NMIs - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilSetupIdtForHlt ( - IN IDT_DESCRIPTOR *NmiIdtDescPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 DescSize; - UINT64 HandlerOffset; - UINT64 EferRegister; - IDT_BASE_LIMIT IdtInfo; - - LibAmdMsrRead (MSR_EXTENDED_FEATURE_EN, &EferRegister, StdHeader); - if ((EferRegister & 0x100) != 0) { - DescSize = 16; - } else { - DescSize = 8; - } - - HandlerOffset = (UINT64) (UINTN) NmiHandler; - NmiIdtDescPtr->OffsetLo = (UINT16) HandlerOffset & 0xFFFF; - NmiIdtDescPtr->OffsetHi = (UINT16) (HandlerOffset >> 16); - GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader); - NmiIdtDescPtr->Flags = IDT_DESC_PRESENT | IDT_DESC_TYPE_INT32; - NmiIdtDescPtr->Rsvd = 0; - NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32); - NmiIdtDescPtr->Rsvd64 = 0; - IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1); - IdtInfo.Base = (UINT64) (UINTN) NmiIdtDescPtr - (DescSize * 2); - IDS_EXCEPTION_TRAP (IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, &IdtInfo, StdHeader); - SetIdtr (&IdtInfo , StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Calculate the APIC ID for a given core. - * - * Get the current node's apic id and deconstruct it to the base id of local apic id space. - * Then construct the target's apic id using that base. - * @b Assumes: The target Socket and Core exist! - * Other Notes: - * - Must run after HT initialization is complete. - * - Code sync: This calculation MUST match the assignment - * calculation done above in LocalApicInitializationAtEarly function. - * - Assumes family homogeneous population of all sockets. - * - * @param[in] TargetSocket The socket in which the Core's Processor is installed. - * @param[in] TargetCore The Core on that Processor - * @param[out] LocalApicId Its APIC Id - * @param[in] StdHeader Handle to header for library and services. - * - */ -VOID -GetLocalApicIdForCore ( - IN UINT32 TargetSocket, - IN UINT32 TargetCore, - OUT UINT32 *LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CoreIdBits; - UINT32 CurrentNode; - UINT32 CurrentCore; - UINT32 TargetNode; - UINT32 MaxCoresInProcessor; - UINT32 TotalCores; - UINT32 CurrentLocalApicId; - UINT64 LocalApicBase; - UINT32 TempVar_a; - UINT64 Address; - UINT32 ProcessorApicIndex; - BOOLEAN ReturnResult; - CPUID_DATA CpuidData; - - TargetNode = 0; - - // Get local apic base Address - ApUtilGetLocalApicBase (&LocalApicBase, StdHeader); - Address = LocalApicBase + APIC_ID_REG; - - LibAmdMemRead (AccessWidth32, Address, &TempVar_a, StdHeader); - - // ApicId [7:0] - CurrentLocalApicId = (TempVar_a >> APIC20_ApicId) & 0x000000FF; - - GetCurrentNodeAndCore (&CurrentNode, &CurrentCore, StdHeader); - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader); - CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12; - MaxCoresInProcessor = (1 << CoreIdBits); - - // Get the APIC Index of this processor. - ProcessorApicIndex = GetProcessorApicIndex (CurrentNode, StdHeader); - - TotalCores = (MaxCoresInProcessor * ProcessorApicIndex) + CurrentCore; - CurrentLocalApicId -= TotalCores; - - // Use the Node Id of TargetSocket, Module 0. No socket transitions are missed or added, - // even if the TargetCore is not on Module 0 in that processor and that's all that matters now. - ReturnResult = GetNodeId (TargetSocket, 0, (UINT8 *)&TargetNode, StdHeader); - ASSERT (ReturnResult); - - // Get the APIC Index of this processor. - ProcessorApicIndex = GetProcessorApicIndex (TargetNode, StdHeader); - - CurrentLocalApicId += ((MaxCoresInProcessor * ProcessorApicIndex) + TargetCore); - *LocalApicId = CurrentLocalApicId; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Securely passes a buffer to the designated remote core. - * - * This function uses a sequence of remote reads to transmit a data - * buffer, one UINT32 at a time. - * - * @param[in] Socket Socket number of the remote core - * @param[in] Core Core number of the remote core - * @param[in] BufferInfo Information about the buffer to pass, and - * how to pass it - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -ApUtilTransmitBuffer ( - IN UINT8 Socket, - IN UINT8 Core, - IN AP_DATA_TRANSFER *BufferInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 TargetCore; - UINT8 MyUniqueId; - UINT8 CurrentStatus; - UINT32 *CurrentPtr; - UINT32 i; - UINT32 MyCore; - UINT32 MySocket; - UINT32 Ignored; - UINT32 TargetApicId; - AP_WAIT_FOR_STATUS WaitForStatus; - AGESA_STATUS IgnoredSts; - - GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader); - - if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) { - ApUtilWriteDataDword ((UINT32) 0x00000000, StdHeader); - } else { - ApUtilWriteDataDword ((UINT32) BufferInfo->DataSizeInDwords, StdHeader); - } - TargetCore = ApUtilCalculateUniqueId (Socket, Core, StdHeader); - - ApUtilWriteControlByte (TargetCore, StdHeader); - - IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &IgnoredSts); - - MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader); - - WaitForStatus.Status = &MyUniqueId; - WaitForStatus.NumberOfElements = 1; - WaitForStatus.RetryCount = WAIT_INFINITELY; - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - ApUtilWriteDataDword (BufferInfo->DataTransferFlags, StdHeader); - - ApUtilWriteControlByte (CORE_DATA_FLAGS_READY, StdHeader); - WaitForStatus.WaitForStatusFlags = 0; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) { - ApUtilTransmitPointer (TargetApicId, (VOID **) &BufferInfo->DataPtr, StdHeader); - } else { - ApUtilWriteControlByte (CORE_STS_DATA_READY_1, StdHeader); - CurrentStatus = CORE_STS_DATA_READY_0; - WaitForStatus.Status = &CurrentStatus; - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - WaitForStatus.WaitForStatusFlags = 0; - CurrentPtr = (UINT32 *) BufferInfo->DataPtr; - for (i = 0; i < BufferInfo->DataSizeInDwords; ++i) { - ApUtilWriteDataDword (*CurrentPtr++, StdHeader); - ApUtilWriteControlByte (CurrentStatus, StdHeader); - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - CurrentStatus ^= 0x01; - } - } - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Securely receives a buffer from the designated remote core. - * - * This function uses a sequence of remote reads to receive a data - * buffer, one UINT32 at a time. - * - * @param[in] Socket Socket number of the remote core - * @param[in] Core Core number of the remote core - * @param[in] BufferInfo Information about where to place the buffer - * @param[in] StdHeader Configuration parameters pointer - * - * @retval AGESA_SUCCESS Transaction was successful - * @retval AGESA_ALERT The non-NULL desired location to place - * the buffer was not used as the buffer - * resides in a shared memory space. The - * input data pointer has changed. - * @retval AGESA_ERROR There is not enough room to receive the - * buffer. - * - */ -AGESA_STATUS -ApUtilReceiveBuffer ( - IN UINT8 Socket, - IN UINT8 Core, - IN OUT AP_DATA_TRANSFER *BufferInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MyUniqueId; - UINT8 SourceUniqueId; - UINT8 CurrentStatus; - UINT32 i; - UINT32 MySocket; - UINT32 MyCore; - UINT32 Ignored; - UINT32 *CurrentPtr; - UINT32 TransactionSize; - UINT32 TargetApicId; - AGESA_STATUS ReturnStatus; - ALLOCATE_HEAP_PARAMS HeapMalloc; - AP_WAIT_FOR_STATUS WaitForStatus; - - ReturnStatus = AGESA_SUCCESS; - IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &ReturnStatus); - - MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader); - - GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader); - - WaitForStatus.Status = &MyUniqueId; - WaitForStatus.NumberOfElements = 1; - WaitForStatus.RetryCount = WAIT_INFINITELY; - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - TransactionSize = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - - if (BufferInfo->DataPtr == NULL && TransactionSize != 0) { - HeapMalloc.BufferHandle = AMD_CPU_AP_TASKING_HANDLE; - HeapMalloc.Persist = HEAP_LOCAL_CACHE; - // Deallocate the general purpose heap structure, if it exists. Ignore - // the status in case it does not exist. - HeapDeallocateBuffer (HeapMalloc.BufferHandle, StdHeader); - HeapMalloc.RequestedBufferSize = (TransactionSize * XFER_ELEMENT_SIZE); - if (HeapAllocateBuffer (&HeapMalloc, StdHeader) == AGESA_SUCCESS) { - BufferInfo->DataPtr = (UINT32 *) HeapMalloc.BufferPtr; - BufferInfo->DataSizeInDwords = (UINT16) (HeapMalloc.RequestedBufferSize / XFER_ELEMENT_SIZE); - } else { - BufferInfo->DataSizeInDwords = 0; - } - } - - if (TransactionSize <= BufferInfo->DataSizeInDwords) { - SourceUniqueId = ApUtilCalculateUniqueId (Socket, Core, StdHeader); - ApUtilWriteControlByte (SourceUniqueId, StdHeader); - CurrentStatus = CORE_DATA_FLAGS_READY; - WaitForStatus.Status = &CurrentStatus; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - BufferInfo->DataTransferFlags = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - ApUtilWriteControlByte (CORE_DATA_FLAGS_ACKNOWLEDGE, StdHeader); - if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) { - if (BufferInfo->DataPtr != NULL) { - ReturnStatus = AGESA_ALERT; - } - ApUtilReceivePointer (TargetApicId, (VOID **) &BufferInfo->DataPtr, StdHeader); - } else { - CurrentStatus = CORE_STS_DATA_READY_1; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - CurrentStatus = CORE_STS_DATA_READY_0; - ApUtilWriteControlByte (CurrentStatus, StdHeader); - CurrentPtr = BufferInfo->DataPtr; - for (i = 0; i < TransactionSize; ++i) { - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - *CurrentPtr++ = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - CurrentStatus ^= 0x01; - ApUtilWriteControlByte (CurrentStatus, StdHeader); - } - } - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); - } else { - BufferInfo->DataSizeInDwords = (UINT16) TransactionSize; - ReturnStatus = AGESA_ERROR; - } - return (ReturnStatus); -} - - -VOID -RelinquishControlOfAllAPs ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - TaskPtr.FuncAddress.PfApTask = PerformFinalHalt; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &Core, StdHeader)) { - while (Core-- > 0) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * The last AGESA code that an AP performs - * - * This function, run only by APs, breaks down their cache subsystem, sets up - * for memory to be present upon wake (from IBV Init/Startup IPIs), and halts. - * - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -PerformFinalHalt ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 PrimaryCore; - UINT32 HaltFlags; - UINT32 CacheEnDis; - CPU_SPECIFIC_SERVICES *FamilyServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - // CacheEnDis is a family specific flag, that lets the code to decide whether to - // keep the cache control bits set or cleared. - CacheEnDis = FamilyServices->InitCacheDisabled; - - // Determine if the current core has the primary core role. The first core to execute - // in each compute unit has the primary role. - PrimaryCore = (UINT32) IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader); - - // Aggregate the flags for the halt service. - HaltFlags = PrimaryCore | (CacheEnDis << 1); - - ApUtilWriteControlByte (CORE_UNAVAILABLE, StdHeader); - ExecuteFinalHltInstruction (HaltFlags, UserOptions.CfgApMtrrSettingsList, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Reads the APIC register on the designated remote core. - * - * This function uses the remote read inter-processor interrupt protocol - * to read an APIC register from the remote core - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[in] RegAddr APIC register to read - * @param[in] StdHeader Configuration parameters pointer - * - * @return The current value of the remote core's desired APIC register - * - */ -UINT32 -STATIC -ApUtilRemoteRead ( - IN UINT32 TargetApicId, - IN UINT8 RegAddr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ApicRegister; - UINT64 ApicBase; - UINT64 ApicAddr; - - ApUtilGetLocalApicBase (&ApicBase, StdHeader); - TargetApicId <<= LOCAL_APIC_ID; - - do { - ApicAddr = ApicBase + APIC_CMD_HI_REG; - LibAmdMemWrite (AccessWidth32, ApicAddr, &TargetApicId, StdHeader); - ApicAddr = ApicBase + APIC_CMD_LO_REG; - ApicRegister = CMD_REG_TO_READ | (UINT32) RegAddr; - LibAmdMemWrite (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); - do { - LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); - } while ((ApicRegister & CMD_REG_DELIVERY_STATUS) != 0); - while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) == CMD_REG_REMOTE_DELIVERY_PENDING) { - LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); - } - } while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) != CMD_REG_REMOTE_DELIVERY_DONE); - ApicAddr = ApicBase + APIC_REMOTE_READ_REG; - LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); - return (ApicRegister); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Writes an APIC register on the executing core. - * - * This function gets the base address of the executing core's local APIC, - * and writes a UINT32 value to a specified offset. - * - * @param[in] RegAddr APIC register to write to - * @param[in] Value Data to be written to the desired APIC register - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilLocalWrite ( - IN UINT32 RegAddr, - IN UINT32 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 ApicAddr; - - ApUtilGetLocalApicBase (&ApicAddr, StdHeader); - ApicAddr += RegAddr; - - LibAmdMemWrite (AccessWidth32, ApicAddr, &Value, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Reads an APIC register on the executing core. - * - * This function gets the base address of the executing core's local APIC, - * and reads a UINT32 value from a specified offset. - * - * @param[in] RegAddr APIC register to read from - * @param[in] StdHeader Configuration parameters pointer - * - * @return The current value of the local APIC register - * - */ -UINT32 -STATIC -ApUtilLocalRead ( - IN UINT32 RegAddr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ApicRegister; - UINT64 ApicAddr; - - ApUtilGetLocalApicBase (&ApicAddr, StdHeader); - ApicAddr += RegAddr; - LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); - - return (ApicRegister); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the 64-bit base address of the executing core's local APIC. - * - * This function reads the APICBASE MSR and isolates the programmed address. - * - * @param[out] ApicBase Base address - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilGetLocalApicBase ( - OUT UINT64 *ApicBase, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMsrRead (MSR_APIC_BAR, ApicBase, StdHeader); - *ApicBase &= LAPIC_BASE_ADDR_MASK; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the unique ID of the input Socket/Core. - * - * This routine converts a socket-core combination to to a number - * that will be used to directly address a particular core. This - * unique value must be less than 128 because we only have a byte - * to use for status. APIC IDs are not guaranteed to be below - * 128. - * - * @param[in] Socket Socket number of the remote core - * @param[in] Core Core number of the remote core - * @param[in] StdHeader Configuration parameters pointer - * - * @return The unique ID of the desired core - * - */ -UINT8 -STATIC -ApUtilCalculateUniqueId ( - IN UINT8 Socket, - IN UINT8 Core, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 UniqueId; - - UniqueId = ((Core << 3) | Socket); - ASSERT ((UniqueId & 0x80) == 0); - return (UniqueId); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Wakes up a core from the halted state. - * - * This function sends a directed NMI inter-processor interrupt to - * the input Socket/Core. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilFireDirectedNmi ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - TargetApicId <<= LOCAL_APIC_ID; - - ApUtilLocalWrite ((UINT32) APIC_CMD_HI_REG, TargetApicId, StdHeader); - ApUtilLocalWrite ((UINT32) APIC_CMD_LO_REG, (UINT32) CMD_REG_TO_NMI, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Securely receives a pointer from the designated remote core. - * - * This function uses a sequence of remote reads to receive a pointer, - * one UINT32 at a time. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[out] ReturnPointer Pointer passed from remote core - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilReceivePointer ( - IN UINT32 TargetApicId, - OUT VOID **ReturnPointer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 WaitStatus; - UINT32 *AddressScratchPtr; - AP_WAIT_FOR_STATUS WaitForStatus; - - WaitStatus = CORE_STS_DATA_READY_0; - WaitForStatus.Status = &WaitStatus; - WaitForStatus.NumberOfElements = 1; - WaitForStatus.RetryCount = WAIT_INFINITELY; - AddressScratchPtr = (UINT32 *) ReturnPointer; - for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); ++i) { - ApUtilWriteControlByte (CORE_NEEDS_PTR, StdHeader); - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - *AddressScratchPtr++ = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); - WaitForStatus.WaitForStatusFlags = 0; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Securely transmits a pointer to the designated remote core. - * - * This function uses a sequence of remote reads to transmit a pointer, - * one UINT32 at a time. - * - * @param[in] TargetApicId Local APIC ID of the desired core - * @param[out] Pointer Pointer passed from remote core - * @param[in] StdHeader Configuration parameters pointer - * - */ -VOID -STATIC -ApUtilTransmitPointer ( - IN UINT32 TargetApicId, - IN VOID **Pointer, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 WaitStatus; - UINT32 *AddressScratchPtr; - AP_WAIT_FOR_STATUS WaitForStatus; - - WaitStatus = CORE_NEEDS_PTR; - WaitForStatus.Status = &WaitStatus; - WaitForStatus.NumberOfElements = 1; - WaitForStatus.RetryCount = WAIT_INFINITELY; - - AddressScratchPtr = (UINT32 *) Pointer; - - for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); i++) { - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - ApUtilWriteDataDword (*AddressScratchPtr++, StdHeader); - ApUtilWriteControlByte (CORE_STS_DATA_READY_0, StdHeader); - WaitForStatus.WaitForStatusFlags = 0; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.h deleted file mode 100644 index 464dcfb518..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.h +++ /dev/null @@ -1,304 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU APIC related utility functions and structures - * - * Contains code that provides mechanism to invoke and control APIC communication. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44393 $ @e \$Date: 2010-12-23 16:38:46 -0700 (Thu, 23 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_APIC_UTILITIES_H_ -#define _CPU_APIC_UTILITIES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -#define APIC_CTRL_DWORD 0xF -#define APIC_CTRL_REG (APIC_CTRL_DWORD << 4) -#define APIC_CTRL_MASK 0xFF -#define APIC_CTRL_SHIFT 0 - -#define APIC_DATA_DWORD 0x38 -#define APIC_DATA_REG (APIC_DATA_DWORD << 4) - -#define APIC_REMOTE_READ_REG 0xC0 -#define APIC_CMD_LO_REG 0x300 -#define APIC_CMD_HI_REG 0x310 - -// APIC_CMD_LO_REG bits -#define CMD_REG_DELIVERY_STATUS 0x1000 -#define CMD_REG_TO_READ 0x300 -#define CMD_REG_REMOTE_RD_STS_MSK 0x30000 -#define CMD_REG_REMOTE_DELIVERY_PENDING 0x10000 -#define CMD_REG_REMOTE_DELIVERY_DONE 0x20000 -#define CMD_REG_TO_NMI 0x400 - -// ExeFlags bits -#define WAIT_FOR_CORE 0x00000001 -#define TASK_HAS_OUTPUT 0x00000002 -#define RETURN_PARAMS 0x00000004 -#define END_AT_HLT 0x00000008 -#define PASS_EARLY_PARAMS 0x00000010 - -// Control Byte Values -// bit 7 indicates the type of message -// 1 - control message -// 0 - launch + APIC ID = message to go -// -#define CORE_UNAVAILABLE 0xFF -#define CORE_IDLE 0xFE -#define CORE_IDLE_HLT 0xFD -#define CORE_ACTIVE 0xFC -#define CORE_NEEDS_PTR 0xFB -#define CORE_NEEDS_DATA_SIZE 0xFA -#define CORE_STS_DATA_READY_1 0xF9 -#define CORE_STS_DATA_READY_0 0xF8 -#define CORE_DATA_FLAGS_READY 0xF7 -#define CORE_DATA_FLAGS_ACKNOWLEDGE 0xF6 -#define CORE_DATA_PTR_READY 0xF5 - -// Macro used to determine the number of dwords to transmit to the AP as input -#define SIZE_IN_DWORDS(sInput) ((UINT32) (((sizeof (sInput)) + 3) >> 2)) - -// IDT table -#define IDT_DESC_PRESENT 0x80 - -#define IDT_DESC_TYPE_LDT 0x02 -#define IDT_DESC_TYPE_CALL16 0x04 -#define IDT_DESC_TYPE_TASK 0x05 -#define IDT_DESC_TYPE_INT16 0x06 -#define IDT_DESC_TYPE_TRAP16 0x07 -#define IDT_DESC_TYPE_CALL32 0x0C -#define IDT_DESC_TYPE_INT32 0x0E -#define IDT_DESC_TYPE_TRAP32 0x0F -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -typedef VOID (*PF_AP_TASK) (AMD_CONFIG_PARAMS *StdHeader); -typedef VOID (*PF_AP_TASK_I) (VOID *, AMD_CONFIG_PARAMS *StdHeader); -typedef VOID (*PF_AP_TASK_C) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); -typedef VOID (*PF_AP_TASK_IC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); -typedef UINT32 (*PF_AP_TASK_O) (AMD_CONFIG_PARAMS *StdHeader); -typedef UINT32 (*PF_AP_TASK_IO) (VOID *, AMD_CONFIG_PARAMS *StdHeader); -typedef UINT32 (*PF_AP_TASK_OC) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); -typedef UINT32 (*PF_AP_TASK_IOC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); - -/// Function pointer union representing the eight different -/// types of functions that an AP can be asked to perform. -typedef union { - PF_AP_TASK PfApTask; ///< AMD_CONFIG_PARAMS * input with no output - PF_AP_TASK_I PfApTaskI; ///< VOID * + AMD_CONFIG_PARAMS * input with no output - PF_AP_TASK_C PfApTaskC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output - PF_AP_TASK_IC PfApTaskIC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output - PF_AP_TASK_O PfApTaskO; ///< AMD_CONFIG_PARAMS * input with UINT32 output - PF_AP_TASK_IO PfApTaskIO; ///< VOID * + AMD_CONFIG_PARAMS * input with UINT32 output - PF_AP_TASK_OC PfApTaskOC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output - PF_AP_TASK_IOC PfApTaskIOC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output -} AP_FUNCTION_PTR; - -/// Input structure for ApUtilTransmitBuffer and ApUtilReceiveBuffer -/// containing information about the data transfer from one core -/// to another. -typedef struct { - IN OUT UINT16 DataSizeInDwords; ///< Size of the data to be transferred rounded up to the nearest dword - IN OUT VOID *DataPtr; ///< Pointer to the data - IN UINT32 DataTransferFlags; ///< Flags dictating certain aspects of the data transfer -} AP_DATA_TRANSFER; - -/// Input structure for ApUtilRunCodeOnSocketCore. -typedef struct _AP_TASK { - AP_FUNCTION_PTR FuncAddress; ///< Pointer to the function that the AP will run - AP_DATA_TRANSFER DataTransfer; ///< Data transfer struct for optionally passing data that the AP should use as input to the function - UINT32 ExeFlags; ///< Flags dictating certain aspects of the AP tasking sequence -} AP_TASK; - -/// Input structure for ApUtilWaitForCoreStatus. -typedef struct { - IN UINT8 *Status; ///< Pointer to the 1st element of an array of values to wait for - IN UINT8 NumberOfElements; ///< Number of elements in the array - IN UINT32 RetryCount; ///< Number of remote read cycles to complete before quitting - IN UINT32 WaitForStatusFlags; ///< Flags dictating certain aspects of ApUtilWaitForCoreStatus -} AP_WAIT_FOR_STATUS; - -/// Interrupt Descriptor Table entry -typedef struct { - UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset - UINT16 Selector; ///< Interrupt handler routine's selector - UINT8 Rsvd; ///< Reserved - UINT8 Flags; ///< Interrupt flags - UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset - UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode - UINT32 Rsvd64; ///< Reserved -} IDT_DESCRIPTOR; - -/// Structure needed to load the IDTR using the lidt instruction -typedef struct { - UINT16 Limit; ///< Interrupt Descriptor Table size - UINT64 Base; ///< Interrupt Descriptor Table base address -} IDT_BASE_LIMIT; - -#define WAIT_STATUS_EQUALITY 0x00000001 -#define WAIT_INFINITELY 0 - -// Data Transfer Flags -#define DATA_IN_MEMORY 0x00000001 - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -// These are P U B L I C functions, used by AGESA -UINT8 -ApUtilReadRemoteControlByte ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -ApUtilWriteControlByte ( - IN UINT8 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -ApUtilReadRemoteDataDword ( - IN UINT32 TargetApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -ApUtilWriteDataDword ( - IN UINT32 Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -ApUtilRunCodeOnSocketCore ( - IN UINT8 Socket, - IN UINT8 Core, - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -ApUtilWaitForCoreStatus ( - IN UINT32 TargetApicId, - IN AP_WAIT_FOR_STATUS *WaitParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -ApEntry ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams - ); - -UINT32 -ApUtilTaskOnExecutingCore ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ); - -VOID -ApUtilTransmitBuffer ( - IN UINT8 Socket, - IN UINT8 Core, - IN AP_DATA_TRANSFER *BufferInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -ApUtilReceiveBuffer ( - IN UINT8 Socket, - IN UINT8 Core, - IN OUT AP_DATA_TRANSFER *BufferInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetLocalApicIdForCore ( - IN UINT32 TargetSocket, - IN UINT32 TargetCore, - OUT UINT32 *LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -ApUtilRunCodeOnAllLocalCoresAtEarly ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ); - -VOID -RelinquishControlOfAllAPs ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetCsSelector ( - IN UINT16 *Selector, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SetIdtr ( - IN IDT_BASE_LIMIT *IdtInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetIdtr ( - IN IDT_BASE_LIMIT *IdtInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif /* _CPU_APIC_UTILITIES_H_ */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBist.c deleted file mode 100644 index 95c4d7f817..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBist.c +++ /dev/null @@ -1,172 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BIST Status Check Implementation. - * - * Implement CPU BIST Status checking - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuApicUtilities.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_CPUBIST_FILECODE - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -UINT32 -STATIC -GetBistResults ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - - /*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - /*---------------------------------------------------------------------------------------*/ - /** - * - * This function checks the status of BIST and places the error status in the event log - * if there are any errors - * - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS No BIST errors have been logged. - * @retval AGESA_ALERT BIST errors have been detected and added to the - * event log. - */ -AGESA_STATUS -CheckBistStatus ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Core; - UINT32 BscSocket; - UINT32 BscCoreNum; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - UINT32 Ignored; - UINT32 ReturnCode; - AGESA_STATUS IgnoredSts; - AGESA_STATUS AgesaStatus; - AP_TASK TaskPtr; - - // Make sure that Standard Header is valid - ASSERT (StdHeader != NULL); - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - AgesaStatus = AGESA_SUCCESS; - - // Get the BscSocket, BscCoreNum and NumberOfSockets in the system - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - // Setup TaskPtr struct to execute routine on APs - TaskPtr.FuncAddress.PfApTaskO = GetBistResults; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ReturnCode = ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader); - } else { - ReturnCode = TaskPtr.FuncAddress.PfApTaskO (StdHeader); - } - - // If BIST value is non-zero, add to BSP's event log - if (ReturnCode != 0) { - IDS_HDT_CONSOLE (CPU_TRACE, " BIST failure: socket %d core %d, status = 0x%x\n", Socket, Core, ReturnCode); - AgesaStatus = AGESA_ALERT; - PutEventLog (AGESA_ALERT, - CPU_EVENT_BIST_ERROR, - ReturnCode, Socket, Core, 0, StdHeader); - } - } - } - } - - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- -*/ - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Reads the lower 32 bits of the BIST register - * - * @param[in] StdHeader Header for library and services - * - * @retval Value of the BIST register -*/ -UINT32 -STATIC -GetBistResults ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 BistResults; - - // Read MSRC001_0060 BIST Results Register - LibAmdMsrRead (MSR_BIST, &BistResults, StdHeader); - - return (UINT32) (BistResults & 0xFFFFFFFF); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBrandId.c deleted file mode 100644 index 2d5f1df177..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBrandId.c +++ /dev/null @@ -1,313 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU BrandId related functions. - * - * Contains code that provides CPU BrandId information - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "OptionPstate.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuEarlyInit.h" -#include "cpuRegisters.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_CPUBRANDID_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -CONST CHAR8 ROMDATA strEngSample[] = "AMD Engineering Sample"; -CONST CHAR8 ROMDATA strTtkSample[] = "AMD Thermal Test Kit"; -CONST CHAR8 ROMDATA strUnknown[] = "AMD Processor Model Unknown"; - -CONST AMD_CPU_BRAND ROMDATA EngSample_Str = {0, 0, 0, SOCKET_IGNORE, strEngSample, sizeof (strEngSample)}; -CONST AMD_CPU_BRAND ROMDATA TtkSample_Str = {0, 1, 0, SOCKET_IGNORE, strTtkSample, sizeof (strTtkSample)}; -CONST AMD_CPU_BRAND ROMDATA Dflt_Str1 = {0, 0, 0, SOCKET_IGNORE, strUnknown, sizeof (strUnknown)}; -CONST AMD_CPU_BRAND ROMDATA Dflt_Str2 = {0, 0, 0, SOCKET_IGNORE, DR_NO_STRING, DR_NO_STRING}; - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -SetBrandIdRegistersAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Program BrandID registers (CPUIDNameStringPtr[0-5]) - * - * This function determines the appropriate brand string for the executing - * core, and programs the namestring MSRs. - * - * @param[in,out] StdHeader Config handle for library and services. - * - */ -VOID -SetBrandIdRegisters ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 SocketIndex; - UINT8 SuffixStatus; - UINT8 TableElements; - UINT8 TableEntryCount; - UINT8 TableEntryIndex; - CHAR8 TempChar; - CHAR8 *NameStringPtr; - CHAR8 *SuffixStringPtr; - CHAR8 *BrandStringPtr; - CHAR8 *TempNameCharPtr; - UINT32 MsrIndex; - UINT32 Quotient; - UINT32 Remainder; - UINT64 *MsrNameStringPtrPtr; - CPUID_DATA CpuId; - CPU_LOGICAL_ID CpuLogicalId; - CPU_BRAND_TABLE *SocketTableEntry; - CPU_BRAND_TABLE **SocketTableEntry1; - AMD_CPU_BRAND *SocketTablePtr; - AMD_CPU_BRAND_DATA Data; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - SuffixStatus = 0; - FamilySpecificServices = NULL; - SocketTablePtr = NULL; - SocketTableEntry = NULL; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - // Step1: Allocate 48 bytes from Heap space - AllocHeapParams.RequestedBufferSize = CPU_BRAND_ID_LENGTH; - AllocHeapParams.BufferHandle = AMD_BRAND_ID_BUFFER_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - // Clear NameBuffer - BrandStringPtr = (CHAR8 *) AllocHeapParams.BufferPtr; - LibAmdMemFill (BrandStringPtr, 0, CPU_BRAND_ID_LENGTH, StdHeader); - } else { - PutEventLog ( - AGESA_ERROR, - CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE, - 0, 0, 0, 0, StdHeader - ); - return; - } - - // Step2: Get brandid from model number and model string - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); - - // Step3: Figure out Socket/Page/Model/String1/String2/Core Number - Data.String2 = (UINT8) (CpuId.EBX_Reg & 0x0f); - Data.Model = (UINT8) ((CpuId.EBX_Reg >> 4) & 0x7f); - Data.String1 = (UINT8) ((CpuId.EBX_Reg >> 11) & 0x0f); - Data.Page = (UINT8) ((CpuId.EBX_Reg >> 15) & 0x01); - Data.Socket = (UINT8) ((CpuId.EBX_Reg >> 28) & 0x0f); - Data.Cores = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader); - - // Step4: If NN = 0, we have an engineering sample, no suffix; then jump to Step6 - if (Data.Model == 0) { - if (Data.Page == 0) { - SocketTablePtr = (AMD_CPU_BRAND *)&EngSample_Str; - } else { - SocketTablePtr = (AMD_CPU_BRAND *)&TtkSample_Str; - } - } else { - - // Model is not equal to zero, so decrement it - // For family 10 if PkgType[3:0] is greater than or equal to 2h and families >= 12h - GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader); - if ((((CpuLogicalId.Family & AMD_FAMILY_10) != 0) && (Data.Socket >= DR_SOCKET_S1G3)) || - ((CpuLogicalId.Family & AMD_FAMILY_GE_12) != 0)) { - Data.Model--; - } - - // Step5: Search for String1 (there can be only 1) - FamilySpecificServices->GetBrandString1 (FamilySpecificServices, (const VOID **) &SocketTableEntry, &TableEntryCount, StdHeader); - SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry; - for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount) - && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) { - if (*SocketTableEntry1 == NULL) { - break; - } - SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table; - TableElements = (*SocketTableEntry1)->NumberOfEntries; - for (SocketIndex = 0; (SocketIndex < TableElements) - && SuffixStatus == 0; SocketIndex++) { - if ((SocketTablePtr->Page == Data.Page) && - (SocketTablePtr->Index == Data.String1) && - (SocketTablePtr->Socket == Data.Socket) && - (SocketTablePtr->Cores == Data.Cores)) { - SuffixStatus = 1; - } else { - SocketTablePtr++; - } - } - } - if (SuffixStatus == 0) { - SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str1; // We did not find one, make 'Unknown' - } - } - - // Step6: Copy String into NameBuffer - // We now have data structure pointing to correct type in (*SocketTablePtr) - LibAmdMemCopy (BrandStringPtr, - (CHAR8 *)SocketTablePtr->Stringstart, - SocketTablePtr->Stringlength, - StdHeader); - - // Step7: Get suffix, determine addition to BRANDSPEED - if (SuffixStatus != 0) { - // Turn our value into a decimal string - // We have a value like 37d which we need to turn into '3' '7' - // Divide by 10, store remainder as an ASCII char on stack, repeat until Quotient is 0 - NameStringPtr = BrandStringPtr + SocketTablePtr->Stringlength - 1; - TempNameCharPtr = NameStringPtr; - Quotient = Data.Model; - do { - Remainder = Quotient % 10; - Quotient = Quotient / 10; - *TempNameCharPtr++ = (CHAR8) (Remainder + '0'); // Put suffix into our NameBuffer - } while (Quotient != 0); - if (Data.Model < 10) { - *TempNameCharPtr++ = '0'; - } - - // Step8: Reverse the string sequence and copy into NameBuffer - SuffixStringPtr = TempNameCharPtr--; - while (NameStringPtr < TempNameCharPtr) { - TempChar = *NameStringPtr; - *NameStringPtr = *TempNameCharPtr; - *TempNameCharPtr = TempChar; - NameStringPtr++; - TempNameCharPtr--; - } - - // Step9: Search for String2 - SuffixStatus = 0; - FamilySpecificServices->GetBrandString2 (FamilySpecificServices, (const VOID **) &SocketTableEntry, &TableEntryCount, StdHeader); - SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry; - for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount) - && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) { - if (*SocketTableEntry1 == NULL) { - break; - } - SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table; - TableElements = (*SocketTableEntry1)->NumberOfEntries; - for (SocketIndex = 0; (SocketIndex < TableElements) - && SuffixStatus == 0; SocketIndex++) { - if ((SocketTablePtr->Page == Data.Page) && - (SocketTablePtr->Index == Data.String2) && - (SocketTablePtr->Socket == Data.Socket) && - (SocketTablePtr->Cores == Data.Cores)) { - SuffixStatus = 1; - } else { - SocketTablePtr++; - } - } - } - if (SuffixStatus == 0) { - SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str2; - } - - // Step10: Copy String2 into our NameBuffer - if (SocketTablePtr->Stringlength != 0) { - LibAmdMemCopy (SuffixStringPtr, - (CHAR8 *)SocketTablePtr->Stringstart, - SocketTablePtr->Stringlength, - StdHeader); - } - } - - // Step11: Put values into name MSRs, Always write the full 48 bytes - MsrNameStringPtrPtr = (UINT64 *) BrandStringPtr; - for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) { - LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader); - MsrNameStringPtrPtr++; - } - HeapDeallocateBuffer (AMD_BRAND_ID_BUFFER_HANDLE, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Program BrandID registers (CPUIDNameStringPtr[0-5]) - * - * This function acts as a wrapper for calling the SetBrandIdRegisters - * routine at AmdInitEarly. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -SetBrandIdRegistersAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_TESTPOINT (TpProcCpuSetBrandID, StdHeader); - SetBrandIdRegisters (StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.c deleted file mode 100644 index 60e460ff7e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.c +++ /dev/null @@ -1,411 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Reset API, and related functions. - * - * Contains code that initialized the CPU after early reset. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "Table.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "Topology.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_CPUEARLYINIT_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -GetPerformEarlyFlag ( - IN OUT UINT32 *PerformEarlyFlag, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -McaInitializationAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that will be invoked by AmdCpuEarly to initialize the input - * structure for the Cpu Init @ Early routine. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] PlatformConfig Config handle for platform specific information - * @param[in,out] CpuEarlyParamsPtr Service Interface structure to initialize. - * - * @retval AGESA_SUCCESS Always Succeeds - */ -VOID -AmdCpuEarlyInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ) -{ - ASSERT (CpuEarlyParamsPtr != NULL); - - CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate; - CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig; -} -/*---------------------------------------------------------------------------------------*/ -/** - * Performs CPU related initialization at the early entry point - * - * This function performs a large list of initialization items. These items - * include: - * - * -1 local APIC initialization - * -2 MSR table initialization - * -3 PCI table initialization - * -4 HT Phy PCI table initialization - * -5 microcode patch loading - * -6 namestring determination/programming - * -7 AP initialization - * -8 power management initialization - * -9 core leveling - * - * This routine must be run by all cores in the system. Please note that - * all APs that enter will never exit. - * - * @param[in] StdHeader Config handle for library and services - * @param[in] PlatformConfig Config handle for platform specific information - * - * @retval AGESA_SUCCESS - * - */ -AGESA_STATUS -AmdCpuEarly ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ) -{ - UINT8 WaitStatus; - UINT8 i; - UINT8 StartCore; - UINT8 EndCore; - UINT32 NodeNum; - UINT32 PrimaryCore; - UINT32 SocketNum; - UINT32 ModuleNum; - UINT32 HighCore; - UINT32 ApHeapIndex; - UINT32 CurrentPerformEarlyFlag; - UINT32 TargetApicId; - AP_WAIT_FOR_STATUS WaitForStatus; - AGESA_STATUS Status; - AGESA_STATUS CalledStatus; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - AMD_CPU_EARLY_PARAMS CpuEarlyParams; - S_PERFORM_EARLY_INIT_ON_CORE *EarlyTableOnCore; - - Status = AGESA_SUCCESS; - CalledStatus = AGESA_SUCCESS; - - AmdCpuEarlyInitializer (StdHeader, PlatformConfig, &CpuEarlyParams); - - IDS_OPTION_HOOK (IDS_CPU_Early_Override, &CpuEarlyParams, StdHeader); - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - EarlyTableOnCore = NULL; - FamilySpecificServices->GetEarlyInitOnCoreTable (FamilySpecificServices, (const S_PERFORM_EARLY_INIT_ON_CORE **)&EarlyTableOnCore, &CpuEarlyParams, StdHeader); - if (EarlyTableOnCore != NULL) { - GetPerformEarlyFlag (&CurrentPerformEarlyFlag, StdHeader); - for (i = 0; EarlyTableOnCore[i].PerformEarlyInitOnCore != NULL; i++) { - if ((EarlyTableOnCore[i].PerformEarlyInitFlag & CurrentPerformEarlyFlag) != 0) { - IDS_HDT_CONSOLE (CPU_TRACE, " Perform core init step %d\n", i); - EarlyTableOnCore[i].PerformEarlyInitOnCore (FamilySpecificServices, &CpuEarlyParams, StdHeader); - } - } - } - - // B S P C O D E T O I N I T I A L I Z E A Ps - // ------------------------------------------------------- - // ------------------------------------------------------- - // IMPORTANT: Here we determine if we are BSP or AP - if (IsBsp (StdHeader, &CalledStatus)) { - - // Even though the bsc does not need to send itself a heap index, this sequence performs other important initialization. - // Use '0' as a dummy heap index value. - GetSocketModuleOfNode (0, &SocketNum, &ModuleNum, StdHeader); - GetCpuServicesOfSocket (SocketNum, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, 0, StdHeader); - FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, StdHeader); - - // Clear BSP's Status Byte - ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); - - NodeNum = 0; - ApHeapIndex = 1; - while (NodeNum < MAX_NODES && - GetSocketModuleOfNode (NodeNum, &SocketNum, &ModuleNum, StdHeader)) { - GetCpuServicesOfSocket (SocketNum, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - GetGivenModuleCoreRange (SocketNum, ModuleNum, &PrimaryCore, &HighCore, StdHeader); - if (NodeNum == 0) { - StartCore = (UINT8) PrimaryCore + 1; - } else { - StartCore = (UINT8) PrimaryCore; - } - - EndCore = (UINT8) HighCore; - for (i = StartCore; i <= EndCore; i++) { - FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, ApHeapIndex, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Launch socket %d core %d\n", SocketNum, i); - if (FamilySpecificServices->LaunchApCore (FamilySpecificServices, SocketNum, ModuleNum, i, PrimaryCore, StdHeader)) { - IDS_HDT_CONSOLE (CPU_TRACE, " Waiting for socket %d core %d\n", SocketNum, i); - GetLocalApicIdForCore (SocketNum, i, &TargetApicId, StdHeader); - WaitStatus = CORE_IDLE; - WaitForStatus.Status = &WaitStatus; - WaitForStatus.NumberOfElements = 1; - WaitForStatus.RetryCount = WAIT_INFINITELY; - WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; - ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); - ApHeapIndex++; - } - } - NodeNum++; - } - - // B S P P h a s e - 1 E N D - - IDS_OPTION_HOOK (IDS_BEFORE_PM_INIT, &CpuEarlyParams, StdHeader); - - AGESA_TESTPOINT (TpProcCpuBeforePMFeatureInit, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features before early power mgmt init\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_BEFORE_PM_INIT, PlatformConfig, StdHeader); - if (CalledStatus > Status) { - Status = CalledStatus; - } - - AGESA_TESTPOINT (TpProcCpuPowerMgmtInit, StdHeader); - CalledStatus = PmInitializationAtEarly (&CpuEarlyParams, StdHeader); - if (CalledStatus > Status) { - Status = CalledStatus; - } - - AGESA_TESTPOINT (TpProcCpuEarlyFeatureInit, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after early power mgmt init\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_PM_INIT, PlatformConfig, StdHeader); - - IDS_OPTION_HOOK (IDS_BEFORE_AP_EARLY_HALT, &CpuEarlyParams, StdHeader); - - // Sleep all APs - IDS_HDT_CONSOLE (CPU_TRACE, " Halting all APs\n"); - ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader); - } // if (amdIsBsp()) - END - else { - ApEntry (StdHeader, &CpuEarlyParams); - } - - if (CalledStatus > Status) { - Status = CalledStatus; - } - - return (Status); -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Initialize Machine Check Architecture registers - * - * This function initializes the MCA MSRs. On cold reset, these registers - * have an invalid data that must be cleared on all cores. - * - * @param[in] StdHeader Config handle for library and services - * - *--------------------------------------------------------------------------------------- - */ -VOID -McaInitialization ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 TempVar16_a; - UINT32 MsrAddress; - UINT64 MsrData; - CPUID_DATA CpuIdDataStruct; - - if (!(IsWarmReset (StdHeader))) { - // Run CPUID to verify that the processor supports MCE and MCA - // i.e. edx[7], and edx[14] - // CPUID_MODEL = 1 - LibAmdCpuidRead (1, &CpuIdDataStruct, StdHeader); - if ((CpuIdDataStruct.EDX_Reg & 0x4080) != 0) { - // Check to see if the MCG_CTL_P bit is set - // MCG = Global Machine Check Exception Reporting Control Register - LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader); - if ((MsrData & MCG_CTL_P) != 0) { - TempVar16_a = (UINT16) ((MsrData & 0x000000FF) << 2); - TempVar16_a += MSR_MC0_CTL; - - // Initialize the data - MsrData = 0; - for (MsrAddress = MSR_MC0_CTL; MsrAddress < TempVar16_a; MsrAddress++) { - LibAmdMsrWrite (MsrAddress, &MsrData, StdHeader); - } - } - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Initialize Machine Check Architecture registers - * - * This function acts as a wrapper for calling the McaInitialization - * routine at AmdInitEarly. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -McaInitializationAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - McaInitialization (StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Runs the given task on all cores (including self) on the socket of the executing - * core 0. - * - * This function is used to invoke all APs on the socket of the executing core 0 to - * run a specified AGESA procedure. - * - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Config handle for library and services - * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization - * - */ -VOID -ApUtilRunCodeOnAllLocalCoresAtEarly ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ) -{ - UINT32 Core; - UINT32 Socket; - UINT32 IgnoredModule; - UINT32 IgnoredCore; - UINT32 ActiveCores; - AGESA_STATUS IgnoredSts; - - IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts); - GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader); - - for (Core = 1; Core < (UINT8) ActiveCores; ++Core) { - ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, TaskPtr, StdHeader); - } - ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get current condition, such as warm/cold reset, to determine if related function - * need to be performed at early stage - * - * @param[in, out] PerformEarlyFlag Perform early flag. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -GetPerformEarlyFlag ( - IN OUT UINT32 *PerformEarlyFlag, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *PerformEarlyFlag = 0; - if (IsWarmReset (StdHeader)) { - *PerformEarlyFlag |= PERFORM_EARLY_WARM_RESET; - } else { - *PerformEarlyFlag |= PERFORM_EARLY_COLD_BOOT; - } - return; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.h deleted file mode 100644 index 9be6ff6a54..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEarlyInit.h +++ /dev/null @@ -1,302 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Reset API, and related functions and structures. - * - * Contains code that initialized the CPU after early reset. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_EARLY_INIT_H_ -#define _CPU_EARLY_INIT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ -AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES); - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -//---------------------------------------------------------------------------- -// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported -#define LOW_NODE_DEVICEID 24 -#define NB_CAPABILITIES 0xE8 //Function 3 Registers -//---------------------------------------------------------------------------- -// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/* All lengths are in bytes */ -#define MICROCODE_TRIADE_SIZE 28 -#define MICROCODE_HEADER_LENGTH 64 - -/** - * @page ucodeflag Microcode Patches Signature Guide - * - * We mark patches in the ROM with a signature so that they can be easily found - * - * @anchor Microcode Patch Signature - * @li @e Microcode Patch Signature @n - * Microcode patches are marked by adding a signature before patches in the ROM image to - * help identify where they are located. - * There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size. - * The other is '$UCODE4K', it indicates there's a following patch with 4K size. - * If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format. - * - * - */ -/// Microcode patch flag for replacement -typedef struct { - IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode -} MICROCODE_PATCHES_FLAG; - - -/* Offsets in UCODE PATCH Header */ -/* Note: Header is 64 bytes */ -#define DATE_CODE_OFFSET 0 // 4 bytes -#define PATCH_ID 4 // 4 bytes -#define MICROCODE_PATH_DATA_ID 8 // 2 bytes -#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte -#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes -#define CHIPSET_1_DEVICE_ID 16 // 4 bytes -#define CHIPSET_2_DEVICE_ID 20 // 4 bytes -#define PROCESSOR_REV_ID 24 // 2 bytes -#define CHIPSET_1_REV_ID 26 // 1 byte -#define CHIPSET_2_REV_ID 27 // 1 byte - -#define MICROCODE_PATCH_2K_SIZE 2048 -#define MICROCODE_PATCH_4K_SIZE 4096 -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -//---------------------------------------------------------------------------- -// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// A structure representing BrandId[15:0] from -/// CPUID Fn8000_0001_EBX -typedef struct { - UINT8 String1:4; ///< An index to a string value used to create the name string - UINT8 String2:4; ///< An index to a string value used to create the name string - UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values - UINT8 Model:7; ///< A field used to create the model number in the name string - UINT8 Socket:4; ///< Specifies the package type - UINT8 Cores:4; ///< Identifies how many physical cores are present -} AMD_CPU_BRAND_DATA; - -/// A structure containing string1 and string2 values -/// as well as information pertaining to their usage -typedef struct { - IN UINT8 Cores; ///< Appropriate number of physical cores - IN UINT8 Page; ///< This string's page number - IN UINT8 Index; ///< String index - IN UINT8 Socket; ///< Package type information - IN CONST CHAR8 *Stringstart; ///< The literal string - IN UINT8 Stringlength; ///< Number of characters in the string -} AMD_CPU_BRAND; - -/// An entire CPU brand table. -typedef struct { - UINT8 NumberOfEntries; ///< The number of entries in the table. - CONST AMD_CPU_BRAND *Table; ///< The table entries. -} CPU_BRAND_TABLE; - -//---------------------------------------------------------------------------- -// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// Microcode patch field definitions -typedef struct { - UINT32 DateCode; ///< Date of patch creation - UINT32 PatchID; ///< Patch level - UINT16 MicrocodePatchDataID; ///< Internal use only - UINT8 MicrocodePatchDataLength; ///< Internal use only - UINT8 InitializationFlag; ///< Internal use only - UINT32 MicrocodePatchDataChecksum; ///< Doubleword sum of data block - UINT32 Chipset1DeviceID; ///< Device ID of 1st HT device to match - UINT32 Chipset2DeviceID; ///< Device ID of 2nd HT device to match - UINT16 ProcessorRevisionID; ///< Equivalent ID - UINT8 Chipset1RevisionID; ///< Revision level of 1st HT device to match - UINT8 Chipset2RevisionID; ///< Revision level of 2nd HT device to match - UINT8 BiosApiRevision; ///< BIOS INT 15 API revision required - UINT8 Reserved1[3]; ///< Reserved - UINT32 MatchRegister0; ///< Internal use only - UINT32 MatchRegister1; ///< Internal use only - UINT32 MatchRegister2; ///< Internal use only - UINT32 MatchRegister3; ///< Internal use only - UINT32 MatchRegister4; ///< Internal use only - UINT32 MatchRegister5; ///< Internal use only - UINT32 MatchRegister6; ///< Internal use only - UINT32 MatchRegister7; ///< Internal use only - UINT8 PatchDataBlock[896]; ///< Raw patch data - UINT8 Reserved2[896]; ///< Reserved - UINT8 X86CodePresent; ///< Boolean to determine if executable code exists - UINT8 X86CodeEntry[191]; ///< Code to execute if X86CodePresent != 0 -} MICROCODE_PATCH; - -/// Two kilobyte array containing the raw -/// microcode patch binary data -typedef struct { - IN UINT8 MicrocodePatches[MICROCODE_PATCH_2K_SIZE]; ///< 2k UINT8 elements -} MICROCODE_PATCHES; - -/// Four kilobyte array containing the raw -/// microcode patch binary data -typedef struct { - IN UINT8 MicrocodePatches[MICROCODE_PATCH_4K_SIZE]; ///< 4k UINT8 elements -} MICROCODE_PATCHES_4K; - -/** - * Set down core register - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Socket Socket ID. - * @param[in] Module Module ID in socket. - * @param[in] LeveledCores Number of core. - * @param[in] CoreLevelMode Core level mode. - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE Down Core register is updated. - * @retval FALSE Down Core register is not updated. - */ -typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) ( - IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, - IN UINT32 *Socket, - IN UINT32 *Module, - IN UINT32 *LeveledCores, - IN CORE_LEVELING_TYPE CoreLevelMode, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER; - -/** - * Provide the interface to the Core Leveling Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above - UINT16 Revision; ///< Interface version - // Public Methods. - PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register. -}; - -//---------------------------------------------------------------------------- -// CPU PERFORM EARLY INIT ON CORE -// -//---------------------------------------------------------------------------- -/// Flag definition. -#define PERFORM_EARLY_WARM_RESET 0x1 // bit 0 --- the related function needs to be run if it's warm reset -#define PERFORM_EARLY_COLD_BOOT 0x2 // bit 1 --- the related function needs to be run if it's cold boot - -#define PERFORM_EARLY_ANY_CONDITION 0xFFFFFFFF // the related function always needs to be run -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -// These are P U B L I C functions, used by IBVs -AGESA_STATUS -AmdCpuEarly ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ); - -// These are P U B L I C functions, used by AGESA -VOID -SetBrandIdRegisters ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PmInitializationAtEarly ( - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -LoadMicrocodePatch ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetPatchEquivalentId ( - IN OUT UINT16 *ProcessorEquivalentId, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -ValidateMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN UINT16 ProcessorEquivalentId, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetMicrocodeVersion ( - OUT UINT32 *pMicrocodeVersion, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -AmdCpuEarlyInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ); - -VOID -McaInitialization ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_EARLY_INIT_H_ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEnvInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEnvInit.h deleted file mode 100644 index e19a75600d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEnvInit.h +++ /dev/null @@ -1,72 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Env Init API functions Prototypes. - * - * Contains code for doing any Env CPU initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_ENV_INIT_H_ -#define _CPU_ENV_INIT_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ -// HobTransfer -AGESA_STATUS -CopyHeapToMainRamAtPost ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_ENV_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c deleted file mode 100644 index 06346576b7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c +++ /dev/null @@ -1,409 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Event (Error) Log APIs, and related functions. - * - * Contains code that records and returns the events and errors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_CPUEVENTLOG_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -#define TOTAL_EVENT_LOG_BUFFERS 16 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/** - * A wrapper for each Event Log entry. - */ -typedef struct { - UINT16 Count; ///< Entry number - AGESA_EVENT AgesaEvent; ///< The entry itself. -} AGESA_EVENT_STRUCT; - -/** - * The Event Log. - */ -typedef struct { - UINT16 ReadWriteFlag; ///< Read Write flag. - UINT16 Count; ///< The total number of active entries. - UINT16 ReadRecordPtr; ///< The next entry to read. - UINT16 WriteRecordPtr; ///< The next entry to write. - AGESA_EVENT_STRUCT AgesaEventStruct[TOTAL_EVENT_LOG_BUFFERS]; ///< The entries. -} AGESA_STRUCT_BUFFER; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -GetEventLogHeapPointer ( - OUT AGESA_STRUCT_BUFFER **EventLog, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * External AGESA interface to read an Event from the Event Log. - * - * This is the implementation of the external AGESA interface entry, as a thin wrapper - * around the internal log services. - * - * @param[in] Event The event class, id, and any associated data. - * - * @retval AGESA_SUCCESS Always Succeeds. - */ -AGESA_STATUS -AmdReadEventLog ( - IN EVENT_PARAMS *Event - ) -{ - AGESA_EVENT LogEvent; - AGESA_STATUS Status; - - AGESA_TESTPOINT (TpIfAmdReadEventLogEntry, &Event->StdHeader); - - ASSERT (Event != NULL); - Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader); - Status = GetEventLog (&LogEvent, &Event->StdHeader); - if (Status != AGESA_SUCCESS) - return Status; - - Event->EventClass = LogEvent.EventClass; - Event->EventInfo = LogEvent.EventInfo; - Event->DataParam1 = LogEvent.DataParam1; - Event->DataParam2 = LogEvent.DataParam2; - Event->DataParam3 = LogEvent.DataParam3; - Event->DataParam4 = LogEvent.DataParam4; - - AGESA_TESTPOINT (TpIfAmdReadEventLogExit, &Event->StdHeader); - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function prepares the Event Log for use. - * - * Allocate the memory for an event log on the heap. Set the read pointer, write pointer, - * and count to reflect the log is empty. - * - * @param[in] StdHeader Our configuration, for passing to services. - * - * @retval AGESA_SUCCESS The event log is initialized. - * @retval AGESA_ERROR Allocate Heap Buffer returned an error. - * - */ -AGESA_STATUS -EventLogInitialization ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - ALLOCATE_HEAP_PARAMS AllocateHeapParams; - AGESA_STRUCT_BUFFER *AgesaEventAlloc; - AGESA_STATUS Status; - - AllocateHeapParams.BufferHandle = EVENT_LOG_BUFFER_HANDLE; - AllocateHeapParams.RequestedBufferSize = sizeof (AGESA_STRUCT_BUFFER); - AllocateHeapParams.Persist = HEAP_SYSTEM_MEM; - Status = HeapAllocateBuffer (&AllocateHeapParams, StdHeader); - AgesaEventAlloc = (AGESA_STRUCT_BUFFER *) AllocateHeapParams.BufferPtr; - AgesaEventAlloc->Count = 0; - AgesaEventAlloc->ReadRecordPtr = 0; - AgesaEventAlloc->WriteRecordPtr = 0; - AgesaEventAlloc->ReadWriteFlag = 1; - - return Status; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function logs AGESA events into the event log. - * - * It will put the information in a circular buffer consisting of 16 such log - * entries. If the buffer gets full, then the next event log entry will be written - * over the oldest event log entry. - * - * @param[in] EventClass The severity of the event, its associated AGESA_STATUS. - * @param[in] EventInfo Uniquely identifies the event. - * @param[in] DataParam1 Event specific additional data - * @param[in] DataParam2 Event specific additional data - * @param[in] DataParam3 Event specific additional data - * @param[in] DataParam4 Event specific additional data - * @param[in] StdHeader Header for library and services - * - */ -VOID -PutEventLog ( - IN AGESA_STATUS EventClass, - IN UINT32 EventInfo, - IN UINT32 DataParam1, - IN UINT32 DataParam2, - IN UINT32 DataParam3, - IN UINT32 DataParam4, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 Index; - AGESA_STRUCT_BUFFER *AgesaEventAlloc; - - IDS_HDT_CONSOLE (MAIN_FLOW, "\n * %s Event: %08x Data: %x, %x, %x, %x\n\n", - (EventClass == AGESA_FATAL) ? "FATAL" : - (EventClass == AGESA_CRITICAL) ? "CRITICAL" : - (EventClass == AGESA_ERROR) ? "ERROR" : - (EventClass == AGESA_WARNING) ? "WARNING" : - (EventClass == AGESA_ALERT) ? "ALERT" : - (EventClass == AGESA_BOUNDS_CHK) ? "BOUNDS_CHK" : - (EventClass == AGESA_UNSUPPORTED) ? "UNSUPPORTED" : - "SUCCESS", EventInfo, DataParam1, DataParam2, DataParam3, DataParam4); - - if (EventClass < AGESA_STATUS_LOG_LEVEL) - return; - - AgesaEventAlloc = NULL; - GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); - ASSERT (AgesaEventAlloc != NULL); - if (AgesaEventAlloc == NULL) - return; - - Index = AgesaEventAlloc->WriteRecordPtr; - - // Add the new event log data into a circular buffer - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass = EventClass; - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo = EventInfo; - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1 = DataParam1; - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2 = DataParam2; - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3 = DataParam3; - AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4 = DataParam4; - - if ((AgesaEventAlloc->WriteRecordPtr == AgesaEventAlloc->ReadRecordPtr) && - (AgesaEventAlloc->ReadWriteFlag == 0)) { - AgesaEventAlloc->WriteRecordPtr += 1; - AgesaEventAlloc->ReadRecordPtr += 1; - if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) { - AgesaEventAlloc->WriteRecordPtr = 0; - AgesaEventAlloc->ReadRecordPtr = 0; - } - } else { - AgesaEventAlloc->WriteRecordPtr += 1; - if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) { - AgesaEventAlloc->WriteRecordPtr = 0; - } - AgesaEventAlloc->ReadWriteFlag = 0; - } - AgesaEventAlloc->Count = AgesaEventAlloc->Count + 1; - - if (AgesaEventAlloc->Count <= TOTAL_EVENT_LOG_BUFFERS) { - AgesaEventAlloc->AgesaEventStruct[Index].Count = Index; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function gets event logs from the circular buffer. - * - * It will read the oldest entry from the circular buffer and place that information to the structure - * pointed to by the parameter. The read pointers will be incremented to remove the entry from buffer - * so that a subsequent call will return the next entry from the buffer. If the buffer is empty the - * returned log event will have EventInfo zero, which is not a valid event id. - * - * @param[out] EventRecord The next log event. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -GetEventLog ( - OUT AGESA_EVENT *EventRecord, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 Index; - AGESA_STRUCT_BUFFER *AgesaEventAlloc; - - AgesaEventAlloc = NULL; - - GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); - ASSERT (AgesaEventAlloc != NULL); - if (AgesaEventAlloc == NULL) - return AGESA_BOUNDS_CHK; - - if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && - (AgesaEventAlloc->ReadWriteFlag == 1)) { - // EventInfo == zero, means no more data. - LibAmdMemFill (EventRecord, 0, sizeof (AGESA_EVENT), StdHeader); - } else { - Index = AgesaEventAlloc->ReadRecordPtr; - EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass; - EventRecord->EventInfo = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo; - EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1; - EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2; - EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3; - EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4; - if (AgesaEventAlloc->ReadRecordPtr == (TOTAL_EVENT_LOG_BUFFERS - 1)) { - AgesaEventAlloc->ReadRecordPtr = 0; - } else { - AgesaEventAlloc->ReadRecordPtr = AgesaEventAlloc->ReadRecordPtr + 1; - } - if (AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) { - AgesaEventAlloc->ReadWriteFlag = 1; - } - } - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function gets event logs from the circular buffer without flushing the entry. - * - * It will read the desired entry from the circular buffer and place that information to the structure - * pointed to by the parameter. The read pointers will not be incremented to remove the entry from the - * buffer. If the buffer is empty, or the desired entry does not exist, FALSE will be returned. - * - * @param[out] EventRecord The next log event. - * @param[in] Index Zero-based unread entry index - * @param[in] StdHeader Header for library and services - * - * @retval TRUE Entry exists - * @retval FALSE Entry does not exist - * - */ -BOOLEAN -PeekEventLog ( - OUT AGESA_EVENT *EventRecord, - IN UINT16 Index, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 ActualIndex; - UINT16 UnreadEntries; - AGESA_STRUCT_BUFFER *AgesaEventAlloc; - - AgesaEventAlloc = NULL; - - GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); - ASSERT (AgesaEventAlloc != NULL); - if (AgesaEventAlloc == NULL) - return FALSE; - - if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && - (AgesaEventAlloc->ReadWriteFlag == 1)) { - // EventInfo == zero, means no more data. - return FALSE; - } - if (AgesaEventAlloc->ReadRecordPtr < AgesaEventAlloc->WriteRecordPtr) { - UnreadEntries = AgesaEventAlloc->WriteRecordPtr - AgesaEventAlloc->ReadRecordPtr; - } else { - UnreadEntries = TOTAL_EVENT_LOG_BUFFERS - (AgesaEventAlloc->ReadRecordPtr - AgesaEventAlloc->WriteRecordPtr); - } - if (Index >= UnreadEntries) { - return FALSE; - } - ActualIndex = Index + AgesaEventAlloc->ReadRecordPtr; - if (ActualIndex >= TOTAL_EVENT_LOG_BUFFERS) { - ActualIndex -= TOTAL_EVENT_LOG_BUFFERS; - } - - EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventClass; - EventRecord->EventInfo = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventInfo; - EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam1; - EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam2; - EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam3; - EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam4; - - return TRUE; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This function gets the Event Log pointer. - * - * It will locate the Event Log on the heap using the heap locate service. If the Event - * Log is not located, NULL is returned. - * - * @param[out] EventLog Pointer to the Event Log, or NULL. - * @param[in] StdHeader Our Configuration, for passing to services. - * - */ -VOID -STATIC -GetEventLogHeapPointer ( - OUT AGESA_STRUCT_BUFFER **EventLog, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LOCATE_HEAP_PTR LocateHeapStruct; - - LocateHeapStruct.BufferHandle = EVENT_LOG_BUFFER_HANDLE; - LocateHeapStruct.BufferPtr = NULL; - if ((HeapLocateBuffer (&LocateHeapStruct, StdHeader)) == AGESA_SUCCESS) { - *EventLog = (AGESA_STRUCT_BUFFER *)LocateHeapStruct.BufferPtr; - } else { - *EventLog = NULL; - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.c deleted file mode 100644 index 8c9e969b53..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.c +++ /dev/null @@ -1,484 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Family Translation functions. - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Interface - * @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "CommonReturns.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_CPUFAMILYTRANSLATION_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -CONST CPU_SPECIFIC_SERVICES ROMDATA cpuNullServices = -{ - 0, - (PF_CPU_DISABLE_PSTATE) CommonReturnAgesaSuccess, - (PF_CPU_TRANSITION_PSTATE) CommonReturnAgesaSuccess, - (PF_CPU_GET_IDD_MAX) CommonReturnFalse, - (PF_CPU_GET_TSC_RATE) CommonReturnAgesaSuccess, - (PF_CPU_GET_NB_FREQ) CommonReturnAgesaSuccess, - (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonReturnAgesaSuccess, - (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse, - (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnAgesaSuccess, - (PF_CPU_GET_NB_IDD_MAX) CommonReturnFalse, - (PF_CPU_AP_INITIAL_LAUNCH) CommonReturnFalse, - (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonReturnZero8, - (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonReturnAgesaSuccess, - (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid, - (PF_CPU_GET_AP_CORE_NUMBER) CommonReturnZero32, - (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid, - (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonReturnAgesaSuccess, - (PF_CPU_SAVE_FEATURES) CommonReturnAgesaSuccess, - (PF_CPU_WRITE_FEATURES) CommonReturnAgesaSuccess, - (PF_CPU_SET_WARM_RESET_FLAG) CommonReturnAgesaSuccess, - (PF_CPU_GET_WARM_RESET_FLAG) CommonReturnAgesaSuccess, - GetEmptyArray, - GetEmptyArray, - GetEmptyArray, - GetEmptyArray, - GetEmptyArray, - GetEmptyArray, - GetEmptyArray, - (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess, - (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse, - (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, - (PF_SET_HT_PHY_REGISTER) CommonVoid, - (PF_GET_NEXT_HT_LINK_FEATURES) CommonVoid, - NULL, - NULL, - NULL, - NULL, - InitCacheDisabled, - (PF_GET_EARLY_INIT_TABLE) CommonVoid -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -GetCpuServices ( - IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, - IN UINT64 *MatchData, - OUT CONST VOID **CpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable; -extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable; - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Returns the logical ID of the desired processor. This will be obtained by - * reading the CPUID and converting it into a "logical ID" which is not package - * dependent. - * - * @param[in] Socket Socket - * @param[out] LogicalId The Processor's Logical ID - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetLogicalIdOfSocket ( - IN UINT32 Socket, - OUT CPU_LOGICAL_ID *LogicalId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RawCpuid; - PCI_ADDR PciAddress; - AGESA_STATUS AssumedSuccess; - - RawCpuid = 0; - - if (GetPciAddress (StdHeader, (UINT8)Socket, 0, &PciAddress, &AssumedSuccess)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPUID_FMR; - LibAmdPciRead (AccessWidth32, PciAddress, &RawCpuid, StdHeader); - GetLogicalIdFromCpuid (RawCpuid, LogicalId, StdHeader); - } else { - LogicalId->Family = 0; - LogicalId->Revision = 0; - // Logical ID was not found. - IDS_ERROR_TRAP; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Returns the logical ID of the executing core. This will be obtained by reading - * the CPUID and converting it into a "logical ID" which is not package dependent. - * - * @param[out] LogicalId The Processor's Logical ID - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetLogicalIdOfCurrentCore ( - OUT CPU_LOGICAL_ID *LogicalId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuidDataStruct; - - LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader); - GetLogicalIdFromCpuid (CpuidDataStruct.EAX_Reg, LogicalId, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Returns the logical ID of a processor with the given CPUID value. This - * will be obtained by converting it into a "logical ID" which is not package - * dependent. - * - * @param[in] RawCpuid The unprocessed CPUID value to be translated - * @param[out] LogicalId The Processor's Logical ID - * @param[in] StdHeader Handle of Header for calling lib functions and services - * - */ -VOID -GetLogicalIdFromCpuid ( - IN UINT32 RawCpuid, - OUT CPU_LOGICAL_ID *LogicalId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 k; - UINT8 NumberOfFamiliesSupported; - UINT8 NumberOfLogicalSubFamilies; - UINT8 LogicalIdEntries; - UINT32 j; - UINT32 RawFamily; - UINT32 CpuModelAndExtendedModel; - UINT64 LogicalFamily; - BOOLEAN IdNotFound; - BOOLEAN FamilyNotFound; - CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY *SubFamilyIdPtr; - CPU_LOGICAL_ID_XLAT *CpuLogicalIdAndRevPtr; - CONST CPU_LOGICAL_ID_FAMILY_XLAT *ImageSupportedId; - - IdNotFound = TRUE; - FamilyNotFound = TRUE; - CpuLogicalIdAndRevPtr = NULL; - ImageSupportedId = CpuSupportedFamilyIdTable.FamilyIdTable; - NumberOfFamiliesSupported = CpuSupportedFamilyIdTable.Elements; - - RawFamily = ((RawCpuid & 0xF00) >> 8) + ((RawCpuid & 0xFF00000) >> 20); - RawCpuid &= (UINT32) CPU_FMS_MASK; - CpuModelAndExtendedModel = (UINT16) ((RawCpuid >> 8) | RawCpuid); - - LogicalId->Family = 0; - LogicalId->Revision = 0; - - for (i = 0; i < NumberOfFamiliesSupported && FamilyNotFound; i++) { - if (ImageSupportedId[i].Family == RawFamily) { - FamilyNotFound = FALSE; - LogicalId->Family = ImageSupportedId[i].UnknownRevision.Family; - LogicalId->Revision = ImageSupportedId[i].UnknownRevision.Revision; - - NumberOfLogicalSubFamilies = ImageSupportedId[i].Elements; - SubFamilyIdPtr = ImageSupportedId[i].SubFamilyIdTable; - for (j = 0; j < NumberOfLogicalSubFamilies && IdNotFound; j++) { - SubFamilyIdPtr[j] ((CONST CPU_LOGICAL_ID_XLAT **)&CpuLogicalIdAndRevPtr, &LogicalIdEntries, &LogicalFamily, StdHeader); - ASSERT (CpuLogicalIdAndRevPtr != NULL); - for (k = 0; k < LogicalIdEntries; k++) { - if (CpuLogicalIdAndRevPtr[k].RawId == CpuModelAndExtendedModel) { - IdNotFound = FALSE; - LogicalId->Family = LogicalFamily; - LogicalId->Revision = CpuLogicalIdAndRevPtr[k].LogicalId; - break; - } - } - } - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the desired processor's family specific services structure. - * - * @param[in] Socket The Processor in this Socket. - * @param[out] FunctionTable The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetCpuServicesOfSocket ( - IN UINT32 Socket, - OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GetFeatureServicesOfSocket (&CpuSupportedFamiliesTable, - Socket, - (CONST VOID **) FunctionTable, - StdHeader); - if (*FunctionTable == NULL) { - *FunctionTable = &cpuNullServices; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the desired processor's family specific services structure. - * - * @param[in] FamilyTable The table to search in. - * @param[in] Socket The Processor in this Socket. - * @param[out] CpuServices The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetFeatureServicesOfSocket ( - IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, - IN UINT32 Socket, - OUT CONST VOID **CpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID CpuFamilyRevision; - - GetLogicalIdOfSocket (Socket, &CpuFamilyRevision, StdHeader); - GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the executing core's family specific services structure. - * - * @param[out] FunctionTable The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetCpuServicesOfCurrentCore ( - OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GetFeatureServicesOfCurrentCore (&CpuSupportedFamiliesTable, - (CONST VOID **) FunctionTable, - StdHeader); - if (*FunctionTable == NULL) { - *FunctionTable = &cpuNullServices; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the family specific services structure for a processor - * with the given logical ID. - * - * @param[in] FamilyTable The table to search in. - * @param[out] CpuServices The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetFeatureServicesOfCurrentCore ( - IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, - OUT CONST VOID **CpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID CpuFamilyRevision; - - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the family specific services structure for a processor - * with the given logical ID. - * - * @param[in] LogicalId The Processor's logical ID. - * @param[out] FunctionTable The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetCpuServicesFromLogicalId ( - IN CPU_LOGICAL_ID *LogicalId, - OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GetFeatureServicesFromLogicalId (&CpuSupportedFamiliesTable, - LogicalId, - (CONST VOID **) FunctionTable, - StdHeader); - if (*FunctionTable == NULL) { - *FunctionTable = &cpuNullServices; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Retrieves a pointer to the family specific services structure for a processor - * with the given logical ID. - * - * @param[in] FamilyTable The table to search in. - * @param[in] LogicalId The Processor's logical ID. - * @param[out] CpuServices The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetFeatureServicesFromLogicalId ( - IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, - IN CPU_LOGICAL_ID *LogicalId, - OUT CONST VOID **CpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GetCpuServices (FamilyTable, &LogicalId->Family, CpuServices, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Finds a family match in the given table, and returns the pointer to the - * appropriate table. If no match is found in the table, NULL will be returned. - * - * @param[in] FamilyTable The table to search in. - * @param[in] MatchData Family data that must match. - * @param[out] CpuServices The Processor's Family Specific services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -STATIC -GetCpuServices ( - IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, - IN UINT64 *MatchData, - OUT CONST VOID **CpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsFamily; - UINT8 i; - UINT8 NumberOfFamiliesSupported; - CONST CPU_SPECIFIC_SERVICES_XLAT *ImageSupportedFamiliesPtr; - - ImageSupportedFamiliesPtr = FamilyTable->FamilyTable; - NumberOfFamiliesSupported = FamilyTable->Elements; - IsFamily = FALSE; - for (i = 0; i < NumberOfFamiliesSupported; i++) { - if ((ImageSupportedFamiliesPtr[i].Family & *MatchData) != 0) { - IsFamily = TRUE; - break; - } - } - if (IsFamily) { - *CpuServices = ImageSupportedFamiliesPtr[i].TablePtr; - } else { - *CpuServices = NULL; - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Used to stub out various family specific tables of information. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Empty NULL, to indicate no data. - * @param[out] NumberOfElements Zero, to indicate no data. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -GetEmptyArray ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **Empty, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = 0; - *Empty = NULL; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h deleted file mode 100644 index 4cb929bd3b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h +++ /dev/null @@ -1,1008 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Family Translation functions. - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 55552 $ @e \$Date: 2011-06-22 09:31:58 -0600 (Wed, 22 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_FAMILY_TRANSLATION_H_ -#define _CPU_FAMILY_TRANSLATION_H_ - -/** - * @page cpuimplfss CPU Family Specific Services Implementation Guide - * - * CPU Family Specific Services provides access to supported family service functions and data, - * in a manner that isolates calling code from knowledge about particular families or which - * families are supported in the current build. - * - * @par Adding a Method to Family Specific Services - * - * To add a new method to Family Specific Services, follow these steps. - *
    - *
  • Create a typedef for the Method with the correct parameters and return type. - * - *
      - *
    • Name the method typedef (*PF_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item, - * but with "_"'s and UPPERCASE, rather than mixed case. - * @n typedef VOID (*PF_METHOD_NAME)(); @n - * - *
    • [Optionally make the type F_ and provide a separate: - * @n typedef F_METHOD_NAME *PF_METHOD_NAME> @n - * and provide a single line "///" doxygen comment brief description on the PF_ type.] - *
    - * - *
  • The first parameter to @b all Family Specific Service Methods is @b required to be a reference to - * their Family Service struct. - * @n IN CPU_SPECIFIC_SERVICES *FamilySpecificServices @n - * - *
  • Provide a standard doxygen function preamble for the Method typedef. Begin the - * detailed description by provide a reference to the method instances page by including - * the lines below: - * @code - * * - * * @CpuServiceInstances - * * - * @endcode - * @note It is important to provide documentation for the method type, because the method may not - * have an implementation in any families supported by the current package. @n - * - *
  • Add to the CPU_SPECIFIC_SERVICES struct an item for the Method: - * @n PF_METHOD_NAME MethodName; ///< Method: description. @n - *
- * - * @par Implementing a Family Specific Instance of the method. - * - * To implement an instance of a method for a specific family follow these steps. - * - * - In appropriate files in the family specific directory, implement the method with the return type - * and parameters matching the method typedef. - * - * - Name the function FnnMethodName(), where nn is the family number. - * - * - Create a doxygen function preamble for the method instance. Begin the detailed description with - * an Implements command to reference the method type and add this instance to the Method Instances page. - * @code - * * - * * @CpuServiceMethod{::F_METHOD_NAME}. - * * - * @endcode - * - * - To access other family specific services as part of the method implementation, the function - * @b must use FamilySpecificServices->OtherMethod(). Do not directly call other family specific - * routines, because in the table there may be overrides or this routine may be shared by multiple families. - * - * - Do @b not call Family translation services from a family specific instance. Use the parameter. - * - * - Add the instance to the family specific CPU_SPECIFIC_SERVICES instance. - * - * - If a family does not need an instance of the method use one of the CommonReturns from - * CommonReturns.h with the same return type. - * - * @par Invoking Family Specific Services. - * - * The following example shows how to invoke a family specific method. - * @n @code - * CPU_SPECIFIC_SERVICES *FamilyServices; - * - * GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - * ASSERT (FamilyServices != NULL); - * FamilyServices->MethodName (FamilyServices, StdHeader); - * @endcode - * - */ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ -#include "cpuPostInit.h" -#include "cpuEnvInit.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "Table.h" -#include "Ids.h" -#include "Topology.h" - -// Forward declaration needed for multi-structure mutual references. -AGESA_FORWARD_DECLARATION (CPU_SPECIFIC_SERVICES); -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - -/** - * Disable the desired P-state. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber Hardware P-state number. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_DISABLE_PSTATE ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_DISABLE_PSTATE *PF_CPU_DISABLE_PSTATE; - -/** - * Transition the current core to the desired P-state. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber Software P-state number. - * @param[in] WaitForChange Wait/don't wait for P-state change to complete. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_TRANSITION_PSTATE ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - IN BOOLEAN WaitForChange, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_TRANSITION_PSTATE *PF_CPU_TRANSITION_PSTATE; - -/** - * Get the desired P-state's maximum current required in milliamps. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The desired hardware P-state number. - * @param[out] ProcIddMax The P-state's maximum current. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The P-state is enabled, and ProcIddMax is valid. - * @retval FALSE The P-state is disabled. - * - */ -typedef BOOLEAN F_CPU_GET_IDD_MAX ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_IDD_MAX *PF_CPU_GET_IDD_MAX; - - -/** - * Returns the rate at which the current core's timestamp counter increments in megahertz. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FreqInMHz The rate at which the TSC increments in megahertz. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_TSC_RATE ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_TSC_RATE *PF_CPU_GET_TSC_RATE; - -/** - * Returns the processor north bridge's clock rate in megahertz. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FreqInMHz The desired node's frequency in megahertz. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS FreqInMHz is valid. - */ -typedef AGESA_STATUS F_CPU_GET_NB_FREQ ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_NB_FREQ *PF_CPU_GET_NB_FREQ; - -/** - * Returns the node's minimum and maximum northbridge frequency. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[out] MinFreqInMHz The minimum north bridge frequency. - * @param[out] MaxFreqInMHz The maximum north bridge frequency. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_STATUS Northbridge frequency is valid - */ -typedef AGESA_STATUS F_CPU_GET_MIN_MAX_NB_FREQ ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - OUT UINT32 *MinFreqInMHz, - OUT UINT32 *MaxFreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_MIN_MAX_NB_FREQ *PF_CPU_GET_MIN_MAX_NB_FREQ; - -/** - * Returns the processor north bridge's P-state settings. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[in] NbPstate The NB P-state number to check. - * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. - * @param[out] FreqDivisor The desired node's frequency divisor. - * @param[out] VoltageInuV The desired node's voltage in microvolts. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE NbPstate is valid - * @retval FALSE NbPstate is disabled or invalid - */ -typedef BOOLEAN F_CPU_GET_NB_PSTATE_INFO ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_NB_PSTATE_INFO *PF_CPU_GET_NB_PSTATE_INFO; - -/** - * Returns whether or not the NB frequency initialization sequence is required - * to be performed by the BIOS. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PciAddress The northbridge to query by pci base address. - * @param[out] NbVidUpdateAll Do all NbVids need to be updated as well. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef BOOLEAN F_CPU_IS_NBCOF_INIT_NEEDED ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PCI_ADDR *PciAddress, - OUT BOOLEAN *NbVidUpdateAll, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_IS_NBCOF_INIT_NEEDED *PF_CPU_IS_NBCOF_INIT_NEEDED; - -/** - * Get the desired NB P-state's maximum current required in milliamps. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StateNumber The desired hardware P-state number. - * @param[out] NbIddMax The NB P-state's maximum current. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The NB P-state is enabled, and NbIddMax is valid. - * @retval FALSE The NB P-state is disabled. - * - */ -typedef BOOLEAN F_CPU_GET_NB_IDD_MAX ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 StateNumber, - OUT UINT32 *NbIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_NB_IDD_MAX *PF_CPU_GET_NB_IDD_MAX; - -/** - * Launches the desired core from the reset vector. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] SocketNumber The desired core's socket number. - * @param[in] ModuleNumber The desired core's die number. - * @param[in] CoreNumber The desired core's die relative core number. - * @param[in] PrimaryCoreNumber SocketNumber / ModuleNumber's primary core number. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The core was launched successfully. - * @retval FALSE The core was previously launched, or has a problem. - */ -typedef BOOLEAN F_CPU_AP_INITIAL_LAUNCH ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 SocketNumber, - IN UINT32 ModuleNumber, - IN UINT32 CoreNumber, - IN UINT32 PrimaryCoreNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_AP_INITIAL_LAUNCH *PF_CPU_AP_INITIAL_LAUNCH; - -/** - * Returns the appropriate number of physical processor cores - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return One-based number of physical cores on current processor - */ -typedef UINT8 F_CPU_NUMBER_OF_PHYSICAL_CORES ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_NUMBER_OF_PHYSICAL_CORES *PF_CPU_NUMBER_OF_PHYSICAL_CORES; - -/** - * Returns a family specific table of information pointer and size. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FamilySpecificArray Pointer to the appropriate list for the core. - * @param[out] NumberOfElements Number of valid entries FamilySpecificArray. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID F_CPU_GET_FAMILY_SPECIFIC_ARRAY ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **FamilySpecificArray, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_FAMILY_SPECIFIC_ARRAY *PF_CPU_GET_FAMILY_SPECIFIC_ARRAY; - -/** - * Returns a model specific list of logical IDs. - * - * @param[out] LogicalIdXlat Installed logical ID table. - * @param[out] NumberOfElements Number of entries in the Logical ID translate table. - * @param[out] LogicalFamily Base logical family bit mask. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID F_CPU_GET_SUBFAMILY_ID_ARRAY ( - OUT CONST CPU_LOGICAL_ID_XLAT **LogicalIdXlat, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method. -typedef F_CPU_GET_SUBFAMILY_ID_ARRAY *PF_CPU_GET_SUBFAMILY_ID_ARRAY; - -/** - * Use the Mailbox Register to get the Ap Mailbox info for the current core. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] ApMailboxInfo The AP Mailbox info - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID (F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE *PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE; - -/** - * Set the AP core number in the AP's Mailbox. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Socket The AP's socket - * @param[in] Module The AP's module - * @param[in] ApCoreNumber The AP's unique core number - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID (F_CPU_SET_AP_CORE_NUMBER) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 ApCoreNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_SET_AP_CORE_NUMBER *PF_CPU_SET_AP_CORE_NUMBER; - -/** - * Get the AP core number from hardware. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The AP's unique core number - */ -typedef UINT32 (F_CPU_GET_AP_CORE_NUMBER) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_GET_AP_CORE_NUMBER *PF_CPU_GET_AP_CORE_NUMBER; - -/** - * Move the AP's core number from the mailbox to hardware. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The AP's unique core number - */ -typedef VOID (F_CPU_TRANSFER_AP_CORE_NUMBER) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_TRANSFER_AP_CORE_NUMBER *PF_CPU_TRANSFER_AP_CORE_NUMBER; - -/** - * Core ID position in the initial APIC ID, reflected as a number zero or one. - */ -typedef enum { - CoreIdPositionZero, ///< Zero, the Core Id bits are the Most Significant bits. - CoreIdPositionOne, ///< One, the Core Id bits are the Least Significant bits. - CoreIdPositionMax ///< Limit check. -} CORE_ID_POSITION; - -/** - * Return a number zero or one, based on the Core ID position in the initial APIC Id. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval CoreIdPositionZero Core Id is not low - * @retval CoreIdPositionOne Core Id is low - */ -typedef CORE_ID_POSITION F_CORE_ID_POSITION_IN_INITIAL_APIC_ID ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CORE_ID_POSITION_IN_INITIAL_APIC_ID *PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID; - -/** - * Get least common features set of all CPUs and save them to CPU_FEATURES_LIST - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] cpuFeatureListPtr The CPU Features List - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID (F_CPU_SAVE_FEATURES) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureListPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_SAVE_FEATURES *PF_CPU_SAVE_FEATURES; - -/** - * Get least common features from CPU_FEATURES_LIST and write them to CPU - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] cpuFeatureListPtr The CPU Features List - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID (F_CPU_WRITE_FEATURES) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureListPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_CPU_WRITE_FEATURES *PF_CPU_WRITE_FEATURES; - -/** - * Set Warm Reset Flag - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Header for library and services. - * @param[in] Request Value to set the flags to. - * - */ -typedef VOID (F_CPU_SET_WARM_RESET_FLAG) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ); - -/// Reference to a method -typedef F_CPU_SET_WARM_RESET_FLAG *PF_CPU_SET_WARM_RESET_FLAG; - -/** - * Get Warm Reset Flag - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Header for library and services. - * @param[out] BiosRstDet Indicate warm reset status. - * - */ -typedef VOID (F_CPU_GET_WARM_RESET_FLAG) ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ); - -/// Reference to a method -typedef F_CPU_GET_WARM_RESET_FLAG *PF_CPU_GET_WARM_RESET_FLAG; - - -/** - * Get CPU Specific Platform Type Info. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] FeaturesUnion The Features supported by this platform. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef AGESA_STATUS F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PLATFORM_FEATS *FeaturesUnion, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO *PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO; - -/** - * Is the Northbridge PState feature enabled? - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The NB PState feature is enabled. - * @retval FALSE The NB PState feature is not enabled. - */ -typedef BOOLEAN F_IS_NB_PSTATE_ENABLED ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a method -typedef F_IS_NB_PSTATE_ENABLED *PF_IS_NB_PSTATE_ENABLED; - -/** - * Gets the next link with features matching the HT phy register table entry type features. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] HtHostCapability Initially the PCI bus, device, function=0, offset=0; - * Each call returns the HT Host Capability function and offset; - * Caller may use it to access registers, but must @b not modify it; - * Each new call passes the previous value as input. - * @param[in,out] Link Initially zero, each call returns the link number; caller passes it back unmodified each call. - * @param[in] HtPhyLinkType Link type field from a register table entry to compare against - * @param[out] MatchedSublink1 TRUE: It is actually just sublink 1 that matches, FALSE: any other condition. - * @param[out] Frequency0 The frequency of sublink0 (200 MHz if not connected). - * @param[out] Frequency1 The frequency of sublink1 (200 MHz if not connected). - * @param[in] StdHeader Standard Head Pointer - * - * @retval TRUE Link matches - * @retval FALSE No more links - * - */ -typedef BOOLEAN F_NEXT_LINK_HAS_HTFPY_FEATS ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT PCI_ADDR *HtHostCapability, - IN OUT UINT32 *Link, - IN HT_PHY_LINK_FEATS *HtPhyLinkType, - OUT BOOLEAN *MatchedSublink1, - OUT HT_FREQUENCIES *Frequency0, - OUT HT_FREQUENCIES *Frequency1, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_NEXT_LINK_HAS_HTFPY_FEATS *PF_NEXT_LINK_HAS_HTFPY_FEATS; - -/** - * Applies an HT Phy read-modify-write based on an HT Phy register table entry. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] HtPhyEntry HT Phy register table entry to apply - * @param[in] CapabilitySet The link's HT Host base address. - * @param[in] Link Zero based, node, link number (not package link), always a sublink0 link. - * @param[in] StdHeader Config handle for library and services - * - */ -typedef VOID F_SET_HT_PHY_REGISTER ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN HT_PHY_TYPE_ENTRY_DATA *HtPhyEntry, - IN PCI_ADDR CapabilitySet, - IN UINT32 Link, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_SET_HT_PHY_REGISTER *PF_SET_HT_PHY_REGISTER; - -/** - * Performs an early initialization function on the executing core. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams CPU module early paramters. - * @param[in] StdHeader Config handle for library and services - * - */ -typedef VOID F_PERFORM_EARLY_INIT_ON_CORE ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_PERFORM_EARLY_INIT_ON_CORE *PF_PERFORM_EARLY_INIT_ON_CORE; - -/** - * A struct that contains function pointer and function flag - * - * the flag indicates if the function need to be run. - */ -typedef struct _S_PERFORM_EARLY_INIT_ON_CORE { - PF_PERFORM_EARLY_INIT_ON_CORE PerformEarlyInitOnCore; ///< Function Pointer, which points to the function need to be run at early stage - UINT32 PerformEarlyInitFlag; ///< Function Flag, which indicates if the function need to be run. -} S_PERFORM_EARLY_INIT_ON_CORE; - -/** - * Returns the initialization steps that the executing core should - * perform at AmdInitEarly. - * - * @CpuServiceInstances - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[out] Table Table of appropriate init steps for the executing core. - * @param[in] EarlyParams CPU module early paramters. - * @param[in] StdHeader Config handle for library and services - * - */ -typedef VOID F_GET_EARLY_INIT_TABLE ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_GET_EARLY_INIT_TABLE *PF_GET_EARLY_INIT_TABLE; - -/** - * Provide the features of the next HT link. - * - * @CpuServiceInstances - * - * This method is different than the HT Phy Features method, because for the phy registers - * sublink 1 matches and should be programmed if the link is ganged but for PCI config - * registers sublink 1 is reserved if the link is ganged. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in,out] Link The link number, for accessing non-capability set registers. - * Zero on initial call, and passed back unmodified on each subsequent call. - * @param[in,out] LinkBase IN: initially the node's PCI config base address, passed back on each call. - * OUT: the base HT Host capability PCI address for the link. - * @param[out] HtHostFeats The link's features. - * @param[in] StdHeader Standard Head Pointer - * - * @retval TRUE Valid link and features found. - * @retval FALSE No more links. - */ -typedef BOOLEAN F_GET_NEXT_HT_LINK_FEATURES ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT UINTN *Link, - IN OUT PCI_ADDR *LinkBase, - OUT HT_HOST_FEATS *HtHostFeats, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_GET_NEXT_HT_LINK_FEATURES *PF_GET_NEXT_HT_LINK_FEATURES; - -/// Cache Enable / Disable policy before giving control back to OS. -typedef enum { - InitCacheDisabled, ///StdHeader); - AmdParamApic->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamApic->StdHeader); - - AmdParamApic->IsPresent = GetApicId ( - &AmdParamApic->StdHeader, - AmdParamApic->Socket, - AmdParamApic->Core, - &AmdParamApic->ApicAddress, - &AgesaStatus - ); - - AGESA_TESTPOINT (TpIfAmdGetApicIdExit, &AmdParamApic->StdHeader); - return AgesaStatus; -} - -/** - * Get Processor Module's PCI Config Space address. - * - * Invoke corresponding Cpu Service for external user. - * - * @param[in,out] AmdParamGetPci Our interface struct - * - * @return The most severe status of any called service. - */ -AGESA_STATUS -AmdGetPciAddress ( - IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci - ) -{ - AGESA_STATUS AgesaStatus; - - AGESA_TESTPOINT (TpIfAmdGetPciAddressEntry, &AmdParamGetPci->StdHeader); - AmdParamGetPci->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamGetPci->StdHeader); - - AmdParamGetPci->IsPresent = GetPciAddress ( - &AmdParamGetPci->StdHeader, - AmdParamGetPci->Socket, - AmdParamGetPci->Module, - &AmdParamGetPci->PciAddress, - &AgesaStatus - ); - - AGESA_TESTPOINT (TpIfAmdGetPciAddressExit, &AmdParamGetPci->StdHeader); - return AgesaStatus; -} - -/** - * "Who am I" for the current running core. - * - * Invoke corresponding Cpu Service for external user. - * - * @param[in,out] AmdParamIdentify Our interface struct - * - * @return The most severe status of any called service. - */ -AGESA_STATUS -AmdIdentifyCore ( - IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify - ) -{ - AGESA_STATUS AgesaStatus; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - - AGESA_TESTPOINT (TpIfAmdIdentifyCoreEntry, &AmdParamIdentify->StdHeader); - AmdParamIdentify->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamIdentify->StdHeader); - - IdentifyCore ( - &AmdParamIdentify->StdHeader, - &Socket, - &Module, - &Core, - &AgesaStatus - ); - AmdParamIdentify->Socket = (UINT8)Socket; - AmdParamIdentify->Module = (UINT8)Module; - AmdParamIdentify->Core = (UINT8)Core; - - AGESA_TESTPOINT (TpIfAmdIdentifyCoreExit, &AmdParamIdentify->StdHeader); - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - AGESA common General Services - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Get a specified Core's APIC ID. - * - * Code sync: This calculation MUST match the assignment - * calculation done in LocalApicInitializationAtEarly function. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The socket in which the Core's Processor is installed. - * @param[in] Core The Core id. - * @param[out] ApicAddress The Core's APIC ID. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, APIC Id valid - * @retval FALSE The core is not present, APIC Id not valid. -*/ -BOOLEAN -GetApicId ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Core, - OUT UINT8 *ApicAddress, - OUT AGESA_STATUS *AgesaStatus - ) -{ - BOOLEAN ReturnValue; - UINT32 CoreCount; - UINT32 ApicID; - - ReturnValue = FALSE; - if (GetActiveCoresInGivenSocket (Socket, &CoreCount, StdHeader)) { - if (Core < CoreCount) { - ReturnValue = TRUE; - GetLocalApicIdForCore (Socket, Core, &ApicID, StdHeader); - *ApicAddress = (UINT8) ApicID; - } - } - - // Always Succeeds. - *AgesaStatus = AGESA_SUCCESS; - - return ReturnValue; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get Processor Module's PCI Config Space address. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The Core's Socket. - * @param[in] Module The Module in that Processor - * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, PCI Address valid - * @retval FALSE The core is not present, PCI Address not valid. - */ -BOOLEAN -GetPciAddress ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Module, - OUT PCI_ADDR *PciAddress, - OUT AGESA_STATUS *AgesaStatus - ) -{ - UINT8 Node; - BOOLEAN Result; - - ASSERT (Socket < MAX_SOCKETS); - ASSERT (Module < MAX_DIES); - - Result = TRUE; - // Always Succeeds. - *AgesaStatus = AGESA_SUCCESS; - - if (GetNodeId (Socket, Module, &Node, StdHeader)) { - // socket is populated - PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - PciAddress->Address.Device = PciAddress->Address.Device + Node; - } else { - // socket is not populated - PciAddress->AddressValue = ILLEGAL_SBDFO; - Result = FALSE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * "Who am I" for the current running core. - * - * @param[in] StdHeader Header for library and services. - * @param[out] Socket The current Core's Socket - * @param[out] Module The current Core's Processor Module - * @param[out] Core The current Core's core id. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - */ -VOID -IdentifyCore ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT UINT32 *Socket, - OUT UINT32 *Module, - OUT UINT32 *Core, - OUT AGESA_STATUS *AgesaStatus - ) -{ - AP_MAIL_INFO ApMailboxInfo; - UINT32 CurrentCore; - - // Always Succeeds. - *AgesaStatus = AGESA_SUCCESS; - - GetApMailbox (&ApMailboxInfo.Info, StdHeader); - ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS); - ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES); - *Socket = (UINT8)ApMailboxInfo.Fields.Socket; - *Module = (UINT8)ApMailboxInfo.Fields.Module; - - // Get Core Id - GetCurrentCore (&CurrentCore, StdHeader); - *Core = (UINT8)CurrentCore; -} - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - cpu component General Services - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the current Platform's number of Sockets, regardless of how many are populated. - * - * The Options component can provide how many sockets are available in system. - * This can be used to avoid testing presence of Processors in Sockets which don't exist. - * The result can be one socket to the maximum possible sockets of any supported processor family. - * You cannot assume that all sockets contain a processor or that the sockets have processors - * installed in any particular order. Do not convert this number to a number of nodes. - * - * @return The number of available sockets for the platform. - * - */ -UINT32 -GetPlatformNumberOfSockets ( VOID ) -{ - return TopologyConfiguration.PlatformNumberOfSockets; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the number of Modules to check presence in each Processor. - * - * The Options component can provide how many modules need to be check for presence in each - * processor, regardless whether all, or any, processor have that many modules present on this boot. - * The result can be one module to the maximum possible modules of any supported processor family. - * You cannot assume that Modules are in any particular order, especially with respect to node id. - * - * @return The maximum number of modules in each processor. - * - */ -UINT32 -GetPlatformNumberOfModules ( VOID ) -{ - return TopologyConfiguration.PlatformNumberOfModules; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is a processor present in Socket? - * - * Check to see if any possible module of the processor is present. This provides - * support for a few cases where a PCI address isn't needed, but code still needs to - * iterate by Socket. - * - * @param[in] Socket The socket which is being tested - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE The socket has a processor installed - * @retval FALSE The socket is empty (or the processor is dead). - * - */ -BOOLEAN -IsProcessorPresent ( - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - BOOLEAN Result; - UINT32 Module; - AGESA_STATUS Status; - - ASSERT (Socket < MAX_SOCKETS); - Result = FALSE; - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - - // Get data block from heap - Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) { - Result = TRUE; - break; - } - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Provide the number of installed processors (not Nodes! and not Sockets!) - * - * Iterate over the Socket, Module to Node Map, counting the number of present nodes. - * Do not use this as a Node Count! Do not use this as the number of Sockets! (This - * is for APIC ID utilities.) - * - * @param[in] StdHeader Header for library and services. - * - * @return the number of processors installed - * - */ -UINT32 -GetNumberOfProcessors ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - UINT32 Result; - UINT32 Socket; - UINT32 Module; - AGESA_STATUS Status; - - Result = 0; - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - - // Get data block from heap - Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) { - Result++; - break; - } - } - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * For a specific Node, get its Socket and Module ids. - * - * If asking for the current running Node, read the mailbox socket, module. Specific Node, - * locate the Node to Socket/Module Map in heap, and return the ids, if present. - * - * @param[in] Node What Socket and Module is this Node? - * @param[out] Socket The Socket containing that Node. - * @param[out] Module The Processor Module of that Node. - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE Node is present, Socket, Module are valid. - * @retval FALSE Node is not present, why do you ask? - */ -BOOLEAN -GetSocketModuleOfNode ( - IN UINT32 Node, - OUT UINT32 *Socket, - OUT UINT32 *Module, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - NODE_TO_SOCKET_DIE_MAP pNodeMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - BOOLEAN Result; - AGESA_STATUS Status; - - Result = FALSE; - - ASSERT (Node < MAX_NODES); - - // Get Map from heap - SocketDieHeapDataBlock.BufferHandle = NODE_ID_MAP_HANDLE; - Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pNodeMap = (NODE_TO_SOCKET_DIE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pNodeMap != NULL) && (Status == AGESA_SUCCESS)); - *Socket = (*pNodeMap)[Node].Socket; - *Module = (*pNodeMap)[Node].Die; - if ((*pNodeMap)[Node].Socket != 0xFF) { - Result = TRUE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the current core's Processor APIC Index. - * - * The Processor APIC Index is the position of the current processor in the APIC id - * assignment. Processors are ordered in node id order. This is not the same, however, - * as the node id of the current socket and module or the current socket id. - * - * @param[in] Node The current desired core's node id (usually the current core). - * @param[in] StdHeader Header for library and services. - * - * @return Processor APIC Index - * - */ -UINT32 -GetProcessorApicIndex ( - IN UINT32 Node, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ProcessorApicIndex; - UINT32 PreviousSocket; - UINT32 CurrentSocket; - UINT32 Ignored; - UINT32 i; - - ASSERT (Node < MAX_NODES); - - // Calculate total APIC devices up to Current Node, Core. - ProcessorApicIndex = 0; - PreviousSocket = 0xFF; - for (i = 0; i < (Node + 1); i++) { - GetSocketModuleOfNode (i, &CurrentSocket, &Ignored, StdHeader); - if (CurrentSocket != PreviousSocket) { - ProcessorApicIndex++; - PreviousSocket = CurrentSocket; - } - } - // Convert to Index (zero based) from count (one based). - ProcessorApicIndex--; - return ProcessorApicIndex; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns current node number - * - * @param[out] Node This Core's Node id - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetCurrentNodeNum ( - OUT UINT32 *Node, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_MAIL_INFO ApMailboxInfo; - - // Get the Node Id from the Mailbox. - GetApMailbox (&ApMailboxInfo.Info, StdHeader); - ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES); - *Node = ApMailboxInfo.Fields.Node; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns Total number of active cores in the current socket - * - * @param[out] CoreCount The cores in this processor. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetActiveCoresInCurrentSocket ( - OUT UINT32 *CoreCount, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuidDataStruct; - UINT32 TotalCoresCount; - - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader); - TotalCoresCount = (CpuidDataStruct.ECX_Reg & 0x000000FF) + 1; - *CoreCount = TotalCoresCount; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Provides the Total number of active cores in the current core's node. - * - * @param[in] StdHeader Header for library and services. - * - * @return The current node core count - */ -UINTN -GetActiveCoresInCurrentModule ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 LowCore; - UINT32 HighCore; - UINT32 ProcessorCoreCount; - AGESA_STATUS AgesaStatus; - - ProcessorCoreCount = 0; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus); - if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) { - ProcessorCoreCount = ((HighCore - LowCore) + 1); - } - return ProcessorCoreCount; -} - -/** - * Provide the number of compute units on current module. - * - * - * @param[in] StdHeader Header for library and services. - * - * @return The current compute unit counts. - * - */ -UINTN -GetNumberOfCompUnitsInCurrentModule ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 CurrentCore; - UINT32 ComputeUnitCount; - UINT32 Enabled; - AGESA_STATUS IgnoredSts; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - - ComputeUnitCount = 0; - - ASSERT ((GetComputeUnitMapping (StdHeader) == AllCoresMapping) || - (GetComputeUnitMapping (StdHeader) == EvenCoresMapping)); - - IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts); - // Get data block from heap - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - IgnoredSts = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (IgnoredSts == AGESA_SUCCESS)); - // Current Core's socket, module must be present. - ASSERT ((*pSocketDieMap)[Socket][Module].Node != 0xFF); - // Process compute unit info - Enabled = (*pSocketDieMap)[Socket][Module].EnabledComputeUnits; - - while (Enabled > 0) { - if ((Enabled & 0x1) != 0) { - ComputeUnitCount++; - } - Enabled >>= 1; - } - - return ComputeUnitCount; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Provides the Total number of active cores in the given socket. - * - * @param[in] Socket Get a core count for the processor in this socket. - * @param[out] CoreCount Its core count - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE A processor is present in the Socket and the CoreCount is valid. - * @retval FALSE The Socket does not have a Processor - */ -BOOLEAN -GetActiveCoresInGivenSocket ( - IN UINT32 Socket, - OUT UINT32 *CoreCount, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 LowCore; - UINT32 HighCore; - UINT32 ProcessorCoreCount; - BOOLEAN Result; - - Result = FALSE; - ProcessorCoreCount = 0; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) { - ProcessorCoreCount = ProcessorCoreCount + ((HighCore - LowCore) + 1); - Result = TRUE; - } else { - break; - } - } - *CoreCount = ProcessorCoreCount; - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Provides the range of Cores in a Processor which are in a Module. - * - * Cores are named uniquely in a processor, 0 to TotalCores. Any module in the processor has - * a set of those cores, named from LowCore to HighCore. - * - * @param[in] Socket Get a core range for the processor in this socket. - * @param[in] Module Get a core range for this Module in the processor. - * @param[out] LowCore The lowest Processor Core in the Module. - * @param[out] HighCore The highest Processor Core in the Module. - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE A processor is present in the Socket and the Core Range is valid. - * @retval FALSE The Socket does not have a Processor - */ -BOOLEAN -GetGivenModuleCoreRange ( - IN UINT32 Socket, - IN UINT32 Module, - OUT UINT32 *LowCore, - OUT UINT32 *HighCore, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - BOOLEAN Result; - AGESA_STATUS Status; - - ASSERT (Socket < MAX_SOCKETS); - ASSERT (Module < MAX_DIES); - Result = FALSE; - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - - // Get data block from heap - Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); - *LowCore = (*pSocketDieMap)[Socket][Module].LowCore; - *HighCore = (*pSocketDieMap)[Socket][Module].HighCore; - if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) { - Result = TRUE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the current running core number. - * - * @param[out] Core The core id. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetCurrentCore ( - OUT UINT32 *Core, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuidDataStruct; - UINT32 LocalApicId; - UINT32 ApicIdCoreIdSize; - CORE_ID_POSITION InitApicIdCpuIdLo; - CPU_SPECIFIC_SERVICES *FamilyServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - // Read CPUID ebx[31:24] to get initial APICID - LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader); - LocalApicId = (CpuidDataStruct.EBX_Reg & 0xFF000000) >> 24; - - // Find the core ID size. - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader); - ApicIdCoreIdSize = (CpuidDataStruct.ECX_Reg & 0x0000F000) >> 12; - - InitApicIdCpuIdLo = FamilyServices->CoreIdPositionInInitialApicId (FamilyServices, StdHeader); - ASSERT (InitApicIdCpuIdLo < CoreIdPositionMax); - - // Now extract the core ID from the Apic ID by right justifying the id and masking off non-core Id bits. - *Core = ((LocalApicId >> ((1 - (UINT32)InitApicIdCpuIdLo) * (MAX_CORE_ID_SIZE - ApicIdCoreIdSize))) & - (MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize))); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns current node, and core number. - * - * @param[out] Node The node id of the current core's node. - * @param[out] Core The core id if the current core. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -GetCurrentNodeAndCore ( - OUT UINT32 *Node, - OUT UINT32 *Core, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Get Node Id - GetCurrentNodeNum (Node, StdHeader); - - // Get Core Id - GetCurrentCore (Core, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is the current core a primary core of it's node? - * - * @param[in] StdHeader Config handle for library and services. - * - * @retval TRUE Is Primary Core - * @retval FALSE Is not Primary Core - * - */ -BOOLEAN -IsCurrentCorePrimary ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Result; - UINT32 Core; - UINT32 Socket; - UINT32 Module; - UINT32 PrimaryCore; - UINT32 IgnoredCore; - AGESA_STATUS IgnoredSts; - - Result = FALSE; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - GetGivenModuleCoreRange (Socket, Module, &PrimaryCore, &IgnoredCore, StdHeader); - if (Core == PrimaryCore) { - Result = TRUE; - } - return Result; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns node id based on SocketId and ModuleId. - * - * @param[in] SocketId The socket to look up - * @param[in] ModuleId The module in that socket - * @param[out] NodeId Provide the corresponding Node Id. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE The socket is populated - * @retval FALSE The socket is not populated - * - */ -BOOLEAN -GetNodeId ( - IN UINT32 SocketId, - IN UINT32 ModuleId, - OUT UINT8 *NodeId, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - BOOLEAN Result; - AGESA_STATUS Status; - - Result = FALSE; - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - - // Get data block from heap - Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); - *NodeId = (*pSocketDieMap)[SocketId][ModuleId].Node; - if ((*pSocketDieMap)[SocketId][ModuleId].Node != 0xFF) { - Result = TRUE; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the cached AP Mailbox Info if available, or read the info from the hardware. - * - * Locate the known AP Mailbox Info Cache buffer in this core's local heap. If it - * doesn't exist, read the hardware to get the info. - * This routine gets the main AP mailbox, not the system degree. - * - * @param[out] ApMailboxInfo Provide the info in this AP core's mailbox - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -GetApMailbox ( - OUT UINT32 *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Ignored; - LOCATE_HEAP_PTR LocalApMailboxCache; - CPU_SPECIFIC_SERVICES *FamilyServices; - AP_MAILBOXES ApMailboxes; - BOOLEAN IamBsp; - - IamBsp = IsBsp (StdHeader, &Ignored); - LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE; - if (((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) || IamBsp) && - (HeapLocateBuffer (&LocalApMailboxCache, StdHeader) == AGESA_SUCCESS)) { - // If during HEAP_LOCAL_CACHE stage, we always try to get ApMailbox from heap - // If we're not in HEAP_LOCAL_CACHE stage, only BSP can get ApMailbox from heap - *ApMailboxInfo = ((AP_MAILBOXES *) LocalApMailboxCache.BufferPtr)->ApMailInfo.Info; - } else if (!IamBsp) { - // If this is an AP, the hardware register should be good. - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader); - *ApMailboxInfo = ApMailboxes.ApMailInfo.Info; - } else { - // This is the BSC. The hardware mailbox has not been set up yet. - ASSERT (FALSE); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Cache the Ap Mailbox info in our local heap for later use. - * - * This enables us to use the info even after the mailbox register is initialized - * with operational values. Get all the AP mailboxes and keep them in one buffer. - * - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -CacheApMailbox ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - ALLOCATE_HEAP_PARAMS AllocHeapParams; - AP_MAILBOXES ApMailboxes; - CPU_SPECIFIC_SERVICES *FamilyServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - // Get mailbox from hardware. - FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader); - - // Allocate heap for the info - AllocHeapParams.RequestedBufferSize = sizeof (AP_MAILBOXES); - AllocHeapParams.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - *(AP_MAILBOXES *)AllocHeapParams.BufferPtr = ApMailboxes; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Compute the degree of the system. - * - * The degree of a system is the maximum degree of any node. The degree of a node is the - * number of nodes to which it is directly connected (not considering width or redundant - * links). - * - * @param[in] StdHeader Config handle for library and services. - * - */ -UINTN -GetSystemDegree ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_MAILBOXES *ApMailboxes; - LOCATE_HEAP_PTR LocalApMailboxCache; - AGESA_STATUS Status; - - // Get data block from heap - LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE; - Status = HeapLocateBuffer (&LocalApMailboxCache, StdHeader); - // non-Success handled by ASSERT not NULL below. - ApMailboxes = (AP_MAILBOXES *)LocalApMailboxCache.BufferPtr; - ASSERT ((ApMailboxes != NULL) && (Status == AGESA_SUCCESS)); - return ApMailboxes->ApMailExtInfo.Fields.SystemDegree; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Spins until the number of microseconds specified have - * expired regardless of CPU operational frequency. - * - * @param[in] Microseconds Wait time in microseconds - * @param[in] StdHeader Header for library and services - * - */ -VOID -WaitMicroseconds ( - IN UINT32 Microseconds, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TscRateInMhz; - UINT64 NumberOfTicks; - UINT64 InitialTsc; - UINT64 CurrentTsc; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - LibAmdMsrRead (TSC, &InitialTsc, StdHeader); - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader); - NumberOfTicks = Microseconds * TscRateInMhz; - do { - LibAmdMsrRead (TSC, &CurrentTsc, StdHeader); - } while ((CurrentTsc - InitialTsc) < NumberOfTicks); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * A boolean function determine executed CPU is BSP core. - * - * @param[in,out] StdHeader Header for library and services - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - */ -BOOLEAN -IsBsp ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - OUT AGESA_STATUS *AgesaStatus - ) -{ - UINT64 MsrData; - - // Always Succeeds. - *AgesaStatus = AGESA_SUCCESS; - - // Read APIC_BASE register (0x1B), bit[8] returns 1 for BSP - LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader); - if ((MsrData & BIT8) != 0 ) { - return TRUE; - } else { - return FALSE; - } - -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the compute unit mapping algorithm. - * - * Look up the compute unit values for the current core's socket/module and find the matching - * core pair map item. This will tell us how to determine the core's status. - * - * @param[in] StdHeader Header for library and services - * - * @retval AllCoresMapping Each core is in a compute unit of its own. - * @retval EvenCoresMapping Even/Odd pairs of cores are in each compute unit. - */ -COMPUTE_UNIT_MAPPING -GetComputeUnitMapping ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CurrentCore; - UINT32 Module; - UINT32 Socket; - UINT8 Enabled; - UINT8 DualCore; - AGESA_STATUS IgnoredSts; - SOCKET_DIE_TO_NODE_MAP pSocketDieMap; - LOCATE_HEAP_PTR SocketDieHeapDataBlock; - CPU_SPECIFIC_SERVICES *FamilyServices; - CORE_PAIR_MAP *CorePairMap; - COMPUTE_UNIT_MAPPING Result; - - // Invalid mapping, unless we find one. - Result = MaxComputeUnitMapping; - - IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts); - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - // Get data block from heap - SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; - IgnoredSts = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); - pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; - ASSERT ((pSocketDieMap != NULL) && (IgnoredSts == AGESA_SUCCESS)); - // Current Core's socket, module must be present. - ASSERT ((*pSocketDieMap)[Socket][Module].Node != 0xFF); - - // Process compute unit info - Enabled = (*pSocketDieMap)[Socket][Module].EnabledComputeUnits; - DualCore = (*pSocketDieMap)[Socket][Module].DualCoreComputeUnits; - CorePairMap = FamilyServices->CorePairMap; - if ((Enabled != 0) && (CorePairMap != NULL)) { - while (CorePairMap->Enabled != 0xFF) { - if ((Enabled == CorePairMap->Enabled) && (DualCore == CorePairMap->DualCore)) { - break; - } - CorePairMap++; - } - // The assert is for finding a processor configured in a way the core pair map doesn't support. - ASSERT (CorePairMap->Enabled != 0xFF); - Result = CorePairMap->Mapping; - } else { - // Families that don't have compute units act as though each core is in its own compute unit - // and all cores are primary - Result = AllCoresMapping; - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is current core the primary core of its compute unit? - * - * Get the mapping algorithm and the current core number. Selecting First/Last ordering for - * primary @b ASSUMES cores are launched in ascending core number order. - * - * @param[in] Selector Select whether first or last core has the primary core role. - * @param[in] StdHeader Header for library and services - * - * @retval TRUE This is the primary core of a compute unit. - * @retval FALSE This is the second shared core of a compute unit. - * - */ -BOOLEAN -IsCorePairPrimary ( - IN COMPUTE_UNIT_PRIMARY_SELECTOR Selector, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Result; - UINT32 CurrentCore; - UINT32 Module; - UINT32 Socket; - AGESA_STATUS IgnoredSts; - - IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts); - - Result = FALSE; - switch (GetComputeUnitMapping (StdHeader)) { - case AllCoresMapping: - // All cores are primaries - Result = TRUE; - break; - case EvenCoresMapping: - // Even core numbers are first to execute, odd cores are last to execute - if (Selector == FirstCoreIsComputeUnitPrimary) { - Result = (BOOLEAN) ((CurrentCore & 1) == 0); - } else { - Result = (BOOLEAN) ((CurrentCore & 1) != 0); - } - break; - default: - ASSERT (FALSE); - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Are the two specified cores shared in a compute unit? - * - * Look up the compute unit values for the current core's socket/module and find the matching - * core pair map item. This will tell us how to determine the core's status. - * - * @param[in] Socket The processor in this socket is to be checked - * @param[in] Module The processor in this module is to be checked - * @param[in] CoreA One of the two cores to check - * @param[in] CoreB The other core to be checked - * @param[in] StdHeader Header for library and services - * - * @retval TRUE The cores are in the same compute unit. - * @retval FALSE The cores are not in the same compute unit, or the processor does - * not have compute units. - * - */ -BOOLEAN -AreCoresPaired ( - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 CoreA, - IN UINT32 CoreB, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Result; - - Result = FALSE; - switch (GetComputeUnitMapping (StdHeader)) { - case AllCoresMapping: - // No cores are sharing a compute unit - Result = FALSE; - break; - case EvenCoresMapping: - // Even core numbers are paired with odd core numbers, n with n + 1 - if ((CoreA & 1) == 0) { - Result = (BOOLEAN) (CoreA == (CoreB - 1)); - } else { - Result = (BOOLEAN) (CoreA == (CoreB + 1)); - } - break; - default: - ASSERT (FALSE); - } - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * This routine programs the registers necessary to get the PCI MMIO mechanism - * up and functioning. - * - * @param[in] StdHeader Pointer to structure containing the function call - * whose parameter structure is to be created, the - * allocation method, and a pointer to the newly - * created structure. - * - */ -VOID -InitializePciMmio ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 EncodedSize; - UINT64 LocalMsrRegister; - - // Make sure that Standard header is valid - ASSERT (StdHeader != NULL); - - if ((UserOptions.CfgPciMmioAddress != 0) && (UserOptions.CfgPciMmioSize != 0)) { - EncodedSize = LibAmdBitScanForward (UserOptions.CfgPciMmioSize); - LocalMsrRegister = ((UserOptions.CfgPciMmioAddress | BIT0) | (EncodedSize << 2)); - LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuInitEarlyTable.c deleted file mode 100644 index 53bc946c08..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuInitEarlyTable.c +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize the 'common' way of running early initialization. - * - * Returns the table of initialization steps to perform at - * AmdInitEarly. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_CPUINITEARLYTABLE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetCommonEarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly; - -CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA CommonEarlyInitOnCoreTable[] = -{ - {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {NULL, 0} -}; - -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a - * processor that uses the standard initialization steps should take. - * - * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[out] Table Table of appropriate init steps for the executing core. - * @param[in] EarlyParams Service Interface structure to initialize. - * @param[in] StdHeader Opaque handle to standard config header. - * - */ -VOID -GetCommonEarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *Table = CommonEarlyInitOnCoreTable; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.c deleted file mode 100644 index d053f4f2e3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.c +++ /dev/null @@ -1,392 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Late Init API - * - * Contains code for doing any late CPU initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_CPULATEINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -DisableCf8ExtCfg ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs CPU related initialization at the late entry point - * - * This function should be the last function run by the AGESA - * CPU module and prepares the processor for the operating system - * bootstrap load process. - * - * @param[in] StdHeader Config handle for library and services - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * - * @retval AGESA_SUCCESS - * - */ -AGESA_STATUS -AmdCpuLate ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ) -{ - AP_EXE_PARAMS ApParams; - - if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode != HARDWARE_PREFETCHER_AUTO) || - (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.SoftwarePrefetchMode != SOFTWARE_PREFETCHES_AUTO)) { - ApParams.StdHeader = *StdHeader; - ApParams.FunctionNumber = AP_LATE_TASK_CPU_LATE_INIT; - ApParams.RelatedDataBlock = (VOID *) PlatformConfig; - ApParams.RelatedBlockLength = sizeof (PLATFORM_CONFIGURATION); - RunLateApTaskOnAllAPs (&ApParams, StdHeader); - CpuLateInitApTask (&ApParams); - } - DisableCf8ExtCfg (StdHeader); - return (AGESA_SUCCESS); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * CpuLateInitApTask - * - * Description: - * This is the last function run on all APs - * - * Parameters: - * @param[in] ApExeParams Handle to config for library and services. - * - * @retval AGESA_STATUS - * - * Processing: - * - */ -AGESA_STATUS -CpuLateInitApTask ( - IN AP_EXE_PARAMS *ApExeParams - ) -{ - UINT64 LocalMsrRegister; - PLATFORM_CONFIGURATION *PlatformConfig; - BOOLEAN CuCfg3Exist; - - PlatformConfig = (PLATFORM_CONFIGURATION *) ApExeParams->RelatedDataBlock; - // The processor that has compute unit has CU_CFG3 MSR - switch (GetComputeUnitMapping (&(ApExeParams->StdHeader))) { - case AllCoresMapping: - CuCfg3Exist = FALSE; - break; - case EvenCoresMapping: - CuCfg3Exist = TRUE; - break; - default: - CuCfg3Exist = FALSE; - } - - // DISABLE_HARDWARE_PREFETCH - if (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_HARDWARE_PREFETCH) { - // DC_CFG (MSR_C001_1022) - // [13] = 1 - // [15] = 1 - LibAmdMsrRead (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); - LocalMsrRegister |= (BIT13 | BIT15); - LibAmdMsrWrite (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); - // CU_CFG3 (MSR_C001_102B) - // [3] = 1 - // [16] = 1 - // [17] = 1 - // [18] = 1 - if ((CuCfg3Exist) && (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader)))) { - LibAmdMsrRead (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); - LocalMsrRegister |= (BIT3 | BIT16 | BIT17 | BIT18); - LibAmdMsrWrite (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); - } - } - - // DISABLE_L1_PREFETCHER - if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER) || - (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES )) { - // CU_CFG3 (MSR_C001_102B) - // [3] = 1 - if ((CuCfg3Exist) && (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader)))) { - LibAmdMsrRead (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); - LocalMsrRegister |= BIT3; - LibAmdMsrWrite (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); - } - - } - - // DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES - if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES ) || - (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES )) { - // DC_CFG (MSR_C001_1022) - // [15] = 1 - LibAmdMsrRead (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); - LocalMsrRegister |= BIT15; - LibAmdMsrWrite (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); - - } - - // DISABLE_SOFTWARE_PREFETCHES - if (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.SoftwarePrefetchMode == DISABLE_SOFTWARE_PREFETCHES) { - // MSR_DE_CFG (MSR_C001_1029) - // [7:2] = 0x3F - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader))) { - LibAmdMsrRead (MSR_DE_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); - LocalMsrRegister |= 0xFC; - LibAmdMsrWrite (MSR_DE_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); - } - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Clear EnableCf8ExtCfg on all socket - * - * Clear F3x8C bit 14 EnableCf8ExtCfg - * - * @param[in] StdHeader Config handle for library and services - * - * - */ -VOID -DisableCf8ExtCfg ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - PCI_ADDR PciAddress; - UINT32 Socket; - UINT32 Module; - UINT32 PciData; - UINT32 LegacyPciAccess; - - ASSERT (IsBsp (StdHeader, &AgesaStatus)); - - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CFG_HIGH_REG; - LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); - // read from PCI register - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); - LibAmdIoRead (AccessWidth32, IOCFC, &PciData, StdHeader); - // Disable Cf8ExtCfg - PciData &= 0xFFFFBFFF; - // write to PCI register - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); - LibAmdIoWrite (AccessWidth32, IOCFC, &PciData, StdHeader); - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Calculate an ACPI style checksum - * - * Computes the checksum and stores the value to the checksum - * field of the passed in ACPI table's header. - * - * @param[in] Table ACPI table to checksum - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -ChecksumAcpiTable ( - IN OUT ACPI_TABLE_HEADER *Table, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BuffTempPtr; - UINT8 Checksum; - UINT32 BufferOffset; - - Table->Checksum = 0; - Checksum = 0; - BuffTempPtr = (UINT8 *) Table; - for (BufferOffset = 0; BufferOffset < Table->TableLength; BufferOffset++) { - Checksum = Checksum - *(BuffTempPtr + BufferOffset); - } - - Table->Checksum = Checksum; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Run code on every AP in the system. - * - * @param[in] ApParams AP task pointer. - * @param[in] StdHeader Handle to config for library and services - * - * @return The most severe AGESA_STATUS returned by an AP. - * - */ -AGESA_STATUS -RunLateApTaskOnAllAPs ( - IN AP_EXE_PARAMS *ApParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - UINT8 Socket; - UINT8 Core; - UINT8 ApicId; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - AGESA_STATUS CalledStatus; - AGESA_STATUS IgnoredStatus; - AGESA_STATUS AgesaStatus; - - ASSERT (IsBsp (StdHeader, &IgnoredStatus)); - - AgesaStatus = AGESA_SUCCESS; - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredStatus); - NumberOfSockets = GetPlatformNumberOfSockets (); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus); - AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader); - CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams); - AGESA_TESTPOINT (TpIfAfterRunApFromAllAps, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - } - } - } - } - return AgesaStatus; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Run code on core 0 of every socket in the system. - * - * @param[in] ApParams AP task pointer. - * @param[in] StdHeader Handle to config for library and services - * - * @return The most severe AGESA_STATUS returned by an AP. - * - */ -AGESA_STATUS -RunLateApTaskOnAllCore0s ( - IN AP_EXE_PARAMS *ApParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NumberOfSockets; - UINT8 Socket; - UINT8 ApicId; - UINT32 BscSocket; - UINT32 IgnoredModule; - UINT32 IgnoredCore; - AGESA_STATUS CalledStatus; - AGESA_STATUS IgnoredStatus; - AGESA_STATUS AgesaStatus; - - ASSERT (IsBsp (StdHeader, &IgnoredStatus)); - - AgesaStatus = AGESA_SUCCESS; - - IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &IgnoredCore, &IgnoredStatus); - NumberOfSockets = GetPlatformNumberOfSockets (); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - if (Socket != BscSocket) { - GetApicId (StdHeader, Socket, 0, &ApicId, &IgnoredStatus); - AGESA_TESTPOINT (TpIfBeforeRunApFromAllCore0s, StdHeader); - CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams); - AGESA_TESTPOINT (TpIfAfterRunApFromAllCore0s, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - } - } - } - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h deleted file mode 100644 index d0103477e7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuLateInit.h +++ /dev/null @@ -1,888 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Late Init API functions Prototypes. - * - * Contains code for doing any late CPU initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 60539 $ @e \$Date: 2011-10-17 17:11:05 -0600 (Mon, 17 Oct 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_LATE_INIT_H_ -#define _CPU_LATE_INIT_H_ - -#include "Filecode.h" - -// Forward declaration needed for multi-structure mutual references. -AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE); -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -CpuLateInitApTask ( - IN AP_EXE_PARAMS *ApExeParams - ); - -#define AP_LATE_TASK_CPU_LATE_INIT (PROC_CPU_CPULATEINIT_FILECODE) -#define CPU_LATE_INIT_AP_TASK {AP_LATE_TASK_CPU_LATE_INIT, (IMAGE_ENTRY) CpuLateInitApTask}, - -//---------------------------------------------------------------------------- -// DMI DEFINITIONS AND MACROS -// -//---------------------------------------------------------------------------- -#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE) -// SMBIOS constant definition -#define CENTRAL_PROCESSOR 0x03 -#define EXTERNAL_CLOCK_DFLT 200 -#define EXTERNAL_CLOCK_100MHZ 100 -#define P_FAMILY_UNKNOWN 0x02 -#define P_ENGINEERING_SAMPLE 0x00 -#define P_CHARACTERISTICS 0x4 -#define CACHE_CFG_L1 0x180 -#define CACHE_CFG_L2 0x181 -#define CACHE_CFG_L3 0x182 -#define SRAM_TYPE 0x10 -#define ERR_CORRECT_TYPE 0x06 -#define CACHE_TYPE 0x05 -#define ASSOCIATIVE_2_WAY 0x04 -#define ASSOCIATIVE_4_WAY 0x05 -#define ASSOCIATIVE_8_WAY 0x07 -#define ASSOCIATIVE_16_WAY 0x08 -#define ASSOCIATIVE_32_WAY 0x0B -#define ASSOCIATIVE_48_WAY 0x0C -#define ASSOCIATIVE_64_WAY 0x0D -#define ASSOCIATIVE_OTHER 0x01 -#define SOCKET_POPULATED 0x40 -#define CPU_STATUS_UNKNOWN 0x00 -#define CPU_STATUS_ENABLED 0x01 - -// Processor Upgrade Definition -#define P_UPGRADE_UNKNOWN 0x02 -#define P_UPGRADE_NONE 0x06 -#define P_UPGRADE_S1GX 0x16 -#define P_UPGRADE_AM2 0x17 -#define P_UPGRADE_F1207 0x18 -#define P_UPGRADE_G34 0x1A -#define P_UPGRADE_AM3 0x1B -#define P_UPGRADE_C32 0x1C -#define P_UPGRADE_FS1 0x27 -#define P_UPGRADE_FM1 0x29 - -//---------------------------------------------------------------------------- -// SRAT DEFINITIONS AND MACROS -// -//---------------------------------------------------------------------------- -#define NorthbridgeCapabilities 0xE8 -#define DRAMBase0 0x40 -#define MMIOBase0 0x80 -#define TOP_MEM 0xC001001Aul -#define LOW_NODE_DEVICEID 24 -#define LOW_APICID 0 - - -// Miscellaneous AMD related values -#define MAX_NUMBER_NODES 8 - -// Flags -#define ENABLED 1 // Bit 0 -#define DISABLED 0 // Bit 0 -#define HOTPLUGGABLE 2 // Bit 1 - -// Affinity Entry Structures -#define AE_APIC 0 -#define AE_MEMORY 1 - - -// Memory Types -#define TYPE_MEMORY 1 -#define TYPE_RESERVED 2 -#define TYPE_ACPI 3 -#define TYPE_NVS 4 - -//---------------------------------------------------------------------------- -// SLIT DEFINITIONS AND MACROS -// -//---------------------------------------------------------------------------- -#define PROBE_FILTER_CTRL_REG 0x1D4 -#define AMD_ACPI_SLIT_SOCKET_NUM_LENGTH 8 - -//---------------------------------------------------------------------------- -// P-STATE DEFINITIONS AND MACROS -// -//---------------------------------------------------------------------------- -//------------------------------------- -// ERROR Codes -//------------------------------------- -#define NO_ERROR 0x0 -#define USER_DISABLE_ERROR 0x01 // User disabled SSDT generation -#define CORES_MISSMATCH_PSS_ERROR 0x02 // No PSS match -#define PNOW_SUPPORT_ERROR 0x04 // One of the Cores do not support PNOW! -#define PWR_FREQ_MATCH_ERROR 0x08 // FREQ and PWR mismatch -#define NO_PSS_SIZE_ERROR 0x10 // Error in PSS Size -#define INVALID_PSTATE_ERROR 0x20 // Invalid Max or only 1 P-State available -#define NO_PSS_ENTRY 0x0FFFF -#define INVALID_FREQ 0x0FFFFFFFF - -//------------------------- -// Default definitions -// AMD BKDG default values -//------------------------- -#define DEFAULT_ISOCH_RELIEF_TIME IRT_80uS -#define DEFAULT_RAMP_VOLTAGE_OFFSET RVO_50mV -#define DEFAULT_MAX_VOLTAGE_STEP MVS_25mV -#define DEFAULT_PERF_PRESENT_CAP 0 // default for Desktop -#define DEFAULT_VOLTAGE_STABLE_TIME (100 / 20) // 100uS -#define DEFAULT_PLL_LOCK_TIME 2 // 2uS -#define DEFAULT_TRANSITION_LATENCY 100 // 100uS -#define DEFAULT_BUS_MASTER_LATENCY 9 // 9uS -#define DEFAULT_CPU_SCOPE_NUMBER "0UPC" - -// Defines for Common ACPI -// ----------------------------- -#define SCOPE_OPCODE 0x10 -#define NAME_OPCODE 0x08 -#define METHOD_OPCODE 0x14 -#define PACKAGE_OPCODE 0x12 -#define BUFFER_OPCODE 0x11 -#define BYTE_PREFIX_OPCODE 0x0A -#define WORD_PREFIX_OPCODE 0x0B -#define DWORD_PREFIX_OPCODE 0x0C -#define RETURN_OPCODE 0xA4 -#define ACPI_BUFFER 0x080A0B11 - -// Generic Register Descriptor (GDR) Fields -#define GDR_ASI_SYSTEM_IO 0x01 // Address Space ID -#define GDR_ASZ_BYTE_ACCESS 0x01 // Address Size - -// Defines for ACPI Scope Table -// ---------------------------- -#define SCOPE_LENGTH (SCOPE_STRUCT_SIZE + \ - PCT_STRUCT_SIZE + \ - PSS_HEADER_STRUCT_SIZE + \ - PSS_BODY_STRUCT_SIZE + \ - PPC_HEADER_BODY_STRUCT_SIZE) -#define SCOPE_VALUE1 0x5C -#define SCOPE_VALUE2 0x2E -#define SCOPE_NAME__ '_' -#define SCOPE_NAME_P 'P' -#define SCOPE_NAME_R 'R' -#define SCOPE_NAME_S 'S' -#define SCOPE_NAME_B 'B' -#define SCOPE_NAME_C 'C' -#define SCOPE_NAME_U 'U' -#define SCOPE_NAME_0 '0' -#define SCOPE_NAME_1 '1' -#define SCOPE_NAME_2 '2' -#define SCOPE_NAME_3 '3' -#define SCOPE_NAME_A 'A' - -#ifdef OEM_SCOPE_NAME - #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A') - #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)" - #endif - #define SCOPE_NAME_VALUE OEM_SCOPE_NAME -#else - #define SCOPE_NAME_VALUE SCOPE_NAME_C -#endif // OEM_SCOPE_NAME - -#ifdef OEM_SCOPE_NAME1 - #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \ - ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \ - (OEM_SCOPE_NAME1 == '_'))) - #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)" - #endif - #define SCOPE_NAME_VALUE1 OEM_SCOPE_NAME1 -#else - #define SCOPE_NAME_VALUE1 SCOPE_NAME_0 -#endif // OEM_SCOPE_NAME - -// Defines for PCT Control and Status Table -// ---------------------------------------- -#define PCT_NAME__ '_' -#define PCT_NAME_P 'P' -#define PCT_NAME_C 'C' -#define PCT_NAME_T 'T' -#define PCT_VALUE1 0x11022C12 -#define PCT_VALUE2 0x0A14 -#define PCT_VALUE3 0x11 -#define GENERIC_REG_DESCRIPTION 0x82 -#define PCT_LENGTH 0x0C -#define PCT_ADDRESS_SPACE_ID 0x7F -#define PCT_REGISTER_BIT_WIDTH 0x40 -#define PCT_REGISTER_BIT_OFFSET 0x00 -#define PCT_RESERVED 0x00 -#define PCT_CONTROL_REG_LO 0xC0010062 -#define PCT_CONTROL_REG_HI 0x00 -#define PCT_VALUE4 0x14110079 -#define PCT_VALUE5 0x110A -#define PCT_STATUS_REG_LO 0x00 -#define PCT_STATUS_REG_HI 0x00 -#define PCT_VALUE6 0x0079 - - -// Defines for PSS Header Table -// ---------------------------- -#define PSS_NAME__ '_' -#define PSS_NAME_X 'X' -#define PSS_NAME_P 'P' -#define PSS_NAME_S 'S' -#define PSS_LENGTH (sizeof pssBodyStruct + 3) -#define NUM_OF_ITEMS_IN_PSS 0x00 - - -// Defines for PSS Header Table -// ---------------------------- -#define PSS_PKG_LENGTH 0x20 // PSS_BODY_STRUCT_SIZE - 1 -#define PSS_NUM_OF_ELEMENTS 0x06 -#define PSS_FREQUENCY 0x00 -#define PSS_POWER 0x00 -#define PSS_TRANSITION_LATENCY DEFAULT_TRANSITION_LATENCY -#define PSS_BUS_MASTER_LATENCY DEFAULT_BUS_MASTER_LATENCY -#define PSS_CONTROL ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \ - (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \ - (DEFAULT_EXT_TYPE << 27) + \ - (DEFAULT_PLL_LOCK_TIME << 20) + \ - (DEFAULT_MAX_VOLTAGE_STEP << 18) + \ - (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \ - (PSS_VID << 6) + PSS_FID) -#define PSS_STATUS (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID) - -// Defines for XPSS Header Table -// ---------------------------- -#define XPSS_PKG_LENGTH 0x47 // XPSS_BODY_STRUCT_SIZE - 1 -#define XPSS_NUM_OF_ELEMENTS 0x08 -#define XPSS_ACPI_BUFFER 0x080A0B11 - - -// Defines for PPC Header Table -// ---------------------------- -#define PPC_NAME__ '_' -#define PPC_NAME_P 'P' -#define PPC_NAME_C 'C' -#define PPC_NAME_V 'V' -#define PPC_METHOD_FLAGS 0x00; -#define PPC_VALUE1 0x0A; - -// Defines for PSD Header Table -// ---------------------------- -#define PSD_NAME__ '_' -#define PSD_NAME_P 'P' -#define PSD_NAME_S 'S' -#define PSD_NAME_D 'D' -#define PSD_HEADER_LENGTH (PSD_BODY_STRUCT_SIZE + 2) -#define PSD_VALUE1 0x01 - - -// Defines for PSD Header Table -// ---------------------------- -#define PSD_PKG_LENGTH (PSD_BODY_STRUCT_SIZE - 1) -#define NUM_OF_ENTRIES 0x05 -#define PSD_NUM_OF_ENTRIES 0x05 -#define PSD_REVISION 0x00 -#define PSD_DEPENDENCY_DOMAIN 0x00 -#define PSD_COORDINATION_TYPE_HW_ALL 0xFE -#define PSD_COORDINATION_TYPE_SW_ANY 0xFD -#define PSD_COORDINATION_TYPE_SW_ALL 0xFC -#define PSD_NUM_OF_PROCESSORS 0x01 -#define PSD_CORE_NUM_PER_COMPUTE_UNIT 0x02 -#define PSD_DOMAIN_COMPUTE_UNIT_MASK 0x7F - - -#define CUSTOM_PSTATE_FLAG 0x55 -#define PSTATE_FLAG_1 0x55 -#define TARGET_PSTATE_FLAG 0xAA -#define PSTATE_FLAG_2 0xAA - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ -//---------------------------------------------------------------------------- -// ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- - -//-------------------------------------------- -// AML code definition -// (Scope) -//--------------------------------------------- -/// SCOPE -typedef struct _SCOPE { - UINT8 ScopeOpcode; ///< Opcode - UINT16 ScopeLength; ///< Scope Length - UINT8 ScopeValue1; ///< Value1 - UINT8 ScopeValue2; ///< Value2 - UINT8 ScopeNamePt1a__; ///< Name Pointer - UINT8 ScopeNamePt1a_P; ///< Name Pointer - UINT8 ScopeNamePt1a_R; ///< Name Pointer - UINT8 ScopeNamePt1b__; ///< Name Pointer - UINT8 ScopeNamePt2a_C; ///< Name Pointer - UINT8 ScopeNamePt2a_P; ///< Name Pointer - UINT8 ScopeNamePt2a_U; ///< Name Pointer - UINT8 ScopeNamePt2a_0; ///< Name Pointer -} SCOPE; -#define SCOPE_STRUCT_SIZE 13 // 13 Bytes - -//-------------------------------------------- -// AML code definition -// (PCT Header and Body) -//--------------------------------------------- - -///Performance Control Header -typedef struct _PCT_HEADER_BODY { - UINT8 NameOpcode; ///< Opcode - UINT8 PctName_a__; ///< String "_" - UINT8 PctName_a_P; ///< String "P" - UINT8 PctName_a_C; ///< String "C" - UINT8 PctName_a_T; ///< String "T" - UINT32 Value1; ///< Value1 - UINT16 Value2; ///< Value2 - UINT8 Value3; ///< Value3 - UINT8 GenericRegDescription1; ///< Generic Reg Description - UINT16 Length1; ///< Length1 - UINT8 AddressSpaceId1; ///< PCT Address Space ID - UINT8 RegisterBitWidth1; ///< PCT Register Bit Width - UINT8 RegisterBitOffset1; ///< PCT Register Bit Offset - UINT8 Reserved1; ///< Reserved - UINT32 ControlRegAddressLo; ///< Control Register Address Low - UINT32 ControlRegAddressHi; ///< Control Register Address High - UINT32 Value4; ///< Value4 - UINT16 Value5; ///< Value 5 - UINT8 GenericRegDescription2; ///< Generic Reg Description - UINT16 Length2; ///< Length2 - UINT8 AddressSpaceId2; ///< PCT Address Space ID - UINT8 RegisterBitWidth2; ///< PCT Register Bit Width - UINT8 RegisterBitOffset2; ///< PCT Register Bit Offset - UINT8 Reserved2; ///< Reserved - UINT32 StatusRegAddressLo; ///< Control Register Address Low - UINT32 StatusRegAddressHi; ///< Control Register Address High - UINT16 Value6; ///< Values -} PCT_HEADER_BODY; -#define PCT_STRUCT_SIZE 50 // 50 Bytes - - -//-------------------------------------------- -// AML code definition -// (PSS Header) -//-------------------------------------------- -///Performance Supported States Header -typedef struct _PSS_HEADER { - UINT8 NameOpcode; ///< Opcode - UINT8 PssName_a__; ///< String "_" - UINT8 PssName_a_P; ///< String "P" - UINT8 PssName_a_S; ///< String "S" - UINT8 PssName_b_S; ///< String "S" - UINT8 PkgOpcode; ///< Package Opcode - UINT16 PssLength; ///< PSS Length - UINT8 NumOfItemsInPss; ///< Number of Items in PSS -} PSS_HEADER; -#define PSS_HEADER_STRUCT_SIZE 9 // 9 Bytes - - -//-------------------------------------------- -// AML code definition -// (PSS Body) -//-------------------------------------------- -///Performance Supported States Body -typedef struct _PSS_BODY { - UINT8 PkgOpcode; ///< Package Opcode - UINT8 PkgLength; ///< Package Length - UINT8 NumOfElements; ///< Number of Elements - UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 - UINT32 Frequency; ///< Frequency - UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 - UINT32 Power; ///< Power - UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 - UINT32 TransitionLatency; ///< Transition Latency - UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4 - UINT32 BusMasterLatency; ///< Bus Master Latency - UINT8 DwordPrefixOpcode5; ///< Prefix Opcode5 - UINT32 Control; ///< Control - UINT8 DwordPrefixOpcode6; ///< Prefix Opcode6 - UINT32 Status; ///< Status -} PSS_BODY; -#define PSS_BODY_STRUCT_SIZE 33 // 33 Bytes - - -/*-------------------------------------------- - * AML code definition - * (XPSS Header) - *-------------------------------------------- - */ -/// Extended PSS Header -typedef struct _XPSS_HEADER { - UINT8 NameOpcode; ///< 08h - UINT8 XpssName_a_X; ///< String "X" - UINT8 XpssName_a_P; ///< String "P" - UINT8 XpssName_a_S; ///< String "S" - UINT8 XpssName_b_S; ///< String "S" - UINT8 PkgOpcode; ///< 12h - UINT16 XpssLength; ///< XPSS Length - UINT8 NumOfItemsInXpss; ///< Number of Items in XPSS -} XPSS_HEADER; -#define XPSS_HEADER_STRUCT_SIZE 9 // 9 Bytes - -/*-------------------------------------------- - * AML code definition - * (XPSS Body) - *-------------------------------------------- - */ -/// Extended PSS Body -typedef struct _XPSS_BODY { - UINT8 PkgOpcode; ///< 12h - UINT8 PkgLength; ///< Package Length - UINT8 XpssValueTbd; ///< XPSS Value - UINT8 NumOfElements; ///< Number of Elements - UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 - UINT32 Frequency; ///< Frequency - UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 - UINT32 Power; ///< Power - UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 - UINT32 TransitionLatency; ///< Transition Latency - UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4 - UINT32 BusMasterLatency; ///< Bus Master Latency - UINT32 ControlBuffer; ///< Control Buffer - UINT32 ControlLo; ///< Control Low - UINT32 ControlHi; ///< Control High - UINT32 StatusBuffer; ///< Status Buffer - UINT32 StatusLo; ///< Status Low - UINT32 StatusHi; ///< Status High - UINT32 ControlMaskBuffer; ///< Control Mask Buffer - UINT32 ControlMaskLo; ///< Control Mask Low - UINT32 ControlMaskHi; ///< Control Mask High - UINT32 StatusMaskBuffer; ///< Status Mask Buffer - UINT32 StatusMaskLo; ///< Status Mask Low - UINT32 StatusMaskHi; ///< Status Mask High -} XPSS_BODY; -#define XPSS_BODY_STRUCT_SIZE 72 // 72 Bytes - -/*-------------------------------------------- - * AML code definition - * (PPC Header and Body) - *-------------------------------------------- - */ -/// Performance Present Capabilities Header -typedef struct _PPC_HEADER_BODY { - UINT8 NameOpcode; ///< Name Opcode - UINT8 PpcName_a_P; ///< String "P" - UINT8 PpcName_b_P; ///< String "P" - UINT8 PpcName_a_C; ///< String "C" - UINT8 PpcName_a_V; ///< String "V" - UINT8 Value1; ///< Value - UINT8 DefaultPerfPresentCap; ///< Default Perf Present Cap - UINT8 MethodOpcode; ///< Method Opcode - UINT8 PpcLength; ///< Method Length - UINT8 PpcName_a__; ///< String "_" - UINT8 PpcName_c_P; ///< String "P" - UINT8 PpcName_d_P; ///< String "P" - UINT8 PpcName_b_C; ///< String "C" - UINT8 MethodFlags; ///< Method Flags - UINT8 ReturnOpcode; ///< Return Opcoce - UINT8 PpcName_e_P; ///< String "P" - UINT8 PpcName_f_P; ///< String "P" - UINT8 PpcName_c_C; ///< String "C" - UINT8 PpcName_b_V; ///< String "V" - -} PPC_HEADER_BODY; -#define PPC_HEADER_BODY_STRUCT_SIZE 19 // 19 Bytes -#define PPC_METHOD_LENGTH 11 // 11 Bytes - - -/*-------------------------------------------- - * AML code definition - * (PSD Header) - *-------------------------------------------- - */ -/// P-State Dependency Header -typedef struct _PSD_HEADER { - UINT8 NameOpcode; ///< Name Opcode - UINT8 PsdName_a__; ///< String "_" - UINT8 PsdName_a_P; ///< String "P" - UINT8 PsdName_a_S; ///< String "S" - UINT8 PsdName_a_D; ///< String "D" - UINT8 PkgOpcode; ///< Package Opcode - UINT8 PsdLength; ///< PSD Length - UINT8 Value1; ///< Value -} PSD_HEADER; -#define PSD_HEADER_STRUCT_SIZE 8 // 8 Bytes - -/*-------------------------------------------- - * AML code definition - * (PSD Body) - *-------------------------------------------- - */ -/// P-State Dependency Body -typedef struct _PSD_BODY { - UINT8 PkgOpcode; ///< Package Opcode - UINT8 PkgLength; ///< Package Length - UINT8 NumOfEntries; ///< Number of Entries - UINT8 BytePrefixOpcode1; ///< Prefix Opcode1 in Byte - UINT8 PsdNumOfEntries; ///< PSD Number of Entries - UINT8 BytePrefixOpcode2; ///< Prefix Opcode2 in Byte - UINT8 PsdRevision; ///< PSD Revision - UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 in DWord - UINT32 DependencyDomain; ///< Dependency Domain - UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 in DWord - UINT32 CoordinationType; ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL) - UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 in DWord - UINT32 NumOfProcessors; ///< Number of Processors -} PSD_BODY; -#define PSD_BODY_STRUCT_SIZE 22 // 22 Bytes - -//---------------------------------------------------------------------------- -// WHEA TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- - -/// HEST MCE TABLE -typedef struct _AMD_HEST_MCE_TABLE { - UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_MCE structure. - UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into - UINT32 GlobCapInitDataMSD; ///< the machine check global capability register(MCG_CAP). - UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will program into - UINT32 GlobCtrlInitDataMSD; ///< the machine check global control register(MCG_CTL). - UINT8 NumHWBanks; ///< The number of hardware error reporting banks. - UINT8 Rsvd[7]; ///< reserve 7 bytes as spec's required -} AMD_HEST_MCE_TABLE; - -/// HEST CMC TABLE -typedef struct _AMD_HEST_CMC_TABLE { - UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_CMC structure. - UINT8 NumHWBanks; ///< The number of hardware error reporting banks. - UINT8 Rsvd[3]; ///< reserve 3 bytes as spec's required -} AMD_HEST_CMC_TABLE; - -/// HEST BANK -typedef struct _AMD_HEST_BANK { - UINT8 BankNum; ///< Zero-based index identifies the machine check error bank. - UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check bank - ///< is to be cleared during system initialization. - UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register - UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be - ///< modified by the OS. If the bit for the associated parameter is - ///< set, the parameter is writable by the OS. - UINT32 CtrlRegMSRAddr; ///< Address of the hardware bank's control MSR. Ignored if zero. - - UINT32 CtrlInitDataLSD; ///< This is the value the OS will program into the machine check - UINT32 CtrlInitDataMSD; ///< bank's control register - UINT32 StatRegMSRAddr; ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero. - UINT32 AddrRegMSRAddr; ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero. - UINT32 MiscRegMSRAddr; ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero. -} AMD_HEST_BANK; - -/// Initial data of AMD_HEST_BANK -typedef struct _AMD_HEST_BANK_INIT_DATA { - UINT32 CtrlInitDataLSD; ///< Initial data of CtrlInitDataLSD - UINT32 CtrlInitDataMSD; ///< Initial data of CtrlInitDataMSD - UINT32 CtrlRegMSRAddr; ///< Initial data of CtrlRegMSRAddr - UINT32 StatRegMSRAddr; ///< Initial data of StatRegMSRAddr - UINT32 AddrRegMSRAddr; ///< Initial data of AddrRegMSRAddr - UINT32 MiscRegMSRAddr; ///< Initial data of MiscRegMSRAddr -} AMD_HEST_BANK_INIT_DATA; - -/// MSR179 Global Machine Check Capabilities data struct -typedef struct _MSR_MCG_CAP_STRUCT { - UINT64 Count:8; ///< Indicates the number of - ///< error-reporting banks visible to each core - UINT64 McgCtlP:1; ///< 1=The machine check control registers - UINT64 Rsvd:55; ///< reserved -} MSR_MCG_CAP_STRUCT; - -/// Initial data of WHEA -typedef struct _AMD_WHEA_INIT_DATA { - UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into the machine - UINT32 GlobCapInitDataMSD; ///< Check global capability register - UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will grogram into the machine - UINT32 GlobCtrlInitDataMSD; ///< Check global control register - UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check - ///< bank is to be cleared during system initialization - UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register - UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be - ///< modified by the OS. If the bit for the associated parameter is - ///< set, the parameter is writable by the OS. - UINT8 HestBankNum; ///< Number of HEST Bank - AMD_HEST_BANK_INIT_DATA *HestBankInitData; ///< Pointer to Initial data of HEST Bank -} AMD_WHEA_INIT_DATA; - -//---------------------------------------------------------------------------- -// DMI TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// DMI brand information -typedef struct { - UINT16 String1:4; ///< String1 - UINT16 String2:4; ///< String2 - UINT16 Model:7; ///< Model - UINT16 Pg:1; ///< Page -} BRAND_ID; - -/// DMI processor information -typedef struct { - UINT8 ExtendedFamily; ///< Extended Family - UINT8 ExtendedModel; ///< Extended Model - UINT8 BaseFamily; ///< Base Family - UINT8 BaseModel; ///< Base Model - UINT8 Stepping; ///< Stepping - UINT8 PackageType; ///< PackageType - BRAND_ID BrandId; ///< BrandId which contains information about String1, String2, Model and Page - UINT8 TotalCoreNumber; ///< Number of total cores - UINT8 EnabledCoreNumber; ///< Number of enabled cores - UINT8 ProcUpgrade; ///< ProcUpdrade - UINT32 L1CacheSize; ///< L1 cache size - UINT32 L2CacheSize; ///< L2 cache size -} CPU_TYPE_INFO; - -/// A structure containing processor name string and -/// the value that should be provide to DMI type 4 processor family -typedef struct { - IN CONST CHAR8 *Stringstart; ///< The literal string - IN UINT8 T4ProcFamilySetting; ///< The value set to DMI type 4 processor family -} CPU_T4_PROC_FAMILY; - -/// DMI ECC information -typedef struct { - BOOLEAN EccCapable; ///< ECC Capable - UINT8 PartitionRowPosition; ///< DMI Type 20 offset 10h: Partition Row Position - ///< 2 - single channel memory - ///< 0 - dual channel memory -} CPU_GET_MEM_INFO; - -/* Transfer vectors for DMI family specific routines */ -typedef VOID OPTION_DMI_GET_CPU_INFO ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef VOID OPTION_DMI_GET_PROC_FAMILY ( - IN OUT UINT8 *T4ProcFamily, - IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, - IN CPU_TYPE_INFO *CpuInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef UINT8 OPTION_DMI_GET_VOLTAGE ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef UINT16 OPTION_DMI_GET_MAX_SPEED ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef UINT16 OPTION_DMI_GET_EXT_CLOCK ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef VOID OPTION_DMI_GET_MEM_INFO ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Brand table entry format -typedef struct { - UINT8 PackageType; ///< Package type - UINT8 PgOfBrandId; ///< Page - UINT8 NumberOfCores; ///< Number of cores - UINT8 String1ofBrandId; ///< String1 - UINT8 ValueSetToDmiTable; ///< The value which will should be set to DMI table -} DMI_BRAND_ENTRY; - -/// Family specific data table structure -struct _PROC_FAMILY_TABLE { - UINT64 ProcessorFamily; ///< processor - OPTION_DMI_GET_CPU_INFO *DmiGetCpuInfo; ///< transfer vectors - OPTION_DMI_GET_PROC_FAMILY *DmiGetT4ProcFamily; ///< Get DMI type 4 processor family information - OPTION_DMI_GET_VOLTAGE *DmiGetVoltage; ///< vector for reading voltage - OPTION_DMI_GET_MAX_SPEED *DmiGetMaxSpeed; ///< vector for reading speed - OPTION_DMI_GET_EXT_CLOCK *DmiGetExtClock; ///< vector for reading external clock speed - OPTION_DMI_GET_MEM_INFO *DmiGetMemInfo; ///< Get memory information - UINT8 LenBrandList; ///< size of brand table - CONST DMI_BRAND_ENTRY *DmiBrandList; ///< translate brand info to DMI identifier -}; - -//---------------------------------------------------------------------------- -// SLIT TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// Format for SRAT Header -typedef struct { - UINT8 Sign[4]; ///< Signature - UINT32 TableLength; ///< Table Length - UINT8 Revision; ///< Revision - UINT8 Checksum; ///< Checksum - UINT8 OemId[6]; ///< OEM ID - UINT8 OemTableId[8]; ///< OEM Tabled ID - UINT32 OemRev; ///< OEM Revision - UINT8 CreatorId[4]; ///< Creator ID - UINT32 CreatorRev; ///< Creator Revision -} ACPI_TABLE_HEADER; - -//---------------------------------------------------------------------------- -// SRAT TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// Format for SRAT Header -typedef struct _CPU_SRAT_HEADER { - UINT8 Sign[4]; ///< Signature - UINT32 TableLength; ///< Table Length - UINT8 Revision; ///< Revision - UINT8 Checksum; ///< Checksum - UINT8 OemId[6]; ///< OEM ID - UINT8 OemTableId[8]; ///< OEM Tabled ID - UINT32 OemRev; ///< OEM Revision - UINT8 CreatorId[4]; ///< Creator ID - UINT32 CreatorRev; ///< Creator Revision - UINT32 TableRev; ///< Table Revision - UINT8 Reserved[8]; ///< Reserved -} CPU_SRAT_HEADER; - - -/// Format for SRAT APIC Affinity Entry -typedef struct _CPU_SRAT_APIC_ENTRY { - UINT8 Type; ///< Type - UINT8 Length; ///< Length - UINT8 Domain; ///< Domain - UINT8 ApicId; ///< Apic ID - UINT32 Flags; ///< Flags - UINT8 LSApicEid; ///< Local SAPIC EID - UINT8 Reserved[7]; ///< Reserved -} CPU_SRAT_APIC_ENTRY; - - -/// Format for SRAT Memory Affinity Entry -typedef struct _CPU_SRAT_MEMORY_ENTRY { - UINT8 Type; ///< 0: Memory affinity = 1 - UINT8 Length; ///< 1: Length = 40 bytes - UINT32 Domain; ///< 2: Proximity domain - UINT8 Reserved1[2]; ///< 6: Reserved - UINT32 BaseAddrLow; ///< 8: Low 32bits address base - UINT32 BaseAddrHigh; ///< 12: High 32bits address base - UINT32 LengthAddrLow; ///< 16: Low 32bits address limit - UINT32 LengthAddrHigh; ///< 20: High 32bits address limit - UINT8 Reserved2[4]; ///< 24: Memory Type - UINT32 Flags; ///< 28: Flags - UINT8 Reserved3[8]; ///< 32: Reserved -} CPU_SRAT_MEMORY_ENTRY; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -AmdCpuLate ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ); - -AGESA_STATUS -CreateAcpiWhea ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ); - -AGESA_STATUS -CreateDmiRecords ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT DMI_INFO **DmiTable - ); - -AGESA_STATUS -GetType4Type7Info ( - IN AP_EXE_PARAMS *ApExeParams - ); - -VOID -DmiGetT4ProcFamilyFromBrandId ( - IN OUT UINT8 *T4ProcFamily, - IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, - IN CPU_TYPE_INFO *CpuInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetNameString ( - IN OUT CHAR8 *String, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -IsSourceStrContainTargetStr ( - IN OUT CHAR8 *SourceStr, - IN OUT CONST CHAR8 *TargetStr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -CreateAcpiSrat ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ); - -AGESA_STATUS -CreateAcpiSlit ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ); - -VOID -ChecksumAcpiTable ( - IN OUT ACPI_TABLE_HEADER *Table, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -RunLateApTaskOnAllAPs ( - IN AP_EXE_PARAMS *ApParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -RunLateApTaskOnAllCore0s ( - IN AP_EXE_PARAMS *ApParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_LATE_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c deleted file mode 100644 index d76a372630..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c +++ /dev/null @@ -1,422 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Microcode Patch Related Functions - * - * Contains code to program a microcode into the CPU - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*--------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *--------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuEarlyInit.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_CPUMICROCODEPATCH_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -typedef union { - UINT64 RawData; - PATCH_LOADER_MSR BitFields; -} PATCH_LOADER; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -LoadMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LoadMicrocodePatchAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/* -----------------------------------------------------------------------------*/ -/** - * Update microcode patch in current processor. - * - * Then reads the patch id, and compare it to the expected, in the Microprocessor - * patch block. - * - * @param[in] StdHeader - Config handle for library and services. - * - * @retval TRUE - Patch Loaded Successfully. - * @retval FALSE - Patch Did Not Get Loaded. - * - */ -BOOLEAN -LoadMicrocodePatch ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PatchNumber; - UINT8 TotalPatches; - UINT16 ProcessorEquivalentId; - BOOLEAN Status; - MICROCODE_PATCH **MicrocodePatchPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - Status = FALSE; - - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - // Get the patch pointer - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (const VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader); - - IDS_OPTION_HOOK (IDS_UCODE, &TotalPatches, StdHeader); - - // Get the processor microcode path equivalent ID - if (GetPatchEquivalentId (&ProcessorEquivalentId, StdHeader)) { - // parse the patch table to see if we have one for the current cpu - for (PatchNumber = 0; PatchNumber < TotalPatches; PatchNumber++) { - if (ValidateMicrocode (MicrocodePatchPtr[PatchNumber], ProcessorEquivalentId, StdHeader)) { - if (LoadMicrocode (MicrocodePatchPtr[PatchNumber], StdHeader)) { - Status = TRUE; - } else { - PutEventLog (AGESA_ERROR, - CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED, - 0, 0, 0, 0, StdHeader); - } - break; // Once we find a microcode patch that matches the processor, exit the for loop - } - } - } - } - return Status; -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * LoadMicrocode - * - * Update microcode patch in current processor, then reads the - * patch id, and compare it to the expected, in the Microprocessor - * patch block. - * - * @param[in] MicrocodePatchPtr - Pointer to Microcode Patch. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval TRUE - Patch Loaded Successfully. - * @retval FALSE - Patch Did Not Get Loaded. - * - */ -BOOLEAN -STATIC -LoadMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MicrocodeVersion; - PATCH_LOADER PatchLoaderMsr; - - // Load microcode patch into CPU - PatchLoaderMsr.RawData = (UINT64) (UINTN) MicrocodePatchPtr; - PatchLoaderMsr.BitFields.SBZ = 0; - LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader); - - // Do ucode patch Authentication - // Read microcode version back from CPU, determine if - // it is the same patch level as contained in the source - // microprocessor patch block passed in - GetMicrocodeVersion (&MicrocodeVersion, StdHeader); - if (MicrocodeVersion == MicrocodePatchPtr->PatchID) { - return (TRUE); - } else { - return (FALSE); - } -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * GetPatchEquivalentId - * - * Return the equivalent ID for microcode patching - * - * @param[in,out] ProcessorEquivalentId - Pointer to Processor Equivalent ID table. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval TRUE - ID Found. - * @retval FALSE - ID Not Found. - * - */ -BOOLEAN -GetPatchEquivalentId ( - IN OUT UINT16 *ProcessorEquivalentId, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 EquivalencyEntries; - UINT16 ProcessorRevisionId; - UINT16 *MicrocodeEquivalenceTable; - CPUID_DATA CpuIdData; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - // - // compute the processor revision ID - // - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuIdData, StdHeader); - // high byte contains extended model and extended family - ProcessorRevisionId = (UINT16) ((CpuIdData.EAX_Reg & (CPU_EMODEL | CPU_EFAMILY)) >> 8); - // low byte contains model and family - ProcessorRevisionId |= (CpuIdData.EAX_Reg & (CPU_STEPPING | CPU_MODEL)); - - // - // find the equivalent ID for microcode purpose using the equivalence table - // - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - - FamilySpecificServices->GetMicrocodeEquivalenceTable (FamilySpecificServices, - (CONST VOID **) &MicrocodeEquivalenceTable, - &EquivalencyEntries, - StdHeader); - - // parse the equivalence table - for (i = 0; i < (EquivalencyEntries * 2); i += 2) { - // check for equivalence - if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) { - *ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1]; - return (TRUE); - } - } - // end of table reach, this processor is not supported - *ProcessorEquivalentId = 0x0000; - return (FALSE); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * ValidateMicrocode - * - * Determine if the microcode patch block, currently pointed to - * is valid, and is appropriate for the current processor - - * @param[in] MicrocodePatchPtr - Pointer to Microcode Patch. - * @param[in] ProcessorEquivalentId - Pointer to Processor Equivalent ID table. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval TRUE - Patch Found. - * @retval FALSE - Patch Not Found. - * - */ -BOOLEAN -ValidateMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN UINT16 ProcessorEquivalentId, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Chipset1Matched; - BOOLEAN Chipset2Matched; - PCI_ADDR PciAddress; - UINT32 PciDeviceVidDid; - UINT8 PciDeviceRevision; - UINT8 DevCount; - UINT8 FunCount; - UINT32 Chipset1DeviceID; - UINT32 Chipset2DeviceID; - UINT8 MulitFunction; - - Chipset1Matched = FALSE; - Chipset2Matched = FALSE; - PciDeviceVidDid = 0; - PciDeviceRevision = 0; - Chipset1DeviceID = MicrocodePatchPtr->Chipset1DeviceID; - Chipset2DeviceID = MicrocodePatchPtr->Chipset2DeviceID; - MulitFunction = 0; - - // - // parse the supplied microcode to see if it is compatible with the processor - // - if (MicrocodePatchPtr->ProcessorRevisionID != ProcessorEquivalentId) { - return (FALSE); - } - - if (Chipset1DeviceID == 0) { - Chipset1Matched = TRUE; - } - if (Chipset2DeviceID == 0) { - Chipset2Matched = TRUE; - } - - if ((!Chipset1Matched) || (!Chipset2Matched)) { - // - // Scan all PCI devices in Bus 0, try to find out matched case. - // - for (DevCount = 0; DevCount < 32; DevCount++) { - for (FunCount = 0; FunCount < 8; FunCount++) { - PciAddress.AddressValue = MAKE_SBDFO (0, 0, DevCount, FunCount, 0); - LibAmdPciRead (AccessWidth32, PciAddress, &PciDeviceVidDid, StdHeader); - if (PciDeviceVidDid == 0xFFFFFFFF) { - if (FunCount == 0) { - break; - } else { - continue; - } - } - PciAddress.Address.Register = 0x8; - LibAmdPciRead (AccessWidth8, PciAddress, &PciDeviceRevision, StdHeader); - if ((!Chipset1Matched) && (PciDeviceVidDid == Chipset1DeviceID)) { - if (PciDeviceRevision == MicrocodePatchPtr->Chipset1RevisionID) { - Chipset1Matched = TRUE; - } - } - if ((!Chipset2Matched) && (PciDeviceVidDid == Chipset2DeviceID)) { - if (PciDeviceRevision == MicrocodePatchPtr->Chipset2RevisionID) { - Chipset2Matched = TRUE; - } - } - if (Chipset1Matched && Chipset2Matched) { - break; - } - // - // Check multi-function. If it doesen't exist, we don't have to loop functions to 7. - // - if (FunCount == 0) { - MulitFunction = 0; - PciAddress.Address.Register = 0xE; - LibAmdPciRead (AccessWidth8, PciAddress, &MulitFunction, StdHeader); - if ((MulitFunction & 0x80) == 0) { - break; - } - } - } // end FunCount for loop. - - if (Chipset1Matched && Chipset2Matched) { - break; - } - } // end DevCount for loop. - } - - return (Chipset1Matched && Chipset2Matched); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * - * GetMicrocodeVersion - * - * Return the version of the currently loaded microcode patch, if any. - * Read from the patch level MSR, return the value in eax. If no patch - * has been loaded, 0 will be returned. - * - * @param[out] pMicrocodeVersion - Pointer to Microcode Version. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -GetMicrocodeVersion ( - OUT UINT32 *pMicrocodeVersion, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrData; - - MsrData = 0; - LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrData, StdHeader); - - *pMicrocodeVersion = (UINT32) MsrData; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Update microcode patch in current processor. - * - * This function acts as a wrapper for calling the LoadMicrocodePatch - * routine at AmdInitEarly. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -LoadMicrocodePatchAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader); - LoadMicrocodePatch (StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPage.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPage.h deleted file mode 100644 index ca7410468e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPage.h +++ /dev/null @@ -1,60 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for CPU Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page cpumain CPU Component Documentation - * - * Additional documentation for the CPU component consists of - * - * - Maintenance Guides: - * - @subpage cpuimplfss "CPU Family Specific Services Implementation Guide" - * - @subpage regtableimpl "Register Table Implementation Guide" - * - @subpage cpufeatimpl "CPU Generic Feature Implementation Guide" - * - @subpage ucodeflag "Microcode Patches Signature Guide" - * - add here >>> - * - Design Guides: - * - add here >>> - * - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c deleted file mode 100644 index 466e0c492b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.c +++ /dev/null @@ -1,493 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU POST API, and related functions. - * - * Contains code that initialized the CPU after memory init. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - **************************************************************************** - * AMD Generic Encapsulated Software Architecture - * - * Description: cpuPostInit.c - Cpu POST Initialization Functions. - * - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Options.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "heapManager.h" -#include "cpuServices.h" -#include "cpuFeatures.h" -#include "GeneralServices.h" -#include "cpuPostInit.h" -#include "cpuPstateTables.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_CPUPOSTINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -SyncVariableMTRR ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -extern -VOID -ExecuteWbinvdInstruction ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -PstateCreateHeapInfo ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs CPU related initialization at the POST entry point - * - * This function performs a large list of initialization items. These items - * include: - * - * -1 AP MTRR sync - * -2 feature leveling - * -3 P-state data gather - * -4 P-state leveling - * -5 AP cache breakdown & release - * - * @param[in] StdHeader Config handle for library and services - * @param[in] PlatformConfig Config handle for platform specific information - * - * @retval AGESA_SUCCESS - * - */ -AGESA_STATUS -AmdCpuPost ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS CalledStatus; - - AgesaStatus = AGESA_SUCCESS; - // - // Sync variable MTRR - // - AGESA_TESTPOINT (TpProcCpuApMtrrSync, StdHeader); - SyncVariableMTRR (StdHeader); - - AGESA_TESTPOINT (TpProcCpuPostFeatureInit, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after AP MTRR sync\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_POST_MTRR_SYNC, PlatformConfig, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - // - // Feature Leveling - // - AGESA_TESTPOINT (TpProcCpuFeatureLeveling, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Perform feature leveling\n"); - FeatureLeveling (StdHeader); - // - // P-state Gathered and set heap info - // - IDS_HDT_CONSOLE (CPU_TRACE, " Create P-state info in the heap\n"); - PstateCreateHeapInfo (PlatformConfig, StdHeader); - - // Set TscFreqSel at the rate specified by the core P0 after core frequency leveling. - SetCoresTscFreqSel (StdHeader); - - // Dispatch CPU features before relinquishing control of APs - AGESA_TESTPOINT (TpProcCpuBeforeRelinquishAPsFeatureInit, StdHeader); - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features before Relinquishing control of APs\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_BEFORE_RELINQUISH_AP, PlatformConfig, StdHeader); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - - // Relinquish control of all APs to IBV. - IDS_HDT_CONSOLE (CPU_TRACE, " Relinquish control of APs\n"); - RelinquishControlOfAllAPs (StdHeader); - - return (AgesaStatus); -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the address in system DRAM that should be used for p-state data - * gather and leveling. - * - * @param[out] Ptr Address to utilize - * @param[in] StdHeader Config handle for library and services - * - * @retval AGESA_SUCCESS - * - */ -AGESA_STATUS -GetPstateGatherDataAddressAtPost ( - OUT UINT64 **Ptr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 AddressValue; - - AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR; - - *Ptr = (UINT64 *)(intptr_t)(AddressValue); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * AP task to sync memory subsystem MSRs with the BSC - * - * This function processes a list of MSRs and the BSC's current values for those - * MSRs. This will allow the APs to see system RAM. - * - * @param[in] MtrrTable Memory related MSR table - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -SyncAllApMtrrToBsc ( - IN VOID *MtrrTable, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - - for (i = 0; ((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress != 0; i++) { - LibAmdMsrWrite (((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress, - &((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterValue, - StdHeader); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Creates p-state information on the heap - * - * This function gathers p-state information from all processors in the system, - * determines a level set of p-states, and places that information into the - * heap. This heap data will be used by GenerateSsdt to generate the - * final _PSS and XPSS objects. - * - * @param[in] PlatformConfig Pointer to runtime configuration options - * @param[in] StdHeader Config handle for library and services - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_ERROR CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE - */ -AGESA_STATUS -PstateCreateHeapInfo ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS AgesaStatus; - S_CPU_AMD_PSTATE *PStateBufferPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT8 *PStateBufferPtrInHeap; - - ASSERT (IsBsp (StdHeader, &AgesaStatus)); - - // - //Get proper address for gather data pool address - //Zero P-state gather data pool - // - GetPstateGatherDataAddressAtPost ((UINT64 **)&PStateBufferPtr, StdHeader); - LibAmdMemFill (PStateBufferPtr, 0, sizeof (S_CPU_AMD_PSTATE), StdHeader); - - // - //Get all the CPUs P-States and fill the PStateBufferPtr for each core - // - AgesaStatus = PStateGatherData (PlatformConfig, PStateBufferPtr, StdHeader); - if (AgesaStatus != AGESA_SUCCESS) { - return AgesaStatus; - } - - // - //Do Pstate Leveling for each core if needed. - // - AgesaStatus = PStateLeveling (PStateBufferPtr, StdHeader); - - // - //Create Heap and store p-state data for ACPI table in CpuLate - // - AllocHeapParams.RequestedBufferSize = PStateBufferPtr->SizeOfBytes; - AllocHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, StdHeader); - if (AgesaStatus == AGESA_SUCCESS) { - // - // Zero Buffer - // - PStateBufferPtrInHeap = (UINT8 *) AllocHeapParams.BufferPtr; - LibAmdMemFill (PStateBufferPtrInHeap, 0, PStateBufferPtr->SizeOfBytes, StdHeader); - LibAmdMemCopy (PStateBufferPtrInHeap, PStateBufferPtr, PStateBufferPtr->SizeOfBytes, StdHeader); - - } else { - PutEventLog (AGESA_ERROR, - CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE, - 0, 0, 0, 0, StdHeader); - } - - return AgesaStatus; -} - -VOID -SyncApMsrsToBsc ( - IN OUT BSC_AP_MSR_SYNC *ApMsrSync, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - UINT16 i; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AGESA_STATUS IgnoredSts; - - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - // - //Sync all MTRR settings with BSP - // - for (i = 0; ApMsrSync[i].RegisterAddress != 0; i++) { - LibAmdMsrRead (ApMsrSync[i].RegisterAddress, &ApMsrSync[i].RegisterValue, StdHeader); - } - - TaskPtr.FuncAddress.PfApTaskI = SyncAllApMtrrToBsc; - TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((((sizeof (BSC_AP_MSR_SYNC)) * i) + 4) >> 2); - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataPtr = ApMsrSync; - TaskPtr.DataTransfer.DataTransferFlags = 0; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * SyncVariableMTRR - * - * Sync variable MTRR - * - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -SyncVariableMTRR ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BSC_AP_MSR_SYNC ApMsrSync[20]; - - ApMsrSync[0].RegisterAddress = SYS_CFG; - ApMsrSync[1].RegisterAddress = TOP_MEM; - ApMsrSync[2].RegisterAddress = TOP_MEM2; - ApMsrSync[3].RegisterAddress = 0x200; - ApMsrSync[4].RegisterAddress = 0x201; - ApMsrSync[5].RegisterAddress = 0x202; - ApMsrSync[6].RegisterAddress = 0x203; - ApMsrSync[7].RegisterAddress = 0x204; - ApMsrSync[8].RegisterAddress = 0x205; - ApMsrSync[9].RegisterAddress = 0x206; - ApMsrSync[10].RegisterAddress = 0x207; - ApMsrSync[11].RegisterAddress = 0x208; - ApMsrSync[12].RegisterAddress = 0x209; - ApMsrSync[13].RegisterAddress = 0x20A; - ApMsrSync[14].RegisterAddress = 0x20B; - ApMsrSync[15].RegisterAddress = 0xC0010016; - ApMsrSync[16].RegisterAddress = 0xC0010017; - ApMsrSync[17].RegisterAddress = 0xC0010018; - ApMsrSync[18].RegisterAddress = 0xC0010019; - ApMsrSync[19].RegisterAddress = 0; - SyncApMsrsToBsc (ApMsrSync, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * The function suppose to do any thing need to be done at the end of AmdInitPost. - * - * @param[in] StdHeader Config handle for library and services - * - * @retval AGESA_SUCCESS - * - */ -AGESA_STATUS -FinalizeAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // - // Execute wbinvd to ensure heap data in cache write back to memory. - // - ExecuteWbinvdInstruction (StdHeader); - - return AGESA_SUCCESS; -} -/*---------------------------------------------------------------------------------------*/ -/** - * Set TSC Frequency Selection. - * - * This function set TSC Frequency Selection. - * - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -SetTscFreqSel ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PSTATE_CPU_FAMILY_SERVICES *FamilyServices; - - FamilyServices = NULL; - - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - if (FamilyServices != NULL) { - FamilyServices->CpuSetTscFreqSel (FamilyServices, StdHeader); - } - -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set TSC Frequency Selection to all cores. - * - * This function set TscFreqSel to all cores in the system. - * - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -SetCoresTscFreqSel ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_TASK TaskPtr; - UINT32 BscSocket; - UINT32 Ignored; - UINT32 BscCoreNum; - UINT32 Core; - UINT32 Socket; - UINT32 NumberOfSockets; - UINT32 NumberOfCores; - AGESA_STATUS IgnoredSts; - - ASSERT (IsBsp (StdHeader, &IgnoredSts)); - - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); - NumberOfSockets = GetPlatformNumberOfSockets (); - - SetTscFreqSel (StdHeader); - - TaskPtr.FuncAddress.PfApTask = SetTscFreqSel; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.DataTransfer.DataPtr = NULL; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { - for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCoreNum)) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); - } - } - } - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.h deleted file mode 100644 index ba63768f88..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPostInit.h +++ /dev/null @@ -1,239 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Reset API, and related functions and structures. - * - * Contains code that initialized the CPU after early reset. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_POST_INIT_H_ -#define _CPU_POST_INIT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ -// Forward declaration needed for multi-structure mutual references -AGESA_FORWARD_DECLARATION (CPU_CFOH_FAMILY_SERVICES); - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -#define P_STATE_DATA_GATHER_TEMP_ADDR 0x200000 ///< Fixed the row data at 2M memory address. -#define GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR 0x200000 ///< Fixed the row data at 2M memory address. -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -//---------------------------------------------------------------------------- -// CPU FEATURE LEVELING TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// CPU FEATURE LIST -typedef struct { - UINT8 ABM:1; ///< byte 0 bit 0 - UINT8 AES:1; ///< byte 0 bit 1 - UINT8 AltMovCr8:1; ///< byte 0 bit 2 - UINT8 APIC:1; ///< byte 0 bit 3 - UINT8 AVX:1; ///< byte 0 bit 4 - UINT8 CLFSH:1; ///< byte 0 bit 5 - UINT8 CMOV:1; ///< byte 0 bit 6 - UINT8 CmpLegacy:1; ///< byte 0 bit 7 - UINT8 CMPXCHG8B:1; ///< byte 1 bit 0 - UINT8 CMPXCHG16B:1; ///< byte 1 bit 1 - UINT8 CVT16:1; ///< byte 1 bit 2 - UINT8 DE:1; ///< byte 1 bit 3 - UINT8 ExtApicSpace:1; ///< byte 1 bit 4 - UINT8 FFXSR:1; ///< byte 1 bit 5 - UINT8 FMA:1; ///< byte 1 bit 6 - UINT8 FMA4:1; ///< byte 1 bit 7 - UINT8 FPU:1; ///< byte 2 bit 0 - UINT8 FXSR:1; ///< byte 2 bit 1 - UINT8 HTT:1; ///< byte 2 bit 2 - UINT8 IBS:1; ///< byte 2 bit 3 - UINT8 LahfSahf:1; ///< byte 2 bit 4 - UINT8 LM:1; ///< byte 2 bit 5 - UINT8 LWP:1; ///< byte 2 bit 6 - UINT8 MCA:1; ///< byte 2 bit 7 - UINT8 MCE:1; ///< byte 3 bit 0 - UINT8 MisAlignSse:1; ///< byte 3 bit 1 - UINT8 MMX:1; ///< byte 3 bit 2 - UINT8 MmxExt:1; ///< byte 3 bit 3 - UINT8 Monitor:1; ///< byte 3 bit 4 - UINT8 MSR:1; ///< byte 3 bit 5 - UINT8 MTRR:1; ///< byte 3 bit 6 - UINT8 NodeId:1; ///< byte 3 bit 7 - UINT8 NX:1; ///< byte 4 bit 0 - UINT8 OSVW:1; ///< byte 4 bit 1 - UINT8 OSXSAVE:1; ///< byte 4 bit 2 - UINT8 PAE:1; ///< byte 4 bit 3 - UINT8 Page1GB:1; ///< byte 4 bit 4 - UINT8 PAT:1; ///< byte 4 bit 5 - UINT8 PCLMULQDQ:1; ///< byte 4 bit 6 - UINT8 PGE:1; ///< byte 4 bit 7 - UINT8 POPCNT:1; ///< byte 5 bit 0 - UINT8 PSE:1; ///< byte 5 bit 1 - UINT8 PSE36:1; ///< byte 5 bit 2 - UINT8 RDTSCP:1; ///< byte 5 bit 3 - UINT8 SKINIT:1; ///< byte 5 bit 4 - UINT8 SSE:1; ///< byte 5 bit 5 - UINT8 SSE2:1; ///< byte 5 bit 6 - UINT8 SSE3:1; ///< byte 5 bit 7 - UINT8 SSE4A:1; ///< byte 6 bit 0 - UINT8 SSE41:1; ///< byte 6 bit 1 - UINT8 SSE42:1; ///< byte 6 bit 2 - UINT8 SSE5:1; ///< byte 6 bit 3 - UINT8 SSSE3:1; ///< byte 6 bit 4 - UINT8 SVM:1; ///< byte 6 bit 5 - UINT8 SysCallSysRet:1; ///< byte 6 bit 6 - UINT8 SysEnterSysExit:1; ///< byte 6 bit 7 - UINT8 TBM0:1; ///< byte 7 bit 0 - UINT8 TCE:1; ///< byte 7 bit 1 - UINT8 ThreeDNow:1; ///< byte 7 bit 2 - UINT8 ThreeDNowExt:1; ///< byte 7 bit 3 - UINT8 ThreeDNowPrefetch:1; ///< byte 7 bit 4 - UINT8 TimeStampCounter:1; ///< byte 7 bit 5 - UINT8 VME:1; ///< byte 7 bit 6 - UINT8 WDT:1; ///< byte 7 bit 7 - UINT8 X2APIC:1; ///< byte 8 bit 0 - UINT8 XOP:1; ///< byte 8 bit 1 - UINT8 XSAVE:1; ///< byte 8 bit 2 - UINT8 Reserve:5; ///< Reserved -} CPU_FEATURES_LIST; - -//---------------------------------------------------------------------------- -// POST INIT TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// BSC to AP MSR sync up -typedef struct { - UINT32 RegisterAddress; ///< MSR Address - UINT64 RegisterValue; ///< BSC's MSR Value -} BSC_AP_MSR_SYNC; - -/** - * Set Cache Flush On Halt Register. - * - * @CpuServiceInstances - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -typedef VOID (F_CPU_SET_CFOH_REG) ( - IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - /// Reference to a Method. -typedef F_CPU_SET_CFOH_REG *PF_CPU_SET_CFOH_REG; - -/** - * Provide the interface to the Cache Flush On Halt Family Specific Services. - * - * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). - * Each supported Family must provide an implementation for all methods in this interface, even if the - * implementation is a CommonReturn(). - */ -struct _CPU_CFOH_FAMILY_SERVICES { // See forward reference above - UINT16 Revision; ///< Interface version - // Public Methods. - PF_CPU_SET_CFOH_REG SetCacheFlushOnHaltRegister; ///< Method: Set Cache Flush On Halt register. -}; - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -// These are P U B L I C functions, used by IBVs -AGESA_STATUS -AmdCpuPost ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ); - -// These are P U B L I C functions, used by AGESA - -VOID -FeatureLeveling ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -CopyHeapToTempRamAtPost ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SyncApMsrsToBsc ( - IN OUT BSC_AP_MSR_SYNC *ApMsrSync, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -FinalizeAtPost ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SetCoresTscFreqSel ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GetPstateGatherDataAddressAtPost ( - OUT UINT64 **Ptr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SyncAllApMtrrToBsc ( - IN VOID *MtrrTable, - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _CPU_POST_INIT_H_ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmt.c deleted file mode 100644 index 8cfa58d5d9..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmt.c +++ /dev/null @@ -1,252 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Power Management functions. - * - * Contains code for doing early power management - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - **************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "OptionMultiSocket.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuPowerMgmtSystemTables.h" -#include "cpuServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_CPUPOWERMGMT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -PerformThisPmStep ( - IN VOID *Step, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ); - -VOID -STATIC -GoToMemInitPstateCore0 ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ); - -VOID -STATIC -GoToMemInitPstateCore ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform the "BIOS Requirements for P-State Initialization and Transitions." - * - * This is the generic arbiter code to be executed by the BSC. The system power - * management init tables will be traversed. This must be run by the system BSC - * only. - * - * @param[in] CpuEarlyParams Required input parameters for early CPU initialization - * @param[in] StdHeader Config handle for library and services - * - * @return Most severe AGESA_STATUS level that any system processor encountered - * - */ -AGESA_STATUS -PmInitializationAtEarly ( - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 NumberOfSystemWideSteps; - AP_TASK TaskPtr; - AGESA_STATUS ReturnCode; - WARM_RESET_REQUEST Request; - - // Determine the number of steps to perform - OptionMultiSocketConfiguration.GetNumberOfSystemPmSteps (&NumberOfSystemWideSteps, StdHeader); - - // Traverse the PM init table - TaskPtr.FuncAddress.PfApTaskIC = PerformThisPmStep; - TaskPtr.DataTransfer.DataSizeInDwords = 1; - TaskPtr.DataTransfer.DataPtr = &i; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - for (i = 0; i < NumberOfSystemWideSteps; ++i) { - IDS_HDT_CONSOLE (CPU_TRACE, " Perform PM init step %d\n", i); - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams); - } - - // GoToMemInitPstateCore0 only if there is no pending warm reset. - GetWarmResetFlag (StdHeader, &Request); - if (Request.RequestBit == FALSE) { - TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore0; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = PASS_EARLY_PARAMS; - IDS_HDT_CONSOLE (CPU_TRACE, " Transition all cores to POST P-state\n"); - OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams); - } - - // Retrieve/Process any errors - ReturnCode = OptionMultiSocketConfiguration.BscRetrievePmEarlyInitErrors (StdHeader); - - return (ReturnCode); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Performs the next step in the executing core 0's family specific power - * management table. - * - * This function determines if the input step is valid, and invokes the power - * management step if appropriate. This must be run by processor core 0s only. - * - * @param[in] Step Zero based step number - * @param[in] StdHeader Config handle for library and services - * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization - * - */ -VOID -STATIC -PerformThisPmStep ( - IN VOID *Step, - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ) -{ - UINT8 MyNumberOfSteps; - SYS_PM_TBL_STEP *FamilyTablePtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &FamilyTablePtr, &MyNumberOfSteps, StdHeader); - - if (*(UINT8 *)Step < MyNumberOfSteps) { - if (FamilyTablePtr[*(UINT8 *)Step].FuncPtr != NULL) { - if (!(BOOLEAN) (FamilyTablePtr[*(UINT8 *)Step].ExeFlags & PM_EXEFLAGS_WARM_ONLY) || - IsWarmReset (StdHeader)) { - FamilyTablePtr[*(UINT8 *)Step].FuncPtr (FamilySpecificServices, CpuEarlyParamsPtr, StdHeader); - } - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Transitions the executing processor to the desired P-state. - * - * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is - * run by all processor core 0s. - * - * @param[in] StdHeader Config handle for library and services - * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization - * - */ -VOID -STATIC -GoToMemInitPstateCore0 ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ) -{ - AP_TASK TaskPtr; - - TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE | PASS_EARLY_PARAMS; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Transitions the executing core to the desired P-state. - * - * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is - * run by all system cores. - * - * @param[in] StdHeader Config handle for library and services - * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization - * - */ -VOID -STATIC -GoToMemInitPstateCore ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, CpuEarlyParamsPtr->MemInitPState, (BOOLEAN) FALSE, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.c deleted file mode 100644 index 2e465f6b19..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.c +++ /dev/null @@ -1,570 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Power Management Multisocket Functions. - * - * Contains code for doing power management for multisocket CPUs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "cpuPowerMgmtSystemTables.h" -#include "cpuPowerMgmtMultiSocket.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -GetNextEvent ( - IN OUT VOID *EventLogEntryPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Multisocket BSC call to start all system core 0s to perform a standard AP_TASK. - * - * This function loops through all possible socket locations, starting core 0 of - * each populated socket to perform the passed in AP_TASK. After starting all - * other core 0s, the BSC will perform the AP_TASK as well. This must be run by - * the system BSC only. - * - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Config handle for library and services - * @param[in] ConfigParams AMD entry point's CPU parameter structure - * - */ -VOID -RunCodeOnAllSystemCore0sMulti ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ) -{ - UINT32 BscSocket; - UINT32 BscModule; - UINT32 BscCoreNum; - UINT8 Socket; - UINT32 NumberOfSockets; - AGESA_STATUS DummyStatus; - - ASSERT (IsBsp (StdHeader, &DummyStatus)); - - NumberOfSockets = GetPlatformNumberOfSockets (); - - IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus); - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (Socket != BscSocket) { - if (IsProcessorPresent (Socket, StdHeader)) { - ApUtilRunCodeOnSocketCore (Socket, 0, TaskPtr, StdHeader); - } - } - } - ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Multisocket BSC call to determine the maximum number of steps that any single - * processor needs to execute. - * - * This function loops through all possible socket locations, gathering the number - * of power management steps each populated socket requires, and returns the - * highest number. - * - * @param[out] NumSystemSteps Maximum number of system steps required - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -GetNumberOfSystemPmStepsPtrMulti ( - OUT UINT8 *NumSystemSteps, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumberOfSteps; - UINT32 NumberOfSockets; - UINT32 Socket; - SYS_PM_TBL_STEP *Ignored; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - NumberOfSockets = GetPlatformNumberOfSockets (); - *NumSystemSteps = 0; - - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &Ignored, &NumberOfSteps, StdHeader); - if (NumberOfSteps > *NumSystemSteps) { - *NumSystemSteps = NumberOfSteps; - } - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Multisocket call to determine the frequency that the northbridges must run. - * - * This function loops through all possible socket locations, comparing the - * maximum NB frequencies to determine the slowest. This function also - * determines if all coherent NB frequencies are equivalent. - * - * @param[in] NbPstate NB P-state number to check (0 = fastest) - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz - * @param[out] SystemNbCofDenominator NB frequency denominator for the system - * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent - * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE At least one processor has NbPstate enabled. - * @retval FALSE NbPstate is disabled on all CPUs - * - */ -BOOLEAN -GetSystemNbCofMulti ( - IN UINT32 NbPstate, - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *SystemNbCofNumerator, - OUT UINT32 *SystemNbCofDenominator, - OUT BOOLEAN *SystemNbCofsMatch, - OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT8 Module; - UINT32 CurrentNbCof; - UINT32 CurrentDivisor; - UINT32 CurrentFreq; - UINT32 LowFrequency; - UINT32 Ignored32; - BOOLEAN FirstCofNotFound; - BOOLEAN NbPstateDisabled; - BOOLEAN IsNbPstateEnabledOnAny; - PCI_ADDR PciAddress; - AGESA_STATUS Ignored; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - // Find the slowest NB COF in the system & whether or not all are equivalent - LowFrequency = 0xFFFFFFFF; - *SystemNbCofsMatch = TRUE; - *NbPstateIsEnabledOnAllCPUs = FALSE; - IsNbPstateEnabledOnAny = FALSE; - FirstCofNotFound = TRUE; - NbPstateDisabled = FALSE; - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored)) { - break; - } - } - if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, - PlatformConfig, - &PciAddress, - NbPstate, - &CurrentNbCof, - &CurrentDivisor, - &Ignored32, - StdHeader)) { - ASSERT (CurrentDivisor != 0); - CurrentFreq = (CurrentNbCof / CurrentDivisor); - if (FirstCofNotFound) { - *SystemNbCofNumerator = CurrentNbCof; - *SystemNbCofDenominator = CurrentDivisor; - LowFrequency = CurrentFreq; - IsNbPstateEnabledOnAny = TRUE; - if (!NbPstateDisabled) { - *NbPstateIsEnabledOnAllCPUs = TRUE; - } - FirstCofNotFound = FALSE; - } else { - if (CurrentFreq != LowFrequency) { - *SystemNbCofsMatch = FALSE; - if (CurrentFreq < LowFrequency) { - LowFrequency = CurrentFreq; - *SystemNbCofNumerator = CurrentNbCof; - *SystemNbCofDenominator = CurrentDivisor; - } - } - } - } else { - NbPstateDisabled = TRUE; - *NbPstateIsEnabledOnAllCPUs = FALSE; - } - } - } - return IsNbPstateEnabledOnAny; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Multisocket call to determine if the BIOS is responsible for updating the - * northbridge operating frequency and voltage. - * - * This function loops through all possible socket locations, checking whether - * any populated sockets require NB COF VID programming. - * - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE BIOS needs to set up NB frequency and voltage - * @retval FALSE BIOS does not need to set up NB frequency and voltage - * - */ -BOOLEAN -GetSystemNbCofVidUpdateMulti ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Module; - UINT32 Socket; - UINT32 NumberOfSockets; - BOOLEAN IgnoredBool; - BOOLEAN AtLeast1RequiresUpdate; - PCI_ADDR PciAddress; - AGESA_STATUS Ignored; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - NumberOfSockets = GetPlatformNumberOfSockets (); - - AtLeast1RequiresUpdate = FALSE; - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, (UINT8) Socket, Module, &PciAddress, &Ignored)) { - break; - } - } - if (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &IgnoredBool, StdHeader)) { - AtLeast1RequiresUpdate = TRUE; - break; - } - } - } - return AtLeast1RequiresUpdate; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Multisocket call to determine the most severe AGESA_STATUS return value after - * processing the power management initialization tables. - * - * This function loops through all possible socket locations, collecting any - * power management initialization errors that may have occurred. These errors - * are transferred from the core 0s of the socket in which the errors occurred - * to the BSC's heap. The BSC's heap is then searched for the most severe error - * that occurred, and returns it. This function must be called by the BSC only. - * - * @param[in] StdHeader Config handle for library and services - * - * @return The most severe error code from power management init - * - */ -AGESA_STATUS -GetEarlyPmErrorsMulti ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 i; - UINT32 BscSocket; - UINT32 BscModule; - UINT32 BscCoreNum; - UINT32 Socket; - UINT32 NumberOfSockets; - AP_TASK TaskPtr; - AGESA_EVENT EventLogEntry; - AGESA_STATUS ReturnCode; - AGESA_STATUS DummyStatus; - - ASSERT (IsBsp (StdHeader, &ReturnCode)); - - ReturnCode = AGESA_SUCCESS; - EventLogEntry.EventClass = AGESA_SUCCESS; - EventLogEntry.EventInfo = 0; - EventLogEntry.DataParam1 = 0; - EventLogEntry.DataParam2 = 0; - EventLogEntry.DataParam3 = 0; - EventLogEntry.DataParam4 = 0; - - NumberOfSockets = GetPlatformNumberOfSockets (); - IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus); - - TaskPtr.FuncAddress.PfApTaskI = GetNextEvent; - TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (AGESA_EVENT); - TaskPtr.DataTransfer.DataPtr = &EventLogEntry; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE | RETURN_PARAMS; - for (Socket = 0; Socket < NumberOfSockets; Socket++) { - if (Socket != BscSocket) { - if (IsProcessorPresent (Socket, StdHeader)) { - do { - ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8) 0, &TaskPtr, StdHeader); - if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) { - PutEventLog ( - EventLogEntry.EventClass, - EventLogEntry.EventInfo, - EventLogEntry.DataParam1, - EventLogEntry.DataParam2, - EventLogEntry.DataParam3, - EventLogEntry.DataParam4, - StdHeader - ); - } - } while (EventLogEntry.EventInfo != 0); - } - } - } - - for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) { - if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) { - if (EventLogEntry.EventClass > ReturnCode) { - ReturnCode = EventLogEntry.EventClass; - } - } - } - return (ReturnCode); -} - -/** - * Multisocket call to loop through all possible socket locations and Nb Pstates, - * comparing the NB frequencies to determine the slowest system and P0 frequency - * - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[out] MinSysNbFreq NB frequency numerator for the system in MHz - * @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz - * @param[in] StdHeader Config handle for library and services - */ -VOID -GetMinNbCofMulti ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *MinSysNbFreq, - OUT UINT32 *MinP0NbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 CurrMinFreq; - UINT32 CurrMaxFreq; - PCI_ADDR PciAddress; - AGESA_STATUS Ignored; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - *MinSysNbFreq = 0xFFFFFFFF; - *MinP0NbFreq = 0xFFFFFFFF; - - for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { - if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored )) { - break; - } - } - - - FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices, - PlatformConfig, - &PciAddress, - &CurrMinFreq, - &CurrMaxFreq, - StdHeader); - // Determine the slowest NB Pmin frequency - if (CurrMinFreq < *MinSysNbFreq) { - *MinSysNbFreq = CurrMinFreq; - } - - // Determine the slowest NB P0 frequency - if (CurrMaxFreq < *MinP0NbFreq) { - *MinP0NbFreq = CurrMaxFreq; - } - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get PCI Config Space Address for the current running core. - * - * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE The core is present, PCI Address valid - * @retval FALSE The core is not present, PCI Address not valid. - */ -BOOLEAN -GetCurrPciAddrMulti ( - OUT PCI_ADDR *PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Node; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - BOOLEAN Result; - AGESA_STATUS IgnoredSts; - - Result = TRUE; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - - ASSERT (Socket < MAX_SOCKETS); - ASSERT (Module < MAX_DIES); - - if (GetNodeId (Socket, Module, &Node, StdHeader)) { - // Socket is populated - PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - PciAddress->Address.Device = PciAddress->Address.Device + Node; - } else { - // Socket is not populated - PciAddress->AddressValue = ILLEGAL_SBDFO; - Result = FALSE; - } - - return Result; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Writes to all nodes on the executing core's socket. - * - * @param[in] PciAddress The Function and Register to update - * @param[in] Mask The bitwise AND mask to apply to the current register value - * @param[in] Data The bitwise OR mask to apply to the current register value - * @param[in] StdHeader Header for library and services. - * - */ -VOID -ModifyCurrSocketPciMulti ( - IN PCI_ADDR *PciAddress, - IN UINT32 Mask, - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 LocalPciRegister; - AGESA_STATUS AgesaStatus; - PCI_ADDR Reg; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus); - - for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) { - Reg.Address.Function = PciAddress->Address.Function; - Reg.Address.Register = PciAddress->Address.Register; - LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader); - LocalPciRegister &= Mask; - LocalPciRegister |= Data; - LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader); - } - } -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * AP task to return the next event log entry to the BSC. - * - * This function calls to the event log manager to retrieve the next error out - * of the heap. - * - * @param[out] EventLogEntryPtr The AP's next event log entry - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -STATIC -GetNextEvent ( - IN OUT VOID *EventLogEntryPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GetEventLog ((AGESA_EVENT *) EventLogEntryPtr, StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.h deleted file mode 100644 index 78f5ce74a9..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.h +++ /dev/null @@ -1,127 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Power Management Multisocket Functions. - * - * Contains code for doing power management for multisocket CPUs - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_POWER_MGMT_MULTI_SOCKET_H_ -#define _CPU_POWER_MGMT_MULTI_SOCKET_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -RunCodeOnAllSystemCore0sMulti ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ); - -VOID -GetNumberOfSystemPmStepsPtrMulti ( - OUT UINT8 *NumSystemSteps, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetSystemNbCofMulti ( - IN UINT32 NbPstate, - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *SystemNbCofNumerator, - OUT UINT32 *SystemNbCofDenominator, - OUT BOOLEAN *SystemNbCofsMatch, - OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetSystemNbCofVidUpdateMulti ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetMinNbCofMulti ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *MinSysNbFreq, - OUT UINT32 *MinP0NbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetCurrPciAddrMulti ( - OUT PCI_ADDR *PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -ModifyCurrSocketPciMulti ( - IN PCI_ADDR *PciAddress, - IN UINT32 Mask, - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GetEarlyPmErrorsMulti ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _CPU_POWER_MGMT_MULTI_SOCKET_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.c deleted file mode 100644 index 1d42943e5d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.c +++ /dev/null @@ -1,325 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Power Management Single Socket Functions. - * - * Contains code for doing power management for single socket CPU - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "cpuPowerMgmtSystemTables.h" -#include "cpuPowerMgmtSingleSocket.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Single socket BSC call to start all system core 0s to perform a standard AP_TASK. - * - * This function will simply invoke the task on the executing core. This must be - * run by the system BSC only. - * - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Config handle for library and services - * @param[in] ConfigParams AMD entry point's CPU parameter structure - * - */ -VOID -RunCodeOnAllSystemCore0sSingle ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ) -{ - ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Single socket BSC call to determine the maximum number of steps that any single - * processor needs to execute. - * - * This function simply returns the number of steps that the BSC needs. - * - * @param[out] NumSystemSteps Maximum number of system steps required - * @param[in] StdHeader Config handle for library and services - * - */ -VOID -GetNumberOfSystemPmStepsPtrSingle ( - OUT UINT8 *NumSystemSteps, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - SYS_PM_TBL_STEP *Ignored; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &Ignored, NumSystemSteps, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Single socket call to determine the frequency that the northbridges must run. - * - * This function simply returns the executing core's NB frequency, and that all - * NB frequencies are equivalent. - * - * @param[in] NbPstate NB P-state number to check (0 = fastest) - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz - * @param[out] SystemNbCofDenominator NB frequency denominator for the system - * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent - * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE At least one processor has NbPstate enabled. - * @retval FALSE NbPstate is disabled on all CPUs - * - */ -BOOLEAN -GetSystemNbCofSingle ( - IN UINT32 NbPstate, - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *SystemNbCofNumerator, - OUT UINT32 *SystemNbCofDenominator, - OUT BOOLEAN *SystemNbCofsMatch, - OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Ignored; - PCI_ADDR PciAddress; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - *SystemNbCofsMatch = TRUE; - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - *NbPstateIsEnabledOnAllCPUs = FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, - PlatformConfig, - &PciAddress, - NbPstate, - SystemNbCofNumerator, - SystemNbCofDenominator, - &Ignored, - StdHeader); - return *NbPstateIsEnabledOnAllCPUs; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Single socket call to determine if the BIOS is responsible for updating the - * northbridge operating frequency and voltage. - * - * This function simply returns whether or not the executing core needs NB COF - * VID programming. - * - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE BIOS needs to set up NB frequency and voltage - * @retval FALSE BIOS does not need to set up NB frequency and voltage - * - */ -BOOLEAN -GetSystemNbCofVidUpdateSingle ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN Ignored; - PCI_ADDR PciAddress; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - return (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &Ignored, StdHeader)); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Single socket call to determine the most severe AGESA_STATUS return value after - * processing the power management initialization tables. - * - * This function searches the event log for the most severe error and returns - * the status code. This function must be called by the BSC only. - * - * @param[in] StdHeader Config handle for library and services - * - * @return The most severe error code from power management init - * - */ -AGESA_STATUS -GetEarlyPmErrorsSingle ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 i; - AGESA_EVENT EventLogEntry; - AGESA_STATUS ReturnCode; - - ASSERT (IsBsp (StdHeader, &ReturnCode)); - - ReturnCode = AGESA_SUCCESS; - for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) { - if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) { - if (EventLogEntry.EventClass > ReturnCode) { - ReturnCode = EventLogEntry.EventClass; - } - } - } - - return (ReturnCode); -} - -/** - * Single socket call to loop through all Nb Pstates, comparing the NB frequencies - * to determine the slowest in the system. This routine also returns the NB P0 frequency. - * - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[out] MinSysNbFreq NB frequency numerator for the system in MHz - * @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz - * @param[in] StdHeader Config handle for library and services - */ -VOID -GetMinNbCofSingle ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *MinSysNbFreq, - OUT UINT32 *MinP0NbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices, - PlatformConfig, - &PciAddress, - MinSysNbFreq, - MinP0NbFreq, - StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get PCI Config Space Address for the current running core. - * - * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE The core is present, PCI Address valid - * @retval FALSE The core is not present, PCI Address not valid. - */ -BOOLEAN -GetCurrPciAddrSingle ( - OUT PCI_ADDR *PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - - return TRUE; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Writes to all nodes on the executing core's socket. - * - * @param[in] PciAddress The Function and Register to update - * @param[in] Mask The bitwise AND mask to apply to the current register value - * @param[in] Data The bitwise OR mask to apply to the current register value - * @param[in] StdHeader Header for library and services. - * - */ -VOID -ModifyCurrSocketPciSingle ( - IN PCI_ADDR *PciAddress, - IN UINT32 Mask, - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - PCI_ADDR Reg; - - Reg.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - Reg.Address.Function = PciAddress->Address.Function; - Reg.Address.Register = PciAddress->Address.Register; - LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader); - LocalPciRegister &= Mask; - LocalPciRegister |= Data; - LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader); -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.h deleted file mode 100644 index 11b71ffa64..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.h +++ /dev/null @@ -1,128 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Power Management Single Socket Functions. - * - * Contains code for doing power management for single socket CPU - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_POWER_MGMT_SINGLE_SOCKET_H_ -#define _CPU_POWER_MGMT_SINGLE_SOCKET_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -RunCodeOnAllSystemCore0sSingle ( - IN AP_TASK *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ); - -VOID -GetNumberOfSystemPmStepsPtrSingle ( - OUT UINT8 *NumSystemSteps, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetSystemNbCofSingle ( - IN UINT32 NbPstate, - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *SystemNbCofNumerator, - OUT UINT32 *SystemNbCofDenominator, - OUT BOOLEAN *SystemNbCofsMatch, - OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetSystemNbCofVidUpdateSingle ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetMinNbCofSingle ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *MinSysNbFreq, - OUT UINT32 *MinP0NbFreq, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetCurrPciAddrSingle ( - OUT PCI_ADDR *PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -ModifyCurrSocketPciSingle ( - IN PCI_ADDR *PciAddress, - IN UINT32 Mask, - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GetEarlyPmErrorsSingle ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_POWER_MGMT_SINGLE_SOCKET_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSystemTables.h deleted file mode 100644 index b4002365af..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPowerMgmtSystemTables.h +++ /dev/null @@ -1,93 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Power Management Table declarations. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_POWER_MGMT_SYSTEM_TABLES_H_ -#define _CPU_POWER_MGMT_SYSTEM_TABLES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -#define PM_EXEFLAGS_WARM_ONLY 0x00000001 /* Skip step if set && cold reset */ -#define PM_EXEFLAGS_NOT_ON_S3 0x00000002 /* Skip step if S3 resume */ -#define PM_EXEFLAGS_SYSTEM_TASK 0x00000004 /* Future use */ -#define PM_EXEFLAGS_SERIAL_EXE 0x00000008 /* BSC will wait for remote core 0 to complete the step*/ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -typedef VOID F_PM_STEP_FUNCTION ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/// Reference to a Method. -typedef F_PM_STEP_FUNCTION *PF_PM_STEP_FUNCTION; - - -/// A structure representing a step in a power management -/// initialization process to be invoked at AmdInitEarly -typedef struct { - UINT32 ExeFlags; ///< Execution flags - PF_PM_STEP_FUNCTION FuncPtr; ///< Function pointer -} SYS_PM_TBL_STEP; - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - - -#endif // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h deleted file mode 100644 index e0959fcb8f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h +++ /dev/null @@ -1,409 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Register Table Related Functions - * - * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 60539 $ @e \$Date: 2011-10-17 17:11:05 -0600 (Mon, 17 Oct 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_REGISTERS_H_ -#define _CPU_REGISTERS_H_ - -#include "cpuFamRegisters.h" -/* - *-------------------------------------------------------------- - * - * M O D U L E S U S E D - * - *--------------------------------------------------------------- - */ - -/* - *-------------------------------------------------------------- - * - * D E F I N I T I O N S / M A C R O S - * - *--------------------------------------------------------------- - */ - -#define BIT0 0x0000000000000001ull -#define BIT1 0x0000000000000002ull -#define BIT2 0x0000000000000004ull -#define BIT3 0x0000000000000008ull -#define BIT4 0x0000000000000010ull -#define BIT5 0x0000000000000020ull -#define BIT6 0x0000000000000040ull -#define BIT7 0x0000000000000080ull -#define BIT8 0x0000000000000100ull -#define BIT9 0x0000000000000200ull -#define BIT10 0x0000000000000400ull -#define BIT11 0x0000000000000800ull -#define BIT12 0x0000000000001000ull -#define BIT13 0x0000000000002000ull -#define BIT14 0x0000000000004000ull -#define BIT15 0x0000000000008000ull -#define BIT16 0x0000000000010000ull -#define BIT17 0x0000000000020000ull -#define BIT18 0x0000000000040000ull -#define BIT19 0x0000000000080000ull -#define BIT20 0x0000000000100000ull -#define BIT21 0x0000000000200000ull -#define BIT22 0x0000000000400000ull -#define BIT23 0x0000000000800000ull -#define BIT24 0x0000000001000000ull -#define BIT25 0x0000000002000000ull -#define BIT26 0x0000000004000000ull -#define BIT27 0x0000000008000000ull -#define BIT28 0x0000000010000000ull -#define BIT29 0x0000000020000000ull -#define BIT30 0x0000000040000000ull -#define BIT31 0x0000000080000000ull -#define BIT32 0x0000000100000000ull -#define BIT33 0x0000000200000000ull -#define BIT34 0x0000000400000000ull -#define BIT35 0x0000000800000000ull -#define BIT36 0x0000001000000000ull -#define BIT37 0x0000002000000000ull -#define BIT38 0x0000004000000000ull -#define BIT39 0x0000008000000000ull -#define BIT40 0x0000010000000000ull -#define BIT41 0x0000020000000000ull -#define BIT42 0x0000040000000000ull -#define BIT43 0x0000080000000000ull -#define BIT44 0x0000100000000000ull -#define BIT45 0x0000200000000000ull -#define BIT46 0x0000400000000000ull -#define BIT47 0x0000800000000000ull -#define BIT48 0x0001000000000000ull -#define BIT49 0x0002000000000000ull -#define BIT50 0x0004000000000000ull -#define BIT51 0x0008000000000000ull -#define BIT52 0x0010000000000000ull -#define BIT53 0x0020000000000000ull -#define BIT54 0x0040000000000000ull -#define BIT55 0x0080000000000000ull -#define BIT56 0x0100000000000000ull -#define BIT57 0x0200000000000000ull -#define BIT58 0x0400000000000000ull -#define BIT59 0x0800000000000000ull -#define BIT60 0x1000000000000000ull -#define BIT61 0x2000000000000000ull -#define BIT62 0x4000000000000000ull -#define BIT63 0x8000000000000000ull - -/// CPUID related registers -#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information -#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID -#define AMD_CPUID_TLB_L1Cache 0x80000005ul -#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul -#define CPUID_ASSOCIATIVITY_2_WAY 0x02 -#define CPUID_ASSOCIATIVITY_4_WAY 0x04 -#define CPUID_ASSOCIATIVITY_8_WAY 0x06 -#define CPUID_ASSOCIATIVITY_16_WAY 0x08 -#define CPUID_ASSOCIATIVITY_32_WAY 0x0A -#define CPUID_ASSOCIATIVITY_48_WAY 0x0B -#define CPUID_ASSOCIATIVITY_64_WAY 0x0C -#define CPUID_ASSOCIATIVITY_96_WAY 0x0D -#define CPUID_ASSOCIATIVITY_128_WAY 0x0E -#define AMD_CPUID_APM 0x80000007ul -#define LOCAL_APIC_ID 24 -#define LOGICAL_PROCESSOR_COUNT 16 -#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count - -/// CPU Logical ID Transfer -typedef struct { - UINT32 RawId; ///< RawID - UINT64 LogicalId; ///< LogicalID -} CPU_LOGICAL_ID_XLAT; - -/// Logical CPU ID Table -typedef struct { - IN UINT32 Elements; ///< Number of Elements - IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer -} LOGICAL_ID_TABLE; - -// MSRs -// ------------------------ -#define MCG_CTL_P 0x00000100ul // bit 8 for MCG_CTL_P under MSRR -#define MSR_MCG_CAP 0x00000179ul -#define MSR_MC0_CTL 0x00000400ul - -#define MSR_APIC_BAR 0x0000001Bul -#define MSR_PATCH_LEVEL 0x0000008Bul - -#define CPUID_LONG_MODE_ADDR 0x80000008ul -#define AMD_CPUID_FMF 0x80000001ul - -#define MSR_EXTENDED_FEATURE_EN 0xC0000080ul -#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408ul -#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409ul -#define MSR_PATCH_LOADER 0xC0010020ul - -/// Patch Loader Register -typedef struct { - UINT64 PatchBase:32; ///< Linear address of patch header address block - UINT64 SBZ:32; ///< Should be zero -} PATCH_LOADER_MSR; - -#define MSR_SYS_CFG 0xC0010010ul // SYSCFG - F15 Shared -#define MSR_TOM2 0xC001001Dul // TOP_MEM2 - F15 Shared -#define MSR_MC0_CTL_MASK 0xC0010044ul // MC0 Control Mask -#define MSR_MC1_CTL_MASK 0xC0010045ul // MC1 Control Mask -#define MSR_MC2_CTL_MASK 0xC0010046ul // MC2 Control Mask -#define MSR_MC4_CTL_MASK 0xC0010048ul // MC4 Control Mask - -#define MSR_CPUID_FEATS 0xC0011004ul // CPUID Features -#define MSR_CPUID_EXT_FEATS 0xC0011005ul // CPUID Extended Features -#define MSR_HWCR 0xC0010015ul -#define MSR_NB_CFG 0xC001001Ful // NB Config -#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46] -#define INIT_APIC_CPUID_LO 0x00400000ul // [54] -#define MSR_LS_CFG 0xC0011020ul -#define MSR_IC_CFG 0xC0011021ul // ICache Config - F15 Shared -#define MSR_DC_CFG 0xC0011022ul -#define MSR_ME_CFG 0xC0011029ul -#define MSR_BU_CFG 0xC0011023ul -#define MSR_CU_CFG 0xC0011023ul // F15 Shared -#define MSR_DE_CFG 0xC0011029ul // F15 Shared -#define MSR_BU_CFG2 0xC001102Aul -#define MSR_CU_CFG2 0xC001102Aul // F15 Shared -#define MSR_BU_CFG3 0xC001102Bul -#define MSR_CU_CFG3 0xC001102Bul // F15 Shared -#define MSR_LS_CFG2 0xC001102Dul -#define MSR_IBS_OP_DATA3 0xC0011037ul -#define MSR_C001_1070 0xC0011070ul // F15 Shared - - -#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register -#define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul -#define MSR_CPUID_NAME_STRING3 0xC0010033ul -#define MSR_CPUID_NAME_STRING4 0xC0010034ul -#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register -#define MSR_MMIO_Cfg_Base 0xC0010058ul // MMIO Configuration Base Address Register -#define MSR_BIST 0xC0010060ul // BIST Results register -#define MSR_OSVW_ID_Length 0xC0010140ul -#define MSR_OSVW_Status 0xC0010141ul -#define MSR_PERF_CONTROL3 0xC0010003ul // Perfromance control register number 3 -#define MSR_PERF_COUNTER3 0xC0010007ul // Performance counter register number 3 -#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits -#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ull // Configure the controller to capture the - // CAR Corruption -// FUNC_0 registers -// ---------------- -#define HT_LINK_FREQ_OFFSET 8 // Link HT Frequency from capability base -#define HT_LINK_CONTROL_REG_OFFSET 4 -#define HT_LINK_TYPE_REG_OFFSET 0x18 -#define HT_LINK_EXTENDED_FREQ 0x1C -#define HT_LINK_HOST_CAP_MAX 0x20 // HT Host Capability offsets are less than its size. -#define HT_CAPABILITIES_POINTER 0x34 -#define NODE_ID 0x60 -#define HT_INIT_CTRL 0x6C -#define HT_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis -#define HT_INIT_COLD_RST_DET BIT4 -#define HT_INIT_BIOS_RST_DET_0 BIT5 -#define HT_INIT_BIOS_RST_DET_1 BIT9 -#define HT_INIT_BIOS_RST_DET_2 BIT10 -#define HT_INIT_BIOS_RST_DET BIT9 | BIT10 -#define HT_TRANS_CTRL 0x68 -#define HT_TRANS_CTRL_CPU1_EN 0x00000020ul // [5] = CPU1 Enable -#define HT_LINK_CONTROL_0 0x84 -#define HT_LINK_FREQ_0 0x88 // Link HT Frequency -#define EXTENDED_NODE_ID 0x160 -#define ECS_HT_TRANS_CTRL 0x168 -#define ECS_HT_TRANS_CTRL_CPU2_EN 0x00000001ul // [0] = CPU2 Enable -#define ECS_HT_TRANS_CTRL_CPU3_EN 0x00000002ul // [1] = CPU3 Enable -#define ECS_HT_TRANS_CTRL_CPU4_EN 0x00000004ul // [2] = CPU4 Enable -#define ECS_HT_TRANS_CTRL_CPU5_EN 0x00000008ul // [3] = CPU5 Enable - -#define CORE_CTRL 0x1DC -#define CORE_CTRL_CORE1_EN 0x00000002ul -#define CORE_CTRL_CORE2_EN 0x00000004ul -#define CORE_CTRL_CORE3_EN 0x00000008ul -#define CORE_CTRL_CORE4_EN 0x00000010ul -#define CORE_CTRL_CORE5_EN 0x00000020ul -#define CORE_CTRL_CORE6_EN 0x00000040ul -#define CORE_CTRL_CORE7_EN 0x00000080ul -#define CORE_CTRL_CORE8_EN 0x00000100ul -#define CORE_CTRL_CORE9_EN 0x00000200ul - -// FUNC_3 registers -// ---------------- -#define HARDWARE_THERMAL_CTRL_REG 0x64 -#define SOFTWARE_THERMAL_CTRL_REG 0x68 - -#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers -#define ACPI_PSC_4_REG 0x84 - -#define NB_CFG_HIGH_REG 0x8C -#define POWER_CTRL_MISCELLANEOUS_REG 0xA0 -#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC -#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8 -#define MULTI_NODE_CPU 29 -#define CPUID_FMR 0xFC // Family / Model registers -#define DOWNCORE_CTRL 0x190 // Downcore Control Register - -#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148 -#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180 -#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184 - -#define HTPHY_OFFSET_MASK 0xE00001FFul -#define HTPHY_WRITE_CMD 0x40000000ul -#define HTPHY_IS_COMPLETE_MASK 0x80000000ul -#define HTPHY_DIRECT_MAP 0x20000000ul -#define HTPHY_DIRECT_OFFSET_MASK 0x6000FFFFul - -// FUNC_5 registers -// ---------------- -#define COMPUTE_UNIT_STATUS 0x80 -#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84 - - -// Misc. defines. -#define PCI_DEV_BASE 24 - -#define CPU_STEPPING 0x0000000F -#define CPU_MODEL 0x000000F0 -#define CPU_EMODEL 0x000F0000 -#define CPU_EFAMILY 0x00F00000 -#define CPU_FMS_MASK CPU_EFAMILY | CPU_EMODEL | CPU_MODEL | CPU_STEPPING - -#define HTPHY_SELECT 2 -#define PCI_SELECT 1 -#define MSR_SELECT 0 - -#define LOGICAL_ID 1 -#define F_SCHEME 0 -#define DR_SCHEME 1 -#define GR_SCHEME 2 - -#define DR_NO_STRING 0 -#define DR_SOCKET_C32 5 -#define DR_SOCKET_ASB2 4 -#define DR_SOCKET_G34 3 -#define DR_SOCKET_S1G3 2 -#define DR_SOCKET_S1G4 2 -#define DR_SOCKET_AM3 1 -#define DR_SOCKET_1207 0 -#define LN_SOCKET_FM1 2 -#define LN_SOCKET_FS1 1 -#define LN_SOCKET_FP1 0 -#define ON_SOCKET_FT1 0 -#define KR_SOCKET_FT2 0 -#define OR_SOCKET_AM3 1 -#define OR_SOCKET_G34 3 -#define OR_SOCKET_C32 5 -#define TN_SOCKET_FP2 0 -#define TN_SOCKET_FS1 1 -#define TN_SOCKET_FM2 2 -#define KM_SOCKET_FM2 2 -#define KM_SOCKET_G2012 3 -#define KM_SOCKET_C2012 5 -#define SOCKET_IGNORE 0xF - -#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull -#define APIC_EXT_BRDCST_MASK 0x000E0000ul -#define APIC_ENABLE_BIT 0x00000800ul -#ifndef LOCAL_APIC_ADDR -#define LOCAL_APIC_ADDR 0xFEE00000ul -#endif -#define INT_CMD_REG_LO 0x300 -#define INT_CMD_REG_HI 0x310 -#define REMOTE_MSG_REG 0x380 -#define REMOTE_READ_REG 0xC0 -#define APIC_ID_REG 0x20 -#define APIC20_ApicId 24 -#define CMD_REG_TO_READ_DATA 0x338 - -#define MAX_CORE_ID_SIZE 8 -#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1) - -/*------------------------- - * Default definitions - *------------------------- - */ -#define DOWNCORE_MASK_SINGLE 0xFFFFFFFEul -#define DOWNCORE_MASK_DUAL 0xFFFFFFFCul -#define DOWNCORE_MASK_TRI 0xFFFFFFF8ul -#define DOWNCORE_MASK_FOUR 0xFFFFFFF0ul -#define DOWNCORE_MASK_FIVE 0xFFFFFFE0ul -#define DOWNCORE_MASK_SIX 0xFFFFFFC0ul -#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFAul -#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEAul -#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAAul - -#define DELIVERY_STATUS BIT13 -#define REMOTE_READ_STAT_MASK 0x00030000ul -#define REMOTE_DELIVERY_PENDING 0x00010000ul -#define REMOTE_DELIVERY_DONE 0x00020000ul - -/* - * -------------------------------------------------------------------------------------- - * - * D E F I N E S / T Y P E D E F S / S T R U C T U R E S - * - * -------------------------------------------------------------------------------------- - */ - -/// CpuEarly param type -typedef struct { - IN UINT8 MemInitPState; ///< Pstate value during memory initial - IN PLATFORM_CONFIGURATION PlatformConfig; ///< Runtime configurable user options -} AMD_CPU_EARLY_PARAMS; - -/// Enum - Will be used to access each structure -/// related to each CPU family -typedef enum { - REVF, ///< NPT, RevF - REVG, ///< NPT, RevG - DEERHOUND, ///< Family 10h, Deerhound - GRIFFIN ///< Family 11h, Griffin -} CPU_FAMILY; - -/// CPUID -typedef enum { - REG_EAX, ///< EAX - REG_EBX, ///< EBX - REG_ECX, ///< ECX - REG_EDX ///< EDX -} CPUID_REG; - -#endif // _CPU_REGISTERS_H_ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuServices.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuServices.h deleted file mode 100644 index 227e23ecbf..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuServices.h +++ /dev/null @@ -1,332 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Services - * - * Related to the General Services API's, but for the CPU component. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CPU_SERVICES_H_ -#define _CPU_SERVICES_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - /// WARM RESET STATE_BITS -#define WR_STATE_COLD 00 -#define WR_STATE_RESET 01 -#define WR_STATE_EARLY 02 -#define WR_STATE_POST 03 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * The role of primary core for each compute unit can be relative to the cores' launch order. - * - * One core of a compute unit is always given the role as primary. In different feature algorithms - * the core performing the primary core role can be designated relative to compute order. In most cases, - * the primary core is the first core of a compute unit to execute. However, in some cases the primary core - * role is associated with the last core to execute. - * - * If the launch order is strictly ascending, then first core is the lowest number and last core is highest. - * But if the launch order is not ascending, the first and last core follow the launch order, not the numbering order. - * - * Note that for compute units with only one core (AllCoresMapping), that core is primary for both orderings. - * (This includes processors without hardware compute units.) - * - */ -typedef enum { - FirstCoreIsComputeUnitPrimary, ///< the primary core role associates with the first core. - LastCoreIsComputeUnitPrimary, ///< the primary core role associates with the last core. - MaxComputeUnitPrimarySelector, ///< limit check. -} COMPUTE_UNIT_PRIMARY_SELECTOR; - -/** - * The supported Core to Compute unit mappings. - */ -typedef enum { - AllCoresMapping, ///< All Cores are primary cores - EvenCoresMapping, ///< Compute units are even/odd core pairs. - BitMapMapping, ///< Currently not supported by any family, arbitrary core - ///< to compute unit mapping. - MaxComputeUnitMapping ///< Not a mapping, use for limit check. -} COMPUTE_UNIT_MAPPING; - -/** - * Core Pair Map entry. - * Provide for interpreting the core pairing for the processor's compute units. - * - * HT_LIST_TERMINAL as an Enabled value means the end of a list of map structs. - * Zero as an Enabled value implies Compute Units are not supported by the processor - * and the mapping is assumed to be AllCoresMapping. - * - */ -typedef struct { - UINT8 Enabled; ///< The value of the Enabled Compute Units - UINT8 DualCore; ///< The value of the Dual Core Compute Units - COMPUTE_UNIT_MAPPING Mapping; ///< When the processor module matches these values, use this mapping method. -} CORE_PAIR_MAP; - -//---------------------------------------------------------------------------- -// CPU SYSTEM INFO TYPEDEFS, STRUCTURES, ENUMS -// -//---------------------------------------------------------------------------- -/// SYSTEM INFO -typedef struct _SYSTEM_INFO { - UINT32 TotalNumberOfSockets; ///< Total Number of Sockets - UINT32 TotalNumberOfCores; ///< Total Number Of Cores - UINT32 CurrentSocketNum; ///< Current Socket Number - UINT32 CurrentCoreNum; ///< Current Core Number - UINT32 CurrentCoreApicId; ///< Current Core Apic ID - UINT32 CurrentLogicalCpuId; ///< Current Logical CPU ID -} SYSTEM_INFO; - -/// WARM_RESET_REQUEST -typedef struct _WARM_RESET_REQUEST { - UINT8 RequestBit:1; ///< Request Bit - UINT8 StateBits:2; ///< State Bits - UINT8 PostStage:2; ///< Post Stage - UINT8 Reserved:(8 - 5); ///< Reserved -} WARM_RESET_REQUEST; -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -VOID -GetCurrentNodeNum ( - OUT UINT32 *Node, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Get the current Platform's number of Sockets, regardless of how many are populated. - * - */ -UINT32 -GetPlatformNumberOfSockets ( VOID ); - -/** - * Get the number of Modules to check presence in each Processor. - * - */ -UINT32 -GetPlatformNumberOfModules ( VOID ); - -BOOLEAN -IsProcessorPresent ( - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * For a specific Node, get its Socket and Module ids. - * - */ -BOOLEAN -GetSocketModuleOfNode ( - IN UINT32 Node, - OUT UINT32 *Socket, - OUT UINT32 *Module, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Get the current core's Processor APIC Index. - */ -UINT32 -GetProcessorApicIndex ( - IN UINT32 Node, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Provide the number of installed processors (not Nodes! and not Sockets!) - */ -UINT32 -GetNumberOfProcessors ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetActiveCoresInCurrentSocket ( - OUT UINT32 *CoreCount, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetActiveCoresInGivenSocket ( - IN UINT32 Socket, - OUT UINT32 *CoreCount, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINTN -GetActiveCoresInCurrentModule ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINTN -GetNumberOfCompUnitsInCurrentModule ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetGivenModuleCoreRange ( - IN UINT32 Socket, - IN UINT32 Module, - OUT UINT32 *LowCore, - OUT UINT32 *HighCore, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetCurrentCore ( - OUT UINT32 *Core, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetCurrentNodeAndCore ( - OUT UINT32 *Node, - OUT UINT32 *Core, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -IsCurrentCorePrimary ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetApMailbox ( - OUT UINT32 *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -CacheApMailbox ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINTN -GetSystemDegree ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -GetNodeId ( - IN UINT32 SocketId, - IN UINT32 ModuleId, - OUT UINT8 *NodeId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -WaitMicroseconds ( - IN UINT32 Microseconds, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Get the compute unit mapping algorithm. - */ -COMPUTE_UNIT_MAPPING -GetComputeUnitMapping ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Does the current core have the role of primary core for the compute unit? - */ -BOOLEAN -IsCorePairPrimary ( - IN COMPUTE_UNIT_PRIMARY_SELECTOR Selector, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Are the two specified cores shared in a compute unit? - */ -BOOLEAN -AreCoresPaired ( - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 CoreA, - IN UINT32 CoreB, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SetWarmResetFlag ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ); - -VOID -GetWarmResetFlag ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ); - -BOOLEAN -IsWarmReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -CheckBistStatus ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -SetWarmResetAtEarly ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader -); - -#endif // _CPU_SERVICES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuWarmReset.c deleted file mode 100644 index 28d11fff3c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuWarmReset.c +++ /dev/null @@ -1,235 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Warm Reset Implementation. - * - * Implement Warm Reset Interface. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_CPUWARMRESET_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will set the CPU register warm reset bits. - * - * Note: This function will be called by UEFI BIOS's - * The UEFI wrapper code should register this function, to be called back later point - * in time, before the wrapper code does warm reset. - * - * @param[in] StdHeader Config handle for library and services - * @param[in] Request Indicate warm reset status - * - *--------------------------------------------------------------------------------------- - **/ -VOID -SetWarmResetFlag ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN WARM_RESET_REQUEST *Request - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - FamilySpecificServices = NULL; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will get the CPU register warm reset bits. - * - * Note: This function will be called by UEFI BIOS's - * The UEFI wrapper code should register this function, to be called back later point - * in time, before the wrapper code does warm reset. - * - * @param[in] StdHeader Config handle for library and services - * @param[out] Request Indicate warm reset status - * - *--------------------------------------------------------------------------------------- - **/ -VOID -GetWarmResetFlag ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT WARM_RESET_REQUEST *Request - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - FamilySpecificServices = NULL; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, Request); - - switch (StdHeader->Func) { - case AMD_INIT_RESET: - Request->PostStage = (UINT8) WR_STATE_RESET; - break; - case AMD_INIT_EARLY: - Request->PostStage = (UINT8) WR_STATE_EARLY; - break; - case AMD_INIT_POST: - // Fall through to default case - default: - Request->PostStage = (UINT8) WR_STATE_POST; - break; - } -} -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - (AGESA ONLY) - *---------------------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------------------*/ -/** - * Is this boot a warm reset? - * - * This function reads the CPU register warm reset bit that is preserved after a warm reset. - * Which in fact gets set before issuing warm reset. We just use the BSP's register always. - * - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE Warm Reset - * @retval FALSE Not Warm Reset - * - */ -BOOLEAN -IsWarmReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PostStage; - WARM_RESET_REQUEST Request; - BOOLEAN WarmReset; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - FamilySpecificServices = NULL; - - switch (StdHeader->Func) { - case AMD_INIT_RESET: - PostStage = WR_STATE_RESET; - break; - case AMD_INIT_EARLY: - PostStage = WR_STATE_EARLY; - break; - case AMD_INIT_POST: - default: - PostStage = WR_STATE_POST; - break; - } - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request); - - if (Request.StateBits >= PostStage) { - WarmReset = TRUE; - } else { - WarmReset = FALSE; - } - - return WarmReset; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will set the CPU register warm reset bits at AmdInitEarly if it is - * currently in cold boot. To request for a warm reset, set the RequestBit to TRUE - * and the StateBits to (current poststage - 1) - * - * @param[in] Data The table data value (unused in this routine) - * @param[in] StdHeader Config handle for library and services - * - *--------------------------------------------------------------------------------------- - **/ -VOID -SetWarmResetAtEarly ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - WARM_RESET_REQUEST Request; - - if (!IsWarmReset (StdHeader)) { - GetWarmResetFlag (StdHeader, &Request); - - Request.RequestBit = TRUE; - Request.StateBits = (Request.PostStage - 1); - - SetWarmResetFlag (StdHeader, &Request); - } -} - -/*---------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c deleted file mode 100644 index 485cb4ceb8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c +++ /dev/null @@ -1,885 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Heap Manager and Heap Allocation APIs, and related functions. - * - * Contains code that initialize, maintain, and allocate the heap space. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $ - * - */ -/******************************************************************************* - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "heapManager.h" -#include "cpuCacheInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_HEAPMANAGER_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINT64 -STATIC -HeapGetCurrentBase ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -DeleteFreeSpaceNode ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 OffsetOfDeletedNode - ); - -VOID -STATIC -InsertFreeSpaceNode ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 OffsetOfInsertNode - ); - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------*/ -/** - * This function initializes the heap for each CPU core. - * - * Check for already initialized. If not, determine offset of local heap in CAS and - * setup initial heap markers and bookkeeping status. Initialize a couple heap items - * all cores need, for convenience. Currently these are caching the AP mailbox info and - * an initial event log. - * - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS This core's heap is initialized - * @retval AGESA_FATAL This core's heap cannot be initialized due to any reasons below: - * - current processor family cannot be identified. - * - */ -AGESA_STATUS -HeapManagerInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // First Time Initialization - // Note: First 16 bytes of buffer is reserved for Heap Manager use - UINT16 HeapAlreadyInitSizeDword; - UINT32 HeapAlreadyRead; - UINT8 L2LineSize; - UINT8 *HeapBufferPtr; - UINT8 *HeapInitPtr; - UINT32 *HeapDataPtr; - UINT64 MsrData; - UINT64 MsrMask; - UINT8 Ignored; - CPUID_DATA CpuId; - BUFFER_NODE *FreeSpaceNode; - CACHE_INFO *CacheInfoPtr; - AGESA_STATUS IgnoredSts; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - CPU_LOGICAL_ID CpuFamilyRevision; - - // Check whether this is a known processor family. - GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - if ((CpuFamilyRevision.Family == 0) && (CpuFamilyRevision.Revision == 0)) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); - HeapBufferPtr = (UINT8 *)(UINTN) StdHeader->HeapBasePtr; - - // Check whether the heap manager is already initialized - LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader); - if (MsrData == (CacheInfoPtr->VariableMtrrMask & AMD_HEAP_MTRR_MASK)) { - LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader); - if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) (UINTN) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) { - if (((HEAP_MANAGER *) HeapBufferPtr)->Signature == HEAP_SIGNATURE_VALID) { - // This is not a bug, there are multiple premem basic entry points, - // and each will call heap init to make sure create struct will succeed. - // If that is later deemed a problem, there needs to be a reasonable test - // for the calling code to make to determine if it needs to init heap or not. - // In the mean time, add this to the event log - PutEventLog (AGESA_SUCCESS, - CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED, - 0, 0, 0, 0, StdHeader); - return AGESA_SUCCESS; - } - } - } - - // Set variable MTRR base and mask - MsrData = ((UINT64) (UINTN) HeapBufferPtr & CacheInfoPtr->HeapBaseMask); - MsrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK; - - MsrData |= 0x06; - LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader); - LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrMask, StdHeader); - - // Set top of memory to a temp value - MsrData = (UINT64) (AMD_TEMP_TOM); - LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - - // Enable variable MTRRs - LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); - MsrData |= AMD_VAR_MTRR_ENABLE_BIT; - LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); - - // Initialize Heap Space - // BIOS may store to a line only after it has been allocated by a load - LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader); - L2LineSize = (UINT8) (CpuId.ECX_Reg); - HeapInitPtr = HeapBufferPtr ; - for (HeapAlreadyRead = 0; HeapAlreadyRead < AMD_HEAP_SIZE_PER_CORE; - (HeapAlreadyRead = HeapAlreadyRead + L2LineSize)) { - Ignored = *HeapInitPtr; - HeapInitPtr += L2LineSize; - } - - HeapDataPtr = (UINT32 *) HeapBufferPtr; - for (HeapAlreadyInitSizeDword = 0; HeapAlreadyInitSizeDword < AMD_HEAP_SIZE_DWORD_PER_CORE; HeapAlreadyInitSizeDword++) { - *HeapDataPtr = 0; - HeapDataPtr++; - } - - // Note: We are reserving the first 16 bytes for Heap Manager use - // UsedSize indicates the size of heap spaced is used for HEAP_MANAGER, BUFFER_NODE, - // Pad for 16-byte alignment, buffer data, and IDS SENTINEL. - // FirstActiveBufferOffset is initalized as invalid heap offset, AMD_HEAP_INVALID_HEAP_OFFSET. - // FirstFreeSpaceOffset is initalized as the byte right after HEAP_MANAGER header. - // Then we set Signature of HEAP_MANAGER header as valid, HEAP_SIGNATURE_VALID. - ((HEAP_MANAGER*) HeapBufferPtr)->UsedSize = sizeof (HEAP_MANAGER); - ((HEAP_MANAGER*) HeapBufferPtr)->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; - ((HEAP_MANAGER*) HeapBufferPtr)->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); - ((HEAP_MANAGER*) HeapBufferPtr)->Signature = HEAP_SIGNATURE_VALID; - // Create free space link - FreeSpaceNode = (BUFFER_NODE *) (HeapBufferPtr + sizeof (HEAP_MANAGER)); - FreeSpaceNode->BufferSize = AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER) - sizeof (BUFFER_NODE); - FreeSpaceNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - - StdHeader->HeapStatus = HEAP_LOCAL_CACHE; - if (!IsBsp (StdHeader, &IgnoredSts)) { - // The BSP's hardware mailbox has not been initialized, so only APs - // can do this at this point. - CacheApMailbox (StdHeader); - } - EventLogInitialization (StdHeader); - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Allocates space for a new buffer in the heap - * - * This function will allocate new buffer either by using internal 'AGESA' heapmanager - * or by using externa (IBV) heapmanager. This function will also determine if whether or not - * there is enough space for the new structure. If so, it will zero out the buffer, - * and return a pointer to the region. - * - * @param[in,out] AllocateHeapParams structure pointer containing the size of the - * desired new region, its handle, and the - * return pointer. - * @param[in,out] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_BOUNDS_CHK Handle already exists, or not enough - * free space - * @retval AGESA_UNSUPPORTED Do not support this kind of heap allocation - * @retval AGESA_ERROR Heap is invaild - * - */ -AGESA_STATUS -HeapAllocateBuffer ( - IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddress; - UINT8 AlignTo16Byte; - UINT8 CalloutFcnData; - UINT32 RemainSize; - UINT32 OffsetOfSplitNode; - UINT32 OffsetOfNode; - HEAP_MANAGER *HeapManager; - BUFFER_NODE *FreeSpaceNode; - BUFFER_NODE *SplitFreeSpaceNode; - BUFFER_NODE *CurrentBufferNode; - BUFFER_NODE *NewBufferNode; - AGESA_BUFFER_PARAMS AgesaBuffer; - - ASSERT (StdHeader != NULL); - if (AllocateHeapParams->Persist == HEAP_RUNTIME_SYSTEM_MEM) { - ASSERT (StdHeader->HeapStatus == HEAP_SYSTEM_MEM); - if (StdHeader->HeapStatus != HEAP_SYSTEM_MEM) { - return AGESA_UNSUPPORTED; - } - } - - // At this stage we will decide to either use external (IBV) heap manger - // or internal (AGESA) heap manager. - - // If (HeapStatus == HEAP_SYSTEM_MEM), then use the call function to call - // external heap manager - if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) { - AgesaBuffer.StdHeader = *StdHeader; - AgesaBuffer.BufferHandle = AllocateHeapParams->BufferHandle; - AgesaBuffer.BufferLength = AllocateHeapParams->RequestedBufferSize; - - if (AllocateHeapParams->Persist == HEAP_RUNTIME_SYSTEM_MEM) { - CalloutFcnData = HEAP_CALLOUT_RUNTIME; - } else { - CalloutFcnData = HEAP_CALLOUT_BOOTTIME; - } - AGESA_TESTPOINT (TpIfBeforeAllocateHeapBuffer, StdHeader); - if (AgesaAllocateBuffer (CalloutFcnData, &AgesaBuffer) != AGESA_SUCCESS) { - AllocateHeapParams->BufferPtr = NULL; - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpIfAfterAllocateHeapBuffer, StdHeader); - - AllocateHeapParams->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer); - return AGESA_SUCCESS; - } - - // If (StdHeader->HeapStatus != HEAP_SYSTEM_MEM), then allocated buffer - // using following AGESA Heap Manager code. - - // Buffer pointer is NULL unless we return a buffer. - AlignTo16Byte = 0; - AllocateHeapParams->BufferPtr = NULL; - AllocateHeapParams->RequestedBufferSize += NUM_OF_SENTINEL * SIZE_OF_SENTINEL; - - // Get base address - BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; - HeapManager = (HEAP_MANAGER *) BaseAddress; - - // Check Heap database is valid - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader); - HeapManager = (HEAP_MANAGER *) BaseAddress; - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // Heap is not available, ASSERT here - ASSERT (FALSE); - return AGESA_ERROR; - } - StdHeader->HeapBasePtr = (UINTN)BaseAddress; - } - - // Allocate - CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + sizeof (HEAP_MANAGER)); - // If there already has been a heap with the incoming BufferHandle, we return AGESA_BOUNDS_CHK. - if (HeapManager->FirstActiveBufferOffset != AMD_HEAP_INVALID_HEAP_OFFSET) { - CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + HeapManager->FirstActiveBufferOffset); - while (CurrentBufferNode->OffsetOfNextNode != AMD_HEAP_INVALID_HEAP_OFFSET) { - if (CurrentBufferNode->BufferHandle == AllocateHeapParams->BufferHandle) { - PutEventLog (AGESA_BOUNDS_CHK, - CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED, - AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader); - return AGESA_BOUNDS_CHK; - } else { - CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + CurrentBufferNode->OffsetOfNextNode); - } - } - if (CurrentBufferNode->BufferHandle == AllocateHeapParams->BufferHandle) { - PutEventLog (AGESA_BOUNDS_CHK, - CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED, - AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader); - return AGESA_BOUNDS_CHK; - } - } - - // Find the buffer size that first matches the requested buffer size (i.e. the first free buffer of greater size). - OffsetOfNode = HeapManager->FirstFreeSpaceOffset; - FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfNode); - while (OffsetOfNode != AMD_HEAP_INVALID_HEAP_OFFSET) { - AlignTo16Byte = (UINT8) ((0x10 - (((UINTN) (VOID *) FreeSpaceNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF); - AllocateHeapParams->RequestedBufferSize = (UINT32) (AllocateHeapParams->RequestedBufferSize + AlignTo16Byte); - if (FreeSpaceNode->BufferSize >= AllocateHeapParams->RequestedBufferSize) { - break; - } - AllocateHeapParams->RequestedBufferSize = (UINT32) (AllocateHeapParams->RequestedBufferSize - AlignTo16Byte); - OffsetOfNode = FreeSpaceNode->OffsetOfNextNode; - FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfNode); - } - if (OffsetOfNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - // We don't find any free space buffer that matches the requested buffer size. - PutEventLog (AGESA_BOUNDS_CHK, - CPU_ERROR_HEAP_IS_FULL, - AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader); - return AGESA_BOUNDS_CHK; - } else { - // We find one matched free space buffer. - DeleteFreeSpaceNode (StdHeader, OffsetOfNode); - NewBufferNode = FreeSpaceNode; - // Add new buffer node to the buffer chain - if (HeapManager->FirstActiveBufferOffset == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapManager->FirstActiveBufferOffset = sizeof (HEAP_MANAGER); - } else { - CurrentBufferNode->OffsetOfNextNode = OffsetOfNode; - } - // New buffer size - RemainSize = FreeSpaceNode->BufferSize - AllocateHeapParams->RequestedBufferSize; - if (RemainSize > sizeof (BUFFER_NODE)) { - NewBufferNode->BufferSize = AllocateHeapParams->RequestedBufferSize; - OffsetOfSplitNode = OffsetOfNode + sizeof (BUFFER_NODE) + NewBufferNode->BufferSize; - SplitFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfSplitNode); - SplitFreeSpaceNode->BufferSize = RemainSize - sizeof (BUFFER_NODE); - InsertFreeSpaceNode (StdHeader, OffsetOfSplitNode); - } else { - // Remain size is less than BUFFER_NODE, we use whole size instead of requested size. - NewBufferNode->BufferSize = FreeSpaceNode->BufferSize; - } - } - - // Initialize BUFFER_NODE structure of NewBufferNode - NewBufferNode->BufferHandle = AllocateHeapParams->BufferHandle; - if ((AllocateHeapParams->Persist == HEAP_TEMP_MEM) || (AllocateHeapParams->Persist == HEAP_SYSTEM_MEM)) { - NewBufferNode->Persist = AllocateHeapParams->Persist; - } else { - NewBufferNode->Persist = HEAP_LOCAL_CACHE; - } - NewBufferNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - NewBufferNode->PadSize = AlignTo16Byte; - - // Clear to 0x00 - LibAmdMemFill ((VOID *) ((UINT8 *) NewBufferNode + sizeof (BUFFER_NODE)), 0x00, NewBufferNode->BufferSize, StdHeader); - - // Debug feature - SET_SENTINEL_BEFORE (NewBufferNode, AlignTo16Byte); - SET_SENTINEL_AFTER (NewBufferNode); - - // Update global variables - HeapManager->UsedSize += NewBufferNode->BufferSize + sizeof (BUFFER_NODE); - - // Now fill in the incoming structure - AllocateHeapParams->BufferPtr = (UINT8 *) ((UINT8 *) NewBufferNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + AlignTo16Byte); - AllocateHeapParams->RequestedBufferSize -= (NUM_OF_SENTINEL * SIZE_OF_SENTINEL + AlignTo16Byte); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Deallocates a previously allocated buffer in the heap - * - * This function will deallocate buffer either by using internal 'AGESA' heapmanager - * or by using externa (IBV) heapmanager. - * - * @param[in] BufferHandle Handle of the buffer to free. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_BOUNDS_CHK Handle does not exist on the heap - * - */ -AGESA_STATUS -HeapDeallocateBuffer ( - IN UINT32 BufferHandle, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddress; - UINT32 NodeSize; - UINT32 OffsetOfFreeSpaceNode; - UINT32 OffsetOfPreviousNode; - UINT32 OffsetOfCurrentNode; - BOOLEAN HeapLocateFlag; - HEAP_MANAGER *HeapManager; - BUFFER_NODE *CurrentNode; - BUFFER_NODE *PreviousNode; - BUFFER_NODE *FreeSpaceNode; - AGESA_BUFFER_PARAMS AgesaBuffer; - - ASSERT (StdHeader != NULL); - - HeapLocateFlag = TRUE; - BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; - HeapManager = (HEAP_MANAGER *) BaseAddress; - - // Check Heap database is valid - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader); - HeapManager = (HEAP_MANAGER *) BaseAddress; - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // Heap is not available, ASSERT here - ASSERT (FALSE); - return AGESA_ERROR; - } - StdHeader->HeapBasePtr = (UINTN)BaseAddress; - } - - OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; - OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset; - CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - - // Locate heap - if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { - if (OffsetOfCurrentNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapLocateFlag = FALSE; - } else { - while (CurrentNode->BufferHandle != BufferHandle) { - if (CurrentNode->OffsetOfNextNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapLocateFlag = FALSE; - break; - } else { - OffsetOfPreviousNode = OffsetOfCurrentNode; - OffsetOfCurrentNode = CurrentNode->OffsetOfNextNode; - CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - } - } - } - } else { - HeapLocateFlag = FALSE; - } - - if (HeapLocateFlag == TRUE) { - // CurrentNode points to the buffer which wanted to be deallocated. - // Remove deallocated heap from active buffer chain. - if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapManager->FirstActiveBufferOffset = CurrentNode->OffsetOfNextNode; - } else { - PreviousNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode); - PreviousNode->OffsetOfNextNode = CurrentNode->OffsetOfNextNode; - } - // Now, CurrentNode become a free space node. - HeapManager->UsedSize -= CurrentNode->BufferSize + sizeof (BUFFER_NODE); - // Loop free space chain to see if any free space node is just before/after CurrentNode, then merge them. - OffsetOfFreeSpaceNode = HeapManager->FirstFreeSpaceOffset; - FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfFreeSpaceNode); - while (OffsetOfFreeSpaceNode != AMD_HEAP_INVALID_HEAP_OFFSET) { - if ((OffsetOfFreeSpaceNode + sizeof (BUFFER_NODE) + FreeSpaceNode->BufferSize) == OffsetOfCurrentNode) { - DeleteFreeSpaceNode (StdHeader, OffsetOfFreeSpaceNode); - NodeSize = FreeSpaceNode->BufferSize + CurrentNode->BufferSize + sizeof (BUFFER_NODE); - OffsetOfCurrentNode = OffsetOfFreeSpaceNode; - CurrentNode = FreeSpaceNode; - CurrentNode->BufferSize = NodeSize; - } else if (OffsetOfFreeSpaceNode == (OffsetOfCurrentNode + sizeof (BUFFER_NODE) + CurrentNode->BufferSize)) { - DeleteFreeSpaceNode (StdHeader, OffsetOfFreeSpaceNode); - NodeSize = FreeSpaceNode->BufferSize + CurrentNode->BufferSize + sizeof (BUFFER_NODE); - CurrentNode->BufferSize = NodeSize; - } - OffsetOfFreeSpaceNode = FreeSpaceNode->OffsetOfNextNode; - FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfFreeSpaceNode); - } - InsertFreeSpaceNode (StdHeader, OffsetOfCurrentNode); - return AGESA_SUCCESS; - } else { - // If HeapStatus == HEAP_SYSTEM_MEM, try callout function - if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) { - AgesaBuffer.StdHeader = *StdHeader; - AgesaBuffer.BufferHandle = BufferHandle; - - AGESA_TESTPOINT (TpIfBeforeDeallocateHeapBuffer, StdHeader); - if (AgesaDeallocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) { - return AGESA_ERROR; - } - AGESA_TESTPOINT (TpIfAfterDeallocateHeapBuffer, StdHeader); - - return AGESA_SUCCESS; - } - // If we are still unable to locate the buffer handle, return AGESA_BOUNDS_CHK - if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { - PutEventLog (AGESA_BOUNDS_CHK, - CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT, - BufferHandle, 0, 0, 0, StdHeader); - } else { - ASSERT (FALSE); - } - return AGESA_BOUNDS_CHK; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Locates a previously allocated buffer on the heap. - * - * This function searches the heap for a buffer with the desired handle, and - * returns a pointer to the buffer. - * - * @param[in,out] LocateHeap Structure containing the buffer's handle, - * and the return pointer. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS No error - * @retval AGESA_BOUNDS_CHK Handle does not exist on the heap - * - */ -AGESA_STATUS -HeapLocateBuffer ( - IN OUT LOCATE_HEAP_PTR *LocateHeap, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *BaseAddress; - UINT8 AlignTo16Byte; - UINT32 OffsetOfCurrentNode; - BOOLEAN HeapLocateFlag; - HEAP_MANAGER *HeapManager; - BUFFER_NODE *CurrentNode; - AGESA_BUFFER_PARAMS AgesaBuffer; - - ASSERT (StdHeader != NULL); - - HeapLocateFlag = TRUE; - BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; - HeapManager = (HEAP_MANAGER *) BaseAddress; - - // Check Heap database is valid - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // The base address in StdHeader is incorrect, get base address by itself - BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader); - HeapManager = (HEAP_MANAGER *) BaseAddress; - if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { - // Heap is not available, ASSERT here - ASSERT (FALSE); - return AGESA_ERROR; - } - StdHeader->HeapBasePtr = (UINTN)BaseAddress; - } - OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset; - CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - - // Find buffer using internal heap manager - // Locate the heap using handle = LocateHeap-> BufferHandle - // If HeapStatus != HEAP_SYSTEM_ MEM - if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { - if (OffsetOfCurrentNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapLocateFlag = FALSE; - } else { - while (CurrentNode->BufferHandle != LocateHeap->BufferHandle) { - if (CurrentNode->OffsetOfNextNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapLocateFlag = FALSE; - break; - } else { - OffsetOfCurrentNode = CurrentNode->OffsetOfNextNode; - CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - } - } - } - } else { - HeapLocateFlag = FALSE; - } - - if (HeapLocateFlag) { - AlignTo16Byte = CurrentNode->PadSize; - LocateHeap->BufferPtr = (UINT8 *) ((UINT8 *) CurrentNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + AlignTo16Byte); - LocateHeap->BufferSize = CurrentNode->BufferSize - NUM_OF_SENTINEL * SIZE_OF_SENTINEL - AlignTo16Byte; - return AGESA_SUCCESS; - } else { - // If HeapStatus == HEAP_SYSTEM_MEM, try callout function - if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) { - AgesaBuffer.StdHeader = *StdHeader; - AgesaBuffer.BufferHandle = LocateHeap->BufferHandle; - - AGESA_TESTPOINT (TpIfBeforeLocateHeapBuffer, StdHeader); - if (AgesaLocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) { - LocateHeap->BufferPtr = NULL; - return AGESA_ERROR; - } - LocateHeap->BufferSize = AgesaBuffer.BufferLength; - AGESA_TESTPOINT (TpIfAfterLocateHeapBuffer, StdHeader); - - LocateHeap->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer); - return AGESA_SUCCESS; - } - - // If we are still unable to deallocate the buffer handle, return AGESA_BOUNDS_CHK - LocateHeap->BufferPtr = NULL; - LocateHeap->BufferSize = 0; - if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { - PutEventLog (AGESA_BOUNDS_CHK, - CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT, - LocateHeap->BufferHandle, 0, 0, 0, StdHeader); - } else { - ASSERT (FALSE); - } - return AGESA_BOUNDS_CHK; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the heap base address - * - * This function will try to locate heap from cache, temp memory, main memory. - * The heap signature will be checked for validity on each possible location. - * Firstly, try if heap base is in cache by calling the function HeapGetCurrentBase. - * Secondly, try if heap base is temp memory by UserOptoions.CfgHeapDramAddress. - * Thirdly, try if heap base is in main memory by doing a buffer locate with buffer handle - * AMD_HEAP_IN_MAIN_MEMORY_HANDLE. - * If no valid heap signature is found in each possible location above, a NULL pointer is returned. - * - * @param[in] StdHeader Config handle for library and services. - * - * @return Heap base address of the executing core's heap. - * - */ -UINT64 -HeapGetBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 BaseAddress; - HEAP_MANAGER *HeapManager; - AGESA_BUFFER_PARAMS AgesaBuffer; - - // Firstly, we try to see if heap is in cache - BaseAddress = HeapGetCurrentBase (StdHeader); - HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress; - - if ((HeapManager->Signature != HEAP_SIGNATURE_VALID) && - (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET) && - (StdHeader->HeapStatus != HEAP_LOCAL_CACHE)) { - // Secondly, we try to see if heap is in temp memory - BaseAddress = UserOptions.CfgHeapDramAddress; - HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress; - if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { - // Thirdly, we try to see if heap in main memory - // by locating with external buffer manager (IBV) - AgesaBuffer.StdHeader = *StdHeader; - AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE; - if (AgesaLocateBuffer (0, &AgesaBuffer) == AGESA_SUCCESS) { - BaseAddress = (UINT64) (UINTN) AgesaBuffer.BufferPointer; - HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress; - if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { - // No valid heap signature ever found, return a NULL pointer - BaseAddress = (UINT64) (UINTN) NULL; - } - } else { - // No heap buffer is allocated by external manager (IBV), return a NULL pointer - BaseAddress = (UINT64) (UINTN) NULL; - } - } - } - - return BaseAddress; -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * DeleteFreeSpaceNode - * - * Description: - * Delete a free space node from free space chain - * - * Parameters: - * @param[in] StdHeader Config handle for library and services. - * @param[in] OffsetOfDeletedNode Offset of deleted node. - * - * Processing: - * - */ -VOID -STATIC -DeleteFreeSpaceNode ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 OffsetOfDeletedNode - ) -{ - UINT8 *BaseAddress; - UINT32 OffsetOfPreviousNode; - UINT32 OffsetOfCurrentNode; - HEAP_MANAGER *HeapManager; - BUFFER_NODE *CurrentFreeSpaceNode; - BUFFER_NODE *PreviousFreeSpaceNode; - - - BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; - HeapManager = (HEAP_MANAGER *) BaseAddress; - - OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; - OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset; - // - // After AmdInitEnv, there is no free space provided for HeapAllocateBuffer. - // Hence if the FirstFreeSpaceOffset is AMD_HEAP_INVALID_HEAP_OFFSET, then - // no need to do more on delete node. - // - if (OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) { - CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) && (OffsetOfCurrentNode != OffsetOfDeletedNode)) { - OffsetOfPreviousNode = OffsetOfCurrentNode; - OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode; - CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - } - if (OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) { - if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapManager->FirstFreeSpaceOffset = CurrentFreeSpaceNode->OffsetOfNextNode; - } else { - PreviousFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode); - PreviousFreeSpaceNode->OffsetOfNextNode = CurrentFreeSpaceNode->OffsetOfNextNode; - } - } - } - return; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * InsertFreeSpaceNode - * - * Description: - * Insert a free space node to free space chain, size order - * - * Parameters: - * @param[in] StdHeader Config handle for library and services. - * @param[in] OffsetOfInsertNode Offset of inserted node. - * - * Processing: - * - */ -VOID -STATIC -InsertFreeSpaceNode ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 OffsetOfInsertNode - ) -{ - UINT8 *BaseAddress; - UINT32 OffsetOfPreviousNode; - UINT32 OffsetOfCurrentNode; - HEAP_MANAGER *HeapManager; - BUFFER_NODE *CurrentFreeSpaceNode; - BUFFER_NODE *PreviousFreeSpaceNode; - BUFFER_NODE *InsertedFreeSpaceNode; - - BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; - HeapManager = (HEAP_MANAGER *) BaseAddress; - - OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; - OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset; - CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - InsertedFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfInsertNode); - while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) && - (CurrentFreeSpaceNode->BufferSize < InsertedFreeSpaceNode->BufferSize)) { - OffsetOfPreviousNode = OffsetOfCurrentNode; - OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode; - CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - } - InsertedFreeSpaceNode->OffsetOfNextNode = OffsetOfCurrentNode; - if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) { - HeapManager->FirstFreeSpaceOffset = OffsetOfInsertNode; - } else { - PreviousFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode); - PreviousFreeSpaceNode->OffsetOfNextNode = OffsetOfInsertNode; - } - return; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the base address of the executing core's heap. - * - * This function uses the executing core's socket/core numbers to determine - * where it's heap should be located. - * - * @param[in] StdHeader Config handle for library and services. - * - * @return A pointer to the executing core's heap. - * - */ -UINT64 -STATIC -HeapGetCurrentBase ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 SystemCoreNumber; - UINT64 ReturnPtr; - AGESA_STATUS IgnoredStatus; - CPU_SPECIFIC_SERVICES *FamilyServices; - - if (IsBsp (StdHeader, &IgnoredStatus)) { - ReturnPtr = AMD_HEAP_START_ADDRESS; - } else { - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - - SystemCoreNumber = FamilyServices->GetApCoreNumber (FamilyServices, StdHeader); - ASSERT (SystemCoreNumber != 0); - ASSERT (SystemCoreNumber < 64); - ReturnPtr = ((SystemCoreNumber * AMD_HEAP_SIZE_PER_CORE) + AMD_HEAP_START_ADDRESS); - } - ASSERT (ReturnPtr <= ((AMD_HEAP_REGION_END_ADDRESS + 1) - AMD_HEAP_SIZE_PER_CORE)); - return ReturnPtr; -} - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.h deleted file mode 100644 index f933dee0e0..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.h +++ /dev/null @@ -1,243 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Heap Manager and Heap Allocation APIs, and related functions. - * - * Contains code that initialize, maintain, and allocate the heap space. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU - * @e \$Revision: 55372 $ @e \$Date: 2011-06-20 17:22:54 -0600 (Mon, 20 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _HEAP_MANAGER_H_ -#define _HEAP_MANAGER_H_ - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ -#define AMD_MTRR_VARIABLE_BASE0 0x200 -#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A -#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1) - -#define AMD_HEAP_START_ADDRESS 0x400000 -#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFF -#define AMD_HEAP_SIZE_PER_CORE 0x010000 -#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFF -#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800ull & ((AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1)) | 0x800) -#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4) - -#define AMD_TEMP_TOM 0x20000000 // Set TOM to 512 MB (temporary value) -#define AMD_VAR_MTRR_ENABLE_BIT 0x100000 // bit 20 - -#define AMD_HEAP_RAM_ADDRESS 0xB0000 - -#define HEAP_SIGNATURE_VALID 0x50414548 // Signature: 'HEAP' -#define HEAP_SIGNATURE_INVALID 0x00000000 // Signature cleared - -///Heap Manager Life cycle -#define HEAP_DO_NOT_EXIST_YET 1 -#define HEAP_LOCAL_CACHE 2 -#define HEAP_TEMP_MEM 3 -#define HEAP_SYSTEM_MEM 4 -#define HEAP_DO_NOT_EXIST_ANYMORE 5 -#define HEAP_S3_RESUME 6 -#define HEAP_RUNTIME_SYSTEM_MEM 7 - -///Heap callout -#define HEAP_CALLOUT_BOOTTIME 0 -#define HEAP_CALLOUT_RUNTIME 1 - -#define AMD_MTRR_FIX64k_00000 0x250 -#define AMD_MTRR_FIX16k_80000 0x258 -#define AMD_MTRR_FIX16k_A0000 0x259 -#define AMD_MTRR_FIX4k_C0000 0x268 -#define AMD_MTRR_FIX4k_C8000 0x269 -#define AMD_MTRR_FIX4k_D0000 0x26A -#define AMD_MTRR_FIX4k_D8000 0x26B -#define AMD_MTRR_FIX4k_E0000 0x26C -#define AMD_MTRR_FIX4k_E8000 0x26D -#define AMD_MTRR_FIX4k_F0000 0x26E -#define AMD_MTRR_FIX4k_F8000 0x26F - -#define AMD_MTRR_FIX64K_WB_DRAM 0x1E -#define AMD_MTRR_FIX64K_WT_DRAM 0x1C -#define AMD_MTRR_FIX64K_UC_DRAM 0x18 -#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1E -#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1C -#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818 -#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1E -#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1C -#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818 - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/// Allocate Heap Parameters -typedef struct _ALLOCATE_HEAP_PARAMS { - UINT32 RequestedBufferSize; ///< Size of buffer. - UINT32 BufferHandle; ///< An unique ID of buffer. - UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate. - UINT8 *BufferPtr; ///< Pointer to buffer. -} ALLOCATE_HEAP_PARAMS; - -/// Locate Heap Parameters -typedef struct _LOCATE_HEAP_PTR { - UINT32 BufferHandle; ///< An unique ID of buffer. - UINT32 BufferSize; ///< Data buffer size. - UINT8 *BufferPtr; ///< Pointer to buffer. -} LOCATE_HEAP_PTR; - -/// Heap Node Header -typedef struct _BUFFER_NODE { - UINT32 BufferHandle; ///< An unique ID of buffer. - UINT32 BufferSize; ///< Size of buffer. - UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate. - UINT8 PadSize; ///< Size of pad. - UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base). -} BUFFER_NODE; - -/// Heap Manager -typedef struct _HEAP_MANAGER { - UINT32 Signature; ///< a signature to indicate if the heap is valid. - UINT32 UsedSize; ///< Used size of heap. - UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer. - UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space. -} HEAP_MANAGER; - -/// AGESA Buffer Handles (These are reserved) -typedef enum { - AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine. - AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine. - AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine. - AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine. - AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine. - AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine. - AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine. - AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine. - AMD_S3_SAVE_HANDLE, ///< Assign 0x000A008 buffer handle to AmdS3Save routine. - AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine. - AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table - AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table - AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters. - AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode. - AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine. - AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine. - AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData - AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training - AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3 - AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3 - AMD_MEM_S3_MR0_DATA_HANDLE, ///< Assign 0x000A014 buffer handle to MR0 data block for S3 - AMD_UMA_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to be used for Uma information - AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A016 buffer handle to DMI Type16 17 19 20 information - HT_STATE_DATA_HANDLE, ///< Assign 0x000A017 buffer handle to HT State Data - PRESERVE_MAIL_BOX_HANDLE, ///< Assign 0x000A018 buffer handle for Preserve Mailbox Feature. - EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A019 buffer handle to Event Log - IDS_CONTROL_HANDLE, ///< Assign 0x000A01A buffer handle to AmdIds routine. - IDS_HT_DATA_HANDLE, ///< Assign 0x000A01B buffer handle to Ht IDS control - IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A01C buffer handle to be used for HDTOUT support. - IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01D buffer handle to Performance analysis - AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01F buffer handle to be used for PCIe support - AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A020 buffer handle to be used for GNB SMU configuration - AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A021 buffer handle to be used for TT fuse table - AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A022 buffer handle to be used for Gfx platform configuration - AMD_GNB_TEMP_DATA_HANDLE, ///< Assign 0x000A024 buffer handle for GNB general purpose data block - AMD_MEM____RDQS_HANDLE, ///< Assign 0x000A025 buffer handle for training - AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE, ///< Assign 0x000A026 buffer handle to be used for GNB IOMMU scratch memory - AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle - AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers. - AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE. - SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt' - NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node' - HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops' - LOCAL_AP_MAIL_BOX_CACHE_HANDLE = 0x414D4258, ///< 'ambx' - AMD_FCH_RESET_DATA_BLOCK_HANDLE = 0x46434852, ///< 'FCHR' Buffer handle for FCH private data block at InitReset - AMD_FCH_DATA_BLOCK_HANDLE = 0x46434845, ///< 'FCHE' Buffer handle for FCH private data block at InitEnv - IDS_REG_TABLE_HANDLE = 0x49524547, ///< 'IREG' Handle for IDS register table - IDS_SAVE_IDTR_HANDLE = 0x49445452, ///< 'IDTR' - IDS_BSC_IDT_HANDLE = 0x42534349, ///< 'BSCI' BSC Idt table - IDS_NV_TO_CMOS_HANDLE = 0x534D4349, ///< 'ICMS' Handle for IDS CMOS save - IDS_GRA_HANDLE = 0x41524749, ///< 'IGRA' Handle for IDS GRA save - IDS_EXTEND_HANDLE = 0x54584549 ///< 'IEXT' Handle for IDS extend module -} AGESA_BUFFER_HANDLE; - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -HeapManagerInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -HeapAllocateBuffer ( - IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -HeapDeallocateBuffer ( - IN UINT32 BufferHandle, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -HeapLocateBuffer ( - IN OUT LOCATE_HEAP_PTR *LocateHeap, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT64 -HeapGetBaseAddress ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -EventLogInitialization ( - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _HEAP_MANAGER_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdFch.h b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdFch.h deleted file mode 100644 index 579ad3db9e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdFch.h +++ /dev/null @@ -1,64 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD FCH Component - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _AMD_FCH_H_ -#define _AMD_FCH_H_ - -typedef AGESA_STATUS FCH_INIT (IN VOID *DataPtr); -typedef VOID FCH_TASK_ENTRY (IN VOID *FchCfg); - - -/// FCH API build options -typedef struct { - FCH_INIT *InitReset; ///< InitReset - FCH_INIT *InitResetConstructor; ///< InitResetConstructor - FCH_INIT *InitEnv; ///< InitEnv - FCH_INIT *InitEnvConstructor; ///< InitEnvConstructor - FCH_INIT *InitMid; ///< InitMid - FCH_INIT *InitMidConstructor; ///< InitMidConstructor - FCH_INIT *InitLate; ///< InitLate - FCH_INIT *InitLateConstructor; ///< InitLateConstructor -} BLDOPT_FCH_FUNCTION; - -#endif diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEarly.c deleted file mode 100644 index 090009b0ad..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEarly.c +++ /dev/null @@ -1,316 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuCacheInit.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "AdvancedApi.h" -#include "cpuServices.h" -#include "CommonInits.h" -#include "GnbInterface.h" -#include "Filecode.h" -#include "heapManager.h" -#include "CreateStruct.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_COMMON_AMDINITEARLY_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -EXECUTION_CACHE_REGION InitExeCacheMap[] = -{ - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000}, - {0x00000000, 0x00000000} -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdEarlyPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -AllocateExecutionCacheInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; -/*------------------------------------------------------------------------------------*/ -/** - * Initialize AmdInitEarly stage platform profile and user option input. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdEarlyPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CommonPlatformConfigInit (PlatformConfig, StdHeader); - - return AGESA_SUCCESS; -} -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that will be invoked by the wrapper to initialize the input - * structure for the AllocateExecutionCache. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] AmdExeAddrMapPtr Our Service interface struct - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AllocateExecutionCacheInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ) -{ - UINT8 i; - ASSERT (AmdExeAddrMapPtr != NULL); - - for (i = 0; i < MAX_CACHE_REGIONS; ++i) { - AmdExeAddrMapPtr[i].ExeCacheStartAddr = InitExeCacheMap[i].ExeCacheStartAddr; - AmdExeAddrMapPtr[i].ExeCacheSize = InitExeCacheMap[i].ExeCacheSize; - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * - * Initializer routine that will be invoked by the wrapper to initialize the input - * structure for the AmdInitEarly. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in,out] EarlyParams The service interface struct to initialize. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -AmdInitEarlyInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_EARLY_PARAMS *EarlyParams - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (EarlyParams != NULL); - - EarlyParams->StdHeader = *StdHeader; - - // We don't check any AGESA_STATUS from the called constructors, since they MUST all SUCCEED. - // - - AllocateExecutionCacheInitializer (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]); - - AmdHtInterfaceConstructor (&EarlyParams->StdHeader, &EarlyParams->HtConfig); - - AmdEarlyPlatformConfigInit (&EarlyParams->PlatformConfig, &EarlyParams->StdHeader); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Perform initialization services required at the Early Init POST time point. - * - * Execution Cache, HyperTransport, and AP Init advanced services are performed. - * - * @param[in] EarlyParams The interface struct for all early services - * - * @return The most severe AGESA_STATUS returned by any called service. - * - */ -AGESA_STATUS -AmdInitEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParams - ) -{ - AGESA_STATUS CalledAgesaStatus; - AGESA_STATUS EarlyInitStatus; - WARM_RESET_REQUEST Request; - UINT8 PrevRequestBit; - UINT8 PrevStateBits; - - AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader); - - EarlyInitStatus = AGESA_SUCCESS; - - // Setup ROM execution cache - IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start\n"); - CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]); - IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End\n"); - if (CalledAgesaStatus > EarlyInitStatus) { - EarlyInitStatus = CalledAgesaStatus; - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - { - extern CHAR8 *BldOptDebugOutput[]; - - UINT8 i; - for (i = 0; BldOptDebugOutput[i] != NULL; i++) { - IDS_HDT_CONSOLE (MAIN_FLOW, "\t%s\n", BldOptDebugOutput[i]); - } - } - ) - - // - // WARNING: AGESA's own IDT is at heap which would be moved from one place to another - // so we MUST restore IDT every time before moving heap. - // - IDS_EXCEPTION_TRAP (IDS_IDT_REPLACE_IDTR_FOR_BSC, NULL, &EarlyParams->StdHeader); - IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader); - ASSERT (EarlyParams != NULL); - PrevRequestBit = FALSE; - PrevStateBits = WR_STATE_COLD; - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: Start %x \n\n", PrevStateBits); - // If a previously requested warm reset cannot be triggered in the - // current stage, store the previous state of request and reset the - // request struct to the current post stage - GetWarmResetFlag (&EarlyParams->StdHeader, &Request); - if (Request.RequestBit == TRUE) { - if (Request.StateBits >= Request.PostStage) { - PrevRequestBit = Request.RequestBit; - PrevStateBits = Request.StateBits; - Request.RequestBit = FALSE; - Request.StateBits = Request.PostStage - 1; - SetWarmResetFlag (&EarlyParams->StdHeader, &Request); - } - } - - IDS_OPTION_HOOK (IDS_INIT_EARLY_BEFORE, EarlyParams, &EarlyParams->StdHeader); - - // Full Hypertransport Initialization - // IMPORTANT: All AP cores call Ht Init. HT Init handles full init for the BSC, and map init for APs. - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: Start\n"); - CalledAgesaStatus = AmdHtInitialize (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig, &EarlyParams->HtConfig); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: End\n"); - if (CalledAgesaStatus > EarlyInitStatus) { - EarlyInitStatus = CalledAgesaStatus; - } - - CalledAgesaStatus = GnbInitAtEarlier (EarlyParams); - if (CalledAgesaStatus > EarlyInitStatus) { - EarlyInitStatus = CalledAgesaStatus; - } - - // AP launch - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: Start\n"); - CalledAgesaStatus = AmdCpuEarly (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: End\n"); - if (CalledAgesaStatus > EarlyInitStatus) { - EarlyInitStatus = CalledAgesaStatus; - } - - // Warm Reset, should be at the end of AmdInitEarly - GetWarmResetFlag (&EarlyParams->StdHeader, &Request); - // If a warm reset is requested in the current post stage, trigger the - // warm reset and ignore the previous request - if (Request.RequestBit == TRUE) { - if (Request.StateBits < Request.PostStage) { - AgesaDoReset (WARM_RESET_WHENEVER, &EarlyParams->StdHeader); - } - } else { - // Otherwise, if there's a previous request, restore it - // so that the subsequent post stage can trigger the warm reset - if (PrevRequestBit == TRUE) { - Request.RequestBit = PrevRequestBit; - Request.StateBits = PrevStateBits; - SetWarmResetFlag (&EarlyParams->StdHeader, &Request); - } - } - - CalledAgesaStatus = GnbInitAtEarly (EarlyParams); - if (CalledAgesaStatus > EarlyInitStatus) { - EarlyInitStatus = CalledAgesaStatus; - } - // Check for Cache As Ram Corruption - IDS_CAR_CORRUPTION_CHECK (&EarlyParams->StdHeader); - - IDS_OPTION_HOOK (IDS_INIT_EARLY_AFTER, EarlyParams, &EarlyParams->StdHeader); - IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdInitEarlyExit, &EarlyParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: End\n\n"); - - // Flush out all debug contents in case warm reset is triggered after this point - IDS_HDT_CONSOLE_FLUSH_BUFFER (&EarlyParams->StdHeader); - - return EarlyInitStatus; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEnv.c deleted file mode 100644 index 4fdbda14f6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitEnv.c +++ /dev/null @@ -1,182 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuEnvInit.h" -#include "heapManager.h" -#include "GnbInterface.h" -#include "CommonInits.h" -#include "AmdFch.h" -#include "S3SaveState.h" -#include "Filecode.h" -#include "CreateStruct.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_COMMON_AMDINITENV_FILECODE - -extern BLDOPT_FCH_FUNCTION BldoptFchFunction; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/* - *--------------------------------------------------------------------------------------- - * - * Initializer routine that will be invoked by the wrapper - * to initialize the input structure for the AmdInitEnv - * - * @param[in,out] EnvParamsPtr Newly created interface parameters for AmdInitEnv - * - * @retval AGESA_SUCCESS Always succeeds - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitEnvInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (EnvParamsPtr != NULL); - - EnvParamsPtr->StdHeader = *StdHeader; - - CommonPlatformConfigInit (&EnvParamsPtr->PlatformConfig, &EnvParamsPtr->StdHeader); - BldoptFchFunction.InitEnvConstructor (EnvParamsPtr); - GnbInitDataStructAtEnvDef (&EnvParamsPtr->GnbEnvConfiguration, EnvParamsPtr); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_ENV function. - * - * This entry point is responsible for copying the heap contents from the - * temp RAM area to main memory. - * - * @param[in,out] EnvParams Required input parameters for the AMD_INIT_ENV - * entry point. - * - * @return Aggregated status across all internal AMD env calls invoked. - * - */ -AGESA_STATUS -AmdInitEnv ( - IN OUT AMD_ENV_PARAMS *EnvParams - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS AmdInitEnvStatus; - - AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader); - - ASSERT (EnvParams != NULL); - AmdInitEnvStatus = AGESA_SUCCESS; - - - //Copy Temp Ram heap content to Main Ram - AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader)); - if (AgesaStatus > AmdInitEnvStatus) { - AmdInitEnvStatus = AgesaStatus; - } - EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - EnvParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&EnvParams->StdHeader); - // Any heap allocate/deallocat/locate buffer should be used after heap is rebuild from here. - // After persist heaps are tansfer and rebuild, HeapLocateBuffer can start to be used in IDS hook. - - //Heap have been relocated, so Debug Print need be init again to get new address - IDS_HDT_CONSOLE_INIT (&EnvParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer End\n"); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEnv: Start\n\n"); - IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &EnvParams->PlatformConfig, &(EnvParams->StdHeader)); - IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader)); - - AgesaStatus = S3ScriptInit (&EnvParams->StdHeader); - if (AgesaStatus > AmdInitEnvStatus) { - AmdInitEnvStatus = AgesaStatus; - } - AgesaStatus = BldoptFchFunction.InitEnv (EnvParams); - AmdInitEnvStatus = (AgesaStatus > AmdInitEnvStatus) ? AgesaStatus : AmdInitEnvStatus; - - AgesaStatus = GnbInitAtEnv (EnvParams); - if (AgesaStatus > AmdInitEnvStatus) { - AmdInitEnvStatus = AgesaStatus; - } - - AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEnv: End\n"); - IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader); - return AmdInitEnvStatus; -} - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitLate.c deleted file mode 100644 index a62af89a13..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitLate.c +++ /dev/null @@ -1,296 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 55552 $ @e \$Date: 2011-06-22 09:31:58 -0600 (Wed, 22 Jun 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionDmi.h" -#include "OptionSlit.h" -#include "cpuLateInit.h" -#include "cpuFeatures.h" -#include "CommonInits.h" -#include "GnbInterface.h" -#include "OptionPstate.h" -#include "Filecode.h" -#include "heapManager.h" -#include "CreateStruct.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_COMMON_AMDINITLATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_DMI_CONFIGURATION OptionDmiConfiguration; // global user config record -extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration; // global user config record -extern OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdLatePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*------------------------------------------------------------------------------------*/ -/** - * Initialize AmdInitLate stage platform profile and user option input. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdLatePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CommonPlatformConfigInit (PlatformConfig, StdHeader); - - return AGESA_SUCCESS; -} - -/* - *--------------------------------------------------------------------------------------- - * - * AmdInitLateInitializer - * - * Initializer routine that will be invoked by the wrapper - * to initialize the input structure for the AmdInitLate - * - * @param[in, out] IN OUT AMD_LATE_PARAMS *LateParamsPtr - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitLateInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (LateParamsPtr != NULL); - - LateParamsPtr->StdHeader = *StdHeader; - - AmdLatePlatformConfigInit (&LateParamsPtr->PlatformConfig, &LateParamsPtr->StdHeader); - - LateParamsPtr->AcpiSlit = NULL; - - LateParamsPtr->AcpiSrat = NULL; - - LateParamsPtr->AcpiWheaMce = NULL; - LateParamsPtr->AcpiWheaCmc = NULL; - - LateParamsPtr->AcpiPState = NULL; - - LateParamsPtr->DmiTable = NULL; - - LateParamsPtr->AcpiAlib = NULL; - - LateParamsPtr->IvrsExclusionRangeList = UserOptions.CfgIvrsExclusionRangeList; - - return AGESA_SUCCESS; -} - -/* - *--------------------------------------------------------------------------------------- - * - * AmdInitLateDestructor - * - * Destruct routine that provide a chance if something need to be done - * before the end of AmdInitLate. - * - * @param[in] StdHeader The standard header. - * @param[in] LateParamsPtr AMD init late param. - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitLateDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_LATE_PARAMS *LateParamsPtr - ) -{ - - ASSERT (LateParamsPtr != NULL); - - (*(OptionDmiConfiguration.DmiReleaseBuffer)) (StdHeader); - (*(OptionSlitConfiguration.SlitReleaseBuffer)) (StdHeader); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_LATE function. - * - * This entry point is responsible for creating any desired ACPI tables, providing - * information for DMI, and to prepare the processors for the operating system - * bootstrap load process. - * - * @param[in,out] LateParams Required input parameters for the AMD_INIT_LATE - * entry point. - * - * @return Aggregated status across all internal AMD late calls invoked. - * - */ -AGESA_STATUS -AmdInitLate ( - IN OUT AMD_LATE_PARAMS *LateParams - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS AmdInitLateStatus; - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitLate: Start\n\n"); - AGESA_TESTPOINT (TpIfAmdInitLateEntry, &LateParams->StdHeader); - IDS_PERF_TIME_MEASURE (&LateParams->StdHeader); - - ASSERT (LateParams != NULL); - AmdInitLateStatus = AGESA_SUCCESS; - - IDS_OPTION_HOOK (IDS_INIT_LATE_BEFORE, LateParams, &LateParams->StdHeader); - - IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: Start\n"); - // _PSS, XPSS, _PCT, _PSD, _PPC, _CST, _CSD Tables - if ((LateParams->PlatformConfig.UserOptionPState) || (IsFeatureEnabled (IoCstate, &LateParams->PlatformConfig, &LateParams->StdHeader))) { - AgesaStatus = ((*(OptionPstateLateConfiguration.SsdtFeature)) (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiPState)); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - } - - // SRAT Table Generation - if (LateParams->PlatformConfig.UserOptionSrat) { - AgesaStatus = CreateAcpiSrat (&LateParams->StdHeader, &LateParams->AcpiSrat); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - } - - // SLIT Table Generation - if (LateParams->PlatformConfig.UserOptionSlit) { - AgesaStatus = CreateAcpiSlit (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiSlit); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - } - - // WHEA Table Generation - if (LateParams->PlatformConfig.UserOptionWhea) { - AgesaStatus = CreateAcpiWhea (&LateParams->StdHeader, &LateParams->AcpiWheaMce, &LateParams->AcpiWheaCmc); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - } - - // DMI Table Generation - if (LateParams->PlatformConfig.UserOptionDmi) { - AgesaStatus = CreateDmiRecords (&LateParams->StdHeader, &LateParams->DmiTable); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - } - IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: End\n"); - - // Cpu Features - IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateStart\n"); - AgesaStatus = DispatchCpuFeatures (CPU_FEAT_INIT_LATE_END, &LateParams->PlatformConfig, &LateParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateEnd\n"); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - - // It is the last function run by the AGESA CPU module and prepares the processor - // for the operating system bootstrap load process. - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: Start\n"); - AgesaStatus = AmdCpuLate (&LateParams->StdHeader, &LateParams->PlatformConfig); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: End\n"); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - - AgesaStatus = GnbInitAtLate (LateParams); - if (AgesaStatus > AmdInitLateStatus) { - AmdInitLateStatus = AgesaStatus; - } - - IDS_OPTION_HOOK (IDS_INIT_LATE_AFTER, LateParams, &LateParams->StdHeader); - IDS_PERF_TIME_MEASURE (&LateParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdInitLateExit, &LateParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitLate: End\n\n"); - AGESA_TESTPOINT (EndAgesaTps, &LateParams->StdHeader); -//End Debug Print Service - IDS_HDT_CONSOLE_EXIT (&LateParams->StdHeader); - return AmdInitLateStatus; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitMid.c deleted file mode 100644 index 03620549cb..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitMid.c +++ /dev/null @@ -1,170 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuFeatures.h" -#include "CommonInits.h" -#include "GnbInterface.h" -#include "AmdFch.h" -#include "Filecode.h" -#include "heapManager.h" -#include "CreateStruct.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_COMMON_AMDINITMID_FILECODE - -extern BLDOPT_FCH_FUNCTION BldoptFchFunction; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/* - *--------------------------------------------------------------------------------------- - * - * Initializer routine that will be invoked by the wrapper - * to initialize the input structure for the AmdInitMid - * - * @param[in,out] MidParamsPtr Newly created interface parameters for AmdInitMid - * - * @retval AGESA_SUCCESS Always succeeds - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitMidInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_MID_PARAMS *MidParamsPtr - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (MidParamsPtr != NULL); - - MidParamsPtr->StdHeader = *StdHeader; - CommonPlatformConfigInit (&MidParamsPtr->PlatformConfig, &MidParamsPtr->StdHeader); - BldoptFchFunction.InitMidConstructor (MidParamsPtr); - - return AGESA_SUCCESS; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_MID function. - * - * This entry point is responsible for performing any necessary functions needed - * after PCI bus enumeration and just before control is passed to the video option ROM. - * - * @param[in,out] MidParams Required input parameters for the AMD_INIT_MID - * entry point. - * - * @return Aggregated status across all internal AMD mid calls invoked. - * - */ -AGESA_STATUS -AmdInitMid ( - IN OUT AMD_MID_PARAMS *MidParams - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS CalledStatus; - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitMid: Start\n\n"); - AGESA_TESTPOINT (TpIfAmdInitMidEntry, &MidParams->StdHeader); - IDS_PERF_TIME_MEASURE (&MidParams->StdHeader); - - AgesaStatus = AGESA_SUCCESS; - - ASSERT (MidParams != NULL); - IDS_OPTION_HOOK (IDS_INIT_MID_BEFORE, MidParams, &MidParams->StdHeader); - - IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidStart\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_INIT_MID_END, &MidParams->PlatformConfig, &MidParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidEnd\n"); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - - CalledStatus = BldoptFchFunction.InitMid (MidParams); - AgesaStatus = (CalledStatus > AgesaStatus) ? CalledStatus : AgesaStatus; - - CalledStatus = GnbInitAtMid (MidParams); - if (CalledStatus > AgesaStatus) { - AgesaStatus = CalledStatus; - } - - IDS_OPTION_HOOK (IDS_INIT_MID_AFTER, MidParams, &MidParams->StdHeader); - - IDS_PERF_TIME_MEASURE (&MidParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdInitMidExit, &MidParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitMid: End\n\n"); - IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader); - return AgesaStatus; -} - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitPost.c deleted file mode 100644 index 415b33dd12..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitPost.c +++ /dev/null @@ -1,341 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "mm.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuPostInit.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CommonInits.h" -#include "cpuServices.h" -#include "GnbInterface.h" -#include "Filecode.h" -#include "CreateStruct.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_COMMON_AMDINITPOST_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdPostPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/*------------------------------------------------------------------------------------*/ -/** - * Initialize AmdInitPost stage platform profile and user option input. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdPostPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CommonPlatformConfigInit (PlatformConfig, StdHeader); - - return AGESA_SUCCESS; -} - -/* - *--------------------------------------------------------------------------------------- - * - * AmdInitPostInitializer - * - * Initializer routine that will be invoked by the wrapper - * to initialize the input structure for the AmdInitPost - * - * @param[in, out] IN OUT AMD_POST_PARAMS *PostParamsPtr - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitPostInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - AGESA_STATUS AgesaStatus; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - ASSERT (StdHeader != NULL); - ASSERT (PostParamsPtr != NULL); - - PostParamsPtr->StdHeader = *StdHeader; - - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &PostParamsPtr->StdHeader); - - if (AgesaStatus == AGESA_SUCCESS) { - PostParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr; - PostParamsPtr->MemConfig.MemData->ParameterListPtr = &(PostParamsPtr->MemConfig); - PostParamsPtr->MemConfig.MemData->StdHeader = PostParamsPtr->StdHeader; - AmdPostPlatformConfigInit (&PostParamsPtr->PlatformConfig, &PostParamsPtr->StdHeader); - AmdMemInitDataStructDef (PostParamsPtr->MemConfig.MemData, &PostParamsPtr->PlatformConfig); - } - return AgesaStatus; -} - -/* - *--------------------------------------------------------------------------------------- - * - * AmdInitPostDestructor - * - * Destruct routine that provide a chance if something need to be done - * before the end of AmdInitPost. - * - * @param[in] StdHeader The standard header. - * @param[in] PostParamsPtr AMD init post param. - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitPostDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_POST_PARAMS *PostParamsPtr - ) -{ - - ASSERT (PostParamsPtr != NULL); - - PostParamsPtr->StdHeader = *StdHeader; - PostParamsPtr->MemConfig.MemData->StdHeader = *StdHeader; - - // - // AmdMemAuto completed. Here, release heap space which is used for memory init. - // - MemAmdFinalize (PostParamsPtr->MemConfig.MemData); - HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - - // - // AmdCpuPost completed. - // - if (PostParamsPtr->MemConfig.SysLimit != 0) { - // WBINVD can only be executed when memory is available - FinalizeAtPost (StdHeader); - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_POST function. - * - * This entry point is responsible for initializing all system memory, - * gathering important data out of the pre-memory cache storage into a - * temporary holding buffer in main memory. After that APs will be - * shutdown in preparation for the host environment to take control. - * Note: pre-memory stack will be disabled also. - * - * @param[in,out] PostParams Required input parameters for the AMD_INIT_POST - * entry point. - * - * @return Aggregated status across all internal AMD POST calls invoked. - * - */ -AGESA_STATUS -AmdInitPost ( - IN OUT AMD_POST_PARAMS *PostParams - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS AmdInitPostStatus; - WARM_RESET_REQUEST Request; - UINT8 PrevRequestBit; - UINT8 PrevStateBits; - - AGESA_TESTPOINT (TpIfAmdInitPostEntry, &PostParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitPost: Start\n\n"); - IDS_PERF_TIME_MEASURE (&PostParams->StdHeader); - - ASSERT (PostParams != NULL); - AmdInitPostStatus = AGESA_SUCCESS; - PrevRequestBit = FALSE; - PrevStateBits = WR_STATE_COLD; - - IDS_OPTION_HOOK (IDS_INIT_POST_BEFORE, PostParams, &PostParams->StdHeader); - - // If a previously requested warm reset cannot be triggered in the - // current stage, store the previous state of request and reset the - // request struct to the current post stage - GetWarmResetFlag (&PostParams->StdHeader, &Request); - if (Request.RequestBit == TRUE) { - if (Request.StateBits >= Request.PostStage) { - PrevRequestBit = Request.RequestBit; - PrevStateBits = Request.StateBits; - Request.RequestBit = FALSE; - Request.StateBits = Request.PostStage - 1; - SetWarmResetFlag (&PostParams->StdHeader, &Request); - } - } - - AgesaStatus = GnbInitAtPost (PostParams); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: Start\n"); - AgesaStatus = AmdMemAuto (PostParams->MemConfig.MemData); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: End\n"); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - - if (AgesaStatus != AGESA_FATAL) { - - // Check BIST status - AgesaStatus = CheckBistStatus (&PostParams->StdHeader); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - - // - // P-State data gathered, then, Relinquish APs - // - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: Start\n"); - AgesaStatus = AmdCpuPost (&PostParams->StdHeader, &PostParams->PlatformConfig); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: End\n"); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - - // Warm Reset - GetWarmResetFlag (&PostParams->StdHeader, &Request); - // If a warm reset is requested in the current post stage, trigger the - // warm reset and ignore the previous request - if (Request.RequestBit == TRUE) { - if (Request.StateBits < Request.PostStage) { - AgesaDoReset (WARM_RESET_WHENEVER, &PostParams->StdHeader); - } - } else { - // Otherwise, if there's a previous request, restore it - // so that the subsequent post stage can trigger the warm reset - if (PrevRequestBit == TRUE) { - Request.RequestBit = PrevRequestBit; - Request.StateBits = PrevStateBits; - SetWarmResetFlag (&PostParams->StdHeader, &Request); - } - } - - AgesaStatus = GnbInitAtPostAfterDram (PostParams); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - - IDS_OPTION_HOOK (IDS_INIT_POST_AFTER, PostParams, &PostParams->StdHeader); - - IDS_PERF_TIME_MEASURE (&PostParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdInitPostExit, &PostParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitPost: End\n\n"); - IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer Start ...\n\n"); - - //For Heap will be relocate to new address in next stage, flush out debug print buffer if needed - IDS_HDT_CONSOLE_FLUSH_BUFFER (&PostParams->StdHeader); - - // WARNING: IDT will be moved from local cache to temp memory, so restore IDTR for BSP here - IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &PostParams->StdHeader); - // Copies BSP heap content to RAM, and it should be at the end of AmdInitPost - AgesaStatus = CopyHeapToTempRamAtPost (&(PostParams->StdHeader)); - if (AgesaStatus > AmdInitPostStatus) { - AmdInitPostStatus = AgesaStatus; - } - PostParams->StdHeader.HeapStatus = HEAP_TEMP_MEM; - } - // Check for Cache As Ram Corruption - IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader); - - // At the end of AmdInitPost, set StateBits to POST to allow any warm reset that occurs outside - // of AGESA to be recognized by IsWarmReset() - GetWarmResetFlag (&PostParams->StdHeader, &Request); - Request.StateBits = Request.PostStage; - SetWarmResetFlag (&PostParams->StdHeader, &Request); - - return AmdInitPostStatus; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c deleted file mode 100644 index 7013f67fd8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitReset.c +++ /dev/null @@ -1,253 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuCacheInit.h" -#include "cpuServices.h" -#include "AdvancedApi.h" -#include "GeneralServices.h" -#include "OptionsHt.h" -#include "AmdFch.h" -#include "Filecode.h" -#include "heapManager.h" -#include "CreateStruct.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_COMMON_AMDINITRESET_FILECODE - -extern BLDOPT_FCH_FUNCTION BldoptFchFunction; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CONST OPTION_HT_INIT_RESET HtOptionInitReset; -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdInitResetExecutionCacheAllocateInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that will be invoked by the wrapper to initialize the input - * structure for the AllocateExecutionCache. - * - * Parameters: - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] AmdExeAddrMapPtr Our Service interface struct - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdInitResetExecutionCacheAllocateInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr - ) -{ - ASSERT (AmdExeAddrMapPtr != NULL); - - LibAmdMemFill (AmdExeAddrMapPtr, 0, sizeof (EXECUTION_CACHE_REGION) * MAX_CACHE_REGIONS, StdHeader); - - return AGESA_SUCCESS; -} -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_RESET function. - * - * This entry point is responsible for establishing the HT links to the program - * ROM and for performing basic processor initialization. - * - * @param[in,out] ResetParams Required input parameters for the AMD_INIT_RESET - * entry point. - * - * @return Aggregated status across all internal AMD reset calls invoked. - * - */ -AGESA_STATUS -AmdInitReset ( - IN OUT AMD_RESET_PARAMS *ResetParams - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS CalledAgesaStatus; - WARM_RESET_REQUEST Request; - UINT8 PrevRequestBit; - UINT8 PrevStateBits; - - AgesaStatus = AGESA_SUCCESS; - - // Setup ROM execution cache - CalledAgesaStatus = AllocateExecutionCache (&ResetParams->StdHeader, &ResetParams->CacheRegion[0]); - if (CalledAgesaStatus > AgesaStatus) { - AgesaStatus = CalledAgesaStatus; - } - - // IDS_EXTENDED_HOOK (IDS_INIT_RESET_BEFORE, NULL, NULL, &ResetParams->StdHeader); - - // Init Debug Print function - IDS_HDT_CONSOLE_INIT (&ResetParams->StdHeader); - - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n"); - - IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", (CHAR8 *)&UserOptions.VersionString); - - AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader); - ASSERT (ResetParams != NULL); - - PrevRequestBit = FALSE; - PrevStateBits = WR_STATE_COLD; - - if (IsBsp (&ResetParams->StdHeader, &AgesaStatus)) { - CalledAgesaStatus = BldoptFchFunction.InitReset (ResetParams); - AgesaStatus = (CalledAgesaStatus > AgesaStatus) ? CalledAgesaStatus : AgesaStatus; - } - - // If a previously requested warm reset cannot be triggered in the - // current stage, store the previous state of request and reset the - // request struct to the current post stage - GetWarmResetFlag (&ResetParams->StdHeader, &Request); - if (Request.RequestBit == TRUE) { - if (Request.StateBits >= Request.PostStage) { - PrevRequestBit = Request.RequestBit; - PrevStateBits = Request.StateBits; - Request.RequestBit = FALSE; - Request.StateBits = Request.PostStage - 1; - SetWarmResetFlag (&ResetParams->StdHeader, &Request); - } - } - - // Initialize the PCI MMIO access mechanism - InitializePciMmio (&ResetParams->StdHeader); - - // Initialize Hyper Transport Registers - if (HtOptionInitReset.HtInitReset != NULL) { - IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: Start\n"); - CalledAgesaStatus = HtOptionInitReset.HtInitReset (&ResetParams->StdHeader, &ResetParams->HtConfig); - IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: End\n"); - if (CalledAgesaStatus > AgesaStatus) { - AgesaStatus = CalledAgesaStatus; - } - } - - // Warm Reset, should be at the end of AmdInitReset - GetWarmResetFlag (&ResetParams->StdHeader, &Request); - // If a warm reset is requested in the current post stage, trigger the - // warm reset and ignore the previous request - if (Request.RequestBit == TRUE) { - if (Request.StateBits < Request.PostStage) { - AgesaDoReset (WARM_RESET_WHENEVER, &ResetParams->StdHeader); - } - } else { - // Otherwise, if there's a previous request, restore it - // so that the subsequent post stage can trigger the warm reset - if (PrevRequestBit == TRUE) { - Request.RequestBit = PrevRequestBit; - Request.StateBits = PrevStateBits; - SetWarmResetFlag (&ResetParams->StdHeader, &Request); - } - } - // Check for Cache As Ram Corruption - IDS_CAR_CORRUPTION_CHECK (&ResetParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: End\n\n"); - - AGESA_TESTPOINT (TpIfAmdInitResetExit, &ResetParams->StdHeader); - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Initialize defaults and options for Amd Init Reset. - * - * @param[in] StdHeader Header - * @param[in] AmdResetParams The Reset Init interface to initialize. - * - * @retval AGESA_SUCCESS Always Succeeds. - */ -AGESA_STATUS -AmdInitResetConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_RESET_PARAMS *AmdResetParams - ) -{ - ASSERT (AmdResetParams != NULL); - - AmdResetParams->StdHeader = *StdHeader; - - AmdInitResetExecutionCacheAllocateInitializer (&AmdResetParams->StdHeader, &AmdResetParams->CacheRegion[0]); - // Initialize Hyper Transport input structure - if (HtOptionInitReset.HtResetConstructor != NULL) { - HtOptionInitReset.HtResetConstructor (&AmdResetParams->StdHeader, &AmdResetParams->HtConfig); - } - BldoptFchFunction.InitResetConstructor (AmdResetParams); - - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitResume.c deleted file mode 100644 index 02d85ac977..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdInitResume.c +++ /dev/null @@ -1,239 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "Filecode.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuPostInit.h" -#include "CommonInits.h" -#include "cpuFeatures.h" -#include "heapManager.h" -#include "CreateStruct.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_COMMON_AMDINITRESUME_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_INIT_RESUME function. - * - * This entry point is responsible for performing silicon device and memory - * re-initialization for the resume boot path. - * - * @param[in] ResumeParams Required input parameters for the AMD_INIT_RESUME - * entry point. - * - * @return Aggregated status across all internal AMD resume calls invoked. - * - */ -AGESA_STATUS -AmdInitResume ( - IN AMD_RESUME_PARAMS *ResumeParams - ) -{ - VOID *OrMaskPtr; - AGESA_STATUS ReturnStatus; - AGESA_STATUS AmdInitResumeStatus; - BSC_AP_MSR_SYNC ApMsrSync[4]; - - AGESA_TESTPOINT (TpIfAmdInitResumeEntry, &ResumeParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitResume Start\n"); - - AmdInitResumeStatus = AGESA_SUCCESS; - - ASSERT (ResumeParams != NULL); - - if (ResumeParams->S3DataBlock.NvStorage != NULL) { - - MemS3ResumeInitNB (&ResumeParams->StdHeader); - - // Restore registers before exiting self refresh - RestorePreESRContext (&OrMaskPtr, - ResumeParams->S3DataBlock.NvStorage, - INIT_RESUME, - &ResumeParams->StdHeader); - // Exit self refresh - ReturnStatus = AmdMemS3Resume (&ResumeParams->StdHeader); - if (ReturnStatus > AmdInitResumeStatus) { - AmdInitResumeStatus = ReturnStatus; - } - if (ReturnStatus == AGESA_SUCCESS) { - - // Restore registers after exiting self refresh - RestorePostESRContext (OrMaskPtr, - ResumeParams->S3DataBlock.NvStorage, - INIT_RESUME, - &ResumeParams->StdHeader); - - ApMsrSync[0].RegisterAddress = SYS_CFG; - ApMsrSync[1].RegisterAddress = TOP_MEM; - ApMsrSync[2].RegisterAddress = TOP_MEM2; - ApMsrSync[3].RegisterAddress = 0; - SyncApMsrsToBsc (ApMsrSync, &ResumeParams->StdHeader); - - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after S3 AP MTRR sync\n"); - ReturnStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_RESUME_MTRR_SYNC, &ResumeParams->PlatformConfig, &ResumeParams->StdHeader); - if (ReturnStatus > AmdInitResumeStatus) { - AmdInitResumeStatus = ReturnStatus; - } - } - } - - // Set TscFreqSel at the rate specified by the core P0 - SetCoresTscFreqSel (&ResumeParams->StdHeader); - - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitResume End\n"); - // HDT out of All Aps - IDS_HDT_CONSOLE_FLUSH_BUFFER (&ResumeParams->StdHeader); - // Relinquish control of all APs to IBV - RelinquishControlOfAllAPs (&ResumeParams->StdHeader); - - // Restore IDT - IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &ResumeParams->StdHeader); - IDS_OPTION_HOOK (IDS_AFTER_S3_RESUME, NULL, &ResumeParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdInitResumeExit, &ResumeParams->StdHeader); - return (AmdInitResumeStatus); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Constructor for the AMD_INIT_RESUME function. - * - * This routine is responsible for setting default values for the - * input parameters needed by the AMD_INIT_RESUME entry point. - * - * @param[in] StdHeader The standard header. - * @param[in,out] ResumeParams Required input parameters for the AMD_INIT_RESUME - * entry point. - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdInitResumeInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_RESUME_PARAMS *ResumeParams - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (ResumeParams != NULL); - - ResumeParams->StdHeader = *StdHeader; - - AmdS3ParamsInitializer (&ResumeParams->S3DataBlock); - CommonPlatformConfigInit (&ResumeParams->PlatformConfig, &ResumeParams->StdHeader); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Destructor for the AMD_INIT_RESUME function. - * - * This routine is responsible for deallocation of heap space allocated during - * AMD_INIT_RESUME entry point. - * - * @param[in] StdHeader The standard header. - * @param[in,out] ResumeParams Required input parameters for the AMD_INIT_RESUME - * entry point. - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -AmdInitResumeDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_RESUME_PARAMS *ResumeParams - ) -{ - AGESA_STATUS ReturnStatus; - AGESA_STATUS RetVal; - - ASSERT (ResumeParams != NULL); - - ReturnStatus = AGESA_SUCCESS; - - // Deallocate heap space allocated during memory S3 resume - RetVal = MemS3Deallocate (&ResumeParams->StdHeader); - if (RetVal > ReturnStatus) { - ReturnStatus = RetVal; - } - - return ReturnStatus; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdLateRunApTask.c deleted file mode 100644 index d14f2160e2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdLateRunApTask.c +++ /dev/null @@ -1,158 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Options.h" -#include "Filecode.h" -#include "heapManager.h" -#include "CreateStruct.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_COMMON_AMDLATERUNAPTASK_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern CONST DISPATCH_TABLE ApDispatchTable[]; - -/*---------------------------------------------------------------------------------------*/ -/** - * Application Processor perform a function as directed by the BSC. - * - * This is needed for an AP task that must run after AGESA has relinquished control - * of the APs to the IBV. - * - * @param[in] AmdApExeParams The interface struct for any required routine. - * - * @return The most severe AGESA_STATUS returned by any called service. Note - * that this will be the return value passed back to the BSC as the - * return value for the call out. - * - */ -AGESA_STATUS -AmdLateRunApTask ( - IN AP_EXE_PARAMS *AmdApExeParams - ) -{ - AGESA_STATUS CalledAgesaStatus; - AGESA_STATUS ApLateTaskStatus; - DISPATCH_TABLE *Entry; - - AGESA_TESTPOINT (TpIfAmdLateRunApTaskEntry, &AmdApExeParams->StdHeader); - - ASSERT (AmdApExeParams != NULL); - ApLateTaskStatus = AGESA_SUCCESS; - CalledAgesaStatus = AGESA_UNSUPPORTED; - - // Dispatch, if valid - Entry = (DISPATCH_TABLE *) ApDispatchTable; - while (Entry->FunctionId != 0) { - if (AmdApExeParams->FunctionNumber == Entry->FunctionId) { - CalledAgesaStatus = Entry->EntryPoint (AmdApExeParams); - break; - } - Entry++; - } - - if (CalledAgesaStatus > ApLateTaskStatus) { - ApLateTaskStatus = CalledAgesaStatus; - } - - AGESA_TESTPOINT (TpIfAmdLateRunApTaskExit, &AmdApExeParams->StdHeader); - return ApLateTaskStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Constructor for the AMD_LATE_RUN_AP_TASK function. - * - * This routine is responsible for setting default values for the - * input parameters needed by the AMD_S3_SAVE entry point. - * - * @param[in] StdHeader The standard header. - * @param[in,out] AmdApExeParams Required input parameters for the AMD_LATE_RUN_AP_TASK - * entry point. - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdLateRunApTaskInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AP_EXE_PARAMS *AmdApExeParams - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (AmdApExeParams != NULL); - - AmdApExeParams->StdHeader = *StdHeader; - AmdApExeParams->FunctionNumber = 0; - AmdApExeParams->RelatedDataBlock = NULL; - AmdApExeParams->RelatedBlockLength = 0; - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c deleted file mode 100644 index e293d46ade..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3LateRestore.c +++ /dev/null @@ -1,218 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 55570 $ @e \$Date: 2011-06-22 14:21:24 -0600 (Wed, 22 Jun 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "S3.h" -#include "cpuFeatures.h" -#include "S3SaveState.h" -#include "CommonInits.h" -#include "Filecode.h" -#include "heapManager.h" -#include "CreateStruct.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_COMMON_AMDS3LATERESTORE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdS3LateRestorePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_S3LATE_RESTORE function. - * - * This entry point is responsible for restoring saved registers and preparing the - * silicon components for OS restart. - * - * @param[in,out] S3LateParams Required input parameters for the AMD_S3LATE_RESTORE - * entry point. - * - * @return Aggregated status across all internal AMD S3 late restore calls invoked. - * - */ -AGESA_STATUS -AmdS3LateRestore ( - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ) -{ - UINT8 *BufferPointer; - VOID *OrMaskPtr; - VOID *LateContextPtr; - AGESA_STATUS ReturnStatus; - AGESA_STATUS CalledStatus; - - AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader); - - ReturnStatus = AGESA_SUCCESS; - - ASSERT (S3LateParams != NULL); - - BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage; - S3LateParams->StdHeader.HeapBasePtr = (UINT64) (intptr_t) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset]; - ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0); - - IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "AmdS3LateRestore: Start\n\n"); - - IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader); - IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader)); - - if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) { - LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset]; - // Restore registers before exiting self refresh - RestorePreESRContext (&OrMaskPtr, - LateContextPtr, - S3_LATE_RESTORE, - &S3LateParams->StdHeader); - // Restore registers after exiting self refresh - RestorePostESRContext (OrMaskPtr, - LateContextPtr, - S3_LATE_RESTORE, - &S3LateParams->StdHeader); - } - - // Dispatch any features needing to run at this time point - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features at S3 late restore end\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END, - &S3LateParams->PlatformConfig, - &S3LateParams->StdHeader); - if (CalledStatus > ReturnStatus) { - ReturnStatus = CalledStatus; - } - - CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader); - if (CalledStatus > ReturnStatus) { - ReturnStatus = CalledStatus; - } - - IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader); - IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdS3LateRestore: End\n\n"); - IDS_HDT_CONSOLE_S3_EXIT (&S3LateParams->StdHeader); - return ReturnStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Constructor for the AMD_S3LATE_RESTORE function. - * - * This routine is responsible for setting default values for the - * input parameters needed by the AMD_S3LATE_RESTORE entry point. - * - * @param[in] StdHeader AMD standard header config param. - * @param[in,out] S3LateParams Required input parameters for the - * AMD_S3LATE_RESTORE entry point. - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdS3LateRestoreInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (S3LateParams != NULL); - - S3LateParams->StdHeader = *StdHeader; - - AmdS3ParamsInitializer (&S3LateParams->S3DataBlock); - - AmdS3LateRestorePlatformConfigInit (&S3LateParams->PlatformConfig, &S3LateParams->StdHeader); - - return AGESA_SUCCESS; -} - -/*------------------------------------------------------------------------------------*/ -/** - * Initialize AmdS3LateRestore stage platform profile and user option input. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdS3LateRestorePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CommonPlatformConfigInit (PlatformConfig, StdHeader); - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c deleted file mode 100644 index 59059a382c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/AmdS3Save.c +++ /dev/null @@ -1,388 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Basic Level Public APIs - * - * Contains basic Level Initialization routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Interface - * @e \$Revision: 55552 $ @e \$Date: 2011-06-22 09:31:58 -0600 (Wed, 22 Jun 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "CommonInits.h" -#include "AmdFch.h" -#include "Filecode.h" -#include "heapManager.h" -#include "CreateStruct.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_COMMON_AMDS3SAVE_FILECODE - -extern BLDOPT_FCH_FUNCTION BldoptFchFunction; - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -CONST UINT32 ROMDATA S3LateHeapTable[] = -{ - EVENT_LOG_BUFFER_HANDLE, - SOCKET_DIE_MAP_HANDLE, - NODE_ID_MAP_HANDLE, - LOCAL_AP_MAIL_BOX_CACHE_HANDLE, - IDS_CONTROL_HANDLE, - AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, - AMD_PCIE_COMPLEX_DATA_HANDLE -}; - -#define S3LATE_TABLE_SIZE (sizeof (S3LateHeapTable) / sizeof (UINT32)) //(sizeof (S3LateHeapTable) / sizeof (S3LATE_HEAP_ELEMENT)) - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdS3SavePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------*/ -/** - * Main entry point for the AMD_S3_SAVE function. - * - * This entry point is responsible for saving silicon component registers to the - * SMM save area in preparation of entering system suspend-to-RAM mode. - * - * @param[in,out] AmdS3SaveParams Required input parameters for the AMD_S3_SAVE - * entry point. - * - * @return Aggregated status across all internal AMD S3 save calls invoked. - * - */ -AGESA_STATUS -AmdS3Save ( - IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams - ) -{ - UINTN i; - UINT32 EarlyBufferSize; - UINT32 LateBufferSize; - UINT32 LateContextSize; - UINT32 HeapSize; - UINT8 *BufferPointer; - UINT8 HeapStatus; - ALLOCATE_HEAP_PARAMS HeapParams; - LOCATE_HEAP_PTR LocateHeap; - BUFFER_NODE *FreeSpaceNode; - ALLOCATE_HEAP_PARAMS AllocParams; - DEVICE_BLOCK_HEADER *MemoryRelatedDeviceList; - DEVICE_BLOCK_HEADER *NonMemoryRelatedDeviceList; - AGESA_STATUS ReturnStatus; - VOID *HeapPtrs[S3LATE_TABLE_SIZE]; - UINT32 HeapSizes[S3LATE_TABLE_SIZE]; - UINT32 HeapBuffersPresent; - HEAP_MANAGER *HeapPtr; - - AGESA_TESTPOINT (TpIfAmdS3SaveEntry, &AmdS3SaveParams->StdHeader); - - ASSERT (AmdS3SaveParams != NULL); - - HeapBuffersPresent = 0; - EarlyBufferSize = 0; - LateBufferSize = 0; - LateContextSize = 0; - HeapSize = 0; - NonMemoryRelatedDeviceList = NULL; - MemoryRelatedDeviceList = NULL; - ReturnStatus = AGESA_SUCCESS; - - IDS_SKIP_HOOK (IDS_BEFORE_S3_SAVE, AmdS3SaveParams, &(AmdS3SaveParams->StdHeader)) { - - // Get memory device list - MemFS3GetDeviceList (&MemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader); - if (MemoryRelatedDeviceList != NULL) { - // Determine size needed - EarlyBufferSize = GetWorstCaseContextSize (MemoryRelatedDeviceList, INIT_RESUME, &AmdS3SaveParams->StdHeader); - } - - if (UserOptions.CfgS3LateRestore) { - for (i = 0; i < S3LATE_TABLE_SIZE; i++) { - LocateHeap.BufferHandle = S3LateHeapTable[i]; - if (HeapLocateBuffer (&LocateHeap, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) { - HeapBuffersPresent++; - HeapSize += LocateHeap.BufferSize; - HeapPtrs[i] = LocateHeap.BufferPtr; - HeapSizes[i] = LocateHeap.BufferSize; - } else { - HeapPtrs[i] = NULL; - HeapSizes[i] = 0; - } - } - - // Determine heap data size requirements - if (HeapBuffersPresent != 0) { - HeapSize += ((sizeof (HEAP_MANAGER)) + (HeapBuffersPresent * ((sizeof (BUFFER_NODE)) + (NUM_OF_SENTINEL * SIZE_OF_SENTINEL) + 0xF))); // reserve 0xF per buffer node for 16 byte alignment - } - - // Get non memory device list - GetNonMemoryRelatedDeviceList (&NonMemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader); - - if (NonMemoryRelatedDeviceList != NULL) { - // Determine size needed - LateContextSize = GetWorstCaseContextSize (NonMemoryRelatedDeviceList, S3_LATE_RESTORE, &AmdS3SaveParams->StdHeader); - } - LateBufferSize = HeapSize + LateContextSize; - if (LateBufferSize != 0) { - LateBufferSize += sizeof (S3_VOLATILE_STORAGE_HEADER); - } - } - - if ((EarlyBufferSize != 0) || (LateBufferSize != 0)) { - // - // Allocate a buffer - // - AllocParams.RequestedBufferSize = EarlyBufferSize + LateBufferSize; - AllocParams.BufferHandle = AMD_S3_INFO_BUFFER_HANDLE; - AllocParams.Persist = 0; - - AGESA_TESTPOINT (TpIfBeforeAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader); - if (HeapAllocateBuffer (&AllocParams, &AmdS3SaveParams->StdHeader) != AGESA_SUCCESS) { - if (AGESA_ERROR > ReturnStatus) { - ReturnStatus = AGESA_ERROR; - } - } - AGESA_TESTPOINT (TpIfAfterAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader); - - if (EarlyBufferSize != 0) { - AmdS3SaveParams->S3DataBlock.NvStorage = AllocParams.BufferPtr; - SaveDeviceListContext (MemoryRelatedDeviceList, - AmdS3SaveParams->S3DataBlock.NvStorage, - INIT_RESUME, - &EarlyBufferSize, - &AmdS3SaveParams->StdHeader); - - AmdS3SaveParams->S3DataBlock.NvStorageSize = EarlyBufferSize; - } - - if (LateBufferSize != 0) { - BufferPointer = AllocParams.BufferPtr; - AmdS3SaveParams->S3DataBlock.VolatileStorage = &(BufferPointer[EarlyBufferSize]); - - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = 0; - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapSize = HeapSize; - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = 0; - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataSize = LateContextSize; - - if (HeapSize != 0) { - // Transfer heap contents - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = sizeof (S3_VOLATILE_STORAGE_HEADER); - HeapPtr = (HEAP_MANAGER *) &BufferPointer[EarlyBufferSize + sizeof (S3_VOLATILE_STORAGE_HEADER)]; - HeapPtr->UsedSize = sizeof (HEAP_MANAGER); - HeapPtr->Signature = HEAP_SIGNATURE_VALID; - HeapPtr->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; - HeapPtr->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); - FreeSpaceNode = (BUFFER_NODE *) ((UINT8 *) HeapPtr + sizeof (HEAP_MANAGER)); - FreeSpaceNode->BufferSize = HeapSize - sizeof (HEAP_MANAGER) - sizeof (BUFFER_NODE); - FreeSpaceNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; - - HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus; - AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME; - AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) (intptr_t) HeapPtr; - - for (i = 0; i < S3LATE_TABLE_SIZE; i++) { - if (HeapPtrs[i] != NULL) { - HeapParams.RequestedBufferSize = HeapSizes[i]; // S3LateHeapTable[i].BufferLength; - HeapParams.BufferHandle = S3LateHeapTable[i]; - HeapParams.Persist = HEAP_S3_RESUME; - if (HeapAllocateBuffer (&HeapParams, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) { - LibAmdMemCopy ((VOID *) HeapParams.BufferPtr, HeapPtrs[i], HeapSizes[i], &AmdS3SaveParams->StdHeader); - } - } - } - - AmdS3SaveParams->StdHeader.HeapStatus = HeapStatus; - } - - - if (LateContextSize != 0) { - - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER); - - SaveDeviceListContext (NonMemoryRelatedDeviceList, - &(BufferPointer[EarlyBufferSize + HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER)]), - S3_LATE_RESTORE, - &LateContextSize, - &AmdS3SaveParams->StdHeader); - } - - AmdS3SaveParams->S3DataBlock.VolatileStorageSize = HeapSize + LateContextSize + sizeof (S3_VOLATILE_STORAGE_HEADER); - } - } - } - - ReturnStatus = BldoptFchFunction.InitLate (AmdS3SaveParams); - - IDS_OPTION_HOOK (IDS_AFTER_S3_SAVE, AmdS3SaveParams, &AmdS3SaveParams->StdHeader); - AGESA_TESTPOINT (TpIfAmdS3SaveExit, &AmdS3SaveParams->StdHeader); - return ReturnStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Constructor for the AMD_S3_SAVE function. - * - * This routine is responsible for setting default values for the - * input parameters needed by the AMD_S3_SAVE entry point. - * - * @param[in] StdHeader The standard header. - * @param[in,out] S3SaveParams Required input parameters for the AMD_S3_SAVE - * entry point. - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdS3SaveInitializer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3SAVE_PARAMS *S3SaveParams - ) -{ - ASSERT (StdHeader != NULL); - ASSERT (S3SaveParams != NULL); - - S3SaveParams->StdHeader = *StdHeader; - - AmdS3ParamsInitializer (&S3SaveParams->S3DataBlock); - - AmdS3SavePlatformConfigInit (&S3SaveParams->PlatformConfig, &S3SaveParams->StdHeader); - BldoptFchFunction.InitLateConstructor (S3SaveParams); - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Destructor for the AMD_S3_SAVE function. - * - * This routine is responsible for deallocation of heap space allocated during - * AMD_S3_SAVE entry point. - * - * @param[in] StdHeader The standard header. - * @param[in,out] S3SaveParams Required input parameters for the AMD_INIT_RESUME - * entry point. - * - * @retval AGESA_STATUS - * - */ -AGESA_STATUS -AmdS3SaveDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3SAVE_PARAMS *S3SaveParams - ) -{ - AGESA_STATUS ReturnStatus; - AGESA_STATUS RetVal; - - ASSERT (S3SaveParams != NULL); - - ReturnStatus = AGESA_SUCCESS; - - // Deallocate heap space allocated during memory S3 save - RetVal = MemS3Deallocate (&S3SaveParams->StdHeader); - if (RetVal > ReturnStatus) { - ReturnStatus = RetVal; - } - - RetVal = HeapDeallocateBuffer (AMD_S3_NB_INFO_BUFFER_HANDLE, StdHeader); - if (RetVal > ReturnStatus) { - ReturnStatus = RetVal; - } - - RetVal = HeapDeallocateBuffer (AMD_S3_INFO_BUFFER_HANDLE, StdHeader); - if (RetVal > ReturnStatus) { - ReturnStatus = RetVal; - } - - return ReturnStatus; -} - -/*------------------------------------------------------------------------------------*/ -/** - * Initialize AmdS3Save stage platform profile and user option input. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -AmdS3SavePlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - CommonPlatformConfigInit (PlatformConfig, StdHeader); - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.c deleted file mode 100644 index 5e52f3c121..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.c +++ /dev/null @@ -1,139 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Common initialization routines. - * - * Contains common initialization routines across AGESA entries of phases. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Filecode.h" -#include "heapManager.h" -#include "CommonInits.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_COMMON_COMMONINITS_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------------*/ - -/** - * Common routine to initialize PLATFORM_CONFIGURATION. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -CommonPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN i; - - PlatformConfig->PlatformProfile = UserOptions.CfgPerformanceProfile; - PlatformConfig->PlatformDeemphasisList = UserOptions.CfgPlatformDeemphasisList; - PlatformConfig->CoreLevelingMode = (UINT8) UserOptions.CfgCoreLevelingMode; - PlatformConfig->C1eMode = UserOptions.CfgPlatformC1eMode; - PlatformConfig->C1ePlatformData = UserOptions.CfgPlatformC1eOpData; - PlatformConfig->C1ePlatformData1 = UserOptions.CfgPlatformC1eOpData1; - PlatformConfig->C1ePlatformData2 = UserOptions.CfgPlatformC1eOpData2; - PlatformConfig->C1ePlatformData3 = UserOptions.CfgPlatformC1eOpData3; - PlatformConfig->CStateMode = UserOptions.CfgPlatformCStateMode; - PlatformConfig->CStatePlatformData = UserOptions.CfgPlatformCStateOpData; - PlatformConfig->CStateIoBaseAddress = UserOptions.CfgPlatformCStateIoBaseAddress; - PlatformConfig->CpbMode = UserOptions.CfgPlatformCpbMode; - PlatformConfig->UserOptionDmi = UserOptions.OptionDmi; - PlatformConfig->UserOptionPState = UserOptions.OptionAcpiPstates; - PlatformConfig->UserOptionSrat = UserOptions.OptionSrat; - PlatformConfig->UserOptionSlit = UserOptions.OptionSlit; - PlatformConfig->UserOptionWhea = UserOptions.OptionWhea; - PlatformConfig->LowPowerPstateForProcHot = UserOptions.CfgLowPowerPstateForProcHot; - PlatformConfig->PowerCeiling = UserOptions.CfgAmdPstateCapValue; - PlatformConfig->ForcePstateIndependent = UserOptions.CfgAcpiPstateIndependent; - PlatformConfig->PStatesInHpcMode = UserOptions.OptionPStatesInHpcMode; - PlatformConfig->NumberOfIoApics = UserOptions.CfgPlatNumIoApics; - for (i = 0; i < MaxVrmType; i++) { - PlatformConfig->VrmProperties[i] = UserOptions.CfgPlatVrmCfg[i]; - } - PlatformConfig->ProcessorScopeInSb = UserOptions.CfgProcessorScopeInSb; - PlatformConfig->ProcessorScopeName0 = UserOptions.CfgProcessorScopeName0; - PlatformConfig->ProcessorScopeName1 = UserOptions.CfgProcessorScopeName1; - PlatformConfig->GnbHdAudio = UserOptions.CfgGnbHdAudio; - PlatformConfig->AbmSupport = UserOptions.CfgAbmSupport; - PlatformConfig->DynamicRefreshRate = UserOptions.CfgDynamicRefreshRate; - PlatformConfig->LcdBackLightControl = UserOptions.CfgLcdBackLightControl; - if ((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) || - (StdHeader->HeapStatus == HEAP_TEMP_MEM) || - (StdHeader->HeapStatus == HEAP_SYSTEM_MEM)) { - IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, PlatformConfig, StdHeader); - } - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.h deleted file mode 100644 index 00ecd86b51..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonInits.h +++ /dev/null @@ -1,64 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Common initialization routines. - * - * Contains common initialization routines across AGESA entries of phases. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _COMMON_INITS_H_ -#define _COMMON_INITS_H_ - -/** - * Common routine to initialize PLATFORM_CONFIGURATION. - * - * @param[in,out] PlatformConfig Platform profile/build option config structure - * @param[in,out] StdHeader AMD standard header config param - * - * @retval AGESA_SUCCESS Always Succeeds. - * - */ -AGESA_STATUS -CommonPlatformConfigInit ( - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _COMMON_INITS_H_ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonPage.h b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonPage.h deleted file mode 100644 index 0db57a79d5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonPage.h +++ /dev/null @@ -1,115 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for Processor Common Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page commonmain Processor Common Component Documentation - * - * Additional documentation for the Common component consists of - * - * - Maintenance Guides: - * - @subpage amdconfigparamname "Naming Guidelines for type AMD_CONFIG_PARAMS" - * - Design Guides: - * - add here >>> - * - */ - -/** - * @page amdconfigparamname Naming Guidelines for type AMD_CONFIG_PARAMS - * @par - * These are the guidelines for naming objects of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * in AGESA code. - *
    - * - *
  • - * Formal parameter names of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * will always be named - * StdHeader. This covers all function prototypes, function definitions, and method typedefs (a - * typedef of a function prototype) in AGESA code. Examples: - * @n @code - * VOID - * LibAmdPciFindNextCap ( - * IN OUT PCI_ADDR *Address, - * IN AMD_CONFIG_PARAMS *StdHeader - * ) - * - * typedef VOID F_DO_TABLE_ENTRY ( - * IN TABLE_ENTRY_DATA *CurrentEntry, - * IN PLATFORM_CONFIGURATION *PlatformConfig, - * IN AMD_CONFIG_PARAMS *StdHeader - * ); - * - * @endcode - * - *
  • - * Structure members of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * will always be named StdHeader. Examples: - * @n @code - /// Example of struct member naming. - * typedef struct { - * IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard Header - * IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. - * } AMD_CPU_RECOVERY_PARAMS; - * - * @endcode - * - *
  • - * Routines which define local variables of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * should - * name the local variable as closely as practical to StdHeader, but otherwise freedom is allowed. Example: - * @n @code - * AMD_CONFIG_PARAMS *NewStdHeader; - * [...] - * NewStdHeader = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr; - * @endcode - * - *
  • - * Arguments to routines with AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * formal parameters are not - * checked. Freedom is allowed in order to conform to these guidelines in a practical, readable - * way. This includes typecast arguments. Examples: - * @n @code - * Status = GetEventLog (&LogEvent, (AMD_CONFIG_PARAMS *)Event); - * - * MemS3ExitSelfRefRegDA (NBPtr, &MemPtr->StdHeader); - * @endcode - * - *
- * - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f15/Proc/Common/CommonReturns.c deleted file mode 100644 index 8c79f9e2b4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/CommonReturns.c +++ /dev/null @@ -1,213 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Common Return routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "Filecode.h" -#include "CommonReturns.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_COMMON_COMMONRETURNS_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -CommonFchInitStub ( - IN VOID *DataPtr - ); - -VOID -FchTaskDummy ( - IN VOID *DataPtr - ); - -/*----------------------------------------------------------------------------------------*/ -/** -* Return TRUE. -* -* @retval TRUE Default case, no special action -*/ -BOOLEAN -CommonReturnTrue ( VOID ) -{ - return TRUE; -} - - -/*----------------------------------------------------------------------------------------*/ -/** -* Return False. -* -* @retval FALSE Default case, no special action -*/ -BOOLEAN -CommonReturnFalse ( VOID ) -{ - return FALSE; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Return (UINT8)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT8 -CommonReturnZero8 ( VOID ) -{ - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Return (UINT32)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT32 -CommonReturnZero32 ( VOID ) -{ - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Return (UINT64)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT64 -CommonReturnZero64 ( VOID ) -{ - return 0; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Return NULL - * - * @retval NULL pointer to nothing - */ -VOID * -CommonReturnNULL ( VOID ) -{ - return NULL; -} - -/*----------------------------------------------------------------------------------------*/ -/** -* Return AGESA_SUCCESS. -* -* @retval AGESA_SUCCESS Success. -*/ -AGESA_STATUS -CommonReturnAgesaSuccess ( VOID ) -{ - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Do Nothing. - * - */ -VOID -CommonVoid ( VOID ) -{ -} - -/*----------------------------------------------------------------------------------------*/ -/** - * ASSERT if this routine is called. - * - */ -VOID -CommonAssert ( VOID ) -{ - ASSERT (FALSE); -} - - -/*----------------------------------------------------------------------------------------*/ -/** -* Return AGESA_SUCCESS. -* -* @retval AGESA_SUCCESS Success. -*/ -AGESA_STATUS -CommonFchInitStub ( - IN VOID *DataPtr - ) -{ - return AGESA_SUCCESS; -} - - -VOID -FchTaskDummy ( - IN VOID *DataPtr - ) -{ -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.c deleted file mode 100644 index ad007e4386..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.c +++ /dev/null @@ -1,314 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Input Structure Creation - * - * Contains AGESA input structure creation support. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_COMMON_CREATESTRUCT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CONST FUNCTION_PARAMS_INFO FuncParamsInfo[]; -extern CONST UINTN InitializerCount; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------*/ -/** - * Allocate and initialize Config headers and Service Interface structures. - * - * This function will be called for each AGESA public APIs. - * This function will do the following: - * -# Locate the AGESA API structure parameters initializer function information. - * -# Find the size of the structure that gets passed to each public APIs as - * the entry parameter. Allocate heap space using the size for PreMemHeap, callout for - * memory allocation for PostMemDram, and just set the config and service interface - * pointers for ByHost. - * -# If the allocation is not ByHost, copy the AmdConfigParams into the newly created AmdConfigParams. - * For ByHost, we're using the caller's existing config params. - * -# Call the initializer function, and pass a reference to the Config params and to - * the Service Interface struct. On return the constructor will have filled the - * remaining structure with default values. - * -# Fill the remaining info in the newly created structure on heap in AMD_CONFIG_PARAMS - * area (i.e. Fill *newStructPtr with the pointer to the newly created structure) - * -# Set the appropriate AGESA function number in the StdHeader member of the input - * parameter structure. - * - * @param[in,out] InterfaceParams Pointer to structure containing the function call - * whose parameter structure is to be created, the - * allocation method, and a pointer to the newly - * created structure. - * - * @retval AGESA_SUCCESS The interface struct is allocated and initialized. - * @retval AGESA_UNSUPPORTED The Service is not supported. - * - */ -AGESA_STATUS -AmdCreateStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - UINTN ServiceIndex; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - AMD_CONFIG_PARAMS *NewlyCreatedConfig; - VOID *NewlyCreatedServiceInterface; - AGESA_STATUS AgesaStatus; - AGESA_STATUS TempStatus; - AGESA_STATUS IgnoredSts; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - AgesaStatus = AGESA_SUCCESS; - - ASSERT (InterfaceParams != NULL); - - switch (InterfaceParams->AgesaFunctionName) { - case AMD_INIT_RESET: - if (!IsBsp (&InterfaceParams->StdHeader, &IgnoredSts)) { - // APs must transfer their system core number from the mailbox to - // a local register while it is still valid. - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &InterfaceParams->StdHeader); - FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, &InterfaceParams->StdHeader); - } - InterfaceParams->StdHeader.HeapStatus = HEAP_DO_NOT_EXIST_YET; - break; - case AMD_INIT_EARLY: - case AMD_INIT_RECOVERY: - case AMD_INIT_RESUME: - case AMD_INIT_POST: - InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; - break; - case AMD_INIT_ENV: - InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM; - break; - case AMD_INIT_LATE: - case AMD_INIT_MID: - case AMD_S3_SAVE: - case AMD_LATE_RUN_AP_TASK: - InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - break; - case AMD_S3LATE_RESTORE: - InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME; - break; - default: - ASSERT (FALSE); - InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; - break; - } - - InterfaceParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&InterfaceParams->StdHeader); - - if (InterfaceParams->AgesaFunctionName == AMD_INIT_RESET) { - AgesaStatus = HeapManagerInit (&InterfaceParams->StdHeader); - } - - // Step 1 - for (ServiceIndex = 0; ServiceIndex < InitializerCount; ServiceIndex++) { - if (FuncParamsInfo[ServiceIndex].AgesaFunctionName == InterfaceParams->AgesaFunctionName) { - break; - } - } - if (ServiceIndex >= InitializerCount) { - // A call was made to AGESA with an invalid function number. This wrapper error may be due to the build target - // not containing the desired entry point. - return AGESA_UNSUPPORTED; - } - - // Step 2 - LibAmdMemFill (&AllocHeapParams, 0, (UINTN) (sizeof (ALLOCATE_HEAP_PARAMS)), &InterfaceParams->StdHeader); - - if (InterfaceParams->AllocationMethod < ByHost) { - // Allocate one buffer to contain the config params and the service struct. - // The service struct begins immediately after the config params. - AllocHeapParams.RequestedBufferSize = FuncParamsInfo[ServiceIndex].CreateStructSize + sizeof (AMD_CONFIG_PARAMS); - AllocHeapParams.BufferHandle = FuncParamsInfo[ServiceIndex].BufferHandle; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - TempStatus = HeapAllocateBuffer (&AllocHeapParams, &(InterfaceParams->StdHeader)); - AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); - NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr; - NewlyCreatedConfig++; - NewlyCreatedServiceInterface = NewlyCreatedConfig; - NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr; - } else { - // The caller (example, agesa basic interface implementation) already has a buffer to use. - NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)InterfaceParams; - NewlyCreatedServiceInterface = InterfaceParams->NewStructPtr; - ASSERT (InterfaceParams->NewStructSize >= FuncParamsInfo[ServiceIndex].CreateStructSize); - } - ASSERT (NewlyCreatedConfig != NULL); - ASSERT (NewlyCreatedServiceInterface != NULL); - - // Step 3 - if (InterfaceParams->AllocationMethod != ByHost) { - *NewlyCreatedConfig = InterfaceParams->StdHeader; - } - - // Step 4 - TempStatus = FuncParamsInfo[ServiceIndex].AgesaFunction (NewlyCreatedConfig, NewlyCreatedServiceInterface); - AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); - - // Step 5 - if (InterfaceParams->AllocationMethod != ByHost) { - InterfaceParams->NewStructPtr = (VOID *) NewlyCreatedServiceInterface; - InterfaceParams->NewStructSize = FuncParamsInfo[ServiceIndex].CreateStructSize; - } - - // Step 6 - ((AMD_CONFIG_PARAMS *) InterfaceParams->NewStructPtr)->Func = InterfaceParams->AgesaFunctionName; - return AgesaStatus; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Clears storage space from allocation for a parameter block of an - * AGESA software call entry. - * - * @param[in,out] InterfaceParams Pointer to structure containing the function call - * whose parameter structure is to be deallocated. - * - * @retval AGESA_STATUS - * - *--------------------------------------------------------------------------------------- - **/ -AGESA_STATUS -AmdReleaseStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - UINT8 i; - UINT8 *BufferPtr; - VOID *ServicePtr; - AGESA_STATUS AgesaStatus; - AGESA_STATUS TempStatus; - LOCATE_HEAP_PTR LocHeap; - - AgesaStatus = AGESA_SUCCESS; - - switch (InterfaceParams->AgesaFunctionName) { - case AMD_INIT_RESET: - case AMD_INIT_EARLY: - case AMD_INIT_RECOVERY: - case AMD_INIT_RESUME: - InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; - break; - case AMD_INIT_POST: - InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM; - break; - case AMD_INIT_ENV: - case AMD_INIT_LATE: - case AMD_INIT_MID: - case AMD_S3_SAVE: - case AMD_LATE_RUN_AP_TASK: - InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - break; - case AMD_S3LATE_RESTORE: - InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME; - break; - default: - ASSERT (FALSE); - InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; - break; - } - - InterfaceParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&InterfaceParams->StdHeader); - -// Step 1 - for (i = 0; i < InitializerCount; i++) { - if (FuncParamsInfo[i].AgesaFunctionName == InterfaceParams->AgesaFunctionName) { - break; - } - } - if (i >= InitializerCount) { - return AGESA_BOUNDS_CHK; - } - - // Step 2 - if (InterfaceParams->AllocationMethod < ByHost) { - LocHeap.BufferHandle = FuncParamsInfo[i].BufferHandle; - if (HeapLocateBuffer (&LocHeap, &(InterfaceParams->StdHeader)) == AGESA_SUCCESS) { - BufferPtr = (UINT8 *) LocHeap.BufferPtr; - ServicePtr = &BufferPtr[sizeof (AMD_CONFIG_PARAMS)]; - TempStatus = FuncParamsInfo[i].AgesaDestructor (&(InterfaceParams->StdHeader), ServicePtr); - AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); - } - } - - // Step 3 - if (InterfaceParams->AllocationMethod < ByHost) { - TempStatus = HeapDeallocateBuffer (FuncParamsInfo[i].BufferHandle, &(InterfaceParams->StdHeader)); - AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); - } else { - // Unless we define service specific destructors, nothing to do for ByHost. - return AGESA_SUCCESS; - } - return AgesaStatus; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.h deleted file mode 100644 index eee396de42..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/CreateStruct.h +++ /dev/null @@ -1,194 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD AGESA Input Structure Creation - * - * Contains AGESA input creation structures. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -#ifndef _CREATE_STRUCT_H_ -#define _CREATE_STRUCT_H_ - -/** - * A constructor method. - * - * Sets inputs to valid, basic level, defaults for the specific service instance. - * Constructors should avoid using the header, since these routines should not - * do operations which may fail or require status back to the user. The constructor - * should always SUCCEED. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] ServiceInterface Service Interface structure to initialize. - * - * @retval AGESA_SUCCESS Constructors are not allowed to fail -*/ -typedef AGESA_STATUS -F_AGESA_FUNCTION ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ServiceInterface - ); - -/// Reference to a Method. -typedef F_AGESA_FUNCTION *PF_AGESA_FUNCTION; - -/** - * A Destructor method. - * - * Sets inputs to valid, basic level, defaults for the specific service instance. - * The constructor should always SUCCEED. - * - * @param[in] StdHeader Opaque handle to standard config header. - * @param[in] ServiceInterface Service Interface structure to initialize. - * - * @retval AGESA_SUCCESS Constructors are not allowed to fail -*/ -typedef AGESA_STATUS -F_AGESA_DESTRUCTOR ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ServiceInterface - ); - -/// Reference to a Method. -typedef F_AGESA_DESTRUCTOR *PF_AGESA_DESTRUCTOR; - -/** - * Provide the information needed to invoke each service constructor. - */ -typedef struct { - IN AGESA_STRUCT_NAME AgesaFunctionName; ///< Identifies the service - IN UINT16 CreateStructSize; ///< The service's input struct size. - /// Do NOT include a config params header! - OUT PF_AGESA_FUNCTION AgesaFunction; ///< The constructor function - OUT PF_AGESA_DESTRUCTOR AgesaDestructor; ///< The destructor function. - IN AGESA_BUFFER_HANDLE BufferHandle; ///< The buffer handle id for the service. -} FUNCTION_PARAMS_INFO; - -/** - * All available services have their constructor info here. - */ -AGESA_STATUS -AmdInitResetConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_RESET_PARAMS *AmdResetParams - ); - -AGESA_STATUS -AmdInitRecoveryInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr - ); - -AGESA_STATUS -AmdInitEarlyInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_EARLY_PARAMS *EarlyParams - ); - -AGESA_STATUS -AmdInitPostInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -AGESA_STATUS -AmdInitPostDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_POST_PARAMS *PostParamsPtr - ); - -AGESA_STATUS -AmdInitEnvInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -AmdInitMidInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_MID_PARAMS *MidParamsPtr - ); - -AGESA_STATUS -AmdInitLateInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ); - -AGESA_STATUS -AmdInitLateDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_LATE_PARAMS *LateParamsPtr - ); - -AGESA_STATUS -AmdInitResumeInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_RESUME_PARAMS *ResumeParams - ); - -AGESA_STATUS -AmdInitResumeDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_RESUME_PARAMS *ResumeParams - ); - -AGESA_STATUS -AmdS3SaveInitializer ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3SAVE_PARAMS *S3SaveParams - ); - -AGESA_STATUS -AmdS3SaveDestructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3SAVE_PARAMS *S3SaveParams - ); - -AGESA_STATUS -AmdS3LateRestoreInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ); - -AGESA_STATUS -AmdLateRunApTaskInitializer ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT AP_EXE_PARAMS *AmdApExeParams - ); -#endif // _CREATE_STRUCT_H_ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Common/Makefile.inc deleted file mode 100644 index 957c98f639..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/Makefile.inc +++ /dev/null @@ -1,15 +0,0 @@ -libagesa-y += AmdInitEarly.c -libagesa-y += AmdInitEnv.c -libagesa-y += AmdInitLate.c -libagesa-y += AmdInitMid.c -libagesa-y += AmdInitPost.c -libagesa-y += AmdInitReset.c -libagesa-y += AmdInitResume.c -libagesa-y += AmdLateRunApTask.c -libagesa-y += AmdS3LateRestore.c -libagesa-y += AmdS3Save.c -libagesa-y += CommonInits.c -libagesa-y += CommonReturns.c -libagesa-y += CreateStruct.c -libagesa-y += S3RestoreState.c -libagesa-y += S3SaveState.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c deleted file mode 100644 index 5f00ec5986..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3RestoreState.c +++ /dev/null @@ -1,442 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * S3 save/restore script - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "S3SaveState.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_COMMON_S3RESTORESTATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration; -extern S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable[]; -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -AGESA_STATUS -STATIC -S3RestoreStateFromTable ( - IN S3_SAVE_TABLE_HEADER *S3SaveTablePtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptRestore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return OptionS3ScriptConfiguration.Restore (StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptRestoreStateStub ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptRestoreState ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - S3SaveTablePtr->Locked = TRUE; - Status = S3RestoreStateFromTable (S3SaveTablePtr, StdHeader); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] S3SaveTablePtr Pointer to S3 Save Table - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -STATIC -S3RestoreStateFromTable ( - IN S3_SAVE_TABLE_HEADER *S3SaveTablePtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - VOID *S3SaveTableRecordPtr; - PCI_ADDR PciAddress; - UINTN Index; - S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER); - IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore: Address: 0x%08x\n", (intptr_t)((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); - while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) { - switch (*(UINT16 *) S3SaveTableRecordPtr) { - case SAVE_STATE_IO_WRITE_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdIoWrite ( - ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_WRITE_OP_HEADER) + - LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_IO_READ_WRITE_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdIoRMW ( - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_READ_WRITE_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_MEM_WRITE_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdMemWrite ( - ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_WRITE_OP_HEADER) + - LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_MEM_READ_WRITE_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdMemRMW ( - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Width), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_READ_WRITE_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE: - PciAddress.AddressValue = (UINT32) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address; - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdPciWrite ( - ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - PciAddress, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_WRITE_OP_HEADER) + - LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE: - PciAddress.AddressValue = (UINT32) ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address; - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - LibAmdPciRMW ( - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, - PciAddress, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_READ_WRITE_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_STALL_OPCODE: - break; - case SAVE_STATE_INFORMATION_OPCODE: - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: Info: [%s]\n", (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_INFO_OP_HEADER)); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_INFO_OP_HEADER) + - ((S3_INFO_OP_HEADER*) S3SaveTableRecordPtr)->Length; - break; - case SAVE_STATE_DISPATCH_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Function Id: 0x%02x, Context: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->FunctionId); - S3SaveDebugPrintHexArray ( - StdHeader, - (VOID*)((UINT8*) S3SaveTableRecordPtr + sizeof (S3_DISPATCH_OP_HEADER)), - ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length, - AccessWidth8); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - Index = 0; - while (S3DispatchFunctionTable[Index].FunctionId != 0) { - if (S3DispatchFunctionTable[Index].FunctionId == ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->FunctionId) { - (S3DispatchFunctionTable[Index].Function) ( - StdHeader, - ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length, - (VOID*)((UINT8*) S3SaveTableRecordPtr + sizeof (S3_DISPATCH_OP_HEADER)) - ); - break; - } - Index++; - } - ASSERT (S3DispatchFunctionTable[Index].FunctionId != 0); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_DISPATCH_OP_HEADER) + - ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length; - break; - - case SAVE_STATE_IO_POLL_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%04x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - 1, - ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - ) - LibAmdIoPoll ( - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width, - (UINT16) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Width), - ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Delay, - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_POLL_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_MEM_POLL_OPCODE: - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT32) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - 1, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - ) - LibAmdMemPoll ( - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay, - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_POLL_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - case SAVE_STATE_PCI_CONFIG_POLL_OPCODE: - PciAddress.AddressValue = (UINT32) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address; - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT32) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - 1, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray ( - StdHeader, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), - 1, - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width - ); - ) - LibAmdPciPoll ( - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width, - PciAddress, - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), - (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), - ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay, - StdHeader - ); - S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + - sizeof (S3_POLL_OP_HEADER) + - 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width); - break; - default: - IDS_HDT_CONSOLE (S3_TRACE, " ERROR!!! Invalid S3 restore opcode\n"); - ASSERT (FALSE); - return AGESA_ERROR; - } - } - IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n"); - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c deleted file mode 100644 index dacef8699a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c +++ /dev/null @@ -1,652 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * S3 save/restore script - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "Porting.h" -#include "AMD.h" -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "S3SaveState.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_COMMON_S3SAVESTATE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -S3SaveStateExtendTableLenth ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return OptionS3ScriptConfiguration.Init (StdHeader); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptInitStateStub ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - */ -AGESA_STATUS -S3ScriptInitState ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS Status; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - AllocHeapParams.RequestedBufferSize = S3_TABLE_LENGTH; - AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); - if (Status == AGESA_SUCCESS) { - ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->TableLength = S3_TABLE_LENGTH; - ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->SaveOffset = sizeof (S3_SAVE_TABLE_HEADER); - ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->Locked = FALSE; - } - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in,out] S3SaveTable S3 save table header - */ -AGESA_STATUS -S3SaveStateExtendTableLenth ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable - ) -{ - AGESA_STATUS Status; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - VOID *TempBuffer; - UINT16 NewTableLength; - UINT16 CurrentTableLength; - //Allocate temporary buffer - NewTableLength = (*S3SaveTable)->TableLength + S3_TABLE_LENGTH_INCREMENT; - AllocHeapParams.RequestedBufferSize = NewTableLength; - AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE; - AllocHeapParams.Persist = StdHeader->HeapStatus; - Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); - if (Status != AGESA_SUCCESS) { - return Status; - } - //Save current table length - CurrentTableLength = (*S3SaveTable)->TableLength; - //Update table length - (*S3SaveTable)->TableLength = NewTableLength; - //Copy S3 save toable to temporary location - LibAmdMemCopy (AllocHeapParams.BufferPtr, *S3SaveTable, CurrentTableLength, StdHeader); - //Save pointer to temp buffer - TempBuffer = AllocHeapParams.BufferPtr; - // Free original S3 save buffer - HeapDeallocateBuffer (AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, StdHeader); - - AllocHeapParams.RequestedBufferSize = NewTableLength; - AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE; - AllocHeapParams.Persist = StdHeader->HeapStatus; - Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); - if (Status != AGESA_SUCCESS) { - return Status; - } - LibAmdMemCopy (AllocHeapParams.BufferPtr, TempBuffer, AllocHeapParams.RequestedBufferSize, StdHeader); - *S3SaveTable = (S3_SAVE_TABLE_HEADER*) AllocHeapParams.BufferPtr; - HeapDeallocateBuffer (AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, StdHeader); - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize S3 Script framework - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[out] S3SaveTable S3 save table header - */ -AGESA_STATUS -S3ScriptGetS3SaveTable ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT S3_SAVE_TABLE_HEADER **S3SaveTable - ) -{ - AGESA_STATUS Status; - LOCATE_HEAP_PTR LocHeapParams; - LocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE; - Status = HeapLocateBuffer (&LocHeapParams, StdHeader); - if (Status != AGESA_SUCCESS) { - *S3SaveTable = NULL; - return Status; - } - *S3SaveTable = (S3_SAVE_TABLE_HEADER *) LocHeapParams.BufferPtr; - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 write opcode - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] OpCode Operation opcode - * @param[in] Width Width - * @param[in] Address Register address - * @param[in] Count Number of register writes - * @param[in] Buffer Pointer to write buffer - */ -AGESA_STATUS -S3SaveStateSaveWriteOp ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 OpCode, - IN ACCESS_WIDTH Width, - IN UINT64 Address, - IN UINT32 Count, - IN VOID *Buffer - ) -{ - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - S3_WRITE_OP_HEADER *SaveOffsetPtr; - UINT32 OpCodeLength; - UINT32 WidthLength; - AGESA_STATUS Status; - - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - if (S3SaveTablePtr->Locked) { - return AGESA_UNSUPPORTED; - } - WidthLength = LibAmdAccessWidth (Width); - OpCodeLength = sizeof (S3_WRITE_OP_HEADER) + WidthLength * Count; - if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { - Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - } - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); - S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - SaveOffsetPtr = (S3_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); - SaveOffsetPtr->OpCode = OpCode; - SaveOffsetPtr->Width = Width; - SaveOffsetPtr->Count = Count; - SaveOffsetPtr->Address = Address; - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_WRITE_OP_HEADER), - Buffer, - WidthLength * Count, - StdHeader - ); - S3SaveTablePtr->SaveOffset += OpCodeLength; - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 write opcode - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] OpCode Operation opcode - * @param[in] Width Width - * @param[in] Address Register address - * @param[in] Data Pointer to data - * @param[in] DataMask Pointer data mask - */ -AGESA_STATUS -S3SaveStateSaveReadWriteOp ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 OpCode, - IN ACCESS_WIDTH Width, - IN UINT64 Address, - IN VOID *Data, - IN VOID *DataMask - ) -{ - - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - S3_READ_WRITE_OP_HEADER *SaveOffsetPtr; - UINT32 OpCodeLength; - UINT32 WidthLength; - AGESA_STATUS Status; - - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - if (S3SaveTablePtr->Locked) { - return AGESA_UNSUPPORTED; - } - WidthLength = LibAmdAccessWidth (Width); - OpCodeLength = sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength * 2; - if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { - Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - } - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); - S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - SaveOffsetPtr = (S3_READ_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); - SaveOffsetPtr->OpCode = OpCode; - SaveOffsetPtr->Width = Width; - SaveOffsetPtr->Address = Address; - - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER), - Data, - WidthLength, - StdHeader - ); - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength, - DataMask, - WidthLength, - StdHeader - ); - S3SaveTablePtr->SaveOffset += OpCodeLength; - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 poll opcode - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] OpCode Operation opcode - * @param[in] Width Width - * @param[in] Address Register address - * @param[in] Data Pointer to data - * @param[in] DataMask Pointer data mask - * @param[in] Delay Time delay for poll - */ -AGESA_STATUS -S3SaveStateSavePollOp ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 OpCode, - IN ACCESS_WIDTH Width, - IN UINT64 Address, - IN VOID *Data, - IN VOID *DataMask, - IN UINT64 Delay - ) -{ - - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - S3_POLL_OP_HEADER *SaveOffsetPtr; - UINT32 OpCodeLength; - UINT32 WidthLength; - AGESA_STATUS Status; - - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - if (S3SaveTablePtr->Locked) { - return AGESA_UNSUPPORTED; - } - WidthLength = LibAmdAccessWidth (Width); - OpCodeLength = sizeof (S3_POLL_OP_HEADER) + WidthLength * 2; - if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { - Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - } - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); - S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); - IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); - S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - SaveOffsetPtr = (S3_POLL_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); - SaveOffsetPtr->OpCode = OpCode; - SaveOffsetPtr->Width = Width; - SaveOffsetPtr->Delay = Delay; - SaveOffsetPtr->Address = Address; - - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER), - Data, - WidthLength, - StdHeader - ); - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER) + WidthLength, - DataMask, - WidthLength, - StdHeader - ); - S3SaveTablePtr->SaveOffset += OpCodeLength; - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 info opcode - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] OpCode Operation opcode - * @param[in] InformationLength Info length - * @param[in] Information Pointer to information - */ -AGESA_STATUS -S3SaveStateSaveInfoOp ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 OpCode, - IN UINT32 InformationLength, - IN VOID *Information - ) -{ - - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - S3_INFO_OP_HEADER *SaveOffsetPtr; - UINT32 OpCodeLength; - - AGESA_STATUS Status; - - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - if (S3SaveTablePtr->Locked) { - return AGESA_UNSUPPORTED; - } - OpCodeLength = sizeof (S3_INFO_OP_HEADER) + InformationLength; - if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { - Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - } - SaveOffsetPtr = (S3_INFO_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); - SaveOffsetPtr->OpCode = OpCode; - SaveOffsetPtr->Length = InformationLength; - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information); - ); - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER), - Information, - InformationLength, - StdHeader - ); - S3SaveTablePtr->SaveOffset += OpCodeLength; - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 dispatch opcode - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] OpCode Operation opcode - * @param[in] FunctionId Function ID - * @param[in] ContextLength Context length - * @param[in] Context Pointer to Context - */ -AGESA_STATUS -S3SaveStateSaveDispatchOp ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 OpCode, - IN UINT16 FunctionId, - IN UINT16 ContextLength, - IN VOID *Context - ) -{ - - S3_SAVE_TABLE_HEADER *S3SaveTablePtr; - S3_DISPATCH_OP_HEADER *SaveOffsetPtr; - UINT32 OpCodeLength; - AGESA_STATUS Status; - - Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - if (S3SaveTablePtr->Locked) { - return AGESA_UNSUPPORTED; - } - OpCodeLength = sizeof (S3_DISPATCH_OP_HEADER) + ContextLength; - if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { - Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); - if (Status != AGESA_SUCCESS) { - return Status; - } - } - S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Function Id: 0x%02x, Context: ", S3SaveDebugOpcodeString (StdHeader, OpCode), FunctionId); - S3SaveDebugPrintHexArray (StdHeader, Context, ContextLength, AccessWidth8); - IDS_HDT_CONSOLE (S3_TRACE, "\n"); - ); - SaveOffsetPtr = (S3_DISPATCH_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); - SaveOffsetPtr->OpCode = OpCode; - SaveOffsetPtr->Length = ContextLength; - SaveOffsetPtr->FunctionId = FunctionId; - LibAmdMemCopy ( - (UINT8 *) SaveOffsetPtr + sizeof (S3_DISPATCH_OP_HEADER), - Context, - ContextLength, - StdHeader - ); - - S3SaveTablePtr->SaveOffset += OpCodeLength; - return AGESA_SUCCESS; -} - - - - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 debug support - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] Op Opcode - */ -CHAR8* -S3SaveDebugOpcodeString ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 Op - ) -{ - switch (Op) { - case SAVE_STATE_IO_WRITE_OPCODE: - return (CHAR8 *)"IO WR"; - case SAVE_STATE_IO_READ_WRITE_OPCODE: - return (CHAR8 *)"IO RD/WR"; - case SAVE_STATE_IO_POLL_OPCODE: - return (CHAR8 *)"IO POLL"; - case SAVE_STATE_MEM_WRITE_OPCODE: - return (CHAR8 *)"MEM WR"; - case SAVE_STATE_MEM_READ_WRITE_OPCODE: - return (CHAR8 *)"MEM RD/WR"; - case SAVE_STATE_MEM_POLL_OPCODE: - return (CHAR8 *)"MEM POLL"; - case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE: - return (CHAR8 *)"PCI WR"; - case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE: - return (CHAR8 *)"PCI RD/WR"; - case SAVE_STATE_PCI_CONFIG_POLL_OPCODE: - return (CHAR8 *)"PCI POLL"; - case SAVE_STATE_STALL_OPCODE: - return (CHAR8 *)"STALL"; - case SAVE_STATE_DISPATCH_OPCODE: - return (CHAR8 *)"DISPATCH"; - default: - IDS_ERROR_TRAP; - } - return (CHAR8 *)"!!! Unrecognize opcode !!!"; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Save S3 debug support - * - * - * - * @param[in] StdHeader Pointer to standard header - * @param[in] Array Array - * @param[in] Count Count of element in array - * @param[in] Width Array Element width - */ -VOID -S3SaveDebugPrintHexArray ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *Array, - IN UINT32 Count, - IN ACCESS_WIDTH Width - ) -{ - UINTN Index; - - for (Index = 0; Index < Count; Index++) { - switch (Width) { - case AccessWidth8: - case AccessS3SaveWidth8: - IDS_HDT_CONSOLE (S3_TRACE, "0x%02x", *((UINT8*)Array + Index)); - break; - case AccessWidth16: - case AccessS3SaveWidth16: - IDS_HDT_CONSOLE (S3_TRACE, "0x%04x", *((UINT16*)Array + Index)); - break; - case AccessWidth32: - case AccessS3SaveWidth32: - IDS_HDT_CONSOLE (S3_TRACE, "0x%08x", *((UINT32*)Array + Index)); - break; - case AccessWidth64: - case AccessS3SaveWidth64: - IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index)[1], ((UINT32*) ((UINT64*)Array + Index))[0])); - break; - default: - IDS_ERROR_TRAP; - break; - } - if (Index < (Count - 1)) { - IDS_HDT_CONSOLE (S3_TRACE, ", "); - } - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.h b/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.h deleted file mode 100644 index ecfa6af28e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.h +++ /dev/null @@ -1,361 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various PCI service routines. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 51711 $ @e \$Date: 2011-04-27 00:23:04 -0600 (Wed, 27 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _S3SAVESTATE_H_ -#define _S3SAVESTATE_H_ - -#pragma pack (push, 1) - -#ifndef S3_SCRIPT_DEBUG_CODE - #define S3_SCRIPT_DEBUG_CODE(Code) Code -#endif - -/// Dispatch function ID repository -typedef enum { - NbSmuIndirectWriteS3Script_ID = 1, ///< GNB SMU service request function ID. - NbSmuServiceRequestS3Script_ID, ///< GNB PCIe late restore function ID. - PcieLateRestoreS3Script_ID, ///< GNB SMU indirect write. - GnbSmuServiceRequestV4S3Script_ID, ///< SMU service request - GnbLibStallS3Script_ID, ///< Stall request - PcieLateRestoreTNS3Script_ID, ///< GNB PCIe late restore TN - PcieLateRestoreKMS3Script_ID, ///< GNB PCIe late restore KM -} S3_DISPATCH_FUNCTION_ID; - -#define SAVE_STATE_IO_WRITE_OPCODE 0x00 -#define SAVE_STATE_IO_READ_WRITE_OPCODE 0x01 -#define SAVE_STATE_MEM_WRITE_OPCODE 0x02 -#define SAVE_STATE_MEM_READ_WRITE_OPCODE 0x03 -#define SAVE_STATE_PCI_CONFIG_WRITE_OPCODE 0x04 -#define SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE 0x05 -#define SAVE_STATE_STALL_OPCODE 0x07 -#define SAVE_STATE_INFORMATION_OPCODE 0x0A -#define SAVE_STATE_IO_POLL_OPCODE 0x0D -#define SAVE_STATE_MEM_POLL_OPCODE 0x0E -#define SAVE_STATE_PCI_CONFIG_POLL_OPCODE 0x0F -#define SAVE_STATE_DISPATCH_OPCODE 0x20 -#define SAVE_STATE_BREAKPOINT_OPCODE 0x21 - - -#define S3_TABLE_LENGTH 8 * 1024 -#define S3_TABLE_LENGTH_INCREMENT 1 * 1024 - -/// S3 Save Table -typedef struct { - UINT16 TableLength; ///< Table Length - UINT32 SaveOffset; ///< Save Location - BOOLEAN Locked; ///< Locked -} S3_SAVE_TABLE_HEADER; - -/// S3 write operation header -typedef struct { - UINT16 OpCode; ///< Opcode - ACCESS_WIDTH Width; ///< Data width (byte, word, dword) - UINT64 Address; ///< Register address - UINT32 Count; ///< Write count -} S3_WRITE_OP_HEADER; - -/// S3 Read and Write Operation header -typedef struct { - UINT16 OpCode; ///< Opcode - ACCESS_WIDTH Width; ///< Data width (byte, word, dword) - UINT64 Address; ///< Register Address -} S3_READ_WRITE_OP_HEADER; - -/// S3 Poll operation header -typedef struct { - UINT16 OpCode; ///< Opcode - ACCESS_WIDTH Width; ///< Data width (byte, word, dword) - UINT64 Address; ///< Register address - UINT64 Delay; ///< Time delay -} S3_POLL_OP_HEADER; - -/// Information operation header -typedef struct { - UINT16 OpCode; ///< Opcode - UINT32 Length; ///< Length of info -} S3_INFO_OP_HEADER; - -/// Dispatch operation header -typedef struct { - UINT16 OpCode; ///< Opcode - UINT16 FunctionId; ///< Function ID - UINT16 Length; ///< Length in bytes of the context -} S3_DISPATCH_OP_HEADER; - - -typedef VOID S3_DISPATCH_FUNCTION ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT16 ContextLength, - IN VOID *Context - ); - -/// Dispatch function table entry -typedef struct { - UINT16 FunctionId; ///ConfigHandle); - - if (Temp != 0) { - MaxNodes = (UINT8) (1 << (~Temp & 0x3)); // That is, 1, 2, 4, or 8 - } else { - MaxNodes = 8; - } - if (State->SysMpCap > MaxNodes) { - State->SysMpCap = MaxNodes; - } - // Note since sysMpCap is one based and NodesDiscovered is zero based, equal returns true - // - return ((BOOLEAN) (State->SysMpCap <= State->NodesDiscovered)); -} - -/** - * Stop a link, so that it is isolated from a connected device. - * - * @HtNbMethod{::F_STOP_LINK}. - * - * Use is for fatal incompatible configurations, or for user interface - * request to power off a link (IgnoreLink, SkipRegang). - * Set ConnDly to make the power effective at the warm reset. - * Set XMT and RCV off. - * - * @param[in] Node the node to stop a link on. - * @param[in] Link the link to stop. - * @param[in] State access to special routine for writing link control register - * @param[in] Nb this northbridge. - */ -VOID -Fam10StopLink ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR Reg; - - // Set ConnDly - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_LINK_GLOBAL_EXT_CONTROL_0x16C); - Temp = 1; - LibAmdPciWriteBits (Reg, 8, 8, &Temp, Nb->ConfigHandle); - // Set TransOff and EndOfChain - Reg = Nb->MakeLinkBase (Node, Link, Nb); - Reg.Address.Register += HTHOST_LINK_CONTROL_REG; - Temp = 3; - State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.h deleted file mode 100644 index 4098b226a7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.h +++ /dev/null @@ -1,67 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Coherent Family 10h specific Routines. - * - * Coherent feature Northbridge implementation specific to Family 10h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/** - * Return whether the current configuration exceeds the capability. - * - */ -BOOLEAN -Fam10IsExceededCapable ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); - -/** - * Stop a link, so that it is isolated from a connected device. - */ -VOID -Fam10StopLink ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbFam10.c deleted file mode 100644 index 60949c4224..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbFam10.c +++ /dev/null @@ -1,485 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initializers for Family 10h northbridge support. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionsHt.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "CommonReturns.h" -#include "htNbCoherent.h" -#include "htNbCoherentFam10.h" -#include "htNbNonCoherent.h" -#include "htNbNonCoherentFam10.h" -#include "htNbOptimization.h" -#include "htNbOptimizationFam10.h" -#include "htNbSystemFam10.h" -#include "htNbUtilities.h" -#include "htNbUtilitiesFam10.h" -#include "cpuFamRegisters.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FAM10_HTNBFAM10_FILECODE - -extern OPTION_HT_CONFIGURATION OptionHtConfiguration; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** - ***************************************************************************/ - -/** - * Map Northbridge links to package links for Family 10h, Rev D, multi-module. - * - * Unfortunately, there is no way to do this except to type the BKDG text into this data structure. - * Note that there is one entry per package external sublink and each connected internal link. - */ -CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[] = -{ - {0, 0, 0}, ///< Module zero, link 0: package link 0 - {4, 0, 4}, ///< Module zero, link 4: package link 4 - {0, 1, 1}, ///< Module one, link 0: package link 1 - {4, 1, 5}, ///< Module one, link 4: package link 5 - {3, 0, 2}, ///< Module zero, link 3: package link 2 - {7, 0, 6}, ///< Module zero, link 7: package link 6 - {2, 0, 3}, ///< Module zero, link 2: package link 3 - {1, 1, 7}, ///< Module one, link 1: package link 7 - {1, 0, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link - {5, 0, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link - {6, 0, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link - {2, 1, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link - {6, 1, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link - {5, 1, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link - {HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL}, ///< End -}; - -/** - * A default Ignore Link list for rev D to power off the 3rd internal sublink. - */ -STATIC CONST IGNORE_LINK ROMDATA Fam10RevDIgnoreLinkList[] = { - {HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK_2, POWERED_OFF}, - {HT_LIST_TERMINAL} -}; - -/** - * Initial construction data for Family 10h North Bridge, default, full features. - */ -CONST NORTHBRIDGE ROMDATA HtFam10NbDefault = -{ - 8, - WriteRoutingTable, - WriteNodeID, - ReadDefaultLink, - EnableRoutingTables, - DisableRoutingTables, - VerifyLinkIsCoherent, - ReadToken, - WriteToken, - WriteFullRoutingTable, - IsIllegalTypeMix, - Fam10IsExceededCapable, - Fam10StopLink, - (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, - HandleSpecialNodeCase, - ReadSouthbridgeLink, - VerifyLinkIsNonCoherent, - Fam10SetConfigAddrMap, - Fam10NorthBridgeFreqMask, - GatherLinkFeatures, - SetLinkRegang, - SetLinkFrequency, - SetLinkUnitIdClumping, - Fam10WriteTrafficDistribution, - Fam10WriteLinkPairDistribution, - (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid, - Fam10BufferOptimizations, - Fam10GetNumCoresOnNode, - SetTotalNodesAndCores, - GetNodeCount, - LimitNodes, - ReadTrueLinkFailStatus, - Fam10GetNextLink, - GetPackageLink, - MakeLinkBase, - Fam10GetModuleInfo, - Fam10PostMailbox, - Fam10RetrieveMailbox, - Fam10GetSocket, - (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, - (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, - 0x00000001, - 0x00000200, - 18, - TRUE, - TRUE, - ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)), - NULL, - 0, - NULL, - MakeKey, - NULL -}; - -/** - * Initial construction data for Family 10h North Bridge, default, full features. - */ -CONST NORTHBRIDGE ROMDATA HtFam10RevDNbDefault = -{ - 8, - WriteRoutingTable, - WriteNodeID, - ReadDefaultLink, - EnableRoutingTables, - DisableRoutingTables, - VerifyLinkIsCoherent, - ReadToken, - WriteToken, - WriteFullRoutingTable, - IsIllegalTypeMix, - Fam10IsExceededCapable, - Fam10StopLink, - (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, - HandleSpecialNodeCase, - ReadSouthbridgeLink, - VerifyLinkIsNonCoherent, - Fam10SetConfigAddrMap, - Fam10RevDNorthBridgeFreqMask, - GatherLinkFeatures, - SetLinkRegang, - SetLinkFrequency, - SetLinkUnitIdClumping, - Fam10WriteTrafficDistribution, - Fam10WriteLinkPairDistribution, - (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid, - Fam10RevDBufferOptimizations, - Fam10RevDGetNumCoresOnNode, - SetTotalNodesAndCores, - GetNodeCount, - LimitNodes, - ReadTrueLinkFailStatus, - Fam10GetNextLink, - GetPackageLink, - MakeLinkBase, - Fam10GetModuleInfo, - Fam10PostMailbox, - Fam10RetrieveMailbox, - Fam10RevDGetSocket, - (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, - (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, - 0x00000001, - 0x00000200, - 18, - TRUE, - TRUE, - (AMD_FAMILY_10_HY), - (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap, - 0, - (IGNORE_LINK *)&Fam10RevDIgnoreLinkList, - MakeKey, - NULL -}; - -/** - * Initial construction data for Family 10h North Bridge, default, full features. - */ -CONST NORTHBRIDGE ROMDATA HtFam10RevENbDefault = -{ - 8, - WriteRoutingTable, - WriteNodeID, - ReadDefaultLink, - EnableRoutingTables, - DisableRoutingTables, - VerifyLinkIsCoherent, - ReadToken, - WriteToken, - WriteFullRoutingTable, - IsIllegalTypeMix, - Fam10IsExceededCapable, - Fam10StopLink, - (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, - HandleSpecialNodeCase, - ReadSouthbridgeLink, - VerifyLinkIsNonCoherent, - Fam10SetConfigAddrMap, - Fam10NorthBridgeFreqMask, - GatherLinkFeatures, - SetLinkRegang, - SetLinkFrequency, - SetLinkUnitIdClumping, - Fam10WriteTrafficDistribution, - Fam10WriteLinkPairDistribution, - (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid, - Fam10BufferOptimizations, - Fam10RevDGetNumCoresOnNode, - SetTotalNodesAndCores, - GetNodeCount, - LimitNodes, - ReadTrueLinkFailStatus, - Fam10GetNextLink, - GetPackageLink, - MakeLinkBase, - Fam10GetModuleInfo, - Fam10PostMailbox, - Fam10RetrieveMailbox, - Fam10GetSocket, - (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, - (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, - 0x00000001, - 0x00000200, - 18, - TRUE, - TRUE, - (AMD_FAMILY_10_PH), - NULL, - 0, - NULL, - MakeKey, - NULL -}; - -/** - * Initial construction data for Family 10h North Bridge, for non-coherent only builds. - */ -CONST NORTHBRIDGE ROMDATA HtFam10NbNonCoherentOnly = -{ - 8, - (PF_WRITE_ROUTING_TABLE)CommonVoid, - (PF_WRITE_NODEID)CommonVoid, - (PF_READ_DEFAULT_LINK)CommonReturnZero8, - (PF_ENABLE_ROUTING_TABLES)CommonVoid, - (PF_DISABLE_ROUTING_TABLES)CommonVoid, - (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse, - (PF_READ_TOKEN)CommonReturnZero8, - (PF_WRITE_TOKEN)CommonVoid, - (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid, - (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse, - (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse, - (PF_STOP_LINK)CommonVoid, - (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, - (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse, - ReadSouthbridgeLink, - VerifyLinkIsNonCoherent, - Fam10SetConfigAddrMap, - Fam10NorthBridgeFreqMask, - GatherLinkFeatures, - SetLinkRegang, - SetLinkFrequency, - SetLinkUnitIdClumping, - (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid, - (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid, - (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid, - Fam10BufferOptimizations, - Fam10GetNumCoresOnNode, - SetTotalNodesAndCores, - GetNodeCount, - LimitNodes, - ReadTrueLinkFailStatus, - Fam10GetNextLink, - GetPackageLink, - MakeLinkBase, - Fam10GetModuleInfo, - Fam10PostMailbox, - Fam10RetrieveMailbox, - Fam10GetSocket, - (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, - (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, - 0x00000001, - 0x00000200, - 18, - TRUE, - TRUE, - ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)), - NULL, - 0, - NULL, - MakeKey, - NULL -}; - -/** - * Initial construction data for Family 10h North Bridge, for RevD compatible non-coherent only builds. - */ -CONST NORTHBRIDGE ROMDATA HtFam10RevDNbNonCoherentOnly = -{ - 8, - (PF_WRITE_ROUTING_TABLE)CommonVoid, - (PF_WRITE_NODEID)CommonVoid, - (PF_READ_DEFAULT_LINK)CommonReturnZero8, - (PF_ENABLE_ROUTING_TABLES)CommonVoid, - (PF_DISABLE_ROUTING_TABLES)CommonVoid, - (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse, - (PF_READ_TOKEN)CommonReturnZero8, - (PF_WRITE_TOKEN)CommonVoid, - (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid, - (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse, - (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse, - (PF_STOP_LINK)CommonVoid, - (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, - (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse, - ReadSouthbridgeLink, - VerifyLinkIsNonCoherent, - Fam10SetConfigAddrMap, - Fam10RevDNorthBridgeFreqMask, - GatherLinkFeatures, - SetLinkRegang, - SetLinkFrequency, - SetLinkUnitIdClumping, - (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid, - (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid, - (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid, - Fam10BufferOptimizations, - Fam10RevDGetNumCoresOnNode, - SetTotalNodesAndCores, - GetNodeCount, - LimitNodes, - ReadTrueLinkFailStatus, - Fam10GetNextLink, - GetPackageLink, - MakeLinkBase, - Fam10GetModuleInfo, - Fam10PostMailbox, - Fam10RetrieveMailbox, - Fam10GetSocket, - (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, - (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, - 0x00000001, - 0x00000200, - 18, - TRUE, - TRUE, - (AMD_FAMILY_10_HY), - NULL, - 0, - NULL, - MakeKey, - NULL -}; - -/** - * Initial construction data for Family 10h North Bridge, for RevE compatible non-coherent only builds. - */ -CONST NORTHBRIDGE ROMDATA HtFam10RevENbNonCoherentOnly = -{ - 8, - (PF_WRITE_ROUTING_TABLE)CommonVoid, - (PF_WRITE_NODEID)CommonVoid, - (PF_READ_DEFAULT_LINK)CommonReturnZero8, - (PF_ENABLE_ROUTING_TABLES)CommonVoid, - (PF_DISABLE_ROUTING_TABLES)CommonVoid, - (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse, - (PF_READ_TOKEN)CommonReturnZero8, - (PF_WRITE_TOKEN)CommonVoid, - (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid, - (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse, - (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse, - (PF_STOP_LINK)CommonVoid, - (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, - (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse, - ReadSouthbridgeLink, - VerifyLinkIsNonCoherent, - Fam10SetConfigAddrMap, - Fam10NorthBridgeFreqMask, - GatherLinkFeatures, - SetLinkRegang, - SetLinkFrequency, - SetLinkUnitIdClumping, - (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid, - (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid, - (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid, - Fam10BufferOptimizations, - Fam10RevDGetNumCoresOnNode, - SetTotalNodesAndCores, - GetNodeCount, - LimitNodes, - ReadTrueLinkFailStatus, - Fam10GetNextLink, - GetPackageLink, - MakeLinkBase, - Fam10GetModuleInfo, - Fam10PostMailbox, - Fam10RetrieveMailbox, - Fam10GetSocket, - (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, - (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, - 0x00000001, - 0x00000200, - 18, - TRUE, - TRUE, - (AMD_FAMILY_10_PH), - NULL, - 0, - NULL, - MakeKey, - NULL -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.c deleted file mode 100644 index 4f852ec70c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.c +++ /dev/null @@ -1,121 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge non-coherent support for Family 10h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbNonCoherentFam10.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable config access to a non-coherent chain for the given bus range. - * - * @HtNbMethod{::F_SET_CONFIG_ADDR_MAP} - * - * @param[in] ConfigMapIndex the map entry to set - * @param[in] SecBus The secondary bus number to use - * @param[in] SubBus The subordinate bus number to use - * @param[in] TargetNode The Node that shall be the recipient of the traffic - * @param[in] TargetLink The Link that shall be the recipient of the traffic - * @param[in] State our global state - * @param[in] Nb this northbridge - */ -VOID -Fam10SetConfigAddrMap ( - IN UINT8 ConfigMapIndex, - IN UINT8 SecBus, - IN UINT8 SubBus, - IN UINT8 TargetNode, - IN UINT8 TargetLink, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ) -{ - UINT8 CurNode; - PCI_ADDR Reg; - UINT32 Temp; - - Reg = Nb->MakeLinkBase (TargetNode, TargetLink, Nb); - - ASSERT (SecBus <= SubBus); - ASSERT (TargetNode <= State->NodesDiscovered); - ASSERT (TargetLink < Nb->MaxLinks); - Temp = SecBus; - Reg.Address.Register += HTHOST_ISOC_REG; - LibAmdPciWriteBits (Reg, 15, 8, &Temp, Nb->ConfigHandle); - - Temp = ((UINT32)SubBus << 24) + ((UINT32)SecBus << 16) + ((UINT32)TargetLink << 8) + - ((UINT32)TargetNode << 4) + (UINT32)3; - for (CurNode = 0; CurNode < (State->NodesDiscovered + 1); CurNode++) { - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (CurNode), - MakePciBusFromNode (CurNode), - MakePciDeviceFromNode (CurNode), - CPU_ADDR_FUNC_01, - REG_ADDR_CONFIG_MAP0_1XE0 + (4 * ConfigMapIndex)); - LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.h deleted file mode 100644 index af621dfedc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.h +++ /dev/null @@ -1,58 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge non-coherent support for Family 10h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/** - * Enable config access to a non-coherent chain for the given bus range. - * - */ -VOID -Fam10SetConfigAddrMap ( - IN UINT8 ConfigMapIndex, - IN UINT8 SecBus, - IN UINT8 SubBus, - IN UINT8 TargetNode, - IN UINT8 TargetLink, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbOptimizationFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbOptimizationFam10.c deleted file mode 100644 index c7b138ebae..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbOptimizationFam10.c +++ /dev/null @@ -1,222 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Link optimization support specific to family 10h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "htNbOptimizationFam10.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Northbridge specific Frequency limit. - * - * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK} - * - * Return a mask that eliminates HT frequencies that cannot be used due to a slow - * northbridge frequency. - * - * @param[in] Node Result could (later) be for a specific Node - * @param[in] Interface Access to non-HT support functions. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] Nb this northbridge - * - * @return Frequency mask - */ -UINT32 -Fam10NorthBridgeFreqMask ( - IN UINT8 Node, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 NbCoreFreq; - UINT32 Supported; - - ASSERT (Node < MAX_NODES); - ASSERT (Interface != NULL); - // The interface to power management will return a system based result. - // So we only need to call it once, not on every link. Save the answer, - // and check to see if we can use a saved answer on subsequent calls. - // - if (Nb->CoreFrequency == 0) { - NbCoreFreq = Interface->GetMinNbCoreFreq (PlatformConfig, Nb->ConfigHandle); - NbCoreFreq = (NbCoreFreq / 100); - ASSERT (NbCoreFreq != 0); - Nb->CoreFrequency = NbCoreFreq; - } else { - NbCoreFreq = Nb->CoreFrequency; - } - - // - // NbCoreFreq is minimum northbridge speed in hundreds of MHz. - // HT can not go faster than the minimum speed of the northbridge. - // - if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) { - // Convert frequency to bit and all less significant bits, - // by setting next power of 2 and subtracting 1. - // - Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1; - } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) { - // Convert frequency to bit and all less significant bits, - // by setting next power of 2 and subtracting 1, noting that - // next power of two is two greater than non-extended frequencies - // (because of the register break). - // - Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1; - } else if (NbCoreFreq > 32) { - Supported = HT_FREQUENCY_LIMIT_MAX; - } else if (NbCoreFreq == 4) { - // unlikely cases, but include as a defensive measure, also avoid trick above - Supported = HT_FREQUENCY_LIMIT_400M; - } else if (NbCoreFreq == 2) { - Supported = HT_FREQUENCY_LIMIT_200M; - } else { - ASSERT (FALSE); - Supported = HT_FREQUENCY_LIMIT_200M; - } - - return (Supported); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Northbridge specific Frequency limit. - * - * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK} - * - * Return a mask that eliminates HT frequencies that cannot be used due to a slow - * northbridge frequency. - * - * @param[in] Node Result could (later) be for a specific Node - * @param[in] Interface Access to non-HT support functions. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] Nb this northbridge - * - * @return Frequency mask - */ -UINT32 -Fam10RevDNorthBridgeFreqMask ( - IN UINT8 Node, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 NbCoreFreq; - UINT32 Supported; - - ASSERT (Node < MAX_NODES); - ASSERT (Interface != NULL); - // The interface to power management will return a system based result. - // So we only need to call it once, not on every link. Save the answer, - // and check to see if we can use a saved answer on subsequent calls. - // - if (Nb->CoreFrequency == 0) { - NbCoreFreq = Interface->GetMinNbCoreFreq (PlatformConfig, Nb->ConfigHandle); - NbCoreFreq = (NbCoreFreq / 100); - ASSERT (NbCoreFreq != 0); - Nb->CoreFrequency = NbCoreFreq; - } else { - NbCoreFreq = Nb->CoreFrequency; - } - - // For Rev D, the Ht frequency can go twice the Nb COF, as long as it's HT3. - // (side note: we are not speculatively upgrading HT1 at 6 .. 10 to HT3, - // to avoid complicated recovery if the final speed is HT1.) - if (NbCoreFreq > 10) { - NbCoreFreq = NbCoreFreq * 2; - } - // - // NbCoreFreq is minimum northbridge speed in hundreds of MHz. - // HT can not go faster than the minimum speed of the northbridge. - // - if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) { - // Convert frequency to bit and all less significant bits, - // by setting next power of 2 and subtracting 1. - // - Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1; - } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) { - // Convert frequency to bit and all less significant bits, - // by setting next power of 2 and subtracting 1, noting that - // next power of two is two greater than non-extended frequencies - // (because of the register break). - // - Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1; - } else if (NbCoreFreq > 32) { - Supported = HT_FREQUENCY_LIMIT_MAX; - } else if (NbCoreFreq == 4) { - // unlikely cases, but include as a defensive measure, also avoid trick above - Supported = HT_FREQUENCY_LIMIT_400M; - } else if (NbCoreFreq == 2) { - Supported = HT_FREQUENCY_LIMIT_200M; - } else { - ASSERT (FALSE); - Supported = HT_FREQUENCY_LIMIT_200M; - } - - return (Supported); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbOptimizationFam10.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbOptimizationFam10.h deleted file mode 100644 index ca75b7fb6c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbOptimizationFam10.h +++ /dev/null @@ -1,74 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Link optimization support specific to family 10h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -/** - * Northbridge specific Frequency limit. - * - */ -UINT32 -Fam10NorthBridgeFreqMask ( - IN UINT8 Node, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ); - -/** - * Northbridge specific Frequency limit. - * - */ -UINT32 -Fam10RevDNorthBridgeFreqMask ( - IN UINT8 Node, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c deleted file mode 100644 index ed921a2e43..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c +++ /dev/null @@ -1,402 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * System Tuning Family 10h specific routines - * - * Support for Traffic Distribution and buffer tunings which - * can not be done in a register table. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbSystemFam10.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/** - * Register Fields for an individual link pair. - */ -typedef struct { - UINT32 Enable:1; ///< Enable distribution on this pair. - UINT32 Asymmetric:1; ///< Links are different widths. - UINT32 MasterSelect:3; ///< The master link. - UINT32 AlternateSelect:3; ///< The alternate link. -} PAIR_SELECT_FIELDS; - -/** - * Register access union for ::PAIR_SELECT_FIELDS. - */ -typedef union { - UINT32 Value; ///< access as a 32 bit value or register. - PAIR_SELECT_FIELDS Fields; ///< access individual fields. -} PAIR_SELECT; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Set the traffic distribution register for the Links provided. - * - * @HtNbMethod{::F_WRITE_TRAFFIC_DISTRIBUTION} - * - * @param[in] Links01 coherent Links from Node 0 to 1 - * @param[in] Links10 coherent Links from Node 1 to 0 - * @param[in] Nb this northbridge - */ -VOID -Fam10WriteTrafficDistribution ( - IN UINT32 Links01, - IN UINT32 Links10, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR TrafficDistReg; - - TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0), - MakePciBusFromNode (0), - MakePciDeviceFromNode (0), - CPU_HTNB_FUNC_00, - REG_HT_TRAFFIC_DIST_0X164); - - // Node 0 - // DstLnk - LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links01, Nb->ConfigHandle); - // DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 - Temp = 0x0107; - LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle); - - TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (1), - MakePciBusFromNode (1), - MakePciDeviceFromNode (1), - CPU_HTNB_FUNC_00, - REG_HT_TRAFFIC_DIST_0X164); - - // Node 1 - // DstLnk - LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links10, Nb->ConfigHandle); - // DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 - Temp = 0x0007; - LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write a link pair to the link pair distribution and fixups. - * - * @HtNbMethod{::F_WRITE_LINK_PAIR_DISTRIBUTION} - * - * Set the links as a pair using the link pair index provided. Set asymmetric attribute as - * provided. If the Master Link is not currently used as the route, fixup the routes for all - * nodes which specify the alternate link. - * - * @param[in] Node Set the pair on this node - * @param[in] ConnectedNode The Node to which this link pair directly connects. - * @param[in] Pair Using this pair set in the register - * @param[in] Asymmetric True if different widths - * @param[in] MasterLink Set this as the master link and in the route - * @param[in] AlternateLink Set this as the alternate link - * @param[in] Nb this northbridge - * - */ -VOID -Fam10WriteLinkPairDistribution ( - IN UINT8 Node, - IN UINT8 ConnectedNode, - IN UINT8 Pair, - IN BOOLEAN Asymmetric, - IN UINT8 MasterLink, - IN UINT8 AlternateLink, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 CurrentRoute; - UINT32 MasterRoute; - UINT32 AlternateRoute; - PAIR_SELECT Selection; - UINT32 RouteIndex; - - ASSERT ((Node < MAX_NODES) && (ConnectedNode < MAX_NODES)); - ASSERT (Pair < MAX_LINK_PAIRS); - ASSERT (MasterLink < Nb->MaxLinks); - ASSERT (AlternateLink < Nb->MaxLinks); - - // Make the master link the route for all routes to or through NodeB, by replacing all occurrences of - // Alternate link with Master link. If routing used the master link, no update is necessary. - MasterRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (MasterLink + 1)); - AlternateRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (AlternateLink + 1)); - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_ROUTE0_0X40); - for (RouteIndex = 0; RouteIndex < MAX_NODES; RouteIndex++) { - Reg.Address.Register = REG_ROUTE0_0X40 + (RouteIndex * 4); - LibAmdPciReadBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle); - if ((CurrentRoute & AlternateRoute) != 0) { - // Since Master and Alternate are redundant, the route must use one or the other but not both. - ASSERT ((CurrentRoute & MasterRoute) == 0); - // Set the master route for Request, Response or Broadcast only if the alternate was used for that case. - // Example, use of a link as a broadcast link is typically not the same route register as its use for Request, Response. - CurrentRoute = ((CurrentRoute & ~AlternateRoute) | - ((((CurrentRoute & AlternateRoute) >> (AlternateLink + 1)) << (MasterLink + 1)) & MasterRoute)); - LibAmdPciWriteBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle); - } - } - - // Set the Link Pair and Enable it - Selection.Fields.Enable = 1; - Selection.Fields.Asymmetric = Asymmetric; - Selection.Fields.MasterSelect = MasterLink; - Selection.Fields.AlternateSelect = AlternateLink; - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_HT_LINK_PAIR_DIST_0X1E0); - LibAmdPciWriteBits ( - Reg, - ((PAIR_SELECT_OFFSET * (Pair + 1)) - 1), - (PAIR_SELECT_OFFSET * Pair), - &Selection.Value, - Nb->ConfigHandle - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Family 10h specific tunings. - * - * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS} - * - * Buffer tunings are inherently northbridge specific. Check for specific configs - * which require adjustments and apply any standard workarounds to this Node. - * - * @param[in] Node the Node to tune - * @param[in] State global state - * @param[in] Nb this northbridge - */ -VOID -Fam10BufferOptimizations ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR currentPtr; - PCI_ADDR GangedReg; - UINT8 i; - - ASSERT (Node < MAX_NODES); - - // - // Link to XCS Token Count Tuning - // - // For each active Link that we reganged (so this unfortunately can't go into the PCI reg - // table), we have to switch the Link to XCS Token Counts to the ganged state. - // We do this here for the non - uma case, which is to write the values that would have - // been power on defaults if the Link was ganged at cold reset. - // - for (i = 0; i < (State->TotalLinks * 2); i++) { - if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) { - // If the Link is greater than 4, this is a subLink 1, so it is not reganged. - if ((*State->PortList)[i].Link < 4) { - currentPtr.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_LINK_XCS_TOKEN0_3X148 + (4 * (*State->PortList)[i].Link) - ); - if ((*State->PortList)[i].SelRegang) { - // Handle all the regang Token count adjustments - - // SubLink 0: [Probe0tok] = 2 [Rsp0tok] = 2 [PReq0tok] = 2 [Req0tok] = 2 - Temp = 0xAA; - LibAmdPciWriteBits (currentPtr, 7, 0, &Temp, Nb->ConfigHandle); - // SubLink 1: [Probe1tok] = 0 [Rsp1tok] = 0 [PReq1tok] = 0 [Req1tok] = 0 - Temp = 0; - LibAmdPciWriteBits (currentPtr, 23, 16, &Temp, Nb->ConfigHandle); - // [FreeTok] = 3 - Temp = 3; - LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle); - - } else { - // Read the regang bit in hardware - GangedReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode ((*State->PortList)[i].NodeID), - MakePciBusFromNode ((*State->PortList)[i].NodeID), - MakePciDeviceFromNode ((*State->PortList)[i].NodeID), - CPU_HTNB_FUNC_00, - REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link)); - LibAmdPciReadBits (GangedReg, 0, 0, &Temp, Nb->ConfigHandle); - if (Temp == 1) { - // handle a minor adjustment for strapped ganged Links. If SelRegang is false we - // didn't do the regang, so if the bit is on then it's hardware strapped. - // - - // [FreeTok] = 3 - Temp = 3; - LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle); - } - } - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Family 10h specific tunings. - * - * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS} - * - * Buffer tunings are inherently northbridge specific. Check for specific configs - * which require adjustments and apply any standard workarounds to this Node. - * - * @param[in] Node the Node to tune - * @param[in] State global state - * @param[in] Nb this northbridge - */ -VOID -Fam10RevDBufferOptimizations ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR Reg; - UINT8 i; - FINAL_LINK_STATE FinalLinkState; - UINT32 WidthIn; - UINT32 WidthOut; - - ASSERT (Node < MAX_NODES); - - // - // Internal link fixup. - // When powering off internal link 2, a performance optimization may be possible where its buffers - // can be made available to the external paired sublink. If the conditions are met, do the fix up here. - // - for (i = 0; i < (State->TotalLinks * 2); i++) { - if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) { - // Is this a sublink 0 paired with internal link 2? - if (((*State->PortList)[i].Link < 4) && - (Nb->GetPackageLink (Node, ((*State->PortList)[i].Link + 4), Nb) == HT_LIST_MATCH_INTERNAL_LINK_2)) { - FinalLinkState = State->HtInterface->GetIgnoreLink (Node, ((*State->PortList)[i].Link + 4), Nb->DefaultIgnoreLinkList, State); - // Are we ignoring the internal link 2 with Power Off? - if (FinalLinkState == POWERED_OFF) { - // Read the regang bit in hardware. - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link)); - LibAmdPciReadBits (Reg, 0, 0, &Temp, Nb->ConfigHandle); - // If it's already ganged, skip to the width fix up. - if (Temp == 0) { - // Clear EndOfChain / XmitOff on internal sublink - Reg = Nb->MakeLinkBase (Node, ((*State->PortList)[i].Link + 4), Nb); - Reg.Address.Register += HTHOST_LINK_CONTROL_REG; - Temp = 0; - State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State); - - // Gang the link - Nb->SetLinkRegang (Node, (*State->PortList)[i].Link, Nb); - } - - // Set InLnSt = PHY_OFF in register table. - // Set sublink 0 widths to 8 bits - if ((*State->PortList)[i].SelWidthOut > 8) { - (*State->PortList)[i].SelWidthOut = 8; - } - if ((*State->PortList)[i].SelWidthIn > 8) { - (*State->PortList)[i].SelWidthIn = 8; - } - WidthOut = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthOut); - WidthIn = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthIn); - Temp = (WidthIn & 7) | ((WidthOut & 7) << 4); - Reg = Nb->MakeLinkBase (Node, (*State->PortList)[i].Link, Nb); - Reg.Address.Register += HTHOST_LINK_CONTROL_REG; - State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State); - } - } - } - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.h deleted file mode 100644 index 9a9647d63c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.h +++ /dev/null @@ -1,91 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * System Tuning Family 10h specific routines - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/** - * Set the traffic distribution register for the Links provided. - * - */ -VOID -Fam10WriteTrafficDistribution ( - IN UINT32 Links01, - IN UINT32 Links10, - IN NORTHBRIDGE *Nb - ); - -/** - * Write a link pair to the link pair distribution and fixups. - * - */ -VOID -Fam10WriteLinkPairDistribution ( - IN UINT8 Node, - IN UINT8 ConnectedNode, - IN UINT8 Pair, - IN BOOLEAN Asymmetric, - IN UINT8 MasterLink, - IN UINT8 AlternateLink, - IN NORTHBRIDGE *Nb - ); - -/** - * Family 10h specific tunings. - * - */ -VOID -Fam10BufferOptimizations ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); - -/** - * Family 10h Rev D specific tunings. - * - */ -VOID -Fam10RevDBufferOptimizations ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.c deleted file mode 100644 index 8241a6370c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.c +++ /dev/null @@ -1,445 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge utility routines. - * - * These routines are needed for support of more than one feature area. - * Collect them in this file so build options don't remove them. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbUtilitiesFam10.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Return the number of cores (1 based count) on Node. - * - * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE} - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - * - * @return the number of cores - */ -UINT8 -Fam10GetNumCoresOnNode ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Result; - UINT32 Leveling; - UINT32 Cores; - UINT8 i; - PCI_ADDR Reg; - - ASSERT ((Node < MAX_NODES)); - // Read CmpCap - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8); - - LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle); - - // Support Downcoring - Result = Cores; - Cores++; - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_DOWNCORE_3X190); - LibAmdPciReadBits (Reg, 3, 0, &Leveling, Nb->ConfigHandle); - for (i = 0; i < Cores; i++) { - if ((Leveling & ((UINT32) 1 << i)) != 0) { - Result--; - } - } - return (UINT8) (Result + 1); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Return the number of cores (1 based count) on Node. - * - * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}. - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - * - * @return the number of cores - */ -UINT8 -Fam10RevDGetNumCoresOnNode ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Result; - UINT32 Leveling; - UINT32 Cores; - UINT32 Cores2; - UINT8 i; - PCI_ADDR Reg; - - ASSERT ((Node < MAX_NODES)); - // Read CmpCap - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8); - - LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle); - LibAmdPciReadBits (Reg, 15, 15, &Cores2, Nb->ConfigHandle); - Cores = Cores + (Cores2 << 2); - - // Support Downcoring - Result = Cores; - Cores++; - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_DOWNCORE_3X190); - LibAmdPciReadBits (Reg, 5, 0, &Leveling, Nb->ConfigHandle); - for (i = 0; i < Cores; i++) { - if ((Leveling & ((UINT32) 1 << i)) != 0) { - Result--; - } - } - return (UINT8) (Result + 1); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the next link for iterating over the links on a node in the correct order. - * - * @HtNbMethod{::F_GET_NEXT_LINK} - * - * Family 10h specific implementation use the Internal Link field in - * the northbridge to prioritize internal links in the order. - * - * @param[in] Node The node on which to iterate links. - * @param[in,out] Link IN: the current iteration context, OUT: the next link. - * @param[in] Nb This Northbridge, access to config pointer. - * - * @retval LinkIteratorExternal The current Link is an external link. - * @retval LinkIteratorInternal The current Link is an internal link. - * @retval LinkIteratorEnd There is no next link (Link is back to BEGIN). - * - */ -LINK_ITERATOR_STATUS -Fam10GetNextLink ( - IN UINT8 Node, - IN OUT UINT8 *Link, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 InternalLinks; - UINT32 ExternalLinks; - UINT32 HigherLinks; - BOOLEAN IsInternalLink; - LINK_ITERATOR_STATUS Status; - - ASSERT ((Node < MAX_NODES)); - ASSERT ((*Link < Nb->MaxLinks) || (*Link == LINK_ITERATOR_BEGIN)); - InternalLinks = 0; - ExternalLinks = 0; - - // Read IntLnkRoute from the Link Initialization Status register. - // (Note that this register field is not reserved prior to rev D, but should be zero.) - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_HT_LINK_INITIALIZATION_0X1A0); - - LibAmdPciReadBits (Reg, 23, 16, &InternalLinks, Nb->ConfigHandle); - // The external links are all possible links which are not Internal - ExternalLinks = (((1 << Nb->MaxLinks) - 1) ^ InternalLinks); - // Can't have no possible links! - ASSERT ((ExternalLinks != 0) || (InternalLinks != 0)); - - - if (*Link == LINK_ITERATOR_BEGIN) { - // If the request is for the first link (BEGIN), get it - if (InternalLinks != 0) { - *Link = LibAmdBitScanForward (InternalLinks); - Status = LinkIteratorInternal; - } else { - *Link = LibAmdBitScanForward (ExternalLinks); - Status = LinkIteratorExternal; - } - } else { - // If the iterator is not at the beginning, search for the next Link starting from the - // current link. - HigherLinks = InternalLinks & ~((1 << (*Link + 1)) - 1); - IsInternalLink = (BOOLEAN) ((InternalLinks & (1 << *Link)) != 0); - if (IsInternalLink && (HigherLinks != 0)) { - // We are still on internal links and there are more to do. - *Link = LibAmdBitScanForward (HigherLinks); - Status = LinkIteratorInternal; - } else { - if (IsInternalLink) { - // We are transitioning now from internal to external, so get the first external link - HigherLinks = ExternalLinks; - } else { - // We are already iterating over external links, so get the next one - HigherLinks = ExternalLinks & ~((1 << (*Link + 1)) - 1); - } - if (HigherLinks != 0) { - *Link = LibAmdBitScanForward (HigherLinks); - Status = LinkIteratorExternal; - } else { - // The end of all links - *Link = LINK_ITERATOR_BEGIN; - Status = LinkIteratorEnd; - } - } - } - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Info about Module Type of this northbridge - * - * @HtNbMethod{::F_GET_MODULE_INFO} - * - * Provide the Processor module type, single or multi, and the node's module id. - * - * @param[in] Node the Node - * @param[out] ModuleType 0 for Single, 1 for Multi - * @param[out] Module The module number of this node (0 if Single) - * @param[in] Nb this northbridge - * - */ -VOID -Fam10GetModuleInfo ( - IN UINT8 Node, - OUT UINT8 *ModuleType, - OUT UINT8 *Module, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 MultNodeCpu; - UINT32 IntNodeNum; - - ASSERT (Node < MAX_NODES); - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8); - LibAmdPciReadBits (Reg, 29, 29, &MultNodeCpu, Nb->ConfigHandle); - LibAmdPciReadBits (Reg, 31, 30, &IntNodeNum, Nb->ConfigHandle); - - *ModuleType = (UINT8) MultNodeCpu; - *Module = (UINT8) IntNodeNum; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. - * - * @HtNbMethod{::F_GET_SOCKET} - * - * The hardware socket naming method is not available for Family 10h prior to rev D. - * - * @param[in] Node The node for which we want the socket id. - * @param[in] TempNode The temporary node id route where the node can be accessed. - * @param[in] Nb Our Northbridge. - * - * @return The Socket Id - */ -UINT8 -Fam10GetSocket ( - IN UINT8 Node, - IN UINT8 TempNode, - IN NORTHBRIDGE *Nb - ) -{ - ASSERT ((Node < MAX_NODES)); - ASSERT (TempNode < MAX_NODES); - ASSERT (Nb != NULL); - return (Node); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. - * - * @HtNbMethod{::F_GET_SOCKET} - * - * The Socket Id is strapped to the Sbi Control Register, F3X1E4[6:4]SbiAddr. - * - * @param[in] Node The node for which we want the socket id. - * @param[in] TempNode The temporary node id route where the node can be accessed. - * @param[in] Nb Our Northbridge. - * - * @return The Socket Id - */ -UINT8 -Fam10RevDGetSocket ( - IN UINT8 Node, - IN UINT8 TempNode, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Socket; - PCI_ADDR Reg; - - ASSERT ((TempNode < MAX_NODES)); - ASSERT ((Node < MAX_NODES)); - // Read SbiAddr - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (TempNode), - MakePciBusFromNode (TempNode), - MakePciDeviceFromNode (TempNode), - CPU_NB_FUNC_03, - REG_NB_SBI_CONTROL_3X1E4); - LibAmdPciReadBits (Reg, 6, 4, &Socket, Nb->ConfigHandle); - return ((UINT8) Socket); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Post info to AP cores via a mailbox. - * - * @HtNbMethod{::F_POST_MAILBOX} - * - * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id, - * and module info. - * - * @param[in] Node the Node - * @param[in] ApMailboxes The info to post - * @param[in] Nb this northbridge - * - */ -VOID -Fam10PostMailbox ( - IN UINT8 Node, - IN AP_MAILBOXES ApMailboxes, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - - ASSERT (Node < MAX_NODES); - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_MCA_LINK_THRESHOLD_3X168); - LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailInfo.Info, Nb->ConfigHandle); - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_MCA_L3_THRESHOLD_3X170); - LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Retrieve info from a node's mailbox. - * - * @HtNbMethod{::F_RETRIEVE_MAILBOX} - * - * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id, - * and module info. - * - * @param[in] Node the Node - * @param[in] Nb this northbridge - * - * @return The ap mailbox info - * - */ -AP_MAIL_INFO -Fam10RetrieveMailbox ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - AP_MAIL_INFO ApMailInfo; - - ASSERT (Node < MAX_NODES); - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_MCA_LINK_THRESHOLD_3X168); - LibAmdPciReadBits (Reg, 11, 0, &ApMailInfo.Info, Nb->ConfigHandle); - return ApMailInfo; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.h deleted file mode 100644 index aaa1ca4621..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.h +++ /dev/null @@ -1,129 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge utility routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/** - * Return the number of cores (1 based count) on Node. - * - */ -UINT8 -Fam10GetNumCoresOnNode ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/** - * Return the number of cores (1 based count) on Node. - * - */ -UINT8 -Fam10RevDGetNumCoresOnNode ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/** - * Get the next link for iterating over the links on a node in the correct order. - * - */ -LINK_ITERATOR_STATUS -Fam10GetNextLink ( - IN UINT8 Node, - IN OUT UINT8 *Link, - IN NORTHBRIDGE *Nb - ); - -/** - * Get Info about Module Type of this northbridge - * - */ -VOID -Fam10GetModuleInfo ( - IN UINT8 Node, - OUT UINT8 *ModuleType, - OUT UINT8 *Module, - IN NORTHBRIDGE *Nb - ); - -/** - * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. - * - */ -UINT8 -Fam10GetSocket ( - IN UINT8 Node, - IN UINT8 TempNode, - IN NORTHBRIDGE *Nb - ); - -/** - * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. - * - */ -UINT8 -Fam10RevDGetSocket ( - IN UINT8 Node, - IN UINT8 TempNode, - IN NORTHBRIDGE *Nb - ); - -/** - * Post info to AP cores via a mailbox. - * - */ -VOID -Fam10PostMailbox ( - IN UINT8 Node, - IN AP_MAILBOXES ApMailboxes, - IN NORTHBRIDGE *Nb - ); - -/** - * Retrieve info from a node's mailbox. - * - */ -AP_MAIL_INFO -Fam10RetrieveMailbox ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/Makefile.inc deleted file mode 100644 index ae6cae44e0..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -libagesa-y += htNbCoherentFam15.c -libagesa-y += htNbFam15.c -libagesa-y += htNbNonCoherentFam15.c -libagesa-y += htNbOptimizationFam15.c -libagesa-y += htNbSystemFam15.c -libagesa-y += htNbUtilitiesFam15.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.c deleted file mode 100644 index 11083e8d18..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.c +++ /dev/null @@ -1,162 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Coherent Family 15h Routines. - * - * Coherent feature Northbridge implementation specific to Family 15h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbCoherentFam15.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Return whether the current configuration exceeds the capability. - * - * @HtNbMethod{::F_IS_EXCEEDED_CAPABLE}. - * - * Get Node capability and update the minimum supported system capability. - * - * @param[in] Node the Node - * @param[in] State sysMpCap (updated) and NodesDiscovered - * @param[in] Nb this northbridge - * - * @retval TRUE system is not capable of current config. - * @retval FALSE system is capable of current config. - */ -BOOLEAN -Fam15IsExceededCapable ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - UINT8 MaxNodes; - PCI_ADDR Reg; - - ASSERT (Node < MAX_NODES); - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8); - - LibAmdPciReadBits (Reg, 18, 16, &Temp, Nb->ConfigHandle); - - if (Temp != 0) { - MaxNodes = (UINT8) (1 << (~Temp & 0x3)); // That is, 1, 2, 4, or 8 - } else { - MaxNodes = 8; - } - if (State->SysMpCap > MaxNodes) { - State->SysMpCap = MaxNodes; - } - // Note since sysMpCap is one based and NodesDiscovered is zero based, equal returns true - // - return ((BOOLEAN) (State->SysMpCap <= State->NodesDiscovered)); -} - -/** - * Stop a link, so that it is isolated from a connected device. - * - * @HtNbMethod{::F_STOP_LINK}. - * - * Use is for fatal incompatible configurations, or for user interface - * request to power off a link (IgnoreLink, SkipRegang). - * Set ConnDly to make the power effective at the warm reset. - * Set XMT and RCV off. - * - * @param[in] Node the node to stop a link on. - * @param[in] Link the link to stop. - * @param[in] State access to special routine for writing link control register - * @param[in] Nb this northbridge. - */ -VOID -Fam15StopLink ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR Reg; - - // Set ConnDly - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_LINK_GLOBAL_EXT_CONTROL_0x16C); - Temp = 1; - LibAmdPciWriteBits (Reg, 8, 8, &Temp, Nb->ConfigHandle); - // Set TransOff and EndOfChain - Reg = Nb->MakeLinkBase (Node, Link, Nb); - Reg.Address.Register += HTHOST_LINK_CONTROL_REG; - Temp = 3; - State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.h deleted file mode 100644 index 11db99bf8d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.h +++ /dev/null @@ -1,67 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Coherent Family 15h specific Routines. - * - * Coherent feature Northbridge implementation specific to Family 15h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/** - * Return whether the current configuration exceeds the capability. - * - */ -BOOLEAN -Fam15IsExceededCapable ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); - -/** - * Stop a link, so that it is isolated from a connected device. - */ -VOID -Fam15StopLink ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbFam15.c deleted file mode 100644 index 112035594e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbFam15.c +++ /dev/null @@ -1,248 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initializers for Family 15h northbridge support. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44846 $ @e \$Date: 2011-01-06 22:21:05 -0700 (Thu, 06 Jan 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionsHt.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "CommonReturns.h" -#include "htNbCoherent.h" -#include "htNbCoherentFam15.h" -#include "htNbNonCoherent.h" -#include "htNbNonCoherentFam15.h" -#include "htNbOptimization.h" -#include "htNbOptimizationFam15.h" -#include "htNbSystemFam15.h" -#include "htNbUtilities.h" -#include "htNbUtilitiesFam15.h" -#include "cpuFamRegisters.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#include "Filecode.h" - -#define FILECODE PROC_HT_FAM15_HTNBFAM15_FILECODE - -extern OPTION_HT_CONFIGURATION OptionHtConfiguration; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** - ***************************************************************************/ - -/** - * Map Northbridge links to package links for Family 15h, multi-module. - * - * Unfortunately, there is no way to do this except to type the BKDG text into this data structure. - * Note that there is one entry per package external sublink and each connected internal link. - */ -CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[] = -{ - {3, 0, 0}, ///< Module zero, link 3: package link 0 - {7, 0, 4}, ///< Module zero, link 7: package link 4 - {0, 1, 1}, ///< Module one, link 0: package link 1 - {4, 1, 5}, ///< Module one, link 4: package link 5 - {1, 0, 2}, ///< Module zero, link 1: package link 2 - {5, 0, 6}, ///< Module zero, link 5: package link 6 - {0, 0, 3}, ///< Module zero, link 0: package link 3 - {3, 1, 7}, ///< Module one, link 3: package link 7 - {2, 0, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link - {6, 0, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link - {4, 0, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link - {1, 1, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link - {5, 1, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link - {7, 1, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link - {HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL}, ///< End -}; - -/** - * A default Ignore Link list to power off the 3rd internal sublink. - */ -STATIC CONST IGNORE_LINK ROMDATA Fam15IgnoreLinkList[] = { - {HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK_2, POWERED_OFF}, - {HT_LIST_TERMINAL} -}; - -/** - * Initial construction data for Family 15h North Bridge, default, full features. - */ -CONST NORTHBRIDGE ROMDATA HtFam15NbDefault = -{ - 8, - WriteRoutingTable, - WriteNodeID, - ReadDefaultLink, - EnableRoutingTables, - DisableRoutingTables, - VerifyLinkIsCoherent, - ReadToken, - WriteToken, - WriteFullRoutingTable, - IsIllegalTypeMix, - Fam15IsExceededCapable, - Fam15StopLink, - (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, - HandleSpecialNodeCase, - ReadSouthbridgeLink, - VerifyLinkIsNonCoherent, - Fam15SetConfigAddrMap, - Fam15NorthBridgeFreqMask, - GatherLinkFeatures, - SetLinkRegang, - SetLinkFrequency, - SetLinkUnitIdClumping, - Fam15WriteTrafficDistribution, - Fam15WriteLinkPairDistribution, - Fam15WriteVictimDistribution, - Fam15BufferOptimizations, - Fam15GetNumCoresOnNode, - SetTotalNodesAndCores, - GetNodeCount, - LimitNodes, - ReadTrueLinkFailStatus, - Fam15GetNextLink, - GetPackageLink, - MakeLinkBase, - Fam15GetModuleInfo, - Fam15PostMailbox, - Fam15RetrieveMailbox, - Fam15StrappedGetSocket, - Fam15GetEnabledComputeUnits, - Fam15GetDualcoreComputeUnits, - 0x00000001, - 0x00000200, - 18, - TRUE, - TRUE, - AMD_FAMILY_15, - (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap, - 0, - (IGNORE_LINK *)&Fam15IgnoreLinkList, - MakeKey, - NULL -}; - -/** - * Initial construction data for Family 15h North Bridge, for non-coherent only builds. - */ -CONST NORTHBRIDGE ROMDATA HtFam15NbNonCoherentOnly = -{ - 8, - (PF_WRITE_ROUTING_TABLE)CommonVoid, - (PF_WRITE_NODEID)CommonVoid, - (PF_READ_DEFAULT_LINK)CommonReturnZero8, - (PF_ENABLE_ROUTING_TABLES)CommonVoid, - (PF_DISABLE_ROUTING_TABLES)CommonVoid, - (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse, - (PF_READ_TOKEN)CommonReturnZero8, - (PF_WRITE_TOKEN)CommonVoid, - (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid, - (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse, - (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse, - (PF_STOP_LINK)CommonVoid, - (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, - (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse, - ReadSouthbridgeLink, - VerifyLinkIsNonCoherent, - Fam15SetConfigAddrMap, - Fam15NorthBridgeFreqMask, - GatherLinkFeatures, - SetLinkRegang, - SetLinkFrequency, - SetLinkUnitIdClumping, - (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid, - (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid, - (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid, - Fam15BufferOptimizations, - Fam15GetNumCoresOnNode, - SetTotalNodesAndCores, - GetNodeCount, - LimitNodes, - ReadTrueLinkFailStatus, - Fam15GetNextLink, - GetPackageLink, - MakeLinkBase, - Fam15GetModuleInfo, - Fam15PostMailbox, - Fam15RetrieveMailbox, - Fam15GetSocket, - Fam15GetEnabledComputeUnits, - Fam15GetDualcoreComputeUnits, - 0x00000001, - 0x00000200, - 18, - TRUE, - TRUE, - ((AMD_FAMILY_15) & ~(AMD_FAMILY_TN | AMD_FAMILY_KM)), - (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap, - 0, - NULL, - MakeKey, - NULL -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.c deleted file mode 100644 index a383492cda..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.c +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge non-coherent support for Family 15h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbNonCoherentFam15.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable config access to a non-coherent chain for the given bus range. - * - * @HtNbMethod{::F_SET_CONFIG_ADDR_MAP} - * - * @param[in] ConfigMapIndex the map entry to set - * @param[in] SecBus The secondary bus number to use - * @param[in] SubBus The subordinate bus number to use - * @param[in] TargetNode The Node that shall be the recipient of the traffic - * @param[in] TargetLink The Link that shall be the recipient of the traffic - * @param[in] State our global state - * @param[in] Nb this northbridge - */ -VOID -Fam15SetConfigAddrMap ( - IN UINT8 ConfigMapIndex, - IN UINT8 SecBus, - IN UINT8 SubBus, - IN UINT8 TargetNode, - IN UINT8 TargetLink, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ) -{ - UINT8 CurNode; - PCI_ADDR Reg; - UINT32 Temp; - - Reg = Nb->MakeLinkBase (TargetNode, TargetLink, Nb); - - ASSERT (SecBus <= SubBus); - ASSERT (TargetNode <= State->NodesDiscovered); - ASSERT (TargetLink < Nb->MaxLinks); - Temp = SecBus; - Reg.Address.Register += HTHOST_ISOC_REG; - LibAmdPciWriteBits (Reg, 15, 8, &Temp, Nb->ConfigHandle); - - Temp = ((UINT32)SubBus << 24) + ((UINT32)SecBus << 16) + ((UINT32)TargetLink << 8) + - ((UINT32)TargetNode << 4) + (UINT32)3; - for (CurNode = 0; CurNode < (State->NodesDiscovered + 1); CurNode++) { - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (CurNode), - MakePciBusFromNode (CurNode), - MakePciDeviceFromNode (CurNode), - CPU_ADDR_FUNC_01, - REG_ADDR_CONFIG_MAP0_1XE0 + (4 * ConfigMapIndex)); - LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.h deleted file mode 100644 index a98f19be48..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.h +++ /dev/null @@ -1,58 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge non-coherent support for Family 15h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/** - * Enable config access to a non-coherent chain for the given bus range. - * - */ -VOID -Fam15SetConfigAddrMap ( - IN UINT8 ConfigMapIndex, - IN UINT8 SecBus, - IN UINT8 SubBus, - IN UINT8 TargetNode, - IN UINT8 TargetLink, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.c deleted file mode 100644 index 75595c4959..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.c +++ /dev/null @@ -1,148 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Link optimization support specific to family 15h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "htNbOptimizationFam15.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Northbridge specific Frequency limit. - * - * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK} - * - * Return a mask that eliminates HT frequencies that cannot be used due to a slow - * northbridge frequency. - * - * @param[in] Node Result could (later) be for a specific Node - * @param[in] Interface Access to non-HT support functions. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] Nb this northbridge - * - * @return Frequency mask - */ -UINT32 -Fam15NorthBridgeFreqMask ( - IN UINT8 Node, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 NbCoreFreq; - UINT32 Supported; - - ASSERT (Node < MAX_NODES); - ASSERT (Interface != NULL); - // The interface to power management will return a system based result. - // So we only need to call it once, not on every link. Save the answer, - // and check to see if we can use a saved answer on subsequent calls. - // - if (Nb->CoreFrequency == 0) { - NbCoreFreq = Interface->GetMinNbCoreFreq (PlatformConfig, Nb->ConfigHandle); - NbCoreFreq = (NbCoreFreq / 100); - ASSERT (NbCoreFreq != 0); - Nb->CoreFrequency = NbCoreFreq; - } else { - NbCoreFreq = Nb->CoreFrequency; - } - - // The Ht frequency can go twice the Nb COF, as long as it's HT3. - // (side note: we are not speculatively upgrading HT1 at 6 .. 10 to HT3, - // to avoid complicated recovery if the final speed is HT1.) - if (NbCoreFreq > 10) { - NbCoreFreq = NbCoreFreq * 2; - } - // - // NbCoreFreq is minimum northbridge speed in hundreds of MHz. - // HT can not go faster than the minimum speed of the northbridge. - // - if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) { - // Convert frequency to bit and all less significant bits, - // by setting next power of 2 and subtracting 1. - // - Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1; - } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) { - // Convert frequency to bit and all less significant bits, - // by setting next power of 2 and subtracting 1, noting that - // next power of two is two greater than non-extended frequencies - // (because of the register break). - // - Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1; - } else if (NbCoreFreq > 32) { - Supported = HT_FREQUENCY_LIMIT_MAX; - } else if (NbCoreFreq == 4) { - // unlikely cases, but include as a defensive measure, also avoid trick above - Supported = HT_FREQUENCY_LIMIT_400M; - } else if (NbCoreFreq == 2) { - Supported = HT_FREQUENCY_LIMIT_200M; - } else { - ASSERT (FALSE); - Supported = HT_FREQUENCY_LIMIT_200M; - } - - return (Supported); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.h deleted file mode 100644 index 1448bea5fe..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbOptimizationFam15.h +++ /dev/null @@ -1,63 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Link optimization support specific to family 15h processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -/** - * Northbridge specific Frequency limit. - * - */ -UINT32 -Fam15NorthBridgeFreqMask ( - IN UINT8 Node, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ); - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c deleted file mode 100644 index 251fc9b60f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c +++ /dev/null @@ -1,373 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * System Tuning Family 15h specific routines - * - * Support for Traffic Distribution and buffer tunings which - * can not be done in a register table. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 50215 $ @e \$Date: 2011-04-05 20:50:13 -0600 (Tue, 05 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbSystemFam15.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/** - * Register Fields for an individual link pair. - */ -typedef struct { - UINT32 Enable:1; ///< Enable distribution on this pair. - UINT32 Asymmetric:1; ///< Links are different widths. - UINT32 MasterSelect:3; ///< The master link. - UINT32 AlternateSelect:3; ///< The alternate link. -} PAIR_SELECT_FIELDS; - -/** - * Register access union for ::PAIR_SELECT_FIELDS. - */ -typedef union { - UINT32 Value; ///< access as a 32 bit value or register. - PAIR_SELECT_FIELDS Fields; ///< access individual fields. -} PAIR_SELECT; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Set the traffic distribution register for the Links provided. - * - * @HtNbMethod{::F_WRITE_TRAFFIC_DISTRIBUTION} - * - * @param[in] Links01 coherent Links from Node 0 to 1 - * @param[in] Links10 coherent Links from Node 1 to 0 - * @param[in] Nb this northbridge - */ -VOID -Fam15WriteTrafficDistribution ( - IN UINT32 Links01, - IN UINT32 Links10, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR TrafficDistReg; - - TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0), - MakePciBusFromNode (0), - MakePciDeviceFromNode (0), - CPU_HTNB_FUNC_00, - REG_HT_TRAFFIC_DIST_0X164); - - // Node 0 - // DstLnk - LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links01, Nb->ConfigHandle); - // DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 - Temp = 0x0107; - LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle); - - TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (1), - MakePciBusFromNode (1), - MakePciDeviceFromNode (1), - CPU_HTNB_FUNC_00, - REG_HT_TRAFFIC_DIST_0X164); - - // Node 1 - // DstLnk - LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links10, Nb->ConfigHandle); - // DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 - Temp = 0x0007; - LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set the victim distribution register for the Links provided. - * - * @HtNbMethod{::F_WRITE_VICTIM_DISTRIBUTION} - * - * @param[in] NodeA Source Node from Node A To Node B and DstNode from Node A To Node B - * @param[in] NodeB Source Node from Node B To Node A and DstNode from Node A To Node B - * @param[in] LinksAB Victimed Link from Node A To Node B - * @param[in] LinksBA Victimed Link from Node B To Node A - * @param[in] Nb this northbridge - */ -VOID -Fam15WriteVictimDistribution ( - IN UINT8 NodeA, - IN UINT8 NodeB, - IN UINT32 LinksAB, - IN UINT32 LinksBA, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR TrafficDistReg; - - TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (NodeA), - MakePciBusFromNode (NodeA), - MakePciDeviceFromNode (NodeA), - CPU_HTNB_FUNC_00, - REG_HT_TRAFFIC_DIST_0X164); - - // Node A - // DstLnk - LibAmdPciWriteBits (TrafficDistReg, 23, 16, &LinksAB, Nb->ConfigHandle); - // DstNode = Node B, cHTPrbDistEn = 0, cHTRspDistEn = 1, cHTReqDistEn = 1, cHTVicDistMode = 1 - Temp = NodeB; - Temp = (Temp << 8) | 0x0B; - LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle); - - TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (NodeB), - MakePciBusFromNode (NodeB), - MakePciDeviceFromNode (NodeB), - CPU_HTNB_FUNC_00, - REG_HT_TRAFFIC_DIST_0X164); - - // Node B - // DstLnk - LibAmdPciWriteBits (TrafficDistReg, 23, 16, &LinksBA, Nb->ConfigHandle); - // DstNode = Node A, cHTPrbDistEn = 0, cHTRspDistEn = 1, cHTReqDistEn = 1, cHTVicDistMode = 1 - Temp = NodeA; - Temp = (Temp << 8) | 0x0B; - LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write a link pair to the link pair distribution and fixups. - * - * @HtNbMethod{::F_WRITE_LINK_PAIR_DISTRIBUTION} - * - * Set the links as a pair using the link pair index provided. Set asymmetric attribute as - * provided. If the Master Link is not currently used as the route, fixup the routes for all - * nodes which specify the alternate link. - * - * @param[in] Node Set the pair on this node - * @param[in] ConnectedNode The Node to which this link pair directly connects. - * @param[in] Pair Using this pair set in the register - * @param[in] Asymmetric True if different widths - * @param[in] MasterLink Set this as the master link and in the route - * @param[in] AlternateLink Set this as the alternate link - * @param[in] Nb this northbridge - * - */ -VOID -Fam15WriteLinkPairDistribution ( - IN UINT8 Node, - IN UINT8 ConnectedNode, - IN UINT8 Pair, - IN BOOLEAN Asymmetric, - IN UINT8 MasterLink, - IN UINT8 AlternateLink, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 CurrentRoute; - UINT32 MasterRoute; - UINT32 AlternateRoute; - PAIR_SELECT Selection; - UINT32 RouteIndex; - - ASSERT ((Node < MAX_NODES) && (ConnectedNode < MAX_NODES)); - ASSERT (Pair < MAX_LINK_PAIRS); - ASSERT (MasterLink < Nb->MaxLinks); - ASSERT (AlternateLink < Nb->MaxLinks); - - // Make the master link the route for all routes to or through NodeB, by replacing all occurrences of - // Alternate link with Master link. If routing used the master link, no update is necessary. - MasterRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (MasterLink + 1)); - AlternateRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (AlternateLink + 1)); - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_ROUTE0_0X40); - for (RouteIndex = 0; RouteIndex < MAX_NODES; RouteIndex++) { - Reg.Address.Register = REG_ROUTE0_0X40 + (RouteIndex * 4); - LibAmdPciReadBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle); - if ((CurrentRoute & AlternateRoute) != 0) { - // Since Master and Alternate are redundant, the route must use one or the other but not both. - ASSERT ((CurrentRoute & MasterRoute) == 0); - // Set the master route for Request, Response or Broadcast only if the alternate was used for that case. - // Example, use of a link as a broadcast link is typically not the same route register as its use for Request, Response. - CurrentRoute = ((CurrentRoute & ~AlternateRoute) | - ((((CurrentRoute & AlternateRoute) >> (AlternateLink + 1)) << (MasterLink + 1)) & MasterRoute)); - LibAmdPciWriteBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle); - } - } - - // Set the Link Pair and Enable it - Selection.Fields.Enable = 1; - Selection.Fields.Asymmetric = Asymmetric; - Selection.Fields.MasterSelect = MasterLink; - Selection.Fields.AlternateSelect = AlternateLink; - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_HT_LINK_PAIR_DIST_0X1E0); - LibAmdPciWriteBits ( - Reg, - ((PAIR_SELECT_OFFSET * (Pair + 1)) - 1), - (PAIR_SELECT_OFFSET * Pair), - &Selection.Value, - Nb->ConfigHandle - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Family 15h specific tunings. - * - * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS} - * - * Buffer tunings are inherently northbridge specific. Check for specific configs - * which require adjustments and apply any standard workarounds to this Node. - * - * @param[in] Node the Node to tune - * @param[in] State global state - * @param[in] Nb this northbridge - */ -VOID -Fam15BufferOptimizations ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR Reg; - UINT8 i; - FINAL_LINK_STATE FinalLinkState; - UINT32 WidthIn; - UINT32 WidthOut; - - ASSERT (Node < MAX_NODES); - - // - // Internal link fixup. - // When powering off internal link 2, a performance optimization may be possible where its buffers - // can be made available to the external paired sublink. If the conditions are met, do the fix up here. - // - for (i = 0; i < (State->TotalLinks * 2); i++) { - if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) { - // Is this a sublink 0 paired with internal link 2? - if (((*State->PortList)[i].Link < 4) && - (Nb->GetPackageLink (Node, ((*State->PortList)[i].Link + 4), Nb) == HT_LIST_MATCH_INTERNAL_LINK_2)) { - FinalLinkState = State->HtInterface->GetIgnoreLink (Node, ((*State->PortList)[i].Link + 4), Nb->DefaultIgnoreLinkList, State); - // Are we ignoring the internal link 2 with Power Off? - if (FinalLinkState == POWERED_OFF) { - // Read the regang bit in hardware. - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link)); - LibAmdPciReadBits (Reg, 0, 0, &Temp, Nb->ConfigHandle); - // If it's already ganged, skip to the width fix up. - if (Temp == 0) { - // Clear EndOfChain / XmitOff of internal sublink - Reg = Nb->MakeLinkBase (Node, ((*State->PortList)[i].Link + 4), Nb); - Reg.Address.Register += HTHOST_LINK_CONTROL_REG; - Temp = 0; - State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State); - - // Gang the link - Nb->SetLinkRegang (Node, (*State->PortList)[i].Link, Nb); - } - - // Set InLnSt = PHY_OFF in register table. - // Set sublink 0 widths to 8 bits - if ((*State->PortList)[i].SelWidthOut > 8) { - (*State->PortList)[i].SelWidthOut = 8; - } - if ((*State->PortList)[i].SelWidthIn > 8) { - (*State->PortList)[i].SelWidthIn = 8; - } - WidthOut = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthOut); - WidthIn = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthIn); - Temp = (WidthIn & 7) | ((WidthOut & 7) << 4); - Reg = Nb->MakeLinkBase (Node, (*State->PortList)[i].Link, Nb); - Reg.Address.Register += HTHOST_LINK_CONTROL_REG; - State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State); - } - } - } - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.h deleted file mode 100644 index b84519f337..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.h +++ /dev/null @@ -1,93 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * System Tuning Family 15h specific routines - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 50215 $ @e \$Date: 2011-04-05 20:50:13 -0600 (Tue, 05 Apr 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/** - * Set the traffic distribution register for the Links provided. - * - */ -VOID -Fam15WriteTrafficDistribution ( - IN UINT32 Links01, - IN UINT32 Links10, - IN NORTHBRIDGE *Nb - ); - -/** - * Write a link pair to the link pair distribution and fixups. - * - */ -VOID -Fam15WriteLinkPairDistribution ( - IN UINT8 Node, - IN UINT8 ConnectedNode, - IN UINT8 Pair, - IN BOOLEAN Asymmetric, - IN UINT8 MasterLink, - IN UINT8 AlternateLink, - IN NORTHBRIDGE *Nb - ); - -/** - * Family 15h specific tunings. - * - */ -VOID -Fam15WriteVictimDistribution ( - IN UINT8 NodeA, - IN UINT8 NodeB, - IN UINT32 LinksAB, - IN UINT32 LinksBA, - IN NORTHBRIDGE *Nb - ); - -/** - * Family 15h specific tunings. - * - */ -VOID -Fam15BufferOptimizations ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.c deleted file mode 100644 index ec47b36309..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.c +++ /dev/null @@ -1,453 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge utility routines. - * - * These routines are needed for support of more than one feature area. - * Collect them in this file so build options don't remove them. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbUtilitiesFam15.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Return the number of cores (1 based count) on Node. - * - * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE} - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - * - * @return the number of cores - */ -UINT8 -Fam15GetNumCoresOnNode ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Result; - UINT32 Leveling; - UINT32 Cores; - UINT8 i; - PCI_ADDR Reg; - - ASSERT ((Node < MAX_NODES)); - // Read CmpCap - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_05, - REG_NB_CAPABILITY_2_5X84); - - LibAmdPciReadBits (Reg, 7, 0, &Result, Nb->ConfigHandle); - - // Support Downcoring - Cores = Result; - Cores++; - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_DOWNCORE_3X190); - LibAmdPciReadBits (Reg, 31, 0, &Leveling, Nb->ConfigHandle); - for (i = 0; i < Cores; i++) { - if ((Leveling & ((UINT32) 1 << i)) != 0) { - Result--; - } - } - return (UINT8) (Result + 1); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the next link for iterating over the links on a node in the correct order. - * - * @HtNbMethod{::F_GET_NEXT_LINK} - * - * Use the Internal Link field in the northbridge to prioritize internal links in the - * order. - * - * @param[in] Node The node on which to iterate links. - * @param[in,out] Link IN: the current iteration context, OUT: the next link. - * @param[in] Nb This Northbridge, access to config pointer. - * - * @retval LinkIteratorExternal The current Link is an external link. - * @retval LinkIteratorInternal The current Link is an internal link. - * @retval LinkIteratorEnd There is no next link (Link is back to BEGIN). - * - */ -LINK_ITERATOR_STATUS -Fam15GetNextLink ( - IN UINT8 Node, - IN OUT UINT8 *Link, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 InternalLinks; - UINT32 ExternalLinks; - UINT32 HigherLinks; - BOOLEAN IsInternalLink; - LINK_ITERATOR_STATUS Status; - - ASSERT ((Node < MAX_NODES)); - ASSERT ((*Link < Nb->MaxLinks) || (*Link == LINK_ITERATOR_BEGIN)); - InternalLinks = 0; - ExternalLinks = 0; - - // Read IntLnkRoute from the Link Initialization Status register. - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_HT_LINK_INITIALIZATION_0X1A0); - - LibAmdPciReadBits (Reg, 23, 16, &InternalLinks, Nb->ConfigHandle); - // The external links are all possible links which are not Internal - ExternalLinks = (((1 << Nb->MaxLinks) - 1) ^ InternalLinks); - // Can't have no possible links! - ASSERT ((ExternalLinks != 0) || (InternalLinks != 0)); - - - if (*Link == LINK_ITERATOR_BEGIN) { - // If the request is for the first link (BEGIN), get it - if (InternalLinks != 0) { - *Link = LibAmdBitScanForward (InternalLinks); - Status = LinkIteratorInternal; - } else { - *Link = LibAmdBitScanForward (ExternalLinks); - Status = LinkIteratorExternal; - } - } else { - // If the iterator is not at the beginning, search for the next Link starting from the - // current link. - HigherLinks = InternalLinks & ~((1 << (*Link + 1)) - 1); - IsInternalLink = (BOOLEAN) ((InternalLinks & (1 << *Link)) != 0); - if (IsInternalLink && (HigherLinks != 0)) { - // We are still on internal links and there are more to do. - *Link = LibAmdBitScanForward (HigherLinks); - Status = LinkIteratorInternal; - } else { - if (IsInternalLink) { - // We are transitioning now from internal to external, so get the first external link - HigherLinks = ExternalLinks; - } else { - // We are already iterating over external links, so get the next one - HigherLinks = ExternalLinks & ~((1 << (*Link + 1)) - 1); - } - if (HigherLinks != 0) { - *Link = LibAmdBitScanForward (HigherLinks); - Status = LinkIteratorExternal; - } else { - // The end of all links - *Link = LINK_ITERATOR_BEGIN; - Status = LinkIteratorEnd; - } - } - } - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Info about Module Type of this northbridge - * - * @HtNbMethod{::F_GET_MODULE_INFO} - * - * Provide the Processor module type, single or multi, and the node's module id. - * - * @param[in] Node the Node - * @param[out] ModuleType 0 for Single, 1 for Multi - * @param[out] Module The module number of this node (0 if Single) - * @param[in] Nb this northbridge - * - */ -VOID -Fam15GetModuleInfo ( - IN UINT8 Node, - OUT UINT8 *ModuleType, - OUT UINT8 *Module, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 MultNodeCpu; - UINT32 IntNodeNum; - - ASSERT (Node < MAX_NODES); - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_CAPABILITY_3XE8); - LibAmdPciReadBits (Reg, 29, 29, &MultNodeCpu, Nb->ConfigHandle); - LibAmdPciReadBits (Reg, 31, 30, &IntNodeNum, Nb->ConfigHandle); - - *ModuleType = (UINT8) MultNodeCpu; - *Module = (UINT8) IntNodeNum; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. - * - * @HtNbMethod{::F_GET_SOCKET} - * - * The hardware socket naming method is not available for Family 15h in some packages. - * - * @param[in] Node The node for which we want the socket id. - * @param[in] TempNode The temporary node id route where the node can be accessed. - * @param[in] Nb Our Northbridge. - * - * @return The Socket Id - */ -UINT8 -Fam15GetSocket ( - IN UINT8 Node, - IN UINT8 TempNode, - IN NORTHBRIDGE *Nb - ) -{ - ASSERT ((Node < MAX_NODES)); - ASSERT (TempNode < MAX_NODES); - ASSERT (Nb != NULL); - return (Node); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. - * - * @HtNbMethod{::F_GET_SOCKET} - * - * The Socket Id is strapped to the Sbi Control Register, F3X1E4[6:4]SbiAddr. - * - * @param[in] Node The node for which we want the socket id. - * @param[in] TempNode The temporary node id route where the node can be accessed. - * @param[in] Nb Our Northbridge. - * - * @return The Socket Id - */ -UINT8 -Fam15StrappedGetSocket ( - IN UINT8 Node, - IN UINT8 TempNode, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Socket; - PCI_ADDR Reg; - - ASSERT ((TempNode < MAX_NODES)); - ASSERT ((Node < MAX_NODES)); - // Read SbiAddr - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (TempNode), - MakePciBusFromNode (TempNode), - MakePciDeviceFromNode (TempNode), - CPU_NB_FUNC_03, - REG_NB_SBI_CONTROL_3X1E4); - LibAmdPciReadBits (Reg, 6, 4, &Socket, Nb->ConfigHandle); - return ((UINT8) Socket); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the enable compute unit status for this node. - * - * @HtNbMethod{::F_GET_ENABLED_COMPUTE_UNITS} - * - * @param[in] Node The node for which we want the enabled compute units. - * @param[in] Nb Our Northbridge. - * - * @return The Enabled Compute Unit value - */ -UINT8 -Fam15GetEnabledComputeUnits ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Enabled; - PCI_ADDR Reg; - - ASSERT ((Node < MAX_NODES)); - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_05, - REG_NB_COMPUTE_UNIT_5X80); - LibAmdPciReadBits (Reg, 3, 0, &Enabled, Nb->ConfigHandle); - return ((UINT8) Enabled); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the dual core compute unit status for this node. - * - * @HtNbMethod{::PF_GET_DUALCORE_COMPUTE_UNITS} - * - * @param[in] Node The node for which we want the dual core status - * @param[in] Nb Our Northbridge. - * - * @return The dual core compute unit status. - */ -UINT8 -Fam15GetDualcoreComputeUnits ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Dual; - PCI_ADDR Reg; - - ASSERT ((Node < MAX_NODES)); - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_05, - REG_NB_COMPUTE_UNIT_5X80); - LibAmdPciReadBits (Reg, 19, 16, &Dual, Nb->ConfigHandle); - return ((UINT8) Dual); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Post info to AP cores via a mailbox. - * - * @HtNbMethod{::F_POST_MAILBOX} - * - * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id, - * and module info. - * - * @param[in] Node the Node - * @param[in] ApMailboxes The info to post - * @param[in] Nb this northbridge - * - */ -VOID -Fam15PostMailbox ( - IN UINT8 Node, - IN AP_MAILBOXES ApMailboxes, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - - ASSERT (Node < MAX_NODES); - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_MCA_LINK_THRESHOLD_3X168); - LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailInfo.Info, Nb->ConfigHandle); - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_MCA_L3_THRESHOLD_3X170); - LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Retrieve info from a node's mailbox. - * - * @HtNbMethod{::F_RETRIEVE_MAILBOX} - * - * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id, - * and module info. - * - * @param[in] Node the Node - * @param[in] Nb this northbridge - * - * @return The ap mailbox info - * - */ -AP_MAIL_INFO -Fam15RetrieveMailbox ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - AP_MAIL_INFO ApMailInfo; - - ASSERT (Node < MAX_NODES); - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_MCA_LINK_THRESHOLD_3X168); - LibAmdPciReadBits (Reg, 11, 0, &ApMailInfo.Info, Nb->ConfigHandle); - return ApMailInfo; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.h deleted file mode 100644 index 73ea813b6b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.h +++ /dev/null @@ -1,137 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge utility routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/** - * Return the number of cores (1 based count) on Node. - * - */ -UINT8 -Fam15GetNumCoresOnNode ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/** - * Get the next link for iterating over the links on a node in the correct order. - * - */ -LINK_ITERATOR_STATUS -Fam15GetNextLink ( - IN UINT8 Node, - IN OUT UINT8 *Link, - IN NORTHBRIDGE *Nb - ); - -/** - * Get Info about Module Type of this northbridge - * - */ -VOID -Fam15GetModuleInfo ( - IN UINT8 Node, - OUT UINT8 *ModuleType, - OUT UINT8 *Module, - IN NORTHBRIDGE *Nb - ); - -/** - * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. - * - */ -UINT8 -Fam15GetSocket ( - IN UINT8 Node, - IN UINT8 TempNode, - IN NORTHBRIDGE *Nb - ); - -/** - * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. - * - */ -UINT8 -Fam15StrappedGetSocket ( - IN UINT8 Node, - IN UINT8 TempNode, - IN NORTHBRIDGE *Nb - ); - -/** - * Get the enable compute unit status for this node. - */ -UINT8 -Fam15GetEnabledComputeUnits ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/** - * Get the dual core compute unit status for this node. - */ -UINT8 -Fam15GetDualcoreComputeUnits ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/** - * Post info to AP cores via a mailbox. - * - */ -VOID -Fam15PostMailbox ( - IN UINT8 Node, - IN AP_MAILBOXES ApMailboxes, - IN NORTHBRIDGE *Nb - ); - -/** - * Retrieve info from a node's mailbox. - * - */ -AP_MAIL_INFO -Fam15RetrieveMailbox ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/Makefile.inc deleted file mode 100644 index 8d4cac712b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -libagesa-y += htFeatDynamicDiscovery.c -libagesa-y += htFeatGanging.c -libagesa-y += htFeatNoncoherent.c -libagesa-y += htFeatOptimization.c -libagesa-y += htFeatRouting.c -libagesa-y += htFeatSets.c -libagesa-y += htFeatSublinks.c -libagesa-y += htFeatTrafficDistribution.c -libagesa-y += htIds.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.c deleted file mode 100644 index c42697ac17..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.c +++ /dev/null @@ -1,783 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Coherent Discovery Routines. - * - * Contains routines for discovery, along with Temporary routing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNotify.h" -#include "htNb.h" -#include "htFeatDynamicDiscovery.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define LOGICAL_PROCESSOR_NONE 0xFF - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/** - * Status result from exploring for a new node on a link. - */ -typedef enum { - ExploreNodeStatusNew, ///< A new node was discovered - ExploreNodeStatusGood, ///< A new link to an already known node was discovered - ExploreNodeStatusStop, ///< Discovery must halt now. - ExploreNodeStatusIgnore, ///< A new node was ignored on purpose. - ExploreNodeStatusMax ///< Use for bounds check and limit only -} EXPLORE_NODE_STATUS; - -/** - * Save all the information needed about a node at its discovery. - * - * When we can access the node at a known temporary route, read everything needed - * to do node to socket mapping, post to ap mailbox at later times. - */ -typedef struct { - UINT8 LogicalProcessor; ///< Independent of Node,Socket group nodes into logical - ///< processors based on discovery. - UINT8 CurrentNode; ///< The node from which discovery occurred. - UINT8 CurrentLink; ///< The link on that node which we explored. - UINT8 PackageLink; ///< The package level link corresponding to CurrentLink. - UINT8 CurrentModuleType; ///< The current node's module type, Single or Multiple. - UINT8 CurrentModule; ///< This current node's module id. - UINT8 HardwareSocket; ///< Save the hardware socket strap (for hardware socket method). - UINT8 NewModuleType; ///< The new node's module type, Single or Multiple. - UINT8 NewModule; ///< The new node's module id. -} NEW_NODE_SAVED_INFO_ITEM; - -/** - * A "no info" initializer for saved new node info. - */ -STATIC CONST NEW_NODE_SAVED_INFO_ITEM ROMDATA NoInfoSavedYet = -{ - LOGICAL_PROCESSOR_NONE, 0, 0, 0, 0, 0, 0, 0 -}; - -/** - * A list of all the new node info, indexed by each new node's nodeid. - */ -typedef NEW_NODE_SAVED_INFO_ITEM (*NEW_NODE_SAVED_INFO_LIST) [MAX_NODES]; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** GENERIC HYPERTRANSPORT DISCOVERY CODE *** - ***************************************************************************/ - -/*-----------------------------------------------------------------------------------*/ -/** - * Ensure a request / response route from target Node to bsp. - * - * Since target Node is always a predecessor of actual target Node, each Node gets a - * route to actual target on the Link that goes to target. The routing produced by - * this routine is adequate for config access during discovery, but NOT for coherency. - * - * @param[in] TargetNode the path to actual target goes through target - * @param[in] ActualTarget the ultimate target being routed to - * @param[in] State our global state, port config info - * - */ -VOID -STATIC -routeFromBSP ( - IN UINT8 TargetNode, - IN UINT8 ActualTarget, - IN STATE_DATA *State - ) -{ - UINT8 PredecessorNode; - UINT8 PredecessorLink; - UINT8 CurrentPair; - - if (TargetNode == 0) { - return; // BSP has no predecessor, stop - } - - // Search for the Link that connects TargetNode to its predecessor - CurrentPair = 0; - while ((*State->PortList)[CurrentPair*2 + 1].NodeID != TargetNode) { - CurrentPair++; - ASSERT (CurrentPair < State->TotalLinks); - } - - PredecessorNode = (*State->PortList)[ (CurrentPair * 2)].NodeID; - PredecessorLink = (*State->PortList)[ (CurrentPair * 2)].Link; - - // Recursively call self to ensure the route from the BSP to the Predecessor - // Node is established - routeFromBSP (PredecessorNode, ActualTarget, State); - - State->Nb->WriteRoutingTable (PredecessorNode, ActualTarget, PredecessorLink, State->Nb); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Test Compatibility of a new node, and handle failure. - * - * Make the compatibility test call for the northbridge. - * If the new node is incompatible, force 1P. Notify the event. - * Additionally, invoke the northbridge stop link method, to - * implement isolation of the BSP from any incompatible node. - * - * @param[in] CurrentNode The node we are exploring from - * @param[in] CurrentLink The Link on that node to explore. - * @param[in] State Access to Northbridge interface. - * - * @retval TRUE Check is Ok - * @retval FALSE Check failed and is handled - */ -BOOLEAN -STATIC -CheckCompatible ( - IN UINT8 CurrentNode, - IN UINT8 CurrentLink, - IN STATE_DATA *State - ) -{ - UINT8 NodeToKill; - BOOLEAN Result; - - Result = TRUE; - - // Check the northbridge of the Node we just found, to make sure it is compatible - // before doing anything else to it. - // - if (State->Nb->IsIllegalTypeMix ((CurrentNode + 1), State->Nb)) { - IDS_ERROR_TRAP; - - // Notify BIOS of event - NotifyFatalCohProcessorTypeMix ( - CurrentNode, - CurrentLink, - State->NodesDiscovered, - State - ); - - // If Node is not compatible, force boot to 1P - // If they are not compatible stop cHT init and: - // 1. Disable all cHT Links on the BSP - // 2. Configure the BSP routing tables as a UP. - // 3. Notify main BIOS. - // - State->NodesDiscovered = 0; - State->TotalLinks = 0; - // Abandon our coherent Link data structure. At this point there may - // be coherent Links on the BSP that are not yet in the portList, and - // we have to turn them off anyway. So depend on the hardware to tell us. - // - for (CurrentLink = 0; CurrentLink < State->Nb->MaxLinks; CurrentLink++) { - // Stop all Links which are connected, coherent, and ready - if (State->Nb->VerifyLinkIsCoherent (0, CurrentLink, State->Nb)) { - State->Nb->StopLink (0, CurrentLink, State, State->Nb); - } - } - - for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) { - State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb); - } - - State->HtInterface->CleanMapsAfterError (State); - - // End Coherent Discovery - Result = FALSE; - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check the system MP capability with a new node and handle any failure. - * - * Invoke the northbridge MP capability check. If it fails, notify the event and force - * 1P. Should not need to stop links on the BSP. - * - * @param[in] CurrentNode The node we are exploring from - * @param[in] CurrentLink The Link on that node to explore. - * @param[in] State Access to Northbridge interface. - * - * @retval TRUE Check is Ok - * @retval FALSE Check Failed and is handled - */ -BOOLEAN -STATIC -CheckCapable ( - IN UINT8 CurrentNode, - IN UINT8 CurrentLink, - IN STATE_DATA *State - ) -{ - UINT8 NodeToKill; - BOOLEAN Result; - - Result = TRUE; - - // Check the capability of northbridges against the currently known configuration - if (State->Nb->IsExceededCapable ((CurrentNode + 1), State, State->Nb)) { - IDS_ERROR_TRAP; - // Notify BIOS of event - NotifyFatalCohMpCapMismatch ( - CurrentNode, - CurrentLink, - State->SysMpCap, - State->NodesDiscovered, - State - ); - - State->NodesDiscovered = 0; - State->TotalLinks = 0; - - for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) { - State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb); - } - - State->HtInterface->CleanMapsAfterError (State); - - // End Coherent Discovery - Result = FALSE; - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Make all the tests needed to determine if a link should be added to the system data structure. - * - * The link should be added to the system data structure if it is: - * - not being Ignored on this boot - * - not having a hard failure - * - coherent and connected - * - not already in the system data structure - * - not subject to some special handling case. - * . - * - * @param[in] CurrentNode The node we are exploring from - * @param[in] CurrentLink The Link on that node to explore. - * @param[in] State Access to Northbridge interface. - * - * @retval FALSE This link should not be added. - * @retval TRUE This link should explored and added to the system. - */ -BOOLEAN -STATIC -IsLinkToAdd ( - IN UINT8 CurrentNode, - IN UINT8 CurrentLink, - IN STATE_DATA *State - ) -{ - BOOLEAN Linkfound; - UINTN Port; - FINAL_LINK_STATE FinalLinkState; - BOOLEAN Result; - - Result = FALSE; - - FinalLinkState = State->HtInterface->GetIgnoreLink (CurrentNode, CurrentLink, State->Nb->DefaultIgnoreLinkList, State); - if ((FinalLinkState != MATCHED) && (FinalLinkState != POWERED_OFF)) { - if (!State->Nb->ReadTrueLinkFailStatus (CurrentNode, CurrentLink, State, State->Nb)) { - // Make sure that the Link is connected, coherent, and ready - if (State->Nb->VerifyLinkIsCoherent (CurrentNode, CurrentLink, State->Nb)) { - // Test to see if the CurrentLink has already been explored - Linkfound = FALSE; - for (Port = 0; Port < State->TotalLinks; Port++) { - if ((((*State->PortList)[ (Port * 2 + 1)].NodeID == CurrentNode) && - ((*State->PortList)[ (Port * 2 + 1)].Link == CurrentLink)) || - (((*State->PortList)[ (Port * 2)].NodeID == CurrentNode) && - ((*State->PortList)[ (Port * 2)].Link == CurrentLink))) { - Linkfound = TRUE; - break; - } - } - if (!Linkfound) { - if (!State->Nb->HandleSpecialLinkCase (CurrentNode, CurrentLink, State, State->Nb)) { - Result = TRUE; - } - } - } - } - } else { - if (FinalLinkState == POWERED_OFF) { - State->Nb->StopLink (CurrentNode, CurrentLink, State, State->Nb); - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Explore for a new node over a link, handling whatever is found. - * - * Open a temporary route over a link on the current node. - * Make checks for compatibility and capability in the proper sequence. - * If the node found is new, set a token to it, so it will be recognized in the - * future, and notify an event for finding a new node. - * If the node is already found (token is set), just return status. - * - * @param[in] CurrentNode The node we are exploring from - * @param[in] CurrentLink The Link on that node to explore. - * @param[in] LogicalProcessor The processor to update in the maps. - * @param[in,out] NewNodeSavedInfo The saved info for nodes in that processor. - * @param[in] State Access to Northbridge interface. - * - * @retval ExploreNodeStatusNew A new node was found - * @retval ExploreNodeStatusGood This is a good link to an already known node - * @retval ExploreNodeStatusStop Stop Coherent Discovery - */ -EXPLORE_NODE_STATUS -STATIC -ExploreNode ( - IN UINT8 CurrentNode, - IN UINT8 CurrentLink, - IN UINT8 LogicalProcessor, - IN OUT NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo, - IN STATE_DATA *State - ) -{ - UINT8 Token; - EXPLORE_NODE_STATUS Status; - - // Modify CurrentNode's routing table to use CurrentLink to send - // traffic to CurrentNode + 1 - // - State->Nb->WriteRoutingTable (CurrentNode, (CurrentNode + 1), CurrentLink, State->Nb); - if (!State->Nb->HandleSpecialNodeCase ((CurrentNode + 1), CurrentLink, State, State->Nb)) { - if (CheckCompatible (CurrentNode, CurrentLink, State)) { - // Read Token from Current + 1 - Token = State->Nb->ReadToken ((CurrentNode + 1), State->Nb); - ASSERT (Token <= State->NodesDiscovered); - if (Token == 0) { - State->NodesDiscovered++; - ASSERT (State->NodesDiscovered < MAX_NODES); - if (CheckCapable (CurrentNode, CurrentLink, State)) { - Token = State->NodesDiscovered; - State->Nb->WriteToken ((CurrentNode + 1), Token, State->Nb); - // Fill in Saved New Node info for the discovered node. - // We do this so we don't have to keep a temporary route open to it. - // So we save everything that might be needed to set the socket and node - // maps for either the software or hardware method. - // - (*NewNodeSavedInfo)[Token].LogicalProcessor = LogicalProcessor; - (*NewNodeSavedInfo)[Token].CurrentNode = CurrentNode; - (*NewNodeSavedInfo)[Token].CurrentLink = CurrentLink; - (*NewNodeSavedInfo)[Token].PackageLink = State->Nb->GetPackageLink (CurrentNode, CurrentLink, State->Nb); - (*NewNodeSavedInfo)[Token].HardwareSocket = State->Nb->GetSocket (Token, (CurrentNode + 1), State->Nb); - State->Nb->GetModuleInfo ( - CurrentNode, - &((*NewNodeSavedInfo)[Token].CurrentModuleType), - &((*NewNodeSavedInfo)[Token].CurrentModule), - State->Nb - ); - State->Nb->GetModuleInfo ( - (CurrentNode + 1), - &((*NewNodeSavedInfo)[Token].NewModuleType), - &((*NewNodeSavedInfo)[Token].NewModule), - State->Nb - ); - - // Notify BIOS with info - NotifyInfoCohNodeDiscovered ( - CurrentNode, - CurrentLink, - Token, - (CurrentNode + 1), - State - ); - Status = ExploreNodeStatusNew; - } else { - // Failed Capable - Status = ExploreNodeStatusStop; - } - } else { - // Not a new node, token already set - Status = ExploreNodeStatusGood; - } - } else { - // Failed Compatible - Status = ExploreNodeStatusStop; - } - } else { - // Ignore this node - Status = ExploreNodeStatusIgnore; - } - - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Process all the saved new node info for the current processor. - * - * When all nodes in the processor have been discovered, we can process all the saved - * info about the nodes. We add each node to the socket and node maps. - * - * @param[in] LogicalProcessor The processor to update in the maps. - * @param[in] NewNodeSavedInfo The saved info for nodes in that processor. - * @param[in] State Our system representation. - */ -VOID -STATIC -ProcessSavedNodeInfo ( - IN UINT8 LogicalProcessor, - IN NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo, - IN STATE_DATA *State - ) -{ - UINT8 NewNode; - UINT8 HardwareSocket; - - // Can't have more processors than nodes, just more (or equal) nodes than processors. - ASSERT (LogicalProcessor <= (State->NodesDiscovered)); - HardwareSocket = 0xFF; - // Find the Hardware Socket value to use (if we are using the hardware socket naming method). - // The new nodes are the ones in this processor, so find the one that is module 0. - for (NewNode = 0; NewNode < (State->NodesDiscovered + 1); NewNode++) { - if (((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) && - ((*NewNodeSavedInfo)[NewNode].NewModule == 0)) { - HardwareSocket = (*NewNodeSavedInfo)[NewNode].HardwareSocket; - break; - } - } - // We must have found a result, however, the hardware socket value doesn't have to be correct - // unless we are using the hardware socket naming method. Northbridge code should return the - // node number for the hardware socket if hardware socket strapping is not supported (i.e. no sbi). - ASSERT (HardwareSocket != 0xFF); - - // Set the node to socket maps for this processor. Node zero is always handled specially, - // so skip it in this loop. - for (NewNode = 1; NewNode < (State->NodesDiscovered + 1); NewNode++) { - if ((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) { - // For the currently discovered logical processor, update node to socket - // map for all the processor's nodes. - State->HtInterface->SetNodeToSocketMap ( - (*NewNodeSavedInfo)[NewNode].CurrentNode, - (*NewNodeSavedInfo)[NewNode].CurrentModule, - (*NewNodeSavedInfo)[NewNode].PackageLink, - NewNode, - HardwareSocket, - (*NewNodeSavedInfo)[NewNode].NewModule, - State); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Create and add a new link to the system data structure. - * - * Add the two port list data structures, source first, initializing - * the two node ids and the link values. The node id of the remote - * node is its token value. Also, update the adjacency matrix and - * node degree table. - * - * @param[in] CurrentNode The node we are exploring from - * @param[in] CurrentLink The Link on that node to explore. - * @param[in] TempRoute The temporary node route that goes over that link. - * @param[in] State Access to Northbridge interface. - * - */ -VOID -STATIC -AddLinkToSystem ( - IN UINT8 CurrentNode, - IN UINT8 CurrentLink, - IN UINT8 TempRoute, - IN STATE_DATA *State - ) -{ - UINT8 Token; - - ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS); - - Token = State->Nb->ReadToken (TempRoute, State->Nb); - - (*State->PortList)[State->TotalLinks * 2].Type = PORTLIST_TYPE_CPU; - (*State->PortList)[State->TotalLinks * 2].Link = CurrentLink; - (*State->PortList)[State->TotalLinks * 2].NodeID = CurrentNode; - - (*State->PortList)[State->TotalLinks * 2 + 1].Type = PORTLIST_TYPE_CPU; - (*State->PortList)[State->TotalLinks * 2 + 1].Link = State->Nb->ReadDefaultLink (TempRoute, State->Nb); - (*State->PortList)[State->TotalLinks * 2 + 1].NodeID = Token; - - State->TotalLinks++; - - if ( !State->Fabric->SysMatrix[CurrentNode][Token] ) { - State->Fabric->SysDegree[CurrentNode]++; - State->Fabric->SysDegree[Token]++; - State->Fabric->SysMatrix[CurrentNode][Token] = TRUE; - State->Fabric->SysMatrix[Token][CurrentNode] = TRUE; - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Start discovery from a new node. - * - * If the node is not the BSP, establish a route between the node and the - * BSP for request/response. - * Set the node id, and enable routing on this node. This gives us control - * on that node to isolate links, by specifying each link in turn as the route - * to a possible new node. - * - * @param[in] CurrentNode The node we are exploring from - * @param[in] State Access to Northbridge interface. - * - */ -VOID -STATIC -StartFromANewNode ( - IN UINT8 CurrentNode, - IN STATE_DATA *State - ) -{ - if (CurrentNode != 0) { - // Set path from BSP to CurrentNode - routeFromBSP (CurrentNode, CurrentNode, State); - - // Set path from BSP to CurrentNode for CurrentNode + 1 if - // CurrentNode + 1 != MAX_NODES - // - if ((CurrentNode + 1) != MAX_NODES) { - routeFromBSP (CurrentNode, (CurrentNode + 1), State); - } - - // Configure CurrentNode to route traffic to the BSP through its - // default Link - // - State->Nb->WriteRoutingTable (CurrentNode, 0, State->Nb->ReadDefaultLink (CurrentNode, State->Nb), State->Nb); - } - - // Set CurrentNode's NodeID field to CurrentNode - State->Nb->WriteNodeID (CurrentNode, CurrentNode, State->Nb); - - // Enable routing tables on CurrentNode - State->Nb->EnableRoutingTables (CurrentNode, State->Nb); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Back up from exploring a one-deep internal node. - * - * When a newly discovered node has internal package links to another - * node in the same processor, discovery moves to that node to do the - * internal links. Afterwards, this routine provides recovery from that. - * The node needs to respond again using deflnk rather than routing, so - * that connections from other nodes to that one can be identified. - * - * @param[in] CurrentNode The node we are exploring from - * @param[in] State Access to Northbridge interface. - * - */ -VOID -STATIC -BackUpFromANode ( - IN UINT8 CurrentNode, - IN STATE_DATA *State - ) -{ - if (CurrentNode != 0) { - // Disable routing tables on CurrentNode - State->Nb->DisableRoutingTables (CurrentNode, State->Nb); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Dynamically Discover all coherent devices in the system. - * - * @HtFeatMethod{::F_COHERENT_DISCOVERY} - * - * Initialize some basics like Node IDs and total Nodes found in the - * process. As we go we also build a representation of the discovered - * system which we will use later to program the routing tables. - * During this step, the routing is via default Link back to BSP and - * to each new Node on the Link it was discovered on (no coherency is - * active yet). - * - * In the case of multiple nodes per processor, do a one deep exploration of internal links - * to ensure those node pairs are always numbered n, n + 1. - * - * @param[in,out] State our global state - * - */ -VOID -CoherentDiscovery ( - IN OUT STATE_DATA *State - ) -{ - UINT8 CurrentNode; - UINT8 OneDeepNode; - UINT8 OneDeepLink; - UINT8 CurrentLink; - UINT8 LogicalProcessor; - EXPLORE_NODE_STATUS ExplorationStatus; - LINK_ITERATOR_STATUS LinkIteratorStatus; - NEW_NODE_SAVED_INFO_ITEM NewNodeSavedInfoItems [MAX_NODES]; - NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo; - - // Initially no info exists for any node, but the BSP is part of logical processor zero. - for (CurrentNode = 0; CurrentNode < MAX_NODES; CurrentNode++) { - NewNodeSavedInfoItems [CurrentNode] = NoInfoSavedYet; - } - NewNodeSavedInfoItems[0].LogicalProcessor = 0; - NewNodeSavedInfoItems[0].HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb); - State->Nb->GetModuleInfo (0, &NewNodeSavedInfoItems[0].NewModuleType, &NewNodeSavedInfoItems[0].NewModule, State->Nb); - NewNodeSavedInfo = (NEW_NODE_SAVED_INFO_LIST) NewNodeSavedInfoItems; - - CurrentNode = 0; - CurrentLink = LINK_ITERATOR_BEGIN; - LogicalProcessor = 0; - // An initial status, for node zero if you will. - ExplorationStatus = ExploreNodeStatusGood; - - // - // Entries are always added in pairs, the even indices are the 'source' - // side closest to the BSP, the odd indices are the 'destination' side - // - - while ((CurrentNode <= State->NodesDiscovered) && (ExplorationStatus != ExploreNodeStatusStop)) { - StartFromANewNode (CurrentNode, State); - - // - // Explore all internal links - // - LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb); - - while ((LinkIteratorStatus == LinkIteratorInternal) && - (ExplorationStatus != ExploreNodeStatusStop)) { - if (IsLinkToAdd (CurrentNode, CurrentLink, State)) { - ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State); - if ((ExplorationStatus == ExploreNodeStatusGood) || - (ExplorationStatus == ExploreNodeStatusNew)) { - AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State); - } - } - LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb); - } - if (CurrentNode == 0) { - // The BSP processor is completely discovered now. - ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State); - LogicalProcessor++; - } - - // - // Explore all the external links from this node. - // - - // Starting this iteration using the link that we last got in the iteration above. - while ((LinkIteratorStatus == LinkIteratorExternal) && - (ExplorationStatus != ExploreNodeStatusStop)) { - if (IsLinkToAdd (CurrentNode, CurrentLink, State)) { - ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State); - if (ExplorationStatus == ExploreNodeStatusNew) { - AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State); - // If this is a new node, we need to explore to its internal mate, if any. - // This allows us to keep internal node pairs as ids n, n+1 - // We use special link and node variables so we can keep our context. - OneDeepLink = 0xFF; - OneDeepNode = State->Nb->ReadToken ((CurrentNode + 1), State->Nb); - StartFromANewNode (OneDeepNode, State); - LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb); - while ((LinkIteratorStatus == LinkIteratorInternal) && - (ExplorationStatus != ExploreNodeStatusStop)) { - if (IsLinkToAdd (OneDeepNode, OneDeepLink, State)) { - ExplorationStatus = ExploreNode (OneDeepNode, OneDeepLink, LogicalProcessor, NewNodeSavedInfo, State); - if ((ExplorationStatus == ExploreNodeStatusGood) || - (ExplorationStatus == ExploreNodeStatusNew)) { - AddLinkToSystem (OneDeepNode, OneDeepLink, (OneDeepNode + 1), State); - } - } - LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb); - } - // Since we completed all the node's internal links, we found all the nodes in that processor. - ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State); - LogicalProcessor++; - // Restore node to discoverable state. Otherwise you can't tell what links it is connected on. - BackUpFromANode (OneDeepNode, State); - } else { - if (ExplorationStatus == ExploreNodeStatusGood) { - AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State); - } - } - } - LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb); - } - CurrentNode++; - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.h deleted file mode 100644 index 25cbfdf0ef..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatDynamicDiscovery.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Coherent Discovery Interface. - * - * Contains interface to the coherent discovery feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _HT_FEAT_DYNAMIC_DISCOVERY_H_ -#define _HT_FEAT_DYNAMIC_DISCOVERY_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * Dynamically Discover all coherent devices in the system. - * - */ -VOID -CoherentDiscovery ( - IN OUT STATE_DATA *State - ); - -#endif /* _HT_FEAT_DYNAMIC_DISCOVERY_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.c deleted file mode 100644 index 533d376871..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.c +++ /dev/null @@ -1,218 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Routines for re-ganging Links. - * - * Implement the reganging feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "htFeatGanging.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FEATURES_HTFEATGANGING_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** Link Optimization *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Test the subLinks of a Link to see if they qualify to be reganged. - * - * @HtFeatMethod{::F_REGANG_LINKS} - * - * If they do, update the port list data to indicate that this should be done. - * @note no actual hardware state is changed in this routine. - * - * @param[in,out] State Our global state - */ -VOID -RegangLinks ( - IN OUT STATE_DATA *State - ) -{ - FINAL_LINK_STATE FinalLinkState; - UINT8 i; - UINT8 j; - for (i = 0; i < (State->TotalLinks * 2); i += 2) { - // Data validation - ASSERT ((*State->PortList)[i].Type < 2 && (*State->PortList)[i].Link < State->Nb->MaxLinks); - ASSERT ((*State->PortList)[i + 1].Type < 2 && (*State->PortList)[i + 1].Link < State->Nb->MaxLinks); - - // Regang is false unless we pass all conditions below - (*State->PortList)[i].SelRegang = FALSE; - (*State->PortList)[i + 1].SelRegang = FALSE; - - // Only process cpu to cpu Links - if ( ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) || - ((*State->PortList)[i + 1].Type != PORTLIST_TYPE_CPU)) { - continue; - } - - for (j = i + 2; j < State->TotalLinks*2; j += 2) { - // Only process cpu to cpu Links - if ( ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) || - ((*State->PortList)[j + 1].Type != PORTLIST_TYPE_CPU) ) { - continue; - } - - // Links must be from the same source - if ((*State->PortList)[i].NodeID != (*State->PortList)[j].NodeID) { - continue; - } - - // Link must be to the same target - if ((*State->PortList)[i + 1].NodeID != (*State->PortList)[j + 1].NodeID) { - continue; - } - - // Ensure same source base port - if (((*State->PortList)[i].Link & 3) != ((*State->PortList)[j].Link & 3)) { - continue; - } - - // Ensure same destination base port - if (((*State->PortList)[i + 1].Link & 3) != ((*State->PortList)[j + 1].Link & 3)) { - continue; - } - - // Ensure subLink0 routes to subLink0 - if (((*State->PortList)[i].Link & 4) != ((*State->PortList)[i + 1].Link & 4)) { - continue; - } - - // (therefore subLink1 routes to subLink1) - ASSERT (((*State->PortList)[j].Link & 4) == ((*State->PortList)[j + 1].Link & 4)); - - FinalLinkState = State->HtInterface->GetSkipRegang ((*State->PortList)[i].NodeID, - (*State->PortList)[i].Link & 0x03, - (*State->PortList)[i + 1].NodeID, - (*State->PortList)[i + 1].Link & 0x03, - State); - if (FinalLinkState == MATCHED) { - continue; - } else if (FinalLinkState == POWERED_OFF) { - // StopLink will be done on the sublink 1, thus OR in 4 to the link to ensure it. - State->Nb->StopLink ((*State->PortList)[i].NodeID, ((*State->PortList)[i].Link | 4), State, State->Nb); - State->Nb->StopLink ((*State->PortList)[i + 1].NodeID, ((*State->PortList)[i + 1].Link | 4), State, State->Nb); - } - - // - // Create a ganged portlist entry for the two regang-able subLinks. - // - // All info will be that of subLink zero. - // (If Link discovery order was other than ascending, fix the .Pointer field too.) - // - // - if (((*State->PortList)[i].Link & 4) != 0) { - (*State->PortList)[i].Pointer = (*State->PortList)[j].Pointer; - (*State->PortList)[i + 1].Pointer = (*State->PortList)[j + 1].Pointer; - } - (*State->PortList)[i].Link &= 0x03; // Force to point to subLink0 - (*State->PortList)[i + 1].Link &= 0x03; - // If powered off, sublink 1 is removed but the link is still 8 bits. - if (FinalLinkState != POWERED_OFF) { - (*State->PortList)[i].SelRegang = TRUE; // Enable Link reganging - (*State->PortList)[i + 1].SelRegang = TRUE; - (*State->PortList)[i].PrvWidthOutCap = HT_WIDTH_16_BITS; - (*State->PortList)[i + 1].PrvWidthOutCap = HT_WIDTH_16_BITS; - (*State->PortList)[i].PrvWidthInCap = HT_WIDTH_16_BITS; - (*State->PortList)[i + 1].PrvWidthInCap = HT_WIDTH_16_BITS; - } - - // Delete PortList[j, j + 1], slow but easy to debug implementation - State->TotalLinks--; - LibAmdMemCopy (&((*State->PortList)[j]), - &((*State->PortList)[j + 2]), - sizeof (PORT_DESCRIPTOR)*(State->TotalLinks* 2 - j), - State->ConfigHandle); - LibAmdMemFill (&((*State->PortList)[State->TotalLinks * 2]), INVALID_LINK, (sizeof (PORT_DESCRIPTOR) * 2), State->ConfigHandle); - - break; // Exit loop, advance to PortList[i + 2] - } - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.h deleted file mode 100644 index 988a4cfdb3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatGanging.h +++ /dev/null @@ -1,81 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Link Reganging Interface. - * - * Contains interface to the Reganging feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - *----------------------------------------------------------------------------- - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _HT_FEAT_GANGING_H_ -#define _HT_FEAT_GANGING_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * Test the subLinks of a Link to see if they qualify to be reganged. - * - */ -VOID -RegangLinks ( - IN OUT STATE_DATA *State - ); - -#endif /* _HT_FEAT_GANGING_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatNoncoherent.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatNoncoherent.c deleted file mode 100644 index bde99c8dc9..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatNoncoherent.c +++ /dev/null @@ -1,375 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Non-Coherent Discovery Routines. - * - * Contains routines for enumerating and initializing non-coherent devices. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNotify.h" -#include "htNb.h" -#include "htFeatNoncoherent.h" -#include "htFeatOptimization.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define NO_DEVICE 0xFFFFFFFFull - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** Non-coherent init code *** - *** Algorithms *** - ***************************************************************************/ -/*----------------------------------------------------------------------------------------*/ -/** - * Process a non-coherent Link. - * - * @HtFeatMethod{::F_PROCESS_LINK} - * - * Enable a range of bus numbers, and set the device ID for all devices found. Add - * non-coherent devices, links to the system data structure. - * - * @param[in] Node Node on which to process nc init - * @param[in] Link The non-coherent Link on that Node - * @param[in] IsCompatChain Is this the chain with the southbridge? TRUE if yes. - * @param[in,out] State our global state - */ -VOID -ProcessLink ( - IN UINT8 Node, - IN UINT8 Link, - IN BOOLEAN IsCompatChain, - IN OUT STATE_DATA *State - ) -{ - UINT8 SecBus; - UINT8 SubBus; - UINT32 CurrentBuid; - UINT32 Temp; - UINT32 UnitIdCount; - PCI_ADDR CurrentPtr; - PCI_ADDR Link1ControlRegister; - UINT8 Depth; - BUID_SWAP_LIST *SwapPtr; - UINT8 LastLink; - BOOLEAN IsCaveDevice; - - ASSERT ((Node < MAX_NODES) && (Link < State->Nb->MaxLinks)); - - if (!State->HtInterface->GetOverrideBusNumbers (Node, Link, &SecBus, &SubBus, State)) { - // Assign Bus numbers - if (State->AutoBusCurrent >= State->HtBlock->AutoBusMax) { - // If we run out of Bus Numbers, notify and skip this chain - // - IDS_ERROR_TRAP; - NotifyErrorNcohBusMaxExceed (Node, Link, State->AutoBusCurrent, State); - return; - } - - if (State->UsedCfgMapEntries >= 4) { - // If we have used all the PCI Config maps we can't add another chain. - // Notify and if call back is unimplemented or returns, skip this chain. - // - IDS_ERROR_TRAP; - NotifyErrorNcohCfgMapExceed (Node, Link, State); - return; - } - - SecBus = State->AutoBusCurrent; - SubBus = SecBus + State->HtBlock->AutoBusIncrement - 1; - State->AutoBusCurrent = State->AutoBusCurrent + State->HtBlock->AutoBusIncrement; - } - - State->Nb->SetConfigAddrMap (State->UsedCfgMapEntries, SecBus, SubBus, Node, Link, State, State->Nb); - State->UsedCfgMapEntries++; - - if (State->HtInterface->GetManualBuidSwapList (Node, Link, &SwapPtr, State)) { - // Manual non-coherent BUID assignment - AGESA_TESTPOINT (TpProcHtManualNc, State->ConfigHandle); - - - if (!IsCompatChain || !State->IsUsingRecoveryHt) { - // If this is the not southbridge chain or Recovery HT was not used - // then we need to assign BUIDs here. - // - Depth = 0; - // Assign BUID's per manual override - while (SwapPtr->Swaps[Depth].FromId != 0xFF) { - CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, SwapPtr->Swaps[Depth].FromId, 0, 0); - if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) { - // Set the device's BUID field [20:16] to the current buid - CurrentBuid = SwapPtr->Swaps[Depth].ToId; - LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle); - Depth++; - } else { - // All non-coherent devices must have a slave interface capability. - ASSERT (FALSE); - break; - } - } - } - - // Build chain of devices. Do this even if Recovery HT assign BUIDs for this chain. - Depth = 0; - while (SwapPtr->FinalIds[Depth] != 0xFF) { - ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS); - (*State->PortList)[(State->TotalLinks * 2)].NodeID = Node; - // Note: depth == 0 is true before depth > 0. This makes LastLink variable work. - if (Depth == 0) { - (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU; - (*State->PortList)[(State->TotalLinks * 2)].Link = Link; - } else { - // Fill in the host side port. Link and base pointer can be deduced from the upstream link's - // downstream port. - (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO; - (*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Link; - (*State->PortList)[(State->TotalLinks * 2)].HostLink = Link; - (*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1; - (*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Pointer; - } - - (*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO; - (*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node; - (*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link; - (*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth; - - CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, (SwapPtr->FinalIds[Depth] & 0x3F), 0, 0); - if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) { - (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr; - } else { - // All non-coherent devices must have a slave interface capability. - ASSERT (FALSE); - break; - } - - // Bit 6 indicates whether orientation override is desired. - // Bit 7 indicates the upstream Link if overriding. - // - // assert catches at least the one known incorrect setting, that a non-zero link - // is specified, but override desired is not set. - ASSERT (((SwapPtr->FinalIds[Depth] & 0x40) != 0) || ((SwapPtr->FinalIds[Depth] & 0x80) == 0)); - if ((SwapPtr->FinalIds[Depth] & 0x40) != 0) { - // Override the device's orientation - LastLink = SwapPtr->FinalIds[Depth] >> 7; - } else { - // Detect the device's orientation, by reading the Master Host bit [26] - LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle); - LastLink = (UINT8)Temp; - } - (*State->PortList)[(State->TotalLinks * 2) + 1].Link = LastLink; - - Depth++; - State->TotalLinks++; - } - } else { - // Automatic non-coherent device detection - AGESA_TESTPOINT (TpProcHtAutoNc, State->ConfigHandle); - IDS_HDT_CONSOLE (HT_TRACE, "Auto IO chain init on node=%d, link=%d, secbus=%d, subbus=%d%s.\n", - Node, Link, SecBus, SubBus, (IsCompatChain ? ", Compat" : "")); - Depth = 0; - CurrentBuid = 1; - for (; ; ) { - CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, 0, 0, 0); - - LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle); - if (Temp == NO_DEVICE) { - if (IsCompatChain && State->IsUsingRecoveryHt) { - // See if the device is aleady at a non-zero BUID because HT Init Reset aleady assigned it. - CurrentPtr.Address.Device = CurrentBuid; - LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle); - if (Temp == NO_DEVICE) { - // No more devices already assigned. - break; - } - } else { - // No more devices found. - break; - } - } - - ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS); - - (*State->PortList)[(State->TotalLinks * 2)].NodeID = Node; - if (Depth == 0) { - (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU; - (*State->PortList)[(State->TotalLinks * 2)].Link = Link; - } else { - // Fill in the host side port. Link and base pointer can be deduced from the upstream link's - // downstream port. - (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO; - (*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Link; - (*State->PortList)[(State->TotalLinks * 2)].HostLink = Link; - (*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1; - (*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Pointer; - } - - (*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO; - (*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node; - (*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link; - (*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth; - - if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) { - - // Get device's unit id count [25:21] - LibAmdPciReadBits (CurrentPtr, 25, 21, &UnitIdCount, State->ConfigHandle); - if (((UnitIdCount + CurrentBuid) > MAX_BUID) || ((SecBus == 0) && ((UnitIdCount + CurrentBuid) > 24))) { - // An error handler for the case where we run out of BUID's on a chain - NotifyErrorNcohBuidExceed (Node, Link, Depth, (UINT8)CurrentBuid, (UINT8)UnitIdCount, State); - IDS_ERROR_TRAP; - break; - } - // While we are still certain we are accessing this device, remember if it is a cave device. - // This is found by reading EOC from the Link 1 Control Register. - Link1ControlRegister = CurrentPtr; - Link1ControlRegister.Address.Register += (HTSLAVE_LINK01_OFFSET + HTSLAVE_LINK_CONTROL_0_REG); - LibAmdPciReadBits (Link1ControlRegister, 6, 6, &Temp, State->ConfigHandle); - IsCaveDevice = ((Temp == 0) ? FALSE : TRUE); - - // Attempt to write the new BUID. Unless this chain was aleady assigned BUIDs during Init Reset, - // then just re-discover the chain. Note this may be true whether the device was found at - // BUID zero or not. - IDS_HDT_CONSOLE (HT_TRACE, "Found device at depth=%d, BUID=%d.\n", Depth, CurrentPtr.Address.Device); - if (!IsCompatChain || !State->IsUsingRecoveryHt) { - IDS_HDT_CONSOLE (HT_TRACE, "Assigning device to BUID=%d.\n", CurrentBuid); - LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle); - } - - CurrentPtr.Address.Device = CurrentBuid; - LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle); - if (Temp != CurrentBuid) { - if ((Depth == 0) && IsCaveDevice) { - // If the chain only consists of a single cave device, that device may have retained zero - // for it's BUID. - CurrentPtr.Address.Device = 0; - LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle); - if (Temp == 0) { - // Per HyperTransport specification, devices not accepting BUID reassignment hardwire BUID to zero. - (*State->PortList)[(State->TotalLinks * 2) + 1].Link = 0; - (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr; - State->TotalLinks++; - Depth++; - // Success! - IDS_HDT_CONSOLE (HT_TRACE, "%s Cave left at BUID=0.\n", ((!IsCompatChain || !State->IsUsingRecoveryHt) ? "Compatible" : "Already Assigned")); - break; - } else if (Temp == CurrentBuid) { - // and then, there are the other kind of devices .... - // Restore the writable BUID field (which contains the value we just wrote) to zero. - Temp = 0; - LibAmdPciWriteBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle); - (*State->PortList)[(State->TotalLinks * 2) + 1].Link = 0; - (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr; - State->TotalLinks++; - Depth++; - // Success! - IDS_HDT_CONSOLE (HT_TRACE, "Cave left at BUID=0.\n"); - break; - } - } - // An error handler for this error, - // this often occurs in new BIOS ports and it means you need to use a Manual BUID Swap List. - NotifyErrorNcohDeviceFailed (Node, Link, Depth, (UINT8)CurrentBuid, State); - IDS_ERROR_TRAP; - break; - } - - LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle); - (*State->PortList)[(State->TotalLinks * 2) + 1].Link = (UINT8)Temp; - (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr; - - IDS_HDT_CONSOLE (HT_TRACE, "Device assigned.\n"); - Depth++; - State->TotalLinks++; - CurrentBuid += UnitIdCount; - } else { - // All non-coherent devices must have a slave interface capability. - ASSERT (FALSE); - break; - } - } - // Provide information on automatic device results - NotifyInfoNcohAutoDepth (Node, Link, (Depth - 1), State); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatNoncoherent.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatNoncoherent.h deleted file mode 100644 index 7293fbb8da..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatNoncoherent.h +++ /dev/null @@ -1,81 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Non-Coherent Discovery Interface. - * - * Contains interface to the Non-Coherent Link processing feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _HT_FEAT_NONCOHERENT_H_ -#define _HT_FEAT_NONCOHERENT_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * Process a non-coherent Link. - * - */ -VOID -ProcessLink ( - IN UINT8 Node, - IN UINT8 Link, - IN BOOLEAN IsCompatChain, - IN OUT STATE_DATA *State - ); - -#endif /* _HT_FEAT_NONCOHERENT_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatOptimization.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatOptimization.c deleted file mode 100644 index c1e20bde3f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatOptimization.c +++ /dev/null @@ -1,890 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Link Optimization Routines. - * - * Contains routines for determining width, frequency, and other - * Link features - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "IdsHt.h" -#include "htInterface.h" -#include "htNb.h" -#include "htFeatOptimization.h" -#include "htNotify.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE - -extern CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define PCI_CONFIG_COMMAND_REG04 4 -#define PCI_CONFIG_REVISION_REG08 8 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** Link Optimization *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Given the bits set in the register field, return the width it represents. - * - * As invalid width values or encodings are rare except during debug, catch those using - * ASSERT(). This means theoretically we are returning an incorrect result if that - * happens. The default chosen for the result is arbitrarily 8 bits. This is likely - * not to be the actual correct width and may cause a crash, hang, or incorrect operation. - * Hardware often ignores writes of invalid width encodings. - * - * @note This routine is used for CPUs as well as IO devices, as all comply to the - * "HyperTransport I/O Link Specification ". - * - * @param[in] Value The bits for the register - * - * @return The width - */ -UINT8 -STATIC -ConvertBitsToWidth ( - IN UINT8 Value - ) -{ - UINT8 Result; - - Result = 0; - - switch (Value) { - - case 1: - Result = 16; - break; - - case 0: - Result = 8; - break; - - case 3: - Result = 32; - break; - - case 5: - Result = 4; - break; - - case 4: - Result = 2; - break; - - default: - ASSERT (FALSE); - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Translate a desired width setting to the bits to set in the register field. - * - * As invalid width values or encodings are rare except during debug, catch those using - * ASSERT(). This means theoretically we are returning an incorrect result if that - * happens. The default chosen for the result is arbitrarily 8 bits. This is likely - * not to be the actual correct width and may cause a crash, hang, or incorrect operation. - * Hardware often ignores writes of invalid width encodings. - * - * @note This routine is used for CPUs as well as IO devices, as all comply to the - * "HyperTransport I/O Link Specification ". - * - * @param[in] Value the width Value - * - * @return The bits for the register - */ -UINT8 -ConvertWidthToBits ( - IN UINT8 Value - ) -{ - UINT8 Result; - - Result = 8; - - switch (Value) { - - case 16: - Result = 1; - break; - - case 8: - Result = 0; - break; - - case 32: - Result = 3; - break; - - case 4: - Result = 5; - break; - - case 2: - Result = 4; - break; - - default: - ASSERT (FALSE); - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Access HT Link Control Register. - * - * @HtFeatMethod{::F_SET_HT_CONTROL_REGISTER_BITS} - * - * Provide a common routine for accessing the HT Link Control registers (84, a4, c4, - * e4), to enforce not clearing the HT CRC error bits. Replaces direct use of - * AmdPCIWriteBits(). - * - * @note: This routine is called for CPUs as well as IO Devices! All comply to the - * "HyperTransport I/O Link Specification ". - * - * @param[in] Reg the PCI config address the control register - * @param[in] HiBit the high bit number - * @param[in] LoBit the low bit number - * @param[in] Value the value to write to that bit range. Bit 0 => loBit. - * @param[in] State Our state, config handle for lib - */ -VOID -SetHtControlRegisterBits ( - IN PCI_ADDR Reg, - IN UINT8 HiBit, - IN UINT8 LoBit, - IN UINT32 *Value, - IN STATE_DATA *State - ) -{ - UINT32 Temp; - UINT32 mask; - - ASSERT ((HiBit < 32) && (LoBit < 32) && (HiBit >= LoBit) && ((Reg.AddressValue & 0x3) == 0)); - ASSERT ((HiBit < 8) || (LoBit > 9)); - - // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case - if ((HiBit - LoBit) != 31) { - mask = (((UINT32)1 << (HiBit - LoBit + 1)) - 1); - } else { - mask = (UINT32)0xFFFFFFFF; - } - - LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle); - Temp &= ~(mask << LoBit); - Temp |= (*Value & mask) << LoBit; - Temp &= (UINT32)HT_CONTROL_CLEAR_CRC; - LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set HT Frequency register for IO Devices - * - * Provide a common routine for accessing the HT Link Frequency registers at offset 8 - * and 0x10, to enforce not clearing the HT Link error bits. Replaces direct use of - * AmdPCIWriteBits(). - * - * @note This routine is called for IO Devices only!! All comply to the - * "HyperTransport I/O Link Specification ". - * - * @param[in] Reg the PCI config address the control register - * @param[in] Hibit the high bit number - * @param[in] Lobit the low bit number - * @param[in] Value the value to write to that bit range. Bit 0 => loBit. - * @param[in] State Our state, config handle for lib - */ -VOID -STATIC -SetHtIoFrequencyRegisterBits ( - IN PCI_ADDR Reg, - IN UINT8 Hibit, - IN UINT8 Lobit, - IN UINT32 *Value, - IN STATE_DATA *State - ) -{ - UINT32 Mask; - UINT32 Temp; - - ASSERT ((Hibit < 32) && (Lobit < 32) && (Hibit >= Lobit) && ((Reg.AddressValue & 0x3) == 0)); - ASSERT ((Hibit < 12) || (Lobit > 14)); - - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - if ((Hibit - Lobit) != 31) { - Mask = (((UINT32)1 << ((Hibit - Lobit) + 1)) - 1); - } else { - Mask = (UINT32)0xFFFFFFFF; - } - - LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle); - Temp &= ~(Mask << Lobit); - Temp |= (*Value & Mask) << Lobit; - Temp &= (UINT32)HT_FREQUENCY_CLEAR_LINK_ERRORS; - LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Link features into system data structure. - * - * @HtFeatMethod{::F_GATHER_LINK_DATA} - * - * For all discovered Links, populate the port list with the frequency and width - * capabilities. Gather support data for: - * - Unit ID Clumping - * - * @param[in] State our global state, port list - */ -VOID -GatherLinkData ( - IN STATE_DATA *State - ) -{ - UINT8 i; - PCI_ADDR LinkBase; - PCI_ADDR Reg; - UINT32 Bits; - UINT8 Revision; - - // Get the capability base for whatever device type the link port is on - for (i = 0; i < (State->TotalLinks * 2); i++) { - if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) { - LinkBase = State->Nb->MakeLinkBase ((*State->PortList)[i].NodeID, (*State->PortList)[i].Link, State->Nb); - (*State->PortList)[i].Pointer = LinkBase; - } else { - LinkBase = (*State->PortList)[i].Pointer; - if ((*State->PortList)[i].Link == 1) { - LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET; - } - } - - // Getting the Width is standard across device types - Reg = LinkBase; - Reg.Address.Register += HTSLAVE_LINK_CONTROL_0_REG; - LibAmdPciReadBits (Reg, 22, 20, &Bits, State->ConfigHandle); - (*State->PortList)[i].PrvWidthOutCap = ConvertBitsToWidth ((UINT8)Bits); - - LibAmdPciReadBits (Reg, 18, 16, &Bits, State->ConfigHandle); - (*State->PortList)[i].PrvWidthInCap = ConvertBitsToWidth ((UINT8)Bits); - - // Get Frequency and other device type specific features - if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) { - State->Nb->GatherLinkFeatures (&(*State->PortList)[i], State->HtInterface, State->PlatformConfiguration, State->Nb); - } else { - Reg = LinkBase; - Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG; - LibAmdPciReadBits (Reg, 31, 16, &Bits, State->ConfigHandle); - (*State->PortList)[i].PrvFrequencyCap = Bits; - - // Unit ID Clumping Support - if (State->IsUsingUnitIdClumping) { - if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) { - Reg.Address.Register += HTUNIT_SUPPORT_REG; - LibAmdPciReadBits (Reg, 31, 0, &Bits, State->ConfigHandle); - } else { - // Not there, that's ok, we don't know that it should have one. - // Check for Passive support. (Bit 0 won't be set if full support is implemented, - // so we can use it to indicate passive support in our portlist struct). - Reg = LinkBase; - Reg.Address.Register += HTSLAVE_FEATURECAP_REG; - Bits = 1; - LibAmdPciWriteBits (Reg, 5, 5, &Bits, State->ConfigHandle); - LibAmdPciReadBits (Reg, 5, 5, &Bits, State->ConfigHandle); - } - (*State->PortList)[i].ClumpingSupport = Bits; - } else { - (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE; - } - - Reg = LinkBase; - Reg.Address.Register = PCI_CONFIG_REVISION_REG08; - LibAmdPciReadBits ( LinkBase, 7, 0, &Bits, State->ConfigHandle); - Revision = (UINT8) Bits; - - LinkBase.Address.Register = 0; - LibAmdPciRead (AccessWidth32, LinkBase, &Bits, State->ConfigHandle); - - State->HtInterface->GetDeviceCapOverride ((*State->PortList)[i].NodeID, - (*State->PortList)[i].HostLink, - (*State->PortList)[i].HostDepth, - (*State->PortList)[i].Pointer, - Bits, - Revision, - (*State->PortList)[i].Link, - &((*State->PortList)[i].PrvWidthInCap), - &((*State->PortList)[i].PrvWidthOutCap), - &((*State->PortList)[i].PrvFrequencyCap), - &((*State->PortList)[i].ClumpingSupport), - State); - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Optimize Links. - * - * @HtFeatMethod{::F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY} - * - * For all Links: - * Examine both sides of a Link and determine the optimal frequency and width, - * taking into account externally provided limits and enforcing any other limit - * or matching rules as applicable except subLink balancing. Update the port - * list data with the optimal settings. - * - * @note no hardware state changes in this routine. - * - * @param[in,out] State Process and update portlist - */ -VOID -SelectOptimalWidthAndFrequency ( - IN OUT STATE_DATA *State - ) -{ - UINT8 i; - UINT8 j; - UINT8 Freq; - UINT32 Temp; - UINT32 CbPcbFreqLimit; - UINT8 CbPcbABDownstreamWidth; - UINT8 CbPcbBAUpstreamWidth; - - for (i = 0; i < (State->TotalLinks * 2); i += 2) { - CbPcbFreqLimit = HT_FREQUENCY_NO_LIMIT; - CbPcbABDownstreamWidth = HT_WIDTH_16_BITS; - CbPcbBAUpstreamWidth = HT_WIDTH_16_BITS; - - if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) { - State->HtInterface->GetCpu2CpuPcbLimits ((*State->PortList)[i].NodeID, - (*State->PortList)[i].Link, - (*State->PortList)[i + 1].NodeID, - (*State->PortList)[i + 1].Link, - &CbPcbABDownstreamWidth, - &CbPcbBAUpstreamWidth, - &CbPcbFreqLimit, - State - ); - } else { - State->HtInterface->GetIoPcbLimits ((*State->PortList)[i + 1].NodeID, - (*State->PortList)[i + 1].HostLink, - (*State->PortList)[i + 1].HostDepth, - &CbPcbABDownstreamWidth, - &CbPcbBAUpstreamWidth, - &CbPcbFreqLimit, - State - ); - } - - Temp = (*State->PortList)[i].PrvFrequencyCap; - Temp &= (*State->PortList)[i + 1].PrvFrequencyCap; - Temp &= CbPcbFreqLimit; - (*State->PortList)[i].CompositeFrequencyCap = (UINT32)Temp; - (*State->PortList)[i + 1].CompositeFrequencyCap = (UINT32)Temp; - - ASSERT (Temp != 0); - Freq = LibAmdBitScanReverse (Temp); - (*State->PortList)[i].SelFrequency = Freq; - (*State->PortList)[i + 1].SelFrequency = Freq; - - Temp = (*State->PortList)[i].PrvWidthOutCap; - if ((*State->PortList)[i + 1].PrvWidthInCap < Temp) { - Temp = (*State->PortList)[i + 1].PrvWidthInCap; - } - if (CbPcbABDownstreamWidth < Temp) { - Temp = CbPcbABDownstreamWidth; - } - (*State->PortList)[i].SelWidthOut = (UINT8)Temp; - (*State->PortList)[i + 1].SelWidthIn = (UINT8)Temp; - - Temp = (*State->PortList)[i].PrvWidthInCap; - if ((*State->PortList)[i + 1].PrvWidthOutCap < Temp) { - Temp = (*State->PortList)[i + 1].PrvWidthOutCap; - } - if (CbPcbBAUpstreamWidth < Temp) { - Temp = CbPcbBAUpstreamWidth; - } - (*State->PortList)[i].SelWidthIn = (UINT8)Temp; - (*State->PortList)[i + 1].SelWidthOut = (UINT8)Temp; - } - // Calculate unit id clumping - // - // Find the root of each IO Chain, process the chain for clumping support. - // The root is always the first link of the chain in the port list. - // Clumping is not device link specific, so we can just look at the upstream ports (j+1). Use ASSERTs to sanity - // check the downstream ports (j). If any device on the chain does not support clumping, the entire chain will be - // disabled for clumping. - // After analyzing the clumping support on the chain the CPU's portlist has the enable mask. Update all the - // IO Devices on the chain with the enable mask. If any device's only have passive support, that is already enabled. - // - if (State->IsUsingUnitIdClumping) { - for (i = 0; i < (State->TotalLinks * 2); i += 2) { - if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_IO)) { - (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE; - if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_DISABLE) { - (*State->PortList)[i].ClumpingSupport |= (*State->PortList)[i + 1].ClumpingSupport; - for (j = i + 2; j < (State->TotalLinks * 2); j += 2) { - if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) { - if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) && - ((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) { - ASSERT (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) && - ((*State->PortList)[i].Link == (*State->PortList)[j].HostLink)); - if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_DISABLE) { - ASSERT ((((*State->PortList)[j + 1].ClumpingSupport & HT_CLUMPING_PASSIVE) == 0) || - (((*State->PortList)[j + 1].ClumpingSupport & ~(HT_CLUMPING_PASSIVE)) == 0)); - (*State->PortList)[i].ClumpingSupport |= (*State->PortList)[j + 1].ClumpingSupport; - } else { - (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE; - break; - } - } - } - } - if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) { - (*State->PortList)[i + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport; - } - for (j = i + 2; j < (State->TotalLinks * 2); j += 2) { - if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) { - if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) && - ((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) { - if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) { - (*State->PortList)[j + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport; - // The downstream isn't really passive, just mark it so in order to write the device only once. - (*State->PortList)[j].ClumpingSupport = HT_CLUMPING_PASSIVE; - } - } - } - } - } - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure. - * - * @HtFeatMethod{::F_SET_LINK_DATA} - * - * @param[in] State our global state, port list - */ -VOID -SetLinkData ( - IN STATE_DATA *State - ) -{ - UINT8 i; - PCI_ADDR LinkBase; - PCI_ADDR Reg; - UINT32 Temp; - UINT32 Widthin; - UINT32 Widthout; - UINT32 Bits; - PCI_ADDR CurrentPtr; - HTIDS_PORT_OVERRIDE_LIST PortOverrides; - - PortOverrides = NULL; - - for (i = 0; i < (State->TotalLinks * 2); i++) { - - ASSERT ((*State->PortList)[i & 0xFE].SelWidthOut == (*State->PortList)[ (i & 0xFE) + 1].SelWidthIn); - ASSERT ((*State->PortList)[i & 0xFE].SelWidthIn == (*State->PortList)[ (i & 0xFE) + 1].SelWidthOut); - ASSERT ((*State->PortList)[i & 0xFE].SelFrequency == (*State->PortList)[ (i & 0xFE) + 1].SelFrequency); - - if ((*State->PortList)[i].SelRegang) { - ASSERT ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU); - ASSERT ((*State->PortList)[i].Link < 4); - State->Nb->SetLinkRegang ( - (*State->PortList)[i].NodeID, - (*State->PortList)[i].Link, - State->Nb - ); - } - - // - // IDS port override for CPUs and IO Devices - // - pf_HtIdsGetPortOverride ((BOOLEAN) ((i & 1) == 0), &(*State->PortList)[i], &(*State->PortList)[i + 1], &PortOverrides, State); - - LinkBase = (*State->PortList)[i].Pointer; - if (((*State->PortList)[i].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[i].Link == 1)) { - LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET; - } - - // HT CRC Feature, set if configured. The default is not to set it, because with some chipsets it - // will lock up if done here. - if (State->IsSetHtCrcFlood) { - Temp = 1; - Reg = LinkBase; - Reg.Address.Register += HTHOST_LINK_CONTROL_REG; - State->HtFeatures->SetHtControlRegisterBits (Reg, 1, 1, &Temp, State); - if ((*State->PortList)[i].Type == PORTLIST_TYPE_IO) { - // IO Devices also need to have SERR enabled. - Reg = LinkBase; - Reg.Address.Register = PCI_CONFIG_COMMAND_REG04; - LibAmdPciWriteBits (Reg, 8, 8, &Temp, State->ConfigHandle); - } - } - - // Some IO devices don't work properly when setting widths, so write them in a single operation, - // rather than individually. - // - Widthout = ConvertWidthToBits ((*State->PortList)[i].SelWidthOut); - ASSERT (Widthout == 1 || Widthout == 0 || Widthout == 5 || Widthout == 4); - Widthin = ConvertWidthToBits ((*State->PortList)[i].SelWidthIn); - ASSERT (Widthin == 1 || Widthin == 0 || Widthin == 5 || Widthin == 4); - - Temp = (Widthin & 7) | ((Widthout & 7) << 4); - Reg = LinkBase; - Reg.Address.Register += HTHOST_LINK_CONTROL_REG; - State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State); - - Temp = (*State->PortList)[i].SelFrequency; - IDS_HDT_CONSOLE (HT_TRACE, "Link Frequency: Node %02d: Link %02d: is running at %2d00MHz\n", - (*State->PortList)[i].NodeID, (*State->PortList)[i].Link, - (Temp < HT_FREQUENCY_800M) ? Temp + 2 : ((Temp < HT_FREQUENCY_2800M) ? 2 * (Temp - 1) : 2 * (Temp - 3))); - - if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) { - State->Nb->SetLinkFrequency ( - (*State->PortList)[i].NodeID, - (*State->PortList)[i].Link, - (UINT8)Temp, - State->Nb - ); - } else { - ASSERT (Temp <= HT_FREQUENCY_2600M); - // Write the frequency setting - Reg = LinkBase; - Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG; - SetHtIoFrequencyRegisterBits (Reg, 11, 8, &Temp, State); - - // Handle additional HT3 frequency requirements, if needed, - // or clear them if switching down to ht1 on a warm reset. - // Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz - // - // Even though we assert if debugging, we need to check that the capability was - // found always, since this is an unknown hardware device, also we are taking - // unqualified frequency from the external interface (could be trying to do ht3 - // on an ht1 IO device). - // - - if (Temp > HT_FREQUENCY_1000M) { - // Enabling features if gen 3 - Bits = 1; - } else { - // Disabling features if gen 1 - Bits = 0; - } - - // Retry Enable - if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_RETRY_CAPABILITY, &CurrentPtr, State)) { - ASSERT ((*State->PortList)[i].Link < 2); - CurrentPtr.Address.Register += HTRETRY_CONTROL_REG; - LibAmdPciWriteBits (CurrentPtr, - ((*State->PortList)[i].Link * 16), - ((*State->PortList)[i].Link * 16), - &Bits, - State->ConfigHandle); - } else { - // If we are turning it off, that may mean the device was only ht1 capable, - // so don't complain that we can't do it. - // - if (Bits != 0) { - NotifyWarningOptRequiredCapRetry ((*State->PortList)[i].NodeID, - (*State->PortList)[i].HostLink, - (*State->PortList)[i].HostDepth, - State); - } - } - - // Scrambling enable - if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_GEN3_CAPABILITY, &CurrentPtr, State)) { - ASSERT ((*State->PortList)[i].Link < 2); - CurrentPtr.Address.Register = CurrentPtr.Address.Register + - HTGEN3_LINK_TRAINING_0_REG + - ((*State->PortList)[i].Link * HTGEN3_LINK01_OFFSET); - LibAmdPciWriteBits (CurrentPtr, 3, 3, &Bits, State->ConfigHandle); - } else { - // If we are turning it off, that may mean the device was only ht1 capable, - // so don't complain that we can't do it. - // - if (Bits != 0) { - NotifyWarningOptRequiredCapGen3 ((*State->PortList)[i].NodeID, - (*State->PortList)[i].HostLink, - (*State->PortList)[i].HostDepth, - State); - } - } - } - // Enable Unit ID Clumping if supported. - if (State->IsUsingUnitIdClumping) { - if (((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_PASSIVE) && - ((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_DISABLE)) { - Bits = (*State->PortList)[i].ClumpingSupport; - if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) { - State->Nb->SetLinkUnitIdClumping ( - (*State->PortList)[i].NodeID, - (*State->PortList)[i].Link, - (*State->PortList)[i].ClumpingSupport, - State->Nb - ); - } else { - if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) { - Reg.Address.Register += HTUNIT_ENABLE_REG; - LibAmdPciWriteBits (Reg, 31, 0, &Bits, State->ConfigHandle); - } else { - // If we found one when gathering support, we have to find one now. - ASSERT (FALSE); - } - } - } - } - } -} - -/*------------------------------------------------------------------------------------------*/ -/** - * Find a specific HT capability type. - * - * Search all the PCI Config space capabilities on any type of device for an - * HT capability of the specific subtype. - * - * @param[in] DevicePointer A PCI Config address somewhere in the device config space - * @param[in] CapSubType The HT capability subtype to find - * @param[out] CapabilityBase The Config space base address of the capability, if found. - * @param[in] State Our State - * - * @retval TRUE the capability was found - * @retval FALSE the capability was not found - */ -BOOLEAN -DoesDeviceHaveHtSubtypeCap ( - IN PCI_ADDR DevicePointer, - IN UINT8 CapSubType, - OUT PCI_ADDR *CapabilityBase, - IN STATE_DATA *State - ) -{ - BOOLEAN IsFound; - BOOLEAN IsDone; - PCI_ADDR Reg; - UINT32 Temp; - UINT32 RegSubType; - UINT32 RegSubTypeMask; - - // Set the PCI Config Space base and the match value. - IsFound = FALSE; - IsDone = FALSE; - Reg = DevicePointer; - Reg.Address.Register = 0; - if (CapSubType < (HT_HOST_CAPABILITY + 1)) { - // HT Interface sub type - RegSubType = ((UINT32) (CapSubType << 29) | (UINT32)8); - RegSubTypeMask = HT_INTERFACE_CAP_SUBTYPE_MASK; - } else { - // Other HT capability subtype - RegSubType = ((UINT32) (CapSubType << 27) | (UINT32)8); - RegSubTypeMask = HT_CAP_SUBTYPE_MASK; - } - (*CapabilityBase).AddressValue = (UINT32)ILLEGAL_SBDFO; - - // Find it - do { - LibAmdPciFindNextCap (&Reg, State->ConfigHandle); - if (Reg.AddressValue != (UINT32)ILLEGAL_SBDFO) { - LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle); - // HyperTransport and subtype capability ? - if ((Temp & RegSubTypeMask) == RegSubType) { - *CapabilityBase = Reg; - IsFound = TRUE; - } - // Some other capability, keep looking - } else { - // Not there - IsDone = TRUE; - } - } while (!IsFound && !IsDone); - - return IsFound; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Retry must be enabled on all coherent links if it is enabled on any coherent links. - * - * @HtFeatMethod{::F_SET_LINK_DATA} - * - * Effectively, this means HT3 on some links cannot be mixed with HT1 on others. - * Scan the CPU to CPU links for this condition and limit those frequencies to HT1 - * if it is detected. - * (Non-coherent links are independent.) - * - * @param[in,out] State global state, port frequency settings. - * - * @retval TRUE Fixup occurred, all coherent links HT1 - * @retval FALSE No changes - */ -BOOLEAN -IsCoherentRetryFixup ( - IN STATE_DATA *State - ) -{ - UINT8 Freq; - UINT8 i; - UINT8 DetectedFrequencyState; - BOOLEAN IsMixed; - UINT32 Temp; - - // - // detectedFrequencyState: - // 0 - initial state - // 1 - HT1 Frequencies detected - // 2 - HT3 Frequencies detected - // - IsMixed = FALSE; - DetectedFrequencyState = 0; - - // Scan coherent links for a mix of HT3 / HT1 - for (i = 0; i < (State->TotalLinks * 2); i += 2) { - if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) { - // At this point, Frequency of port [i+1] must equal [i], so just check one of them. - switch (DetectedFrequencyState) { - case 0: - // Set current state to indicate what link frequency we found first - if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) { - // HT3 frequencies - DetectedFrequencyState = 2; - } else { - // HT1 frequencies - DetectedFrequencyState = 1; - } - break; - case 1: - // If HT1 frequency detected, fail any HT3 frequency - if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) { - IsMixed = TRUE; - } - break; - case 2: - // If HT3 frequency detected, fail any HT1 frequency - if ((*State->PortList)[i].SelFrequency <= HT_FREQUENCY_1000M) { - IsMixed = TRUE; - } - break; - default: - ASSERT (FALSE); - } - if (IsMixed) { - // Don't need to keep checking after we find a mix. - break; - } - } - } - - if (IsMixed) { - for (i = 0; i < (State->TotalLinks * 2); i += 2) { - if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) { - // Limit coherent links to HT 1 frequencies. - Temp = (*State->PortList)[i].CompositeFrequencyCap & (*State->PortList)[i + 1].CompositeFrequencyCap; - Temp &= HT_FREQUENCY_LIMIT_HT1_ONLY; - ASSERT (Temp != 0); - (*State->PortList)[i].CompositeFrequencyCap = Temp; - (*State->PortList)[i + 1].CompositeFrequencyCap = Temp; - Freq = LibAmdBitScanReverse (Temp); - (*State->PortList)[i].SelFrequency = Freq; - (*State->PortList)[i + 1].SelFrequency = Freq; - } - } - } - return (IsMixed); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatOptimization.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatOptimization.h deleted file mode 100644 index e4cf5099a2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatOptimization.h +++ /dev/null @@ -1,140 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Link Optimization Feature. - * - * Contains interface for Link Optimization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _HT_FEAT_OPTIMIZATION_H_ -#define _HT_FEAT_OPTIMIZATION_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * Translate a desired width setting to the bits to set in the register field. - */ -UINT8 -ConvertWidthToBits ( - IN UINT8 Value - ); - -/** - * Access HT Link Control Register. - * - */ -VOID -SetHtControlRegisterBits ( - IN PCI_ADDR Reg, - IN UINT8 HiBit, - IN UINT8 LoBit, - IN UINT32 *Value, - IN STATE_DATA *State - ); - -/** - * Get Link features into system data structure. - * - */ -VOID -GatherLinkData ( - IN STATE_DATA *State - ); - -/** - * Optimize Links. - * - */ -VOID -SelectOptimalWidthAndFrequency ( - IN OUT STATE_DATA *State - ); - -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure. - * - */ -VOID -SetLinkData ( - IN STATE_DATA *State - ); - -/** - * Retry must be enabled on all coherent links if it is enabled on any coherent links. - * - */ -BOOLEAN -IsCoherentRetryFixup ( - IN STATE_DATA *State - ); - -/** - * Find a specific HT capability type. - * - * @retval FALSE the capability was not found - */ -BOOLEAN -DoesDeviceHaveHtSubtypeCap ( - IN PCI_ADDR DevicePointer, - IN UINT8 CapSubType, - OUT PCI_ADDR *CapabilityBase, - IN STATE_DATA *State - ); - -#endif /* _HT_FEAT_OPTIMIZATION_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.c deleted file mode 100644 index 5d34153fc5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.c +++ /dev/null @@ -1,493 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Routing Routines - * - * Contains routines for isomorphic topology matching, - * routing determination, and routing initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNotify.h" -#include "htNb.h" -#include "htGraph.h" -#include "htFeatRouting.h" -#include "htTopologies.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FEATURES_HTFEATROUTING_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -typedef struct { - UINT8 **CurrentPosition; - BOOLEAN IsCustomList; -} TOPOLOGY_CONTEXT; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** ISOMORPHISM BASED ROUTING TABLE GENERATION CODE *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Return the Link on source Node which connects to target Node - * - * @param[in] SourceNode The Node on which to find the Link - * @param[in] TargetNode The Link will connect to this Node - * @param[in] State Our global state - * - * @return the Link to target - */ -UINT8 -STATIC -FindLinkToNode ( - IN UINT8 SourceNode, - IN UINT8 TargetNode, - IN STATE_DATA *State - ) -{ - UINT8 TargetLink; - UINT8 k; - - // A node linked to itself is not a supported topology graph, this is probably an error in the - // topology data. There is not going to be a portlist match for it. - ASSERT (SourceNode != TargetNode); - TargetLink = INVALID_LINK; - for (k = 0; k < State->TotalLinks*2; k += 2) { - if (((*State->PortList)[k].NodeID == SourceNode) && ((*State->PortList)[k + 1].NodeID == TargetNode)) { - TargetLink = (*State->PortList)[k].Link; - break; - } else if (((*State->PortList)[k + 1].NodeID == SourceNode) && ((*State->PortList)[k].NodeID == TargetNode)) { - TargetLink = (*State->PortList)[k + 1].Link; - break; - } - } - ASSERT (TargetLink != INVALID_LINK); - - return TargetLink; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Is graphA isomorphic to graphB? - * - * If this function returns true, then Perm will contain the permutation - * required to transform graphB into graphA. - * We also use the degree of each Node, that is the number of connections it has, to - * speed up rejection of non-isomorphic graphs (if there is a Node in graphA with n - * connections, there must be at least one unmatched in graphB with n connections). - * - * @param[in] Node the discovered Node which we are trying to match - * with a permutation the topology - * @param[in,out] State our global state, degree and adjacency matrix, - * output a permutation if successful - * @retval TRUE the graphs are isomorphic - * @retval FALSE the graphs are not isomorphic - * - */ -BOOLEAN -STATIC -IsIsomorphic ( - IN UINT8 Node, - IN OUT STATE_DATA *State - ) -{ - UINT8 j; - UINT8 k; - UINT8 Nodecnt; - - // We have only been called if Nodecnt == pSelected->size ! - Nodecnt = State->NodesDiscovered + 1; - - if (Node != Nodecnt) { - // Keep building the permutation - for (j = 0; j < Nodecnt; j++) { - // Make sure the degree matches - if (State->Fabric->SysDegree[Node] != State->Fabric->DbDegree[j]) { - continue; - } - - // Make sure that j hasn't been used yet (ought to use a "used" - // array instead, might be faster) - for (k = 0; k < Node; k++) { - if (State->Fabric->Perm[k] == j) { - break; - } - } - if (k != Node) { - continue; - } - State->Fabric->Perm[Node] = j; - if (IsIsomorphic (Node + 1, State)) { - return TRUE; - } - } - return FALSE; - } else { - // Test to see if the permutation is isomorphic - for (j = 0; j < Nodecnt; j++) { - for (k = 0; k < Nodecnt; k++) { - if (State->Fabric->SysMatrix[j][k] != State->Fabric->DbMatrix[State->Fabric->Perm[j]][State->Fabric->Perm[k]] ) { - return FALSE; - } - } - } - return TRUE; - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set Topology List iterator context to the Beginning and provide the first topology. - * - * Check the interface for a custom topology list. If one is found, set context to the - * first item, and return that item. Otherwise return the first item in the built in list. - * - * @param[in,out] TopologyContextHandle Initialize this context to beginning of lists. - * @param[out] NextTopology The next topology, NULL if end. - * @param[in] State Access to interface, handles. - * - */ -VOID -STATIC -BeginTopologies ( - OUT TOPOLOGY_CONTEXT *TopologyContextHandle, - OUT UINT8 **NextTopology, - IN STATE_DATA *State - ) -{ - if (State->HtBlock->Topolist != NULL) { - // Start with a custom list - TopologyContextHandle->CurrentPosition = State->HtBlock->Topolist; - TopologyContextHandle->IsCustomList = TRUE; - } else { - // Start with the built in list - GetAmdTopolist (&TopologyContextHandle->CurrentPosition); - TopologyContextHandle->IsCustomList = FALSE; - } - *NextTopology = *TopologyContextHandle->CurrentPosition; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Iterate through available topologies. - * - * Increment to the next list item. If we are doing a custom list, when we reach the end - * switch to the built in list. - * - * @param[in,out] TopologyContextHandle Maintain iterator's context from one call to the next - * @param[out] NextTopology The next topology, NULL if end. - * - */ -VOID -STATIC -GetNextTopology ( - IN OUT TOPOLOGY_CONTEXT *TopologyContextHandle, - OUT UINT8 **NextTopology - ) -{ - // Not valid to continue calling this routine after reaching the end. - ASSERT (TopologyContextHandle->CurrentPosition != NULL); - - if (TopologyContextHandle->IsCustomList) { - // We are iterating the custom list from the interface. - TopologyContextHandle->CurrentPosition++; - if (*TopologyContextHandle->CurrentPosition == NULL) { - // We are at the end of the custom list, switch to the built in list. - TopologyContextHandle->IsCustomList = FALSE; - GetAmdTopolist (&TopologyContextHandle->CurrentPosition); - } - } else { - // We are iterating the built in list - TopologyContextHandle->CurrentPosition++; - // If we are at the end of the built in list, NextTopology == NULL is the AtEnd. - } - *NextTopology = *TopologyContextHandle->CurrentPosition; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Using the description of the fabric topology we discovered, try to find a match - * among the supported topologies. - * - * @HtFeatMethod{::F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES} - * - * A supported topology description matches the discovered fabric if the Nodes can be - * matched in such a way that all the Nodes connected in one set are exactly the - * Nodes connected in the other (formally, that the graphs are isomorphic). Which - * Links are used is not really important to matching. If the graphs match, then - * there is a permutation of one that translates the Node positions and Linkages to - * the other. - * - * In order to make the isomorphism test efficient, we test for matched number of Nodes - * (a 4 Node fabric is not isomorphic to a 2 Node topology), and provide degrees of Nodes - * to the isomorphism test. - * - * The generic routing table solution for any topology is predetermined and represented - * as part of the topology. The permutation we computed tells us how to interpret the - * routing onto the fabric we discovered. We do this working backward from the last - * Node discovered to the BSP, writing the routing tables as we go. - * - * @param[in,out] State the discovered fabric, degree matrix, permutation - * - */ -VOID -LookupComputeAndLoadRoutingTables ( - IN OUT STATE_DATA *State - ) -{ - TOPOLOGY_CONTEXT TopologyContextHandle; - UINT8 *Selected; - UINT8 Size; - UINT8 PairCounter; - UINT8 ReqTargetLink; - UINT8 RspTargetLink; - UINT8 ReqTargetNode; - UINT8 RspTargetNode; - UINT8 AbstractBcTargetNodes; - UINT32 BcTargetLinks; - UINT8 NodeCounter; - UINT8 NodeBeingRouted; - UINT8 NodeRoutedTo; - UINT8 BroadcastSourceNode; - - Size = State->NodesDiscovered + 1; - BeginTopologies (&TopologyContextHandle, &Selected, State); - while (Selected != NULL) { - if (GraphHowManyNodes (Selected) == Size) { - // Build Degree vector and Adjacency Matrix for this entry - for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) { - State->Fabric->DbDegree[NodeCounter] = 0; - for (PairCounter = 0; PairCounter < Size; PairCounter++) { - if (GraphIsAdjacent (Selected, NodeCounter, PairCounter)) { - State->Fabric->DbMatrix[NodeCounter][PairCounter] = TRUE; - State->Fabric->DbDegree[NodeCounter]++; - } else { - State->Fabric->DbMatrix[NodeCounter][PairCounter] = FALSE; - } - } - } - - if (IsIsomorphic (0, State)) { - break; // A matching topology was found - } - } - GetNextTopology (&TopologyContextHandle, &Selected); - } - - if (Selected != NULL) { - // Compute the reverse Permutation - for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) { - State->Fabric->ReversePerm[State->Fabric->Perm[NodeCounter]] = NodeCounter; - } - - // Start with the last discovered Node, and move towards the BSP - for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) { - NodeBeingRouted = ((Size - 1) - NodeCounter); - for (NodeRoutedTo = 0; NodeRoutedTo < Size; NodeRoutedTo++) { - BcTargetLinks = 0; - AbstractBcTargetNodes = GraphGetBc (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]); - - for (BroadcastSourceNode = 0; BroadcastSourceNode < MAX_NODES; BroadcastSourceNode++) { - if ((AbstractBcTargetNodes & ((UINT32)1 << BroadcastSourceNode)) != 0) { - // Accepting broadcast from yourself is handled in Nb, so in the topology graph it is an error. - ASSERT (NodeBeingRouted != State->Fabric->ReversePerm[BroadcastSourceNode]); - BcTargetLinks |= (UINT32)1 << FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[BroadcastSourceNode], State); - } - } - - if (NodeBeingRouted == NodeRoutedTo) { - ReqTargetLink = ROUTE_TO_SELF; - RspTargetLink = ROUTE_TO_SELF; - } else { - ReqTargetNode = GraphGetReq (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]); - ReqTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[ReqTargetNode], State); - - RspTargetNode = GraphGetRsp (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]); - RspTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[RspTargetNode], State); - } - State->Nb->WriteFullRoutingTable (NodeBeingRouted, NodeRoutedTo, ReqTargetLink, RspTargetLink, BcTargetLinks, State->Nb); - } - // Clean up discovery 'footprint' that otherwise remains in the routing table. It didn't hurt - // anything, but might cause confusion during debug and validation. Do this by setting the - // route back to all self routes. Since it's the Node that would be one more than actually installed, - // this only applies if less than MaxNodes were found. - // - if (Size < MAX_NODES) { - State->Nb->WriteFullRoutingTable (NodeBeingRouted, Size, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb); - } - } - } else { - // - // No Matching Topology was found - // Error Strategy: - // Auto recovery doesn't seem likely, Force boot as 1P. - // For reporting, logging, provide number of Nodes - // If not implemented or returns, boot as BSP uniprocessor. - // - // This can be caused by not supplying an additional topology list, if your board is not one of the built-in topologies. - // - NotifyErrorCohNoTopology (State->NodesDiscovered, State); - IDS_ERROR_TRAP; - // Force 1P - State->NodesDiscovered = 0; - State->TotalLinks = 0; - State->Nb->EnableRoutingTables (0, State->Nb); - State->HtInterface->CleanMapsAfterError (State); - } - // Save the topology pointer, or NULL, for other features - State->Fabric->MatchedTopology = Selected; - IDS_HDT_CONSOLE ( - HT_TRACE, - "System routed as %s.\n", - ((TopologyContextHandle.IsCustomList) ? - "custom topology" : - (((Selected == amdHtTopologySingleNode) || (Selected == NULL)) ? - "single node" : - ((Selected == amdHtTopologyDualNode) ? - "dual node" : - ((Selected == amdHtTopologyFourSquare) ? - "four node box" : - ((Selected == amdHtTopologyFourKite) ? - "four node kite" : - ((Selected == amdHtTopologyFourFully) ? - "fully connected four-way" : - ((Selected == amdHtTopologyEightDoubloon) ? - "MCM max performance" : - ((Selected == amdHtTopologyEightTwinFullyFourWays) ? - "MCM max I/O" : - "AMD builtin topology")))))))) - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Make a Hop Count Table for the installed topology. - * - * @HtFeatMethod{::F_MAKE_HOP_COUNT_TABLE} - * - * For SLIT, create a node x node matrix with the number of hops. We can do this - * using the topology and the permutation, counting the nodes visited in the routes between - * nodes. - * - * @param[in,out] State access topology, permutation, update hop table - * - */ -VOID -MakeHopCountTable ( - IN OUT STATE_DATA *State - ) -{ - UINT8 Origin; - UINT8 Target; - UINT8 Current; - UINT8 Hops; - UINT8 Size; - - ASSERT (State->Fabric != NULL); - if (State->HopCountTable != NULL) { - if (State->Fabric->MatchedTopology != NULL) { - Size = GraphHowManyNodes (State->Fabric->MatchedTopology); - State->HopCountTable->Size = Size; - // - // For each node, targeting each node, follow the request path through the database graph, - // counting the number of edges. - // - for (Origin = 0; Origin < Size; Origin++) { - for (Target = 0; Target < Size; Target++) { - // If both nodes are the same the answer will be zero - Hops = 0; - // Current starts as the database node corresponding to system node Origin. - Current = State->Fabric->Perm[Origin]; - // Stop if Current is the database node corresponding to system node Target - while (Current != State->Fabric->Perm[Target]) { - // This is a hop, so count it. Move Current to the next intermediate database node. - Hops++; - Current = GraphGetReq (State->Fabric->MatchedTopology, Current, State->Fabric->Perm[Target]); - } - // Put the hop count in the table. - State->HopCountTable->Hops[ ((Origin * Size) + Target)] = Hops; - } - } - } - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.h deleted file mode 100644 index f672cc4c83..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatRouting.h +++ /dev/null @@ -1,90 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Routing Feature Interface. - * - * Interfaces to routing and isomorphism routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _HT_FEAT_ROUTING_H_ -#define _HT_FEAT_ROUTING_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * Using the description of the fabric topology we discovered, try to find a match - * among the supported topologies. - * - */ -VOID -LookupComputeAndLoadRoutingTables ( - IN OUT STATE_DATA *State - ); - -/** - * Make a Hop Count Table for the installed topology. - * - */ -VOID -MakeHopCountTable ( - IN OUT STATE_DATA *State - ); - -#endif /* _HT_FEAT_ROUTING_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSets.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSets.c deleted file mode 100644 index 112dc486a3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSets.c +++ /dev/null @@ -1,135 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HyperTransport feature sets initializers. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionsHt.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "CommonReturns.h" -#include "htFeatDynamicDiscovery.h" -#include "htFeatRouting.h" -#include "htFeatNoncoherent.h" -#include "htFeatOptimization.h" -#include "htFeatGanging.h" -#include "htFeatSublinks.h" -#include "htFeatTrafficDistribution.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FEATURES_HTFEATSETS_FILECODE -extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration; - -/** - * Initializer for the default feature set implementation, - * full features. - */ -CONST HT_FEATURES ROMDATA HtFeaturesDefault = -{ - CoherentDiscovery, - LookupComputeAndLoadRoutingTables, - MakeHopCountTable, - ProcessLink, - GatherLinkData, - SelectOptimalWidthAndFrequency, - RegangLinks, - SubLinkRatioFixup, - IsCoherentRetryFixup, - SetLinkData, - TrafficDistribution, - SetHtControlRegisterBits, - ConvertWidthToBits -}; - -/** -* Initializer for the coherent HT feature set implementation -* (IO is using PCIe). -*/ -CONST HT_FEATURES ROMDATA HtFeaturesCoherentOnly = -{ - CoherentDiscovery, - LookupComputeAndLoadRoutingTables, - MakeHopCountTable, - (PF_PROCESS_LINK)CommonVoid, - GatherLinkData, - SelectOptimalWidthAndFrequency, - RegangLinks, - SubLinkRatioFixup, - IsCoherentRetryFixup, - SetLinkData, - TrafficDistribution, - SetHtControlRegisterBits, - ConvertWidthToBits -}; - -/** - * Initializer for the non-coherent only build option. - */ -CONST HT_FEATURES ROMDATA HtFeaturesNonCoherentOnly = -{ - (PF_COHERENT_DISCOVERY)CommonVoid, - (PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid, - (PF_MAKE_HOP_COUNT_TABLE)CommonVoid, - ProcessLink, - GatherLinkData, - SelectOptimalWidthAndFrequency, - (PF_REGANG_LINKS)CommonVoid, - (PF_SUBLINK_RATIO_FIXUP)CommonVoid, - (PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse, - SetLinkData, - (PF_TRAFFIC_DISTRIBUTION)CommonVoid, - SetHtControlRegisterBits, - ConvertWidthToBits -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.c deleted file mode 100644 index 194861a055..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.c +++ /dev/null @@ -1,232 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * SubLink management Routines. - * - * Contains routines for subLink frequency ratios. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Topology.h" -#include "htFeat.h" -#include "IdsHt.h" -#include "htFeatSublinks.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -typedef struct { - UINT8 HiFreq; - UINT8 LoFreq; -} VALID_RATIO_ITEM; - -STATIC CONST VALID_RATIO_ITEM ROMDATA ValidRatioList[] = -{ - {HT_FREQUENCY_3200M, HT_FREQUENCY_1600M}, // 3200MHz / 1600MHz 2:1 - {HT_FREQUENCY_3200M, HT_FREQUENCY_800M}, // 3200MHz / 800MHz 4:1 - {HT_FREQUENCY_3200M, HT_FREQUENCY_400M}, // 3200MHz / 400MHz 8:1 - {HT_FREQUENCY_2800M, HT_FREQUENCY_1400M}, // 2800MHz / 1400MHz 2:1 - {HT_FREQUENCY_2400M, HT_FREQUENCY_1200M}, // 2400MHz / 1200MHz 2:1 - {HT_FREQUENCY_2400M, HT_FREQUENCY_600M}, // 2400MHz / 600MHz 4:1 - {HT_FREQUENCY_2400M, HT_FREQUENCY_400M}, // 2400MHz / 400MHz 6:1 - {HT_FREQUENCY_2000M, HT_FREQUENCY_1000M}, // 2000MHz / 1000MHz 2:1 - {HT_FREQUENCY_1600M, HT_FREQUENCY_800M}, // 1600MHz / 800MHz 2:1 - {HT_FREQUENCY_1600M, HT_FREQUENCY_400M}, // 1600MHz / 400MHz 4:1 - {HT_FREQUENCY_1600M, HT_FREQUENCY_200M}, // 1600MHz / 200Mhz 8:1 - {HT_FREQUENCY_1200M, HT_FREQUENCY_600M}, // 1200MHz / 600MHz 2:1 - {HT_FREQUENCY_1200M, HT_FREQUENCY_200M}, // 1200MHz / 200MHz 6:1 - {HT_FREQUENCY_800M, HT_FREQUENCY_400M}, // 800MHz / 400MHz 2:1 - {HT_FREQUENCY_800M, HT_FREQUENCY_200M}, // 800MHz / 200MHz 4:1 - {HT_FREQUENCY_400M, HT_FREQUENCY_200M} // 400MHz / 200MHz 2:1 -}; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** Link Optimization *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Iterate through all Links, checking the frequency of each subLink pair. - * - * @HtFeatMethod{::F_SUBLINK_RATIO_FIXUP} - * - * Make the adjustment to the port list data so that the frequencies - * are at a valid ratio, reducing frequency as needed to achieve - * this. (All Links support the minimum 200 MHz frequency.) Repeat - * the above until no adjustments are needed. - * @note no hardware state changes in this routine. - * - * @param[in,out] State Link state and port list - * - */ -VOID -SubLinkRatioFixup ( - IN OUT STATE_DATA *State - ) -{ - UINT8 i; - UINT8 j; - UINT8 ValidRatioItem; - BOOLEAN Changes; - BOOLEAN Downgrade; - UINT8 HiIndex; - UINT8 HiFreq; - UINT8 LoFreq; - - UINT32 Temp; - - do { - Changes = FALSE; - for (i = 0; i < State->TotalLinks*2; i++) { - // Must be a CPU Link - if ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) { - continue; - } - // Only look for subLink1's - if ((*State->PortList)[i].Link < 4) { - continue; - } - - for (j = 0; j < State->TotalLinks*2; j++) { - // Step 1. Find the matching subLink0 - if ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) { - continue; - } - if ((*State->PortList)[j].NodeID != (*State->PortList)[i].NodeID) { - continue; - } - if ((*State->PortList)[j].Link != ((*State->PortList)[i].Link & 0x03)) { - continue; - } - - // Step 2. Check for an illegal frequency ratio - if ((*State->PortList)[i].SelFrequency >= (*State->PortList)[j].SelFrequency) { - HiIndex = i; - HiFreq = (*State->PortList)[i].SelFrequency; - LoFreq = (*State->PortList)[j].SelFrequency; - } else { - HiIndex = j; - HiFreq = (*State->PortList)[j].SelFrequency; - LoFreq = (*State->PortList)[i].SelFrequency; - } - - // The frequencies are 1:1, no need to do anything - if (HiFreq == LoFreq) { - break; - } - - Downgrade = TRUE; - - for (ValidRatioItem = 0; ValidRatioItem < (sizeof (ValidRatioList) / sizeof (VALID_RATIO_ITEM)); ValidRatioItem++) { - if ((HiFreq == ValidRatioList[ValidRatioItem].HiFreq) && - (LoFreq == ValidRatioList[ValidRatioItem].LoFreq)) { - Downgrade = FALSE; - break; - } - } - - // Step 3. Downgrade the higher of the two frequencies, and set Changes to FALSE - if (Downgrade) { - // Although the problem was with the port specified by hiIndex, we need to - // Downgrade both ends of the Link. - HiIndex = HiIndex & 0xFE; // Select the 'upstream' (i.e. even) port - - Temp = (*State->PortList)[HiIndex].CompositeFrequencyCap; - - // Remove HiFreq from the list of valid frequencies - Temp = Temp & ~((UINT32)1 << HiFreq); - ASSERT (Temp != 0); - (*State->PortList)[HiIndex].CompositeFrequencyCap = (UINT32)Temp; - (*State->PortList)[HiIndex + 1].CompositeFrequencyCap = (UINT32)Temp; - - HiFreq = LibAmdBitScanReverse (Temp); - - (*State->PortList)[HiIndex].SelFrequency = HiFreq; - (*State->PortList)[HiIndex + 1].SelFrequency = HiFreq; - - Changes = TRUE; - } - } - } - } while (Changes); // Repeat until a valid configuration is reached -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.h deleted file mode 100644 index d8c1d9d00b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatSublinks.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * SubLink Interface. - * - * Contains interface to subLink management feature, for unganged subLinks. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _HT_FEAT_SUBLINKS_H_ -#define _HT_FEAT_SUBLINKS_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * Iterate through all Links, checking the frequency of each subLink pair. - * - */ -VOID -SubLinkRatioFixup ( - IN OUT STATE_DATA *State - ); - -#endif /* _HT_FEAT_SUBLINKS_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.c deleted file mode 100644 index 5e9fe0e7ba..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.c +++ /dev/null @@ -1,420 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Traffic Distribution Routines. - * - * Contains routines for traffic distribution - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "htNotify.h" -#include "htFeatTrafficDistribution.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/// Enum for the possible link connection status -typedef enum { - Unconnected = 0, ///< Nodes have not connected link. - UngangedLink, ///< Nodes are connected with one unganged link. - Redundant, ///< Nodes are connected with multi-unganged link. - GangedLink, ///< Nodes are connected with one or mutiple ganged link. - MaxLink ///< Max links status. -} LINK_STATUS; - -/// Local port connection state data structure -typedef struct { - LINK_STATUS ConnectionState; /**< The link connection state. */ - UINT8 BigLinkPort; /**< The Port number for ganged Link */ -} PORT_CONNECTION_STATE; - -/// Local ganged link for Victim Distribution data structure -typedef struct { -UINT8 NodeA; ///< Source Node from Node A To Node B and DstNode from Node A To Node B. -UINT8 NodeB; ///< Source Node from Node B To Node A and DstNode from Node A To Node B. -UINT8 VictimedLinkFromNodeAToNodeB; ///< Victimed Link from Node A To Node B. -UINT8 VictimedLinkFromNodeBToNodeA; ///< Victimed Link from Node B To Node A. -} VICTIM_ROUTED_LINK; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Identify Links which can have traffic distribution. - * - * @HtFeatMethod{::F_TRAFFIC_DISTRIBUTION} - * - * If there are redundant links between any nodes, traffic distribution allows the - * redundant links to be used to improve performance. - * - * There are three types of traffic distribution. Their use is mutually exclusive, all - * can not be used at once. - * - * Coherent Traffic Distribution is for systems of exactly two nodes only. All links must - * be symmetrical (the same width). As many links as are connected can be distributed over. - * - * Victim Distribution is a way to direct victim traffic on to ganged links and away from unganged links - * as a way to reduce unganged link congestion for a system only if 2 processor (4 node) G34 system. - * A node can enables victim distribution mode only if the node connects to another node directly with - * only 1 unganged link hop and indirectly through 2 ganged link hops. - * - * Link Pair Traffic Distribution works with redundant pairs of links between any two nodes, - * it does not matter how many nodes are in the system or how many have a redundant link pair. - * A node can have redundant link pairs with more than one other node. - * The link pair can be asymmetric, the largest link must be used as the master. However, - * between any pair of nodes there is only one pair of redundant links, and there is a limit - * to the total number of pairs each node can have. So not all links will necessarily be - * made usable. - * - * @param[in] State port list data - */ -VOID -TrafficDistribution ( - IN STATE_DATA *State - ) -{ - UINT32 Links01; - UINT32 Links10; - UINT32 LinksAB; - UINT32 LinksBA; - UINT8 LinkCount; - UINT8 UngandLinkCount; - UINT8 VictimedRouteCount; - UINT8 i; - UINT8 LastLink; - BOOLEAN IsAsymmetric; - BOOLEAN IsVictimedRouteFound; - UINT8 RedundantLinkCount[MAX_NODES][MAX_NODES]; - UINT8 MasterLinkPort[MAX_NODES][MAX_NODES]; - UINT8 AlternateLinkPort[MAX_NODES][MAX_NODES]; - UINT8 NodeA; - UINT8 NodeB; - UINT8 PairCount; - VICTIM_ROUTED_LINK VictimRoutedLink[MAX_NODES]; - PORT_CONNECTION_STATE GangedLinkPort[MAX_NODES][MAX_NODES]; - - LastLink = 0xFF; - IsAsymmetric = FALSE; - - // Traffic Distribution is only used when there are exactly two Nodes in the system - // and when all the links are symmetric, same width. - if ((State->NodesDiscovered + 1) == 2) { - Links01 = 0; - Links10 = 0; - LinkCount = 0; - for (i = 0; i < (State->TotalLinks * 2); i += 2) { - if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && - ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) { - if ((LastLink != 0xFF) && - ((*State->PortList)[i].SelWidthOut != (*State->PortList)[LastLink].SelWidthOut) && - ((*State->PortList)[i + 1].SelWidthOut != (*State->PortList)[LastLink + 1].SelWidthOut)) { - IsAsymmetric = TRUE; - break; - } - Links01 |= (UINT32)1 << (*State->PortList)[i].Link; - Links10 |= (UINT32)1 << (*State->PortList)[i + 1].Link; - LinkCount++; - LastLink = i; - } - } - ASSERT (LinkCount != 0); - // Don't setup Traffic Distribution if only one Link is being used or there were asymmetric widths - if ((LinkCount != 1) && !IsAsymmetric) { - IDS_HDT_CONSOLE (HT_TRACE, "Applying coherent traffic distribution.\n"); - State->Nb->WriteTrafficDistribution (Links01, Links10, State->Nb); - // If we did Traffic Distribution, we must not do Link Pair, so get out of here. - return; - } - } - - // Victim Distribution is only used when there are exactly two processor (4 node) system - // and the node connects to another node directly with only 1 unganged link hop and indirectly - // through 2 ganged link hops. - if ((State->NodesDiscovered + 1) == 4) { - UngandLinkCount = 0; - - // Initialize the ganged link state data structures - for (NodeA = 0; NodeA < MAX_NODES; NodeA++) { - for (NodeB = 0; NodeB < MAX_NODES; NodeB++) { - GangedLinkPort[NodeA][NodeB].ConnectionState = 0; - GangedLinkPort[NodeA][NodeB].BigLinkPort = 0; - } - } - - for (i = 0; i < (State->TotalLinks * 2); i += 2) { - if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && - ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) { - NodeA = (*State->PortList)[i].NodeID; - NodeB = (*State->PortList)[i + 1].NodeID; - if ((((*State->PortList)[i].SelRegang == TRUE) && - ((*State->PortList)[i].PrvWidthOutCap == HT_WIDTH_16_BITS)) || - ((*State->PortList)[i].SelWidthOut == HT_WIDTH_16_BITS)) { - if (GangedLinkPort[NodeA][NodeB].ConnectionState <= Redundant) { - // Record it if it is the first ganged link connecting two nodes. - GangedLinkPort[NodeA][NodeB].BigLinkPort = (*State->PortList)[i].Link; - GangedLinkPort[NodeB][NodeA].BigLinkPort = (*State->PortList)[i + 1].Link; - GangedLinkPort[NodeA][NodeB].ConnectionState = GangedLink; - GangedLinkPort[NodeB][NodeA].ConnectionState = GangedLink; - } - } else { - if (GangedLinkPort[NodeA][NodeB].ConnectionState == Unconnected) { - // Save it if it is firstly unganged link and also does no exist ganged link between node A and node B. - GangedLinkPort[NodeA][NodeB].ConnectionState = UngangedLink; - GangedLinkPort[NodeB][NodeA].ConnectionState = UngangedLink; - - UngandLinkCount++; - } else if (GangedLinkPort[NodeA][NodeB].ConnectionState == UngangedLink) { - // Ignore it if there are multi-unganged links between node A and node B. - GangedLinkPort[NodeA][NodeB].ConnectionState = Redundant; - GangedLinkPort[NodeB][NodeA].ConnectionState = Redundant; - - // Adjust the count because had it recorded once. - UngandLinkCount--; - } - } - } - } - - if (UngandLinkCount != 0) { - VictimedRouteCount = 0; - - // Check Link by Link if one unganged link can direct victim traffic on to indirectly 2 ganged link hops - for (NodeA = 0; NodeA <= (State->NodesDiscovered); NodeA++) { - for (NodeB = NodeA +1; NodeB <= (State->NodesDiscovered); NodeB++) { - if (GangedLinkPort[NodeA][NodeB].ConnectionState == UngangedLink) { - // This is unganged link connecting two nodes - IsVictimedRouteFound = FALSE; - - for (i = 0; i <= (State->NodesDiscovered); i++) { - if ((i != NodeA) && (i != NodeB) && (GangedLinkPort[NodeA][i].ConnectionState == GangedLink)) { - // This is the first ganged link hop to Destined Node - VictimRoutedLink[VictimedRouteCount].NodeA = NodeA; - VictimRoutedLink[VictimedRouteCount].VictimedLinkFromNodeAToNodeB = GangedLinkPort[NodeA][i].BigLinkPort; - if (GangedLinkPort[i][NodeB].ConnectionState == GangedLink) { - // This is the second ganged link hop to Destined Node - // Save the Destined Node and the Reversed Destination Link - VictimRoutedLink[VictimedRouteCount].NodeB = NodeB; - VictimRoutedLink[VictimedRouteCount].VictimedLinkFromNodeBToNodeA = GangedLinkPort[NodeB][i].BigLinkPort; - if (!IsVictimedRouteFound) { - VictimedRouteCount++; - - // This is first victimed route where there are indirectly 2 ganged link hops to Destined Node - IsVictimedRouteFound = TRUE; - } else { - // This is second victimed route, so we need to replace to the new Reversed Destination Link - VictimRoutedLink[VictimedRouteCount - 1].VictimedLinkFromNodeBToNodeA = GangedLinkPort[NodeB][i].BigLinkPort; - } - } - } - } - } - } - } - - // Setup Victim Distribution Mode - if (VictimedRouteCount != 0) { - IDS_HDT_CONSOLE (HT_TRACE, "Applying coherent Victim distribution.\n"); - LinksAB = 0; - LinksBA = 0; - for (i = 0; i < VictimedRouteCount; i++) { - LinksAB = (UINT32)1 << VictimRoutedLink[i].VictimedLinkFromNodeAToNodeB; - LinksBA = (UINT32)1 << VictimRoutedLink[i].VictimedLinkFromNodeBToNodeA; - State->Nb->WriteVictimDistribution ( - VictimRoutedLink[i].NodeA, - VictimRoutedLink[i].NodeB, - LinksAB, - LinksBA, - State->Nb - ); - } - // If we did Victim Distribution, we must not do Link Pair when there are more than two nodes, so exit here. - return; - } - } - } - - // Either there are more than two nodes, Asymmetric links, or no redundant links. - // See if we can use Link Pair Traffic Distribution - LibAmdMemFill (&RedundantLinkCount, 0, (MAX_NODES * MAX_NODES), State->ConfigHandle); - for (i = 0; i < (State->TotalLinks * 2); i += 2) { - if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && - ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) { - NodeA = (*State->PortList)[i].NodeID; - NodeB = (*State->PortList)[i + 1].NodeID; - if (RedundantLinkCount[NodeA][NodeB] == 0) { - // This is the first link connecting two nodes - ASSERT (RedundantLinkCount[NodeB][NodeA] == 0); - MasterLinkPort[NodeA][NodeB] = i; - MasterLinkPort[NodeB][NodeA] = i + 1; - } else { - // This is a redundant link. If it is larger than the current master link, - // make it the new master link. - // - if (((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) && - ((*State->PortList)[MasterLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) { - // Make the old master link the alternate, we don't need to check, it is bigger. - AlternateLinkPort[NodeA][NodeB] = MasterLinkPort[NodeA][NodeB]; - AlternateLinkPort[NodeB][NodeA] = MasterLinkPort[NodeB][NodeA]; - MasterLinkPort[NodeA][NodeB] = i; - MasterLinkPort[NodeB][NodeA] = i + 1; - } else { - // Since the new link isn't bigger than the Master, check if it is bigger than the alternate, - // if we have an alternate. If we don't have an alternate yet, make this link the alternate. - if (RedundantLinkCount[NodeA][NodeB] == 1) { - AlternateLinkPort[NodeA][NodeB] = i; - AlternateLinkPort[NodeB][NodeA] = i + 1; - } else { - if (((*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) && - ((*State->PortList)[AlternateLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) { - // Warning: the alternate link is an unusable redundant link - // Then make the new link the alternate link. - NotifyWarningOptUnusedLinks ( - NodeA, - (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link, - NodeB, - (*State->PortList)[AlternateLinkPort[NodeB][NodeA]].Link, - State - ); - ASSERT (RedundantLinkCount[NodeB][NodeA] > 1); - AlternateLinkPort[NodeA][NodeB] = i; - AlternateLinkPort[NodeB][NodeA] = i + 1; - } else { - // Warning the current link is an unusable redundant link - NotifyWarningOptUnusedLinks (NodeA, (*State->PortList)[i].Link, NodeB, (*State->PortList)[i].Link, State); - } - } - } - } - RedundantLinkCount[NodeA][NodeB]++; - RedundantLinkCount[NodeB][NodeA]++; - } - } - // If we found any, now apply up to 4 per node - for (NodeA = 0; NodeA < MAX_NODES; NodeA++) { - PairCount = 0; - for (NodeB = 0; NodeB < MAX_NODES; NodeB++) { - if (RedundantLinkCount[NodeA][NodeB] > 1) { - // Then there is a pair of links (at least, but we only care about the pair not the extras) - if (PairCount < MAX_LINK_PAIRS) { - // Program it - if ((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut - != (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut) { - IsAsymmetric = TRUE; - } else { - IsAsymmetric = FALSE; - } - State->Nb->WriteLinkPairDistribution ( - NodeA, - NodeB, - PairCount, - IsAsymmetric, - (*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link, - (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link, - State->Nb - ); - PairCount++; - } else { - // Warning: More link pairs than can be distributed - NotifyWarningOptLinkPairExceed ( - NodeA, NodeB, - (*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link, - (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link, - State); - // Disable the link pair from the other node, the analysis loop made sure there - // can only be a single link pair between a pair of nodes. - RedundantLinkCount[NodeB][NodeA] = 1; - } - } - } - IDS_HDT_CONSOLE ( - HT_TRACE, - ((PairCount != 0) ? - "Node %d applying %d link pair distributions.\n" : - ""), - NodeA, - PairCount - ); - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.h b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.h deleted file mode 100644 index c1c02295b6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htFeatTrafficDistribution.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Traffic Distribution Interface. - * - * Interface to traffic distribution feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ -#define _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -/** - * Identify Links which can have traffic distribution. - * - */ -VOID -TrafficDistribution ( - IN STATE_DATA *State - ); - -#endif /* _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htIds.c deleted file mode 100644 index 05028dbcc3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Features/htIds.c +++ /dev/null @@ -1,150 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD IDS HyperTransport Implementation. - * - * Contains AMD AGESA Integrated Debug HT related support. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "IdsHt.h" -#include "htInterface.h" -#include "htInterfaceGeneral.h" -#include "htNb.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_HT_FEATURES_HTIDS_FILECODE - - -/*-------------------------------------------------------------------------------------*/ -/** - * Apply an IDS port override to the desired HT link. - * - * The IDS port override allows absolute control of a link's frequency and width, such as - * would be used for board characterization and test. The IDS backend code is responsible - * for handling the NV items and building them into a port override list. Here we search - * that list for any overrides which apply, and update the data used by the HT feature code. - * - * @param[in] IsSourcePort Since we handle both ports on a match, only do that if TRUE. - * @param[in,out] Port0 The PORTLIST item for the first endpoint of a link. - * @param[in,out] Port1 The PORTLIST item for the second endpoint of a link. - * @param[in,out] PortOverrideList IN: A pointer to the port override list or NULL, - * OUT: A pointer to the port override list. - * @param[in] State access to ht interface and nb support methods. - * - */ -VOID -HtIdsGetPortOverride ( - IN BOOLEAN IsSourcePort, - IN OUT PORT_DESCRIPTOR *Port0, - IN OUT PORT_DESCRIPTOR *Port1, - IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList, - IN STATE_DATA *State - ) -{ - LOCATE_HEAP_PTR LocHeapParams; - UINT8 SocketA; - UINT8 SocketB; - UINT8 PackageLinkA; - UINT8 PackageLinkB; - HTIDS_PORT_OVERRIDE_LIST p; - - if (IsSourcePort) { - ASSERT (PortOverrideList != NULL); - // The caller can cache the override list by providing the pointer (to the heap buffer). - // If the pointer to the port override list is null, then check if it is on the heap, - // and update the caller's pointer so it is cached. - // If the buffer is not in heap, call the IDS backend to get the NV data (which is likely also - // in heap). - if (*PortOverrideList == NULL) { - // locate the table in heap - LocHeapParams.BufferHandle = IDS_HT_DATA_HANDLE; - if (HeapLocateBuffer (&LocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) { - *PortOverrideList = (HTIDS_PORT_OVERRIDE_LIST)LocHeapParams.BufferPtr; - } else { - // Ask IDS backend code for the list - IDS_OPTION_HOOK (IDS_HT_CONTROL, PortOverrideList, State->ConfigHandle); - } - } - ASSERT (*PortOverrideList != NULL); - - // Search the port override list to see if there is an override that applies to this link. - // The match criteria are if either endpoint of the current port list item matches - // port override. - p = *PortOverrideList; - SocketA = State->HtInterface->GetSocketFromMap (Port0->NodeID, State); - PackageLinkA = State->Nb->GetPackageLink (Port0->NodeID, Port0->Link, State->Nb); - SocketB = State->HtInterface->GetSocketFromMap (Port1->NodeID, State); - PackageLinkB = State->Nb->GetPackageLink (Port1->NodeID, Port1->Link, State->Nb); - - while ((p != NULL) && (p->Socket != HT_LIST_TERMINAL)) { - if ((((p->Socket == SocketA) || (p->Socket == HT_LIST_MATCH_ANY)) && - ((p->Link == PackageLinkA) || ((p->Link == HT_LIST_MATCH_ANY) && - (!IsPackageLinkInternal (PackageLinkA))) || ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA))))) || - (((p->Socket == SocketB) || (p->Socket == HT_LIST_MATCH_ANY)) && - ((p->Link == PackageLinkB) || ((p->Link == HT_LIST_MATCH_ANY) && - (!IsPackageLinkInternal (PackageLinkA))) || ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB)))))) - { - // Found a match, update width and frequency of both endpoints. - if (p->WidthIn != HT_LIST_TERMINAL) { - Port0->SelWidthIn = p->WidthIn; - Port1->SelWidthOut = p->WidthIn; - } - if (p->WidthOut != HT_LIST_TERMINAL) { - Port0->SelWidthOut = p->WidthOut; - Port1->SelWidthIn = p->WidthOut; - } - if (p->Frequency != HT_LIST_TERMINAL) { - Port0->SelFrequency = p->Frequency; - Port1->SelFrequency = p->Frequency; - } - break; - } else { - p++; - } - } - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/HT/Makefile.inc deleted file mode 100644 index f54568a1f1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -libagesa-y += htFeat.c -libagesa-y += htInterface.c -libagesa-y += htInterfaceCoherent.c -libagesa-y += htInterfaceGeneral.c -libagesa-y += htInterfaceNonCoherent.c -libagesa-y += htMain.c -libagesa-y += htNb.c -libagesa-y += htNotify.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/Makefile.inc deleted file mode 100644 index 17944aa83e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -libagesa-y += htNbCoherent.c -libagesa-y += htNbNonCoherent.c -libagesa-y += htNbOptimization.c -libagesa-y += htNbUtilities.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.c b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.c deleted file mode 100644 index 4eca9e98d8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.c +++ /dev/null @@ -1,492 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Coherent Feature Northbridge routines. - * - * Provide access to hardware for routing, coherent discovery. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbCoherent.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Establish a Temporary route from one Node to another. - * - * @HtNbMethod{::F_WRITE_ROUTING_TABLE} - * - * This routine will modify the routing tables on the - * SourceNode to cause it to route both request and response traffic to the - * targetNode through the specified Link. - * - * @note: This routine is to be used for early discovery and initialization. The - * final routing tables must be loaded some other way because this - * routine does not address the issue of probes, or independent request - * response paths. - * - * @param[in] Node the Node that will have it's routing tables modified. - * @param[in] Target For routing to Node target - * @param[in] Link Link from Node to target - * @param[in] Nb this northbridge - */ -VOID -WriteRoutingTable ( - IN UINT8 Node, - IN UINT8 Target, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 Temp; - - ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES) && (Link < Nb->MaxLinks)); - Temp = (Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (Link + 1); - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_ROUTE0_0X40 + (Target * 4)); - LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Modifies the NodeID register on the target Node - * - * @HtNbMethod{::F_WRITE_NODEID} - * - * @param[in] Node the Node that will have its NodeID altered. - * @param[in] NodeID the new value for NodeID - * @param[in] Nb this northbridge - */ -VOID -WriteNodeID ( - IN UINT8 Node, - IN UINT8 NodeID, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 Temp; - Temp = NodeID; - ASSERT ((Node < MAX_NODES) && (NodeID < MAX_NODES)); - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_NODE_ID_0X60); - LibAmdPciWriteBits (Reg, 2, 0, &Temp, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read the Default Link - * - * @HtNbMethod{::F_READ_DEFAULT_LINK} - * - * Read the DefLnk (the source Link of the current packet) from Node. Since this code - * is running on the BSP, this should be the Link pointing back towards the BSP. - * - * @param[in] Node the Node that will have its NodeID altered. - * @param[in] Nb this northbridge - * - * @return The HyperTransport Link where the request to - * read the default Link came from. - */ -UINT8 -ReadDefaultLink ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 DefaultLink; - PCI_ADDR Reg; - UINT32 Temp; - - DefaultLink = 0; - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_LINK_INIT_CONTROL_0X6C); - - ASSERT ((Node < MAX_NODES)); - LibAmdPciReadBits (Reg, 3, 2, &DefaultLink, Nb->ConfigHandle); - LibAmdPciReadBits (Reg, 8, 8, &Temp, Nb->ConfigHandle); - DefaultLink |= (Temp << 2); - return (UINT8)DefaultLink; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Turns routing tables on for a given Node - * - * @HtNbMethod{::F_ENABLE_ROUTING_TABLES} - * - * @param[in] Node the Node that will have it's routing tables enabled - * @param[in] Nb this northbridge - */ -VOID -EnableRoutingTables ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 Temp; - Temp = 0; - ASSERT ((Node < MAX_NODES)); - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_LINK_INIT_CONTROL_0X6C); - LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Turns routing tables off for a given Node - * - * @HtNbMethod{::F_DISABLE_ROUTING_TABLES} - * - * @param[in] Node the Node that will have it's routing tables disabled - * @param[in] Nb this northbridge - */ -VOID -DisableRoutingTables ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 Temp; - Temp = 1; - ASSERT ((Node < MAX_NODES)); - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_LINK_INIT_CONTROL_0X6C); - LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Verify that the Link is coherent, connected, and ready - * - * @HtNbMethod{::F_VERIFY_LINK_IS_COHERENT} - * - * @param[in] Node the Node that will be examined - * @param[in] Link the Link on that Node to examine - * @param[in] Nb this northbridge - * - * @retval TRUE The Link has the following status - * - LinkCon=1, Link is connected - * - InitComplete=1, Link initialization is complete - * - NC=0, Link is coherent - * - UniP-cLDT=0, Link is not Uniprocessor cLDT - * - LinkConPend=0 Link connection is not pending - * @retval FALSE The Link has some other status -*/ -BOOLEAN -VerifyLinkIsCoherent ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 LinkType; - PCI_ADDR LinkBase; - - ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks)); - - LinkBase = Nb->MakeLinkBase (Node, Link, Nb); - - // FN0_98/A4/C4 = LDT Type Register - LinkBase.Address.Register += HTHOST_LINK_TYPE_REG; - LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle); - - // Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 - return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read the token stored in the scratchpad register field. - * - * @HtNbMethod{::F_READ_TOKEN} - * - * Use the CPU core count as a scratch pad. - * - * @note The location used to store the token is arbitrary. The only requirement is - * that the location warm resets to zero, and that using it will have no ill-effects - * during HyperTransport initialization. - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - * - * @return the Token read from the Node - */ -UINT8 -ReadToken ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR Reg; - - ASSERT ((Node < MAX_NODES)); - // Use CpuCnt as a scratch register - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_NODE_ID_0X60); - LibAmdPciReadBits (Reg, 19, 16, &Temp, Nb->ConfigHandle); - - return (UINT8)Temp; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Write the token stored in the scratchpad register - * - * @HtNbMethod{::F_WRITE_TOKEN} - * - * Use the CPU core count as a scratch pad. - * - * @note The location used to store the token is arbitrary. The only requirement is - * that the location warm resets to zero, and that using it will have no ill-effects - * during HyperTransport initialization. - * - * @param[in] Node the Node that marked with token - * @param[in] Value the token Value - * @param[in] Nb this northbridge - */ -VOID -WriteToken ( - IN UINT8 Node, - IN UINT8 Value, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 Temp; - Temp = Value; - ASSERT ((Node < MAX_NODES)); - // Use CpuCnt as a scratch register - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_NODE_ID_0X60); - LibAmdPciWriteBits (Reg, 19, 16, &Temp, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Full Routing Table Register initialization - * - * @HtNbMethod{::F_WRITE_FULL_ROUTING_TABLE} - * - * Write the routing table entry for Node to target, using the request Link, response - * Link, and broadcast Links provided. - * - * @param[in] Node the Node that will be examined - * @param[in] Target the Target Node for these routes - * @param[in] ReqLink the Link for requests to Target - * @param[in] RspLink the Link for responses to Target - * @param[in] BroadcastLinks the broadcast Links - * @param[in] Nb this northbridge - */ -VOID -WriteFullRoutingTable ( - IN UINT8 Node, - IN UINT8 Target, - IN UINT8 ReqLink, - IN UINT8 RspLink, - IN UINT32 BroadcastLinks, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 Value; - - Value = 0; - ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES)); - if (ReqLink == ROUTE_TO_SELF) { - Value |= Nb->SelfRouteRequestMask; - } else { - Value |= Nb->SelfRouteRequestMask << (ReqLink + 1); - } - - if (RspLink == ROUTE_TO_SELF) { - Value |= Nb->SelfRouteResponseMask; - } else { - Value |= Nb->SelfRouteResponseMask << (RspLink + 1); - } - - // Allow us to accept a Broadcast ourselves, then set broadcasts for routes - Value |= (UINT32)1 << Nb->BroadcastSelfBit; - Value |= (UINT32)BroadcastLinks << (Nb->BroadcastSelfBit + 1); - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_ROUTE0_0X40 + (Target * 4)); - LibAmdPciWrite (AccessWidth32, Reg, &Value, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Determine whether a Node is compatible with the discovered configuration so far. - * - * @HtNbMethod{::F_IS_ILLEGAL_TYPE_MIX}. - * - * Currently, that means the family, extended family of the new Node are the - * same as the BSP's. - * - * @param[in] Node the Node - * @param[in] Nb this northbridge - * - * @retval TRUE the new node is not compatible - * @retval FALSE the new node is compatible - */ -BOOLEAN -IsIllegalTypeMix ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - return ((BOOLEAN) ((Nb->MakeKey (Node, Nb) & Nb->CompatibleKey) == 0)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Fix (hopefully) exceptional conditions. - * - * @HtNbMethod{::F_HANDLE_SPECIAL_NODE_CASE}. - * - * Currently, this routine is implemented for all coherent HT families to check - * vendor ID of coherent Node. If the vendor ID is 0x1022 then return FALSE, - * or return TRUE. - * - * @param[in] Node The Node which need to be checked. - * @param[in] Link The link to check for special conditions. - * @param[in] State our global state. - * @param[in] Nb this northbridge. - * - * @retval TRUE This node received special handling. - * @retval FALSE This node was not handled specially, handle it normally. - * - */ -BOOLEAN -HandleSpecialNodeCase ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ) -{ - BOOLEAN Result; - PCI_ADDR Reg; - UINT32 VendorID; - - Result = TRUE; - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - 0, - 0); - - LibAmdPciReadBits (Reg, 15, 0, &VendorID, Nb->ConfigHandle); - if (VendorID == 0x1022) { - Result = FALSE; - } - - return Result; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.h b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.h deleted file mode 100644 index 74c2a9c857..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.h +++ /dev/null @@ -1,178 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Coherent Feature Northbridge common routines. - * - * Provide access to hardware for routing, coherent discovery. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** FAMILY/NORTHBRIDGE GENERIC FUNCTIONS *** - ***************************************************************************/ - -/** - * Establish a Temporary route from one Node to another. - * - */ -VOID -WriteRoutingTable ( - IN UINT8 Node, - IN UINT8 Target, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); - -/** - * Modifies the NodeID register on the target Node - * - */ -VOID -WriteNodeID ( - IN UINT8 Node, - IN UINT8 NodeID, - IN NORTHBRIDGE *Nb - ); - -/** - * Read the Default Link - * - */ -UINT8 -ReadDefaultLink ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/** - * Turns routing tables on for a given Node - * - */ -VOID -EnableRoutingTables ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/** - * Turns routing tables off for a given Node - * - */ -VOID -DisableRoutingTables ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/** - * Verify that the Link is coherent, connected, and ready - * -*/ -BOOLEAN -VerifyLinkIsCoherent ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); - -/** - * Read the token stored in the scratchpad register field. - * - */ -UINT8 -ReadToken ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/** - * Write the token stored in the scratchpad register - * - */ -VOID -WriteToken ( - IN UINT8 Node, - IN UINT8 Value, - IN NORTHBRIDGE *Nb - ); - -/** - * Full Routing Table Register initialization - * - */ -VOID -WriteFullRoutingTable ( - IN UINT8 Node, - IN UINT8 Target, - IN UINT8 ReqLink, - IN UINT8 RspLink, - IN UINT32 BroadcastLinks, - IN NORTHBRIDGE *Nb - ); - -/** - * Determine whether a Node is compatible with the discovered configuration so far. - * - */ -BOOLEAN -IsIllegalTypeMix ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/** - * Fix (hopefully) exceptional conditions. - * - */ -BOOLEAN -HandleSpecialNodeCase ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.c b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.c deleted file mode 100644 index b563f3cfc3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.c +++ /dev/null @@ -1,142 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge generic non-coherent support routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbNonCoherent.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** Non-coherent init code *** - *** Northbridge access routines *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Return the Link to the Southbridge - * - * @HtNbMethod{::F_READ_SB_LINK} - * - * @param[in] Nb this northbridge - * - * @return the Link to the southbridge - */ -UINT8 -ReadSouthbridgeLink ( - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR Reg; - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0), - MakePciBusFromNode (0), - MakePciDeviceFromNode (0), - CPU_HTNB_FUNC_00, - REG_UNIT_ID_0X64); - LibAmdPciReadBits (Reg, 10, 8, &Temp, Nb->ConfigHandle); - return (UINT8)Temp; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Verify that the Link is non-coherent, connected, and ready - * - * @HtNbMethod{::F_VERIFY_LINK_IS_NON_COHERENT} - * - * @param[in] Node the Node that will be examined - * @param[in] Link the Link on that Node to examine - * @param[in] Nb this northbridge - * - * @retval TRUE The Link has the following status - * - LinkCon=1, Link is connected - * - InitComplete=1, Link initialization is complete - * - NC=1, Link is noncoherent - * - UniP-cLDT=0, Link is not Uniprocessor cLDT - * - LinkConPend=0 Link connection is not pending - * @retval FALSE The Link has some other status - */ -BOOLEAN -VerifyLinkIsNonCoherent ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 LinkType; - PCI_ADDR LinkBase; - - ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES)); - - LinkBase = Nb->MakeLinkBase (Node, Link, Nb); - LinkBase.Address.Register += HTHOST_LINK_TYPE_REG; - - // FN0_98/A4/C4 = LDT Type Register - LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle); - - // Verify LinkCon = 1, InitComplete = 1, NC = 1, UniP-cLDT = 0, LinkConPend = 0 - return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_NONCOHERENT); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.h b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.h deleted file mode 100644 index c56c14b923..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.h +++ /dev/null @@ -1,62 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge generic non-coherent support routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/** - * Return the Link to the Southbridge - */ -UINT8 -ReadSouthbridgeLink ( - IN NORTHBRIDGE *Nb - ); - -/** - * Verify that the Link is non-coherent, connected, and ready - * - */ -BOOLEAN -VerifyLinkIsNonCoherent ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbOptimization.c b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbOptimization.c deleted file mode 100644 index 26aa0381f6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbOptimization.c +++ /dev/null @@ -1,258 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Link optimization support. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "IdsHt.h" -#include "htInterface.h" -#include "htInterfaceGeneral.h" -#include "htNotify.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbOptimization.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** Link Optimization *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Link features into system data structure. - * - * @HtNbMethod{::F_GATHER_LINK_FEATURES} - * - * For a specific discovered CPU Link, populate the port list with the frequency - * capabilities. Support for other link oriented capabilities, currently: - * - Unit ID Clumping. Set to disabled. This doesn't mean the CPU doesn't support clumping, - * it just means: - * - The CPU doesn't clump its host unit ids, and - * - We don't have to check as carefully in SetLinkData whether the port is an IO host link. - * - * @param[in,out] ThisPort The PortList structure entry for this link's port - * @param[in] Interface Access to non-HT support functions. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] Nb this northbridge - */ -VOID -GatherLinkFeatures ( - IN OUT PORT_DESCRIPTOR *ThisPort, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 Frequency; - UINT32 ExtendedFrequency; - - Reg = ThisPort->Pointer; - Reg.Address.Register += HTHOST_FREQ_REV_REG; - LibAmdPciReadBits (Reg, 30, 16, &Frequency, Nb->ConfigHandle); - Reg = ThisPort->Pointer; - Reg.Address.Register += HTHOST_FREQ_EXTENSION; - LibAmdPciReadBits (Reg, 15, 1, &ExtendedFrequency, Nb->ConfigHandle); - ThisPort->PrvFrequencyCap = ((Frequency | (ExtendedFrequency << HT_FREQUENCY_2800M)) & - Nb->NorthBridgeFreqMask (ThisPort->NodeID, Interface, PlatformConfig, Nb)); - // Check for Internal link restriction not to run at 1000 MHz (but allow lower) - if (IsPackageLinkInternal (Nb->GetPackageLink (ThisPort->NodeID, ThisPort->Link, Nb))) { - ThisPort->PrvFrequencyCap &= ~(HT_FREQUENCY_LIMIT_1000M & ~HT_FREQUENCY_LIMIT_800M); - } - ThisPort->ClumpingSupport = HT_CLUMPING_DISABLE; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure for link reganging. - * - * @HtNbMethod{::F_SET_LINK_REGANG} - * - * @param[in] Node the node on which to regang a link - * @param[in] Link the sublink 0 of the sublink pair to regang - * @param[in] Nb this northbridge - */ -VOID -SetLinkRegang ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - UINT32 Temp; - - Temp = 1; - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link)); - - LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure for Unit Id Clumping. - * - * @HtNbMethod{::F_SET_LINK_UNITID_CLUMPING} - * - * This applies to the host root of a non-coherent chain. - * - * @param[in] Node the node on which to enable clumping - * @param[in] Link the link for which to enable clumping - * @param[in] ClumpingEnables the unit id clumping enables - * @param[in] Nb this northbridge - */ -VOID -SetLinkUnitIdClumping ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT32 ClumpingEnables, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR Reg; - - // Host Unit Ids are not clumped. - ASSERT ((ClumpingEnables & 0x3) == 0); - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_HT_LINK_CLUMPING0_0X110 + (4 * Link)); - - LibAmdPciWriteBits (Reg, 31, 0, &ClumpingEnables, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure for link frequency. - * - * @HtNbMethod{::F_SET_LINK_FREQUENCY} - * - * Handle extended frequencies. For HT3 frequencies, ensure Retry and Scrambling are - * set. For HT1, clear them. - * - * @param[in] Node the node on which to set frequency for a link - * @param[in] Link the link to set frequency - * @param[in] Frequency the frequency to set - * @param[in] Nb this northbridge - */ -VOID -SetLinkFrequency ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Frequency, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR Reg; - - ASSERT ((Frequency >= HT_FREQUENCY_600M && Frequency <= HT_FREQUENCY_3200M) - || (Frequency == HT_FREQUENCY_200M) || (Frequency == HT_FREQUENCY_400M)); - - // Handle extended frequencies, 2800 MHz and above. 31 > Frequency > 16 in this case. - if (Frequency > HT_FREQUENCY_2600M) { - Temp = 1; - } else { - // Clear it if not extended. - Temp = 0; - } - Reg = Nb->MakeLinkBase (Node, Link, Nb); - Reg.Address.Register += HTHOST_FREQ_EXTENSION; - LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle); - Reg = Nb->MakeLinkBase (Node, Link, Nb); - Reg.Address.Register += HTHOST_FREQ_REV_REG; - Temp = (Frequency & 0x0F); - LibAmdPciWriteBits (Reg, 11, 8, &Temp, Nb->ConfigHandle); - // Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz - if (Frequency > HT_FREQUENCY_1000M) { - // Enable for Gen3 frequencies - Temp = 1; - } else { - // Disable for Gen1 frequencies - Temp = 0; - } - // HT3 retry mode enable / disable - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_HT_LINK_RETRY0_0X130 + (4 * Link)); - LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle); - // and Scrambling enable / disable - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link)); - LibAmdPciWriteBits (Reg, 3, 3, &Temp, Nb->ConfigHandle); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbOptimization.h b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbOptimization.h deleted file mode 100644 index 56f719cb2d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbOptimization.h +++ /dev/null @@ -1,91 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Link optimization generic support. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/** - * Get Link features into system data structure. - * - */ -VOID -GatherLinkFeatures ( - IN OUT PORT_DESCRIPTOR *ThisPort, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ); - -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure. - * - */ -VOID -SetLinkRegang ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); - -/** - * Set the link's Unit Id Clumping enable. - * - */ -VOID -SetLinkUnitIdClumping ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT32 ClumpingEnables, - IN NORTHBRIDGE *Nb - ); - -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure. - */ -VOID -SetLinkFrequency ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Frequency, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.c deleted file mode 100644 index 237cccc3ea..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.c +++ /dev/null @@ -1,335 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge utility routines. - * - * These routines are needed for support of more than one feature area. - * Collect them in this file so build options don't remove them. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNotify.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "htNbUtilities.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Return the HT Host capability base PCI config address for a Link. - * - * @HtNbMethod{::F_MAKE_LINK_BASE} - * - * @param[in] Node the Node this Link is on - * @param[in] Link the Link - * @param[in] Nb this northbridge - * - * @return the pci config address - */ -PCI_ADDR -MakeLinkBase ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR LinkBase; - - ASSERT (Nb != NULL); - if (Link < 4) { - LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_HT_CAP_BASE_0X80 + Link*HT_HOST_CAP_SIZE); - } else { - LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_04, - REG_HT_CAP_BASE_0X80 + (Link - 4)*HT_HOST_CAP_SIZE); - } - return LinkBase; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Return the LinkFailed status AFTER an attempt is made to clear the bit. - * - * @HtNbMethod{::F_READ_TRUE_LINK_FAIL_STATUS} - * - * Dependency!: HT_FEATURES::SetHtControlRegisterBits - * - * Also, call event notify if a Hardware Fault caused a sync flood on a previous boot. - * - * The table below summarizes correct responses of this routine. - * - * - * - * - * - *
Family before after unconnected Notify? return
10 0 0 0 No FALSE
10 1 0 0 Yes FALSE
10 1 0 3 No TRUE
- * - * @param[in] Node the Node that will be examined - * @param[in] Link the Link on that Node to examine - * @param[in] State access to call back routine - * @param[in] Nb this northbridge - * - * @retval TRUE the Link is not connected or has hard error - * @retval FALSE the Link is connected - */ -BOOLEAN -ReadTrueLinkFailStatus ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Before; - UINT32 After; - UINT32 Unconnected; - UINT32 Crc; - PCI_ADDR Reg; - - ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks)); - - Reg = Nb->MakeLinkBase (Node, Link, Nb); - Reg.Address.Register += HTHOST_LINK_CONTROL_REG; - - // Save the CRC status before doing anything else. - // Read, Clear, re-read the error bits in the Link Control Register - // (FN0_84/A4/C4[4] = LinkFail bit), - // and check the connection status, TransOff and EndOfChain. - // - LibAmdPciReadBits (Reg, 9, 8, &Crc, Nb->ConfigHandle); - LibAmdPciReadBits (Reg, 4, 4, &Before, Nb->ConfigHandle); - State->HtFeatures->SetHtControlRegisterBits (Reg, 4, 4, &Before, State); - LibAmdPciReadBits (Reg, 4, 4, &After, Nb->ConfigHandle); - LibAmdPciReadBits (Reg, 7, 6, &Unconnected, Nb->ConfigHandle); - - if (Before != After) { - if (Unconnected == 0) { - if (Crc != 0) { - // A sync flood occurred due to HT CRC - // Pass the Node and Link on which the generic sync flood event occurred. - NotifyAlertHwHtCrc (Node, Link, (UINT8)Crc, State); - } else { - // Some sync flood occurred - // Pass the Node and Link on which the generic sync flood event occurred. - NotifyAlertHwSyncFlood (Node, Link, State); - } - } - } - return (BOOLEAN) ((After != 0) || (Unconnected != 0)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write the total number of cores and Nodes to the Node - * - * @HtNbMethod{::F_SET_TOTAL_NODES_AND_CORES} - * - * @param[in] Node the Node that will be examined - * @param[in] TotalNodes the total number of Nodes - * @param[in] TotalCores the total number of cores - * @param[in] Nb this northbridge - */ -VOID -SetTotalNodesAndCores ( - IN UINT8 Node, - IN UINT8 TotalNodes, - IN UINT8 TotalCores, - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR NodeIDReg; - UINT32 Temp; - - ASSERT ((Node < MAX_NODES) && (TotalNodes <= MAX_NODES)); - NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_NODE_ID_0X60); - - Temp = ((TotalCores - 1) & HTREG_NODE_CPUCNT_4_0); - LibAmdPciWriteBits (NodeIDReg, 20, 16, &Temp, Nb->ConfigHandle); - Temp = TotalNodes - 1; - LibAmdPciWriteBits (NodeIDReg, 6, 4, &Temp, Nb->ConfigHandle); - - NodeIDReg.Address.Register = REG_HT_EXTENDED_NODE_ID_F0X160; - - Temp = (((TotalCores - 1) & HTREG_EXTNODE_CPUCNT_7_5) >> 5); - LibAmdPciWriteBits (NodeIDReg, 18, 16, &Temp, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the Count (1 based) of Nodes in the system. - * - * @HtNbMethod{::F_GET_NODE_COUNT} - * - * This is intended to support AP Core HT init, since the Discovery State data is not - * available (State->NodesDiscovered), there needs to be this way to find the number - * of Nodes. The Node count can be read from the BSP. - * - * @param[in] Nb this northbridge - * - * @return The number of nodes - */ -UINT8 -GetNodeCount ( - IN NORTHBRIDGE *Nb - ) -{ - PCI_ADDR NodeIDReg; - UINT32 Temp; - - NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0), - MakePciBusFromNode (0), - MakePciDeviceFromNode (0), - CPU_HTNB_FUNC_00, - REG_NODE_ID_0X60); - LibAmdPciReadBits (NodeIDReg, 6, 4, &Temp, Nb->ConfigHandle); - return ((UINT8) (++Temp)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Limit coherent config accesses to cpus as indicated by Nodecnt. - * - * @HtNbMethod{::F_LIMIT_NODES} - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - */ -VOID -LimitNodes ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - UINT32 Temp; - PCI_ADDR Reg; - - Temp = 1; - ASSERT ((Node < MAX_NODES)); - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_HTNB_FUNC_00, - REG_LINK_TRANS_CONTROL_0X68); - LibAmdPciWriteBits (Reg, 15, 15, &Temp, Nb->ConfigHandle); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the Package Link number, given the node and real link number. - * - * @HtNbMethod{::F_GET_PACKAGE_LINK} - * - * Based on the link to package link mapping from BKDG, look up package link for - * the input link on the internal node number corresponding to Node id. - * - * @param[in] Node the node which has this link - * @param[in] Link the link on that node - * @param[in] Nb this northbridge - * - * @return the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link. - * - */ -UINT8 -GetPackageLink ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ) -{ - UINT8 ModuleType; - UINT8 Module; - UINTN PackageLinkMapItem; - UINT8 PackageLink; - - ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks)); - PackageLink = HT_LIST_TERMINAL; - - Nb->GetModuleInfo (Node, &ModuleType, &Module, Nb); - - if (ModuleType != 0) { - ASSERT (Nb->PackageLinkMap != NULL); - // Use table to find this module's package link - PackageLinkMapItem = 0; - while ((*Nb->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) { - if (((*Nb->PackageLinkMap)[PackageLinkMapItem].Module == Module) && - ((*Nb->PackageLinkMap)[PackageLinkMapItem].Link == Link)) { - PackageLink = (*Nb->PackageLinkMap)[PackageLinkMapItem].PackageLink; - break; - } - PackageLinkMapItem++; - } - } else { - PackageLink = Link; - } - return PackageLink; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.h b/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.h deleted file mode 100644 index aca80ec9ef..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.h +++ /dev/null @@ -1,108 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge utility routines. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/** - * Return the HT Host capability base PCI config address for a Link. - * - */ -PCI_ADDR -MakeLinkBase ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); - -/** - * Return the LinkFailed status AFTER an attempt is made to clear the bit. - * - */ -BOOLEAN -ReadTrueLinkFailStatus ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); - -/** - * Write the total number of cores and Nodes to the Node - * - */ -VOID -SetTotalNodesAndCores ( - IN UINT8 Node, - IN UINT8 TotalNodes, - IN UINT8 TotalCores, - IN NORTHBRIDGE *Nb - ); - -/** - * Get the Count (1 based) of Nodes in the system. - * - */ -UINT8 -GetNodeCount ( - IN NORTHBRIDGE *Nb - ); - -/** - * Limit coherent config accesses to cpus as indicated by Nodecnt. - * - */ -VOID -LimitNodes ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/** - * Get the Package Link number, given the node and real link number. - * - */ -UINT8 -GetPackageLink ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.c deleted file mode 100644 index 1ff0d66194..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.c +++ /dev/null @@ -1,112 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HyperTransport features constructor. - * - * Initialize the set of available features. - * This file implements build options using conditional compilation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionsHt.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "CommonReturns.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_HTFEAT_FILECODE -extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration; - -/** - * A no features Initializer. - */ -CONST HT_FEATURES ROMDATA HtFeaturesNone = -{ - (PF_COHERENT_DISCOVERY)CommonVoid, - (PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid, - (PF_MAKE_HOP_COUNT_TABLE)CommonVoid, - (PF_PROCESS_LINK)CommonVoid, - (PF_GATHER_LINK_DATA)CommonVoid, - (PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY)CommonVoid, - (PF_REGANG_LINKS)CommonVoid, - (PF_SUBLINK_RATIO_FIXUP)CommonVoid, - (PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse, - (PF_SET_LINK_DATA)CommonVoid, - (PF_TRAFFIC_DISTRIBUTION)CommonVoid, - (PF_SET_HT_CONTROL_REGISTER_BITS)CommonVoid, - (PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8 -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Provide the current Feature set implementation. - * - * Initialize using the installed initializer. - * - * @param[in] HtFeatures A feature object to initialize - * @param[in] StdHeader Opaque handle to standard config header -*/ -VOID -NewHtFeatures ( - OUT HT_FEATURES *HtFeatures, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMemCopy ( - (VOID *) HtFeatures, - (VOID *) OptionHtConfiguration.HtOptionInternalFeatures , - (UINT32) (sizeof (HT_FEATURES)), - StdHeader - ); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.h deleted file mode 100644 index 61898c013c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.h +++ /dev/null @@ -1,562 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HT Features. - * - * This file provides definitions used in common by HT internal modules. The - * data is private and not for external client access. - * Definitions include the HT global internal state data structures, and - * access to the available HT features from the main HT entry point. - * - * This file includes the feature constructor and feature support which is not - * removed with various build options. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _HT_FEAT_H_ -#define _HT_FEAT_H_ - -/** - * @page htimplfeat HT Features Implementation Guide - * - * HT Features provides access to the HT Feature set, in a manner that isolates - * calling code from knowledge about the Feature set implementation or which - * features are supported in the current build. In the case of feature sets, this - * is mostly used for build options to reduce code size by removing unneeded features. - * - * @par Adding a Method to HT Features - * - * To add a new method to the HT Features, follow these steps. - *
    - *
  • Create a typedef for the Method with the correct parameters and return type. - * - *
      - *
    • Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item, - * but with "_"'s and UPPERCASE, rather than mixed case. - * @n typedef VOID (F_METHOD_NAME)(); @n - * - *
    • Make a reference type for references to a method implementation: - * @n /// Reference to a Method - * @n typedef F_METHOD_NAME *PF_METHOD_NAME @n - *
    - * - *
  • Provide a standard doxygen function preamble for the Method typedef. Begin the - * detailed description by providing a reference to the method instances page by including - * the lines below: - * @code - * * - * * @HtFeatInstances. - * * - * @endcode - * @note It is important to provide documentation for the method type, because the method may not - * have an implementation in any families supported by the current package. @n - * - *
  • Add to the _HT_FEATURES struct an item for the Method: - * @n PF_METHOD_NAME MethodName; ///< Method: description. @n - *
- * - * @par Implementing an HT Features Instance of the method. - * - * To implement an instance of a method for a specific feature follow these steps. - * - * - In appropriate files, implement the method with the return type and parameters - * matching the method typedef. - * - * - Name the function MethodName(). - * - * - Create a doxygen function preamble for the method instance. Begin the detailed description with - * an Implements command to reference the method type and add this instance to the Method Instances page. - * @code - * * - * * @HtFeatMethod{::F_METHOD_NAME}. - * * - * @endcode - * - * - To access other Ht feature routines or data as part of the method implementation, the function - * must use HtFeatures->OtherMethod(). Do not directly access other HT feature - * routines, because in the table there may be overrides or this routine may be shared by multiple configurations. - * - * - Add the instance to the HT_FEATURES instances. - * - * - If a configuration does not need an instance of the method use one of the CommonReturns from - * CommonReturns.h with the same return type. - * - * @par Invoking HT Features Methods. - * - * The first step is carried out only once by the top level HT entry point. - * @n @code - * HT_FEATURES HtFeatures; - * // Get the current HT Feature Set - * NewHtFeatures (&HtFeatures); - * State->HtFeatures = &HtFeatures; - * @endcode - * - * The following example shows how to invoke a HT Features method. - * @n @code - * State->HtFeatures->MethodName (); - * @endcode - * - */ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define MAX_PLATFORM_LINKS 64 -#define MAX_LINK_PAIRS 4 - -/* These following are internal definitions */ -#define ROUTE_TO_SELF 0x0F -#define INVALID_LINK 0xCC /* Used in port list data structure to mark unused data entries. - Can also be used for no Link found in a port list search */ - -/* definitions for working with the port list structure */ -#define PORTLIST_TYPE_CPU 0 -#define PORTLIST_TYPE_IO 1 - -/* - * Hypertransport Capability definitions and macros - * - */ - -#define HT_INTERFACE_CAP_SUBTYPE_MASK ((UINT32)0xE00000FF) -#define HT_CAP_SUBTYPE_MASK ((UINT32)0xF80000FF) - -/* HT Host Capability */ -#define HT_HOST_CAPABILITY 1 -#define HT_HOST_CAP_SIZE 0x20 - -/* Host CapabilityRegisters */ -#define HTHOST_LINK_CAPABILITY_REG 0x00 -#define HTHOST_LINK_CONTROL_REG 0x04 -#define HTHOST_FREQ_REV_REG 0x08 -#define HTHOST_REV_REV3 0x60 -#define HTHOST_FEATURE_CAP_REG 0x0C -#define HTHOST_BUFFER_COUNT_REG 0x10 -#define HTHOST_ISOC_REG 0x14 -#define HTHOST_LINK_TYPE_REG 0x18 -#define HTHOST_FREQ_EXTENSION 0x1C -#define HTHOST_TYPE_COHERENT 3 -#define HTHOST_TYPE_NONCOHERENT 7 -#define HTHOST_TYPE_MASK 0x1F - -/* HT Slave Capability (HT1 compat) */ -#define HT_SLAVE_CAPABILITY 0 -#define HTSLAVE_LINK01_OFFSET 4 -#define HTSLAVE_LINK_CONTROL_0_REG 4 -#define HTSLAVE_FREQ_REV_0_REG 0xC -#define HTSLAVE_FEATURECAP_REG 0x10 -#define HT_CONTROL_CLEAR_CRC (~(3 << 8)) -#define HT_FREQUENCY_CLEAR_LINK_ERRORS (~(0x7 << 12)) -#define MAX_BUID 31 - -/* HT3 gen Capability */ -#define HT_GEN3_CAPABILITY (0xD << 1) -#define HTGEN3_LINK01_OFFSET 0x10 -#define HTGEN3_LINK_TRAINING_0_REG 0x10 - -/* HT3 Retry Capability */ -#define HT_RETRY_CAPABILITY (0xC << 1) -#define HTRETRY_CONTROL_REG 4 - -/* Unit ID Clumping Capability */ -#define HT_UNITID_CAPABILITY (0x9 << 1) -#define HTUNIT_SUPPORT_REG 4 -#define HTUNIT_ENABLE_REG 8 -#define HT_CLUMPING_PASSIVE 1 - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -// Forward declarations. -/// Used for forward reference. -typedef struct _NORTHBRIDGE NORTHBRIDGE; -/// Used for forward reference. -typedef struct _HT_FEATURES HT_FEATURES; -/// Used for forward reference. -typedef struct _HT_INTERFACE HT_INTERFACE; - -/** - * Coherent Init Data. - * - * Metrics representing the coherent fabric which was discovered: Degree of nodes, adjacency, - * node numbering permutations, and the topology which it matched. - */ -typedef struct { - /** The number of coherent Links connected on each Node (the 'Degree' of the Node) */ - UINT8 SysDegree[MAX_NODES]; - /** The systems adjacency (sysMatrix[i][j] is true if Node_i has a Link to Node_j) */ - BOOLEAN SysMatrix[MAX_NODES][MAX_NODES]; - - UINT8 DbDegree[MAX_NODES]; /**< Like sysDegree, but for the current database topology */ - BOOLEAN DbMatrix[MAX_NODES][MAX_NODES]; /**< Like sysMatrix, but for the current database topology */ - - UINT8 Perm[MAX_NODES]; /**< The Node mapping from the system to the database */ - UINT8 ReversePerm[MAX_NODES]; /**< The Node mapping from the database to the system */ - UINT8 *MatchedTopology; /**< The topology that matched the current system or NULL */ -} COHERENT_FABRIC; - -/** - * Represent the system as Links of matched port pairs. - * A pair consists of a source Node, a Link to the destination Node, the - * destination Node, and its Link back to source Node. The even indices are - * the source Nodes and Links, and the odd indices are for the destination - * Nodes and Links. - * @note The Port pair 2*N and 2*N+1 are connected together to form a Link - * (e.g. 0,1 and 8,9 are ports on either end of an HT Link) The lower number - * port (2*N) is the source port. The device that owns the source port is - * always the device closer to the BSP. (i.e. nearer the CPU in a - * non-coherent chain, or the CPU with the lower NodeID). - */ -typedef struct { - /* This section is where the Link is in the system and how to find it */ - UINT8 Type; /**< 0 = CPU, 1 = Device, all others reserved */ - UINT8 Link; /**< 0-1 for devices, 0-7 for CPUs */ - UINT8 NodeID; /**< The Node, or a pointer to the devices parent Node */ - UINT8 HostLink; /**< For Devices, the root CPU's Link to the chain */ - UINT8 HostDepth; /**< Link Depth in chain, only used by devices */ - PCI_ADDR Pointer; /**< A pointer to the device's slave HT capability, so we don't have to keep searching */ - - /* This section is for the final settings, which are written to hardware */ - BOOLEAN SelRegang; /**< Indicates to software regang Link, only used for CPU->CPU Links */ - UINT8 SelWidthIn; /**< Width in setting */ - UINT8 SelWidthOut; /**< Width out setting */ - UINT8 SelFrequency; /**< Frequency setting */ - - /* This section is for keeping track of capabilities and possible configurations */ - BOOLEAN RegangCap; /**< Is the port capable of reganging? CPUs only */ - UINT32 PrvFrequencyCap; /**< Possible frequency settings */ - UINT8 PrvWidthInCap; /**< Possible Width setting */ - UINT8 PrvWidthOutCap; /**< Possible Width setting */ - UINT32 CompositeFrequencyCap; /**< Possible Link frequency setting */ - UINT32 ClumpingSupport; /**< Unit ID Clumping value (bit 0 = passive support) */ -} PORT_DESCRIPTOR; - -/// Reference to a set of PORT_DESCRIPTORs. -typedef PORT_DESCRIPTOR (*PORT_LIST)[MAX_PLATFORM_LINKS*2]; - -/** - * Our global state data structure - */ -typedef struct { - AMD_HT_INTERFACE *HtBlock; /**< The input data structure. */ - - UINT8 NodesDiscovered; /**< One less than the number of Nodes found in the system */ - UINT8 TotalLinks; /**< How many HT Links have we discovered so far. */ - UINT8 SysMpCap; /**< The maximum number of Nodes that all processors are capable of */ - AGESA_STATUS MaxEventClass; /**< The event class of the highest severity event generated */ - - PORT_LIST PortList; /**< Represent the system as a set of Links, each two Ports. */ - COHERENT_FABRIC *Fabric; /**< Describe metrics about the coherent fabric. - * Limited scope to CoherentInit(). */ - /* Data interface to other Agesa Modules */ - SOCKET_DIE_TO_NODE_MAP SocketDieToNodeMap; /**< For each Socket, Die the Node ids */ - NODE_TO_SOCKET_DIE_MAP NodeToSocketDieMap; /**< For each Node id, Socket and Die */ - HOP_COUNT_TABLE *HopCountTable; /**< Table of hops between nodes */ - - /* Data for non-coherent initialization */ - UINT8 AutoBusCurrent; /**< The next bus number available */ - UINT8 UsedCfgMapEntries; /**< The next Config address Map set available, Limit 4 (F1X[EC:E0]) */ - BOOLEAN IsUsingRecoveryHt; /**< Manual BUID Swap List processing should assume that HT Recovery was used */ - BOOLEAN IsSetHtCrcFlood; /**< Enable setting of HT CRC Flood */ - BOOLEAN IsUsingUnitIdClumping; /**< Enable automatic Unit Id Clumping configuration. */ - - HT_INTERFACE *HtInterface; /**< Interface for feature code to external parameters */ - HT_FEATURES *HtFeatures; /**< The current feature implementations */ - NORTHBRIDGE *Nb; /**< The current northbridge */ - - PLATFORM_CONFIGURATION *PlatformConfiguration; /**< The platform specific configuration customizations */ - VOID *ConfigHandle; /**< Config Pointer, opaque handle for passing to lib */ -} STATE_DATA; - -// -// Feature Method types -// - -/** - * Discover all coherent devices in the system. - * - * @HtFeatInstances. - * - * @param[in,out] State our global state - * - */ -typedef VOID F_COHERENT_DISCOVERY ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_COHERENT_DISCOVERY *PF_COHERENT_DISCOVERY; - -/** - * Using the description of the fabric topology we discovered, try to find a match - * among the supported topologies. - * - * @HtFeatInstances. - * - * @param[in,out] State the discovered fabric, degree matrix, permutation - * - */ -typedef VOID F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES *PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES; - -/** - * Make a Hop Count Table for the installed topology. - * - * @HtFeatInstances. - * - * @param[in,out] State access topology, permutation, update hop table - * - */ -typedef VOID F_MAKE_HOP_COUNT_TABLE ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_MAKE_HOP_COUNT_TABLE *PF_MAKE_HOP_COUNT_TABLE; - -/** - * Process a non-coherent Link. - * - * @HtFeatInstances. - * - * @param[in] Node Node on which to process nc init - * @param[in] Link The non-coherent Link on that Node - * @param[in] IsCompatChain Is this the chain with the southbridge? TRUE if yes. - * @param[in,out] State our global state - */ -typedef VOID F_PROCESS_LINK ( - IN UINT8 Node, - IN UINT8 Link, - IN BOOLEAN IsCompatChain, - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_PROCESS_LINK *PF_PROCESS_LINK; - -/** - * Get Link features into system data structure. - * - * @HtFeatInstances. - * - * @param[in] State our global state, port list - */ -typedef VOID F_GATHER_LINK_DATA ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GATHER_LINK_DATA *PF_GATHER_LINK_DATA; - -/** - * Optimize Links. - * - * @HtFeatInstances. - * - * @param[in,out] State Process and update portlist - */ -typedef VOID F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY *PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY; - -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure. - * - * @HtFeatInstances. - * - * @param[in] State our global state, port list - */ -typedef VOID F_SET_LINK_DATA ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_SET_LINK_DATA *PF_SET_LINK_DATA; - -/** - * Retry must be enabled on all coherent links if it is enabled on any coherent links. - * - * @HtFeatInstances. - * - * @param[in,out] State global state, port frequency settings. - * - * @retval TRUE Fixup occurred, all coherent links HT1 - * @retval FALSE No changes - */ -typedef BOOLEAN F_IS_COHERENT_RETRY_FIXUP ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_IS_COHERENT_RETRY_FIXUP *PF_IS_COHERENT_RETRY_FIXUP; - - -/** - * Test the subLinks of a Link to see if they qualify to be reganged. - * - * @HtFeatInstances. - * - * @param[in,out] State Our global state - */ -typedef VOID F_REGANG_LINKS ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_REGANG_LINKS *PF_REGANG_LINKS; - -/** - * Iterate through all Links, checking the frequency of each subLink pair. - * - * @HtFeatInstances. - * - * @param[in,out] State Link state and port list - * - */ -typedef VOID F_SUBLINK_RATIO_FIXUP ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_SUBLINK_RATIO_FIXUP *PF_SUBLINK_RATIO_FIXUP; - -/** - * Identify Links which can have traffic distribution. - * - * @HtFeatInstances. - * - * @param[in] State port list data - */ -typedef VOID F_TRAFFIC_DISTRIBUTION ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_TRAFFIC_DISTRIBUTION *PF_TRAFFIC_DISTRIBUTION; - -/** - * Access HT Link Control Register. - * - * @HtFeatInstances. - * - * @param[in] Reg the PCI config address the control register - * @param[in] HiBit the high bit number - * @param[in] LoBit the low bit number - * @param[in] Value the value to write to that bit range. Bit 0 => loBit. - * @param[in] State Our state, config handle for lib - */ -typedef VOID F_SET_HT_CONTROL_REGISTER_BITS ( - IN PCI_ADDR Reg, - IN UINT8 HiBit, - IN UINT8 LoBit, - IN UINT32 *Value, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_SET_HT_CONTROL_REGISTER_BITS *PF_SET_HT_CONTROL_REGISTER_BITS; - -/** - * Translate a desired width setting to the bits to set in the register field. - * - * @HtFeatInstances. - * - * @param[in] Value the width Value - * - * @return The bits for the register - */ -typedef UINT8 F_CONVERT_WIDTH_TO_BITS ( - IN UINT8 Value - ); -/// Reference to a method. -typedef F_CONVERT_WIDTH_TO_BITS *PF_CONVERT_WIDTH_TO_BITS; - -/** - * HT Feature Methods. - * - * Provides abstract methods which are bound to specific feature implementations. - */ -struct _HT_FEATURES { - PF_COHERENT_DISCOVERY CoherentDiscovery; /**< Method: Coherent Discovery. */ - PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES LookupComputeAndLoadRoutingTables; - /**< Method: Route the discovered system */ - PF_MAKE_HOP_COUNT_TABLE MakeHopCountTable; /**< Method: Compute slit hop counts */ - PF_PROCESS_LINK ProcessLink; /**< Method: Process a non-coherent Link. */ - PF_GATHER_LINK_DATA GatherLinkData; /**< Method: Gather Link Capabilities and data. */ - PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY SelectOptimalWidthAndFrequency; - /**< Method: Optimize link features. */ - PF_REGANG_LINKS RegangLinks; /**< Method: Regang Sublinks. */ - PF_SUBLINK_RATIO_FIXUP SubLinkRatioFixup; /**< Method: Fix Sublink Frequency ratios */ - PF_IS_COHERENT_RETRY_FIXUP IsCoherentRetryFixup; - /**< Method: Fix Retry mixed on coherent links. */ - PF_SET_LINK_DATA SetLinkData; /**< Method: Set optimized values. */ - PF_TRAFFIC_DISTRIBUTION TrafficDistribution; /**< Method: Detect and Initialize Traffic Distribution */ - PF_SET_HT_CONTROL_REGISTER_BITS SetHtControlRegisterBits; /**< Method: Access HT Link Control Reg. */ - PF_CONVERT_WIDTH_TO_BITS ConvertWidthToBits; /**< Method: Convert a bit width to the value used for register setting. */ -} ; - -/*---------------------------------------------------------------------------- - * Prototypes - * - *---------------------------------------------------------------------------- - */ - -/** - * Provide the current Feature set implementation. - * - * Add an implementation reference for the constructor, just to make sure the page is created. - * @HtFeatMethod{_HT_FEATURES}. - * - */ -VOID -NewHtFeatures ( - OUT HT_FEATURES *HtFeatures, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -#endif /* _HT_FEAT_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph.h deleted file mode 100644 index c596160494..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph.h +++ /dev/null @@ -1,142 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Topology Interface. - * - * Contains interface to the topology data. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _HT_GRAPH_H_ -#define _HT_GRAPH_H_ - -/** - * @page htgraphdesign Graph Support routines - * - * These routines provide support for dealing with the graph representation - * of the topologies, along with the routing table information for that topology. - * The routing information is compressed and these routines currently decompress - * 'on the fly'. A graph is represented as a set of routes. All the edges in the - * graph are routes; a direct route from Node i to Node j exists in the graph IFF - * there is an edge directly connecting Node i to Node j. All other routes designate - * the edge which the route to that Node initially takes, by designating a Node - * to which a direct connection exists. That is, the route to non-adjacent Node j - * from Node i specifies Node k where Node i directly connects to Node k. - * - *@code - * pseudo definition of compressed graph: - * typedef struct - * { - * // First byte - * UINT8 broadcast[8]:1; // that is, 8 1-bit values - * // Second byte - * UINT8 requestRoute:4; // [3:0] - * UINT8 responseRoute:4; // [7:4] - * } sRoute; - * typedef struct - * { - * UINT8 size; - * sRoute graph[size][size]; - * } sGraph; - *@endcode - */ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -VOID -GetAmdTopolist ( - OUT UINT8 ***List - ); - -UINT8 -GraphHowManyNodes ( - IN UINT8 *Graph - ); - -BOOLEAN -GraphIsAdjacent ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ); - -UINT8 -GraphGetRsp ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ); - -UINT8 -GraphGetReq ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ); - -UINT8 -GraphGetBc ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ); - -#endif /* _HT_GRAPH_H_ */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/Makefile.inc deleted file mode 100644 index fceb584093..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -libagesa-y += htGraph.c -libagesa-y += htGraph1.c -libagesa-y += htGraph2.c -libagesa-y += htGraph3Line.c -libagesa-y += htGraph3Triangle.c -libagesa-y += htGraph4Degenerate.c -libagesa-y += htGraph4FullyConnected.c -libagesa-y += htGraph4Kite.c -libagesa-y += htGraph4Line.c -libagesa-y += htGraph4Square.c -libagesa-y += htGraph4Star.c -libagesa-y += htGraph5FullyConnected.c -libagesa-y += htGraph5TwistedLadder.c -libagesa-y += htGraph6DoubloonLower.c -libagesa-y += htGraph6DoubloonUpper.c -libagesa-y += htGraph6FullyConnected.c -libagesa-y += htGraph6TwinTriangles.c -libagesa-y += htGraph6TwistedLadder.c -libagesa-y += htGraph7FullyConnected.c -libagesa-y += htGraph7TwistedLadder.c -libagesa-y += htGraph8DoubloonM.c -libagesa-y += htGraph8FullyConnected.c -libagesa-y += htGraph8Ladder.c -libagesa-y += htGraph8TwinFullyFourWays.c -libagesa-y += htGraph8TwistedLadder.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph.c deleted file mode 100644 index 1b9b0947b4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph.c +++ /dev/null @@ -1,199 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Routines to deal with topology data. - * - * Access the topologies and information about a topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#include "AGESA.h" -#include "Ids.h" -#include "htGraph.h" -#include "OptionsHt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_HTGRAPH_HTGRAPH_FILECODE - -extern OPTION_HT_CONFIGURATION OptionHtConfiguration; - -/*----------------------------------------------------------------------------------------*/ -/** - * Returns the AGESA built in topology list - * - * @param[out] List a pointer to the built in topology list - */ -VOID -GetAmdTopolist ( - OUT UINT8 ***List - ) -{ - // Cast below to hush CONST warning. The built in list must be CONST to be in ROM statically. - // The caller of this routine may get a topolist pointer from the interface, however, and - // that is not CONST, since it could be on the stack. - // - *List = (UINT8 **)OptionHtConfiguration.HtOptionBuiltinTopologies; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Returns the number of Nodes in the compressed graph - * - * @param[in] Graph a compressed graph - * - * @return the number of Nodes in the graph - */ -UINT8 -GraphHowManyNodes ( - IN UINT8 *Graph - ) -{ - return Graph[0]; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Returns true if NodeA is directly connected to NodeB, false otherwise - * - * if NodeA == NodeB also returns false. - * Relies on rule that directly connected Nodes always route requests directly. - * - * @param[in] Graph the graph to examine - * @param[in] NodeA the Node number of the first Node - * @param[in] NodeB the Node number of the second Node - * - * @retval TRUE NodeA connects to NodeB - * @retval FALSE NodeA does not connect to NodeB - */ -BOOLEAN -GraphIsAdjacent ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ) -{ - UINT8 size; - size = Graph[0]; - ASSERT ((NodeA < size) && (NodeB < size)); - return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F) == NodeB; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Returns the graph Node used by NodeA to route responses targeted at NodeB. - * - * This will be a Node directly connected to NodeA (possibly NodeB itself), - * or "Route to Self" if NodeA and NodeB are the same Node. - * Note that all Node numbers are abstract Node numbers of the topology graph, - * it is the responsibility of the caller to apply any permutation needed. - * - * @param[in] Graph the graph to examine - * @param[in] NodeA the Node number of the first Node - * @param[in] NodeB the Node number of the second Node - * - * @return The response route Node - */ -UINT8 -GraphGetRsp ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ) -{ - UINT8 size; - size = Graph[0]; - ASSERT ((NodeA < size) && (NodeB < size)); - return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0xF0) >> 4; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Returns the graph Node used by NodeA to route requests targeted at NodeB. - * - * This will be a Node directly connected to NodeA (possibly NodeB itself), - * or "Route to Self" if NodeA and NodeB are the same Node. - * Note that all Node numbers are abstract Node numbers of the topology graph, - * it is the responsibility of the caller to apply any permutation needed. - * - * @param[in] Graph the graph to examine - * @param[in] NodeA the Node number of the first Node - * @param[in] NodeB the Node number of the second Node - * - * @return The request route Node - */ -UINT8 -GraphGetReq ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ) -{ - UINT8 size; - size = Graph[0]; - ASSERT ((NodeA < size) && (NodeB < size)); - return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Returns a bit vector of Nodes that NodeA should forward a broadcast from - * NodeB towards - * - * @param[in] Graph the graph to examine - * @param[in] NodeA the Node number of the first Node - * @param[in] NodeB the Node number of the second Node - * - * @return the broadcast routes for NodeA from NodeB - */ -UINT8 -GraphGetBc ( - IN UINT8 *Graph, - IN UINT8 NodeA, - IN UINT8 NodeB - ) -{ - UINT8 size; - size = Graph[0]; - ASSERT ((NodeA < size) && (NodeB < size)); - return Graph[1 + (NodeA*size + NodeB)*2]; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph1.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph1.c deleted file mode 100644 index eaed064ddc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph1.c +++ /dev/null @@ -1,70 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Single node topology - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* - * 0 - */ -/** - * single node - */ -/** - * @dot - strict graph one { - node [shape="plaintext"]; - 0; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologySingleNode[] = -{ - 0x01, - 0x00, 0xFF // Node 0 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph2.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph2.c deleted file mode 100644 index 7466564fb8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph2.c +++ /dev/null @@ -1,71 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Two nodes. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* - * 0---1 - */ -/** - * Two Nodes. - */ -/** - * @dot - strict graph two { - node [shape="plaintext"]; - 0 -- 1 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyDualNode[] = -{ - 0x02, - 0x02, 0xFF, 0x00, 0x11, // Node 0 - 0x00, 0x00, 0x01, 0xFF // Node 1 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph3Line.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph3Line.c deleted file mode 100644 index 1f6b439a5f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph3Line.c +++ /dev/null @@ -1,76 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Three Line. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* - * 2 - * | - * | - * 0---1 - */ -/** - * Three Line - */ -/** - * @dot - strict graph three { - node [shape="plaintext"]; - 0 -- 1 ; - 0 -- 2 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyThreeLine[] = -{ - 0x03, - 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, // Node 0 - 0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 1 - 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF // Node 2 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph3Triangle.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph3Triangle.c deleted file mode 100644 index 5a5e01f256..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph3Triangle.c +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Three Triangle Topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* - * 2 - * |\ - * | \ - * 0---1 - */ -/** - * Three triangle - */ -/** - * @dot - strict graph triangle { - node [shape="plaintext"]; - 0 -- 1 ; - 0 -- 2 ; - 1 -- 2 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyTriangle[] = -{ - 0x03, - 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, // Node 0 - 0x00, 0x00, 0x05, 0xFF, 0x00, 0x22, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x03, 0xFF // Node 2 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Degenerate.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Degenerate.c deleted file mode 100644 index ad0974231b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Degenerate.c +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Four node degenerate. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/* - * 2 3 - * |\ | - * | \| - * 0---1 - */ -/** - * Four Node degenerate - */ -/** - * @dot - strict graph degen4 { - node [shape="plaintext"]; - {rank=same; 0; 1} - {rank=same; 2; 3} - 0 -- 1 ; - 0 -- 2 ; - 1 -- 2 ; - 1 -- 3 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[] = -{ - 0x04, - 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0 - 0x08, 0x00, 0x0D, 0xFF, 0x08, 0x22, 0x05, 0x33, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x03, 0xFF, 0x00, 0x11, // Node 2 - 0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4FullyConnected.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4FullyConnected.c deleted file mode 100644 index 41467520b7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4FullyConnected.c +++ /dev/null @@ -1,83 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Four node fully connected. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* - * 2---3 - * |\ /| - * |/ \| - * 0---1 - */ -/** - * Four Node Fully - */ -/** - * @dot - strict graph full4 { - node [shape="plaintext"]; - {rank=same; 0; 1} - {rank=same; 2; 3} - 0 -- 1 ; - 0 -- 2 ; - 0 -- 3 ; - 1 -- 2 ; - 1 -- 3 ; - 2 -- 3 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyFourFully[] = -{ - 0x04, - 0x0E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, // Node 0 - 0x00, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x00, 0x33, // Node 2 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x07, 0xFF // Node 3 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Kite.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Kite.c deleted file mode 100644 index 5f1d3df58c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Kite.c +++ /dev/null @@ -1,81 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Four node kite Topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/* - * 2---3 - * |\ | - * | \| - * 0---1 - */ -/** - * Four Node kite - */ -/** - * @dot - strict graph kite4 { - node [shape="plaintext"]; - {rank=same; 0; 1} - {rank=same; 2; 3} - 0 -- 1 ; - 0 -- 2 ; - 1 -- 2 ; - 1 -- 3 ; - 2 -- 3 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyFourKite[] = -{ - 0x04, - 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0 - 0x08, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x01, 0x33, // Node 2 - 0x00, 0x22, 0x00, 0x11, 0x00, 0x22, 0x06, 0xFF // Node 3 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Line.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Line.c deleted file mode 100644 index 3cc8e59b1f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Line.c +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Four node Line Topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* - * 2 3 - * | | - * | | - * 0---1 - */ -/** - * Four Node line - */ -/** - * @dot - strict graph line4 { - node [shape="plaintext"]; - {rank=same; 0; 1} - {rank=same; 2; 3} - 0 -- 1 ; - 0 -- 2 ; - 1 -- 3 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyFourLine[] = -{ - 0x04, - 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x04, 0x11, // Node 0 - 0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, // Node 1 - 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 2 - 0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Square.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Square.c deleted file mode 100644 index b17e119d6a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Square.c +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Four node Square Topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/* - * 2---3 - * | | - * | | - * 0---1 - */ -/** - * Four Node square - */ -/** - * @dot - strict graph square4 { - node [shape="plaintext"]; - {rank=same; 0; 1} - {rank=same; 2; 3} - 0 -- 1 ; - 0 -- 2 ; - 1 -- 3 ; - 2 -- 3 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyFourSquare[] = -{ - 0x04, - 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, // Node 0 - 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, // Node 1 - 0x08, 0x00, 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, // Node 2 - 0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0x06, 0xFF // Node 3 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Star.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Star.c deleted file mode 100644 index ff08bb82fe..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph4Star.c +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Four node Star Topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* - * 2---3 - * |\ - * | \ - * 0 1 - */ -/** - * Four Node Star - */ -/** - * @dot - strict graph star4 { - node [shape="plaintext"]; - {rank=same; 0; 1} - {rank=same; 2; 3} - 0 -- 2 ; - 1 -- 2 ; - 2 -- 3 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyFourStar[] = -{ - 0x04, - 0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node 0 - 0x00, 0x22, 0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, // Node 1 - 0x0A, 0x00, 0x09, 0x11, 0x0B, 0xFF, 0x03, 0x33, // Node 2 - 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x04, 0xFF // Node 3 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph5FullyConnected.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph5FullyConnected.c deleted file mode 100644 index 5b35b90e9c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph5FullyConnected.c +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Five node Fully Connected Topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/** - * Five node fully connected - */ -/** - * @dot - strict graph full5 { - node [shape="plaintext"]; - 0 -- 1 ; - 0 -- 2 ; - 0 -- 3 ; - 0 -- 4 ; - 1 -- 2 ; - 1 -- 3 ; - 1 -- 4 ; - 2 -- 3 ; - 2 -- 4 ; - 3 -- 4 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyFiveFully[] = -{ - 0x05, - 0x1E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 0 - 0x00, 0x00, 0x1D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x1B, 0xFF, 0x00, 0x33, 0x00, 0x44, // Node 2 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x17, 0xFF, 0x00, 0x44, // Node 3 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x0F, 0xFF // Node 4 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph5TwistedLadder.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph5TwistedLadder.c deleted file mode 100644 index c0d80b002a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph5TwistedLadder.c +++ /dev/null @@ -1,89 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Five node pop order twisted ladder Topology. - * - * The population order fall back to five nodes on a twisted ladder. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* - * - * 4 - * |\ - * | \ - * 2 3 - * | | - * 0---1 - */ -/** - * Five node twisted ladder - */ -/** - * @dot - strict graph twl5 { - node [shape="plaintext"]; - {rank=same; 0; 1} - {rank=same; 2; 3} - {rank=same; 4} - 0 -- 1 ; - 0 -- 2 ; - 1 -- 3 ; - 2 -- 4 ; - 3 -- 4 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[] = -{ - 0x05, - 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x00, 0x22, // Node0 - 0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, 0x00, 0x30, // Node1 - 0x10, 0x00, 0x10, 0x00, 0x11, 0xFF, 0x00, 0x40, 0x01, 0x44, // Node2 - 0x00, 0x11, 0x00, 0x11, 0x00, 0x14, 0x12, 0xFF, 0x02, 0x44, // Node3 - 0x00, 0x22, 0x00, 0x23, 0x00, 0x22, 0x04, 0x33, 0x0C, 0xFF // Node4 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6DoubloonLower.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6DoubloonLower.c deleted file mode 100644 index 0445a71b3c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6DoubloonLower.c +++ /dev/null @@ -1,75 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Six node hydra Topology using "Doubloon/Drachma", Lower nodes remain. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/** - * 6 node hydra doubloon lower nodes, 3 MCM processors. - * For partial populations, note nodes are removed in pairs. - */ -/** - * @dot - strict graph doubloon8lower { - node [shape="plaintext"]; - 0 -- 1 ; 2 -- 3 ; 4 -- 5 ; - 0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ; - 0 -- 4 ; 1 -- 5 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[] = -{ - 0x06, - 0x16, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0 - 0x00, 0x00, 0x25, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, // Node 1 - 0x08, 0x00, 0x08, 0x11, 0x19, 0xFF, 0x03, 0x33, 0x08, 0x44, 0x00, 0x44, // Node 2 - 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x24, 0xFF, 0x00, 0x55, 0x04, 0x55, // Node 3 - 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x25, 0xFF, 0x00, 0x55, // Node 4 - 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x1A, 0xFF, // Node 5 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6DoubloonUpper.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6DoubloonUpper.c deleted file mode 100644 index e67923920d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6DoubloonUpper.c +++ /dev/null @@ -1,75 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Six node hydra Topology using "Doubloon/Drachma", Upper nodes remain. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/** - * 6 node hydra drachma, upper nodes remain, 3 MCM processors. - * For partial population cases, note that nodes are removed in pairs. - */ -/** - * @dot - strict graph doubloon6upper { - node [shape="plaintext"]; - 0 -- 1 ; 2 -- 3 ; 4 -- 5 ; - 0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ; - 0 -- 4 ; 1 -- 5 ; 2 -- 5 ; 3 -- 4 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[] = -{ - 0x06, - 0x16, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0 - 0x00, 0x00, 0x25, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, // Node 1 - 0x08, 0x00, 0x08, 0x11, 0x3B, 0xFF, 0x03, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 2 - 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x34, 0xFF, 0x00, 0x44, 0x00, 0x55, // Node 3 - 0x20, 0x00, 0x00, 0x00, 0x00, 0x22, 0x00, 0x33, 0x2D, 0xFF, 0x00, 0x55, // Node 4 - 0x00, 0x11, 0x10, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x1E, 0xFF, // Node 5 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6FullyConnected.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6FullyConnected.c deleted file mode 100644 index 5e85b68a2e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6FullyConnected.c +++ /dev/null @@ -1,86 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Six node Fully Connected Topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/** - * 6 node fully connected - */ -/** - * @dot - strict graph full6 { - node [shape="plaintext"]; - 0 -- 1 ; - 0 -- 2 ; - 0 -- 3 ; - 0 -- 4 ; - 0 -- 5 ; - 1 -- 2 ; - 1 -- 3 ; - 1 -- 4 ; - 1 -- 5 ; - 2 -- 3 ; - 2 -- 4 ; - 2 -- 5 ; - 3 -- 4 ; - 3 -- 5 ; - 4 -- 5 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologySixFully[] = -{ - 0x06, - 0x3E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 0 - 0x00, 0x00, 0x3D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x3B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 2 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x37, 0xFF, 0x00, 0x44, 0x00, 0x55, // Node 3 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x2F, 0xFF, 0x00, 0x55, // Node 4 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x1F, 0xFF // Node 5 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6TwinTriangles.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6TwinTriangles.c deleted file mode 100644 index b1e4b8bec7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6TwinTriangles.c +++ /dev/null @@ -1,92 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * A six node Topology of three MCMs. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* (2 fully connected three ways connected at the 'corners') - * - * 5 - * /| \ - * / 1 - 3 - * / / / - * 4 / / - * | \ / - * 0 - 2- - */ -/** - * Six Node hydra - */ -/** - * @dot - strict graph hmcm6 { - node [shape="plaintext"]; - subgraph even { - 0 -- 2 ; 2 -- 4 ; - 0 -- 4 ; - } - subgraph odd { - 1 -- 3 ; 3 -- 5 - 1 -- 5 ; - } - {rank=same; 0; 2; 1; 3} - {rank=same; 4; 5} - 0 -- 1 ; 2 -- 3 ; 4 -- 5 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[] = -{ - 0x06, - 0x16, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0 - 0x00, 0x00, 0x29, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x55, 0x01, 0x55, // Node 1 - 0x08, 0x00, 0x00, 0x00, 0x19, 0xFF, 0x00, 0x33, 0x08, 0x44, 0x00, 0x44, // Node 2 - 0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0x26, 0xFF, 0x00, 0x55, 0x04, 0x55, // Node 3 - 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x25, 0xFF, 0x00, 0x55, // Node 4 - 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x1A, 0xFF, // Node 5 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6TwistedLadder.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6TwistedLadder.c deleted file mode 100644 index 5e46065cec..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph6TwistedLadder.c +++ /dev/null @@ -1,92 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Six node pop order twisted ladder Topology. - * - * The population order fall back to Six nodes on a twisted ladder. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* - * - * 4 5 - * |\ /| - * |/ \| - * 2 3 - * | | - * 0---1 - */ -/** - * 6 node twisted ladder - */ -/** - * @dot - strict graph twl6 { - node [shape="plaintext"]; - {rank=same; 0; 1} - {rank=same; 2; 3} - {rank=same; 4; 5} - 0 -- 1 ; - 0 -- 2 ; - 1 -- 3 ; - 2 -- 4 ; - 2 -- 5 ; - 3 -- 4 ; - 3 -- 5 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[] = -{ - 0x06, - 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, // Node0 - 0x08, 0x00, 0x09, 0xFF, 0x00, 0x00, 0x01, 0x33, 0x00, 0x03, 0x01, 0x33, // Node1 - 0x30, 0x00, 0x00, 0x00, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x00, 0x55, // Node2 - 0x00, 0x11, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x00, 0x44, 0x12, 0x55, // Node3 - 0x00, 0x22, 0x00, 0x32, 0x08, 0x22, 0x00, 0x33, 0x0C, 0xFF, 0x00, 0x32, // Node4 - 0x00, 0x23, 0x00, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF // Node5 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph7FullyConnected.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph7FullyConnected.c deleted file mode 100644 index e97b2685de..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph7FullyConnected.c +++ /dev/null @@ -1,78 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Seven node Fully Connected Topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/** - * 7 node fully connected - */ -/** - * @dot - strict graph full7 { - node [shape="plaintext"]; - 0 -- 1 ; 1 -- 2 ; 2 -- 3 ; 3 -- 4 ; 4 -- 5 ; 5 -- 6 ; - 0 -- 2 ; 1 -- 3 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ; - 0 -- 3 ; 1 -- 4 ; 2 -- 5 ; 3 -- 6 ; - 0 -- 4 ; 1 -- 5 ; 2 -- 6 ; - 0 -- 5 ; 1 -- 6 ; - 0 -- 6 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologySevenFully[] = -{ - 0x07, - 0x7E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 0 - 0x00, 0x00, 0x7D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0x7B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 2 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x77, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 3 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x6F, 0xFF, 0x00, 0x55, 0x00, 0x66, // Node 4 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x5F, 0xFF, 0x00, 0x66, // Node 5 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x3F, 0xFF // Node 6 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph7TwistedLadder.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph7TwistedLadder.c deleted file mode 100644 index 6456ef5be2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph7TwistedLadder.c +++ /dev/null @@ -1,95 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Seven node pop order twisted ladder Topology. - * - * The population order fall back to Seven nodes on a twisted ladder. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* 6 - * | - * 4 5 - * |\ /| - * |/ \| - * 2 3 - * | | - * 0---1 - */ -/** - * 7 node twisted ladder - */ -/** - * @dot - strict graph twl7 { - node [shape="plaintext"]; - {rank=same; 0; 1} - {rank=same; 2; 3} - {rank=same; 4; 5} - {rank=same; 6} - 0 -- 1 ; - 0 -- 2 ; - 1 -- 3 ; - 2 -- 4 ; - 2 -- 5 ; - 3 -- 4 ; - 3 -- 5 ; - 4 -- 6 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[] = -{ - 0x07, - 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0 - 0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1 - 0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, // Node2 - 0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3 - 0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4 - 0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5 - 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8DoubloonM.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8DoubloonM.c deleted file mode 100644 index 92e8174514..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8DoubloonM.c +++ /dev/null @@ -1,76 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Eight node hydra Topology using "Doubloon/Drachma". - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/** - * 8 node hydra doubloon, 4 MCM processors. - */ -/** - * @dot - strict graph doubloon8 { - node [shape="plaintext"]; - 0 -- 1 ; 2 -- 3 ; 4 -- 5 ; 6 -- 7 ; - 0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ; 5 -- 6 ; - 0 -- 4 ; 1 -- 5 ; 2 -- 6 ; 3 -- 7 ; - 0 -- 6 ; 1 -- 7 ; 2 -- 7 ; 3 -- 6 - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[] = -{ - 0x08, - 0x56, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, 0x02, 0x66, 0x00, 0x66, // Node 0 - 0x00, 0x00, 0xA5, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, 0x00, 0x77, 0x01, 0x77, // Node 1 - 0x08, 0x00, 0x08, 0x11, 0xDB, 0xFF, 0x03, 0x33, 0x08, 0x44, 0x00, 0x44, 0x00, 0x66, 0x00, 0x77, // Node 2 - 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0xE4, 0xFF, 0x00, 0x55, 0x04, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 3 - 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x65, 0xFF, 0x00, 0x55, 0x00, 0x66, 0x00, 0x66, // Node 4 - 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x5A, 0xFF, 0x00, 0x66, 0x00, 0x66, // Node 5 - 0x80, 0x00, 0x00, 0x00, 0x00, 0x22, 0x00, 0x33, 0x80, 0x44, 0x80, 0x55, 0xBD, 0xFF, 0x30, 0x77, // Node 6 - 0x00, 0x11, 0x40, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x66, 0x00, 0x66, 0x00, 0x66, 0x4E, 0xFF // Node 7 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8FullyConnected.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8FullyConnected.c deleted file mode 100644 index 282f6f20fa..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8FullyConnected.c +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Eight node Fully Connected Topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/** - * 8 node fully connected - */ -/** - * @dot - strict graph full8 { - node [shape="plaintext"]; - 0 -- 1 ; 1 -- 2 ; 2 -- 3 ; 3 -- 4 ; 4 -- 5 ; 5 -- 6 ; 6 -- 7 ; - 0 -- 2 ; 1 -- 3 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ; 5 -- 7 ; - 0 -- 3 ; 1 -- 4 ; 2 -- 5 ; 3 -- 6 ; 4 -- 7 ; - 0 -- 4 ; 1 -- 5 ; 2 -- 6 ; 3 -- 7 ; - 0 -- 5 ; 1 -- 6 ; 2 -- 7 ; - 0 -- 6 ; 1 -- 7 ; - 0 -- 7 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyEightFully[] = -{ - 0x08, - 0xFE, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 0 - 0x00, 0x00, 0xFD, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 1 - 0x00, 0x00, 0x00, 0x11, 0xFB, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 2 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0xF7, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 3 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0xEF, 0xFF, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 4 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0xDF, 0xFF, 0x00, 0x66, 0x00, 0x77, // Node 5 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0xBF, 0xFF, 0x00, 0x77, // Node 6 - 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x7F, 0xFF // Node 7 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8Ladder.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8Ladder.c deleted file mode 100644 index 35f6ddf338..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8Ladder.c +++ /dev/null @@ -1,96 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Eight node Ladder Topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* 6---7 - * | | - * 4---5 - * | | - * 2---3 - * | | - * 0---1 - */ -/** - * 8 node ladder - */ -/** - * @dot - strict graph ladder8 { - node [shape="plaintext"]; - {rank=same; 0; 1} - {rank=same; 2; 3} - {rank=same; 4; 5} - {rank=same; 6; 7} - 0 -- 1 ; - 0 -- 2 ; - 1 -- 3 ; - 2 -- 4 ; - 2 -- 3 ; - 3 -- 5 ; - 4 -- 5 ; - 4 -- 6 ; - 5 -- 7 ; - 6 -- 7 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[] = -{ - 0x08, - 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, // Node0 - 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, // Node1 - 0x18, 0x00, 0x00, 0x00, 0x19, 0xFF, 0x00, 0x33, 0x09, 0x44, 0x00, 0x44, 0x09, 0x44, 0x00, 0x44, // Node2 - 0x00, 0x11, 0x24, 0x11, 0x00, 0x22, 0x26, 0xFF, 0x00, 0x55, 0x06, 0x55, 0x00, 0x55, 0x06, 0x55, // Node3 - 0x60, 0x22, 0x00, 0x22, 0x60, 0x22, 0x00, 0x22, 0x64, 0xFF, 0x00, 0x55, 0x24, 0x66, 0x00, 0x66, // Node4 - 0x00, 0x33, 0x90, 0x33, 0x00, 0x33, 0x90, 0x33, 0x00, 0x44, 0x98, 0xFF, 0x00, 0x77, 0x18, 0x77, // Node5 - 0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x90, 0xFF, 0x00, 0x77, // Node6 - 0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7 -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c deleted file mode 100644 index adb26b9023..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c +++ /dev/null @@ -1,96 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Eight node Topology of two fully connected four ways. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - - -/* (2 fully connected four ways connected at the 'corners') - * - * 5 - 7 - * /| X | - * / 1 - 3 - * / / / / - * 4 - 6 / - * | X | / - * 0 - 2- - */ -/** - * 8 node twin fully connected four ways, connected by the MCM internal links. - */ -/** - * @dot - strict graph hydra8 { - node [shape="plaintext"]; - subgraph even { - 0 -- 2 ; 2 -- 4 ; 4 -- 6 ; - 0 -- 4 ; 2 -- 6 ; - 0 -- 6 ; - } - subgraph odd { - 1 -- 3 ; 3 -- 5 ; 5 -- 7 ; - 1 -- 5 ; 3 -- 7 ; - 1 -- 7 ; - } - {rank=same; 0; 2; 1; 3} - {rank=same; 4; 6; 5; 7} - 0 -- 1 ; 2 -- 3 ; 4 -- 5 ; 6 -- 7 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[] = -{ - 0x08, - 0x56, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, 0x02, 0x66, 0x00, 0x66, // Node 0 - 0x00, 0x00, 0xA9, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x55, 0x01, 0x55, 0x00, 0x77, 0x01, 0x77, // Node 1 - 0x08, 0x00, 0x00, 0x00, 0x59, 0xFF, 0x00, 0x33, 0x08, 0x44, 0x00, 0x44, 0x08, 0x66, 0x00, 0x66, // Node 2 - 0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0xA6, 0xFF, 0x00, 0x55, 0x04, 0x55, 0x00, 0x77, 0x04, 0x77, // Node 3 - 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x65, 0xFF, 0x00, 0x55, 0x20, 0x66, 0x00, 0x66, // Node 4 - 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x9A, 0xFF, 0x00, 0x77, 0x10, 0x77, // Node 5 - 0x80, 0x00, 0x00, 0x00, 0x80, 0x22, 0x00, 0x22, 0x80, 0x44, 0x00, 0x44, 0x95, 0xFF, 0x00, 0x77, // Node 6 - 0x00, 0x11, 0x40, 0x11, 0x00, 0x33, 0x40, 0x33, 0x00, 0x55, 0x40, 0x55, 0x00, 0x66, 0x6A, 0xFF // Node 7 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8TwistedLadder.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8TwistedLadder.c deleted file mode 100644 index 84eededa82..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htGraph/htGraph8TwistedLadder.c +++ /dev/null @@ -1,95 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Eight node twisted ladder Topology. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "Porting.h" -#include "htTopologies.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/* 6---7 - * | | - * 4 5 - * |\ /| - * |/ \| - * 2 3 - * | | - * 0---1 - */ -/** - * 8 node twisted ladder - */ -/** - * @dot - strict graph twl8 { - node [shape="plaintext"]; - {rank=same; 0; 1} - {rank=same; 2; 3} - {rank=same; 4; 5} - {rank=same; 6; 7} - 0 -- 1 ; - 0 -- 2 ; - 1 -- 3 ; - 2 -- 4 ; - 2 -- 5 ; - 3 -- 4 ; - 3 -- 5 ; - 4 -- 6 ; - 5 -- 7 ; - 6 -- 7 ; - } - @enddot - * - */ -CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[] = -{ - 0x08, - 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0 - 0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1 - 0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, 0x01, 0x55, // Node2 - 0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, 0x12, 0x55, // Node3 - 0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x00, 0x32, 0x0C, 0x66, 0x00, 0x36, // Node4 - 0x80, 0x22, 0x84, 0x33, 0x80, 0x22, 0x84, 0x33, 0x00, 0x23, 0x8C, 0xFF, 0x00, 0x27, 0x0C, 0x77, // Node5 - 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x74, 0x90, 0xFF, 0x00, 0x77, // Node6 - 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x65, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7 -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.c deleted file mode 100644 index f2cae04a28..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.c +++ /dev/null @@ -1,263 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * External Interface implementation. - * - * Contains routines for implementing the interface to the client BIOS. - * This file includes the interface access constructor. - * This file implements build options using conditional compilation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "OptionsHt.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "CommonReturns.h" -#include "htInterfaceGeneral.h" -#include "htInterfaceCoherent.h" -#include "htInterfaceNonCoherent.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_HTINTERFACE_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/** - * The default initializer for the HT internal interface, full features. - */ -CONST HT_INTERFACE ROMDATA HtInterfaceDefault = -{ - GetCpu2CpuPcbLimits, - GetSkipRegang, - NewHopCountTable, - GetOverrideBusNumbers, - GetManualBuidSwapList, - GetDeviceCapOverride, - GetIoPcbLimits, - GetSocketFromMap, - GetIgnoreLink, - PostMapToAp, - NewNodeAndSocketTables, - CleanMapsAfterError, - SetNodeToSocketMap, - GetMinNbCoreFreq -}; - -/** - * The initializer for the HT internal interface, coherent only features. - */ -CONST HT_INTERFACE ROMDATA HtInterfaceCoherentOnly = -{ - GetCpu2CpuPcbLimits, - GetSkipRegang, - NewHopCountTable, - GetOverrideBusNumbers, - (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse, - (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid, - (PF_GET_IO_PCB_LIMITS)CommonVoid, - GetSocketFromMap, - GetIgnoreLink, - PostMapToAp, - NewNodeAndSocketTables, - CleanMapsAfterError, - SetNodeToSocketMap, - GetMinNbCoreFreq -}; - -/** - * The non-coherent only build option initializer for the HT internal interface. - */ -CONST HT_INTERFACE ROMDATA HtInterfaceNonCoherentOnly = -{ - (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid, - (PF_GET_SKIP_REGANG)CommonReturnFalse, - (PF_NEW_HOP_COUNT_TABLE)CommonVoid, - GetOverrideBusNumbers, - GetManualBuidSwapList, - GetDeviceCapOverride, - GetIoPcbLimits, - GetSocketFromMap, - GetIgnoreLink, - PostMapToAp, - NewNodeAndSocketTables, - (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid, - SetNodeToSocketMap, - GetMinNbCoreFreq -}; - -/** - * Topology Maps only feature build option initializer for the HT internal interface. - */ -CONST HT_INTERFACE ROMDATA HtInterfaceMapsOnly = -{ - (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid, - (PF_GET_SKIP_REGANG)CommonReturnFalse, - (PF_NEW_HOP_COUNT_TABLE)CommonVoid, - (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse, - (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse, - (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid, - (PF_GET_IO_PCB_LIMITS)CommonVoid, - (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8, - (PF_GET_IGNORE_LINK)CommonReturnFalse, - PostMapToAp, - NewNodeAndSocketTables, - (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid, - SetNodeToSocketMap, - (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8 -}; - -/** - * No features build option initializer for the HT internal interface. - */ -CONST HT_INTERFACE ROMDATA HtInterfaceNone = -{ - (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid, - (PF_GET_SKIP_REGANG)CommonReturnFalse, - (PF_NEW_HOP_COUNT_TABLE)CommonVoid, - (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse, - (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse, - (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid, - (PF_GET_IO_PCB_LIMITS)CommonVoid, - (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8, - (PF_GET_IGNORE_LINK)CommonReturnFalse, - (PF_POST_MAP_TO_AP)CommonVoid, - (PF_NEW_NODE_AND_SOCKET_TABLES)CommonVoid, - (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid, - (PF_SET_NODE_TO_SOCKET_MAP)CommonVoid, - (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8 -}; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * A constructor for the internal Ht Interface. - * - * The install has a reference to the initializer appropriate to the user selected build - * options. Use the selected initializer to construct the internal interface. - * - * @param[in,out] HtInterface Contains pointer to HT Interface structure to initialize. - * @param[in] StdHeader Opaque handle to standard config header - * -*/ -VOID -NewHtInterface ( - OUT HT_INTERFACE *HtInterface, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMemCopy ( - (VOID *) HtInterface, - (VOID *) OptionHtConfiguration.HtOptionInternalInterface, - (sizeof (HT_INTERFACE)), - StdHeader - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * A "constructor" for the HyperTransport external interface. - * - * Sets inputs to valid, basic level, defaults. - * - * Copy the initial default values from the build options tables to the interface struct. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] AmdHtInterface HT Interface structure to initialize. - * - * @retval AGESA_SUCCESS Constructors are not allowed to fail -*/ -AGESA_STATUS -AmdHtInterfaceConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_INTERFACE *AmdHtInterface - ) -{ - LibAmdMemCopy ( - (VOID *) AmdHtInterface, - (VOID *) OptionHtConfiguration.HtOptionPlatformDefaults, - (UINT32) (sizeof (AMD_HT_INTERFACE)), - StdHeader - ); - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.h deleted file mode 100644 index 783c1295ba..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.h +++ /dev/null @@ -1,488 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Internal access to HT Interface. - * - * This file provides definitions used by HT internal modules. The - * external HT interface (in agesa.h) is accessed using these methods. - * This keeps the HT Feature implementations abstracted from the HT - * interface. - * - * This file includes the interface access constructor and interface - * support which is not removed with various build options. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_INTERFACE_H_ -#define _HT_INTERFACE_H_ - -/** - * @page htimplintf HT Internal Interface Implementation Guide - * - * HT Internal Interface provides access to the HT Component external interface (see AGESA.h), - * in a manner that isolates calling code from knowledge about the external interface or which - * interfaces are supported in the current build. - * - * @par Adding a Method to HT Internal Interface - * - * To add a new method to the HT Internal Interface, follow these steps. - *
    - *
  • Create a typedef for the Method with the correct parameters and return type. - * - *
      - *
    • Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item, - * but with "_"'s and UPPERCASE, rather than mixed case. - * @n typedef VOID (F_METHOD_NAME)(); @n - * - *
    • Make a reference type for references to a method implementation: - * @n /// Reference to a Method - * @n typedef F_METHOD_NAME *PF_METHOD_NAME @n - *
    - * - *
  • Provide a standard doxygen function preamble for the Method typedef. Begin the - * detailed description by providing a reference to the method instances page by including - * the lines below: - * @code - * * - * * @HtInterfaceInstances - * * - * @endcode - * @note It is important to provide documentation for the method type, because the method may not - * have an implementation in any families supported by the current package. @n - * - *
  • Add to the HT_INTERFACE struct an item for the Method: - * @n PF_METHOD_NAME MethodName; ///< Method: description. @n - *
- * - * @par Implementing an HT Internal Interface Instance of the method. - * - * To implement an instance of a method for a specific interface follow these steps. - * - * - In appropriate files, implement the method with the return type and parameters - * matching the method typedef. - * - * - Name the function MethodName(). - * - * - Create a doxygen function preamble for the method instance. Begin the detailed description with - * an Implements command to reference the method type and add this instance to the Method Instances page. - * @code - * * - * * @HtInterfaceMethod{::F_METHOD_NAME}. - * * - * @endcode - * - * - To access other Ht internal interface routines or data as part of the method implementation, the function - * must use HtInterface->OtherMethod(). Do not directly access other HT internal interface - * routines, because in the table there may be overrides or this routine may be shared by multiple families. - * - * - Add the instance to the HT_INTERFACE instances. - * - * - If a configuration does not need an instance of the method use one of the CommonReturns from - * CommonReturns.h with the same return type. - * - * @par Invoking HT Internal Interface Methods. - * - * The first step is carried out only once by the top level HT entry point. - * @n @code - * HT_INTERFACE HtInterface; - * // Get the current HT internal interface (to HtBlock data) - * NewHtInterface (&HtInterface); - * State->HtInterface = &HtInterface; - * @endcode - * - * The following example shows how to invoke a HT Internal Interface method. - * @n @code - * State->HtInterface->MethodName (); - * @endcode - * - */ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/** - * Get limits for CPU to CPU Links. - * - * @HtInterfaceInstances. - * - * @param[in] NodeA One Node on which this Link is located - * @param[in] LinkA The Link on this Node - * @param[in] NodeB The other Node on which this Link is located - * @param[in] LinkB The Link on that Node - * @param[in,out] ABLinkWidthLimit modify to change the Link Width In - * @param[in,out] BALinkWidthLimit modify to change the Link Width Out - * @param[in,out] PcbFreqCap modify to change the Link's frequency capability - * @param[in] State the input data - * - */ -typedef VOID F_GET_CPU_2_CPU_PCB_LIMITS ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN OUT UINT8 *ABLinkWidthLimit, - IN OUT UINT8 *BALinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_CPU_2_CPU_PCB_LIMITS *PF_GET_CPU_2_CPU_PCB_LIMITS; - -/** - * Skip reganging of subLinks. - * - * @HtInterfaceInstances. - * - * @param[in] NodeA One Node on which this Link is located - * @param[in] LinkA The Link on this Node - * @param[in] NodeB The other Node on which this Link is located - * @param[in] LinkB The Link on that Node - * @param[in] State the input data - * - * @retval MATCHED leave Link unganged - * @retval POWERED_OFF leave link unganged and power off the paired sublink - * @retval UNMATCHED regang Link automatically - */ -typedef FINAL_LINK_STATE F_GET_SKIP_REGANG ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_SKIP_REGANG *PF_GET_SKIP_REGANG; - -/** - * Manually control bus number assignment. - * - * @HtInterfaceInstances. - * - * @param[in] Node The Node on which this chain is located - * @param[in] Link The Link on the host for this chain - * @param[out] SecBus Secondary Bus number for this non-coherent chain - * @param[out] SubBus Subordinate Bus number - * @param[in] State the input data - * - * @retval TRUE this routine is supplying the bus numbers - * @retval FALSE use auto Bus numbering - */ -typedef BOOLEAN F_GET_OVERRIDE_BUS_NUMBERS ( - IN UINT8 Node, - IN UINT8 Link, - OUT UINT8 *SecBus, - OUT UINT8 *SubBus, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_OVERRIDE_BUS_NUMBERS *PF_GET_OVERRIDE_BUS_NUMBERS; - -/** - * Get Manual BUID assignment list. - * - * @HtInterfaceInstances. - * - * @param[in] Node The Node on which this chain is located - * @param[in] Link The Link on the host for this chain - * @param[out] List a pointer to a list, if returns TRUE - * @param[in] State the input data - * - * @retval TRUE use manual List - * @retval FALSE initialize the Link automatically. List not valid. - */ -typedef BOOLEAN F_GET_MANUAL_BUID_SWAP_LIST ( - IN UINT8 Node, - IN UINT8 Link, - OUT BUID_SWAP_LIST **List, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_MANUAL_BUID_SWAP_LIST *PF_GET_MANUAL_BUID_SWAP_LIST; - -/** - * Override capabilities of a device. - * - * @HtInterfaceInstances. - * - * @param[in] HostNode The Node on which this chain is located - * @param[in] HostLink The Link on the host for this chain - * @param[in] Depth The Depth in the I/O chain from the Host - * @param[in] PciAddress The Device's PCI config address (for callout) - * @param[in] DevVenId The Device's PCI Vendor + Device ID (offset 0x00) - * @param[in] Revision The Device's PCI Revision - * @param[in] Link The Device's Link number (0 or 1) - * @param[in,out] LinkWidthIn modify to change the Link Width In - * @param[in,out] LinkWidthOut modify to change the Link Width Out - * @param[in,out] FreqCap modify to change the Link's frequency capability - * @param[in,out] Clumping modify to change unit id clumping capability - * @param[in] State the input data - * - */ -typedef VOID F_GET_DEVICE_CAP_OVERRIDE ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN PCI_ADDR PciAddress, - IN UINT32 DevVenId, - IN UINT8 Revision, - IN UINT8 Link, - IN OUT UINT8 *LinkWidthIn, - IN OUT UINT8 *LinkWidthOut, - IN OUT UINT32 *FreqCap, - IN OUT UINT32 *Clumping, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_DEVICE_CAP_OVERRIDE *PF_GET_DEVICE_CAP_OVERRIDE; - -/** - * Get limits for non-coherent Links. - * - * @HtInterfaceInstances. - * - * @param[in] HostNode The Node on which this Link is located - * @param[in] HostLink The Link about to be initialized - * @param[in] Depth The Depth in the I/O chain from the Host - * @param[in,out] DownstreamLinkWidthLimit modify to change the Link Width In - * @param[in,out] UpstreamLinkWidthLimit modify to change the Link Width Out - * @param[in,out] PcbFreqCap modify to change the Link's frequency capability - * @param[in] State the input data - */ -typedef VOID F_GET_IO_PCB_LIMITS ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN OUT UINT8 *DownstreamLinkWidthLimit, - IN OUT UINT8 *UpstreamLinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_IO_PCB_LIMITS *PF_GET_IO_PCB_LIMITS; - -/** - * Get the Socket number for a given Node number. - * - * @HtInterfaceInstances. - * - * @param[in] Node Node discovered event data. - * @param[in] State reference to Node to socket map - * - * @return the socket id - * - */ -typedef UINT8 F_GET_SOCKET_FROM_MAP ( - IN UINT8 Node, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_SOCKET_FROM_MAP *PF_GET_SOCKET_FROM_MAP; - -/** - * Ignore a Link. - * - * @HtInterfaceInstances. - * - * @param[in] Node The Node on which this Link is located - * @param[in] Link The Link about to be initialized - * @param[in] NbList The northbridge default ignore link list - * @param[in] State the input data - * - * @retval MATCHED ignore this Link and skip it - * @retval POWERED_OFF ignore this link and power it off. - * @retval UNMATCHED initialize the Link normally - */ -typedef FINAL_LINK_STATE F_GET_IGNORE_LINK ( - IN UINT8 Node, - IN UINT8 Link, - IN IGNORE_LINK *NbIgnoreLinkList, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_GET_IGNORE_LINK *PF_GET_IGNORE_LINK; - -/** - * Post Node id and other context info to AP cores via mailbox. - * - * @HtInterfaceInstances. - * - * @param[in] State Our state - */ -typedef VOID F_POST_MAP_TO_AP ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_POST_MAP_TO_AP *PF_POST_MAP_TO_AP; - -/** - * Clean up the map structures after severe event has caused a fall back to 1 node. - * - * @HtInterfaceInstances. - * - * @param[in] State Our state - */ -typedef VOID F_CLEAN_MAPS_AFTER_ERROR ( - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_CLEAN_MAPS_AFTER_ERROR *PF_CLEAN_MAPS_AFTER_ERROR; - -/** - * Get a new Socket Die to Node Map. - * - * @HtInterfaceInstances. - * - * @param[in,out] State global state - */ -typedef VOID F_NEW_NODE_AND_SOCKET_TABLES ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_NEW_NODE_AND_SOCKET_TABLES *PF_NEW_NODE_AND_SOCKET_TABLES; - -/** - * Fill in the socket's Node id when a processor is discovered in that socket. - * - * @HtInterfaceInstances. - * - * @param[in] Node Node from which a new node was discovered - * @param[in] CurrentNodeModule The current node's module id in it's processor. - * @param[in] PackageLink The package level link from Node to NewNode. - * @param[in] NewNode The new node's id - * @param[in] HardwareSocket If we use the hardware method (preferred), this is the socket of new node. - * @param[in] Module The new node's module id in it's processor. - * @param[in] State our State - */ -typedef VOID F_SET_NODE_TO_SOCKET_MAP ( - IN UINT8 Node, - IN UINT8 CurrentNodeModule, - IN UINT8 PackageLink, - IN UINT8 NewNode, - IN UINT8 HardwareSocket, - IN UINT8 Module, - IN STATE_DATA *State - ); -/// Reference to a method. -typedef F_SET_NODE_TO_SOCKET_MAP *PF_SET_NODE_TO_SOCKET_MAP; - -/** - * Get a new, empty Hop Count Table, to make one for the installed topology. - * - * @HtInterfaceInstances. - * - * @param[in,out] State Keep our buffer handle. - * - */ -typedef VOID F_NEW_HOP_COUNT_TABLE ( - IN OUT STATE_DATA *State - ); -/// Reference to a method. -typedef F_NEW_HOP_COUNT_TABLE *PF_NEW_HOP_COUNT_TABLE; - -/** - * Get the minimum Northbridge frequency for the system. - * - * @HtInterfaceInstances. - * - * Invoke the CPU component power mgt interface. - * - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] StdHeader Config for library and services. - * - * @return Frequency in MHz. - * - */ -typedef UINT32 F_GET_MIN_NB_CORE_FREQ ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); -/// Reference to a Method. -typedef F_GET_MIN_NB_CORE_FREQ *PF_GET_MIN_NB_CORE_FREQ; - -/** - * The HT Interface, feature code uses these methods to get interface parameters. - */ -struct _HT_INTERFACE { // See Forward Declaration in HtFeates.h - PF_GET_CPU_2_CPU_PCB_LIMITS GetCpu2CpuPcbLimits; /**< Method: Get link limits for coherent links. */ - PF_GET_SKIP_REGANG GetSkipRegang; /**< Method: Skip reganging for coherent links. */ - PF_NEW_HOP_COUNT_TABLE NewHopCountTable; /**< Method: Get a new hop count table. */ - PF_GET_OVERRIDE_BUS_NUMBERS GetOverrideBusNumbers; /**< Method: Control Bus number assignment. */ - PF_GET_MANUAL_BUID_SWAP_LIST GetManualBuidSwapList; /**< Method: Assign device IDs. */ - PF_GET_DEVICE_CAP_OVERRIDE GetDeviceCapOverride; /**< Method: Override Device capabilities. */ - PF_GET_IO_PCB_LIMITS GetIoPcbLimits; /**< Method: Get link limits for noncoherent links. */ - PF_GET_SOCKET_FROM_MAP GetSocketFromMap; /**< Method: Get the Socket for a node id. */ - PF_GET_IGNORE_LINK GetIgnoreLink; /**< Method: Ignore a link. */ - PF_POST_MAP_TO_AP PostMapToAp; /**< Method: Post Socket and other info to AP cores. */ - PF_NEW_NODE_AND_SOCKET_TABLES NewNodeAndSocketTables; /**< Method: Get new socket and node maps. */ - PF_CLEAN_MAPS_AFTER_ERROR CleanMapsAfterError; /**< Method: Clean up maps for forced 1P on error fall back. */ - PF_SET_NODE_TO_SOCKET_MAP SetNodeToSocketMap; /**< Method: Associate a node id with a socket. */ - PF_GET_MIN_NB_CORE_FREQ GetMinNbCoreFreq; /**< Method: Get the minimum northbridge frequency */ -} ; - -/*---------------------------------------------------------------------------- - * Prototypes to Interface from Feature Code - * - *---------------------------------------------------------------------------- - */ - -/** - * A constructor for the internal Ht Interface. - * -*/ -VOID -NewHtInterface ( - OUT HT_INTERFACE *HtInterface, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif /* _HT_INTERFACE_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceCoherent.c deleted file mode 100644 index 87819dc2d8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceCoherent.c +++ /dev/null @@ -1,264 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * External Interface implementation for coherent features. - * - * Contains routines for accessing the interface to the client BIOS, - * for support only required for coherent features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htInterfaceGeneral.h" -#include "htInterfaceCoherent.h" -#include "htNb.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_HTINTERFACECOHERENT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------------------*/ -/** - * Get limits for CPU to CPU Links. - * - * @HtInterfaceMethod{::F_GET_CPU_2_CPU_PCB_LIMITS} - * - * For each coherent connection this routine is called once. Update the frequency - * and width if needed for this Link (usually based on board restriction). This is - * used with CPU device capabilities and northbridge limits to compute the default - * settings. The input width and frequency are valid, but do not necessarily reflect - * the minimum setting that will be chosen. - * - * @param[in] NodeA One Node on which this Link is located - * @param[in] LinkA The Link on this Node - * @param[in] NodeB The other Node on which this Link is located - * @param[in] LinkB The Link on that Node - * @param[in,out] ABLinkWidthLimit modify to change the Link Width In - * @param[in,out] BALinkWidthLimit modify to change the Link Width Out - * @param[in,out] PcbFreqCap modify to change the Link's frequency capability - * @param[in] State the input data - * - */ -VOID -GetCpu2CpuPcbLimits ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN OUT UINT8 *ABLinkWidthLimit, - IN OUT UINT8 *BALinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ) -{ - CPU_TO_CPU_PCB_LIMITS *p; - UINT8 SocketA; - UINT8 SocketB; - UINT8 PackageLinkA; - UINT8 PackageLinkB; - - ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES)); - ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks)); - - SocketA = State->HtInterface->GetSocketFromMap (NodeA, State); - PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb); - SocketB = State->HtInterface->GetSocketFromMap (NodeB, State); - PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb); - - if (State->HtBlock->CpuToCpuPcbLimitsList != NULL) { - p = State->HtBlock->CpuToCpuPcbLimitsList; - - while (p->SocketA != HT_LIST_TERMINAL) { - if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) && - ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) || - ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) && - ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) && - ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) || - ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) { - // Found a match, update width and frequency - *ABLinkWidthLimit = p->ABLinkWidthLimit; - *BALinkWidthLimit = p->BALinkWidthLimit; - *PcbFreqCap = p->PcbFreqCap; - break; - } else { - p++; - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Skip reganging of subLinks. - * - * @HtInterfaceMethod{::F_GET_SKIP_REGANG} - * - * This routine is called whenever two subLinks are both connected to the same CPUs. - * Normally, unganged sublinks between the same two CPUs are reganged. Return true - * from this routine to leave the Links unganged. - * - * @param[in] NodeA One Node on which this Link is located - * @param[in] LinkA The Link on this Node - * @param[in] NodeB The other Node on which this Link is located - * @param[in] LinkB The Link on that Node - * @param[in] State the input data - * - * @retval MATCHED leave Link unganged - * @retval POWERED_OFF leave link unganged and power off the paired sublink - * @retval UNMATCHED regang Link automatically - */ -FINAL_LINK_STATE -GetSkipRegang ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN STATE_DATA *State - ) -{ - SKIP_REGANG *p; - FINAL_LINK_STATE Result; - UINT8 SocketA; - UINT8 SocketB; - UINT8 PackageLinkA; - UINT8 PackageLinkB; - - ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES)); - ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks)); - - Result = UNMATCHED; - SocketA = State->HtInterface->GetSocketFromMap (NodeA, State); - PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb); - SocketB = State->HtInterface->GetSocketFromMap (NodeB, State); - PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb); - - if (State->HtBlock->SkipRegangList != NULL) { - p = State->HtBlock->SkipRegangList; - - while (p->SocketA != HT_LIST_TERMINAL) { - if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) && - ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) || - ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) && - ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) && - ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) || - ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) { - // Found a match return final link state - Result = p->LinkState; - break; - } else { - p++; - } - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get a new, empty Hop Count Table, to make one for the installed topology. - * - * @HtInterfaceMethod{::F_NEW_HOP_COUNT_TABLE} - * - * For SLIT, publish a matrix with the hop count, by allocating a buffer on heap with a - * known signature. - * - * @param[in,out] State Keep our buffer handle. - * - */ -VOID -NewHopCountTable ( - IN OUT STATE_DATA *State - ) -{ - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - AllocHeapParams.RequestedBufferSize = sizeof (HOP_COUNT_TABLE); - AllocHeapParams.BufferHandle = HOP_COUNT_TABLE_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer ( &AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) { - State->HopCountTable = (HOP_COUNT_TABLE *)AllocHeapParams.BufferPtr; - } else { - State->HopCountTable = NULL; - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceCoherent.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceCoherent.h deleted file mode 100644 index defce7dcc3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceCoherent.h +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Internal access to HT Interface for coherent features. - * - * This file provides definitions used by HT internal modules. The - * external HT interface (in agesa.h) is accessed using these methods. - * This keeps the HT Feature implementations abstracted from the HT - * interface. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_INTERFACE_COHERENT_H_ -#define _HT_INTERFACE_COHERENT_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Prototypes to Interface from Feature Code - * - *---------------------------------------------------------------------------- - */ - -/** - * Get limits for CPU to CPU Links. - * - */ -VOID -GetCpu2CpuPcbLimits ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN OUT UINT8 *ABLinkWidthLimit, - IN OUT UINT8 *BALinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ); - -/** - * Skip reganging of subLinks. - * - */ -FINAL_LINK_STATE -GetSkipRegang ( - IN UINT8 NodeA, - IN UINT8 LinkA, - IN UINT8 NodeB, - IN UINT8 LinkB, - IN STATE_DATA *State - ); - -/** - * Get a new, empty Hop Count Table, to make one for the installed topology. - * - */ -VOID -NewHopCountTable ( - IN OUT STATE_DATA *State - ); - -#endif /* _HT_INTERFACE_COHERENT_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceGeneral.c deleted file mode 100644 index 0e7c0d2116..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceGeneral.c +++ /dev/null @@ -1,539 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * External Interface implementation, general purpose features. - * - * Contains routines for implementing the interface to the client BIOS. This file - * includes the interface support which is not removed with various build options. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMultiSocket.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htInterfaceGeneral.h" -#include "htNb.h" -#include "cpuServices.h" -#include "cpuFeatures.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_HTINTERFACEGENERAL_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Is PackageLink an Internal Link? - * - * This is a test for the logical link match codes in the user interface, not a test for - * the actual northbridge links. - * - * @param[in] PackageLink The link - * - * @retval TRUE This is an internal link - * @retval FALSE This is not an internal link - */ -BOOLEAN -IsPackageLinkInternal ( - IN UINT8 PackageLink - ) -{ - return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0)); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Ignore a Link. - * - * @HtInterfaceMethod{::F_GET_IGNORE_LINK} - * - * This routine is called every time a coherent Link is found and then every time a - * non-coherent Link from a CPU is found. Any coherent or non-coherent Link from a - * CPU can be ignored and not used for discovery or initialization. Useful for - * connection based systems. - * - * @note not called for IO device to IO Device Links. - * - * @param[in] Node The Node on which this Link is located - * @param[in] Link The Link about to be initialized - * @param[in] NbIgnoreLinkList The northbridge default ignore link list - * @param[in] State the input data - * - * @retval MATCHED ignore this Link and skip it - * @retval POWERED_OFF ignore this link and power it off. - * @retval UNMATCHED initialize the Link normally - */ -FINAL_LINK_STATE -GetIgnoreLink ( - IN UINT8 Node, - IN UINT8 Link, - IN IGNORE_LINK *NbIgnoreLinkList, - IN STATE_DATA *State - ) -{ - IGNORE_LINK *p; - FINAL_LINK_STATE Result; - BOOLEAN IsFound; - UINT8 Socket; - UINT8 PackageLink; - - ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES)); - - Result = UNMATCHED; - IsFound = FALSE; - Socket = State->HtInterface->GetSocketFromMap (Node, State); - PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb); - - if (State->HtBlock->IgnoreLinkList != NULL) { - p = State->HtBlock->IgnoreLinkList; - while (p->Socket != HT_LIST_TERMINAL) { - if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) && - ((p->Link == PackageLink) || - ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) || - ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) { - // Found a match return the desired link state. - ASSERT (Result < MaxFinalLinkState); - Result = p->LinkState; - IsFound = TRUE; - break; - } else { - p++; - } - } - } - // If there wasn't a match in the user interface, see if the northbridge provides one. - if (!IsFound && (NbIgnoreLinkList != NULL)) { - p = NbIgnoreLinkList; - while (p->Socket != HT_LIST_TERMINAL) { - if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) && - ((p->Link == PackageLink) || - ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) || - ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) { - // Found a match return the desired link state. - ASSERT (Result < MaxFinalLinkState); - Result = p->LinkState; - break; - } else { - p++; - } - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the Socket number for a given Node number. - * - * @HtInterfaceMethod{::F_GET_SOCKET_FROM_MAP} - * - * Return the id. - * - * @param[in] Node The Node to translate - * @param[in] State reference to Node to socket map - * - * @return the socket id - * - */ -UINT8 -GetSocketFromMap ( - IN UINT8 Node, - IN STATE_DATA *State - ) -{ - UINT8 Socket; - - ASSERT (State->NodeToSocketDieMap != NULL); - - Socket = (*State->NodeToSocketDieMap)[Node].Socket; - return Socket; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get a new Socket Die to Node Map. - * - * @HtInterfaceMethod{::F_NEW_NODE_AND_SOCKET_TABLES} - * - * Put the Socket Die Table in heap with a known handle. Content will be generated as - * each node is discovered. - * - * @param[in,out] State global state - */ -VOID -NewNodeAndSocketTables ( - IN OUT STATE_DATA *State - ) -{ - UINT8 i; - UINT8 j; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - // Allocate heap for the table - State->SocketDieToNodeMap = NULL; - AllocHeapParams.RequestedBufferSize = (((MAX_SOCKETS) * (MAX_DIES)) * sizeof (SOCKET_DIE_TO_NODE_ITEM)); - AllocHeapParams.BufferHandle = SOCKET_DIE_MAP_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) { - State->SocketDieToNodeMap = (SOCKET_DIE_TO_NODE_MAP)AllocHeapParams.BufferPtr; - // Initialize shared data structures - for (i = 0; i < MAX_SOCKETS; i++) { - for (j = 0; j < MAX_DIES; j++) { - (*State->SocketDieToNodeMap)[i][j].Node = HT_LIST_TERMINAL; - (*State->SocketDieToNodeMap)[i][j].LowCore = HT_LIST_TERMINAL; - (*State->SocketDieToNodeMap)[i][j].HighCore = HT_LIST_TERMINAL; - } - } - } - // Allocate heap for the table - State->NodeToSocketDieMap = NULL; - AllocHeapParams.RequestedBufferSize = (MAX_NODES * sizeof (NODE_TO_SOCKET_DIE_ITEM)); - AllocHeapParams.BufferHandle = NODE_ID_MAP_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) { - State->NodeToSocketDieMap = (NODE_TO_SOCKET_DIE_MAP)AllocHeapParams.BufferPtr; - // Initialize shared data structures - for (i = 0; i < MAX_NODES; i++) { - (*State->NodeToSocketDieMap)[i].Socket = HT_LIST_TERMINAL; - (*State->NodeToSocketDieMap)[i].Die = HT_LIST_TERMINAL; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get the minimum Northbridge frequency for the system. - * - * @HtInterfaceMethod{::F_GET_MIN_NB_CORE_FREQ} - * - * Invoke the CPU component power mgt interface. - * - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] StdHeader Config for library and services. - * - * @return Frequency in MHz. - * - */ -UINT32 -GetMinNbCoreFreq ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MinSysNbFreq; - UINT32 MinP0NbFreq; - - OptionMultiSocketConfiguration.GetMinNbCof (PlatformConfig, &MinSysNbFreq, &MinP0NbFreq, StdHeader); - - ASSERT (MinSysNbFreq != 0); - - return MinSysNbFreq; -} - -/** - * @page physicalsockethowto Physical Socket Map, How To Create - * - * To create a physical system socket map for a platform: - * - * - Start at the Node which will be the BSP. - * - * - Begin a breadth first enumeration of all the coherent Links between sockets - * by creating a socket structure for each socket connection from the BSP. - * For example, if the BSP is in socket zero and Link one connects to socket two, - * create socket {0, 1, 2}. - * - * - When all Links from the BSP are described, go to the first socket connected - * to the BSP and continue the breadth first enumeration. - * - * - It should not be necessary to describe the back Links; in the example above, there - * should be no need to create {2, 1, 0} (assuming socket two connects back to - * socket zero on its Link one). - * - * - When completed: - * - * - Every socket except the BSP's (usually zero) must be listed as a targetSocket, - * at least once. Some sockets may be listed more than once. - * - * - There usually should be at least as many entries as Links. An exception is a - * fully connected system, only the Links from the BSP are needed. - * - * - Every socket but the last one in the breadth first order should usually have one - * or more entries listing it as a currentSocket. (The last one has only back Links.) - * - * There are no strict assumptions about the ordering of the socket structures. - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Update maps between Sockets and Nodes for a specific newly discovered node. - * - * @HtInterfaceMethod{::F_SET_NODE_TO_SOCKET_MAP} - * - * There are two methods for providing socket naming of nodes. - * - * Hardware Method (preferred): A value strapped in hardware by the board is read and - * passed to this routine. - * - * Software Method: The current node's socket is looked up, since it was - * previously a new node and went through this process. The link is converted to - * a package level link. A user data structure describing the package level - * layout of the system is searched for the current node's socket and package link, - * and now we know the new node's socket. - * - * In either case, the Socket, Module to Node map and the Node to Socket, Module - * map are updated with the new node, socket, and module. - * - * Data needed to do this is passed in to the routine as arguments rather than read by this routine, - * so that it is not necessary to know a valid temporary route to either node at the time this code runs. - * - * @param[in] Node Node from which a new node was discovered - * @param[in] CurrentNodeModule The current node's module id in it's processor. - * @param[in] PackageLink The package link for the current node's link. - * @param[in] NewNode The new node's id - * @param[in] HardwareSocket If we use the hardware method (preferred), this is the socket of new node. - * @param[in] Module The new node's module id in it's processor. - * @param[in] State our State - */ -VOID -SetNodeToSocketMap ( - IN UINT8 Node, - IN UINT8 CurrentNodeModule, - IN UINT8 PackageLink, - IN UINT8 NewNode, - IN UINT8 HardwareSocket, - IN UINT8 Module, - IN STATE_DATA *State - ) -{ - UINT8 SourceSocket; - UINT8 TargetSocket; - SYSTEM_PHYSICAL_SOCKET_MAP *Map; - - // While this code could be written to recover from a NULL socket map, AGESA cannot function without one. - ASSERT (State->SocketDieToNodeMap != NULL); - - if (State->HtBlock->SystemPhysicalSocketMap != NULL) { - if (NewNode != 0) { - // Find the logical Node from which a new Node was discovered in the Node field of - // some socket. It must already be there, Nodes are assigned ascending. - // - for (SourceSocket = 0; SourceSocket < MAX_SOCKETS; SourceSocket++) { - if ((*State->SocketDieToNodeMap)[SourceSocket][CurrentNodeModule].Node == Node) { - break; - } - } - // This ASSERT should be understood as "the Node did not have a match", not as a limit check on SourceSocket. - ASSERT (SourceSocket != MAX_SOCKETS); - - // Find the sourceSocket in the CurrentSocket field, for the Link on which a new Node - // was discovered. When we find an entry with that socket and Link number, update the - // Node for that socket. - // - if (IsPackageLinkInternal (PackageLink)) { - // Internal Nodes are in the same socket, don't search the physical system map. - TargetSocket = SourceSocket; - } else { - // Find the target socket in the physical system map. - Map = State->HtBlock->SystemPhysicalSocketMap; - while ((Map->CurrentSocket != 0xFF) && - ((Map->CurrentSocket != SourceSocket) || (Map->CurrentLink != PackageLink))) { - Map++; - } - ASSERT (Map->CurrentSocket != 0xFF); - TargetSocket = Map->TargetSocket; - } - } else { - // The BSP (BSN, if you will) has no predecessor node from which it is discovered. - TargetSocket = 0; - } - } else { - // Use the hardware method - // The hardware strapped socket id is passed to us in this case. - TargetSocket = HardwareSocket; - } - // If the target socket, module is already mapped to something, that's not good. Socket labeling conflict. - // Check that the board is strapped correctly. If not you need a SystemPhysicalSocketMap. If you have one, - // check it for correctness. - ASSERT ((*State->SocketDieToNodeMap)[TargetSocket][Module].Node == 0xFF); - // Update the map for the rest of agesa - (*State->SocketDieToNodeMap)[TargetSocket][Module].Node = NewNode; - // and the node to socket map - ASSERT (State->NodeToSocketDieMap != NULL); - (*State->NodeToSocketDieMap)[NewNode].Socket = TargetSocket; - (*State->NodeToSocketDieMap)[NewNode].Die = Module; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Clean up the map structures after severe event has caused a fall back to 1 node. - * - * @HtInterfaceMethod{::F_CLEAN_MAPS_AFTER_ERROR} - * - * @param[in] State Our state, access to socket, node maps - * - */ -VOID -CleanMapsAfterError ( - IN STATE_DATA *State - ) -{ - UINTN Socket; - UINTN Module; - UINTN Node; - - ASSERT (State->NodeToSocketDieMap != NULL); - ASSERT (State->SocketDieToNodeMap != NULL); - - // Clear all the socket, module items except for the socket and module containing node zero. - for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { - for (Module = 0; Module < MAX_DIES; Module++) { - if (((*State->NodeToSocketDieMap)[0].Socket != Socket) || ((*State->NodeToSocketDieMap)[0].Die != Module)) { - (*State->SocketDieToNodeMap)[Socket][Module].Node = HT_LIST_TERMINAL; - (*State->SocketDieToNodeMap)[Socket][Module].LowCore = HT_LIST_TERMINAL; - (*State->SocketDieToNodeMap)[Socket][Module].HighCore = HT_LIST_TERMINAL; - } - } - } - // Clear all the node items except for node zero. - for (Node = 1; Node < MAX_NODES; Node++) { - (*State->NodeToSocketDieMap)[Node].Socket = HT_LIST_TERMINAL; - (*State->NodeToSocketDieMap)[Node].Die = HT_LIST_TERMINAL; - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Post Node id and other context info to AP cores via mailbox. - * - * @HtInterfaceMethod{::F_POST_MAP_TO_AP} - * - * Since Ap's can not view map until after mp communication is established, - * provide them with initial context info via a mailbox register. A mailbox - * register is one that can be written in PCI space and read in MSR space. - * - * @param[in] State Our state, access to socket, node maps - */ -VOID -PostMapToAp ( - IN STATE_DATA *State - ) -{ - UINT8 ModuleType; - UINT8 Module; - AP_MAILBOXES ApMailboxes; - UINT8 Node; - UINT32 Degree; - AGESA_STATUS CalledStatus; - - // Dispatch any features (such as Preserve Mailbox) that need to run as soon as discovery is completed. - IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after HT discovery\n"); - CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_COHERENT_DISCOVERY, State->PlatformConfiguration, State->ConfigHandle); - - ASSERT (State->Fabric != NULL); - Degree = 0; - // Compute the degree of the system by finding the maximum degree of any node. - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - if (State->Fabric->SysDegree[Node] > Degree) { - Degree = State->Fabric->SysDegree[Node]; - } - } - // Post the information on all nodes. - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - ModuleType = 0; - Module = 0; - State->Nb->GetModuleInfo (Node, &ModuleType, &Module, State->Nb); - ApMailboxes.ApMailInfo.Info = 0; - ApMailboxes.ApMailInfo.Fields.Node = Node; - ApMailboxes.ApMailInfo.Fields.Socket = State->HtInterface->GetSocketFromMap (Node, State); - ApMailboxes.ApMailInfo.Fields.ModuleType = ModuleType; - ApMailboxes.ApMailInfo.Fields.Module = Module; - ApMailboxes.ApMailExtInfo.Info = 0; - ApMailboxes.ApMailExtInfo.Fields.SystemDegree = Degree; - // other fields of the extended info are used during ap init, and will be initialized at that time. - State->Nb->PostMailbox (Node, ApMailboxes, State->Nb); - } - // Now that the mailboxes have been initialized, cache the info on the BSC. The APs - // will cache during heap initialization. - CacheApMailbox (State->ConfigHandle); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceGeneral.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceGeneral.h deleted file mode 100644 index d4ee3dd336..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceGeneral.h +++ /dev/null @@ -1,160 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Internal access to HT Interface, general purpose features. - * - * This file provides definitions used by HT internal modules. The - * external HT interface (in agesa.h) is accessed using these methods. - * This keeps the HT Feature implementations abstracted from the HT - * external interface. - * - * This file includes the interface support which is not removed with - * various build options. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_INTERFACE_GENERAL_H_ -#define _HT_INTERFACE_GENERAL_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Prototypes to Interface from Feature Code - * - *---------------------------------------------------------------------------- - */ - -/** - * Is PackageLink an Internal Link? - */ -BOOLEAN -IsPackageLinkInternal ( - IN UINT8 PackageLink - ); - -/** - * Get the Socket number for a given Node number. - * - */ -UINT8 -GetSocketFromMap ( - IN UINT8 Node, - IN STATE_DATA *State - ); - -/** - * Ignore a Link. - * - */ -FINAL_LINK_STATE -GetIgnoreLink ( - IN UINT8 Node, - IN UINT8 Link, - IN IGNORE_LINK *NbIgnoreLinkList, - IN STATE_DATA *State - ); - -/** - * Get a new Socket Die to Node Map. - * - */ -VOID -NewNodeAndSocketTables ( - IN OUT STATE_DATA *State - ); - -/** - * Get the minimum Northbridge frequency for the system. - * - */ -UINT32 -GetMinNbCoreFreq ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * Fill in the socket's Node id when a processor is discovered in that socket. - * - */ -VOID -SetNodeToSocketMap ( - IN UINT8 Node, - IN UINT8 CurrentNodeModule, - IN UINT8 PackageLink, - IN UINT8 NewNode, - IN UINT8 HardwareSocket, - IN UINT8 Module, - IN STATE_DATA *State - ); - -/** - * Clean up the map structures after severe event has caused a fall back to 1 node. - * - */ -VOID -CleanMapsAfterError ( - IN STATE_DATA *State - ); - -/** - * Post Node id and other context info to AP cores via mailbox. - * - */ -VOID -PostMapToAp ( - IN STATE_DATA *State - ); - -#endif /* _HT_INTERFACE_GENERAL_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c deleted file mode 100644 index c075e15271..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c +++ /dev/null @@ -1,394 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * External Interface implementation for non-coherent features. - * - * Contains routines for accessing the interface to the client BIOS, - * for non-coherent features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htInterfaceNonCoherent.h" -#include "htNb.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_HTINTERFACENONCOHERENT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_ZERO_32 ((UINT32)0) - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Manual BUID assignment list. - * - * @HtInterfaceMethod{::F_GET_MANUAL_BUID_SWAP_LIST} - * - * This routine is called every time a non-coherent chain is processed. BUID - * assignment may be controlled explicitly on a non-coherent chain. Swaps controls - * the BUID assignment and FinalIds provides the device to device Linking. Device - * orientation can be detected automatically, or explicitly. See documentation for - * more details. - * - * If a manual swap list is not supplied, automatic non-coherent init assigns BUIDs - * starting at 1 and incrementing sequentially based on each device's unit count. - * - * @param[in] Node The Node on which this chain is located - * @param[in] Link The Link on the host for this chain - * @param[out] List supply a pointer to a list. - * List is NOT valid unless routine returns TRUE. - * @param[in] State the input data - * - * @retval TRUE use a manual list - * @retval FALSE initialize the Link automatically - */ -BOOLEAN -GetManualBuidSwapList ( - IN UINT8 Node, - IN UINT8 Link, - OUT BUID_SWAP_LIST **List, - IN STATE_DATA *State - ) -{ - MANUAL_BUID_SWAP_LIST *p; - BOOLEAN result; - UINT8 Socket; - UINT8 PackageLink; - - ASSERT ((Node < MAX_NODES) && (List != NULL)); - - result = FALSE; - Socket = State->HtInterface->GetSocketFromMap (Node, State); - PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb); - - if (State->HtBlock->ManualBuidSwapList != NULL) { - p = State->HtBlock->ManualBuidSwapList; - - while (p->Socket != HT_LIST_TERMINAL) { - if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) && - ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) { - // Found a match implies TRUE, ignore the Link - result = TRUE; - *List = &(p->SwapList); - break; - } else { - p++; - } - } - } - // List is not valid if Result is FALSE. - return result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Override capabilities of a device. - * - * @HtInterfaceMethod{::F_GET_DEVICE_CAP_OVERRIDE} - * - * This routine is called once for every Link on every IO device. Update the width - * and frequency capability if needed for this device. This is used along with - * device capabilities, the limit call backs, and northbridge limits to compute the - * default settings. The components of the device's PCI config address are provided, - * so its settings can be consulted if need be. The input width and frequency are the - * reported device capabilities. - * - * @param[in] HostNode The Node on which this chain is located - * @param[in] HostLink The Link on the host for this chain - * @param[in] Depth The Depth in the I/O chain from the Host - * @param[in] PciAddress The Device's PCI config address (for callout) - * @param[in] DevVenId The Device's PCI Vendor + Device ID (offset 0x00) - * @param[in] Revision The Device's PCI Revision - * @param[in] Link The Device's Link number (0 or 1) - * @param[in,out] LinkWidthIn modify to change the Link Width In - * @param[in,out] LinkWidthOut modify to change the Link Width Out - * @param[in,out] FreqCap modify to change the Link's frequency capability - * @param[in,out] Clumping modify to change unit id clumping capability - * @param[in] State the input data and config header - * - */ -VOID -GetDeviceCapOverride ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN PCI_ADDR PciAddress, - IN UINT32 DevVenId, - IN UINT8 Revision, - IN UINT8 Link, - IN OUT UINT8 *LinkWidthIn, - IN OUT UINT8 *LinkWidthOut, - IN OUT UINT32 *FreqCap, - IN OUT UINT32 *Clumping, - IN STATE_DATA *State - ) -{ - DEVICE_CAP_OVERRIDE *p; - UINT8 HostSocket; - UINT8 PackageLink; - DEVICE_CAP_CALLOUT_PARAMS CalloutParams; - AGESA_STATUS CalloutStatus; - - ASSERT ((HostNode < MAX_NODES) && (Depth < 32) && ((Link == 0) || (Link == 1))); - - HostSocket = State->HtInterface->GetSocketFromMap (HostNode, State); - PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb); - - if (State->HtBlock->DeviceCapOverrideList != NULL) { - p = State->HtBlock->DeviceCapOverrideList; - - while (p->HostSocket != HT_LIST_TERMINAL) { - if (((p->HostSocket == HostSocket) || (p->HostSocket == HT_LIST_MATCH_ANY)) && - ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) && - ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY)) && - ((p->Link == Link) || (p->Link == HT_LIST_MATCH_ANY)) && - // Found a potential match. Check the additional optional matches. - ((p->Options.IsCheckDevVenId == 0) || (p->DevVenId == DevVenId)) && - ((p->Options.IsCheckRevision == 0) || (p->Revision == Revision))) { - // - // Found a match. Check what override actions are desired. - // Unlike the PCB limit routines, which handle the info returned, - // deviceCapOverride is actually overriding the settings, so we need - // to check that the field actually has an update. - // The Callout is a catch all for situations the data is not up to handling. - // It is expected, but not enforced, that either the data overrides are used, - // or the callout is used, rather than both. - // - if (p->Options.IsOverrideWidthIn != 0) { - *LinkWidthIn = p->LinkWidthIn; - } - if (p->Options.IsOverrideWidthOut != 0) { - *LinkWidthOut = p->LinkWidthOut; - } - if (p->Options.IsOverrideFreq != 0) { - *FreqCap = p->FreqCap; - } - if (p->Options.IsOverrideClumping != 0) { - *Clumping = p->Clumping; - } - if (p->Options.IsDoCallout != 0) { - // - // Pass the actual info being matched, not the matched struct data. - // This callout is expected to be built in as part of the options file, and does not use the - // callout interface, even though we use the consistent interface declaration for the routine. - // So, the first two int parameters have no meaning in this case. - // It is not meaningful for the callout to have any status but Success. - // - CalloutParams.HostSocket = HostSocket; - CalloutParams.HostLink = PackageLink; - CalloutParams.Depth = Depth; - CalloutParams.DevVenId = DevVenId; - CalloutParams.Revision = Revision; - CalloutParams.Link = Link; - CalloutParams.PciAddress = PciAddress; - CalloutParams.LinkWidthIn = LinkWidthIn; - CalloutParams.LinkWidthOut = LinkWidthOut; - CalloutParams.FreqCap = FreqCap; - CalloutParams.Clumping = Clumping; - CalloutParams.StdHeader = *((AMD_CONFIG_PARAMS *) (State->ConfigHandle)); - CalloutStatus = p->Callout (UNUSED_ZERO_32, UNUSED_ZERO_32, (VOID *) &CalloutParams); - ASSERT (CalloutStatus == AGESA_SUCCESS); - } - break; - } else { - p++; - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get limits for non-coherent Links. - * - * @HtInterfaceMethod{::F_GET_IO_PCB_LIMITS} - * - * For each non-coherent connection this routine is called once. Update the - * frequency and width if needed for this Link (usually based on board restriction). - * This is used with device capabilities, device overrides, and northbridge limits to - * compute the default settings. The input width and frequency are valid, but do not - * necessarily reflect the minimum setting that will be chosen. - * - * @param[in] HostNode The Node on which this Link is located - * @param[in] HostLink The Link about to be initialized - * @param[in] Depth The Depth in the I/O chain from the Host - * @param[in,out] DownstreamLinkWidthLimit modify to change the Link Width In - * @param[in,out] UpstreamLinkWidthLimit modify to change the Link Width Out - * @param[in,out] PcbFreqCap modify to change the Link's frequency capability - * @param[in] State the input data - */ -VOID -GetIoPcbLimits ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN OUT UINT8 *DownstreamLinkWidthLimit, - IN OUT UINT8 *UpstreamLinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ) -{ - IO_PCB_LIMITS *p; - UINT8 Socket; - UINT8 PackageLink; - - ASSERT ((HostNode < MAX_NODES) && (HostLink < MAX_NODES)); - - Socket = State->HtInterface->GetSocketFromMap (HostNode, State); - PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb); - - if (State->HtBlock->IoPcbLimitsList != NULL) { - p = State->HtBlock->IoPcbLimitsList; - - while (p->HostSocket != HT_LIST_TERMINAL) { - if (((p->HostSocket == Socket) || (p->HostSocket == HT_LIST_MATCH_ANY)) && - ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) && - ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY))) { - // Found a match, return the override info - *DownstreamLinkWidthLimit = p->DownstreamLinkWidthLimit; - *UpstreamLinkWidthLimit = p->UpstreamLinkWidthLimit; - *PcbFreqCap = p->PcbFreqCap; - break; - } else { - p++; - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Manually control bus number assignment. - * - * @HtInterfaceMethod{::F_GET_OVERRIDE_BUS_NUMBERS} - * - * This routine is called every time a non-coherent chain is processed. If a system - * can not use the auto Bus numbering feature for non-coherent chain bus assignments, - * this routine can provide explicit control. For each chain, provide the bus number - * range to use. - * - * The outputs SecBus and SubBus are not valid unless this routine returns TRUE - * - * @param[in] Node The Node on which this chain is located - * @param[in] Link The Link on the host for this chain - * @param[out] SecBus Secondary Bus number for this non-coherent chain - * @param[out] SubBus Subordinate Bus number - * @param[in] State the input data - * - * @retval TRUE this routine is supplying the bus numbers. - * @retval FALSE use auto Bus numbering, bus outputs not valid. - */ -BOOLEAN -GetOverrideBusNumbers ( - IN UINT8 Node, - IN UINT8 Link, - OUT UINT8 *SecBus, - OUT UINT8 *SubBus, - IN STATE_DATA *State - ) -{ - OVERRIDE_BUS_NUMBERS *p; - BOOLEAN result; - UINT8 Socket; - UINT8 PackageLink; - - ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES)); - - result = FALSE; - Socket = State->HtInterface->GetSocketFromMap (Node, State); - PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb); - - if (State->HtBlock->OverrideBusNumbersList != NULL) { - p = State->HtBlock->OverrideBusNumbersList; - - while (p->Socket != HT_LIST_TERMINAL) { - if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) && - ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) { - // Found a match, return the bus overrides - *SecBus = p->SecBus; - *SubBus = p->SubBus; - ASSERT (*SubBus > *SecBus); - result = TRUE; - break; - } else { - p++; - } - } - } - // SecBus, SubBus are not valid if Result is FALSE. - return result; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.h deleted file mode 100644 index c88d673fb4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.h +++ /dev/null @@ -1,136 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Internal access to HT Interface, for non-coherent features. - * - * This file provides definitions used by HT internal modules. The - * external HT interface (in agesa.h) is accessed using these methods. - * This keeps the HT Feature implementations abstracted from the HT - * interface. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_INTERFACE_NONCOHERENT_H_ -#define _HT_INTERFACE_NONCOHERENT_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Prototypes to Interface from Feature Code - * - *---------------------------------------------------------------------------- - */ - -/** - * Manually control bus number assignment. - * - */ -BOOLEAN -GetOverrideBusNumbers ( - IN UINT8 Node, - IN UINT8 Link, - OUT UINT8 *SecBus, - OUT UINT8 *SubBus, - IN STATE_DATA *State - ); - -/** - * Get Manual BUID assignment list. - * - */ -BOOLEAN -GetManualBuidSwapList ( - IN UINT8 Node, - IN UINT8 Link, - OUT BUID_SWAP_LIST **List, - IN STATE_DATA *State - ); - -/** - * Override capabilities of a device. - * - */ - -VOID -GetDeviceCapOverride ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN PCI_ADDR PciAddress, - IN UINT32 DevVenId, - IN UINT8 Revision, - IN UINT8 Link, - IN OUT UINT8 *LinkWidthIn, - IN OUT UINT8 *LinkWidthOut, - IN OUT UINT32 *FreqCap, - IN OUT UINT32 *Clumping, - IN STATE_DATA *State - ); - -/** - * Get limits for non-coherent Links. - * - */ -VOID -GetIoPcbLimits ( - IN UINT8 HostNode, - IN UINT8 HostLink, - IN UINT8 Depth, - IN OUT UINT8 *DownstreamLinkWidthLimit, - IN OUT UINT8 *UpstreamLinkWidthLimit, - IN OUT UINT32 *PcbFreqCap, - IN STATE_DATA *State - ); - -#endif /* _HT_INTERFACE_NONCOHERENT_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htMain.c deleted file mode 100644 index 43eb4f1f76..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htMain.c +++ /dev/null @@ -1,579 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HyperTransport features and sequence implementation. - * - * Implements the external AmdHtInitialize entry point. - * Contains routines for directing the sequence of available features. - * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be - * contained in this file, and not in the feature code. - * - * From a build option perspective, it may be that a few lines could be removed - * from compilation in this file for certain options. It is considered that - * the code savings from this are too small to be of concern and this file - * should not have any explicit build option implementation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htInterface.h" -#include "htNb.h" -#include "heapManager.h" -#include "cpuServices.h" -#include "OptionsHt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_HTMAIN_FILECODE -#define APIC_Base_BSP 8 -#define APIC_Base 0x1b - -extern OPTION_HT_CONFIGURATION OptionHtConfiguration; - -BOOLEAN -STATIC -IsBootCore ( - IN STATE_DATA *State - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Update maps with the core range for each module. - * - * Cores are numbered relative to a Processor, but sometimes there is a need to know the - * starting and ending core ids on a particular node. This same info is also useful for - * supporting the Core count on a node other than the one currently executing. - * - * For each Processor, get the core count of each node using the family specific PCI core count - * interface. The order of cores in a processor, and whether it is special for the BSP is family - * specific. But whether the processor orders core ids by module or node, iterate in the right - * order and use the counts to determine each start and end range. - * - * Update compute unit status for each node. - * - * @param[in] State number of Nodes discovered. -*/ -VOID -STATIC -UpdateCoreRanges ( - IN STATE_DATA *State - ) -{ - UINT8 Node; - UINT8 ProcessorCores; - UINT8 ModuleCoreCount[MAX_DIES]; - UINT8 Socket; - UINT8 Module; - - ASSERT (State->SocketDieToNodeMap != NULL); - ASSERT (State->NodeToSocketDieMap != NULL); - - for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { - // Is a Processor present in Socket? - if ((*State->SocketDieToNodeMap)[Socket][0].Node != HT_LIST_TERMINAL) { - // Get all the Module core counts for this processor - // Note that the core counts are 1 based counts. - // Since Compute Unit info is not module ordering dependent, write it now. - for (Module = 0; Module < MAX_DIES; Module++) { - if ((*State->SocketDieToNodeMap)[Socket][Module].Node != HT_LIST_TERMINAL) { - ModuleCoreCount[Module] = State->Nb->GetNumCoresOnNode ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb); - (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits = - State->Nb->GetEnabledComputeUnits ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb); - (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits = - State->Nb->GetDualCoreComputeUnits ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb); - } else { - ModuleCoreCount[Module] = 0; - } - } - // Determine the core ordering rule for this processor. - if ((((*State->NodeToSocketDieMap)[0].Socket == Socket) && State->Nb->IsOrderBSPCoresByNode) || - (!State->Nb->IsOrderCoresByModule)) { - // Order core ranges on this processor by Node Id. - ProcessorCores = 0; - for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) { - // Is this node a module in this processor? - if ((*State->NodeToSocketDieMap)[Node].Socket == Socket) { - Module = (*State->NodeToSocketDieMap)[Node].Die; - if (ModuleCoreCount[Module] != 0) { - (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores; - (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1); - IDS_HDT_CONSOLE ( - HT_TRACE, - (IsBootCore (State) ? - "Topology: Socket %d, Die %d, is Node %d, with Cores %d thru %d. Compute Unit status (0x%x,0x%x).\n" : - ""), - Socket, - Module, - Node, - (*State->SocketDieToNodeMap)[Socket][Module].LowCore, - (*State->SocketDieToNodeMap)[Socket][Module].HighCore, - (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits, - (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits - ); - ProcessorCores = ProcessorCores + ModuleCoreCount[Module]; - } - } - } - } else { - // Order core ranges in this processor by Module Id. - ProcessorCores = 0; - for (Module = 0; Module < MAX_DIES; Module++) { - if (ModuleCoreCount[Module] != 0) { - (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores; - (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1); - IDS_HDT_CONSOLE ( - HT_TRACE, - (IsBootCore (State) ? - "Topology: Socket %d, Die %d, is Node %d, with Cores %d thru %d. Compute Unit status (0x%x,0x%x).\n" : - ""), - Socket, - Module, - (*State->SocketDieToNodeMap)[Socket][Module].Node, - (*State->SocketDieToNodeMap)[Socket][Module].LowCore, - (*State->SocketDieToNodeMap)[Socket][Module].HighCore, - (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits, - (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits - ); - ProcessorCores = ProcessorCores + ModuleCoreCount[Module]; - } - } - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Complete the coherent init with any system level initialization. - * - * Find the total number of cores and update the number of Nodes and cores in all cpus. - * Limit cpu config access to installed cpus. - * - * @param[in] State number of Nodes discovered. -*/ -VOID -STATIC -FinalizeCoherentInit ( - IN STATE_DATA *State - ) -{ - UINT8 Node; - UINT8 TotalCores; - - TotalCores = 0; - - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - TotalCores = TotalCores + State->Nb->GetNumCoresOnNode (Node, State->Nb); - } - - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - State->Nb->SetTotalNodesAndCores (Node, State->NodesDiscovered + 1, TotalCores, State->Nb); - } - - // Set all nodes to limit config space based on node count, after all nodes have a valid count. - // (just being cautious, probably we could combine the loops.) - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - State->Nb->LimitNodes (Node, State->Nb); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize the coherent fabric. - * - * Perform discovery and initialization of the coherent fabric, for builds including - * support for multiple coherent nodes. - * - * @param[in] State global state - */ -VOID -STATIC -CoherentInit ( - IN OUT STATE_DATA *State - ) -{ - UINT8 i; - UINT8 j; - UINT8 ModuleType; - UINT8 Module; - UINT8 HardwareSocket; - COHERENT_FABRIC Fabric; - - // Because Node 0, the BSP, is not discovered, initialize info about it specially here. - // Allocate Socket Die Map. - // While the BSP is always capable of being the only processor in the system, call the - // IsExceededCapable method to make sure the BSP's capability is included in the aggregate system - // capability. We don't care to check the return value. - // - State->Fabric = &Fabric; - State->NodesDiscovered = 0; - State->TotalLinks = 0; - State->SysMpCap = MAX_NODES; - State->Nb->IsExceededCapable (0, State, State->Nb); - HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb); - ModuleType = 0; - Module = 0; - State->Nb->GetModuleInfo (0, &ModuleType, &Module, State->Nb); - // No predecessor info for BSP, so pass 0xFF for those parameters. - State->HtInterface->SetNodeToSocketMap (0xFF, 0xFF, 0xFF, 0, HardwareSocket, Module, State); - - // Initialize system state data structures - for (i = 0; i < MAX_NODES; i++) { - State->Fabric->SysDegree[i] = 0; - for (j = 0; j < MAX_NODES; j++) { - State->Fabric->SysMatrix[i][j] = 0; - } - } - - // - // Call the coherent init features - // - - // Discovery - State->HtFeatures->CoherentDiscovery (State); - State->HtInterface->PostMapToAp (State); - // Topology matching and Routing - AGESA_TESTPOINT (TpProcHtTopology, State->ConfigHandle); - State->HtFeatures->LookupComputeAndLoadRoutingTables (State); - State->HtFeatures->MakeHopCountTable (State); - - // UpdateCoreRanges requires the other maps to be initialized, and the node count set. - FinalizeCoherentInit (State); - UpdateCoreRanges (State); - State->Fabric = NULL; -} - -/*************************************************************************** - *** Non-coherent init code *** - *** Algorithms *** - ***************************************************************************/ -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize the non-coherent fabric. - * - * Begin with the Compat Link on the BSP, then find and initialize all other - * non-coherent chains. - * - * @param[in] State our global state - */ -VOID -STATIC -NcInit ( - IN STATE_DATA *State - ) -{ - UINT8 Node; - UINT8 Link; - UINT8 CompatLink; - FINAL_LINK_STATE FinalLinkState; - - // Initialize the southbridge chain. - State->AutoBusCurrent = State->HtBlock->AutoBusStart; - State->UsedCfgMapEntries = 0; - CompatLink = State->Nb->ReadSouthbridgeLink (State->Nb); - State->HtFeatures->ProcessLink (0, CompatLink, TRUE, State); - - // Find and initialize all other non-coherent chains. - for (Node = 0; Node <= State->NodesDiscovered; Node++) { - for (Link = 0; Link < State->Nb->MaxLinks; Link++) { - // Skip the Link, if any of these tests indicate - FinalLinkState = State->HtInterface->GetIgnoreLink (Node, Link, State->Nb->DefaultIgnoreLinkList, State); - if (FinalLinkState == UNMATCHED) { - if ( !((Node == 0) && (Link == CompatLink))) { - if ( !(State->Nb->ReadTrueLinkFailStatus (Node, Link, State, State->Nb))) { - if (State->Nb->VerifyLinkIsNonCoherent (Node, Link, State->Nb)) { - State->HtFeatures->ProcessLink (Node, Link, FALSE, State); - } - } - } - } - } - } -} - -/*************************************************************************** - *** Link Optimization *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Optimize Link Features. - * - * Based on Link capabilities, apply optimization rules to come up with the best - * settings, including several external limit decision from the interface. This includes - * handling of subLinks. Finally, after the port list data is updated, set the hardware - * state for all Links. - * - * @param[in] State our global state - */ -VOID -STATIC -LinkOptimization ( - IN STATE_DATA *State - ) -{ - AGESA_TESTPOINT (TpProcHtOptGather, State->ConfigHandle); - State->HtFeatures->GatherLinkData (State); - - AGESA_TESTPOINT (TpProcHtOptRegang, State->ConfigHandle); - State->HtFeatures->RegangLinks (State); - - AGESA_TESTPOINT (TpProcHtOptLinks, State->ConfigHandle); - State->HtFeatures->SelectOptimalWidthAndFrequency (State); - - // A likely cause of mixed Retry settings on coherent links is sublink ratio balancing - // so check this after doing the sublinks. - AGESA_TESTPOINT (TpProcHtOptSubLinks, State->ConfigHandle); - State->HtFeatures->SubLinkRatioFixup (State); - if (State->HtFeatures->IsCoherentRetryFixup (State)) { - // Fix sublinks again within HT1 only frequencies, as ratios may be invalid again. - State->HtFeatures->SubLinkRatioFixup (State); - } - - AGESA_TESTPOINT (TpProcHtOptFinish, State->ConfigHandle); - State->HtFeatures->SetLinkData (State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Handle system and performance tunings. - * - * Including traffic distribution, fifo and - * buffer tuning that can't be placed in the register table, - * and special config tunings. - * - * @param[in] State Total Nodes, port list data - */ -VOID -STATIC -Tuning ( - IN STATE_DATA *State - ) -{ - UINT8 Node; - - // For each Node, invoke northbridge specific buffer tunings that can not be done in reg table. - // - AGESA_TESTPOINT (TpProcHtTuning, State->ConfigHandle); - for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { - State->Nb->BufferOptimizations (Node, State, State->Nb); - } - - // See if traffic distribution can be done and do it if so. - // - AGESA_TESTPOINT (TpProcHtTrafficDist, State->ConfigHandle); - State->HtFeatures->TrafficDistribution (State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize the Node and Socket maps for an AP Core. - * - * In each core's local heap, create a Node to Socket map and a Socket/Module to Node map. - * The mapping is filled in by reading the AP Mailboxes from PCI config on each node. - * - * @param[in] State global state, input data - * - */ -VOID -STATIC -InitApMaps ( - IN STATE_DATA *State - ) -{ - UINT8 Node; - AP_MAIL_INFO NodeApMailBox; - - // There is no option to not have socket - node maps, if they aren't allocated that is a fatal bug. - ASSERT (State->SocketDieToNodeMap != NULL); - ASSERT (State->NodeToSocketDieMap != NULL); - - for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) { - NodeApMailBox = State->Nb->RetrieveMailbox (Node, State->Nb); - (*State->SocketDieToNodeMap)[NodeApMailBox.Fields.Socket][NodeApMailBox.Fields.Module].Node = Node; - (*State->NodeToSocketDieMap)[Node].Socket = (UINT8)NodeApMailBox.Fields.Socket; - (*State->NodeToSocketDieMap)[Node].Die = (UINT8)NodeApMailBox.Fields.Module; - } - // This requires the other maps to be initialized. - UpdateCoreRanges (State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Is the currently running core the BSC? - * - * Determine whether the init steps for BSC or AP core should be run. - * - * @param[in] State global state, input data - * - * @retval TRUE This is the boot core. - * @retval FALSE This is not the boot core. - */ -BOOLEAN -STATIC -IsBootCore ( - IN STATE_DATA *State - ) -{ - UINT64 Value; - - LibAmdMsrRead (APIC_Base, &Value, State->ConfigHandle); - - return ((BOOLEAN) (((UINT32) (Value & 0xFFFFFFFF) & ((UINT32)1 << APIC_Base_BSP)) != 0)); -} - -/*************************************************************************** - *** HT Initialize *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * The top level external interface for Hypertransport Initialization. - * - * Create our initial internal state, initialize the coherent fabric, - * initialize the non-coherent chains, and perform any required fabric tuning or - * optimization. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] PlatformConfiguration The platform configuration options. - * @param[in] AmdHtInterface HT Interface structure. - * - * @retval AGESA_SUCCESS Only information events logged. - * @retval AGESA_ALERT Sync Flood or CRC error logged. - * @retval AGESA_WARNING Example: expected capability not found - * @retval AGESA_ERROR logged events indicating some devices may not be available - * @retval AGESA_FATAL Mixed Family or MP capability mismatch - * - */ -AGESA_STATUS -AmdHtInitialize ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfiguration, - IN AMD_HT_INTERFACE *AmdHtInterface - ) -{ - STATE_DATA State; - NORTHBRIDGE Nb; - HT_FEATURES HtFeatures; - HT_INTERFACE HtInterface; - AGESA_STATUS DeallocateStatus; - AP_MAIL_INFO ApMailboxInfo; - UINT8 ApNode; - - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - State.HtBlock = AmdHtInterface; - State.ConfigHandle = StdHeader; - State.PlatformConfiguration = PlatformConfiguration; - - // Get the current HT internal interface (to HtBlock data) - NewHtInterface (&HtInterface, State.ConfigHandle); - State.HtInterface = &HtInterface; - - // Get the current HT Feature Set - NewHtFeatures (&HtFeatures, State.ConfigHandle); - State.HtFeatures = &HtFeatures; - - // Initialize from static options - State.IsUsingRecoveryHt = OptionHtConfiguration.IsUsingRecoveryHt; - State.IsSetHtCrcFlood = OptionHtConfiguration.IsSetHtCrcFlood; - State.IsUsingUnitIdClumping = OptionHtConfiguration.IsUsingUnitIdClumping; - - // Initialize for status and event output - State.MaxEventClass = AGESA_SUCCESS; - - // Allocate permanent heap structs that are interfaces to other AGESA services. - State.HtInterface->NewNodeAndSocketTables (&State); - - if (IsBootCore (&State)) { - AGESA_TESTPOINT (TpProcHtEntry, State.ConfigHandle); - // Allocate Bsp only interface heap structs. - State.HtInterface->NewHopCountTable (&State); - // Allocate heap for our temporary working space. - AllocHeapParams.RequestedBufferSize = (sizeof (PORT_DESCRIPTOR) * (MAX_PLATFORM_LINKS * 2)); - AllocHeapParams.BufferHandle = HT_STATE_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, State.ConfigHandle) == AGESA_SUCCESS) { - State.PortList = (PORT_LIST)AllocHeapParams.BufferPtr; - // Create the BSP's northbridge. - NewNorthBridge (0, &State, &Nb); - State.Nb = &Nb; - - CoherentInit (&State); - NcInit (&State); - LinkOptimization (&State); - Tuning (&State); - - DeallocateStatus = HeapDeallocateBuffer (HT_STATE_DATA_HANDLE, State.ConfigHandle); - ASSERT (DeallocateStatus == AGESA_SUCCESS); - AGESA_TESTPOINT (TpProcHtDone, State.ConfigHandle); - } else { - ASSERT (FALSE); - State.MaxEventClass = AGESA_ERROR; - // Cannot Log entry due to heap allocate failed. - } - } else { - // Do the AP HT Init, which produces Node and Socket Maps for the AP's use. - AGESA_TESTPOINT (TpProcHtApMapEntry, State.ConfigHandle); - GetApMailbox (&ApMailboxInfo.Info, State.ConfigHandle); - ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES); - ApNode = (UINT8)ApMailboxInfo.Fields.Node; - NewNorthBridge (ApNode, &State, &Nb); - State.Nb = &Nb; - InitApMaps (&State); - AGESA_TESTPOINT (TpProcHtApMapDone, State.ConfigHandle); - } - return State.MaxEventClass; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c deleted file mode 100644 index 74d0c14252..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c +++ /dev/null @@ -1,248 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Construct a northbridge interface for a Node. - * - * Handle build options and run-time detection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionsHt.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNb.h" -#include "htNbCommonHardware.h" -#include "CommonReturns.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuFamRegisters.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#include "Filecode.h" - -#define FILECODE PROC_HT_HTNB_FILECODE - -extern OPTION_HT_CONFIGURATION OptionHtConfiguration; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** - ***************************************************************************/ - - -/** - * Initial construction data for no HT Northbridge. - */ -CONST NORTHBRIDGE ROMDATA HtFam10NbNone = -{ - 1, - (PF_WRITE_ROUTING_TABLE)CommonVoid, - (PF_WRITE_NODEID)CommonVoid, - (PF_READ_DEFAULT_LINK)CommonReturnZero8, - (PF_ENABLE_ROUTING_TABLES)CommonVoid, - (PF_DISABLE_ROUTING_TABLES)CommonVoid, - (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse, - (PF_READ_TOKEN)CommonReturnZero8, - (PF_WRITE_TOKEN)CommonVoid, - (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid, - (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse, - (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse, - (PF_STOP_LINK)CommonVoid, - (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse, - (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse, - (PF_READ_SB_LINK)CommonReturnZero8, - (PF_VERIFY_LINK_IS_NON_COHERENT)CommonReturnFalse, - (PF_SET_CONFIG_ADDR_MAP)CommonVoid, - (PF_NORTH_BRIDGE_FREQ_MASK)CommonReturnZero32, - (PF_GATHER_LINK_FEATURES)CommonVoid, - (PF_SET_LINK_REGANG)CommonVoid, - (PF_SET_LINK_FREQUENCY)CommonVoid, - (PF_SET_LINK_UNITID_CLUMPING)CommonVoid, - (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid, - (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid, - (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid, - (PF_BUFFER_OPTIMIZATIONS)CommonVoid, - (PF_GET_NUM_CORES_ON_NODE)CommonReturnZero8, - (PF_SET_TOTAL_NODES_AND_CORES)CommonVoid, - (PF_GET_NODE_COUNT)CommonReturnZero8, - (PF_LIMIT_NODES)CommonVoid, - (PF_READ_TRUE_LINK_FAIL_STATUS)CommonReturnFalse, - (PF_GET_NEXT_LINK)CommonReturnZero32, - (PF_GET_PACKAGE_LINK)CommonReturnZero8, - (PF_MAKE_LINK_BASE)CommonReturnZero32, - (PF_GET_MODULE_INFO)CommonVoid, - (PF_POST_MAILBOX)CommonVoid, - (PF_RETRIEVE_MAILBOX)CommonReturnZero32, - (PF_GET_SOCKET)CommonReturnZero8, - (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, - (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, - 0, - 0, - 0, - TRUE, - TRUE, - 0, - NULL, - 0, - NULL, - (PF_MAKE_KEY)CommonReturnZero64, - NULL -}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Make a compatibility key. - * - * @HtNbMethod{::F_MAKE_KEY} - * - * Private routine to northbridge code. - * Create a key which can be used to determine whether a Node is compatible with - * the discovered configuration so far. Currently, that means the family, - * extended family of the new Node are the same as the BSP's. Family specific - * implementations can add whatever else is necessary. - * - * @param[in] Node the Node - * @param[in] Nb this northbridge - * - * @return the key - */ -UINT64 -MakeKey ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - CPU_LOGICAL_ID LogicalId; - UINT32 RawCpuId; - PCI_ADDR Reg; - - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_CPUID_3XFC); - - LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, Nb->ConfigHandle); - GetLogicalIdFromCpuid (RawCpuId, &LogicalId, Nb->ConfigHandle); - return LogicalId.Family; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Construct a new northbridge. - * - * This routine encapsulates knowledge of how to tell significant differences between - * families of supported northbridges and what routines can be used in common and - * which are unique. A fully populated northbridge interface is provided by Nb. - * - * @param[in] Node create a northbridge interface for this Node. - * @param[in] State global state - * @param[out] Nb the caller's northbridge structure to initialize. - */ -VOID -NewNorthBridge ( - IN UINT8 Node, - IN STATE_DATA *State, - OUT NORTHBRIDGE *Nb - ) -{ - CPU_LOGICAL_ID LogicalId; - UINT64 Match; - UINT32 RawCpuId; - PCI_ADDR Reg; - NORTHBRIDGE **InitializerInstance; - - // Start with enough of the key to identify the northbridge interface - Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node), - MakePciBusFromNode (Node), - MakePciDeviceFromNode (Node), - CPU_NB_FUNC_03, - REG_NB_CPUID_3XFC); - LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, State->ConfigHandle); - IDS_HDT_CONSOLE (HT_TRACE, "AMD Processor at Node %d has raw CPUID=%x.\n", Node, RawCpuId); - GetLogicalIdFromCpuid (RawCpuId, &LogicalId, State->ConfigHandle); - Match = LogicalId.Family; - - // Test each Northbridge interface in turn looking for a match. - // Use it to Init the Nb struct if a match is found. - // - ASSERT (OptionHtConfiguration.HtOptionFamilyNorthbridgeList != NULL); - InitializerInstance = (NORTHBRIDGE **) (OptionHtConfiguration.HtOptionFamilyNorthbridgeList); - while (*InitializerInstance != NULL) { - if ((Match & (*InitializerInstance)->CompatibleKey) != 0) { - LibAmdMemCopy ((VOID *)Nb, (VOID *)*InitializerInstance, (UINT32) sizeof (NORTHBRIDGE), State->ConfigHandle); - break; - } - InitializerInstance++; - } - // There must be an available northbridge implementation. - ASSERT (*InitializerInstance != NULL); - - // Set the config handle for passing to the library. - Nb->ConfigHandle = State->ConfigHandle; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.h deleted file mode 100644 index 97ad91337a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNb.h +++ /dev/null @@ -1,1132 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HT NorthBridge header - * - * Defines the interface to the HT NorthBridge module for use by other internal - * HT modules. This is not a wrapper or external interface, "public" in the - * comments below is used in the class definition style and refers to HT client - * modules only ("private" being for use only by the HT NB module itself). - * - * It is expected that there will be multiple northbridge implementation files all - * conforming to this common interface. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_NB_H_ -#define _HT_NB_H_ - -/** - * @page htimplnb HT Northbridge Implementation Guide - * - * The HT Northbridge provides access to the Northbridge hardware, in a manner that - * isolates calling code from knowledge about the hardware implementation or which - * features are supported in the current build. This is the mechanism in the HT code for - * supporting new Family or Model northbridges, as well as the means for supporting - * multiple northbridges in a single build or mixed revision northbridge sets. - * - * @par Adding a Method to the Northbridge - * - * To add a new method to the Northbridge, follow these steps. - *
    - *
  • Create a typedef for the Method with the correct parameters and return type. - * - *
      - *
    • Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same - * name as the method table item, but with "_"'s and UPPERCASE, rather than mixed case. - * @n typedef VOID (F_METHOD_NAME)(); @n - * - *
    • Make a reference type for references to a method implementation: - * @n /// Reference to a Method - * @n typedef F_METHOD_NAME *PF_METHOD_NAME @n - *
    - * - *
  • One of the parameters to @b all northbridge Methods is @b required to be a - * reference to its current northbridge object. By convention, this is the - * last parameter. - * - *
  • Provide a standard doxygen function preamble for the Method typedef. Begin the - * detailed description by providing a reference to the method instances page by including - * the lines below: - * @code - * * - * * @HtNbInstances - * * - * @endcode - * @note It is important to provide documentation for the method type, because the method may not - * have an implementation in any families supported by the current package. @n - * - *
  • Add to the NORTHBRIDGE struct an item for the Method: - * @n PF_METHOD_NAME MethodName; ///< Method: description. @n - *
- * - * @par Implementing an Instance of a Northbridge method. - * - * To implement an instance of a method for a specific feature follow these steps. - * - * - In appropriate files, implement the method with the return type and parameters - * matching the Method typedef. - * - If the Method implementation is common to all families, use the northbridge file - * for the function area, for example, add a new coherent initialization support method to the - * coherent northbridge file. - * - If the Method implementation is unique to each supported northbridge, use the - * family specific file for that function area (create it, if it doesn't already exist). - * The family specific files have the same name as the common one suffixed with "FamNN", - * or "FamNNRevX" if for a model or revision. - * - * - Name the function MethodName(). If Family specific, FamNNMethodName(). - * - * - Create a doxygen function preamble for the method instance. Begin the detailed description with - * an Implements command to reference the method type and add this instance to the Method Instances page. - * @code - * * - * * @HtNbMethod{::F_METHOD_NAME}. - * * - * @endcode - * - * - To access other northbridge routines or data as part of the method implementation, - * the function must use Nb->OtherMethod(). Do not directly access other northbridge - * routines, because in the table there may be overrides or this routine may be shared by - * multiple configurations. - * - * - Add the instance, or the correct family specific instance, to the NORTHBRIDGE instances - * used by the northbridge constructor. - * - * - If a northbridge does not need an instance of the method use one of the CommonReturns from - * CommonReturns.h with the same return type. - * - * @par Making common Northbridge Methods. - * - * In some cases, Northbridge methods can easily have a common implementation because the hardware - * is very compatible or is even standard. In other cases, where processor family northbridges - * differ in their implementation, it may be possible to provide a single, common method - * implementation. This can be accomplished by adding Northbridge data members. - * - * For example, a bit position or bit field mask can be used to accommodate different bit placement or size. - * Another example, a small table can be used to translate index values from a common set - * to specific sets. - * - * The Northbridge Method Instance must use its NORTHBRIDGE reference parameter to access - * private data members. - * - * @par Invoking HT Northbridge Methods. - * - * Each unique northbridge is constructed based on matching the current northbridge. - * @n @code - * NORTHBRIDGE Nb; - * // Create the BSP's northbridge. - * NewNorthBridge (0, State, &Nb); - * State->Nb = &Nb; - * @endcode - * - * The following example shows how to invoke a Northbridge method. - * @n @code - * State->Nb->MethodName (State->Nb); - * @endcode - * - */ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/** Use a macro to convert a Node number to a PCI device. If some future port of - * this code needs to, this can easily be replaced by the function declaration: - * UINT8 makePCIDeviceFromNode(UINT8 Node); - */ -#define MakePciDeviceFromNode(Node) \ - ((UINT8) (24 + (Node))) - -/** Use a macro to convert a Node number to a PCI bus. If some future port of - * this code needs to, this can easily be replaced by the function declaration: - * UINT8 MakePciBusFromNode(UINT8 Node); - */ -#define MakePciBusFromNode(Node) \ - ((UINT8) (0)) - -/** Use a macro to convert a Node number to a PCI Segment. If some future port of - * this code needs to, this can easily be replaced by the function declaration: - * UINT8 MakePciSegmentFromNode(UINT8 Node); - */ -#define MakePciSegmentFromNode(Node) \ - ((UINT8) (0)) - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ -/** - * Status for iterating through internal (if supported) and external links. - */ -typedef enum { - LinkIteratorEnd, ///< This is the end of all links, no valid link. - LinkIteratorExternal, ///< The next link (the one we got on this call) is an external link. - LinkIteratorInternal, ///< The next link (the one we got on this call) is an internal link. - LinkIteratorMax ///< For bounds checking and limit only. -} LINK_ITERATOR_STATUS; - -#define LINK_ITERATOR_BEGIN 0xFF - -/** - * Write a temporary Route. - * - * @HtNbInstances - * - * @param[in] Node The node on which to set a temporary route - * @param[in] Target A route to this node, which route table entry is to be set - * @param[in] Link The link which routes to the target node - * @param[in] Nb This northbridge - */ -typedef VOID F_WRITE_ROUTING_TABLE ( - IN UINT8 Node, - IN UINT8 Target, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_ROUTING_TABLE *PF_WRITE_ROUTING_TABLE; - -/** - * Modifies the NodeID register on the target Node - * - * @HtNbInstances - * - * @param[in] Node the Node that will have its NodeID altered. - * @param[in] NodeID the new value for NodeID - * @param[in] Nb this northbridge - */ -typedef VOID F_WRITE_NODEID ( - IN UINT8 Node, - IN UINT8 NodeID, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_NODEID *PF_WRITE_NODEID; - -/** - * Read the Default Link - * - * @HtNbInstances - * - * @param[in] Node the Node that will have its NodeID altered. - * @param[in] Nb this northbridge - * - * @return The HyperTransport Link where the request to - * read the default Link came from. Since this code is running on the BSP, - * this should be the Link pointing back towards the BSP. - */ -typedef UINT8 F_READ_DEFAULT_LINK ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_READ_DEFAULT_LINK *PF_READ_DEFAULT_LINK; - -/** - * Turns routing tables on for a given Node - * - * @HtNbInstances - * - * @param[in] Node the Node that will have it's routing tables enabled - * @param[in] Nb this northbridge - */ -typedef VOID F_ENABLE_ROUTING_TABLES ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_ENABLE_ROUTING_TABLES *PF_ENABLE_ROUTING_TABLES; - -/** - * Turns routing tables off for a given Node - * - * @HtNbInstances - * - * @param[in] Node the Node that will have it's routing tables disabled - * @param[in] Nb this northbridge - */ -typedef VOID F_DISABLE_ROUTING_TABLES ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_DISABLE_ROUTING_TABLES *PF_DISABLE_ROUTING_TABLES; - -/** - * Verify that the Link is coherent, connected, and ready - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Link the Link on that Node to examine - * @param[in] Nb this northbridge - * - * @retval TRUE The Link is coherent - * @retval FALSE The Link has some other status -*/ -typedef BOOLEAN F_VERIFY_LINK_IS_COHERENT ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_VERIFY_LINK_IS_COHERENT *PF_VERIFY_LINK_IS_COHERENT; - -/** - * Read the token stored in the scratchpad register field. - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - * - * @return the Token read from the Node - */ -typedef UINT8 F_READ_TOKEN ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_READ_TOKEN *PF_READ_TOKEN; - -/** - * Write the token stored in the scratchpad register - * - * @HtNbInstances - * - * @param[in] Node the Node that marked with token - * @param[in] Value the token Value - * @param[in] Nb this northbridge - */ -typedef VOID F_WRITE_TOKEN ( - IN UINT8 Node, - IN UINT8 Value, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_TOKEN *PF_WRITE_TOKEN; - -/** - * Full Routing Table Register initialization - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Target the Target Node for these routes - * @param[in] ReqLink the Link for requests to Target - * @param[in] RspLink the Link for responses to Target - * @param[in] BroadcastLinks the broadcast Links - * @param[in] Nb this northbridge - */ -typedef VOID F_WRITE_FULL_ROUTING_TABLE ( - IN UINT8 Node, - IN UINT8 Target, - IN UINT8 ReqLink, - IN UINT8 RspLink, - IN UINT32 BroadcastLinks, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_FULL_ROUTING_TABLE *PF_WRITE_FULL_ROUTING_TABLE; - -/** - * Determine whether a Node is compatible with the discovered configuration so far. - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[in] Nb this northbridge - * - * @retval TRUE the node is not compatible - * @retval FALSE the node is compatible - */ -typedef BOOLEAN F_IS_ILLEGAL_TYPE_MIX ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_IS_ILLEGAL_TYPE_MIX *PF_IS_ILLEGAL_TYPE_MIX; - -/** - * Return whether the current configuration exceeds the capability - * of the nodes detected. - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[in] State sysMpCap (updated) and NodesDiscovered - * @param[in] Nb this northbridge - * - * @retval TRUE system is not capable of current config. - * @retval FALSE system is capable of current config. - */ -typedef BOOLEAN F_IS_EXCEEDED_CAPABLE ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_IS_EXCEEDED_CAPABLE *PF_IS_EXCEEDED_CAPABLE; - -/** - * Stop a link, so that it is isolated from a connected device. - * - * @HtNbInstances - * - * Use is for fatal incompatible configurations. - * While XMIT and RCV off are HT standard, the use of these bits - * is generally family specific. - * - * @param[in] Node the node to stop a link on. - * @param[in] Link the link to stop. - * @param[in] State access to special routine for writing link control register - * @param[in] Nb this northbridge. - */ -typedef VOID F_STOP_LINK ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_STOP_LINK *PF_STOP_LINK; - -/** - * Fix (hopefully) exceptional conditions. - * - * @HtNbInstances - * - * This routine is expected to be unimplemented for most families. - * Some configurations may require that links be processed specially to prevent - * serious problems, like hangs. Check for that condition in this routine, - * handle the link both for hardware and for adding to port list, if appropriate. - * If this routine adds the link to port list or the link should not be added, return TRUE. - * - * @param[in] Node The Node which has this link - * @param[in] Link The link to check for special conditions. - * @param[in] State our global state. - * @param[in] Nb this northbridge. - * - * @retval TRUE This link received special handling. - * @retval FALSE This link was not handled specially, handle it normally. - * - */ -typedef BOOLEAN F_HANDLE_SPECIAL_LINK_CASE ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_HANDLE_SPECIAL_LINK_CASE *PF_HANDLE_SPECIAL_LINK_CASE; - -/** - * Fix (hopefully) exceptional conditions. - * - * @HtNbInstances - * - * This routine is expected to be unimplemented for most families. - * Some configurations may require that nodes be processed specially to prevent - * serious problems, like hangs. Check for that condition in this routine, - * handle the node both for hardware and for adding to port list, if appropriate. - * If this routine adds the node to port list or the node should not be added, return TRUE. - * - * @param[in] Node The Node which need to be checked. - * @param[in] Link The link to check for special conditions. - * @param[in] State our global state. - * @param[in] Nb this northbridge. - * - * @retval TRUE This node received special handling. - * @retval FALSE This node was not handled specially, handle it normally. - * - */ -typedef BOOLEAN F_HANDLE_SPECIAL_NODE_CASE ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_HANDLE_SPECIAL_NODE_CASE *PF_HANDLE_SPECIAL_NODE_CASE; - -/** - * Get Info about Module Type of this northbridge - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[out] ModuleType 0 for Single, 1 for Multi - * @param[out] Module The module number of this node (0 if Single) - * @param[in] Nb this northbridge - * - */ -typedef VOID F_GET_MODULE_INFO ( - IN UINT8 Node, - OUT UINT8 *ModuleType, - OUT UINT8 *Module, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_GET_MODULE_INFO *PF_GET_MODULE_INFO; - -/** - * Post info to AP cores via a mailbox. - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[in] ApMailInfo The info to post - * @param[in] Nb this northbridge - * - */ -typedef VOID F_POST_MAILBOX ( - IN UINT8 Node, - IN AP_MAILBOXES ApMailInfo, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_POST_MAILBOX *PF_POST_MAILBOX; - -/** - * Retrieve info from a node's AP mailbox. - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[in] ApMailInfo The info to post - * @param[in] Nb this northbridge - * - */ -typedef AP_MAIL_INFO F_RETRIEVE_MAILBOX ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_RETRIEVE_MAILBOX *PF_RETRIEVE_MAILBOX; - -/** - * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register. - * - * @HtNbInstances - * - * @param[in] Node The node for which we want the socket id. - * @param[in] TempNode The temporary node id route where the node can be accessed. - * @param[in] Nb Our Northbridge. - * - * @return The Socket Id - */ -typedef UINT8 F_GET_SOCKET ( - IN UINT8 Node, - IN UINT8 TempNode, - IN NORTHBRIDGE *Nb - ); - -/// Reference to a method. -typedef F_GET_SOCKET *PF_GET_SOCKET; - -/** - * Get the enabled Compute Units. - * - * Processors which don't support compute units return zero. - * - * @HtNbInstances - * - * @param[in] Node The node for which we want the socket id. - * @param[in] Nb Our Northbridge. - * - * @return The Socket Id - */ -typedef UINT8 F_GET_ENABLED_COMPUTE_UNITS ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/// Reference to a method. -typedef F_GET_ENABLED_COMPUTE_UNITS *PF_GET_ENABLED_COMPUTE_UNITS; - -/** - * Get the dual core Compute Units. - * - * Processors which don't support compute units return zero. - * - * @HtNbInstances - * - * @param[in] Node The node for which we want the socket id. - * @param[in] Nb Our Northbridge. - * - * @return The Socket Id - */ -typedef UINT8 F_GET_DUALCORE_COMPUTE_UNITS ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -/// Reference to a method. -typedef F_GET_DUALCORE_COMPUTE_UNITS *PF_GET_DUALCORE_COMPUTE_UNITS; - -/** - * Return the Link to the Southbridge - * - * @HtNbInstances - * - * @param[in] Nb this northbridge - * - * @return the Link to the southbridge - */ -typedef UINT8 F_READ_SB_LINK ( - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_READ_SB_LINK *PF_READ_SB_LINK; - -/** - * Verify that the Link is non-coherent, connected, and ready - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Link the Link on that Node to examine - * @param[in] Nb this northbridge - * - * @retval TRUE The Link is non-coherent. - * @retval FALSE The Link has some other status - */ -typedef BOOLEAN F_VERIFY_LINK_IS_NON_COHERENT ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_VERIFY_LINK_IS_NON_COHERENT *PF_VERIFY_LINK_IS_NON_COHERENT; - -/** - * Enable config access to a non-coherent chain for the given bus range. - * - * @HtNbInstances - * - * @param[in] ConfigMapIndex the map entry to set - * @param[in] SecBus The secondary bus number to use - * @param[in] SubBus The subordinate bus number to use - * @param[in] TargetNode The Node that shall be the recipient of the traffic - * @param[in] TargetLink The Link that shall be the recipient of the traffic - * @param[in] State our global state - * @param[in] Nb this northbridge - */ -typedef VOID F_SET_CONFIG_ADDR_MAP ( - IN UINT8 ConfigMapIndex, - IN UINT8 SecBus, - IN UINT8 SubBus, - IN UINT8 TargetNode, - IN UINT8 TargetLink, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_SET_CONFIG_ADDR_MAP *PF_SET_CONFIG_ADDR_MAP; - -/** - * Northbridge specific Frequency limit. - * - * @HtNbInstances - * - * Return a mask that eliminates HT frequencies that cannot be used due to a slow - * northbridge frequency. - * - * @param[in] Node Result could (later) be for a specific Node - * @param[in] Interface Access to non-HT support functions. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] Nb this northbridge - * - * @return Frequency mask - */ -typedef UINT32 F_NORTH_BRIDGE_FREQ_MASK ( - IN UINT8 Node, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_NORTH_BRIDGE_FREQ_MASK *PF_NORTH_BRIDGE_FREQ_MASK; - -/** - * Get Link features into system data structure. - * - * @HtNbInstances - * - * @param[in,out] ThisPort The PortList structure entry for this link's port - * @param[in] Interface Access to non-HT support functions. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] Nb this northbridge - */ -typedef VOID F_GATHER_LINK_FEATURES ( - IN OUT PORT_DESCRIPTOR *ThisPort, - IN HT_INTERFACE *Interface, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_GATHER_LINK_FEATURES *PF_GATHER_LINK_FEATURES; - -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure. - * - * @HtNbInstances - * - * @param[in] Node the node on which to regang a link - * @param[in] Link the sublink 0 of the sublink pair to regang - * @param[in] Nb this northbridge - */ -typedef VOID F_SET_LINK_REGANG ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_SET_LINK_REGANG *PF_SET_LINK_REGANG; - -/** - * Change the hardware state for all Links according to the now optimized data in the - * port list data structure. - * - * @HtNbInstances - * - * @param[in] Node the node on which to set frequency for a link - * @param[in] Link the link to set frequency - * @param[in] Frequency the frequency to set - * @param[in] Nb this northbridge - */ -typedef VOID F_SET_LINK_FREQUENCY ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Frequency, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_SET_LINK_FREQUENCY *PF_SET_LINK_FREQUENCY; - -/** - * Set the link's Unit Id Clumping enable. - * - * @HtNbInstances - * - * This applies to the host root of a non-coherent chain. - * - * @param[in] Node the node on which to set frequency for a link - * @param[in] Link the link to set frequency - * @param[in] ClumpingEnables the unit id clumping enables to set - * @param[in] Nb this northbridge - */ -typedef VOID F_SET_LINK_UNITID_CLUMPING ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT32 ClumpingEnables, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_SET_LINK_UNITID_CLUMPING *PF_SET_LINK_UNITID_CLUMPING; - -/** - * Set the traffic distribution register for the Links provided. - * - * @HtNbInstances - * - * @param[in] Links01 coherent Links from Node 0 to 1 - * @param[in] Links10 coherent Links from Node 1 to 0 - * @param[in] Nb this northbridge - */ -typedef VOID F_WRITE_TRAFFIC_DISTRIBUTION ( - IN UINT32 Links01, - IN UINT32 Links10, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_TRAFFIC_DISTRIBUTION *PF_WRITE_TRAFFIC_DISTRIBUTION; - -/** - * Set the traffic distribution register for the Links provided. - * - * @HtNbInstances - * - * @param[in] NodeA Source Node from Node A To Node B and DstNode from Node A To Node B - * @param[in] NodeB Source Node from Node B To Node A and DstNode from Node A To Node B - * @param[in] VictimedLinkFromNodeAToNodeB Victimed Link from Node A To Node B - * @param[in] VictimedLinkFromNodeBToNodeA Victimed Link from Node B To Node A - * @param[in] Nb this northbridge - */ -typedef VOID F_WRITE_VICTIM_DISTRIBUTION ( - IN UINT8 NodeA, - IN UINT8 NodeB, - IN UINT32 VictimedLinkFromNodeAToNodeB, - IN UINT32 VictimedLinkFromNodeBToNodeA, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_WRITE_VICTIM_DISTRIBUTION *PF_WRITE_VICTIM_DISTRIBUTION; - -/** - * Write a link pair to the link pair distribution and fixups. - * - * @HtNbInstances - * - * @param[in] Node Set the pair on this node - * @param[in] ConnectedNode The Node to which this link pair directly connects. - * @param[in] Pair Using this pair set in the register - * @param[in] Asymmetric True if different widths - * @param[in] MasterLink Set this as the master link and in the route - * @param[in] AlternateLink Set this as the alternate link - * @param[in] Nb this northbridge - * - */ -typedef VOID F_WRITE_LINK_PAIR_DISTRIBUTION ( - IN UINT8 Node, - IN UINT8 ConnectedNode, - IN UINT8 Pair, - IN BOOLEAN Asymmetric, - IN UINT8 MasterLink, - IN UINT8 AlternateLink, - IN NORTHBRIDGE *Nb - ); -/// Pointer to method WriteLinkPairDistribution -typedef F_WRITE_LINK_PAIR_DISTRIBUTION *PF_WRITE_LINK_PAIR_DISTRIBUTION; - -/** - * Family specific tunings. - * - * @HtNbInstances - * - * Buffer tunings are inherently northbridge specific. Check for specific configs - * which require adjustments and apply any standard workarounds to this Node. - * - * @param[in] Node the Node to tune - * @param[in] State global state - * @param[in] Nb this northbridge - */ -typedef VOID F_BUFFER_OPTIMIZATIONS ( - IN UINT8 Node, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_BUFFER_OPTIMIZATIONS *PF_BUFFER_OPTIMIZATIONS; - -/** - * Return the number of cores (1 based count) on Node. - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - * - * @return the number of cores - */ -typedef UINT8 F_GET_NUM_CORES_ON_NODE ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_GET_NUM_CORES_ON_NODE *PF_GET_NUM_CORES_ON_NODE; - -/** - * Write the total number of cores and Nodes to the Node - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] TotalNodes the total number of Nodes - * @param[in] TotalCores the total number of cores - * @param[in] Nb this northbridge - */ -typedef VOID F_SET_TOTAL_NODES_AND_CORES ( - IN UINT8 Node, - IN UINT8 TotalNodes, - IN UINT8 TotalCores, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_SET_TOTAL_NODES_AND_CORES *PF_SET_TOTAL_NODES_AND_CORES; - -/** - * Get the Count of Nodes in the system. - * - * @HtNbInstances - * - * @param[in] Nb This Northbridge. - * - * @return The Count (1 based) of Nodes in the system. - */ -typedef UINT8 F_GET_NODE_COUNT ( - IN NORTHBRIDGE *Nb - ); - -/// Reference to a method. -typedef F_GET_NODE_COUNT *PF_GET_NODE_COUNT; - -/** - * Limit coherent config accesses to cpus as indicated by Nodecnt. - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Nb this northbridge - */ -typedef VOID F_LIMIT_NODES ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_LIMIT_NODES *PF_LIMIT_NODES; - -/** - * Return the LinkFailed status AFTER an attempt is made to clear the bit. - * - * @HtNbInstances - * - * @param[in] Node the Node that will be examined - * @param[in] Link the Link on that Node to examine - * @param[in] State access to call back routine - * @param[in] Nb this northbridge - * - * @retval TRUE the Link is not connected or has hard error - * @retval FALSE the Link is connected - */ -typedef BOOLEAN F_READ_TRUE_LINK_FAIL_STATUS ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_READ_TRUE_LINK_FAIL_STATUS *PF_READ_TRUE_LINK_FAIL_STATUS; - -/** - * Get the next link for iterating over the links on a node in the correct order. - * - * @HtNbInstances - * - * @param[in] Node The node on which to iterate links. - * @param[in,out] Link IN: the current iteration context, OUT: the next link. - * @param[in] Nb This Northbridge, access to config pointer. - * - * @retval LinkIteratorEnd There is no next link (Link is back to BEGIN). - * @retval LinkIteratorExternal The next Link is an external link. - * @retval LinkIteratorInternal The next Link is an internal link. - */ -typedef LINK_ITERATOR_STATUS F_GET_NEXT_LINK ( - IN UINT8 Node, - IN OUT UINT8 *Link, - IN NORTHBRIDGE *Nb - ); -/// Pointer to method GetNextLink -typedef F_GET_NEXT_LINK *PF_GET_NEXT_LINK; - -/** - * Get the Package Link number, given the node and real link number. - * - * @HtNbInstances - * - * @param[in] Node the node which has this link - * @param[in] Link the link on that node - * @param[in] Nb this northbridge - * - * @return the Package Link - * - */ -typedef UINT8 F_GET_PACKAGE_LINK ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method -typedef F_GET_PACKAGE_LINK *PF_GET_PACKAGE_LINK; - -/** - * Return the HT Host capability base PCI config address for a Link. - * - * @HtNbInstances - * - * @param[in] Node the Node this Link is on - * @param[in] Link the Link - * @param[in] Nb this northbridge - * - * @return the pci config address - */ -typedef PCI_ADDR F_MAKE_LINK_BASE ( - IN UINT8 Node, - IN UINT8 Link, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_MAKE_LINK_BASE *PF_MAKE_LINK_BASE; - -/** - * Make a compatibility key. - * - * @HtNbInstances - * - * @param[in] Node the Node - * @param[in] Nb this northbridge - * - * @return the key - */ -typedef UINT64 F_MAKE_KEY ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); -/// Reference to a method. -typedef F_MAKE_KEY *PF_MAKE_KEY; - -/** - * The northbridge interface. - * - * Abstract the hardware implementation of the processor northbridge. Feature code does - * not need to be tailored to specific families. Also, more than a single family (or - * model in some cases) can be supported at once. Multiple family support can be for - * mixed revisions or for incompatible revisions where only one is used at a time. - * - * The northbridge object contains both HT component public and northbridge private - * members. These sets are grouped together. Within each group, members are grouped - * according to the function area they support. - * - */ -struct _NORTHBRIDGE { // See forward declaration in HtFeats.h - /* Public data, clients of northbridge can access */ - UINT8 MaxLinks; /**< The maximum number of Links implemented by the northbridge */ - - /* Public Interfaces for northbridge clients, coherent init*/ - PF_WRITE_ROUTING_TABLE WriteRoutingTable; /**< Method: Write a Temporary route for discovery */ - PF_WRITE_NODEID WriteNodeID; /**< Method: Assign a Node ID*/ - PF_READ_DEFAULT_LINK ReadDefaultLink; /**< Method: Which link are we connected to on a remote node? */ - PF_ENABLE_ROUTING_TABLES EnableRoutingTables; /**< Method: Make the routing table active */ - PF_DISABLE_ROUTING_TABLES DisableRoutingTables; /**< Method: Put a node back in discoverable state (deflnk) */ - PF_VERIFY_LINK_IS_COHERENT VerifyLinkIsCoherent; /**< Method: is a link connected and coherent? */ - PF_READ_TOKEN ReadToken; /**< Method: Read the enumeration token from a node */ - PF_WRITE_TOKEN WriteToken; /**< Method: Assign an enumeration token to a node */ - PF_WRITE_FULL_ROUTING_TABLE WriteFullRoutingTable; /**< Method: Set a complete routing table entry on a node */ - PF_IS_ILLEGAL_TYPE_MIX IsIllegalTypeMix; /**< Method: Is this node compatible with the system */ - PF_IS_EXCEEDED_CAPABLE IsExceededCapable; /**< Method: Is this node capable of working in this system */ - PF_STOP_LINK StopLink; /**< Method: stop a link which must be unused */ - PF_HANDLE_SPECIAL_LINK_CASE HandleSpecialLinkCase; /**< Method: Fix broken configuration designs */ - PF_HANDLE_SPECIAL_NODE_CASE HandleSpecialNodeCase; /**< Method: Fix broken configuration designs */ - - /* Public Interfaces for northbridge clients, noncoherent init */ - PF_READ_SB_LINK ReadSouthbridgeLink; /**< Method: Which link goes to the southbridge? */ - PF_VERIFY_LINK_IS_NON_COHERENT VerifyLinkIsNonCoherent; /**< Method: is a link connected and non-coherent? */ - PF_SET_CONFIG_ADDR_MAP SetConfigAddrMap; /**< Method: Add a non-coherent chain to the PCI Config Bus Address Map */ - - /* Public Interfaces for northbridge clients, Optimization */ - PF_NORTH_BRIDGE_FREQ_MASK NorthBridgeFreqMask; /**< Method: Check for frequency limits other than HT */ - PF_GATHER_LINK_FEATURES GatherLinkFeatures; /**< Method: Get frequency and link features */ - PF_SET_LINK_REGANG SetLinkRegang; /**< Method: Set a Link to regang */ - PF_SET_LINK_FREQUENCY SetLinkFrequency; /**< Method: Set the link Frequency */ - PF_SET_LINK_UNITID_CLUMPING SetLinkUnitIdClumping; /**< Method: Set the link's Unit Id Clumping register */ - - /* Public Interfaces for northbridge clients, System and performance Tuning. */ - PF_WRITE_TRAFFIC_DISTRIBUTION WriteTrafficDistribution; /**< Method: traffic distribution setting */ - PF_WRITE_LINK_PAIR_DISTRIBUTION WriteLinkPairDistribution; /**< Method: Link Pair setting and fix up */ - PF_WRITE_VICTIM_DISTRIBUTION WriteVictimDistribution; /**< Method: victim distribution setting */ - PF_BUFFER_OPTIMIZATIONS BufferOptimizations; /**< Method: system tunings which can not be - * done using register table */ - - /* Public Interfaces for northbridge clients, utility routines */ - PF_GET_NUM_CORES_ON_NODE GetNumCoresOnNode; /**< Method: Count cores */ - PF_SET_TOTAL_NODES_AND_CORES SetTotalNodesAndCores; /**< Method: Set Node and Core counts */ - PF_GET_NODE_COUNT GetNodeCount; /**< Method: Get the Count (1 based) of Nodes in the system. */ - PF_LIMIT_NODES LimitNodes; /**< Method: Set the Limit Config Space feature */ - PF_READ_TRUE_LINK_FAIL_STATUS ReadTrueLinkFailStatus; /**< Method: Get Fault status and connectivity of a link */ - PF_GET_NEXT_LINK GetNextLink; /**< Method: Iterate over a node's Internal, then External links. */ - PF_GET_PACKAGE_LINK GetPackageLink; /**< Method: the package link corresponding to a node's link */ - PF_MAKE_LINK_BASE MakeLinkBase; /**< Method: Provide the PCI Config Base register offset of a CPU link */ - PF_GET_MODULE_INFO GetModuleInfo; /**< Method: Get Module Type and internal Module number */ - PF_POST_MAILBOX PostMailbox; /**< Method: Post info to the mailbox register */ - PF_RETRIEVE_MAILBOX RetrieveMailbox; /**< Method: Retrieve info from the mailbox register */ - PF_GET_SOCKET GetSocket; /**< Method: Get a node's Socket, using the hardware naming method. */ - PF_GET_ENABLED_COMPUTE_UNITS GetEnabledComputeUnits; /**< Method: Get the Enabled Compute Units */ - PF_GET_DUALCORE_COMPUTE_UNITS GetDualCoreComputeUnits; /**< Method: Get which Compute Units have two cores. */ - - /* Private Data for northbridge implementation use only */ - UINT32 SelfRouteRequestMask; /**< Bit pattern for route request to self in routing table register */ - UINT32 SelfRouteResponseMask; /**< Bit pattern for route response to self in routing table register */ - UINT8 BroadcastSelfBit; /**< Bit offset of broadcast self bit in routing table register */ - BOOLEAN IsOrderBSPCoresByNode; /**< This processor orders Cores by Node id on the BSP, if TRUE. */ - BOOLEAN IsOrderCoresByModule; /**< Processors other than the BSP order Cores by Module, if TRUE. */ - UINT64 CompatibleKey; /**< Used for checking compatibility of northbridges in the system */ - PACKAGE_HTLINK_MAP PackageLinkMap; /**< Tell GetPackageLink() how to assign link names */ - UINT32 CoreFrequency; /**< Cache the northbridge core frequency, so repeated interface calls are avoided. - * A value of zero, means no value yet. */ - IGNORE_LINK *DefaultIgnoreLinkList; /**< After processing the user interface ignore link, process this list. */ - - /* Private Interfaces for northbridge implementation. */ - PF_MAKE_KEY MakeKey; /**< Method: make the compatibility key for this node */ - - /** Config Pointer, opaque handle for passing to lib */ - VOID *ConfigHandle; -}; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -/** - * Make a compatibility key. - * - */ -UINT64 -MakeKey ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); - -VOID -NewNorthBridge ( - IN UINT8 Node, - IN STATE_DATA *State, - OUT NORTHBRIDGE *Nb - ); - -#endif /* _HT_NB_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNbCommonHardware.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htNbCommonHardware.h deleted file mode 100644 index 1bafda5627..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNbCommonHardware.h +++ /dev/null @@ -1,121 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Northbridge hardware definitions for Family 10h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _HT_NB_HARDWARE_FAM10_H_ -#define _HT_NB_HARDWARE_FAM10_H_ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/* CPU Northbridge Functions */ -#define CPU_HTNB_FUNC_00 0 -#define CPU_HTNB_FUNC_04 4 -#define CPU_ADDR_FUNC_01 1 -#define CPU_NB_FUNC_03 3 -#define CPU_NB_FUNC_05 5 - -/* Function 0 registers */ -#define REG_ROUTE0_0X40 0x40 -#define REG_ROUTE1_0X44 0x44 -#define REG_NODE_ID_0X60 0x60 -#define REG_UNIT_ID_0X64 0x64 -#define REG_LINK_TRANS_CONTROL_0X68 0x68 -#define REG_LINK_INIT_CONTROL_0X6C 0x6C -#define REG_HT_CAP_BASE_0X80 0x80 -#define REG_HT_LINK_CLUMPING0_0X110 0x110 -#define REG_HT_LINK_RETRY0_0X130 0x130 -#define REG_HT_EXTENDED_NODE_ID_F0X160 0x160 -#define HTREG_NODE_CPUCNT_4_0 0x1F -#define HTREG_EXTNODE_CPUCNT_7_5 0xE0 -#define REG_HT_TRAFFIC_DIST_0X164 0x164 -#define REG_LINK_GLOBAL_EXT_CONTROL_0x16C 0x16C -#define REG_HT_LINK_EXT_CONTROL0_0X170 0x170 -#define REG_HT_LINK_INITIALIZATION_0X1A0 0x1A0 -#define PAIR_SELECT_OFFSET 8 -#define REG_HT_LINK_PAIR_DIST_0X1E0 0x1E0 - -/* Function 1 registers */ -#define REG_ADDR_CONFIG_MAP0_1XE0 0xE0 -#define CPU_ADDR_NUM_CONFIG_MAPS 4 - -/* Function 3 registers */ -#define REG_NB_SRI_XBAR_BUF_3X70 0x70 -#define REG_NB_MCT_XBAR_BUF_3X78 0x78 -#define REG_NB_FIFOPTR_3XDC 0xDC -#define REG_NB_CAPABILITY_3XE8 0xE8 -#define REG_NB_CPUID_3XFC 0xFC -#define REG_NB_LINK_XCS_TOKEN0_3X148 0x148 -#define REG_NB_MCA_LINK_THRESHOLD_3X168 0x168 -#define REG_NB_MCA_L3_THRESHOLD_3X170 0x170 -#define REG_NB_DOWNCORE_3X190 0x190 -#define REG_NB_SBI_CONTROL_3X1E4 0x1E4 - -/* Function 4 registers */ - -/* Function 5 registers */ -#define REG_NB_COMPUTE_UNIT_5X80 0x80 -#define REG_NB_CAPABILITY_2_5X84 0x84 - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -#endif /* _HT_NB_HARDWARE_FAM10_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.c deleted file mode 100644 index 990a67dc2c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.c +++ /dev/null @@ -1,670 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Code for detailed notification of events and status. - * - * Routines for logging and reporting details and summary status. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "Topology.h" -#include "htFeat.h" -#include "htNotify.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_HT_HTNOTIFY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Log an event. - * - * Errors, events, faults, warnings, and useful information are provided by - * calling this routine as often as necessary, once for each notification. - * @sa AGESA.h for class, and event definitions. - * @sa htNotify.h for event data definitions. - * - * @param[in] EvtClass What level event is this - * @param[in] Event A unique ID of this event - * @param[in] EventData useful data associated with the event. - * @param[in] State the log area and remaining free space - */ -VOID -STATIC -setEventNotify ( - IN AGESA_STATUS EvtClass, - IN UINT32 Event, - IN CONST UINT8 *EventData, - IN STATE_DATA *State - ) -{ - UINT32 DataParam[NUMBER_OF_EVENT_DATA_PARAMS]; - - // Remember the highest event class notified, that becomes our return code. - if (State->MaxEventClass < EvtClass) { - State->MaxEventClass = EvtClass; - } - - // Copy the event data to the log data - LibAmdMemCopy ( - DataParam, - (VOID *)EventData, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - // Log the event - PutEventLog ( - EvtClass, - Event, - DataParam[0], - DataParam[1], - DataParam[2], - DataParam[3], - State->ConfigHandle - ); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_HW_SYNCFLOOD - * - * @param[in] Node The node on which the fault is reported - * @param[in] Link The link from that node - * @param[in] State our State - * - */ -VOID -NotifyAlertHwSyncFlood ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_HW_SYNCFLOOD Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "Sync Flood on Node %d Link %d.\n", Node, Link); - Evt.Node = Node; - Evt.Link = Link; - setEventNotify (AGESA_ALERT, - HT_EVENT_HW_SYNCFLOOD, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_HW_HTCRC - * - * @param[in] Node The node on which the error is reported - * @param[in] Link The link from that node - * @param[in] LaneMask The lanes which had CRC - * @param[in] State our State - * - */ -VOID -NotifyAlertHwHtCrc ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 LaneMask, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_HW_HT_CRC Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "CRC Error on Node %d Link %d lanes %x.\n", Node, Link, LaneMask); - Evt.Node = Node; - Evt.Link = Link; - Evt.LaneMask = LaneMask; - setEventNotify (AGESA_ALERT, - HT_EVENT_HW_HTCRC, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_NCOH_BUS_MAX_EXCEED - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Bus The bus number to assign - * @param[in] State our State - * - */ -VOID -NotifyErrorNcohBusMaxExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Bus, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Bus = Bus; - setEventNotify (AGESA_ERROR, - HT_EVENT_NCOH_BUS_MAX_EXCEED, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_NCOH_CFG_MAP_EXCEED - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] State our State - * - */ -VOID -NotifyErrorNcohCfgMapExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - setEventNotify (AGESA_ERROR, - HT_EVENT_NCOH_CFG_MAP_EXCEED, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_NCOH_BUID_EXCEED - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Depth Position on chain - * @param[in] Id The Id which was attempted to assigned - * @param[in] Units The number of units in this device - * @param[in] State our State - * - */ -VOID -NotifyErrorNcohBuidExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN UINT8 Id, - IN UINT8 Units, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_NCOH_BUID_EXCEED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Depth = Depth; - Evt.CurrentBuid = Id; - Evt.UnitCount = Units; - setEventNotify (AGESA_ERROR, - HT_EVENT_NCOH_BUID_EXCEED, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_NCOH_DEVICE_FAILED - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Depth Position on chain - * @param[in] Id The Id which was attempted to assigned - * @param[in] State our State - * - */ -VOID -NotifyErrorNcohDeviceFailed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN UINT8 Id, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_NCOH_DEVICE_FAILED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Depth = Depth; - Evt.AttemptedBuid = Id; - setEventNotify (AGESA_ERROR, - HT_EVENT_NCOH_DEVICE_FAILED, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_NCOH_AUTO_DEPTH - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Depth Position on chain - * @param[in] State our State - * - */ -VOID -NotifyInfoNcohAutoDepth ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_NCOH_AUTO_DEPTH Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Depth = Depth; - setEventNotify (AGESA_SUCCESS, - HT_EVENT_NCOH_AUTO_DEPTH, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_OPT_REQUIRED_CAP_RETRY - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Depth Position on chain - * @param[in] State our State - * - */ -VOID -NotifyWarningOptRequiredCapRetry ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_OPT_REQUIRED_CAP Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Depth = Depth; - setEventNotify (AGESA_WARNING, - HT_EVENT_OPT_REQUIRED_CAP_RETRY, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_OPT_REQUIRED_CAP_GEN3 - * - * @param[in] Node The node on which the chain is located - * @param[in] Link The link from that node - * @param[in] Depth Position on chain - * @param[in] State our State - * - */ -VOID -NotifyWarningOptRequiredCapGen3 ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_OPT_REQUIRED_CAP Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.Node = Node; - Evt.Link = Link; - Evt.Depth = Depth; - setEventNotify (AGESA_WARNING, - HT_EVENT_OPT_REQUIRED_CAP_GEN3, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_OPT_UNUSED_LINKS - * - * @param[in] NodeA One of the nodes connected - * @param[in] NodeB The other connected node - * @param[in] LinkA its unusable link - * @param[in] LinkB its unusable link - * @param[in] State our State - * - */ -VOID -NotifyWarningOptUnusedLinks ( - IN UINT32 NodeA, - IN UINT32 LinkA, - IN UINT32 NodeB, - IN UINT32 LinkB, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_OPT_UNUSED_LINKS Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.NodeA = NodeA; - Evt.LinkA = LinkA; - Evt.NodeB = NodeB; - Evt.LinkB = LinkB; - setEventNotify (AGESA_WARNING, - HT_EVENT_OPT_UNUSED_LINKS, - (UINT8 *)&Evt, State); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_OPT_LINK_PAIR_EXCEED - * - * @param[in] NodeA One of the nodes connected - * @param[in] NodeB The other connected node - * @param[in] MasterLink its unusable Masterlink - * @param[in] AltLink its unusable Alternate link - * @param[in] State our State - * - */ -VOID -NotifyWarningOptLinkPairExceed ( - IN UINT32 NodeA, - IN UINT32 NodeB, - IN UINT32 MasterLink, - IN UINT32 AltLink, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - Evt.NodeA = NodeA; - Evt.MasterLink = MasterLink; - Evt.NodeB = NodeB; - Evt.AltLink = AltLink; - setEventNotify (AGESA_WARNING, - HT_EVENT_OPT_LINK_PAIR_EXCEED, - (UINT8 *)&Evt, State); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_COH_NO_TOPOLOGY - * - * @param[in] Nodes The total number of nodes found so far - * @param[in] State our State - * - */ -VOID -NotifyErrorCohNoTopology ( - IN UINT8 Nodes, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_COH_NO_TOPOLOGY Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "No Topology Matched system with %d nodes found.\n", Nodes); - Evt.TotalNodes = Nodes; - setEventNotify (AGESA_ERROR, - HT_EVENT_COH_NO_TOPOLOGY, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_COH_PROCESSOR_TYPE_MIX - * - * @param[in] Node The node from which a new node was discovered - * @param[in] Link The link from that node - * @param[in] Nodes The total number of nodes found so far - * @param[in] State our State - * - */ -VOID -NotifyFatalCohProcessorTypeMix ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Nodes, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "Illegal Processor Type Mix.\n"); - Evt.Node = Node; - Evt.Link = Link; - Evt.TotalNodes = Nodes; - setEventNotify (AGESA_CRITICAL, - HT_EVENT_COH_PROCESSOR_TYPE_MIX, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_COH_NODE_DISCOVERED - * - * @param[in] Node Node from which a new node was discovered - * @param[in] Link The link to that new node - * @param[in] NewNode The new node's id - * @param[in] TempRoute Temporarily, during discovery, the new node is accessed at this id. - * @param[in] State our State - * - */ -VOID -NotifyInfoCohNodeDiscovered ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 NewNode, - IN UINT8 TempRoute, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_COH_NODE_DISCOVERED Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "Adding Node %d.\n", NewNode); - Evt.Node = Node; - Evt.Link = Link; - Evt.NewNode = NewNode; - Evt.TempRoute = TempRoute; - setEventNotify (AGESA_SUCCESS, - HT_EVENT_COH_NODE_DISCOVERED, - (UINT8 *)&Evt, State); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * For event HT_EVENT_COH_MPCAP_MISMATCH - * - * @param[in] Node The node from which a new node was discovered - * @param[in] Link The link from that node - * @param[in] Cap The aggregate system MP Capability - * @param[in] Nodes The total number of nodes found so far - * @param[in] State our State - * - */ -VOID -NotifyFatalCohMpCapMismatch ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Cap, - IN UINT8 Nodes, - IN STATE_DATA *State - ) -{ - HT_EVENT_DATA_COH_MP_CAP_MISMATCH Evt; - // Zero out the event data - LibAmdMemFill ( - &Evt, - 0, - (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS), - State->ConfigHandle - ); - - IDS_HDT_CONSOLE (HT_TRACE, "Mp Capability Mismatch.\n"); - Evt.Node = Node; - Evt.Link = Link; - Evt.SysMpCap = Cap; - Evt.TotalNodes = Nodes; - setEventNotify (AGESA_CRITICAL, - HT_EVENT_COH_MPCAP_MISMATCH, - (UINT8 *)&Evt, State); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h deleted file mode 100644 index efbea11338..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h +++ /dev/null @@ -1,296 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HT Notify interface. - * - * This file provides internal interface to event and status - * notification. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _HT_NOTIFY_H_ -#define _HT_NOTIFY_H_ - -/*----------------------------------------------------------------------------------------*/ -/* Event specific event data definitions. - * All structures must be 4 UINT32's in size, no more, no less. - */ - -/// For event ::HT_EVENT_HW_SYNCFLOOD -typedef struct { - UINT32 Node; ///< The Node on which observed - UINT32 Link; ///< The Link on that Node which reported synch flood - UINT32 Reserved1; ///< Reserved. - UINT32 Reserved2; ///< Reserved. -} HT_EVENT_DATA_HW_SYNCFLOOD; - -/// For event ::HT_EVENT_HW_HTCRC -typedef struct { - UINT32 Node; ///< The Node on which event is observed - UINT32 Link; ///< The Link on that Node which reported CRC error - UINT32 LaneMask; ///< The CRC lane mask for the Link - UINT32 Reserved1; ///< Reserved. -} HT_EVENT_DATA_HW_HT_CRC; - -/// For event ::HT_EVENT_NCOH_BUS_MAX_EXCEED -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Bus; ///< the current bus number - UINT32 Reserved1; ///< Reserved. -} HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED; - -/// For event ::HT_EVENT_NCOH_CFG_MAP_EXCEED -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Reserved1; ///< Reserved. - UINT32 Reserved2; ///< Reserved. -} HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED; - -/// For event ::HT_EVENT_NCOH_BUID_EXCEED -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Depth; ///< the position on the chain, zero is CPU host - UINT16 CurrentBuid; ///< the current available BUID - UINT16 UnitCount; ///< the number of ids which would be consumed by this device -} HT_EVENT_DATA_NCOH_BUID_EXCEED; - -/// For event ::HT_EVENT_NCOH_DEVICE_FAILED -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Depth; ///< the position on the chain, zero is CPU host - UINT32 AttemptedBuid; ///< the BUID we tried to assign to that device -} HT_EVENT_DATA_NCOH_DEVICE_FAILED; - -/// For event ::HT_EVENT_NCOH_AUTO_DEPTH -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Depth; ///< the position on the chain of the last device, zero is CPU host - UINT32 Reserved1; ///< Reserved. -} HT_EVENT_DATA_NCOH_AUTO_DEPTH; - -/// For event ::HT_EVENT_OPT_REQUIRED_CAP_RETRY, -/// ::HT_EVENT_OPT_REQUIRED_CAP_GEN3. -typedef struct { - UINT32 Node; ///< the Node with this non-coherent chain - UINT32 Link; ///< the Link on that Node to this chain - UINT32 Depth; ///< the position on the chain, zero is CPU host - UINT32 Reserved1; ///< Reserved. -} HT_EVENT_DATA_OPT_REQUIRED_CAP; - -/// For event ::HT_EVENT_OPT_UNUSED_LINKS -typedef struct { - UINT32 NodeA; ///< One of the nodes connected - UINT32 LinkA; ///< its unusable link - UINT32 NodeB; ///< The other connected node - UINT32 LinkB; ///< its unusable link -} HT_EVENT_DATA_OPT_UNUSED_LINKS; - -/// For event ::HT_EVENT_OPT_LINK_PAIR_EXCEED -typedef struct { - UINT32 NodeA; ///< One of the nodes connected - UINT32 NodeB; ///< The other connected node - UINT32 MasterLink; ///< NodeA's unusable Master link - UINT32 AltLink; ///< NodeA's unusable Alternatelink -} HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED; - -/// For event ::HT_EVENT_COH_NO_TOPOLOGY. -/// There is no routing for this system's topology. -typedef struct { - UINT32 TotalNodes; ///< the number of Nodes in the unmatched topology - UINT32 Reserved1; ///< Reserved. - UINT32 Reserved2; ///< Reserved. - UINT32 Reserved3; ///< Reserved. -} HT_EVENT_DATA_COH_NO_TOPOLOGY; - -/// For event ::HT_EVENT_COH_PROCESSOR_TYPE_MIX -typedef struct { - UINT32 Node; ///< the Node from which the incompatible family was found - UINT32 Link; ///< the Link to the incompatible Node - UINT32 TotalNodes; ///< the number of Nodes found at that point - UINT32 Reserved1; ///< Reserved. -} HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX; - -/// For event ::HT_EVENT_COH_NODE_DISCOVERED -typedef struct { - UINT32 Node; ///< the Node from which the new Node was found - UINT32 Link; ///< the Link to the new Node - UINT32 NewNode; ///< the Node id of the newly discovered Node - UINT32 TempRoute; ///< the new Node is temporarily at this id -} HT_EVENT_DATA_COH_NODE_DISCOVERED; - -/// For event ::HT_EVENT_COH_MPCAP_MISMATCH -typedef struct { - UINT32 Node; ///< the Node from which condition was observed - UINT32 Link; ///< the Link on the current Node - UINT32 SysMpCap; ///< the current aggregate system capability (the minimum found so far) - UINT32 TotalNodes; ///< the number of Nodes found, before this was observed -} HT_EVENT_DATA_COH_MP_CAP_MISMATCH; - -/*----------------------------------------------------------------------------------------*/ -/* Event specific Notify functions. - */ - -VOID -NotifyAlertHwSyncFlood ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State - ); - -VOID -NotifyAlertHwHtCrc ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 LaneMask, - IN STATE_DATA *State - ); - -VOID -NotifyErrorNcohBusMaxExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Bus, - IN STATE_DATA *State - ); - -VOID -NotifyErrorNcohCfgMapExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN STATE_DATA *State - ); - -VOID -NotifyErrorNcohBuidExceed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN UINT8 Id, - IN UINT8 Units, - IN STATE_DATA *State - ); - -VOID -NotifyErrorNcohDeviceFailed ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN UINT8 Id, - IN STATE_DATA *State - ); - -VOID -NotifyInfoNcohAutoDepth ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ); - -VOID -NotifyWarningOptRequiredCapRetry ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ); - -VOID -NotifyWarningOptRequiredCapGen3 ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Depth, - IN STATE_DATA *State - ); - -VOID -NotifyWarningOptUnusedLinks ( - IN UINT32 NodeA, - IN UINT32 LinkA, - IN UINT32 NodeB, - IN UINT32 LinkB, - IN STATE_DATA *State - ); - -VOID -NotifyWarningOptLinkPairExceed ( - IN UINT32 NodeA, - IN UINT32 NodeB, - IN UINT32 MasterLink, - IN UINT32 AltLink, - IN STATE_DATA *State - ); - -VOID -NotifyErrorCohNoTopology ( - IN UINT8 Nodes, - IN STATE_DATA *State - ); - -VOID -NotifyFatalCohProcessorTypeMix ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Nodes, - IN STATE_DATA *State - ); - -VOID -NotifyInfoCohNodeDiscovered ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 NewNode, - IN UINT8 TempRoute, - IN STATE_DATA *State - ); - -VOID -NotifyFatalCohMpCapMismatch ( - IN UINT8 Node, - IN UINT8 Link, - IN UINT8 Cap, - IN UINT8 Nodes, - IN STATE_DATA *State - ); - -#endif /* _HT_NOTIFY_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htPage.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htPage.h deleted file mode 100644 index e2c82294a0..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htPage.h +++ /dev/null @@ -1,63 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for HyperTransport Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page htmain HyperTransport Component Documentation - * - * Additional documentation for the HyperTransport component consists of - * - * - Member Cross References - * - @subpage instanceshtnb "HT Northbridge Method Instances" - * - Maintenance Guides: - * - @subpage htimplintf "HT Internal Interface Implementation Guide" - * - @subpage htimplfeat "HT Feature Implementation Guide" - * - @subpage htimplnb "HT Northbridge Implementation Guide" - * - add here >>> - * - Design Guides: - * - @subpage htgraphdesign "Graph Support Design" - * - @subpage physicalsockethowto "How to Create a Physical System Socket Map" - * - add here >>> - * - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/HT/htTopologies.h b/src/vendorcode/amd/agesa/f15/Proc/HT/htTopologies.h deleted file mode 100644 index cf852415c2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/HT/htTopologies.h +++ /dev/null @@ -1,70 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Provide selection of available topologies. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _HT_TOPOLOGIES_H_ -#define _HT_TOPOLOGIES_H_ - -extern CONST UINT8 ROMDATA amdHtTopologySingleNode[]; -extern CONST UINT8 ROMDATA amdHtTopologyDualNode[]; -extern CONST UINT8 ROMDATA amdHtTopologyThreeLine[]; -extern CONST UINT8 ROMDATA amdHtTopologyTriangle[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourLine[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourStar[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourSquare[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourKite[]; -extern CONST UINT8 ROMDATA amdHtTopologyFourFully[]; -extern CONST UINT8 ROMDATA amdHtTopologyFiveFully[]; -extern CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[]; -extern CONST UINT8 ROMDATA amdHtTopologySixFully[]; -extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[]; -extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[]; -extern CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[]; -extern CONST UINT8 ROMDATA amdHtTopologySevenFully[]; -extern CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[]; -extern CONST UINT8 ROMDATA amdHtTopologyEightFully[]; -extern CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[]; -extern CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[]; -extern CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[]; -extern CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[]; -extern CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[]; - -#endif // _HT_TOPOLOGIES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f15/Proc/IDS/IdsLib.h deleted file mode 100644 index d72eb2e968..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/IDS/IdsLib.h +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD IDS Routines - * - * Contains AMD AGESA Integrated Debug Macros - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: IDS - * @e \$Revision: 55552 $ @e \$Date: 2011-06-22 09:31:58 -0600 (Wed, 22 Jun 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - -#ifndef _IDS_LIB_H_ -#define _IDS_LIB_H_ -#include "OptionsIds.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "Table.h" -///Specific time stamp performance analysis which need ids control support -#if IDSOPT_CONTROL_ENABLED == TRUE - #define PERF_SPEC_TS_ANALYSE(StdHeader) -#else - #define PERF_SPEC_TS_ANALYSE(StdHeader) -#endif - - -#define IDS_NV_READ_SKIP(NvValue, Nvid, IdsNvPtr, StdHeader) -#define IDS_GET_MASK32(HighBit, LowBit) - -#define IDS_MAX_MEM_ITEMS 80 ///< Maximum IDS Mem Table Size in Heap. -///Macro for Ids family feat -#define MAKE_IDS_FAMILY_FEAT_ALL_CORES(FEAT_ID, FAMILY, FUNCTION) \ - {IDS_FEAT_COMMON, IDS_ALL_CORES, FEAT_ID, FAMILY, FUNCTION} - - -// TYPEDEFS, STRUCTURES, ENUMS -// - -typedef AGESA_STATUS (*PF_IDS_AP_TASK) (VOID *AptaskPara, AMD_CONFIG_PARAMS *StdHeader); - -///Structure define for IdsAgesaRunFcnOnApLate -typedef struct _IDSAPLATETASK { - PF_IDS_AP_TASK ApTask; ///< Point function which AP need to do - VOID *ApTaskPara; ///< Point to Ap function parameter1 -} IDSAPLATETASK; - -/// Data Structure defining IDS Data in HEAP -/// This data structure contains information that is stored in HEAP and will be -/// used in IDS backend function. It includes the size of memory to be allocated -/// for IDS, the relative offsets of the mapping table IDS setup options, the GRA -/// table and the register table to override mem setting. It also includes a base -/// address of IDS override image which will be used to control the behavior of -/// AGESA testpoint if this feature is enabled. -typedef struct { - BOOLEAN IgnoreIdsDefault; ///< Control ignore Default value of IDS NV list specified by IdsNvTableOffset - UINT64 IdsImageBase; ///< IDS Override Image Base Address - UINT32 IdsHeapMemSize; ///< IDS Total Memory Size in Heap - UINT32 IdsNvTableOffset; ///< Offset of IDS NV Table - UINT32 IdsMemTableOffset; ///< Offset of IDS Mem Table - UINT32 IdsExtendOffset; ///< Offset of Ids extend heap -} IDS_CONTROL_STRUCT; - - -/// Data Structure of Parameters for TestPoint_TSC. -typedef struct { - UINT8 TestPoint; ///< The TestPoint of TestPoint_TSC - UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC -} TestPoint_TSC; - -/// Data Structure of Parameters for TP_Perf_STRUCT. -typedef struct { - UINT8 Index; ///< The Index of TP_Perf_STRUCT - UINT32 TscInMhz; ///< Tsc counter in 1 mhz - TestPoint_TSC TP[EndAgesaTps]; ///< The TP of TP_Perf_STRUCT -} TP_Perf_STRUCT; - - -///Bus speed Optimization -typedef enum { - IDS_POWER_POLICY_PERFORMANCE = 0, ///< Performance - IDS_POWER_POLICY_POWER = 1, ///< Power - IDS_POWER_POLICY_AUTO = 3, ///< Auto -} IDS_NV_AMDBUSSPEEDOPTIMIZATION; - - -#define IDS_ALL_SOCKET 0xFF -#define IDS_ALL_MODULE 0xFF -#define IDS_ALL_CORE 0xFF -#define IDS_ALL_DCT 0xFF - -#define IDS_CPB_BOOST_DIS_IGNORE 0xFFFFFFFF - -#endif //_IDS_LIB_H_ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/IDS/IdsPage.h b/src/vendorcode/amd/agesa/f15/Proc/IDS/IdsPage.h deleted file mode 100644 index 7606a77007..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/IDS/IdsPage.h +++ /dev/null @@ -1,56 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for Integrated Debug Support Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page idsmain Integrated Debug Support Component Documentation - * - * Additional documentation for the Integrated Debug Support component consists of - * - * - Maintenance Guides: - * - add here >>> - * - Design Guides: - * - add here >>> - * - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/Makefile.inc deleted file mode 100644 index 1149973123..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += marc32_3.c -libagesa-y += mauc32_3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/marc32_3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/marc32_3.c deleted file mode 100644 index fa76b1fa6c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/marc32_3.c +++ /dev/null @@ -1,593 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * marc32_3.c - * - * Memory Controller, registered dimms - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ardk) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support AM3 */ - - -#include "AGESA.h" -#include "ma.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_ARDK_C32_MARC32_3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -STATIC CONST UINT8 ROMDATA C32RDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00}; - -// Even chip select maps to M[B,A]_CKE[0] -// Odd chip select maps to M[B,A]_CKE[1] -STATIC CONST UINT8 ROMDATA C32RDdr3CKETri[] = {0x55, 0xAA}; - -// 2 dimms per channel -// Dimm 0: BP_MEMODTx[2,0] -// Dimm 1: BP_MEMODTx[3,1] -STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8}; -// 3 dimms per channel -// Dimm 0: BP_MEMODTx[0] -// Dimm 1: BP_MEMODTx[3,1] -// Dimm 2: BP_MEMODTx[2] -STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8}; -// 4 dimms per channel -// Dimm 0: BP_MEMODTx[0] -// Dimm 1: BP_MEMODTx[1] -// Dimm 2: BP_MEMODTx[2] -// Dimm 3: BP_MEMODTx[3] -STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0}; - -// BIOS must not tri-state chip select pin corresponding to the second chip -// select of a single rank registered dimm -STATIC CONST UINT8 ROMDATA C32RDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for C32 DDR3 L1 system - * - * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE - * @param[in] SocketID Socket number - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return AGESA_SUCCESS - * @return CurrentChannel->MemClkDisMap Points this pointer to C32 MemClkDis table - * @return CurrentChannel->ChipSelTriMap Points this pointer to C32 CS table - * @return CurrentChannel->CKETriMap Points this pointer to C32 ODT table - * @return CurrentChannel->ODTTriMap Points this pointer to C32 CKE table - * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC - * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte - * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel - * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel - * @return CurrentChannel->SlowMode Slow Mode - * - */ - -AGESA_STATUS -MemAGetPsCfgRC32_3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ) -{ - // - // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel - // - // Code searches table for matching speed, then matches the current dimm - // population and # of dimms to current config and programs the Addr Timing and RC2/RC2 - // - // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated - // in SPD Byte 63. - // Bits 15-12 RC2 if One register - // Bits 11-8 RC8 if One register - // Bits 7-4 RC2 for more than one register - // Bits 3-0 RC8 for more than one register - // - // Frequency, Dimm Config , - // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match - // - STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = { - {DDR667_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \ - 0x00000000, 0x4004, 2}, - {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x00000000, 0x0000, 1}, - {DDR800_FREQUENCY, QR_DIMM1, \ - 0x00000000, 0x0040, 1}, - {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x00000000, 0x4004, 2}, - {DDR800_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \ - 0x00000000, 0x4004, 2}, - {DDR800_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \ - 0x00000000, 0x4004, 2}, - {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x003C3C3C, 0x0000,1}, - {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ - 0x003C3C3C, 0x0040, 1}, - {DDR1066_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \ - 0x003A3C3A, 0x4004, 2}, - {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x003A3A3A, 0x0000, 1}, - {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ - 0x003A3A3A, 0x0040, 1}, - {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x00383A38, 0x4040, 2}, - }; - // - // Address Timings and Drive Strengths for 3 DIMMs per channel - // - // Code searches table for matching speed, then matches the current dimm - // population and # of dimms to current config and programs the Addr Timing and RC2/RC2 - // - // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated - // in SPD Byte 63. - // Bits 15-12 RC2 if One register - // Bits 11-8 RC8 if One register - // Bits 7-4 RC2 for more than one register - // Bits 3-0 RC8 for more than one register - // - // Frequency, Dimm Config , - // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match - // - STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = { - {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00000000, 0x0000, 1}, - {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00000000, 0x4040, 2}, - {DDR667_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00000000, 0x4004, 2}, - {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00380038, 0x4004, 3}, - {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00000000, 0x0000, 1}, - {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \ - 0x00000000, 0x4040, 2}, - {DDR800_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00000000, 0x4004, 2}, - {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00380038, 0x4004, 3}, - {DDR800_FREQUENCY, QR_DIMM1, \ - 0x00000000, 0x0040, 1}, - {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x003C3C3C, 0x0000, 1}, - {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \ - 0x003A3C3A, 0x4040, 2}, - {DDR1066_FREQUENCY, SR_DIMM0 + SR_DIMM1 + SR_DIMM2, \ - 0x00373C37, 0x4040, 3}, - {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x003A3A3A, 0x0000, 1}, - {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \ - 0x00383A38, 0x4040, 2}, - }; - - // - // DIMM ODT Pattern (1 or 2 DIMMs per channel) - // - // Dimm Config , - // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match - // - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = { - {SR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, - {DR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1}, - {QR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000505, 0x00000505, 1}, - {SR_DIMM1, \ - 0x00000000, 0x00000000, 0x00020000, 0x00000000, 1}, - {DR_DIMM1, \ - 0x00000000, 0x00000000, 0x02080000, 0x00000000, 1}, - {QR_DIMM1, \ - 0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x01010202, 0x00000000, 0x09030603, 0x00000000, 2}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \ - 0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2}, - {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2}, - {QR_DIMM0 + QR_DIMM1, \ - 0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2} - }; - // DIMM ODT Pattern (3 DIMMs per channel) - // - // Dimm Config , - // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match - // - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = { - {SR_DIMM2 + DR_DIMM2, \ - 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1}, - {SR_DIMM0 + DR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \ - 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3}, - {QR_DIMM1, \ - 0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1}, - {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \ - 0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3} - }; - // - // DIMM ODT Pattern (4 DIMMs per channel) - // - // Dimm Config , - // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match - // - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = { - {ANY_DIMM3, \ - 0x00000000, 0x00000000, 0x00000000, 0x08080000, 1}, - {ANY_DIMM2 + ANY_DIMM3, \ - 0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2}, - {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \ - 0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3}, - {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \ - 0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4} - }; - // - // DIMM Write Leveling ODT Pattern 1 or 2 Dimms Per Channel - // - // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match - // - STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = { - {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, - {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, - {QR_DIMM0, {0x05, 0x00, 0x00, 0x00}, 1}, - {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, - {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, - {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}, - {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, - {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, - {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2}, - {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2}, - {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2} - }; - // - // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel - // - // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match - // - STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = { - {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1}, - {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3}, - {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1}, - {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3} - }; - // - // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel - // - // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match - // - STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = { - {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1}, - {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2}, - {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3}, - {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4} - }; - - - UINT16 i; - UINT16 j; - UINT8 MaxDimmPerCH; - UINT8 Dimms; - UINT16 Speed; - UINT16 DIMMRankType; - UINT16 _DIMMRankType; - UINT8 DimmTpMatch; - UINT32 AddrTmgCTL; - UINT32 DctOdcCtl; - UINT16 RC2RC8; - UINT32 PhyRODTCSLow; - UINT32 PhyRODTCSHigh; - UINT32 PhyWODTCSLow; - UINT32 PhyWODTCSHigh; - BOOLEAN SlowMode; - UINT8 PSCfgSize; - UINT8 PSCfgODTSize; - UINT8 PSCfgWlODTSize; - UINT8 PhyWLODT[4]; - - CONST ADV_R_PSCFG_ENTRY *PSCfgPtr; - CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr; - CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr; - UINT8 *DimmsPerChPtr; - - ASSERT (MemData != NULL); - ASSERT (CurrentChannel != NULL); - - AddrTmgCTL = 0; - DctOdcCtl = 0; - RC2RC8 = 0; - PhyRODTCSLow = 0; - PhyRODTCSHigh = 0; - PhyWODTCSLow = 0; - PhyWODTCSHigh = 0; - SlowMode = FALSE; - PhyWLODT[0] = 0x0F; - PhyWLODT[1] = 0x0F; - PhyWLODT[2] = 0x0F; - PhyWLODT[3] = 0x0F; - - if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) { - return AGESA_UNSUPPORTED; - } - if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (CurrentChannel->RegDimmPresent == 0) { - return AGESA_UNSUPPORTED; - } - - // Prepare inputs - Dimms = CurrentChannel->Dimms; - Speed = CurrentChannel->DCTPtr->Timings.Speed; - - DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmPerCH = *DimmsPerChPtr; - } else { - MaxDimmPerCH = 2; - } - - DIMMRankType = MemAGetPsRankType (CurrentChannel); - - if (MaxDimmPerCH == 4) { - PSCfgPtr = NULL; - PSCfgSize = 0; - PSCfgODTPtr = PSCfg4DIMMsODT; - PSCfgWlODTPtr = PSCfg4DIMMsWlODT; - PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); - PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); - } else if (MaxDimmPerCH == 3) { - PSCfgPtr = PSCfg3DIMMs; - PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY); - PSCfgODTPtr = PSCfg3DIMMsODT; - PSCfgWlODTPtr = PSCfg3DIMMsWlODT; - PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); - PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); - } else { - PSCfgPtr = PSCfg2DIMMs; - PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY); - PSCfgODTPtr = PSCfg2DIMMsODT; - PSCfgWlODTPtr = PSCfg2DIMMsWlODT; - PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); - PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); - } - - // AddrTmgCTL and DctOdcCtl - if (MaxDimmPerCH != 4) { - for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) { - if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgPtr->Dimms) { - AddrTmgCTL = PSCfgPtr->AddrTmg; - DctOdcCtl = 0x00223222; - RC2RC8 = PSCfgPtr->RC2RC8; - break; - } - } - } - - // - // Overrides and/or exceptions - // - // - // Count slots with SR/DR poulated. - // - DimmTpMatch = 0; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) { - DimmTpMatch++; - } - } - // - // DimmTpMatch is equal to the count of slot that have either an SR or DR - // installed. - // - if (MaxDimmPerCH == 4) { - // - // Any SR/DR in 4 DPCH - // - if (DimmTpMatch > 0) { - DctOdcCtl = 0x00223222; - if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) { - DctOdcCtl = 0x00113222; - } - } - // - // At Least 3 SR/DR in 4 DPCH - // - if (DimmTpMatch >= 3) { - AddrTmgCTL |= 0x002F0000; - } - // At Least 2 SR/DR in 4 DPCH - if (DimmTpMatch >= 2) { - RC2RC8 = 0x4040; - } - } else { - // - // Less than 4 DPCH - // - // - // Only 1 Dimm Populated and its a SR or DR OR - // 3 Dimms Populated and Frequency is 800 MHz - // - if (((Dimms == 1) && (DimmTpMatch == 1)) || - ((Dimms == 3) && ((Speed == DDR800_FREQUENCY) || - (Speed == DDR1066_FREQUENCY)))) { - DctOdcCtl = 0x00113222; - } - } - - //RC2 and RC8 - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution. - if (CurrentChannel->CtrlWrd02[j] > 0) { - if (CurrentChannel->CtrlWrd02[j] == 1) { - // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s). - CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F; - CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F; - } else { - // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s). - CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F; - CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F; - } - } - } - - //Programmable ODT - for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) { - if (Dimms != PSCfgODTPtr->Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgODTPtr->Dimms) { - PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow; - PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh; - PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow; - PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh; - break; - } - } - - //WLODT - for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) { - if (Dimms != PSCfgWlODTPtr->Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgWlODTPtr->Dimms) { - PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0]; - PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1]; - PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2]; - PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3]; - break; - } - } - - // Set ProcODT - DctOdcCtl |= 0x20000000; - - CurrentChannel->MemClkDisMap = (UINT8 *) C32RDdr3CLKDis; - CurrentChannel->CKETriMap = (UINT8 *) C32RDdr3CKETri; - CurrentChannel->ChipSelTriMap = (UINT8 *) C32RDdr3CSTri; - - switch (MaxDimmPerCH) { - case 3: - CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri3D; - break; - case 4: - CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri4D; - break; - default: - CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri2D; // Most conservative - } - - CurrentChannel->DctAddrTmg = AddrTmgCTL; - CurrentChannel->DctOdcCtl = DctOdcCtl; - CurrentChannel->PhyRODTCSLow = PhyRODTCSLow; - CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh; - CurrentChannel->PhyWODTCSLow = PhyWODTCSLow; - CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh; - for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { - CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; - } - CurrentChannel->SlowMode = SlowMode; - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/mauc32_3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/mauc32_3.c deleted file mode 100644 index d53c41c128..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/C32/mauc32_3.c +++ /dev/null @@ -1,356 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mauc32_3.c - * - * Platform specific settings for C32 DDR3 unbuffered dimms - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ardk) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -/* This file contains routine that add platform specific support AM3 */ - - -#include "AGESA.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_ARDK_C32_MAUC32_3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -STATIC CONST UINT8 ROMDATA C32UDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; -// Even chip select maps to M[B,A]_CKE[0] -// Odd chip select maps to M[B,A]_CKE[1] -STATIC CONST UINT8 ROMDATA C32UDdr3CKETri[] = {0x55, 0xAA}; -// Bit 0: M[B,A]0_ODT[0] -// Bit 1: M[B,A]1_ODT[0] -// Bit 2: M[B,A]0_ODT[1] -// Bit 3: M[B,A]1_ODT[1] -STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08}; -// 3 dimms per channel -// Dimm 0: BP_MEMODTx[0] -// Dimm 1: BP_MEMODTx[3,1] -// Dimm 2: BP_MEMODTx[2] -STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF}; -// Bit 0: M[B,A]0_CS_H/L[0] -// Bit 1: M[B,A]0_CS_H/L[1] -// Bit 2: M[B,A]0_CS_H/L[2] -// Bit 3: M[B,A]0_CS_H/L[3] -STATIC CONST UINT8 ROMDATA C32UDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for C32 DDR3 unbuffered dimms - * - * - * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE - * @param[in] SocketID Socket number - * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return AGESA_SUCCESS - * @return CurrentChannel->MemClkDisMap Points this pointer to C32 MemClkDis table - * @return CurrentChannel->ChipSelTriMap Points this pointer to C32 CS table - * @return CurrentChannel->CKETriMap Points this pointer to C32 ODT table - * @return CurrentChannel->ODTTriMap Points this pointer to C32 CKE table - * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC - * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte - * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel - * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel - * @return CurrentChannel->SlowMode Slow Mode - * - * - */ - -AGESA_STATUS -MemAGetPsCfgUC32_3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ) -{ - STATIC CONST PSCFG_ENTRY PSCfg[] = { - {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323}, - {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323}, - {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323}, - {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323} - }; - - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = { - {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, - {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1}, - {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1}, - {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2}, - }; - - STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = { - {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, - {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, - {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, - {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} - }; - - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = { - {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1}, - //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2}, - //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3}, - }; - - STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = { - {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1}, - //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2}, - //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3}, - }; - - UINT16 i; - UINT16 j; - UINT8 MaxDimmPerCH; - UINT8 Loads; - UINT8 Dimms; - UINT16 Speed; - UINT16 DIMMRankType; - UINT16 _DIMMRankType; - UINT32 AddrTmgCTL; - UINT32 DctOdcCtl; - UINT32 PhyRODTCSLow; - UINT32 PhyRODTCSHigh; - UINT32 PhyWODTCSLow; - UINT32 PhyWODTCSHigh; - UINT8 PhyWLODT[4]; - UINT8 PSCfgODTSize; - UINT8 PSCfgWlODTSize; - BOOLEAN SlowMode; - UINT8 DimmTpMatch; - CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr; - CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr; - UINT8 *DimmsPerChPtr; - - ASSERT (MemData != NULL); - ASSERT (CurrentChannel != NULL); - - AddrTmgCTL = 0; - DctOdcCtl = 0; - PhyRODTCSLow = 0; - PhyRODTCSHigh = 0; - PhyWODTCSLow = 0; - PhyWODTCSHigh = 0; - PhyWLODT[0] = 0x0F; - PhyWLODT[1] = 0x0F; - PhyWLODT[2] = 0x0F; - PhyWLODT[3] = 0x0F; - - if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) { - return AGESA_UNSUPPORTED; - } - if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (CurrentChannel->RegDimmPresent) { - return AGESA_UNSUPPORTED; - } - // Prepare inputs - - DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmPerCH = *DimmsPerChPtr; - } else { - MaxDimmPerCH = 2; - } - - Loads = CurrentChannel->Loads; - Dimms = CurrentChannel->Dimms; - Speed = CurrentChannel->DCTPtr->Timings.Speed; - - DIMMRankType = MemAGetPsRankType (CurrentChannel); - - if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) { - SlowMode = TRUE; // 2T - } else { - SlowMode = FALSE; // 1T - } - - for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { - if (Speed == PSCfg[i].Speed) { - if (Loads <= PSCfg[i].Loads) { - AddrTmgCTL = PSCfg[i].AddrTmg; - DctOdcCtl = PSCfg[i].Odc; - break; - } - } - } - - ASSERT (i < GET_SIZE_OF (PSCfg)); - - if (MaxDimmPerCH == 3) { - PSCfgODTPtr = PSCfg3DIMMsODT; - PSCfgWlODTPtr = PSCfg3DIMMsWlODT; - PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); - PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); - } else { - PSCfgODTPtr = PSCfg2DIMMsODT; - PSCfgWlODTPtr = PSCfg2DIMMsWlODT; - PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); - PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); - } - - // Programmable ODT - for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) { - if (Dimms != PSCfgODTPtr->Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgODTPtr->Dimms) { - PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow; - PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh; - PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow; - PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh; - break; - } - } - - // WL ODT - for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) { - if (Dimms != PSCfgWlODTPtr->Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgWlODTPtr->Dimms) { - PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0]; - PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1]; - PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2]; - PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3]; - break; - } - } - - // - // Overrides and/or exceptions - // - if (Dimms == 1) { - if (Loads >= 16) { - if (Speed == DDR800_FREQUENCY) { - AddrTmgCTL = 0x003B0000; - } else if (Speed == DDR1066_FREQUENCY) { - AddrTmgCTL = 0x00380000; - } else if (Speed == DDR1333_FREQUENCY) { - AddrTmgCTL = 0x00360000; - } else { - AddrTmgCTL = 0x00340000; - SlowMode = TRUE; - } - } else { - AddrTmgCTL = 0; - } - DctOdcCtl = 0x20113222; - } - - CurrentChannel->MemClkDisMap = (UINT8 *) C32UDdr3CLKDis; - CurrentChannel->CKETriMap = (UINT8 *) C32UDdr3CKETri; - CurrentChannel->ChipSelTriMap = (UINT8 *) C32UDdr3CSTri; - - switch (MaxDimmPerCH) { - case 3: - CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri3D; - break; - default: - CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri2D; // Most conservative - } - - CurrentChannel->DctEccDqsLike = 0x0403; - CurrentChannel->DctEccDqsScale = 0x70; - CurrentChannel->DctAddrTmg = AddrTmgCTL; - CurrentChannel->DctOdcCtl = DctOdcCtl; - CurrentChannel->PhyRODTCSLow = PhyRODTCSLow; - CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh; - CurrentChannel->PhyWODTCSLow = PhyWODTCSLow; - CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh; - for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { - CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; - } - CurrentChannel->SlowMode = SlowMode; - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/Makefile.inc deleted file mode 100644 index a9f4861d45..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += marhy3.c -libagesa-y += mauhy3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/marhy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/marhy3.c deleted file mode 100644 index 3f37034a6e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/marhy3.c +++ /dev/null @@ -1,577 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * marhy3.c - * - * Memory Controller, registered dimms - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ardk) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support AM3 */ - - -#include "AGESA.h" -#include "ma.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_ARDK_HY_MARHY3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -STATIC CONST UINT8 ROMDATA HyRDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00}; - -// Even chip select maps to M[B,A]_CKE[0] -// Odd chip select maps to M[B,A]_CKE[1] -STATIC CONST UINT8 ROMDATA HyRDdr3CKETri[] = {0x55, 0xAA}; - -// 2 dimms per channel -// Dimm 0: BP_MEMODTx[2,0] -// Dimm 1: BP_MEMODTx[3,1] -STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8}; -// 3 dimms per channel -// Dimm 0: BP_MEMODTx[0] -// Dimm 1: BP_MEMODTx[3,1] -// Dimm 2: BP_MEMODTx[2] -STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8}; -// 4 dimms per channel -// Dimm 0: BP_MEMODTx[0] -// Dimm 1: BP_MEMODTx[1] -// Dimm 2: BP_MEMODTx[2] -// Dimm 3: BP_MEMODTx[3] -STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0}; - -// BIOS must not tri-state chip select pin corresponding to the second chip -// select of a single rank registered dimm -STATIC CONST UINT8 ROMDATA HyRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for HY DDR3 L1 system - * - * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE - * @param[in] SocketID Socket number - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return AGESA_SUCCESS - * @return CurrentChannel->MemClkDisMap Points this pointer to HY MemClkDis table - * @return CurrentChannel->ChipSelTriMap Points this pointer to HY CS table - * @return CurrentChannel->CKETriMap Points this pointer to HY ODT table - * @return CurrentChannel->ODTTriMap Points this pointer to HY CKE table - * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC - * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte - * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel - * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel - * @return CurrentChannel->SlowMode Slow Mode - * - */ - -AGESA_STATUS -MemAGetPsCfgRHy3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ) -{ - // - // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel - // - // Code searches table for matching speed, then matches the current dimm - // population and # of dimms to current config and programs the Addr Timing and RC2/RC2 - // - // Frequency, Dimm Config , - // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match - // - STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = { - {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x00000000, 0x0000, 1}, - {DDR800_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ - 0x00000000, 0x0040, 1}, - {DDR800_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \ - 0x00000000, 0x4004, 2}, - {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x003C3C3C, 0x0000,1}, - {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ - 0x003C3C3C, 0x0040, 1}, - {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x003A3C3A, 0x4004, 2}, - {DDR1066_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \ - 0x003A3C3A, 0x4004, 2}, - {DDR1066_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \ - 0x003A3C3A, 0x4004, 2}, - {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x003A3A3A, 0x0000, 1}, - {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ - 0x003A3A3A, 0x0040, 1}, - {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x00383A38, 0x4040, 2}, - {DDR1333_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \ - 0x00383A38, 0x4004, 2}, - {DDR1333_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \ - 0x00383A38, 0x4004, 2}, - {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x00373937, 0x0000, 1}, - {DDR1600_FREQUENCY, QR_DIMM0 + QR_DIMM1, \ - 0x00373937, 0x0040, 1}, - {DDR1600_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \ - 0x00353935, 0x4004, 2} - }; - // - // Address Timings and Drive Strengths for 3 DIMMs per channel - // - // Code searches table for matching speed, then matches the current dimm - // population and # of dimms to current config and programs the Addr Timing and RC2/RC2 - // - // Frequency, Dimm Config , - // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match - // - STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = { - {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00000000, 0x0000, 1}, - {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00000000, 0x4040, 2}, - {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00380038, 0x4004, 3}, - {DDR800_FREQUENCY, QR_DIMM1, \ - 0x00000000, 0x0040, 1}, - {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00000000, 0x4004, 2}, - {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x003C3C3C, 0x0000, 1}, - {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x003A3C3A, 0x4040, 2}, - {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00373C37, 0x4040, 3}, - {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00373C37, 0x4004, 3}, - {DDR1066_FREQUENCY, QR_DIMM1, \ - 0x003C3C3C, 0x0040, 1}, - {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x003A3C3A, 0x4004, 2}, - {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x003A3A3A, 0x0000, 1}, - {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00383A38, 0x4040, 2}, - {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00343A34, 0x4004, 3}, - {DDR1333_FREQUENCY, QR_DIMM1, \ - 0x003A3A3A, 0x0040, 1}, - {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00383A38, 0x4004, 2}, - {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00393939, 0x0000, 1}, - {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00363936, 0x4040, 2}, - {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00303930, 0x4004, 3}, - {DDR1600_FREQUENCY, QR_DIMM1, \ - 0x00393939, 0x0040, 1}, - {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x00363936, 0x4004, 2} - }; - // - // DIMM ODT Pattern (1 or 2 DIMMs per channel) - // - // Dimm Config , - // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match - // - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = { - {SR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, - {DR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1}, - {QR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000505, 0x00000505, 1}, - {SR_DIMM1, \ - 0x00000000, 0x00000000, 0x00020000, 0x00000000, 1}, - {DR_DIMM1, \ - 0x00000000, 0x00000000, 0x02080000, 0x00000000, 1}, - {QR_DIMM1, \ - 0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x01010202, 0x00000000, 0x09030603, 0x00000000, 2}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \ - 0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2}, - {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \ - 0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2}, - {QR_DIMM0 + QR_DIMM1, \ - 0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2} - }; - // DIMM ODT Pattern (3 DIMMs per channel) - // - // Dimm Config , - // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match - // - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = { - {SR_DIMM2 + DR_DIMM2, \ - 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1}, - {SR_DIMM0 + DR_DIMM0, \ - 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \ - 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3}, - {QR_DIMM1, \ - 0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1}, - {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \ - 0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \ - 0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3} - }; - // - // DIMM ODT Pattern (4 DIMMs per channel) - // - // Dimm Config , - // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match - // - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = { - {ANY_DIMM3, \ - 0x00000000, 0x00000000, 0x00000000, 0x08080000, 1}, - {ANY_DIMM2 + ANY_DIMM3, \ - 0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2}, - {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \ - 0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3}, - {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \ - 0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4} - }; - // - // DIMM Write Leveling ODT Pattern for 1 or 2 Dimms Per Channel - // - // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match - // - STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = { - {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, - {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, - {QR_DIMM0, {0x05, 0x00, 0x00, 0x00}, 1}, - {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, - {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, - {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}, - {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, - {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, - {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2}, - {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2}, - {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2} - }; - // - // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel - // - // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match - // - STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = { - {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1}, - {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3}, - {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1}, - {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3} - }; - // - // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel - // - // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match - // - STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = { - {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1}, - {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2}, - {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3}, - {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4} - }; - - UINT16 i; - UINT16 j; - UINT8 MaxDimmPerCH; - UINT8 Dimms; - UINT16 Speed; - UINT16 DIMMRankType; - UINT16 _DIMMRankType; - UINT8 DimmTpMatch; - UINT32 AddrTmgCTL; - UINT32 DctOdcCtl; - UINT16 RC2RC8; - UINT32 PhyRODTCSLow; - UINT32 PhyRODTCSHigh; - UINT32 PhyWODTCSLow; - UINT32 PhyWODTCSHigh; - BOOLEAN SlowMode; - UINT8 PSCfgSize; - UINT8 PSCfgODTSize; - UINT8 PSCfgWlODTSize; - UINT8 PhyWLODT[4]; - - CONST ADV_R_PSCFG_ENTRY *PSCfgPtr; - CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr; - CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr; - UINT8 *DimmsPerChPtr; - - ASSERT (MemData != NULL); - ASSERT (CurrentChannel != NULL); - - AddrTmgCTL = 0; - DctOdcCtl = 0; - RC2RC8 = 0; - PhyRODTCSLow = 0; - PhyRODTCSHigh = 0; - PhyWODTCSLow = 0; - PhyWODTCSHigh = 0; - SlowMode = FALSE; - PhyWLODT[0] = 0x0F; - PhyWLODT[1] = 0x0F; - PhyWLODT[2] = 0x0F; - PhyWLODT[3] = 0x0F; - - if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { - return AGESA_UNSUPPORTED; - } - if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (CurrentChannel->RegDimmPresent == 0) { - return AGESA_UNSUPPORTED; - } - - // Prepare inputs - Dimms = CurrentChannel->Dimms; - Speed = CurrentChannel->DCTPtr->Timings.Speed; - DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmPerCH = *DimmsPerChPtr; - } else { - MaxDimmPerCH = 2; - } - - DIMMRankType = MemAGetPsRankType (CurrentChannel); - - if (MaxDimmPerCH == 4) { - PSCfgPtr = NULL; - PSCfgSize = 0; - PSCfgODTPtr = PSCfg4DIMMsODT; - PSCfgWlODTPtr = PSCfg4DIMMsWlODT; - PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); - PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); - } else if (MaxDimmPerCH == 3) { - PSCfgPtr = PSCfg3DIMMs; - PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY); - PSCfgODTPtr = PSCfg3DIMMsODT; - PSCfgWlODTPtr = PSCfg3DIMMsWlODT; - PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); - PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); - } else { - PSCfgPtr = PSCfg2DIMMs; - PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY); - PSCfgODTPtr = PSCfg2DIMMsODT; - PSCfgWlODTPtr = PSCfg2DIMMsWlODT; - PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); - PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); - } - - // AddrTmgCTL and DctOdcCtl - if (MaxDimmPerCH != 4) { - for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) { - if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgPtr->Dimms) { - AddrTmgCTL = PSCfgPtr->AddrTmg; - DctOdcCtl = 0x00223222; - RC2RC8 = PSCfgPtr->RC2RC8; - break; - } - } - } - - // - // Overrides and/or exceptions - // - DimmTpMatch = 0; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (MaxDimmPerCH == 4) { - if (DimmTpMatch > 0) { - DctOdcCtl = 0x00223222; - if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) { - DctOdcCtl = 0x00113222; - } - } - if (DimmTpMatch >= 3) { - AddrTmgCTL |= 0x002F0000; - } - if (DimmTpMatch >= 2) { - RC2RC8 = 0x4040; - } - } else if ((MaxDimmPerCH == 3) && (CurrentChannel->Dimms == 3)) { - DctOdcCtl = 0x00113222; - } else { - if ((Dimms == 1) && (DimmTpMatch == 1)) { - DctOdcCtl = 0x00113222; - } - } - - //RC2 and RC8 - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution. - if (CurrentChannel->CtrlWrd02[j] > 0) { - if (CurrentChannel->CtrlWrd02[j] == 1) { - // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s). - CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F; - CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F; - } else { - // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s). - CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F; - CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F; - } - } - } - - //Programmable ODT - for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) { - if (Dimms != PSCfgODTPtr->Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgODTPtr->Dimms) { - PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow; - PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh; - PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow; - PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh; - break; - } - } - - //WLODT - for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) { - if (Dimms != PSCfgWlODTPtr->Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgWlODTPtr->Dimms) { - PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0]; - PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1]; - PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2]; - PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3]; - break; - } - } - - // Set ProcODT - DctOdcCtl |= 0x20000000; - - CurrentChannel->MemClkDisMap = (UINT8 *) HyRDdr3CLKDis; - CurrentChannel->CKETriMap = (UINT8 *) HyRDdr3CKETri; - CurrentChannel->ChipSelTriMap = (UINT8 *) HyRDdr3CSTri; - - switch (MaxDimmPerCH) { - case 3: - CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri3D; - break; - case 4: - CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri4D; - break; - default: - CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri2D; // Most conservative - } - - CurrentChannel->DctAddrTmg = AddrTmgCTL; - CurrentChannel->DctOdcCtl = DctOdcCtl; - CurrentChannel->PhyRODTCSLow = PhyRODTCSLow; - CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh; - CurrentChannel->PhyWODTCSLow = PhyWODTCSLow; - CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh; - for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { - CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; - } - CurrentChannel->SlowMode = SlowMode; - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/mauhy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/mauhy3.c deleted file mode 100644 index d598392316..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/HY/mauhy3.c +++ /dev/null @@ -1,356 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mauhy3.c - * - * Platform specific settings for HY DDR3 unbuffered dimms - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ardk) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -/* This file contains routine that add platform specific support AM3 */ - - -#include "AGESA.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_ARDK_HY_MAUHY3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -STATIC CONST UINT8 ROMDATA HyUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; -// Even chip select maps to M[B,A]_CKE[0] -// Odd chip select maps to M[B,A]_CKE[1] -STATIC CONST UINT8 ROMDATA HyUDdr3CKETri[] = {0x55, 0xAA}; -// Bit 0: M[B,A]0_ODT[0] -// Bit 1: M[B,A]1_ODT[0] -// Bit 2: M[B,A]0_ODT[1] -// Bit 3: M[B,A]1_ODT[1] -STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08}; -// 3 dimms per channel -// Dimm 0: BP_MEMODTx[0] -// Dimm 1: BP_MEMODTx[3,1] -// Dimm 2: BP_MEMODTx[2] -STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF}; -// Bit 0: M[B,A]0_CS_H/L[0] -// Bit 1: M[B,A]0_CS_H/L[1] -// Bit 2: M[B,A]0_CS_H/L[2] -// Bit 3: M[B,A]0_CS_H/L[3] -STATIC CONST UINT8 ROMDATA HyUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for HY DDR3 unbuffered dimms - * - * - * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE - * @param[in] SocketID Socket number - * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return AGESA_SUCCESS - * @return CurrentChannel->MemClkDisMap Points this pointer to HY MemClkDis table - * @return CurrentChannel->ChipSelTriMap Points this pointer to HY CS table - * @return CurrentChannel->CKETriMap Points this pointer to HY ODT table - * @return CurrentChannel->ODTTriMap Points this pointer to HY CKE table - * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC - * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte - * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel - * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel - * @return CurrentChannel->SlowMode Slow Mode - * - * - */ - -AGESA_STATUS -MemAGetPsCfgUHy3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ) -{ - STATIC CONST PSCFG_ENTRY PSCfg[] = { - {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323}, - {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323}, - {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323}, - {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323} - }; - - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = { - {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1}, - {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1}, - {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1}, - {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2}, - }; - - STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = { - {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1}, - {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1}, - {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1}, - {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2} - }; - - STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = { - {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1}, - //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2}, - //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3}, - }; - - STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = { - {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1}, - //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2}, - //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3}, - }; - - UINT16 i; - UINT16 j; - UINT8 MaxDimmPerCH; - UINT8 Loads; - UINT8 Dimms; - UINT16 Speed; - UINT16 DIMMRankType; - UINT16 _DIMMRankType; - UINT32 AddrTmgCTL; - UINT32 DctOdcCtl; - UINT32 PhyRODTCSLow; - UINT32 PhyRODTCSHigh; - UINT32 PhyWODTCSLow; - UINT32 PhyWODTCSHigh; - UINT8 PhyWLODT[4]; - UINT8 PSCfgODTSize; - UINT8 PSCfgWlODTSize; - BOOLEAN SlowMode; - UINT8 DimmTpMatch; - CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr; - CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr; - UINT8 *DimmsPerChPtr; - - ASSERT (MemData != NULL); - ASSERT (CurrentChannel != NULL); - - AddrTmgCTL = 0; - DctOdcCtl = 0; - PhyRODTCSLow = 0; - PhyRODTCSHigh = 0; - PhyWODTCSLow = 0; - PhyWODTCSHigh = 0; - PhyWLODT[0] = 0x0F; - PhyWLODT[1] = 0x0F; - PhyWLODT[2] = 0x0F; - PhyWLODT[3] = 0x0F; - - if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { - return AGESA_UNSUPPORTED; - } - if (CurrentChannel->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (CurrentChannel->RegDimmPresent) { - return AGESA_UNSUPPORTED; - } - // Prepare inputs - - DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmPerCH = *DimmsPerChPtr; - } else { - MaxDimmPerCH = 2; - } - - Loads = CurrentChannel->Loads; - Dimms = CurrentChannel->Dimms; - Speed = CurrentChannel->DCTPtr->Timings.Speed; - - DIMMRankType = MemAGetPsRankType (CurrentChannel); - - if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) { - SlowMode = TRUE; // 2T - } else { - SlowMode = FALSE; // 1T - } - - for (i = 0; i < GET_SIZE_OF (PSCfg); i++) { - if (Speed == PSCfg[i].Speed) { - if (Loads <= PSCfg[i].Loads) { - AddrTmgCTL = PSCfg[i].AddrTmg; - DctOdcCtl = PSCfg[i].Odc; - break; - } - } - } - - ASSERT (i < GET_SIZE_OF (PSCfg)); - - if (MaxDimmPerCH == 3) { - PSCfgODTPtr = PSCfg3DIMMsODT; - PSCfgWlODTPtr = PSCfg3DIMMsWlODT; - PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); - PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); - } else { - PSCfgODTPtr = PSCfg2DIMMsODT; - PSCfgWlODTPtr = PSCfg2DIMMsWlODT; - PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY); - PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY); - } - - // Programmable ODT - for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) { - if (Dimms != PSCfgODTPtr->Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgODTPtr->Dimms) { - PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow; - PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh; - PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow; - PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh; - break; - } - } - - // WL ODT - for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) { - if (Dimms != PSCfgWlODTPtr->Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == PSCfgWlODTPtr->Dimms) { - PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0]; - PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1]; - PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2]; - PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3]; - break; - } - } - - // - // Overrides and/or exceptions - // - if (Dimms == 1) { - if (Loads >= 16) { - if (Speed == DDR800_FREQUENCY) { - AddrTmgCTL = 0x003B0000; - } else if (Speed == DDR1066_FREQUENCY) { - AddrTmgCTL = 0x00380000; - } else if (Speed == DDR1333_FREQUENCY) { - AddrTmgCTL = 0x00360000; - } else { - AddrTmgCTL = 0x00340000; - SlowMode = TRUE; - } - } else { - AddrTmgCTL = 0; - } - DctOdcCtl = 0x20113222; - } - - CurrentChannel->MemClkDisMap = (UINT8 *) HyUDdr3CLKDis; - CurrentChannel->CKETriMap = (UINT8 *) HyUDdr3CKETri; - CurrentChannel->ChipSelTriMap = (UINT8 *) HyUDdr3CSTri; - - switch (MaxDimmPerCH) { - case 3: - CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri3D; - break; - default: - CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri2D; // Most conservative - } - - CurrentChannel->DctEccDqsLike = 0x0403; - CurrentChannel->DctEccDqsScale = 0x70; - CurrentChannel->DctAddrTmg = AddrTmgCTL; - CurrentChannel->DctOdcCtl = DctOdcCtl; - CurrentChannel->PhyRODTCSLow = PhyRODTCSLow; - CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh; - CurrentChannel->PhyWODTCSLow = PhyWODTCSLow; - CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh; - for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) { - CurrentChannel->PhyWLODT[i] = PhyWLODT[i]; - } - CurrentChannel->SlowMode = SlowMode; - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/Makefile.inc deleted file mode 100644 index 3b5087cbcb..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += ma.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/Makefile.inc deleted file mode 100644 index 6e046d1830..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += maror3.c -libagesa-y += mauor3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/maror3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/maror3.c deleted file mode 100644 index c73f7ea4d2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/maror3.c +++ /dev/null @@ -1,105 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * maror3.c - * - * Memory Controller, registered dimms - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ardk) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support AM3 */ - - -#include "AGESA.h" -#include "ma.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_ARDK_OR_MAROR3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for OR DDR3 L1 system - * - * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE - * @param[in] SocketID Socket number - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemAGetPsCfgROr3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ) -{ - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/mauor3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/mauor3.c deleted file mode 100644 index 7c240a9004..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/OR/mauor3.c +++ /dev/null @@ -1,106 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mauor3.c - * - * Platform specific settings for OR DDR3 unbuffered dimms - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ardk) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -/* This file contains routine that add platform specific support AM3 */ - - -#include "AGESA.h" -#include "ma.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_ARDK_OR_MAUOR3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for OR DDR3 unbuffered dimms - * - * - * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE - * @param[in] SocketID Socket number - * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return AGESA_SUCCESS - * - * - */ - -AGESA_STATUS -MemAGetPsCfgUOr3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ) -{ - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/ma.c deleted file mode 100644 index e29e4000e6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/ma.c +++ /dev/null @@ -1,144 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * ma.c - * - * Initializes ARDK Block - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ardk) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "ma.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_ARDK_MA_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is the default return function of the ARDK block. The function always - * returns AGESA_UNSUPPORTED - * - * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE - * @param[in] SocketID Socket number - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return AGESA_UNSUPPORTED AGESA status indicating that default is unsupported - * - */ - -AGESA_STATUS -MemAGetPsCfgDef ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ) -{ - return AGESA_UNSUPPORTED; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the rank type map of a channel. - * - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return UINT16 - The map of rank type. - * - */ -UINT16 -MemAGetPsRankType ( - IN CH_DEF_STRUCT *CurrentChannel - ) -{ - UINT8 i; - UINT16 DIMMRankType; - - DIMMRankType = 0; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if (CurrentChannel->MCTPtr->Status[SbLrdimms]) { - if ((CurrentChannel->LrDimmPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) 1 << (i << 2); - } - } else { - if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) { - if (i < 2) { - DIMMRankType |= (UINT16) 4 << (i << 2); - } - } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) 2 << (i << 2); - } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) 1 << (i << 2); - } - } - } - return DIMMRankType; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/Makefile.inc deleted file mode 100644 index 6599c4723d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfchi.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.c deleted file mode 100644 index fb2d5b4302..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.c +++ /dev/null @@ -1,210 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfchi.c - * - * Feature Channel interleaving support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/Chintlv) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "mfchi.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define _4GB_ (0x10000ul >> 10) - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * MemFInterleaveChannels: - * - * Applies DIMM channel interleaving if enabled, if not ganged mode, and - * there are valid dimms in both channels. Called once per Node. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFInterleaveChannels ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 DramBase; - UINT32 DctSelBase; - UINT32 HoleSize; - UINT32 HoleBase; - UINT32 HoleOffset; - UINT32 Dct0Size; - UINT32 Dct1Size; - UINT32 SmallerDct; - UINT8 DctSelIntLvAddr; - UINT8 DctSelHi; - UINT8 DctSelHiRngEn; - UINT32 HoleValid; - - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - - ASSERT (NBPtr != NULL); - - RefPtr = NBPtr->RefPtr; - - DctSelIntLvAddr = NBPtr->DefDctSelIntLvAddr; - if (RefPtr->EnableChannelIntlv) { - HoleSize = 0; - HoleBase = 0; - if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) { - // HoleBase scaled from [47:16] to [47:26] - HoleBase = RefPtr->HoleBase >> 10; - HoleSize = _4GB_ - HoleBase; - } - - MCTPtr = NBPtr->MCTPtr; - - HoleValid = NBPtr->GetBitField (NBPtr, BFDramHoleValid); - if ((!MCTPtr->GangedMode) && - (MCTPtr->DctData[0].Timings.DctMemSize != 0) && - (MCTPtr->DctData[1].Timings.DctMemSize != 0)) { - // DramBase scaled [47:16] to [47:26] - DramBase = MCTPtr->NodeSysBase >> 10; - // Scale NodeSysLimit [47:16] to [47:26] - Dct1Size = (MCTPtr->NodeSysLimit + 1) >> 10; - Dct0Size = NBPtr->GetBitField (NBPtr, BFDctSelBaseOffset); - if ((Dct0Size >= _4GB_) && (DramBase < HoleBase)) { - Dct0Size -= HoleSize; - } - if ((Dct1Size >= _4GB_) && (DramBase < HoleBase)) { - Dct1Size -= HoleSize; - } - Dct1Size -= Dct0Size; - Dct0Size -= DramBase; - - // Select the bigger size DCT to put in DctSelHi - DctSelHiRngEn = 1; - DctSelHi = 0; - SmallerDct = Dct1Size; - if (Dct1Size == Dct0Size) { - SmallerDct = 0; - DctSelHiRngEn = 0; - } else if (Dct1Size > Dct0Size) { - SmallerDct = Dct0Size; - DctSelHi = 1; - } - - if (SmallerDct != 0) { - DctSelBase = (SmallerDct * 2) + DramBase; - } else { - DctSelBase = 0; - } - if ((DctSelBase >= HoleBase) && (DramBase < HoleBase)) { - DctSelBase += HoleSize; - } - IDS_OPTION_HOOK (IDS_CHANNEL_INTERLEAVE, &DctSelIntLvAddr, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, DctSelBase >> 1); - NBPtr->SetBitField (NBPtr, BFDctSelHiRngEn, DctSelHiRngEn); - NBPtr->SetBitField (NBPtr, BFDctSelHi, DctSelHi); - NBPtr->SetBitField (NBPtr, BFDctSelIntLvAddr, DctSelIntLvAddr); - NBPtr->SetBitField (NBPtr, BFDctSelIntLvEn, 1); - - // DctSelBaseOffset = DctSelBaseAddr - Interleaved region - NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, DctSelBase - SmallerDct); - - // Adjust DramHoleOffset - if (HoleValid != 0) { - HoleOffset = DramBase; - if ((DctSelBase < HoleBase) && (DctSelBase != 0)) { - HoleOffset += (DctSelBase - DramBase) >> 1; - } - HoleOffset += HoleSize; - NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset << 3); - } - } else { - // - // Channel Interleaving is requested but cannot be enabled - // - PutEventLog (AGESA_WARNING, MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_WARNING, MCTPtr); - } - - return TRUE; - } else { - return FALSE; - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.h deleted file mode 100644 index 74a4194720..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfchi.h - * - * Feature channel interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFCHI_H_ -#define _MFCHI_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFInterleaveChannels ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFCHI_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/Makefile.inc deleted file mode 100644 index c7dc75b38c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfcsi.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.c deleted file mode 100644 index d1d7f9f7a1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.c +++ /dev/null @@ -1,354 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfcsi.c - * - * Feature bank interleaving support (AKA Chip Select Interleaving ) - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/Csintlv) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -/* This file contains functions for Chip Select interleaving */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mfcsi.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemFDctInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -CsIntSwap ( - IN OUT UINT32 *BaseMaskRegPtr, - IN UINT8 EnChipSels, - IN UINT8 LoBit, - IN UINT8 HiBit - ); - -BOOLEAN -MemFUndoInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Applies DIMM bank (chip-select) interleaving if enabled - * and if all criteria are met. Interleaves chip-selects on page boundaries. - * This function calls subfunctions that sets up CS interleaving on multiple Sockets - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - BOOLEAN RetFlag; - - ASSERT (NBPtr != NULL); - - RetFlag = FALSE; - if (NBPtr->RefPtr->EnableBankIntlv) { - if (NBPtr->MCTPtr->NodeMemSize) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - RetFlag |= MemFDctInterleaveBanks (NBPtr); - } - } - } - return RetFlag; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function checks if bank interleaving has been enabled or not. If yes, it will - * undo bank interleaving. Otherwise, it does nothing. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Bank interleaving has been enabled. - * @return FALSE - Bank interleaving has not been enabled. - */ - -BOOLEAN -MemFUndoInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Cs; - UINT8 Dct; - UINT32 CSMask; - BOOLEAN CSIntlvEnabled; - BOOLEAN RetFlag; - - ASSERT (NBPtr != NULL); - - RetFlag = FALSE; - - if (NBPtr->RefPtr->EnableBankIntlv) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize) { - CSIntlvEnabled = FALSE; - for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) { - if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) { - CSMask = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2)); - if (((CSMask >> 5) & 0x1FF) != 0x1FF) { - CSIntlvEnabled = TRUE; - break; - } - } - } - if (CSIntlvEnabled) { - MemFDctInterleaveBanks (NBPtr); - RetFlag = TRUE; - } - } - } - } - return RetFlag; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Applies DIMM bank (chip-select) interleaving if enabled - * and if all criteria are met. Interleaves chip-selects on page boundaries. - * This function is run once per Socket - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Register bits have been swapped. - * @return FALSE - Register bits have not been swapped. - * - */ - -BOOLEAN -STATIC -MemFDctInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Cs; - UINT8 EnChipSels; - UINT8 BankEncd; - UINT8 BankEncd0; - UINT8 i; - UINT8 j; - UINT32 BankAddrReg; - UINT32 BaseRegS0; - UINT32 BaseRegS1; - UINT32 MaskReg; - UINT8 Offset; - UINT8 Dct; - - ASSERT (NBPtr != NULL); - - Dct = NBPtr->Dct; - - // Check if CS interleaving can be enabled - EnChipSels = 0; - BankEncd0 = 0xFF; - Offset = 0; - for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) { - if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 3) != 0) { - BankAddrReg = NBPtr->GetBitField (NBPtr, BFDramBankAddrReg); - BankEncd = (UINT8) ((BankAddrReg >> ((Cs / 2) * 4)) & 0xF); - if (BankEncd0 == 0xFF) { - BankEncd0 = BankEncd; - } else if (BankEncd0 != BankEncd) { - break; - } - if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) { - EnChipSels++; - } - } - } - - // Swap Dram Base/Mask Addr to enable CS interleaving - if ((Cs == MAX_CS_PER_CHANNEL) && ((EnChipSels == 2) || (EnChipSels == 4) || (EnChipSels == 8))) { - NBPtr->TechPtr->GetCSIntLvAddr (BankEncd0, &i, &j); - // Family specific CS interleaving low address adjustment - NBPtr->FamilySpecificHook[AdjustCSIntLvLowAddr] (NBPtr, &i); - - if (NBPtr->MCTPtr->Status[Sb128bitmode]) { - i++; - j++; - } - - for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs += 2) { - // - // LRDIMMS - Add an offset to the bit positions specified based on D18F2x[6C:60]_dct[1:0][RankDef] as follows: - // RankDef=0xb: 0 RankDef=10b: 1 RankDef=11b: 2 - // Using RankMult information: Lo/HiBit <<= (Mult >> 1) - // - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - Offset = ((NBPtr->ChannelPtr->LrDimmRankMult[Cs >> 1]) >> 1); - } - BaseRegS0 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs); - BaseRegS1 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1); - if (((BaseRegS0 | BaseRegS1) & 1) != 0) { - // Swap Mask register bits - MaskReg = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2)); - CsIntSwap (&MaskReg, EnChipSels, (i + Offset), (j + Offset)); - NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (Cs / 2), MaskReg); - - // Swap Base register bits - CsIntSwap (&BaseRegS0, EnChipSels, (i + Offset), (j + Offset)); - NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs, BaseRegS0); - CsIntSwap (&BaseRegS1, EnChipSels, (i + Offset), (j + Offset)); - NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1, BaseRegS1); - } - } - // - // Bank Interleaving is requested and has been enabled as well - // - NBPtr->MCTPtr->DctData[Dct].BkIntDis = FALSE; - return TRUE; - } else { - // - // Bank Interleaving is requested but cannot be enabled - // - PutEventLog (AGESA_WARNING, MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_WARNING, NBPtr->MCTPtr); - NBPtr->MCTPtr->DctData[Dct].BkIntDis = TRUE; - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This supporting function swaps Chip selects - * - * @param[in,out] *BaseMaskRegPtr - Pointer to the Mask Register - * @param[in] *EnChipSels - Chip Selects to Enable - * @param[in] *LoBit - Lowest Bit - * @param[in] *HiBit - Highest Bit - * - * - */ - -VOID -STATIC -CsIntSwap ( - IN OUT UINT32 *BaseMaskRegPtr, - IN UINT8 EnChipSels, - IN UINT8 LoBit, - IN UINT8 HiBit - ) -{ - UINT8 BitDelta; - UINT32 TempHi; - UINT32 TempLo; - UINT32 AddrLoMask; - UINT32 AddrHiMask; - - ASSERT (BaseMaskRegPtr != NULL); - ASSERT (HiBit > LoBit); - - BitDelta = HiBit - LoBit; - AddrLoMask = (((UINT32)EnChipSels) - 1) << LoBit; - AddrHiMask = AddrLoMask << BitDelta; - - TempHi = TempLo = *BaseMaskRegPtr; - TempLo &= AddrLoMask; - TempLo <<= BitDelta; // move lower bits to upper bit position - TempHi &= AddrHiMask; - TempHi >>= BitDelta; // move upper bits to lower bit position - - *BaseMaskRegPtr &= ~AddrLoMask; - *BaseMaskRegPtr &= ~AddrHiMask; - *BaseMaskRegPtr |= TempLo | TempHi; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.h deleted file mode 100644 index 8e873f5ec1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfcsi.h - * - * Memory Controller - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFCSI_H_ -#define _MFCSI_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFInterleaveBanks ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFCSI_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/Makefile.inc deleted file mode 100644 index c5c1eac7d8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfDMI.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c deleted file mode 100644 index 1247e2f915..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c +++ /dev/null @@ -1,637 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfDMI.c - * - * Memory DMI table support. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 60218 $ @e \$Date: 2011-10-10 23:12:47 -0600 (Mon, 10 Oct 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Ids.h" -#include "heapManager.h" -#include "cpuServices.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_DMI_MFDMI_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -#define MAX_DCTS_PER_DIE 2 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemFDMISupport3 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -MemFDMISupport2 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets DDR3 DMI information from SPD buffer and stores the info into heap - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -BOOLEAN -MemFDMISupport3 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 i; - UINT8 Dimm; - UINT8 Socket; - UINT8 NodeId; - UINT8 Dct; - UINT8 Channel; - UINT8 temp; - UINT8 MaxDimms; - UINT8 DimmIndex; - UINT8 MaxChannelsPerSocket; - UINT8 MaxDimmsPerChannel; - UINT8 FormFactor; - UINT16 TotalWidth; - UINT16 Capacity; - UINT16 Width; - UINT16 Rank; - UINT16 BusWidth; - UINT64 ManufacturerIdCode; - UINT32 MaxSockets; - UINT32 Address; - UINT32 TotalSize; - UINT32 DimmSize; - UINT64 AddrValue; - INT32 MTB_ps; - INT32 FTB_ps; - INT32 Value32; - - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DMI_INFO *DmiTable; - MEM_PARAMETER_STRUCT *RefPtr; - - DIE_STRUCT *MCTPtr; - CH_DEF_STRUCT *ChannelPtr; - SPD_DEF_STRUCT *SpdDataStructure; - - NBPtr = MemMainPtr->NBPtr; - MemPtr = MemMainPtr->MemPtr; - SpdDataStructure = MemPtr->SpdDataStructure; - MCTPtr = NBPtr->MCTPtr; - RefPtr = MemPtr->ParameterListPtr; - - // Initialize local variables - MaxDimms = 0; - TotalSize = 0; - - AGESA_TESTPOINT (TpProcMemDmi, &MemPtr->StdHeader); - - ASSERT (NBPtr != NULL); - - MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ()); - for (Socket = 0; Socket < MaxSockets; Socket++) { - for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) { - temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); - MaxDimms = MaxDimms + temp; - } - } - - // Allocate heap for memory DMI table 16, 17, 19, 20 - AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 6 + sizeof (DMI_T17_MEMORY_TYPE); - - AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { - PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR3 - return FALSE; - } - - DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 6 + sizeof (DMI_T17_MEMORY_TYPE)); - *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms; // Number of memory devices - *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 6)) = Ddr3MemType; // Memory type - - // - // Gather memory DMI info - // - DimmIndex = 0; - for (Socket = 0; Socket < MaxSockets; Socket++) { - MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); - for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { - // - // Get Node number and Dct number for this channel - // - ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel]; - NodeId = ChannelPtr->MCTPtr->NodeId; - Dct = ChannelPtr->Dct; - NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct); - MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); - for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) { - DmiTable[DimmIndex].TotalWidth = 0xFFFF; - DmiTable[DimmIndex].DataWidth = 0xFFFF; - DmiTable[DimmIndex].MemorySize = 0; - DmiTable[DimmIndex].Speed = 0; - DmiTable[DimmIndex].ManufacturerIdCode = 0; - DmiTable[DimmIndex].Attributes = 0; - DmiTable[DimmIndex].StartingAddr = 0; - DmiTable[DimmIndex].EndingAddr = 0; - DmiTable[DimmIndex].DimmPresent = 0; - DmiTable[DimmIndex].Socket = Socket; - DmiTable[DimmIndex].Channel = Channel; - DmiTable[DimmIndex].Dimm = Dimm; - DmiTable[DimmIndex].ConfigSpeed = 0; - DmiTable[DimmIndex].ExtSize = 0; - DmiTable[DimmIndex].ExtStartingAddr = 0; - DmiTable[DimmIndex].ExtEndingAddr = 0; - - for (i = 0; i < 4; i++) { - DmiTable[DimmIndex].SerialNumber[i] = 0xFF; - } - - for (i = 0; i < 18; i++) { - DmiTable[DimmIndex].PartNumber[i] = 0x0; - } - - if (SpdDataStructure[DimmIndex].DimmPresent) { - // Total Width (offset 08h) & Data Width (offset 0Ah) - TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[8]; - if ((TotalWidth & 0x18) == 0) { - // non ECC - if ((TotalWidth & 0x07) == 0) { - DmiTable[DimmIndex].TotalWidth = 8; // 8 bits - } else if ((TotalWidth & 0x07) == 1) { - DmiTable[DimmIndex].TotalWidth = 16; // 16 bits - } else if ((TotalWidth & 0x07) == 2) { - DmiTable[DimmIndex].TotalWidth = 32; // 32 bits - } else if ((TotalWidth & 0x07) == 3) { - DmiTable[DimmIndex].TotalWidth = 64; // 64 bits - } - DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth ; - } else { - // ECC - if ((TotalWidth & 0x07) == 0) { - DmiTable[DimmIndex].TotalWidth = 8 + 8; // 8 bits - } else if ((TotalWidth & 0x07) == 1) { - DmiTable[DimmIndex].TotalWidth = 16 + 8; // 16 bits - } else if ((TotalWidth & 0x07) == 2) { - DmiTable[DimmIndex].TotalWidth = 32 + 8; // 32 bits - } else if ((TotalWidth & 0x07) == 3) { - DmiTable[DimmIndex].TotalWidth = 64 + 8; // 64 bits - } - DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth - 8; - } - - // Memory Size (offset 0Ch) - Capacity = 0; - BusWidth = 0; - Width = 0; - Rank = 0; - temp = (UINT8) SpdDataStructure[DimmIndex].Data[4]; - if ((temp & 0x0F) == 0) { - Capacity = 0x0100; // 256M - } else if ((temp & 0x0F) == 1) { - Capacity = 0x0200; // 512M - } else if ((temp & 0x0F) == 2) { - Capacity = 0x0400; // 1G - } else if ((temp & 0x0F) == 3) { - Capacity = 0x0800; // 2G - } else if ((temp & 0x0F) == 4) { - Capacity = 0x1000; // 4G - } else if ((temp & 0x0F) == 5) { - Capacity = 0x2000; // 8G - } else if ((temp & 0x0F) == 6) { - Capacity = 0x4000; // 16G - } - - temp = (UINT8) SpdDataStructure[DimmIndex].Data[8]; - if ((temp & 0x07) == 0) { - BusWidth = 8; // 8 bits - } else if ((temp & 0x07) == 1) { - BusWidth = 16; // 16 bits - } else if ((temp & 0x07) == 2) { - BusWidth = 32; // 32 bits - } else if ((temp & 0x07) == 3) { - BusWidth = 64; // 64 bits - } - - temp = (UINT8) SpdDataStructure[DimmIndex].Data[7]; - if ((temp & 0x07) == 0) { - Width = 4; // 4 bits - } else if ((temp & 0x07) == 1) { - Width = 8; // 8 bits - } else if ((temp & 0x07) == 2) { - Width = 16; // 16 bits - } else if ((temp & 0x07) == 3) { - Width = 32; // 32 bits - } - - temp = (UINT8) SpdDataStructure[DimmIndex].Data[7]; - if (((temp >> 3) & 0x07) == 0) { - Rank = 1; // 4 bits - DmiTable[DimmIndex].Attributes = 1; // Single Rank Dimm - } else if (((temp >> 3) & 0x07) == 1) { - Rank = 2; // 8 bits - DmiTable[DimmIndex].Attributes = 2; // Dual Rank Dimm - } else if (((temp >> 3) & 0x07) == 2) { - Rank = 3; // 16 bits - } else if (((temp >> 3) & 0x07) == 3) { - Rank = 4; // 32 bits - DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm - } - - if ((!BusWidth) || (!Width) || (!Rank)) - DimmSize = 0xFFFF; // size is unknown - else - DimmSize = (UINT32) (Capacity / 8 * BusWidth / Width * Rank); - if (DimmSize < 0x7FFF) { - DmiTable[DimmIndex].MemorySize = (UINT16) DimmSize; - } else { - DmiTable[DimmIndex].MemorySize = 0x7FFF; - DmiTable[DimmIndex].ExtSize = DimmSize; - } - - // Form Factor (offset 0Eh) - FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[3]; - if ((FormFactor & 0x0F) == 0x01 || (FormFactor & 0x0F) == 0x02) { - DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM - } else if ((FormFactor & 0x0F) == 0x03) { - DmiTable[DimmIndex].FormFactor = 0x0D; // SO-DIMM - } - - // DIMM Present - DmiTable[DimmIndex].DimmPresent = 1; - - // Speed (offset 15h) - - // If SPD is wrong, division by 0 in DIMM speed calculation could reboot CPU - // So avoid it by this check - if ((SpdDataStructure[DimmIndex].Data[11]==0) || - ((SpdDataStructure[DimmIndex].Data[9] & 0xF) == 0)) { - DmiTable[DimmIndex].Speed = 0; // Unknown - } else { - MTB_ps = ((INT32) SpdDataStructure[DimmIndex].Data[10] * 1000) / - SpdDataStructure[DimmIndex].Data[11]; - FTB_ps = (SpdDataStructure[DimmIndex].Data[9] >> 4) / - (SpdDataStructure[DimmIndex].Data[9] & 0xF); - Value32 = (MTB_ps * SpdDataStructure[DimmIndex].Data[12]) + - (FTB_ps * (INT8) SpdDataStructure[DimmIndex].Data[34]); - if (Value32 <= 938) { - DmiTable[DimmIndex].Speed = 1067; // DDR3-2133 - } else if (Value32 <= 1071) { - DmiTable[DimmIndex].Speed = 933; // DDR3-1866 - } else if (Value32 <= 1250) { - DmiTable[DimmIndex].Speed = 800; // DDR3-1600 - } else if (Value32 <= 1500) { - DmiTable[DimmIndex].Speed = 667; // DDR3-1333 - } else if (Value32 <= 1875) { - DmiTable[DimmIndex].Speed = 533; // DDR3-1066 - } else if (Value32 <= 2500) { - DmiTable[DimmIndex].Speed = 400; // DDR3-800 - } - } - - // Manufacturer (offset 17h) - ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[118]; - DmiTable[DimmIndex].ManufacturerIdCode = (ManufacturerIdCode << 8) | ((UINT64) SpdDataStructure[DimmIndex].Data[117]); - - // Serial Number (offset 18h) - for (i = 0; i < 4; i++) { - DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 122]; - } - // Part Number (offset 1Ah) - for (i = 0; i < 18; i++) { - DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 128]; - } - - // Configured Memory Clock Speed (offset 20h) - DmiTable[DimmIndex].ConfigSpeed = NBPtr[NodeId].DCTPtr->Timings.Speed; - - // Starting/Ending Address for each DIMM - // If Ending Address >= 0xFFFFFFFF, update Starting Address & Ending Address to 0xFFFFFFFF, - // and use the Extended Starting Address & Extended Ending Address instead. - if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) { - Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & NBPtr->CsRegMsk; - Address = (Address & 0xFFFF0000) >> 2; - DmiTable[DimmIndex].StartingAddr = Address; - if (RefPtr->EnableBankIntlv && !NBPtr[NodeId].MCTPtr->DctData[Dct].BkIntDis) { - AddrValue = (UINT64) Address + ((UINT64) ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSMask0Reg + Dimm) & 0xFFFF0000) + 0x00080000) >> 2) - 1; - if (AddrValue >= (UINT64) 0xFFFFFFFF) { - DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF; - DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF; - DmiTable[DimmIndex].ExtStartingAddr = (UINT64) Address; - DmiTable[DimmIndex].ExtEndingAddr = AddrValue; - } else { - DmiTable[DimmIndex].EndingAddr = (UINT32) AddrValue; - } - } else { - AddrValue = (UINT64) Address + (UINT64) (DmiTable[DimmIndex].MemorySize * 0x0400) - 1; - if (AddrValue >= (UINT64) 0xFFFFFFFF) { - DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF; - DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF; - DmiTable[DimmIndex].ExtStartingAddr = (UINT64) Address; - DmiTable[DimmIndex].ExtEndingAddr = AddrValue; - } else { - DmiTable[DimmIndex].EndingAddr = (UINT32) AddrValue; - } - } - } - } // Dimm present - TotalSize += (UINT32) DmiTable[DimmIndex].MemorySize; - } // Dimm loop - } // Channel loop - } // Socket loop - - *((UINT32 *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = TotalSize; // Max Capacity - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets DDR2 DMI information from SPD buffer and stores the info into heap - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -BOOLEAN -MemFDMISupport2 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 i; - UINT8 Dimm; - UINT8 Socket; - UINT8 NodeId; - UINT8 Dct; - UINT8 Channel; - UINT8 temp; - UINT8 MaxDimms; - UINT8 DimmIndex; - UINT8 MaxChannelsPerSocket; - UINT8 MaxDimmsPerChannel; - UINT8 FormFactor; - UINT8 Temp; - UINT8 Rank; - UINT16 TotalWidth; - UINT32 Speed; - UINT32 MaxSockets; - UINT32 Address; - - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DMI_INFO *DmiTable; - DIE_STRUCT *MCTPtr; - CH_DEF_STRUCT *ChannelPtr; - SPD_DEF_STRUCT *SpdDataStructure; - MEM_PARAMETER_STRUCT *RefPtr; - - NBPtr = MemMainPtr->NBPtr; - MemPtr = MemMainPtr->MemPtr; - SpdDataStructure = MemPtr->SpdDataStructure; - MCTPtr = NBPtr->MCTPtr; - RefPtr = MemPtr->ParameterListPtr; - - // Initialize local variables - MaxDimms = 0; - - ASSERT (NBPtr != NULL); - - MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ()); - for (Socket = 0; Socket < MaxSockets; Socket++) { - for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) { - temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); - MaxDimms = MaxDimms + temp; - } - } - - // Allocate heap for memory DMI table 16, 17, 19, 20 - AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 3; - - AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { - PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR2 - return FALSE; - } - - DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE)); - *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms; // Number of memory devices - *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = Ddr2MemType; // Memory type - - // - // DMI TYPE 17 - // - DimmIndex = 0; - for (Socket = 0; Socket < MaxSockets; Socket++) { - MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); - for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { - // - // Get Node number and Dct number for this channel - // - ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel]; - NodeId = ChannelPtr->MCTPtr->NodeId; - Dct = ChannelPtr->Dct; - NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct); - NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct); - MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel); - for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) { - DmiTable[DimmIndex].TotalWidth = 0xFFFF; - DmiTable[DimmIndex].DataWidth = 0xFFFF; - DmiTable[DimmIndex].MemorySize = 0xFFFF; - DmiTable[DimmIndex].Speed = 0; - DmiTable[DimmIndex].ManufacturerIdCode = 0; - DmiTable[DimmIndex].Attributes = 0; - DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF; - DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF; - DmiTable[DimmIndex].DimmPresent = 0; - DmiTable[DimmIndex].ConfigSpeed = 0; - - for (i = 0; i < 4; i++) { - DmiTable[DimmIndex].SerialNumber[i] = 0xFF; - } - - for (i = 0; i < 18; i++) { - DmiTable[DimmIndex].PartNumber[i] = 0x0; - } - - if (SpdDataStructure[DimmIndex].DimmPresent) { - // Total Width (offset 08h) & Data Width (offset 0Ah) - TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[13]; - if ((TotalWidth & 0x04) != 0) { - DmiTable[DimmIndex].TotalWidth = 4; // 4 bits - } else if ((TotalWidth & 0x08) != 0) { - DmiTable[DimmIndex].TotalWidth = 8; // 8 bits - } else if ((TotalWidth & 0x10) != 0) { - DmiTable[DimmIndex].TotalWidth = 16; // 16 bits - } else if ((TotalWidth & 0x20) != 0) { - DmiTable[DimmIndex].TotalWidth = 32; // 32 bits - } - DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth; - - // Memory Size (offset 0Ch), Attributes (offset 1Bh) - Rank = (UINT8) SpdDataStructure[DimmIndex].Data[5] & 0x07; - if (Rank == 0) { - DmiTable[DimmIndex].Attributes = 1; // Single Rank Dimm - } else if (Rank == 1) { - DmiTable[DimmIndex].Attributes = 2; // Dual Rank Dimm - } else if (Rank == 3) { - DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm - } - - Temp = (UINT8) SpdDataStructure[DimmIndex].Data[31]; - for (i = 0; i < 8; i++) { - if ((Temp & 0x01) == 1) { - DmiTable[DimmIndex].MemorySize = 0x80 * (i + 1) * (Rank + 1); - } - Temp = Temp >> 1; - } - - // Form Factor (offset 0Eh) - FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[20]; - if ((FormFactor & 0x04) == 4) { - DmiTable[DimmIndex].FormFactor = 0x0D; // SO-DIMM - } else { - DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM - } - - // DIMM Present - DmiTable[DimmIndex].DimmPresent = 1; - - // DIMM Index - DmiTable[DimmIndex].Socket = Socket; - DmiTable[DimmIndex].Channel = Channel; - DmiTable[DimmIndex].Dimm = Dimm; - - // Speed (offset 15h) - Speed = NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFDramConfigHiReg); - Speed = Speed & 0x00000007; - if (Speed == 0) { - DmiTable[DimmIndex].Speed = 400; // 400MHz - } else if (Speed == 1) { - DmiTable[DimmIndex].Speed = 533; // 533MHz - } else if (Speed == 2) { - DmiTable[DimmIndex].Speed = 667; // 667MHz - } else if (Speed == 3) { - DmiTable[DimmIndex].Speed = 800; // 800MHz - } - - // Manufacturer (offset 17h) - DmiTable[DimmIndex].ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[64]; - - // Serial Number (offset 18h) - for (i = 0; i < 4; i++) { - DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 95]; - } - - // Part Number (offset 1Ah) - for (i = 0; i < 18; i++) { - DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 73]; - } - - // Configured Memory Clock Speed (offset 20h) - DmiTable[DimmIndex].ConfigSpeed = NBPtr[NodeId].DCTPtr->Timings.Speed; - - // AGESA does NOT support this feature when bank interleaving is enabled. - if (!RefPtr->EnableBankIntlv) { - if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) { - Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & NBPtr->CsRegMsk; - Address = Address >> 2; - DmiTable[DimmIndex].StartingAddr = Address; - DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400); - } - } - - } // DIMM Present - } // DIMM loop - } - } - - return TRUE; -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/Makefile.inc deleted file mode 100644 index 25c0f38607..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += mfecc.c -libagesa-y += mfemp.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.c deleted file mode 100644 index cf4e32960e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.c +++ /dev/null @@ -1,290 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfecc.c - * - * Feature ECC initialization functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/ECC) - * @e \$Revision: 54543 $ @e \$Date: 2011-06-08 23:19:25 -0600 (Wed, 08 Jun 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mfecc.h" -#include "Filecode.h" -#include "mfmemclr.h" -#include "GeneralServices.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_ECC_MFECC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -InitECCOverriedeStruct ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT ECC_OVERRIDE_STRUCT *pecc_override_struct - ); - -BOOLEAN -MemFCheckECC ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function checks to see if ECC can be enabled on all nodes - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFCheckECC ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - DIE_STRUCT *MCTPtr; - MEM_SHARED_DATA *SharedPtr; - BOOLEAN ErrorRecovery; - - ASSERT (NBPtr != NULL); - - MCTPtr = NBPtr->MCTPtr; - SharedPtr = NBPtr->SharedPtr; - - ErrorRecovery = TRUE; - IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, &NBPtr->MemPtr->StdHeader); - - if (MCTPtr->NodeMemSize != 0) { - if (SharedPtr->AllECC && MCTPtr->Status[SbEccDimms] && (ErrorRecovery || (MCTPtr->ErrCode < AGESA_ERROR))) { - // Clear all MCA reports before using scrubber - // to initialize ECC check bits - // - NBPtr->McaNbCtlReg = NBPtr->GetBitField (NBPtr, BFMcaNbCtlReg); - NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, 0); - NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, 0); - // In unganged mode, set DctDctIntlv - if (!NBPtr->Ganged) { - NBPtr->SetBitField (NBPtr, BFDctDatIntLv, 1); - } - // - // Set Ecc Symbol Size - // - NBPtr->SetEccSymbolSize (NBPtr); - // If ECC can be enabled on this node, - // set the master ECCen bit (according to setup) - // - NBPtr->SetBitField (NBPtr, BFDramEccEn, 1); - // Do mem clear on current node - MemFMctMemClr_Init (NBPtr); - return TRUE; - } else { - if (SharedPtr->AllECC) { - SharedPtr->AllECC = FALSE; - } - // ECC requested but cannot be enabled - MCTPtr->Status[SbEccDimms] = FALSE; - MCTPtr->ErrStatus[EsbDramECCDis] = TRUE; - PutEventLog (AGESA_WARNING, MEM_WARNING_ECC_DIS, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_WARNING, MCTPtr); - } - } - return FALSE; -} - - /* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the ECC on all nodes - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFInitECC ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Node; - UINT32 ScrubAddrRJ16; - DIE_STRUCT *MCTPtr; - MEM_SHARED_DATA *SharedPtr; - ECC_OVERRIDE_STRUCT ecc_override_struct; - BOOLEAN Flag; - - InitECCOverriedeStruct (NBPtr, &ecc_override_struct); - IDS_OPTION_HOOK (IDS_ECC, &ecc_override_struct, &(NBPtr->MemPtr->StdHeader)); - - ASSERT (NBPtr != NULL); - - MCTPtr = NBPtr->MCTPtr; - Node = MCTPtr->NodeId; - SharedPtr = NBPtr->SharedPtr; - Flag = TRUE; - - NBPtr->FamilySpecificHook[ScrubberErratum] (NBPtr, (VOID *) &Flag); - - if ((MCTPtr->Status[SbEccDimms]) && (SharedPtr->AllECC)) { - // Check if the input dram scrub rate is supported or not - ASSERT (ecc_override_struct.CfgScrubDramRate <= 0x16); - if (ecc_override_struct.CfgScrubDramRate != 0) { - // Program scrub address, - // let the scrub Addr be the Base of this Node - // Only enable Dram scrubber when there is memory on current node - // - NBPtr->SetBitField (NBPtr, BFScrubReDirEn, 0); - ScrubAddrRJ16 = (NBPtr->GetBitField (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8; - ScrubAddrRJ16 |= NBPtr->GetBitField (NBPtr, BFDramBaseHiReg0 + Node) << 24; - NBPtr->SetBitField (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16); - NBPtr->SetBitField (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16); - NBPtr->SetBitField (NBPtr, BFDramScrub, ecc_override_struct.CfgScrubDramRate); - } - } - // Scrub CTL for Dcache, L2, L3 - // Check if the input L2 scrub rate is supported or not - ASSERT (ecc_override_struct.CfgScrubL2Rate <= 0x16); - NBPtr->SetBitField (NBPtr, BFL2Scrub, ecc_override_struct.CfgScrubL2Rate); - // Check if the input Dcache scrub rate is supported or not - ASSERT (ecc_override_struct.CfgScrubDcRate <= 0x16); - NBPtr->SetBitField (NBPtr, BFDcacheScrub, ecc_override_struct.CfgScrubDcRate); - // Do not enable L3 Scrub if F3xE8[L3Capable] is 0 or F3x188[BFReserved00B] is 1 - if ((NBPtr->GetBitField (NBPtr, BFL3Capable) == 1) && (NBPtr->GetBitField (NBPtr, BFReserved00B) == 0)) { - // Check if input L3 scrub rate is supported or not - ASSERT (ecc_override_struct.CfgScrubL3Rate <= 0x16); - NBPtr->SetBitField (NBPtr, BFL3Scrub, ecc_override_struct.CfgScrubL3Rate); - } - - // Check if Dcache scrubber or L2 scrubber is enabled - if ((ecc_override_struct.CfgScrubL2Rate != 0) || (ecc_override_struct.CfgScrubDcRate!= 0)) { - // If ClkDivisor is deeper than divide-by-16 - if (NBPtr->GetBitField (NBPtr, BFC1ClkDivisor) > 4) { - // Set it to divide-by-16 - NBPtr->SetBitField (NBPtr, BFC1ClkDivisor, 4); - } - } - - NBPtr->SetBitField (NBPtr, BFScrubReDirEn, ecc_override_struct.CfgEccRedirection); - NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, ecc_override_struct.CfgEccSyncFlood); - // Restore MCA reports after scrubber is done - // with initializing ECC check bits - NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, NBPtr->McaNbCtlReg); - - Flag = FALSE; - NBPtr->FamilySpecificHook[ScrubberErratum] (NBPtr, (VOID *) &Flag); - - return TRUE; -} - -VOID -STATIC -InitECCOverriedeStruct ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT ECC_OVERRIDE_STRUCT *pecc_override_struct - ) -{ - // - // If (D18F3x44[DramEccEn]==1) THEN 1 ELSE 0 ENDIF - // - if (NBPtr->GetBitField (NBPtr, BFDramEccEn) == 1) { - pecc_override_struct->CfgEccRedirection = 1; - } else { - pecc_override_struct->CfgEccRedirection = 0; - } - - pecc_override_struct->CfgEccSyncFlood = UserOptions.CfgEccSyncFlood; - pecc_override_struct->CfgScrubDcRate = UserOptions.CfgScrubDcRate; - - if (UserOptions.CfgScrubDramRate != 0xFF) { - pecc_override_struct->CfgScrubDramRate = UserOptions.CfgScrubDramRate; - } else { - if (NBPtr->MCTPtr->NodeMemSize <= 0x4000) { - pecc_override_struct->CfgScrubDramRate = 0x12; // 1 ~ 1 GB - } else if (NBPtr->MCTPtr->NodeMemSize <= 0x8000) { - pecc_override_struct->CfgScrubDramRate = 0x11; // 1 GB + 1 ~ 2 GB - } else if (NBPtr->MCTPtr->NodeMemSize <= 0x10000) { - pecc_override_struct->CfgScrubDramRate = 0x10; // 2 GB + 1 ~ 4 GB - } else if (NBPtr->MCTPtr->NodeMemSize <= 0x20000) { - pecc_override_struct->CfgScrubDramRate = 0x0F; // 4 GB + 1 ~ 8 GB - } else if (NBPtr->MCTPtr->NodeMemSize <= 0x40000) { - pecc_override_struct->CfgScrubDramRate = 0x0E; // 8 GB + 1 ~ 16 GB - } else { - pecc_override_struct->CfgScrubDramRate = 0x0D; //16 GB + 1 above - } - } - - pecc_override_struct->CfgScrubL2Rate = UserOptions.CfgScrubL2Rate; - pecc_override_struct->CfgScrubL3Rate = UserOptions.CfgScrubL3Rate; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.h deleted file mode 100644 index f2990e0cc8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfecc.h - * - * Feature ECC initialization functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFECC_H_ -#define _MFECC_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFInitECC ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFECC_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfemp.c deleted file mode 100644 index 6d3e9eb6ef..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ECC/mfemp.c +++ /dev/null @@ -1,176 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfemp.c - * - * Feature EMP initialization functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/ECC) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_ECC_MFEMP_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -IsPowerOfTwo ( - IN UINT32 TestNumber - ); - -BOOLEAN -MemFInitEMP ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes EMP (Enhanced Memory Protection) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFInitEMP ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - - ASSERT (NBPtr != NULL); - - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - if (RefPtr->EnableEccFeature) { - if (NBPtr->GetBitField (NBPtr, BFEnhMemProtCap) == 0) { - PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_SUPPORTED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - MCTPtr->ErrStatus[EsbEMPNotSupported] = TRUE; - } else if (RefPtr->EnableChannelIntlv || RefPtr->EnableBankIntlv || RefPtr->EnableBankSwizzle) { - PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_CONFLICT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - MCTPtr->ErrStatus[EsbEMPConflict] = TRUE; - } else if ((!MCTPtr->GangedMode) && - (!IsPowerOfTwo (MCTPtr->DctData[0].Timings.DctMemSize) && - !IsPowerOfTwo (MCTPtr->DctData[1].Timings.DctMemSize))) { - PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - MCTPtr->ErrStatus[EsbEMPDis] = TRUE; - } else { - // Reduce memory size to 7/8 of the original memory size - ASSERT ((MCTPtr->NodeMemSize % 8) == 0); - NBPtr->SetBitField (NBPtr, BFDramHoleValid, 0); - MCTPtr->NodeMemSize = (MCTPtr->NodeMemSize / 8) * 7; - NBPtr->HtMemMapInit (NBPtr); - NBPtr->CpuMemTyping (NBPtr); - - // Enable EMP - NBPtr->SetBitField (NBPtr, BFDramEccEn, 1); - - // Scrub CTL settings for Dcache, L2 - NBPtr->SetBitField (NBPtr, BFL2Scrub, UserOptions.CfgScrubL2Rate); - NBPtr->SetBitField (NBPtr, BFDcacheScrub, UserOptions.CfgScrubDcRate); - - NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, UserOptions.CfgEccSyncFlood); - return TRUE; - } - } - return FALSE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function checks to see if the input is power of two. - * - * @param[in] TestNumber - Value to check for power of two - * - * @return TRUE - is power of two - * FALSE - is not power of two - */ -BOOLEAN -STATIC -IsPowerOfTwo ( - IN UINT32 TestNumber - ) -{ - return (BOOLEAN) ((TestNumber & (TestNumber - 1)) == 0); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/Makefile.inc deleted file mode 100644 index 31cf348efc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfdimmexclud.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c deleted file mode 100644 index b608caf844..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +++ /dev/null @@ -1,205 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfdimmexclud.c - * - * Feature DIMM exclude. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/EXCLUDIMM) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemFRASExcludeDIMM ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and disable Chip selects that fail training for each node. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFRASExcludeDIMM ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 ReserveDCT; - UINT8 q; - BOOLEAN Flag; - BOOLEAN IsCSIntlvEnabled; - UINT16 CsTestFail; - DIE_STRUCT *MCTPtr; - BOOLEAN RetVal; - - ASSERT (NBPtr != NULL); - ReserveDCT = NBPtr->Dct; - CsTestFail = 0; - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.CsTestFail != 0) { - // When there is no new failed dimm that needs to be excluded, then no need to go through the process. - switch (NBPtr->SharedPtr->DimmExcludeFlag) { - case NORMAL: - // See there is new dimm that needs to be excluded - if ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0) { - CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail; - } - break; - case TRAINING: - // Do not do any dimm excluding during training - // Dimm exclude will be done at the end of training - break; - case END_TRAINING: - // Exclude all dimms that have failures during training - if ((NBPtr->DCTPtr->Timings.CsTrainFail != 0) || - ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0)) { - CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail; - } - break; - default: - IDS_ERROR_TRAP; - } - } - } - - if (CsTestFail != 0) { - IsCSIntlvEnabled = FALSE; - MCTPtr = NBPtr->MCTPtr; - MCTPtr->NodeMemSize = 0; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = FALSE; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = 0; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = 0; - NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0); - NBPtr->SetBitField (NBPtr, BFDramLimitAddr, 0); - - if (MCTPtr->GangedMode) { - // if ganged mode, disable all pairs of CS that fail. - NBPtr->DCTPtr->Timings.CsTestFail |= CsTestFail; - } - - // if chip select interleaving has been enabled, need to undo it before remapping memory - if (NBPtr->FeatPtr->UndoInterleaveBanks (NBPtr)) { - IsCSIntlvEnabled = TRUE; - } - - Flag = TRUE; - NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) { - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - NBPtr->DCTPtr->Timings.DctMemSize = 0; - - NBPtr->DCTPtr->Timings.CsEnabled = 0; - for (q = 0; q < MAX_CS_PER_CHANNEL; q++) { - NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0); - } - - // Set F2x94[DisDramInterface] = 1 if all chip selects fail training on the DCT - if ((NBPtr->DCTPtr->Timings.CsPresent & ~NBPtr->DCTPtr->Timings.CsTestFail) == 0) { - NBPtr->DisableDCT (NBPtr); - } - - Flag = NBPtr->StitchMemory (NBPtr); - ASSERT (Flag == TRUE); - } - } - } - Flag = FALSE; - NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag); - - // Re-enable chip select interleaving when remapping is done. - if (IsCSIntlvEnabled) { - NBPtr->FeatPtr->InterleaveBanks (NBPtr); - } - - RetVal = TRUE; - } else { - RetVal = FALSE; - } - NBPtr->SwitchDCT (NBPtr, ReserveDCT); - return RetVal; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/Makefile.inc deleted file mode 100644 index 8f98ec3c1b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfidendimm.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.c deleted file mode 100644 index 7315b8ed1d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.c +++ /dev/null @@ -1,550 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfidendimm.c - * - * Translate physical system address to dimm identification. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "heapManager.h" -#include "mfidendimm.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE -extern MEM_NB_SUPPORT memNBInstalled[]; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define MAX_DCTS_PER_DIE 2 ///< Max DCTs per die -#define MAX_CHLS_PER_DCT 1 ///< Max Channels per DCT - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -STATIC -MemFTransSysAddrToCS ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify, - IN MEM_MAIN_DATA_BLOCK *mmPtr - ); - -UINT32 -STATIC -MemFGetPCI ( - IN MEM_NB_BLOCK *NBPtr, - IN UINT8 NodeID, - IN UINT8 DctNum, - IN BIT_FIELD_NAME BitFieldName - ); - -UINT8 -STATIC -MemFUnaryXOR ( - IN UINT32 address - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*-----------------------------------------------------------------------------*/ -/** -* -* This function identifies the dimm on which the given memory address locates. -* -* @param[in, out] *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM -* -* @retval AGESA_SUCCESS - Successfully translate physical system address -* to dimm identification. -* AGESA_BOUNDS_CHK - Targeted address is out of bound. -* -*/ - -AGESA_STATUS -AmdIdentifyDimm ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify - ) -{ - UINT8 i; - AGESA_STATUS RetVal; - MEM_MAIN_DATA_BLOCK mmData; // Main Data block - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT MemData; - LOCATE_HEAP_PTR LocHeap; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT8 Node; - UINT8 Dct; - UINT8 Die; - UINT8 DieCount; - - LibAmdMemCopy (&(MemData.StdHeader), &(AmdDimmIdentify->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(AmdDimmIdentify->StdHeader)); - mmData.MemPtr = &MemData; - RetVal = MemSocketScan (&mmData); - if (RetVal == AGESA_FATAL) { - return RetVal; - } - DieCount = mmData.DieCount; - - // Search for AMD_MEM_AUTO_HANDLE on the heap first. - // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap. - LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE; - if (HeapLocateBuffer (&LocHeap, &AmdDimmIdentify->StdHeader) == AGESA_SUCCESS) { - // NB block has already been constructed by main block. - // No need to construct it here. - NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr; - mmData.NBPtr = NBPtr; - } else { - AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, &AmdDimmIdentify->StdHeader) != AGESA_SUCCESS) { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK, 0, 0, 0, 0, &AmdDimmIdentify->StdHeader); - ASSERT(FALSE); // Could not allocate heap space for NB block for Identify DIMM - return AGESA_FATAL; - } - NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; - mmData.NBPtr = NBPtr; - // Construct each die. - for (Die = 0; Die < DieCount; Die ++) { - i = 0; - while (memNBInstalled[i].MemIdentifyDimmConstruct != 0) { - if (memNBInstalled[i].MemIdentifyDimmConstruct (&NBPtr[Die], &MemData, Die)) { - break; - } - i++; - }; - if (memNBInstalled[i].MemIdentifyDimmConstruct == 0) { - PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM, Die, 0, 0, 0, &AmdDimmIdentify->StdHeader); - ASSERT(FALSE); // No Identify DIMM constructor found - return AGESA_FATAL; - } - } - } - - if ((RetVal = MemFTransSysAddrToCS (AmdDimmIdentify, &mmData)) == AGESA_SUCCESS) { - // Translate Node, DCT and Chip select number to Socket, Channel and Dimm number. - Node = AmdDimmIdentify->SocketId; - Dct = AmdDimmIdentify->MemChannelId; - AmdDimmIdentify->SocketId = MemData.DiesPerSystem[Node].SocketId; - AmdDimmIdentify->MemChannelId = NBPtr[Node].GetSocketRelativeChannel (&NBPtr[Node], Dct, 0); - AmdDimmIdentify->DimmId /= 2; - } - - return RetVal; -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*-----------------------------------------------------------------------------*/ -/** -* -* This function translates the given physical system address to -* a node, channel select, chip select, bank, row, and column address. -* -* @param[in, out] *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM -* @param[in, out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK -* -* @retval AGESA_SUCCESS - The chip select address is found -* @retval AGESA_BOUNDS_CHK - Targeted address is out of bound. -* -*/ -AGESA_STATUS -STATIC -MemFTransSysAddrToCS ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify, - IN MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - BOOLEAN CSFound; - BOOLEAN DctSelHiRngEn; - BOOLEAN DctSelIntLvEn; - BOOLEAN DctGangEn; - BOOLEAN HiRangeSelected; - BOOLEAN DramHoleValid; - BOOLEAN CSEn; - BOOLEAN SwapDone; - BOOLEAN IntLvRgnSwapEn; - UINT8 DctSelHi; - UINT8 DramEn; - UINT8 range; - UINT8 IntlvEn; - UINT8 IntlvSel; - UINT8 ILog; - UINT8 DctSelIntLvAddr; - UINT8 DctNum; - UINT8 cs; - UINT8 BadDramCs; - UINT8 spare; - UINT8 IntLvRgnBaseAddr; - UINT8 IntLvRgnLmtAddr; - UINT8 IntLvRgnSize; - UINT32 temp; - UINT32 DramHoleOffset; - UINT32 DramHoleBase; - UINT64 DramBase; - UINT64 DramLimit; - UINT64 DramLimitSysAddr; - UINT64 DctSelBaseAddr; - UINT64 DctSelBaseOffset; - UINT64 ChannelAddr; - UINT64 CSBase; - UINT64 CSMask; - UINT64 InputAddr; - UINT64 ChannelOffset; - MEM_NB_BLOCK *NBPtr; - UINT8 Die; - - UINT64 SysAddr; - UINT8 *NodeID; - UINT8 *ChannelSelect; - UINT8 *ChipSelect; - - SysAddr = AmdDimmIdentify->MemoryAddress; - NodeID = &(AmdDimmIdentify->SocketId); - ChannelSelect = &(AmdDimmIdentify->MemChannelId); - ChipSelect = &(AmdDimmIdentify->DimmId); - CSFound = FALSE; - ILog = 0; - NBPtr = mmPtr->NBPtr; - - NBPtr->FamilySpecificHook[FixupSysAddr] (NBPtr, &SysAddr); - - // Loop to determine the dram range - for (Die = 0; Die < mmPtr->DieCount; Die ++) { - range = NBPtr[Die].Node; - - // DRAM Base - temp = MemFGetPCI (NBPtr, 0, 0, BFDramBaseReg0 + range); - DramEn = (UINT8) (temp & 0x3); - IntlvEn = (UINT8) ((temp >> 8) & 0x7); - - DramBase = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramBaseHiReg0 + range) & 0xFF) << 40) | - (((UINT64) temp & 0xFFFF0000) << 8); - - // DRAM Limit - temp = MemFGetPCI (NBPtr, 0, 0, BFDramLimitReg0 + range); - *NodeID = (UINT8) (temp & 0x7); - IntlvSel = (UINT8) ((temp >> 8) & 0x7); - DramLimit = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramLimitHiReg0 + range) & 0xFF) << 40) | - (((UINT64) temp << 8) | 0xFFFFFF); - DramLimitSysAddr = (((UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDramLimitAddr)) << 27) | 0x7FFFFFF; - ASSERT (DramLimit <= DramLimitSysAddr); - - if ((DramEn != 0) && (DramBase <= SysAddr) && (SysAddr <= DramLimitSysAddr) && - ((IntlvEn == 0) || (IntlvSel == ((SysAddr >> 12) & IntlvEn)))) { - // Determine the number of bit positions consumed by Node Interleaving - switch (IntlvEn) { - - case 0x0: - ILog = 0; - break; - - case 0x1: - ILog = 1; - break; - - case 0x3: - ILog = 2; - break; - - case 0x7: - ILog = 3; - break; - - default: - IDS_ERROR_TRAP; - } - - DramHoleOffset = MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleOffset) << 23; - DramHoleValid = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleValid); - DramHoleBase = MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleBase) << 24; - // Address belongs to this node based on DramBase/Limit, - // but is in the memory hole so it doesn't map to DRAM - if (DramHoleValid && (DramHoleBase <= SysAddr) && (SysAddr < 0x100000000)) { - return AGESA_BOUNDS_CHK; - } - - // F2x10C Swapped Interleaved Region - IntLvRgnSwapEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSwapEn); - if (IntLvRgnSwapEn) { - IntLvRgnBaseAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnBaseAddr); - IntLvRgnLmtAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnLmtAddr); - IntLvRgnSize = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSize); - ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1)); - if (((SysAddr >> 34) == 0) && - ((((SysAddr >> 27) >= IntLvRgnBaseAddr) && ((SysAddr >> 27) <= IntLvRgnLmtAddr)) - || ((SysAddr >> 27) < IntLvRgnSize))) { - SysAddr ^= (UINT64) IntLvRgnBaseAddr << 27; - } - } - - // Extract variables from F2x110 DRAM Controller Select Low Register - DctSelHiRngEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHiRngEn); - DctSelHi = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHi); - DctSelIntLvEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvEn); - DctGangEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctGangEn); - DctSelIntLvAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvAddr); - DctSelBaseAddr = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseAddr) << 27; - DctSelBaseOffset = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseOffset) << 26; - - - // Determine if high DCT address range is being selected - if (DctSelHiRngEn && !DctGangEn && (SysAddr >= DctSelBaseAddr)) { - HiRangeSelected = TRUE; - } else { - HiRangeSelected = FALSE; - } - - // Determine Channel - if (DctGangEn) { - *ChannelSelect = (UINT8) ((SysAddr >> 3) & 0x1); - } else if (HiRangeSelected) { - *ChannelSelect = DctSelHi; - } else if (DctSelIntLvEn && (DctSelIntLvAddr == 0)) { - *ChannelSelect = (UINT8) ((SysAddr >> 6) & 0x1); - } else if (DctSelIntLvEn && (((DctSelIntLvAddr >> 1) & 0x1) != 0)) { - temp = MemFUnaryXOR ((UINT32) ((SysAddr >> 16) & 0x1F)); - if ((DctSelIntLvAddr & 0x1) != 0) { - *ChannelSelect = (UINT8) (((SysAddr >> 9) & 0x1) ^ temp); - } else { - *ChannelSelect = (UINT8) (((SysAddr >> 6) & 0x1) ^ temp); - } - } else if (DctSelIntLvEn) { - *ChannelSelect = (UINT8) ((SysAddr >> (12 + ILog)) & 0x1); - } else if (DctSelHiRngEn) { - *ChannelSelect = ~DctSelHi & 0x1; - } else { - *ChannelSelect = 0; - } - ASSERT (*ChannelSelect < NBPtr[*NodeID].DctCount); - - // Determine base address offset - if (HiRangeSelected) { - if ((DctSelBaseAddr < DramHoleBase) && DramHoleValid && (SysAddr >= (UINT64) 0x100000000)) { - ChannelOffset = (UINT64) DramHoleOffset; - } else { - ChannelOffset = DctSelBaseOffset; - } - } else { - if (DramHoleValid && (SysAddr >= (UINT64) 0x100000000)) { - ChannelOffset = (UINT64) DramHoleOffset; - } else { - ChannelOffset = DramBase; - } - } - - // Remove hoisting offset and normalize to DRAM bus addresses - ChannelAddr = SysAddr - ChannelOffset; - - // Remove node interleaving - if (IntlvEn != 0) { - ChannelAddr = ((ChannelAddr >> (12 + ILog)) << 12) | (ChannelAddr & 0xFFF); - } - - // Remove channel interleave - if (DctSelIntLvEn && !HiRangeSelected && !DctGangEn) { - if ((DctSelIntLvAddr & 1) != 1) { - // A[6] Select or Hash 6 - ChannelAddr = ((ChannelAddr >> 7) << 6) | (ChannelAddr & 0x3F); - } else if (DctSelIntLvAddr == 1) { - // A[12] - ChannelAddr = ((ChannelAddr >> 13) << 12) | (ChannelAddr & 0xFFF); - } else { - // Hash 9 - ChannelAddr = ((ChannelAddr >> 10) << 9) | (ChannelAddr & 0x1FF); - } - } - - // Determine the Chip Select - for (cs = 0; cs < MAX_CS_PER_CHANNEL; ++ cs) { - DctNum = DctGangEn ? 0 : *ChannelSelect; - - // Obtain the CS Base - temp = MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + cs); - CSEn = (BOOLEAN) (temp & 0x1); - CSBase = ((UINT64) temp & NBPtr->CsRegMsk) << 8; - - // Obtain the CS Mask - CSMask = ((UINT64) MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSMask0Reg + (cs >> 1)) & NBPtr->CsRegMsk) << 8; - - // Adjust the Channel Addr for easy comparison - InputAddr = ((ChannelAddr >> 8) & NBPtr->CsRegMsk) << 8; - - if (CSEn && ((InputAddr & ~CSMask) == (CSBase & ~CSMask))) { - CSFound = TRUE; - - *ChipSelect = cs; - - temp = MemFGetPCI (NBPtr, *NodeID, 0, BFOnLineSpareControl); - SwapDone = (BOOLEAN) ((temp >> (1 + 2 * (*ChannelSelect))) & 0x1); - BadDramCs = (UINT8) ((temp >> (4 + 4 * (*ChannelSelect))) & 0x7); - if (SwapDone && (cs == BadDramCs)) { - // Find the spare rank for the channel - for (spare = 0; spare < MAX_CS_PER_CHANNEL; ++spare) { - if ((MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + spare) & 0x2) != 0) { - *ChipSelect = spare; - break; - } - } - } - ASSERT (*ChipSelect < MAX_CS_PER_CHANNEL); - - break; - } - } - } - if (CSFound) { - break; - } - } - - // last ditch sanity check - ASSERT (!CSFound || ((*NodeID < mmPtr->DieCount) && (*ChannelSelect < NBPtr[*NodeID].DctCount) && (*ChipSelect < MAX_CS_PER_CHANNEL))); - if (CSFound) { - return AGESA_SUCCESS; - } else { - return AGESA_BOUNDS_CHK; - } - -} - - -/*-----------------------------------------------------------------------------*/ -/** -* -* This function is the interface to call the PCI register access function -* defined in NB block. -* -* @param[in] *NBPtr - Pointer to the parameter structure MEM_NB_BLOCK -* @param[in] NodeID - Node ID number of the target Northbridge -* @param[in] DctNum - DCT number if applicable, otherwise, put 0 -* @param[in] BitFieldName - targeted bitfield -* -* @retval UINT32 - 32 bits PCI register value -* -*/ -UINT32 -STATIC -MemFGetPCI ( - IN MEM_NB_BLOCK *NBPtr, - IN UINT8 NodeID, - IN UINT8 DctNum, - IN BIT_FIELD_NAME BitFieldName - ) -{ - MEM_NB_BLOCK *LocalNBPtr; - UINT8 Die; - - // Find NBBlock that associates with node NodeID - for (Die = 0; Die < MAX_NODES_SUPPORTED; Die ++) - if (NBPtr[Die].Node == NodeID) - break; - - ASSERT (Die < MAX_NODES_SUPPORTED); - - // Get the northbridge pointer for the targeted node. - LocalNBPtr = &NBPtr[Die]; - LocalNBPtr->FamilySpecificHook[DCTSelectSwitch] (LocalNBPtr, &DctNum); - LocalNBPtr->Dct = DctNum; - // The caller of this function will take care of the ganged/unganged situation. - // So Ganged is set to be false here, and do PCI read on the DCT specified by DctNum. - return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName); -} - -/*-----------------------------------------------------------------------------*/ -/** -* -* This function returns an even parity bit (making the total # of 1's even) -* {0, 1} = number of set bits in argument is {even, odd}. -* -* @param[in] address - the address on which the parity bit will be calculated -* -* @retval UINT8 - parity bit -* -*/ - -UINT8 -STATIC -MemFUnaryXOR ( - IN UINT32 address - ) -{ - UINT8 parity; - UINT8 index; - parity = 0; - for (index = 0; index < 32; ++ index) { - parity = (UINT8) (parity ^ (address & 0x1)); - address = address >> 1; - } - return parity; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.h deleted file mode 100644 index 70ee6beac2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.h +++ /dev/null @@ -1,106 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfidendimm.h - * - * Header file for address to dimm identification translator. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _MFIDENDIMM_H_ -#define _MFIDENDIMM_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemNIdentifyDimmConstructorDr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNIdentifyDimmConstructorDA ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNIdentifyDimmConstructorHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNIdentifyDimmConstructorC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNIdentifyDimmConstructorLN ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -#endif //_MFIDENDIMM_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/Makefile.inc deleted file mode 100644 index d9fca46951..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfintlvrn.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c deleted file mode 100644 index c786270bee..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c +++ /dev/null @@ -1,162 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfrintlv.c - * - * Feature Region interleaving support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/Intlvrgn) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "heapManager.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mfintlvrn.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define _4GB_RJ27 ((UINT32)4 << (30 - 27)) -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * MemFInterleaveRegion: - * - * Applies region interleaving if both DCTs have different size of memory, and - * the channel interleaving region doesn't have UMA covered. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemFInterleaveRegion ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 TOM; - UINT32 TOM2; - UINT32 TOMused; - UINT32 UmaBase; - UINT32 DctSelBase; - S_UINT64 SMsr; - LOCATE_HEAP_PTR LocHeap; - UMA_INFO *UmaInfoPtr; - - MEM_DATA_STRUCT *MemPtr; - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - - MemPtr = NBPtr->MemPtr; - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - - UmaBase = (UINT32) RefPtr->UmaBase >> (27 - 16); - - //TOM scaled from [47:0] to [47:27] - LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.lo += (16 << 20); // Add 16MB to gain back C6 region if C6 is enabled - TOM = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27)); - - //TOM2 scaled from [47:0] to [47:27] - LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - TOM2 = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27)); - - TOMused = (UmaBase >= _4GB_RJ27) ? TOM2 : TOM; - - if (UmaBase != 0) { - //Check if channel interleaving is enabled ? if so, go to next step. - if (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) { - DctSelBase = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr); - //Skip if DctSelBase is equal to 0, because DCT0 has as the same memory size as DCT1. - if (DctSelBase != 0) { - //We need not enable swapped interleaved region when channel interleaving region has covered all of the UMA. - if (DctSelBase < TOMused) { - NBPtr->EnableSwapIntlvRgn (NBPtr, UmaBase, TOMused); - - // Set UMA attribute to interleaved after interleaved region has been swapped - LocHeap.BufferHandle = AMD_UMA_INFO_HANDLE; - if (HeapLocateBuffer (&LocHeap, &(NBPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) { - UmaInfoPtr = (UMA_INFO *) LocHeap.BufferPtr; - UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; - } else { - ASSERT (FALSE); - } - } - } - } - } -} - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.h deleted file mode 100644 index 5ddeeae9d6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfintlvrn.h - * - * Feature region interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFINTLVRN_H_ -#define _MFINTLVRN_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -VOID -MemFInterleaveRegion ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFINTLVRN_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/Makefile.inc deleted file mode 100644 index 436ceb372c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mflvddr3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.c deleted file mode 100644 index bd899818f1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.c +++ /dev/null @@ -1,171 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * lvddr3.c - * - * Voltage change for DDR3 DIMMs. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/LVDDR3) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE -/* features */ -#include "mflvddr3.h" - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function calculate the common lowest voltage supported by all DDR3 - * DIMMs in the system. This function only needs to be called on BSP. - * - * @param[in, out] *NBPtr - Pointer to NB block - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFLvDdr3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CH_DEF_STRUCT *ChannelPtr; - MEM_TECH_BLOCK *TechPtr; - MEM_SHARED_DATA *mmSharedPtr; - UINT8 Dct; - UINT8 Channel; - UINT8 Dimm; - UINT8 *SpdBufferPtr; - UINT8 VDDByte; - UINT8 VoltageMap; - - mmSharedPtr = NBPtr->SharedPtr; - TechPtr = NBPtr->TechPtr; - VoltageMap = 0xFF; - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, Dimm)) { - // SPD byte 6: Module Nominal Voltage, VDD - // 1.5v - bit 0 - // 1.35v - bit 1 - // 1.2v - bit 2 - VDDByte = SpdBufferPtr[MNVVDD]; - IDS_HDT_CONSOLE (MEM_FLOW, "Node%d DCT%d Channel%d Dimm%d VDD Byte: 0x%02x\n", NBPtr->Node, Dct, Channel, Dimm, VDDByte); - - // Reverse the 1.5V operable bit. So its encoding can be consistent - // with that of 1.35V and 1.25V operable bit. - VDDByte ^= 1; - ASSERT (VDDByte != 0); - - if (mmSharedPtr->VoltageMap != 0) { - // Get the common supported voltage map - VoltageMap &= VDDByte; - } else { - // This is the second execution of all the loop as no common voltage is found - if (VDDByte == (1 << VOLT1_5_ENCODED_VAL)) { - // Always exclude 1.5V dimm if no common voltage is found - ChannelPtr->DimmExclude |= (UINT16) 1 << Dimm; - } - } - } - } - if (mmSharedPtr->VoltageMap == 0) { - NBPtr->DCTPtr->Timings.DimmExclude |= ChannelPtr->DimmExclude; - } - } - } - - if (mmSharedPtr->VoltageMap != 0) { - mmSharedPtr->VoltageMap &= VoltageMap; - } - - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.h deleted file mode 100644 index 82b0e8b5ed..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mflvddr3.h - * - * Header file for DDR3 DIMMs voltage configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _MFLVDDR3_H_ -#define _MFLVDDR3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define MNVVDD 6 -#define LOWEST_VOLT_BIT 2 - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemFLvDdr3 ( - IN OUT MEM_NB_BLOCK *NBPtr -); - -#endif //_MFLVDDR3_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/Makefile.inc deleted file mode 100644 index 94d80c7187..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfmemclr.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c deleted file mode 100644 index ab1c9b838f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c +++ /dev/null @@ -1,150 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfmemclr.c - * - * Feature function for memory clear operation - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/Memclr) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "mfmemclr.h" -#include "Ids.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Initiates memory clear operation on one node with Dram on it. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemFMctMemClr_Init ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - AGESA_TESTPOINT (TpProcMemMemClr, &NBPtr->MemPtr->StdHeader); - if (NBPtr->RefPtr->EnableMemClr == TRUE) { - if (NBPtr->MCTPtr->NodeMemSize != 0) { - if (!NBPtr->MemCleared) { - NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, SPECIAL_PCI_ACCESS_TIMEOUT, FALSE); - if (NBPtr->GetBitField (NBPtr, BFDramEnabled) == 1) { - NBPtr->FamilySpecificHook[BeforeMemClr] (NBPtr, NBPtr); - NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0); - NBPtr->SetBitField (NBPtr, BFMemClrInit, 1); - } - } - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Ensures memory clear operation has completed on one node with Dram on it. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemFMctMemClr_Sync ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 MicroSecondToWait; - - MicroSecondToWait = 0; - if (NBPtr->RefPtr->EnableMemClr == TRUE) { - if (NBPtr->MCTPtr->NodeMemSize != 0) { - // Calculate Timeout value: - // Timeout (in microsecond) = Memory Size * 1.5 ns / 8 Byte * 4 (Margin) * 1000 (change millisecond to us) - // NodeMemSize is system address right shifted by 16, so shift it 4 bits to right to convert it to MB. - // 1.5 / 8 * 4 * 1000 = 750 - MicroSecondToWait = (NBPtr->MCTPtr->NodeMemSize >> 4) * 750; - - if (!NBPtr->MemCleared) { - NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, MicroSecondToWait, FALSE); - NBPtr->PollBitField (NBPtr, BFMemCleared, 1, MicroSecondToWait, FALSE); - NBPtr->SetBitField (NBPtr, BFDramBaseAddr, NBPtr->MCTPtr->NodeSysBase >> (27 - 16)); - NBPtr->MemCleared = TRUE; - } - } - } - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/Makefile.inc deleted file mode 100644 index 66e1772502..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfndi.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.c deleted file mode 100644 index e827f17dc9..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.c +++ /dev/null @@ -1,244 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfndi.c - * - * Feature applies Node memory interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/Ndintlv) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "mm.h" -#include "mn.h" -#include "mport.h" -#include "mfndi.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define _4GB_ (0x10000) - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFCheckInterleaveNodes ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * Perform a check to see if node interleaving can be enabled on each node. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Node interleaving can be enabled. - * @return FALSE - Node interleaving cannot be enabled. - */ - -BOOLEAN -MemFCheckInterleaveNodes ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - DIE_STRUCT *MCTPtr; - - ASSERT (NBPtr != NULL); - - MCTPtr = NBPtr->MCTPtr; - - if (MCTPtr->NodeMemSize != 0) { - if (!NBPtr->SharedPtr->NodeIntlv.IsValid) { - NBPtr->SharedPtr->NodeIntlv.NodeMemSize = MCTPtr->NodeMemSize; - NBPtr->SharedPtr->NodeIntlv.Dct0MemSize = MCTPtr->DctData[0].Timings.DctMemSize; - NBPtr->SharedPtr->NodeIntlv.IsValid = TRUE; - } else { - if ((NBPtr->SharedPtr->NodeIntlv.NodeMemSize != MCTPtr->NodeMemSize) || - (NBPtr->SharedPtr->NodeIntlv.Dct0MemSize != MCTPtr->DctData[0].Timings.DctMemSize)) { - return FALSE; - } - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Applies Node memory interleaving for each node. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFInterleaveNodes ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 NodeCnt; - UINT8 BitShift; - UINT32 MemSize; - UINT32 Dct0MemSize; - UINT32 NodeSysBase; - UINT32 NodeSysLimit; - UINT32 HoleBase; - UINT32 HoleSize; - UINT32 HoleOffset; - S_UINT64 SMsr; - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - - ASSERT (NBPtr != NULL); - - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) { - HoleBase = RefPtr->HoleBase; - HoleSize = _4GB_ - HoleBase; - } else { - HoleBase = 0; - HoleSize = 0; - } - - NodeCnt = NBPtr->SharedPtr->NodeIntlv.NodeCnt; - Dct0MemSize = NBPtr->SharedPtr->NodeIntlv.Dct0MemSize; - MemSize = NBPtr->SharedPtr->NodeIntlv.NodeMemSize; - - BitShift = LibAmdBitScanForward (NodeCnt); - Dct0MemSize <<= BitShift; - if (HoleSize != 0) { - RefPtr->GStatus[GsbHWHole] = TRUE; - HoleOffset = HoleSize; - if (Dct0MemSize >= HoleBase) { - Dct0MemSize += HoleSize; - } else { - HoleOffset += Dct0MemSize; - } - } else { - HoleOffset = 0; - } - - MemSize = (MemSize << BitShift) + HoleSize; - - MCTPtr->NodeSysBase = 0; - MCTPtr->NodeSysLimit = MemSize - 1; - RefPtr->SysLimit = MemSize - 1; - - // When node interleaving is enabled with larger than 1012GB memory, - // system memory limit will be lowered to fill in HT reserved region. - // TOP_MEM2 was set in CpuMemTyping and needs to be updated as well. - if (RefPtr->SysLimit >= HT_REGION_BASE_RJ16) { - if (RefPtr->LimitMemoryToBelow1Tb) { - SMsr.hi = HT_REGION_BASE_RJ16 >> (32 - 16); - SMsr.lo = HT_REGION_BASE_RJ16 << 16; - } else { - SMsr.hi = MemSize >> (32 - 16); - SMsr.lo = MemSize << 16; - } - LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", MemSize); - RefPtr->Sub1THoleBase = HT_REGION_BASE_RJ16; - RefPtr->SysLimit = HT_REGION_BASE_RJ16 - 1; - } else { - RefPtr->Sub1THoleBase = RefPtr->SysLimit + 1; - } - - NBPtr->SetBitField (NBPtr, BFDramIntlvSel, NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel); - NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0); - NBPtr->SetBitField (NBPtr, BFDramIntlvEn, NodeCnt - 1); - NBPtr->SetBitField (NBPtr, BFDramLimitAddr, (MemSize - 1) >> (27 - 16)); - - if (HoleSize != 0) { - MCTPtr->Status[SbHWHole] = TRUE; - // DramHoleBase will be set when sync address map to other nodes. - NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset >> (23 - 16)); - NBPtr->SetBitField (NBPtr, BFDramHoleValid, 1); - } - - if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) { - NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, Dct0MemSize >> (27 - 16)); - NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, Dct0MemSize >> (26 - 16)); - } - - NodeSysBase = NodeCnt - 1; - NodeSysLimit = ((MemSize - 1)& 0xFFFFFF00) | NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit; - - NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel++; - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.h deleted file mode 100644 index ec7cc4e5cb..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfndi.h - * - * Feature node interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ -#ifndef _MFNDI_H_ -#define _MFNDI_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFInterleaveNodes ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFNDI_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/Makefile.inc deleted file mode 100644 index e1b5923668..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfodthermal.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c deleted file mode 100644 index 22a06f2515..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +++ /dev/null @@ -1,175 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfodthermal.c - * - * On Dimm thermal management. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Ids.h" -#include "mfodthermal.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*-----------------------------------------------------------------------------*/ -/** - * - * This function does On-Dimm thermal management. - * - * @param[in, out] *NBPtr - Pointer to the MEM_NB_BLOCK. - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFOnDimmThermal ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - UINT8 Dct; - CH_DEF_STRUCT *ChannelPtr; - MEM_DATA_STRUCT *MemPtr; - UINT8 *SpdBufferPtr; - UINT8 ThermalOp; - BOOLEAN ODTSEn; - BOOLEAN ExtendTmp; - - ODTSEn = FALSE; - ExtendTmp = FALSE; - - ASSERT (NBPtr != NULL); - MemPtr = NBPtr->MemPtr; - AGESA_TESTPOINT (TpProcMemOnDimmThermal, &MemPtr->StdHeader); - if (NBPtr->MCTPtr->NodeMemSize != 0) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - // Only go through the DCT if it is not disabled. - if (NBPtr->GetBitField (NBPtr, BFDisDramInterface) == 0) { - ChannelPtr = NBPtr->ChannelPtr; - // If Ganged mode is enabled, need to go through all dram devices on both DCTs. - if (!NBPtr->Ganged || (NBPtr->Dct != 1)) { - if (!(NBPtr->IsSupported[CheckSetSameDctODTsEn]) || (NBPtr->IsSupported[CheckSetSameDctODTsEn] && (NBPtr->Dct != 1))) { - ODTSEn = TRUE; - ExtendTmp = TRUE; - } - } - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { - if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, i)) { - // Check byte 31: thermal and refresh option. - ThermalOp = SpdBufferPtr[THERMAL_OPT]; - // Bit 3: ODTS readout - if (!((ThermalOp >> 3) & 1)) { - ODTSEn = FALSE; - } - // Bit 0: Extended Temperature Range. - if (!(ThermalOp & 1)) { - ExtendTmp = FALSE; - } - } - } - - if (!NBPtr->Ganged || (NBPtr->Dct == 1)) { - // If in ganged mode, need to switch back to DCT0 to set the registers. - if (NBPtr->Ganged || NBPtr->IsSupported[CheckSetSameDctODTsEn]) { - NBPtr->SwitchDCT (NBPtr, 0); - ChannelPtr = NBPtr->ChannelPtr; - } - // If all dram devices on a DCT support ODTS - if (ODTSEn) { - NBPtr->SetBitField (NBPtr, BFODTSEn, 1); - } - ChannelPtr->ExtendTmp = ExtendTmp; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\tDct %d\n", Dct); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tODTSEn = %d\n", ODTSEn); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tExtendTmp = %d\n", ExtendTmp); - } - } - return TRUE; -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h deleted file mode 100644 index ace9cae60d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h +++ /dev/null @@ -1,76 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfodthermal.h - * - * Header file for On-Dimm thermal management. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _MFODTHERMAL_H_ -#define _MFODTHERMAL_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFOnDimmThermal ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif //_MFODTHERMAL_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/Makefile.inc deleted file mode 100644 index 06def969ba..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfspr.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.c deleted file mode 100644 index 55e038cf23..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.c +++ /dev/null @@ -1,170 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfspr.c - * - * Feature enable online spare - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/Olspare) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "mfspr.h" -#include "Ids.h" -#include "amdlib.h" -#include "Filecode.h" -#include "GeneralServices.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * Enable online spare on current node if it is requested. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ - -BOOLEAN -MemFOnlineSpare ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 q; - UINT8 Value8; - BOOLEAN Flag; - BOOLEAN OnlineSprEnabled[MAX_CHANNELS_PER_SOCKET]; - - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - - ASSERT (NBPtr != NULL); - - RefPtr = NBPtr->RefPtr; - Flag = FALSE; - if (RefPtr->EnableOnLineSpareCtl != 0) { - RefPtr->GStatus[GsbEnDIMMSpareNW] = TRUE; - MCTPtr = NBPtr->MCTPtr; - - // Check if online spare can be enabled on current node - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - ASSERT (Dct < sizeof (OnlineSprEnabled)); - NBPtr->SwitchDCT (NBPtr, Dct); - OnlineSprEnabled[Dct] = FALSE; - if ((MCTPtr->GangedMode == 0) || (MCTPtr->Dct == 0)) { - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - // Make sure at least two chip-selects are available - Value8 = LibAmdBitScanReverse (NBPtr->DCTPtr->Timings.CsEnabled); - if (Value8 > LibAmdBitScanForward (NBPtr->DCTPtr->Timings.CsEnabled)) { - OnlineSprEnabled[Dct] = TRUE; - Flag = TRUE; - } else { - PutEventLog (AGESA_ERROR, MEM_ERROR_DIMM_SPARING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - MCTPtr->ErrStatus[EsbSpareDis] = TRUE; - } - } - } - } - - // If we don't have spared rank on any DCT, we don't run the rest part of the code. - if (!Flag) { - return FALSE; - } - - MCTPtr->NodeMemSize = 0; - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (OnlineSprEnabled[Dct]) { - // Only run StitchMemory if we need to set a spare rank. - NBPtr->DCTPtr->Timings.DctMemSize = 0; - for (q = 0; q < MAX_CS_PER_CHANNEL; q++) { - NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0); - } - Flag = NBPtr->StitchMemory (NBPtr); - ASSERT (Flag == TRUE); - } else if ((MCTPtr->GangedMode == 0) && (NBPtr->DCTPtr->Timings.DctMemSize != 0)) { - // Otherwise, need to adjust the memory size on the node. - MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize; - MCTPtr->NodeSysLimit = MCTPtr->NodeMemSize - 1; - } - } - return TRUE; - } else { - return FALSE; - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.h deleted file mode 100644 index bc8daa7b80..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfspr.h - * - * Feature enable Online spare - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _MFSPR_H_ -#define _MFSPR_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFOnlineSpare ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFSPR_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/Makefile.inc deleted file mode 100644 index 90c8566627..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += mfParallelTraining.c -libagesa-y += mfStandardTraining.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfParallelTraining.c deleted file mode 100644 index 271f12b34c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +++ /dev/null @@ -1,289 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfParallelTraining.c - * - * This is the parallel training feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/PARTRN) - * @e \$Revision: 50871 $ @e \$Date: 2011-04-14 15:39:51 -0600 (Thu, 14 Apr 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE - -/*----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the main function to perform parallel training on all nodes. - * This is the routine which will run on the remote AP. - * - * @param[in,out] *EnvPtr - Pointer to the Training Environment Data - * @param[in,out] *StdHeader - Pointer to the Standard Header of the AP - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - MEM_PARAMETER_STRUCT ParameterList; - MEM_NB_BLOCK NB; - MEM_TECH_BLOCK TB; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - UINT8 p; - UINT8 i; - UINT8 Dct; - UINT8 Channel; - UINT8 *BufferPtr; - UINT8 DctCount; - UINT8 ChannelCount; - UINT8 RowCount; - UINT8 ColumnCount; - UINT16 SizeOfNewBuffer; - AP_DATA_TRANSFER ReturnData; - - // - // Initialize Parameters - // - ReturnData.DataPtr = NULL; - ReturnData.DataSizeInDwords = 0; - ReturnData.DataTransferFlags = 0; - - ASSERT (EnvPtr != NULL); - // - // Replace Standard header of a AP - // - LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader)); - - - // - // Allocate buffer for training data - // - BufferPtr = (UINT8 *) (&EnvPtr->DieStruct); - DctCount = EnvPtr->DieStruct.DctCount; - BufferPtr += sizeof (DIE_STRUCT); - ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount; - BufferPtr += DctCount * sizeof (DCT_STRUCT); - RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount; - ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount; - - SizeOfNewBuffer = sizeof (DIE_STRUCT) + - DctCount * ( - sizeof (DCT_STRUCT) + ( - ChannelCount * ( - sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( - RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ) - ) - ) - ); - AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - BufferPtr = AllocHeapParams.BufferPtr; - LibAmdMemCopy ( BufferPtr, - &(EnvPtr->DieStruct), - sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))), - StdHeader - ); - - // - // Fix up pointers - // - MCTPtr = (DIE_STRUCT *) BufferPtr; - BufferPtr += sizeof (DIE_STRUCT); - MCTPtr->DctData = (DCT_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr; - BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT); - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct]; - } - } - NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr; - BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK); - - ReturnData.DataPtr = AllocHeapParams.BufferPtr; - ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4; - ReturnData.DataTransferFlags = 0; - - // - // Allocate Memory for the MEM_DATA_STRUCT we will use - // - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; - - LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader); - - // - // Copy Parameters from environment - // - ParameterList.HoleBase = EnvPtr->HoleBase; - ParameterList.BottomIo = EnvPtr->BottomIo; - ParameterList.UmaSize = EnvPtr->UmaSize; - ParameterList.SysLimit = EnvPtr->SysLimit; - ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations; - ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration; - MemPtr->ParameterListPtr = &ParameterList; - - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p]; - } - - MemPtr->ErrorHandling = EnvPtr->ErrorHandling; - // - // Create Local NBBlock and Tech Block - // - EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr); - NB.RefPtr = &ParameterList; - NB.MemPtr = MemPtr; - i = 0; - while (memTechInstalled[i] != NULL) { - if (memTechInstalled[i] (&TB, &NB)) { - break; - } - i++; - } - NB.TechPtr = &TB; - NB.TechBlockSwitch (&NB); - - // - // Setup CPU Mem Type MSRs on the AP - // - NB.CpuMemTyping (&NB); - - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node); - // - // Call Technology Specific Training routine - // - NB.TrainingFlow (&NB); - // - // Copy training data to ReturnData buffer - // - LibAmdMemCopy ( BufferPtr, - MCTPtr->DctData[0].ChData[0].RcvEnDlys, - ((DctCount * ChannelCount) * ( - (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ) - ), - StdHeader); - - HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - // - // Restore pointers - // - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct; - MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct]; - - MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqs__Dlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqs__Dlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys; - MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys; - MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask; - } - MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData; - } - MCTPtr->DctData = EnvPtr->DieStruct.DctData; - } - - // - // Signal to BSP that training is complete and Send Results - // - ASSERT (ReturnData.DataPtr != NULL); - ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader); - - // - // Clean up and exit. - // - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader); - } else { - MCTPtr = &EnvPtr->DieStruct; - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfStandardTraining.c deleted file mode 100644 index 35681a1d92..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/PARTRN/mfStandardTraining.c +++ /dev/null @@ -1,86 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfStandardTraining.c - * - * This is the standard training routine which performs all training from the BSP - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/PARTRN) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "mfStandardTraining.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the main function to perform memory training on all nodes from - * the BSP only. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - This feature is enabled. - * @return FALSE - This feature is not enabled. - */ -BOOLEAN -MemFStandardTraining ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - ASSERT (NBPtr != NULL); - - NBPtr->TrainingFlow (NBPtr); - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/Makefile.inc deleted file mode 100644 index 506cda03d7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mfs3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c deleted file mode 100644 index e2e5de8e25..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c +++ /dev/null @@ -1,717 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfs3.c - * - * Main S3 resume memory Entrypoint file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/FEAT/S3) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "heapManager.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_S3_MFS3_FILECODE - -extern MEM_NB_SUPPORT memNBInstalled[]; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function is the main memory entry point for the S3 resume sequence - * Requirements: - * - * Run-Time Requirements: - * 1. Complete Hypertransport Bus Configuration - * 4. BSP in Big Real Mode - * 5. Stack available - * - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -AmdMemS3Resume ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - MEM_MAIN_DATA_BLOCK mmData; - S3_MEM_NB_BLOCK *S3NBPtr; - MEM_DATA_STRUCT *MemData; - UINT8 Die; - UINT8 DieCount; - - //--------------------------------------------- - // Creation of NB Block for S3 resume - //--------------------------------------------- - RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader); - if (RetVal == AGESA_FATAL) { - return RetVal; - } - DieCount = mmData.DieCount; - - //--------------------------------------------- - //1. Errata Before resume sequence - //2. S3 Resume sequence - //3. Errata After resume sequence - //--------------------------------------------- - for (Die = 0; Die < DieCount; Die ++) { - if (!S3NBPtr[Die].MemS3Resume (&S3NBPtr[Die], Die)) { - return AGESA_FATAL; - } - S3NBPtr[Die].MemS3RestoreScrub (S3NBPtr[Die].NBPtr, Die); - } - - HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader); - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function deallocates heap space allocated in memory S3 resume. - * - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemS3Deallocate ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - AGESA_STATUS tempRetVal; - UINT8 Tab; - - RetVal = AGESA_SUCCESS; - for (Tab = 0; Tab < NumberOfNbRegTables; Tab++) { - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Tab, 0, 0), StdHeader); - } - - tempRetVal = HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), StdHeader); - if (tempRetVal > RetVal) { - RetVal = tempRetVal; - } - tempRetVal = HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, StdHeader); - if (tempRetVal > RetVal) { - RetVal = tempRetVal; - } - RetVal = HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader); - if (tempRetVal > RetVal) { - RetVal = tempRetVal; - } - RetVal = HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); - if (tempRetVal > RetVal) { - RetVal = tempRetVal; - } - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function is the entrance to get device list for memory registers. - * - * @param[in, out] **DeviceBlockHdrPtr - Pointer to the memory containing the - * device descriptor list - * @param[in] *StdHeader - Config handle for library and services - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemFS3GetDeviceList ( - IN OUT DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT16 BufferSize; - UINT64 BufferOffset; - S3_MEM_NB_BLOCK *S3NBPtr; - MEM_DATA_STRUCT *MemData; - MEM_MAIN_DATA_BLOCK mmData; - UINT8 Die; - UINT8 DieCount; - AGESA_STATUS RetVal; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED]; - BufferSize = 0; - - //--------------------------------------------- - // Creation of NB Block for S3 resume - //--------------------------------------------- - RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader); - if (RetVal == AGESA_FATAL) { - return RetVal; - } - DieCount = mmData.DieCount; - - // Get the mask bit and the register list for node that presents - for (Die = 0; Die < DieCount; Die ++) { - S3NBPtr->MemS3GetConPCIMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]); - S3NBPtr->MemS3GetConMSRMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]); - BufferSize = BufferSize + S3NBPtr->MemS3GetRegLstPtr (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]); - } - - // Base on the size of the device list, apply for a buffer for it. - AllocHeapParams.RequestedBufferSize = BufferSize + sizeof (DEVICE_BLOCK_HEADER); - AllocHeapParams.BufferHandle = AMD_S3_NB_INFO_BUFFER_HANDLE; - AllocHeapParams.Persist = HEAP_S3_RESUME; - AGESA_TESTPOINT (TpIfBeforeAllocateMemoryS3SaveBuffer, StdHeader); - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { - return AGESA_FATAL; - } - AGESA_TESTPOINT (TpIfAfterAllocateMemoryS3SaveBuffer, StdHeader); - - *DeviceBlockHdrPtr = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr; - (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; - - // Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (UINTN) AllocHeapParams.BufferPtr; - for (Die = 0; Die < DieCount; Die ++) { - for (i = PRESELFREF; i <= POSTSELFREF; i ++) { - // Copy PCI device descriptor to the heap if it exists. - if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); - (*DeviceBlockHdrPtr)->NumDevices ++; - BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); - } - // Copy conditional PCI device descriptor to the heap if it exists. - if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); - (*DeviceBlockHdrPtr)->NumDevices ++; - BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); - } - // Copy MSR device descriptor to the heap if it exists. - if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); - (*DeviceBlockHdrPtr)->NumDevices ++; - BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); - } - // Copy conditional MSR device descriptor to the heap if it exists. - if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) (UINTN) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); - (*DeviceBlockHdrPtr)->NumDevices ++; - BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); - } - } - } - - return RetVal; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initialize the northbridge block and apply for heap space - * before any function call is made to memory component during S3 resume. - * - * @param[in] *StdHeader - Config handle for library and services - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemS3ResumeInitNB ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - MEM_MAIN_DATA_BLOCK mmData; - S3_MEM_NB_BLOCK *S3NBPtr; - MEM_DATA_STRUCT *MemData; - UINT8 Die; - UINT8 DieCount; - UINT8 SpecialCaseHeapSize; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - S3_SPECIAL_CASE_HEAP_HEADER SpecialHeapHeader[MAX_NODES_SUPPORTED]; - - SpecialCaseHeapSize = 0; - - //--------------------------------------------- - // Creation of NB Block for S3 resume - //--------------------------------------------- - RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader); - if (RetVal == AGESA_FATAL) { - return RetVal; - } - DieCount = mmData.DieCount; - - //-------------------------------------------------- - // Apply for heap space for special case registers - //-------------------------------------------------- - for (Die = 0; Die < DieCount; Die ++) { - // Construct the header for the special case heap. - SpecialHeapHeader[Die].Node = S3NBPtr[Die].NBPtr->Node; - SpecialHeapHeader[Die].Offset = SpecialCaseHeapSize + (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER))); - SpecialCaseHeapSize = SpecialCaseHeapSize + S3NBPtr->MemS3SpecialCaseHeapSize; - } - AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER))) + SpecialCaseHeapSize; - AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS, S3NBPtr[Die].NBPtr->Node, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, S3NBPtr[Die].NBPtr->MCTPtr); - ASSERT(FALSE); // Could not allocate heap space for "S3_SPECIAL_CASE_HEAP_HEADER" - return AGESA_FATAL; - } - LibAmdMemCopy ((VOID *) AllocHeapParams.BufferPtr, (VOID *) SpecialHeapHeader, (sizeof (S3_SPECIAL_CASE_HEAP_HEADER) * DieCount), StdHeader); - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the PCI device register list according to the register - * list ID. - * - * @param[in] *Device - pointer to the PCI_DEVICE_DESCRIPTOR - * @param[out] **RegisterHdr - pointer to the address of the register list - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemFS3GetPciDeviceRegisterList ( - IN PCI_DEVICE_DESCRIPTOR *Device, - OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; - LOCATE_HEAP_PTR LocHeap; - AGESA_BUFFER_PARAMS LocBufferParams; - LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; - - LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - - AGESA_TESTPOINT (TpIfBeforeLocateS3PciBuffer, StdHeader); - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr - return AGESA_FATAL; - } - AGESA_TESTPOINT (TpIfAfterLocateS3PciBuffer, StdHeader); - - // NB block has already been constructed by main block. - // No need to construct it here. - RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); - *RegisterHdr = (PCI_REGISTER_BLOCK_HEADER *)RegisterHeader; - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the conditional PCI device register list according - * to the register list ID. - * - * @param[in] *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR - * @param[out] **RegisterHdr - pointer to the address of the register list - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemFS3GetCPciDeviceRegisterList ( - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; - LOCATE_HEAP_PTR LocHeap; - AGESA_BUFFER_PARAMS LocBufferParams; - - LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; - LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - - AGESA_TESTPOINT (TpIfBeforeLocateS3CPciBuffer, StdHeader); - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr - return AGESA_FATAL; - } - AGESA_TESTPOINT (TpIfAfterLocateS3CPciBuffer, StdHeader); - - // NB block has already been constructed by main block. - // No need to construct it here. - RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); - *RegisterHdr = (CPCI_REGISTER_BLOCK_HEADER *)RegisterHeader; - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the MSR device register list according to the register - * list ID. - * - * @param[in] *Device - pointer to the MSR_DEVICE_DESCRIPTOR - * @param[out] **RegisterHdr - pointer to the address of the register list - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemFS3GetMsrDeviceRegisterList ( - IN MSR_DEVICE_DESCRIPTOR *Device, - OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; - LOCATE_HEAP_PTR LocHeap; - AGESA_BUFFER_PARAMS LocBufferParams; - - LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; - LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - - AGESA_TESTPOINT (TpIfBeforeLocateS3MsrBuffer, StdHeader); - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr - return AGESA_FATAL; - } - AGESA_TESTPOINT (TpIfAfterLocateS3MsrBuffer, StdHeader); - - // NB block has already been constructed by main block. - // No need to construct it here. - RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); - *RegisterHdr = (MSR_REGISTER_BLOCK_HEADER *)RegisterHeader; - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the conditional MSR device register list according - * to the register list ID. - * - * @param[in] *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR - * @param[out] **RegisterHdr - pointer to the address of the register list - * @param[in] *StdHeader - Config handle for library and services - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemFS3GetCMsrDeviceRegisterList ( - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AGESA_STATUS RetVal; - S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; - LOCATE_HEAP_PTR LocHeap; - AGESA_BUFFER_PARAMS LocBufferParams; - - LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; - LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - - - AGESA_TESTPOINT (TpIfBeforeLocateS3CMsrBuffer, StdHeader); - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr - return AGESA_FATAL; - } - AGESA_TESTPOINT (TpIfAfterLocateS3CMsrBuffer, StdHeader); - - // NB block has already been constructed by main block. - // No need to construct it here. - RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader); - *RegisterHdr = (CMSR_REGISTER_BLOCK_HEADER *)RegisterHeader; - return RetVal; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initialize needed data structures for S3 resume. - * - * @param[in, out] **S3NBPtr - Pointer to the pointer of northbridge block. - * @param[in, out] *MemPtr - Pointer to MEM_DATA_STRUCT. - * @param[in, out] *mmData - Pointer to MEM_MAIN_DATA_BLOCK. - * @param[in] *StdHeader - Config handle for library and services. - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemS3InitNB ( - IN OUT S3_MEM_NB_BLOCK **S3NBPtr, - IN OUT MEM_DATA_STRUCT **MemPtr, - IN OUT MEM_MAIN_DATA_BLOCK *mmData, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - AGESA_STATUS RetVal; - LOCATE_HEAP_PTR LocHeap; - MEM_NB_BLOCK *NBPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT8 Die; - UINT8 DieCount; - BOOLEAN SkipScan; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - SkipScan = FALSE; - LocHeap.BufferHandle = AMD_MEM_DATA_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - // NB block has already been constructed by main block. - // No need to construct it here. - *MemPtr = (MEM_DATA_STRUCT *)LocHeap.BufferPtr; - SkipScan = TRUE; - } else { - AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); - AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { - ASSERT(FALSE); // Allocate failed for MEM_DATA_STRUCT - return AGESA_FATAL; - } - *MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr; - LibAmdMemCopy (&(*MemPtr)->StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &(*MemPtr)->StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &(*MemPtr)->TscRate, &(*MemPtr)->StdHeader); - - } - mmData->MemPtr = *MemPtr; - - if (!SkipScan) { - RetVal = MemSocketScan (mmData); - if (RetVal == AGESA_FATAL) { - return RetVal; - } - } else { - // We already have initialize data block, no need to do it again. - mmData->DieCount = mmData->MemPtr->DieCount; - } - DieCount = mmData->DieCount; - - //--------------------------------------------- - // Creation of NB Block for S3 resume - //--------------------------------------------- - // Search for AMD_MEM_AUTO_HANDLE on the heap first. - // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap. - LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - // NB block has already been constructed by main block. - // No need to construct it here. - *S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_MEM_NB_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { - ASSERT(FALSE); // Could not allocate space for "S3_MEM_NB_BLOCK" - return AGESA_FATAL; - } - *S3NBPtr = (S3_MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; - - LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - // NB block has already been constructed by main block. - // No need to construct it here. - NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr; - } else { - AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) { - ASSERT(FALSE); // Allocate failed for "MEM_NB_BLOCK" - return AGESA_FATAL; - } - NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; - } - // Construct each die. - for (Die = 0; Die < DieCount; Die ++) { - i = 0; - ((*S3NBPtr)[Die]).NBPtr = &NBPtr[Die]; - while (memNBInstalled[i].MemS3ResumeConstructNBBlock != 0) { - if (memNBInstalled[i].MemS3ResumeConstructNBBlock ((VOID *)&((*S3NBPtr)[Die]), *MemPtr, Die)) { - break; - } - i++; - }; - if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) { - ASSERT(FALSE); // S3 resume NB constructor not found - return AGESA_FATAL; - } - } - } - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Waits specified number of 10ns cycles - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] Count - Number of 10ns cycles to wait - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemFS3Wait10ns ( - IN UINT32 Count, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT64 TargetTsc; - UINT64 CurrentTsc; - - ASSERT (Count <= 1000000); - - LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); - TargetTsc = CurrentTsc + ((Count * MemPtr->TscRate + 99) / 100); - do { - LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); - } while (CurrentTsc < TargetTsc); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/Makefile.inc deleted file mode 100644 index 27dcfe7f00..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mftds.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/mftds.c deleted file mode 100644 index f22482885c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/mftds.c +++ /dev/null @@ -1,398 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mftds.c - * - * Northbridge table drive support file for DR - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/TABLE) - * @e \$Revision: 51024 $ @e \$Date: 2011-04-18 06:02:44 -0600 (Mon, 18 Apr 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mftds.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_FEAT_TABLE_MFTDS_FILECODE -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define MAX_BYTELANES_PER_CHANNEL (8 + 1) ///< Max Bytelanes per channel - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -VOID -SetTableValues ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_TABLE_ALIAS MTPtr - ); - -VOID -SetTableValuesLoop ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_TABLE_ALIAS *MTPtr, - IN UINT8 time - ); - -/*----------------------------------------------------------------------------- - * - * This function initializes bit field translation table - * - * @param[in,out] *NBPtr - Pointer to the MEM_TABLE_ALIAS structure - * @param[in] time - Indicate the timing for the register which is written. - * - * @return None - * ---------------------------------------------------------------------------- - */ -VOID -MemFInitTableDrive ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 time - ) -{ - MEM_TABLE_ALIAS *MTPtr; - MEM_TABLE_ALIAS *IdsMTPtr; - - ASSERT (NBPtr != NULL); - IdsMTPtr = NULL; - IDS_HDT_CONSOLE (MEM_FLOW, "MemFInitTableDrive [%X] Start\n", time); - MTPtr = (MEM_TABLE_ALIAS *) NBPtr->RefPtr->TableBasedAlterations; - - IDS_SKIP_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader)) { - IDS_OPTION_HOOK (IDS_INIT_DRAM_TABLE, NBPtr, &(NBPtr->MemPtr->StdHeader)); - IDS_OPTION_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader)); - } - - SetTableValuesLoop (NBPtr, MTPtr, time); - SetTableValuesLoop (NBPtr, IdsMTPtr, time); - - IDS_OPTION_HOOK (IDS_MT_BASE + time, NBPtr, &(NBPtr->MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "MemFInitTableDrive End\n"); -} - -/*----------------------------------------------------------------------------- - * - * This function initializes bit field translation table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MTPtr - Pointer to the MEM_TABLE_ALIAS structure - * @param[in] time - Indicate the timing for the register which is written. - * - * @return None - * ---------------------------------------------------------------------------- - */ -VOID -SetTableValuesLoop ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_TABLE_ALIAS *MTPtr, - IN UINT8 time - ) -{ - UINT8 i; - UINT8 CurDct; - - if (MTPtr != NULL) { - CurDct = NBPtr->Dct; - for (i = 0; MTPtr[i].time != MTEnd; i++) { - if ((MTPtr[i].attr != MTAuto) && (MTPtr[i].time == time)) { - SetTableValues (NBPtr, MTPtr[i]); - } - } - NBPtr->SwitchDCT (NBPtr, CurDct); - } -} - -/*----------------------------------------------------------------------------- - * - * Engine for setting Table Value. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] MTPtr - Pointer to the MEM_TABLE_ALIAS structure - * - * @return None - * ---------------------------------------------------------------------------- - */ -VOID -SetTableValues ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_TABLE_ALIAS MTPtr - ) -{ - UINT8 AccessType; - UINT16 ByteLane; - UINT8 Dct; - UINT8 i; - UINT8 j; - UINT32 TempVal[36]; - UINT32 Temp2Val[72]; - UINT8 *DqsSavePtr; - UINT8 DqsOffset; - BOOLEAN SaveDqs; - - AccessType = 0; - DqsSavePtr = NULL; - SaveDqs = TRUE; - - ASSERT (MTPtr.time <= MTValidTimePointLimit); - ASSERT (MTPtr.attr <= MTOr); - ASSERT (MTPtr.node <= MTNodes); - ASSERT (MTPtr.dct <= MTDcts); - ASSERT (MTPtr.dimm <= MTDIMMs); - ASSERT (MTPtr.data.s.bytelane <= MTBLs); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - if ((MTPtr.dct == MTDcts) || (MTPtr.dct == Dct)) { - NBPtr->SwitchDCT (NBPtr, Dct); - switch (MTPtr.bfindex) { - case BFRcvEnDly: - AccessType = AccessRcvEnDly; - DqsSavePtr = NULL; - break; - case BFWrDatDly: - AccessType = AccessWrDatDly; - DqsSavePtr = NBPtr->ChannelPtr->WrDatDlys; - break; - case BFRdDqsDly: - AccessType = AccessRdDqsDly; - DqsSavePtr = NBPtr->ChannelPtr->RdDqsDlys; - break; - case BFWrDqsDly: - AccessType = AccessWrDqsDly; - DqsSavePtr = NBPtr->ChannelPtr->WrDqsDlys; - break; - case BFRdDqs__Dly: - AccessType = AccessRdDqs__Dly; - DqsSavePtr = NBPtr->ChannelPtr->RdDqs__Dlys; - break; - case BFPhRecDly: - AccessType = AccessPhRecDly; - SaveDqs = FALSE; - break; - default: - AccessType = 0xFF; - break; - } - if (AccessType == 0xFF) { - if (MTPtr.attr == MTOverride) { - NBPtr->SetBitField (NBPtr, MTPtr.bfindex, MTPtr.data.s.value); - } - if (MTPtr.attr == MTSubtract) { - NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) - MTPtr.data.s.value); - } - if (MTPtr.attr == MTAdd) { - NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) + MTPtr.data.s.value); - } - if (MTPtr.attr == MTAnd) { - NBPtr->SetBitField (NBPtr, MTPtr.bfindex, (NBPtr->GetBitField (NBPtr, MTPtr.bfindex) & MTPtr.data.s.value)); - } - if (MTPtr.attr == MTOr) { - NBPtr->SetBitField (NBPtr, MTPtr.bfindex, (NBPtr->GetBitField (NBPtr, MTPtr.bfindex) | MTPtr.data.s.value)); - } - } else { - // Store the DQS data first - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if (AccessType == AccessRdDqs__Dly) { - for (j = 0; j < MAX_NUMBER_LANES; j++) { - Temp2Val[i * MAX_NUMBER_LANES + j] = NBPtr->GetTrainDly (NBPtr, AccessType, DIMM_NBBL_ACCESS (i, j)); - } - } else { - for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { - TempVal[i * MAX_BYTELANES_PER_CHANNEL + j] = NBPtr->GetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j)); - } - } - } - // - // Single Value with Bytleane mask option - // Indicated by the vtype flag - // - if (MTPtr.vtype == VT_MSK_VALUE) { - // set the value which defined in Memory table. - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - ByteLane = MTPtr.data.s.bytelane; - if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) { - if (AccessType == AccessRdDqs__Dly) { - for (j = 0; j < MAX_NUMBER_LANES; j++) { - DqsOffset = (i * MAX_NUMBER_LANES + j); - if ((ByteLane & (UINT16)1) != 0) { - if (MTPtr.attr == MTOverride) { - Temp2Val[DqsOffset] = (UINT16)MTPtr.data.s.value; - } - if (MTPtr.attr == MTSubtract) { - Temp2Val[DqsOffset] -= (UINT16)MTPtr.data.s.value; - } - if (MTPtr.attr == MTAdd) { - Temp2Val[DqsOffset] += (UINT16)MTPtr.data.s.value; - } - NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_NBBL_ACCESS (i, j), (UINT16)Temp2Val[DqsOffset]); - if (SaveDqs) { - if (DqsSavePtr == NULL) { - NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset]; - } else { - DqsSavePtr[DqsOffset] = (UINT8)Temp2Val[DqsOffset]; - } - } - } - ByteLane = ByteLane >> (UINT16)1; - } - } else { - for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { - DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j); - if ((ByteLane & (UINT16)1) != 0) { - if (MTPtr.attr == MTOverride) { - TempVal[DqsOffset] = (UINT16)MTPtr.data.s.value; - } - if (MTPtr.attr == MTSubtract) { - TempVal[DqsOffset] -= (UINT16)MTPtr.data.s.value; - } - if (MTPtr.attr == MTAdd) { - TempVal[DqsOffset] += (UINT16)MTPtr.data.s.value; - } - NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]); - if (SaveDqs) { - if (DqsSavePtr == NULL) { - NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset]; - } else { - DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset]; - } - } - } - ByteLane = ByteLane >> (UINT16)1; - } - } - } - } - } else { - // Multiple values specified in a byte array - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) { - if (AccessType == AccessRdDqs__Dly) { - for (j = 0; j < MAX_NUMBER_LANES; j++) { - DqsOffset = (i * MAX_NUMBER_LANES + j); - if (MTPtr.attr == MTOverride) { - Temp2Val[DqsOffset] = MTPtr.data.bytelanevalue[j]; - } - if (MTPtr.attr == MTSubtract) { - Temp2Val[DqsOffset] -= MTPtr.data.bytelanevalue[j]; - } - if (MTPtr.attr == MTAdd) { - Temp2Val[DqsOffset] += MTPtr.data.bytelanevalue[j]; - } - NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_NBBL_ACCESS (i, j), (UINT16)Temp2Val[DqsOffset]); - if (SaveDqs) { - if (DqsSavePtr == NULL) { - NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)Temp2Val[DqsOffset]; - } else { - DqsSavePtr[DqsOffset] = (UINT8)Temp2Val[DqsOffset]; - } - } - } - } else { - for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { - DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j); - if (MTPtr.attr == MTOverride) { - TempVal[DqsOffset] = MTPtr.data.bytelanevalue[j]; - } - if (MTPtr.attr == MTSubtract) { - TempVal[DqsOffset] -= MTPtr.data.bytelanevalue[j]; - } - if (MTPtr.attr == MTAdd) { - TempVal[DqsOffset] += MTPtr.data.bytelanevalue[j]; - } - NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]); - if (SaveDqs) { - if (DqsSavePtr == NULL) { - NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset]; - } else { - DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset]; - } - } - } - } - } - } - } - // set the DQS value to left DIMMs. - i = MTPtr.dimm; - while ((i != MTDIMMs) && ((++i) < MAX_DIMMS_PER_CHANNEL)) { - if (AccessType == AccessRdDqs__Dly) { - for (j = 0; j < MAX_NUMBER_LANES; j++) { - NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_NBBL_ACCESS (i, j), (UINT16)Temp2Val[i * MAX_BYTELANES_PER_CHANNEL + j]); - } - } else { - for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) { - NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[i * MAX_BYTELANES_PER_CHANNEL + j]); - } - } - } - } - } - } -} - - - - - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/C32/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/C32/Makefile.inc deleted file mode 100644 index 66045b1c3b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/C32/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mmflowC32.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/C32/mmflowC32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/C32/mmflowC32.c deleted file mode 100644 index 9c295ed1ed..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/C32/mmflowC32.c +++ /dev/null @@ -1,380 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmflowC32.c - * - * Main Memory initialization sequence for C32 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main/C32) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnc32.h" -#include "mt.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "GeneralServices.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE -/* features */ -#include "mftds.h" - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -AGESA_STATUS -MemMFlowC32 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function defines the memory initialization flow for - * systems that only support C32 processors. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemMFlowC32 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 NodeCnt; - MEM_NB_BLOCK *NBPtr; - MEM_TECH_BLOCK *TechPtr; - MEM_DATA_STRUCT *MemPtr; - - NBPtr = MemMainPtr->NBPtr; - TechPtr = MemMainPtr->TechPtr; - NodeCnt = MemMainPtr->DieCount; - MemPtr = MemMainPtr->MemPtr; - - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { - MemPtr->IsFlowControlSupported = FALSE; - return AGESA_FATAL; - } else { - MemPtr->IsFlowControlSupported = TRUE; - } - - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTBeforeInitializeMCT); - } - - //---------------------------------------------------------------- - // Initialize MCT - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // Low voltage DDR3 - //---------------------------------------------------------------- - // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. - AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.LvDDR3 (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Initialize DRAM and DCTs, and Create Memory Map - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - // Initialize Memory Controller and Dram - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); - if (!NBPtr[Node].InitMCT (&NBPtr[Node])) { - return AGESA_FATAL; //fatalexit - } - - // Create memory map - AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------- - // If there is no dimm on the system, do fatal exit - //---------------------------------------------------- - if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { - PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); - ASSERT (FALSE); - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Synchronize DCTs - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // CpuMemTyping - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Before Training Table values - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn); - } - - //---------------------------------------------------------------- - // Memory Context Restore - //---------------------------------------------------------------- - if (!MemFeatMain.MemRestore (MemMainPtr)) { - // Do DQS training only if memory context restore fails - - //---------------------------------------------------------------- - // Training - //---------------------------------------------------------------- - MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; - AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); - IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { - if (!MemFeatMain.Training (MemMainPtr)) { - return AGESA_FATAL; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); - } - - //---------------------------------------------------------------- - // Disable chipselects that fail training - //---------------------------------------------------------------- - MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; - MemFeatMain.ExcludeDIMM (MemMainPtr); - MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; - - //---------------------------------------------------------------- - // OtherTiming - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // After Training Table values - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTAfterTrn); - } - - //---------------------------------------------------------------- - // SetDqsEccTimings - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // Online Spare - //---------------------------------------------------------------- - if (!MemFeatMain.OnlineSpare (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Interleave banks - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) { - if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - } - - //---------------------------------------------------------------- - // Interleave Nodes - //---------------------------------------------------------------- - if (!MemFeatMain.InterleaveNodes (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Interleave channels - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) { - if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - } - - //---------------------------------------------------------------- - // After Programming Interleave registers - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave); - } - - //---------------------------------------------------------------- - // UMA Allocation & UMAMemTyping - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.UmaAllocation (MemMainPtr)) { - return AGESA_FATAL; - } - - // ECC - //---------------------------------------------------------------- - if (!MemFeatMain.InitEcc (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Memory Clear - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.MemClr (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // OnDimm Thermal - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) { - if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - } - - //---------------------------------------------------------------- - // Finalize MCT - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // After Finalize MCT - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT); - } - - //---------------------------------------------------------------- - // Memory Context Save - //---------------------------------------------------------------- - MemFeatMain.MemSave (MemMainPtr); - - //---------------------------------------------------------------- - // Memory DMI support - //---------------------------------------------------------------- - if (!MemFeatMain.MemDmi (MemMainPtr)) { - return AGESA_CRITICAL; - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/HY/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/HY/Makefile.inc deleted file mode 100644 index 52307e2c07..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/HY/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += mmflowhy.c -libagesa-y += mmflowhy.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/HY/mmflowhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/HY/mmflowhy.c deleted file mode 100644 index 915000c241..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/HY/mmflowhy.c +++ /dev/null @@ -1,380 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmflowhy.c - * - * Main Memory initialization sequence for HY - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnhy.h" -#include "mt.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "GeneralServices.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE -/* features */ -#include "mftds.h" - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -AGESA_STATUS -MemMFlowHy ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function defines the memory initialization flow for - * systems that only support HY processors. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemMFlowHy ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 NodeCnt; - MEM_NB_BLOCK *NBPtr; - MEM_TECH_BLOCK *TechPtr; - MEM_DATA_STRUCT *MemPtr; - - NBPtr = MemMainPtr->NBPtr; - TechPtr = MemMainPtr->TechPtr; - NodeCnt = MemMainPtr->DieCount; - MemPtr = MemMainPtr->MemPtr; - - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { - MemPtr->IsFlowControlSupported = FALSE; - return AGESA_FATAL; - } else { - MemPtr->IsFlowControlSupported = TRUE; - } - - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTBeforeInitializeMCT); - } - - //---------------------------------------------------------------- - // Initialize MCT - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // Low voltage DDR3 - //---------------------------------------------------------------- - // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. - AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.LvDDR3 (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Initialize DRAM and DCTs, and Create Memory Map - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - // Initialize Memory Controller and Dram - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); - if (!NBPtr[Node].InitMCT (&NBPtr[Node])) { - return AGESA_FATAL; //fatalexit - } - - // Create memory map - AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------- - // If there is no dimm on the system, do fatal exit - //---------------------------------------------------- - if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { - PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); - ASSERT (FALSE); - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Synchronize DCTs - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // CpuMemTyping - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Before Training Table values - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn); - } - - //---------------------------------------------------------------- - // Memory Context Restore - //---------------------------------------------------------------- - if (!MemFeatMain.MemRestore (MemMainPtr)) { - // Do DQS training only if memory context restore fails - - //---------------------------------------------------------------- - // Training - //---------------------------------------------------------------- - MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; - AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); - IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { - if (!MemFeatMain.Training (MemMainPtr)) { - return AGESA_FATAL; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); - } - - //---------------------------------------------------------------- - // Disable chipselects that fail training - //---------------------------------------------------------------- - MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; - MemFeatMain.ExcludeDIMM (MemMainPtr); - MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; - - //---------------------------------------------------------------- - // OtherTiming - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // After Training Table values - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTAfterTrn); - } - - //---------------------------------------------------------------- - // SetDqsEccTimings - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // Online Spare - //---------------------------------------------------------------- - if (!MemFeatMain.OnlineSpare (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Interleave banks - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) { - if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - } - - //---------------------------------------------------------------- - // Interleave Nodes - //---------------------------------------------------------------- - if (!MemFeatMain.InterleaveNodes (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Interleave channels - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) { - if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - } - - //---------------------------------------------------------------- - // After Programming Interleave registers - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave); - } - - //---------------------------------------------------------------- - // UMA Allocation & UMAMemTyping - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.UmaAllocation (MemMainPtr)) { - return AGESA_FATAL; - } - - // ECC - //---------------------------------------------------------------- - if (!MemFeatMain.InitEcc (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Memory Clear - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.MemClr (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // OnDimm Thermal - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) { - if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - } - - //---------------------------------------------------------------- - // Finalize MCT - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // After Finalize MCT - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT); - } - - //---------------------------------------------------------------- - // Memory Context Save - //---------------------------------------------------------------- - MemFeatMain.MemSave (MemMainPtr); - - //---------------------------------------------------------------- - // Memory DMI support - //---------------------------------------------------------------- - if (!MemFeatMain.MemDmi (MemMainPtr)) { - return AGESA_CRITICAL; - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/Makefile.inc deleted file mode 100644 index 4c61d95629..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -libagesa-y += mdef.c -libagesa-y += merrhdl.c -libagesa-y += minit.c -libagesa-y += mm.c -libagesa-y += mmConditionalPso.c -libagesa-y += mmEcc.c -libagesa-y += mmExcludeDimm.c -libagesa-y += mmLvDdr3.c -libagesa-y += mmMemClr.c -libagesa-y += mmMemRestore.c -libagesa-y += mmNodeInterleave.c -libagesa-y += mmOnlineSpare.c -libagesa-y += mmParallelTraining.c -libagesa-y += mmStandardTraining.c -libagesa-y += mmUmaAlloc.c -libagesa-y += mmflow.c -libagesa-y += mu.c -libagesa-y += muc.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/OR/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/OR/Makefile.inc deleted file mode 100644 index 7a0b6db612..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/OR/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mmflowor.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/OR/mmflowor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/OR/mmflowor.c deleted file mode 100644 index 090efa9898..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/OR/mmflowor.c +++ /dev/null @@ -1,423 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmflowor.c - * - * Main Memory initialization sequence for OR - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main/OR) - * @e \$Revision: 54925 $ @e \$Date: 2011-06-14 09:05:43 -0600 (Tue, 14 Jun 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnor.h" -#include "mt.h" -#include "mmLvDdr3.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "GeneralServices.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE -/* features */ -#include "mftds.h" - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -AGESA_STATUS -MemMFlowOr ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function defines the memory initialization flow for - * systems that only support OR processors. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemMFlowOr ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 NodeCnt; - MEM_NB_BLOCK *NBPtr; - MEM_TECH_BLOCK *TechPtr; - MEM_DATA_STRUCT *MemPtr; - ID_INFO CallOutIdInfo; - - NBPtr = MemMainPtr->NBPtr; - TechPtr = MemMainPtr->TechPtr; - NodeCnt = MemMainPtr->DieCount; - MemPtr = MemMainPtr->MemPtr; - - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedOr (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { - MemPtr->IsFlowControlSupported = FALSE; - return AGESA_FATAL; - } else { - MemPtr->IsFlowControlSupported = TRUE; - } - - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTBeforeInitializeMCT); - } - - //---------------------------------------------------------------- - // Initialize MCT - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // Low voltage DDR3 - //---------------------------------------------------------------- - // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms. - AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.LvDDR3 (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Initialize DRAM and DCTs - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - // Initialize Memory Controller and Dram - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); - if (!NBPtr[Node].InitMCT (&NBPtr[Node])) { - return AGESA_FATAL; //fatalexit - } - - MemFInitTableDrive (NBPtr, MTBeforeDInit); - } - - //------------------------------------------------ - // Finalize target frequency - //------------------------------------------------ - if (!MemMLvDdr3PerformanceEnhFinalize (MemMainPtr)) { - return AGESA_FATAL; - } - - //------------------------------------------------ - // Callout before Dram Init - //------------------------------------------------ - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node ++) { - CallOutIdInfo.IdField.SocketId = NBPtr[Node].MCTPtr->SocketId; - CallOutIdInfo.IdField.ModuleId = NBPtr[Node].MCTPtr->DieId; - IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS on Socket %d Module %d...\n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId); - AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, MemMainPtr->MemPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr[Node].RefPtr->DDR3Voltage == VOLT1_5) ? 5 : - (NBPtr[Node].RefPtr->DDR3Voltage == VOLT1_35) ? 35 : - (NBPtr[Node].RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999); - } - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); - - //------------------------------------------------- - // Do dram init and create memory map - //------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, &NBPtr[Node], &(MemMainPtr->MemPtr->StdHeader)); - NBPtr[Node].StartupDCT (&NBPtr[Node]); - - // Create memory map - AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------- - // If there is no dimm on the system, do fatal exit - //---------------------------------------------------- - if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { - PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Synchronize DCTs - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // CpuMemTyping - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); - if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Before Training Table values - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn); - } - - //---------------------------------------------------------------- - // Memory Context Restore - //---------------------------------------------------------------- - if (!MemFeatMain.MemRestore (MemMainPtr)) { - // Do DQS training only if memory context restore fails - - //---------------------------------------------------------------- - // Training - //---------------------------------------------------------------- - MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; - AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); - IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { - if (!MemFeatMain.Training (MemMainPtr)) { - return AGESA_FATAL; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); - } - - //---------------------------------------------------------------- - // Disable chipselects that fail training - //---------------------------------------------------------------- - MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; - MemFeatMain.ExcludeDIMM (MemMainPtr); - MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; - - //---------------------------------------------------------------- - // OtherTiming - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd Non-SPD Timings.\n"); - - //---------------------------------------------------------------- - // After Training Table values - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTAfterTrn); - } - - //---------------------------------------------------------------- - // Online Spare - //---------------------------------------------------------------- - if (!MemFeatMain.OnlineSpare (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Interleave banks - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) { - if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - } - - //---------------------------------------------------------------- - // Interleave Nodes - //---------------------------------------------------------------- - if (!MemFeatMain.InterleaveNodes (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Interleave channels - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) { - if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - } - - //---------------------------------------------------------------- - // After Programming Interleave registers - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave); - } - - // ECC - //---------------------------------------------------------------- - if (!MemFeatMain.InitEcc (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Memory Clear - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.MemClr (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // C6 Storage Allocation - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - NBPtr[Node].AllocateC6Storage (&NBPtr[Node]); - } - - //---------------------------------------------------------------- - // UMA Allocation & UMAMemTyping - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); - if (!MemFeatMain.UmaAllocation (MemMainPtr)) { - return AGESA_FATAL; - } - - //---------------------------------------------------------------- - // Interleave region - //---------------------------------------------------------------- - NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]); - - //---------------------------------------------------------------- - // OnDimm Thermal - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) { - if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) { - return AGESA_FATAL; - } - } - } - - //---------------------------------------------------------------- - // Finalize MCT - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) { - return AGESA_FATAL; - } - } - - //---------------------------------------------------------------- - // After Finalize MCT - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node++) { - MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT); - } - - //---------------------------------------------------------------- - // Memory Context Save - //---------------------------------------------------------------- - MemFeatMain.MemSave (MemMainPtr); - - //---------------------------------------------------------------- - // Memory DMI support - //---------------------------------------------------------------- - if (!MemFeatMain.MemDmi (MemMainPtr)) { - return AGESA_CRITICAL; - } - - //---------------------------------------------------------------- - // Switch back to DCT 0 before sending control back - //---------------------------------------------------------------- - for (Node = 0; Node < NodeCnt; Node ++) { - NBPtr[Node].SwitchDCT (&NBPtr[Node], 0); - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mdef.c deleted file mode 100644 index aa825e5230..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mdef.c +++ /dev/null @@ -1,147 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mdef.c - * - * Memory Controller header file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "Filecode.h" -#include "AdvancedApi.h" -#include "mm.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MDEF_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -MemMFlowDef ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This is the default return function - */ - -VOID -memDefRet ( VOID ) -{ -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the default return function that returns TRUE - * - */ -BOOLEAN -memDefTrue ( VOID ) -{ - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is used in place of an un-supported function that returns FALSE. - * - */ -BOOLEAN -memDefFalse ( VOID ) -{ - return FALSE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This is the default return function for flow control - */ -AGESA_STATUS -MemMFlowDef ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - MemMainPtr->MemPtr->IsFlowControlSupported = FALSE; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is used in place of an un-supported function that returns AGESA_SUCCESS. - * - */ -AGESA_STATUS -memDefRetSuccess ( VOID ) -{ - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/merrhdl.c deleted file mode 100644 index 924a5ae5ec..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/merrhdl.c +++ /dev/null @@ -1,188 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * merrhdl.c - * - * Memory error handling - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "heapManager.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MERRHDL_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function handle errors occur in memory code. - * - * - * @param[in,out] *MCTPtr - pointer to DIE_STRUCT. - * @param[in,out] DCT - DCT that needs to be handled. - * @param[in,out] ChipSelMask - Chip select mask that needs to be handled - * @param[in,out] *StdHeader - pointer to AMD_CONFIG_PARAMS - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemErrHandle ( - IN DIE_STRUCT *MCTPtr, - IN UINT8 DCT, - IN UINT16 ChipSelMask, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN ErrorRecovery; - BOOLEAN IgnoreErr; - DCT_STRUCT *DCTPtr; - UINT8 CurrentDCT; - LOCATE_HEAP_PTR LocHeap; - MEM_NB_BLOCK *NBPtr; - MEM_MAIN_DATA_BLOCK mmData; - - DCTPtr = MCTPtr->DctData; - ErrorRecovery = TRUE; - IgnoreErr = FALSE; - IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, StdHeader); - - if (ErrorRecovery) { - if (DCT == EXCLUDE_ALL_DCT) { - // Exclude all DCTs on a node - for (CurrentDCT = 0; CurrentDCT < MCTPtr->DctCount; CurrentDCT++) { - DCTPtr[CurrentDCT].Timings.CsTestFail = DCTPtr[CurrentDCT].Timings.CsPresent; - } - } else if (ChipSelMask == EXCLUDE_ALL_CHIPSEL) { - // Exclude the specified DCT - DCTPtr[DCT].Timings.CsTestFail = DCTPtr[DCT].Timings.CsPresent; - } else { - // Exclude the chip select that has been marked out - DCTPtr[DCT].Timings.CsTestFail |= ChipSelMask & DCTPtr[DCT].Timings.CsPresent; - IDS_OPTION_HOOK (IDS_LOADCARD_ERROR_RECOVERY, &DCTPtr[DCT], StdHeader); - } - - // Exclude the failed dimm to recovery from error - if (MCTPtr->NodeMemSize != 0) { - LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - // NB block has already been constructed by main block. - // No need to construct it here. - NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr; - if (!NBPtr->SharedPtr->NodeMap[MCTPtr->NodeId].IsValid) { - // Memory map has not been calculated, no need to remap memory across node here. - // Only need to remap memory within the node. - NBPtr = &NBPtr[MCTPtr->NodeId]; - NBPtr->FeatPtr->ExcludeDIMM (NBPtr); - } else { - // Need to remap memory across the whole system. - mmData.MemPtr = NBPtr->MemPtr; - mmData.mmSharedPtr = NBPtr->SharedPtr; - mmData.NBPtr = NBPtr; - mmData.TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[NBPtr->MemPtr->DieCount]); - mmData.DieCount = NBPtr->MemPtr->DieCount; - if (!MemFeatMain.ExcludeDIMM (&mmData)) { - return FALSE; - } - } - } - // If allocation fails, that means the code is not running at BSP. - // Parallel training is in process. - // Remap for parallel training will be done when control returns to BSP. - } - return TRUE; - } else { - IDS_OPTION_HOOK (IDS_MEM_IGNORE_ERROR, &IgnoreErr, StdHeader); - if (IgnoreErr) { - return TRUE; - } - SetMemError (AGESA_FATAL, MCTPtr); - // ErrorRecovery is FALSE - return FALSE; - } -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/minit.c deleted file mode 100644 index 34fd929077..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/minit.c +++ /dev/null @@ -1,138 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * minit.c - * - * Initializer support function - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "AdvancedApi.h" -#include "mu.h" -#include "OptionMemory.h" -#include "Ids.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MINIT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern MEM_NB_SUPPORT memNBInstalled[]; -extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[]; - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the default parameter, function pointers, build options - * and SPD data for memory configuration - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in,out] *PlatFormConfig - Platform profile/build option config structure - * - */ - -VOID -AmdMemInitDataStructDef ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT PLATFORM_CONFIGURATION *PlatFormConfig - ) -{ - UINT8 p; - UINT8 i; - // We need a way of specifying default values for each particular northbridge - // family. We also need to make sure that the IBV knows which parameter struct - // is for which northbridge. - //---------------------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &MemPtr->StdHeader); - - MemPtr->PlatFormConfig = PlatFormConfig; - - memNBInstalled[0].MemNInitDefaults (MemPtr); - - //---------------------------------------------------------------------------- - // INITIALIZE PLATFORM SPECIFIC CONFIGURATION STRUCT - //---------------------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &MemPtr->StdHeader); - i = 0; - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - if (memPlatformTypeInstalled[i] != NULL) { - MemPtr->GetPlatformCfg[p] = memPlatformTypeInstalled[i]; - i++; - } else { - MemPtr->GetPlatformCfg[p] = MemAGetPsCfgDef; - } - } - AGESA_TESTPOINT (TpProcMemAfterMemDataInit, &MemPtr->StdHeader); - MemPtr->ErrorHandling = MemErrHandle; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mm.c deleted file mode 100644 index 80df83a42f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mm.c +++ /dev/null @@ -1,253 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mm.c - * - * Main Memory Entrypoint file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MM_FILECODE -/* features */ - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function deallocates heap buffers that were allocated in AmdMemAuto - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -MemAmdFinalize ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT8 Die; - - for (Die = 0; Die < MemPtr->DieCount; Die++ ) { - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, Die, 0, 0), &MemPtr->StdHeader); - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, Die, 0, 0), &MemPtr->StdHeader); - } - - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), &MemPtr->StdHeader); - HeapDeallocateBuffer (AMD_S3_SAVE_HANDLE, &MemPtr->StdHeader); - HeapDeallocateBuffer (AMD_MEM_SPD_HANDLE, &MemPtr->StdHeader); - HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, &MemPtr->StdHeader); - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * MemSocketScan - Scan all nodes, recording the physical Socket number, - * Die Number (relative to the socket), and PCI Device address of each - * populated socket. - * - * This information is used by the northbridge block to map a dram - * channel on a particular DCT, on a particular CPU Die, in a particular - * socket to a the DRAM SPD Data for the DIMMS physically connected to - * that channel. - * - * Also, the customer socket map is populated with pointers to the - * appropriate channel structures, so that the customer can locate the - * appropriate channel configuration data. - * - * This socket scan will always result in Die 0 as the BSP. - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -AGESA_STATUS -MemSocketScan ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - UINT8 DieIndex; - UINT8 DieCount; - UINT32 SocketId; - UINT32 DieId; - UINT8 Die; - PCI_ADDR Address; - AGESA_STATUS AgesaStatus; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - ASSERT (mmPtr != NULL); - ASSERT (mmPtr->MemPtr != NULL); - MemPtr = mmPtr->MemPtr; - - // - // Count the number of dies in the system - // - DieCount = 0; - for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) { - if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) { - DieCount++; - } - } - MemPtr->DieCount = DieCount; - mmPtr->DieCount = DieCount; - - if (DieCount > 0) { - // - // Allocate buffer for DIE_STRUCTs - // - AllocHeapParams.RequestedBufferSize = ((UINT16)DieCount * sizeof (DIE_STRUCT)); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) { - MemPtr->DiesPerSystem = (DIE_STRUCT *)AllocHeapParams.BufferPtr; - // - // Find SocketId, DieId, and PCI address of each node - // - DieIndex = 0; - for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) { - if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) { - if (GetPciAddress ((VOID *)MemPtr, (UINT8)SocketId, (UINT8)DieId, &Address, &AgesaStatus)) { - MemPtr->DiesPerSystem[DieIndex].SocketId = (UINT8)SocketId; - MemPtr->DiesPerSystem[DieIndex].DieId = (UINT8)DieId; - MemPtr->DiesPerSystem[DieIndex].PciAddr.AddressValue = Address.AddressValue; - - DieIndex++; - } - } - } - AgesaStatus = AGESA_SUCCESS; - } else { - ASSERT(FALSE); // Heap allocation failed for DIE_STRUCTs - AgesaStatus = AGESA_FATAL; - } - } else { - ASSERT(FALSE); // No die in the system - AgesaStatus = AGESA_FATAL; - } - return AgesaStatus; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets memory errors into MemDataStruct - * - * - * @param[in,out] *MCTPtr - Pointer to the DIE_STRUCT - * @param[in] Errorval - Error value to update - */ - -VOID -SetMemError ( - IN AGESA_STATUS Errorval, - IN OUT DIE_STRUCT *MCTPtr - ) -{ - if (MCTPtr->ErrCode < Errorval) { - MCTPtr->ErrCode = Errorval; - } -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function is default function for the fultion list - * - * @param[in,out] *pMemData - Pointer to the MEM_DATA_STRUCT - */ -VOID -AmdMemFunctionListDef ( - IN OUT VOID *pMemData - ) -{ -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmConditionalPso.c deleted file mode 100644 index 2adc24a918..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmConditionalPso.c +++ /dev/null @@ -1,696 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmConditionalPso.c - * - * Functions to support conditional entries in the Platform Specific Override Table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -#define PSO_TYPE 0 -#define PSO_LENGTH 1 -#define PSO_DATA 2 - -typedef enum _PSO_STATE { - PSO_FIND_CONDITION = 100, // Searching for initial Condition statement - PSO_FIND_ACTION, // Searching for initial Action Statement - PSO_MATCH_ACTION, // Trying to find an action that matches the caller's request - PSO_CHECK_CONDITION, // Checking the condition that preceded the found action - PSO_DO_ACTION, // Performing Action - PSO_COMPLETE // Completed processing of this request -} PSO_STATE; - -typedef struct _D3_CMP_CAL { - UINT32 D3Cmp0NCal :3; - UINT32 Reserved34 :2; - UINT32 D3Cmp0PCal :3; - UINT32 Reserved89 :2; - UINT32 D3Cmp1NCal :3; - UINT32 Reserved1314 :2; - UINT32 D3Cmp1PCal :3; - UINT32 Reserved1819 :2; - UINT32 D3Cmp2NCal :3; - UINT32 Reserved2324 :2; - UINT32 D3Cmp2PCal :3; - UINT32 Reserved2831 :2; -} D3_CMP_CAL; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN - STATIC - MemPSODoActionODT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - - BOOLEAN - STATIC - MemPSODoActionAddrTmg ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - - BOOLEAN - STATIC - MemPSODoActionODCControl ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - - BOOLEAN - STATIC - MemPSODoActionSlewRate ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemPSODoActionGetFreqLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemCheckRankType ( - IN CH_DEF_STRUCT *CurrentChannel, - IN UINT16 RankType - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * Process Conditional Platform Specific Overrides - * - * @param[in] PlatformMemoryConfiguration - Pointer to Platform config table - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] PsoAction - Action type - * @param[in] Dimm - Dimm Number - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemProcessConditionalOverrides ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 PsoAction, - IN UINT8 Dimm - ) -{ - BOOLEAN Result; - MEM_TECH_BLOCK *TechPtr; - UINT8 *Buffer; - UINT8 *ConditionStartPtr; - UINT8 *ActionStartPtr; - UINT8 *SpdBufferPtr; - UINT8 i; - UINT8 DimmMask; - UINT8 CurDimmMask; - BOOLEAN Condition; - BOOLEAN TmpCond; - PSO_STATE State; - ASSERT (PlatformMemoryConfiguration != NULL); - ASSERT (NBPtr != NULL); - ASSERT ((PsoAction >= PSO_ACTION_MIN) && (PsoAction <= PSO_ACTION_MAX)); - // - // Set up local data - // - TechPtr = NBPtr->TechPtr; - Buffer = PlatformMemoryConfiguration; - State = PSO_FIND_CONDITION; - ConditionStartPtr = NULL; - ActionStartPtr = NULL; - Condition = FALSE; - DimmMask = 0xFF; - CurDimmMask = 0xFF; - Result = FALSE; - - if (Dimm != 0xFF) { - DimmMask = ( 1 << Dimm); - } - DimmMask &= (UINT8) (NBPtr->ChannelPtr->ChDimmValid & 0xFF); - if (DimmMask == 0) { - return Result; - } - - // - // Search for Condition Entry - // - while (State != PSO_COMPLETE) { - switch (State) { - // - // Searching for initial Condition statement - // - case PSO_FIND_CONDITION: - ASSERT (Buffer != NULL); - while (Buffer[PSO_TYPE] != PSO_CONDITION_AND) { - // - // If end of table is reached, Change state to complete and break. - // - if (Buffer[PSO_TYPE] == PSO_END) { - State = PSO_COMPLETE; - break; - } - // - // Otherwise, increment Buffer Pointer to the next PSO entry. - // - Buffer += (Buffer[PSO_LENGTH] + 2); - } - // - // If Condition statement has been found, save the Condition Start Pointer, - // and change to next state - // - if (State != PSO_COMPLETE) { - ASSERT (Buffer != NULL); - State = PSO_FIND_ACTION; - ConditionStartPtr = Buffer; - Buffer += (Buffer[PSO_LENGTH] + 2); - } - break; - // - // Searching for an action that matches the caller's request - // - case PSO_FIND_ACTION: - ASSERT (Buffer != NULL); - while (Buffer[PSO_TYPE] != PsoAction) { - // - // If non-conditional entry, change state to complete and break. - // - if ((Buffer[PSO_TYPE] < CONDITIONAL_PSO_MIN) || (Buffer[PSO_TYPE] > CONDITIONAL_PSO_MAX)) { - State = PSO_COMPLETE; - break; - } - // - // Check for the Start of a new condition block - // - if (Buffer[PSO_TYPE] == PSO_CONDITION_AND) { - ConditionStartPtr = Buffer; - } - // - // Otherwise, increment buffer pointer to the next PSO entry. - // - Buffer += (Buffer[PSO_LENGTH] + 2); - } - // - // If Action statement has been found, Save the Action Start Pointer, Reset Buffer to Condition Start - // and Change to next state. - // - if (State != PSO_COMPLETE) { - State = PSO_CHECK_CONDITION; - ASSERT (Buffer != NULL); - ActionStartPtr = Buffer; - Buffer = ConditionStartPtr; - Condition = TRUE; - } - break; - // - // Checking the condition that preceded the found action - // - case PSO_CHECK_CONDITION: - ASSERT (Buffer != NULL); - // - // Point to the next Condition - // - Buffer += (Buffer[PSO_LENGTH] + 2); - ASSERT ((Buffer[PSO_TYPE] >= CONDITIONAL_PSO_MIN) && (Buffer[PSO_TYPE] <= CONDITIONAL_PSO_MAX)); - // - // This section has already been checked for invalid statements so just exit on ACTION_xx - // - if ((Buffer[PSO_TYPE] >= PSO_ACTION_MIN) && (Buffer[PSO_TYPE] <= PSO_ACTION_MAX)) { - if (Condition) { - ASSERT (Buffer != NULL); - State = PSO_DO_ACTION; // Perform the Action - } else { - State = PSO_FIND_CONDITION; // Go back and look for another condition/action - } - Buffer = ActionStartPtr; // Restore Action Pointer - break; - } - switch (Buffer[PSO_TYPE]) { - - case PSO_CONDITION_AND: - // - // Additional CONDITION_AND is ORed with Previous ones, so if Previous result is TRUE - // just restore action pointer and perform the action. - // - if (Condition) { - State = PSO_DO_ACTION; - Buffer = ActionStartPtr; - } else { - // - // If its false, Start over and evaluate next cond. - // reset the Current Dimm Mask - // - Condition = TRUE; - CurDimmMask = 0xFF; - } - break; - - case PSO_CONDITION_LOC: - // - // Condition location - // - CurDimmMask = Buffer[4]; - Condition &= ( ((Buffer[2] & (1 << (NBPtr->MCTPtr->SocketId))) != 0) && - ((Buffer[3] & (1 << (NBPtr->ChannelPtr->ChannelID))) != 0) && - ((CurDimmMask & DimmMask) != 0) ); - break; - - case PSO_CONDITION_SPD: - // - // Condition SPD - // - TmpCond = FALSE; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { - if ( ((DimmMask & CurDimmMask) & ((UINT16) (1 << i))) != 0) { - if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, i)) { - TmpCond |= ( (SpdBufferPtr[Buffer[2]] & Buffer[3]) == Buffer[4]); - } - } - } - Condition &= TmpCond; - break; - - case PSO_CONDITION_REG: - // - // Condition Register - unsupported at this time - // - break; - - default: - ASSERT (FALSE); - } // End Condition Switch - break; - - case PSO_DO_ACTION: - ASSERT (Buffer != NULL); - // - // Performing Action - // - if ((Buffer[PSO_TYPE] < PSO_ACTION_MIN) || (Buffer[PSO_TYPE] > PSO_ACTION_MAX)) { - State = PSO_COMPLETE; - } - if (Buffer[PSO_TYPE] == PsoAction) { - switch (Buffer[PSO_TYPE]) { - case PSO_ACTION_ODT: - Result = MemPSODoActionODT (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_ADDRTMG: - Result = MemPSODoActionAddrTmg (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_ODCCONTROL: - Result = MemPSODoActionODCControl (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_SLEWRATE: - Result = MemPSODoActionSlewRate (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_SPEEDLIMIT: - Result = MemPSODoActionGetFreqLimit (NBPtr, &Buffer[PSO_DATA]); - break; - case PSO_ACTION_REG: - break; - default: - ASSERT (FALSE); - } // End Action Switch - // - // If Action was performed, mark complete. - // - if (Result) { - State = PSO_COMPLETE; - } - }// End Action - - // - // Point to the next PSO Entry - // - Buffer += (Buffer[PSO_LENGTH] + 2); - break; - - case PSO_COMPLETE: - // - // Completed processing of this request - // - break; - - default: - ASSERT (FALSE); - } // End State Switch - - } // End While - - return Result; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * Perform ODT Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionODT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - UINT32 Speed; - UINT8 Dimms; - UINT8 i; - UINT8 QR_Dimms; - Result = FALSE; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - Dimms = NBPtr->ChannelPtr->Dimms; - QR_Dimms = 0; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) { - QR_Dimms ++; - } - } - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if ((((UINT8) (1 << (Dimms - 1)) & Buffer[4]) != 0) || (Buffer[4] == ANY_NUM)) { - if (((QR_Dimms == 0) && (Buffer[5] == NO_DIMM)) || - ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & Buffer[5]) != 0)) || - (Buffer[5] == ANY_NUM)) { - NBPtr->PsPtr->DramTerm = Buffer[6]; - NBPtr->PsPtr->QR_DramTerm = Buffer[7]; - NBPtr->PsPtr->DynamicDramTerm = Buffer[8]; - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: DramTerm:%02x, QRDramTerm:%02x, DynDramTerm:%02x\n", Buffer[6], Buffer[7], Buffer[8]); - } - } - } - return Result; - } - - /* -----------------------------------------------------------------------------*/ -/** - * Perform Address Timing Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionAddrTmg ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - UINT32 Speed; - UINT16 DimmConfig; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - DimmConfig = *(UINT16 *) &(Buffer[4]); - - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - ChannelPtr->DctAddrTmg = *(UINT32*) &(Buffer[6]); - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Address Timing:%08x\n", *(UINT32*) &(Buffer[6])); - } - } - return Result; - } - - /* -----------------------------------------------------------------------------*/ -/** - * Perform Drive Strength Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionODCControl ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - UINT32 Speed; - UINT16 DimmConfig; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - DimmConfig = *(UINT16 *) &(Buffer[4]); - - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - ChannelPtr->DctOdcCtl = *(UINT32*) &(Buffer[6]); - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: ODC Control:%08x\n", *(UINT32*)&(Buffer[6])); - } - } - return Result; - } - - /* -----------------------------------------------------------------------------*/ -/** - * Perform Slew Rate Platform Override - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPSODoActionSlewRate ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - UINT32 Speed; - UINT16 DimmConfig; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66)); - DimmConfig = *(UINT16 *) &(Buffer[4]); - - if ((Speed & ((UINT32 *) Buffer)[0]) != 0) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0NCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0PCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1NCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1PCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2NCal ); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2PCal ); - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Slew Rate:%08x\n", *(UINT32 *) &(Buffer[6])); - } - } - return Result; - } - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the POR supported speed for a specific config - * - * @param[in] NBPtr - Pointer to Current NBBlock - * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len) - * - * @return BOOLEAN - TRUE : Action was performed - * FALSE: Action was not performed - * - */ -BOOLEAN -STATIC -MemPSODoActionGetFreqLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - BOOLEAN Result; - CH_DEF_STRUCT *ChannelPtr; - DCT_STRUCT *DCTPtr; - UINT16 DimmConfig; - UINT16 SpeedLimit; - - Result = FALSE; - ChannelPtr = NBPtr->ChannelPtr; - DCTPtr = NBPtr->DCTPtr; - DimmConfig = *(UINT16*) &(Buffer[0]); - SpeedLimit = 0; - // - // Match number of dimms, then Rank Type - // - if (ChannelPtr->Dimms == Buffer[2]) { - if (MemCheckRankType (ChannelPtr, DimmConfig)) { - // - // Select speed based on current voltage - // - if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { - SpeedLimit = *(UINT16*) &(Buffer[3]); - } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) { - SpeedLimit = *(UINT16*) &(Buffer[7]); - } else { - SpeedLimit = *(UINT16*) &(Buffer[5]); - } - // - // Set the Speed limit - // - if (DCTPtr->Timings.TargetSpeed > SpeedLimit) { - DCTPtr->Timings.TargetSpeed = SpeedLimit; - } - Result = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Max Memory Speed for Channel %d: %d\n", NBPtr->Channel, SpeedLimit); - } - } - return Result; -} - - /* -----------------------------------------------------------------------------*/ -/** - * - * This function matches a particular Rank Type Mask to the installed - * DIMM configuration on the provided channel. - * - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * @param[in] RankType Mask of rank type to match - * - * @return BOOLEAN - TRUE : Rank types match - * FALSE: Rank types do not match - * - */ -BOOLEAN -STATIC -MemCheckRankType ( - IN CH_DEF_STRUCT *CurrentChannel, - IN UINT16 RankType - ) -{ - BOOLEAN Result; - UINT8 i; - UINT16 DIMMRankType; - - DIMMRankType = MemAGetPsRankType (CurrentChannel); - Result = TRUE; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ( ((DIMMRankType & (0x0F << (i << 2))) + (RankType & (0x0F << (i << 2)))) != 0) { - Result &= (((DIMMRankType & (0x0F << (i << 2))) & ( RankType & ( 0x0F << ( i << 2)))) != 0); - } - if (!Result) { - break; - } - } - return Result; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmEcc.c deleted file mode 100644 index dbce871c1a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmEcc.c +++ /dev/null @@ -1,136 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmEcc.c - * - * Main Memory Feature implementation file for ECC Initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "Porting.h" -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "mfmemclr.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMECC_FILECODE -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemMEcc ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMEcc ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - UINT8 Die; - MEM_SHARED_DATA *SharedPtr; - MEM_PARAMETER_STRUCT *RefPtr; - BOOLEAN RetVal; - - RetVal = TRUE; - RefPtr = mmPtr->MemPtr->ParameterListPtr; - SharedPtr = mmPtr->mmSharedPtr; - - // - // Run Northbridge-specific ECC initialization feature for each die. - // - SharedPtr->AllECC = FALSE; - if (RefPtr->EnableEccFeature) { - SharedPtr->AllECC = TRUE; - AGESA_TESTPOINT (TpProcMemEccInitialization, &(mmPtr->MemPtr->StdHeader)); - - for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { - mmPtr->NBPtr[Die].FeatPtr->CheckEcc (&(mmPtr->NBPtr[Die])); - RetVal &= (BOOLEAN) (mmPtr->NBPtr[Die].MCTPtr->ErrCode < AGESA_FATAL); - } - if (SharedPtr->AllECC == TRUE) { - RefPtr->GStatus[GsbAllECCDimms] = TRUE; - // Sync mem clear before setting scrub rate. - for (Die = 0; Die < mmPtr->DieCount; Die++) { - MemFMctMemClr_Sync (&(mmPtr->NBPtr[Die])); - } - } - } - // Scrubber control - for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { - mmPtr->NBPtr[Die].FeatPtr->InitEcc (&(mmPtr->NBPtr[Die])); - } - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmExcludeDimm.c deleted file mode 100644 index 914d833d53..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmExcludeDimm.c +++ /dev/null @@ -1,245 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmExcludeDimm.c - * - * Main Memory Feature implementation file for RAS DIMM Exclude Feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 58065 $ @e \$Date: 2011-08-19 01:55:26 -0600 (Fri, 19 Aug 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "mport.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemMRASExcludeDIMM ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and disable Chip selects that fail training on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMRASExcludeDIMM ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN IsEnabled; - BOOLEAN RetVal; - BOOLEAN IsChannelIntlvEnabled[MAX_NODES_SUPPORTED]; - UINT8 FirstEnabledNode; - UINT32 BottomIO; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *RefPtr; - S_UINT64 SMsr; - - FirstEnabledNode = 0; - IsEnabled = FALSE; - RetVal = TRUE; - NBPtr = MemMainPtr->NBPtr; - RefPtr = NBPtr[BSP_DIE].RefPtr; - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (NBPtr[Node].FeatPtr->ExcludeDIMM (&NBPtr[Node])) { - if (!IsEnabled) { - // Record the first node that has exclude dimm enabled - FirstEnabledNode = Node; - IsEnabled = TRUE; - } - } - } - - // Force memory address remap when we want to undo 1TB hoisting - if (NBPtr->SharedPtr->UndoHoistingAbove1TB) { - IsEnabled = TRUE; - } - - if (IsEnabled) { - // Check if all nodes have all dimms excluded. If yes, fatal exit - NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0; - BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8; - // If the first node that has excluded dimms does not have a system base smaller - // than bottomIO, then we don't need to reset the GStatus, as we don't need to - // remap memory hole. - if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) { - RefPtr->GStatus[GsbHWHole] = FALSE; - RefPtr->GStatus[GsbSpIntRemapHole] = FALSE; - RefPtr->GStatus[GsbSoftHole] = FALSE; - RefPtr->HoleBase = 0; - RefPtr->SysLimit = 0; - } - // If Node Interleaving has been executed before the remapping then we need to - // start from the first node. - // There may be a few senarios: - // 1. Node interleaving is not enabled before the remap, and still cannot be enabled after - // remap - // 2. Node interleaving cannot be enabled before the remap, but it can be enabled after - // remap - // 3. Node interleaving is enabled before the remap, but it cannot be enabled after the remap - if (NBPtr->SharedPtr->NodeIntlv.IsValid) { - FirstEnabledNode = 0; - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - IsChannelIntlvEnabled [Node] = FALSE; - // Check if node interleaving has been enabled on this node - // if yes, disable it. - if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDramIntlvEn) != 0) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvEn, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvSel, 0); - } - if (Node >= FirstEnabledNode) { - // Remap memory on nodes with node number larger than the first node that has excluded dimms. - // If channel interleaving has already been enabled, need to disable it before remapping memory. - if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDctSelIntLvEn) != 0) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelIntLvEn, 0); - IsChannelIntlvEnabled [Node] = TRUE; - } - NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE; - NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE; - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - NBPtr[Node].HtMemMapInit (&NBPtr[Node]); - } else if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { - // No change is needed in the memory map of this node. - // Need to adjust the current system base for other nodes processed later. - NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0; - RefPtr->SysLimit = NBPtr[Node].MCTPtr->NodeSysLimit; - // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0. - // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base - // and DramMemHoistValid. - // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well - // DramHoleValid. - if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - } - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); - } - - LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - // Only when TOM is set can CpuMemTyping be re-run - if ((SMsr.hi != 0) || (SMsr.lo != 0)) { - if (RefPtr->SysLimit != 0) { - NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]); - - // When 1TB hoisting is not supported, TOP_MEM2 cannot exceed HT reserved region base. - if ((RefPtr->SysLimit >= HT_REGION_BASE_RJ16) && (NBPtr->SharedPtr->UndoHoistingAbove1TB)) { - SMsr.hi = HT_REGION_BASE_RJ16 >> (32 - 16); - SMsr.lo = HT_REGION_BASE_RJ16 << 16; - LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", HT_REGION_BASE_RJ16); - RefPtr->Sub1THoleBase = HT_REGION_BASE_RJ16; - RefPtr->SysLimit = HT_REGION_BASE_RJ16 - 1; - } - } - } - - // Re-run node interleaving if it has been exeucuted before the remap - if (NBPtr->SharedPtr->NodeIntlv.IsValid) { - MemFeatMain.InterleaveNodes (MemMainPtr); - } - - // Re-enable channel interleaving if it was enabled before remapping memory - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (IsChannelIntlvEnabled [Node]) { - NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node]); - } - } - - // Reset UndoHoistingAbove1TB if it was previously set - NBPtr->SharedPtr->UndoHoistingAbove1TB = FALSE; - } - - // if all dimms on all nodes are excluded, do fatal exit - if (RefPtr->SysLimit == 0) { - PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr); - ASSERT (FALSE); - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c deleted file mode 100644 index 2874f3f76f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c +++ /dev/null @@ -1,292 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmLvDdr3.c - * - * Main Memory Feature implementation file for low voltage DDR3 support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mmLvDdr3.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMLVDDR3_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * Find the common supported voltage on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMLvDdr3 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN RetVal; - BOOLEAN SecondLoop; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *ParameterPtr; - MEM_SHARED_DATA *mmSharedPtr; - - NBPtr = MemMainPtr->NBPtr; - mmSharedPtr = MemMainPtr->mmSharedPtr; - ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; - mmSharedPtr->VoltageMap = 0xFF; - SecondLoop = FALSE; - RetVal = TRUE; - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].FeatPtr->LvDdr3 (&NBPtr[Node]); - // Check if there is no common supported voltage - if ((mmSharedPtr->VoltageMap == 0) && !SecondLoop) { - // restart node loop by setting node to 0xFF - Node = 0xFF; - SecondLoop = TRUE; - } - } - - if (mmSharedPtr->VoltageMap == 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo commonly supported VDDIO is found.\n"); - PutEventLog (AGESA_WARNING, MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader)); - SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr); - // When there is no commonly supported VDDIO, use 1.35V as the temporal VDDIO - ParameterPtr->DDR3Voltage = VOLT1_35; - } else { - IDS_HDT_CONSOLE (MEM_FLOW, "\nCommonly supported VDDIO is: %s%s%s.\n", ((mmSharedPtr->VoltageMap & 1) != 0) ? "1.5V, " : "", ((mmSharedPtr->VoltageMap & 2) != 0) ? "1.35V, " : "", ((mmSharedPtr->VoltageMap & 4) != 0) ? "1.25V" : ""); - ParameterPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (LibAmdBitScanReverse (mmSharedPtr->VoltageMap)); - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - // Check if the voltage needs force to 1.5V - NBPtr[Node].FamilySpecificHook[ForceLvDimmVoltage] (&NBPtr[Node], MemMainPtr); - - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Find the common supported voltage on all nodes, taken into account of the - * user option for performance and power saving. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMLvDdr3PerformanceEnhPre ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN RetVal; - DIMM_VOLTAGE VDDIO; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *ParameterPtr; - MEM_SHARED_DATA *mmSharedPtr; - PLATFORM_POWER_POLICY PowerPolicy; - - NBPtr = MemMainPtr->NBPtr; - mmSharedPtr = MemMainPtr->mmSharedPtr; - ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; - PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy; - - IDS_OPTION_HOOK (IDS_MEMORY_POWER_POLICY, &PowerPolicy, &NBPtr->MemPtr->StdHeader); - IDS_HDT_CONSOLE (MEM_FLOW, (PowerPolicy == Performance) ? "\nMaximize Performance\n" : "\nMaximize Battery Life\n"); - - if (ParameterPtr->DDR3Voltage != VOLT_INITIAL) { - mmSharedPtr->VoltageMap = VDDIO_DETERMINED; - PutEventLog (AGESA_WARNING, MEM_WARNING_INITIAL_DDR3VOLT_NONZERO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader)); - SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "Warning: Initial Value for VDDIO has been changed.\n"); - RetVal = TRUE; - } else { - RetVal = MemMLvDdr3 (MemMainPtr); - - VDDIO = ParameterPtr->DDR3Voltage; - if (NBPtr->IsSupported[PerformanceOnly] || ((PowerPolicy == Performance) && (mmSharedPtr->VoltageMap != 0))) { - // When there is no commonly supported voltage, do not optimize performance - // For cases where we can maximize performance, do the following - // When VDDIO is enforced, DDR3Voltage will be overriden by specific VDDIO - // So cases with DDR3Voltage left to be VOLT_UNSUPPORTED will be open to maximizing performance. - ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED; - } - - IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader); - - if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) { - // When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance - mmSharedPtr->VoltageMap = VDDIO_DETERMINED; - IDS_HDT_CONSOLE (MEM_FLOW, "VDDIO is determined. No further optimization will be done.\n"); - } else { - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY; - NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY; - NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY; - } - // Reprogram the leveling result as temporal candidate - ParameterPtr->DDR3Voltage = VDDIO; - } - } - - ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED); - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Finalize the VDDIO for the board for performance enhancement. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMLvDdr3PerformanceEnhFinalize ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Dct; - UINT8 Node; - UINT8 NodeCnt[VOLT1_25 + 1]; - UINT8 MaxCnt; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *ParameterPtr; - MEM_SHARED_DATA *mmSharedPtr; - UINT8 CurrentVoltage; - DIMM_VOLTAGE Voltage; - MEMORY_BUS_SPEED HighestFreq; - - ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr; - mmSharedPtr = MemMainPtr->mmSharedPtr; - NBPtr = MemMainPtr->NBPtr; - - LibAmdMemFill (NodeCnt, 0, VOLT1_25_ENCODED_VAL + 1, &NBPtr->MemPtr->StdHeader); - if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) { - Voltage = ParameterPtr->DDR3Voltage; - IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency: \n"); - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - HighestFreq = 0; - // Find out what the highest frequency that can be reached is on this node across different voltage. - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (HighestFreq < NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]) { - HighestFreq = NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "Node%d: 1.5V -> %dMHz, 1.35V -> %dMHz, 1.25V -> %dMHz\n", Node, NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL], NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL], NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL]); - // Figure out what voltage we can have when attaining the highest frequency. - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (NBPtr[Node].MaxFreqVDDIO[CurrentVoltage] == HighestFreq) { - NodeCnt[CurrentVoltage] ++; - } - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "Number of nodes that can run at maximize performance: 1.5V -> %d Nodes 1.35V -> %d Nodes 1.25V -> %d Nodes.\n", NodeCnt[VOLT1_5_ENCODED_VAL], NodeCnt[VOLT1_35_ENCODED_VAL], NodeCnt[VOLT1_25_ENCODED_VAL]); - MaxCnt = 0; - // Use the VDDIO at which most nodes can run at higher frequency - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (MaxCnt <= NodeCnt[CurrentVoltage]) { - MaxCnt = NodeCnt[CurrentVoltage]; - ParameterPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (CurrentVoltage); - } - } - - ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED); - - mmSharedPtr->VoltageMap = VDDIO_DETERMINED; - if (Voltage != ParameterPtr->DDR3Voltage) { - // Finalize frequency with updated finalized VDDIO - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - // Need to re-sync target speed and different VDDIO may cause different settings - NBPtr[Node].TechPtr->SpdGetTargetSpeed (NBPtr[Node].TechPtr); - for (Dct = 0; Dct < NBPtr[Node].DctCount; Dct++) { - NBPtr[Node].SwitchDCT (&(NBPtr[Node]), Dct); - if (NBPtr[Node].DCTPtr->Timings.CsEnabled != 0) { - if (!NBPtr[Node].PlatformSpec (&(NBPtr[Node]))) { - return FALSE; - } - } - } - } - } - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.h deleted file mode 100644 index 64aeeb5108..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.h +++ /dev/null @@ -1,86 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmLvDdr3.h - * - * Main low voltage DDR3 support common header - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 37291 $ @e \$Date: 2010-09-01 13:55:44 -0500 (Wed, 01 Sep 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _MMLVDDR3_H_ -#define _MMLVDDR3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemMLvDdr3 ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -MemMLvDdr3PerformanceEnhPre ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -MemMLvDdr3PerformanceEnhFinalize ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); -#endif /* _MMLVDDR3_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemClr.c deleted file mode 100644 index 84ad09b16c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemClr.c +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmMemclr.c - * - * Main Memory Feature implementation file for Memory Clear. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "mfmemclr.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMMEMCLR_FILECODE -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemMMctMemClr ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Initiates/synchronizes memory clear on all nodes with Dram on it. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMMctMemClr ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 NodeCnt; - BOOLEAN RetVal; - MEM_NB_BLOCK *NBPtr; - - NBPtr = MemMainPtr->NBPtr; - NodeCnt = MemMainPtr->DieCount; - RetVal = TRUE; - - IDS_OPTION_HOOK (IDS_BEFORE_MEMCLR, NULL, &NBPtr->MemPtr->StdHeader); - - for (Node = 0; Node < NodeCnt; Node++) { - MemFMctMemClr_Init (&NBPtr[Node]); - } - - for (Node = 0; Node < NodeCnt; Node++) { - MemFMctMemClr_Sync (&NBPtr[Node]); - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - - return RetVal; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemRestore.c deleted file mode 100644 index df1c1d7efb..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmMemRestore.c +++ /dev/null @@ -1,607 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmMemRestore.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "S3.h" -#include "mfs3.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMMEMRESTORE_FILECODE - -#define ST_PRE_ESR 0 -#define ST_POST_ESR 1 -#define ST_DONE 2 - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemMRestoreDqsTimings ( - IN VOID *Storage, - IN MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -STATIC -MemMSetCSRNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, - IN PCI_ADDR PciAddr, - IN UINT32 Value - ); - -VOID -STATIC -MemMCreateS3NbBlock ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr, - OUT S3_MEM_NB_BLOCK **S3NBPtr - ); - -VOID -MemMContextSave ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -BOOLEAN -MemMContextRestore ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -extern MEM_NB_SUPPORT memNBInstalled[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and save memory context if possible. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -VOID -MemMContextSave ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 i; - MEM_PARAMETER_STRUCT *RefPtr; - LOCATE_HEAP_PTR LocHeap; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - DEVICE_BLOCK_HEADER *DeviceList; - AMD_CONFIG_PARAMS *StdHeader; - UINT32 BufferSize; - VOID *BufferOffset; - MEM_NB_BLOCK *NBArray; - S3_MEM_NB_BLOCK *S3NBPtr; - DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED]; - - NBArray = MemMainPtr->NBPtr; - RefPtr = NBArray[BSP_DIE].RefPtr; - - if (RefPtr->SaveMemContextCtl) { - RefPtr->MemContext.NvStorage = NULL; - RefPtr->MemContext.NvStorageSize = 0; - - // Make sure DQS training has occurred before saving memory context - if (!RefPtr->MemRestoreCtl) { - StdHeader = &MemMainPtr->MemPtr->StdHeader; - - MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr); - if (S3NBPtr != NULL) { - // Get the mask bit and the register list for node that presents - BufferSize = 0; - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - S3NBPtr->MemS3GetConPCIMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]); - S3NBPtr->MemS3GetConMSRMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]); - BufferSize += S3NBPtr->MemS3GetRegLstPtr (&NBArray[Node], (VOID *)&DeviceDescript[Node]); - } - - // Base on the size of the device list, apply for a buffer for it. - AllocHeapParams.RequestedBufferSize = (UINT32) (BufferSize + sizeof (DEVICE_BLOCK_HEADER)); - AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - DeviceList = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr; - DeviceList->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; - - // Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + AllocHeapParams.BufferPtr; - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - for (i = PRESELFREF; i <= POSTSELFREF; i ++) { - // Copy PCI device descriptor to the heap if it exists. - if (DeviceDescript[Node].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset = sizeof (PCI_DEVICE_DESCRIPTOR) + (UINT8 *)BufferOffset; - } - // Copy conditional PCI device descriptor to the heap if it exists. - if (DeviceDescript[Node].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset = sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR) + (UINT8 *)BufferOffset; - } - // Copy MSR device descriptor to the heap if it exists. - if (DeviceDescript[Node].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset = sizeof (MSR_DEVICE_DESCRIPTOR) + (UINT8 *)BufferOffset; - } - // Copy conditional MSR device descriptor to the heap if it exists. - if (DeviceDescript[Node].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); - DeviceList->NumDevices ++; - BufferOffset = sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR) + (UINT8 *)BufferOffset; - } - } - } - - // Determine size needed - BufferSize = GetWorstCaseContextSize (DeviceList, INIT_RESUME, StdHeader); - AllocHeapParams.RequestedBufferSize = BufferSize; - AllocHeapParams.BufferHandle = AMD_S3_SAVE_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - // Save memory context - SaveDeviceListContext (DeviceList, AllocHeapParams.BufferPtr, INIT_RESUME, &BufferSize, StdHeader); - RefPtr->MemContext.NvStorageSize = BufferSize; - } - - HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader); - } - } - HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader); - - // Locate MemContext since it might have been shifted after deallocating - LocHeap.BufferHandle = AMD_S3_SAVE_HANDLE; - if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) { - RefPtr->MemContext.NvStorage = LocHeap.BufferPtr; - } - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and restore memory context if possible. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - DQS timing restore succeeds. - * @return FALSE - DQS timing restore fails. - */ -BOOLEAN -MemMContextRestore ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - MEM_NB_BLOCK *NBArray; - MEM_PARAMETER_STRUCT *RefPtr; - S3_MEM_NB_BLOCK *S3NBPtr; - - NBArray = MemMainPtr->NBPtr; - RefPtr = NBArray[BSP_DIE].RefPtr; - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Mem Restore\n"); - if (RefPtr->MemRestoreCtl) { - if (RefPtr->MemContext.NvStorage != NULL) { - MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr); - if (S3NBPtr != NULL) { - // Check DIMM config and restore DQS timings if possible - if (!MemMRestoreDqsTimings (RefPtr->MemContext.NvStorage, MemMainPtr)) { - RefPtr->MemRestoreCtl = FALSE; - } - } else { - RefPtr->MemRestoreCtl = FALSE; - } - HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, &(MemMainPtr->MemPtr->StdHeader)); - } else { - RefPtr->MemRestoreCtl = FALSE; - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]); - } - IDS_HDT_CONSOLE (MEM_FLOW, RefPtr->MemRestoreCtl ? "Mem Restore Succeeds!\n" : "Mem Restore Fails!\n"); - return RefPtr->MemRestoreCtl; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Restores all devices that contains DQS timings - * - * @param[in] Storage Beginning of the device list. - * @param[in,out] MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - * - */ -BOOLEAN -STATIC -MemMRestoreDqsTimings ( - IN VOID *Storage, - IN MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - UINT8 *OrMask; - DEVICE_DESCRIPTORS Device; - INT16 i; - INT16 j; - DEVICE_BLOCK_HEADER *DeviceList; - PCI_REGISTER_BLOCK_HEADER *Reg; - CPCI_REGISTER_BLOCK_HEADER *CReg; - MSR_REGISTER_BLOCK_HEADER *MsrReg; - CMSR_REGISTER_BLOCK_HEADER *CMsrReg; - PCI_ADDR PciAddress; - MEM_NB_BLOCK *NBArray; - UINT8 State; - UINT8 Node; - UINT8 Dct; - UINT8 MaxNode; - - NBArray = MemMainPtr->NBPtr; - StdHeader = &(MemMainPtr->MemPtr->StdHeader); - DeviceList = (DEVICE_BLOCK_HEADER *) Storage; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; - - if (DeviceList->NumDevices == 0) { - return FALSE; - } - - MaxNode = 0; - State = ST_PRE_ESR; - for (i = 0; State != ST_DONE; i++) { - if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI))) { - MemFS3GetPciDeviceRegisterList (Device.PciDevice, &Reg, StdHeader); - Node = Device.PciDevice->Node; - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); - PciAddress = NBArray[Node].PciAddr; - for (j = 0; j < Reg->NumRegisters; j++) { - PciAddress.Address.Function = Reg->RegisterList[j].Function; - PciAddress.Address.Register = Reg->RegisterList[j].Offset; - PciAddress.Address.Segment = (Reg->RegisterList[j].Type.SpecialCaseFlag != 0) ? - 0xF - Reg->RegisterList[j].Type.SpecialCaseIndex : 0; - if (!MemMSetCSRNb (&NBArray[Node], Reg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & Reg->RegisterList[j].AndMask)) { - return FALSE; // Restore fails - } - OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 : Reg->RegisterList[j].Type.RegisterSize; - } - - if (MaxNode < Node) { - MaxNode = Node; - } - - } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI))) { - MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &CReg, StdHeader); - Node = Device.CPciDevice->Node; - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node); - PciAddress = NBArray[Node].PciAddr; - for (j = 0; j < CReg->NumRegisters; j++) { - if (((Device.CPciDevice->Mask1 & CReg->RegisterList[j].Mask1) != 0) && - ((Device.CPciDevice->Mask2 & CReg->RegisterList[j].Mask2) != 0)) { - PciAddress.Address.Function = CReg->RegisterList[j].Function; - PciAddress.Address.Register = CReg->RegisterList[j].Offset; - PciAddress.Address.Segment = (CReg->RegisterList[j].Type.SpecialCaseFlag != 0) ? - 0xF - CReg->RegisterList[j].Type.SpecialCaseIndex : 0; - if (!MemMSetCSRNb (&NBArray[Node], CReg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & CReg->RegisterList[j].AndMask)) { - return FALSE; // Restore fails - } - OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 : CReg->RegisterList[j].Type.RegisterSize; - } - } - } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR))) { - MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &MsrReg, StdHeader); - for (j = 0; j < MsrReg->NumRegisters; j++) { - OrMask += 8; - } - } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR_PRE_ESR)) || - ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR))) { - MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &CMsrReg, StdHeader); - for (j = 0; j < CMsrReg->NumRegisters; j++) { - if (((Device.CMsrDevice->Mask1 & CMsrReg->RegisterList[j].Mask1) != 0) && - ((Device.CMsrDevice->Mask2 & CMsrReg->RegisterList[j].Mask2) != 0)) { - OrMask += 8; - } - } - } - - switch (Device.CommonDeviceHeader->Type) { - case DEV_TYPE_PCI_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_PCI: - Device.PciDevice++; - break; - case DEV_TYPE_CPCI_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_CPCI: - Device.CPciDevice++; - break; - case DEV_TYPE_MSR_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_MSR: - Device.MsrDevice++; - break; - case DEV_TYPE_CMSR_PRE_ESR: - // Fall through to advance the pointer after restoring context - case DEV_TYPE_CMSR: - Device.CMsrDevice++; - break; - default: - ASSERT (FALSE); - break; - } - - if (i == (DeviceList->NumDevices - 1)) { - // Go to next state - State++; - i = -1; - Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; - - // Check to see if processor or DIMM population has changed - if ((MaxNode + 1) != MemMainPtr->DieCount) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: Population changed\n"); - return FALSE; - } - - // Perform MemClk frequency change - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - if (NBArray[Node].MCTPtr->NodeMemSize != 0) { - NBArray[Node].BeforeDqsTraining (&NBArray[Node]); - if (NBArray[Node].DCTPtr->Timings.Speed < NBArray[Node].DCTPtr->Timings.TargetSpeed) { - for (Dct = 0; Dct < NBArray[Node].DctCount; Dct++) { - NBArray[Node].SwitchDCT (&NBArray[Node], Dct); - NBArray[Node].DCTPtr->Timings.Speed = NBArray[Node].DCTPtr->Timings.TargetSpeed; - } - IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, &NBArray[Node], &(MemMainPtr->MemPtr->StdHeader)); - NBArray[Node].ChangeFrequency (&NBArray[Node]); - } - } - } - } - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function filters out other settings and only restores DQS timings. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] SpecialCases - Pointer to special cases array handlers - * @param[in] PciAddr - address of the CSR register in PCI_ADDR format. - * @param[in] Value - Value to be programmed - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - * - */ - -BOOLEAN -STATIC -MemMSetCSRNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, - IN PCI_ADDR PciAddr, - IN UINT32 Value - ) -{ - UINT32 Offset; - UINT8 Dct; - UINT32 Temp; - BOOLEAN RetVal; - UINT32 BOffset; - - RetVal = TRUE; - if (PciAddr.Address.Segment != 0) { - if (PciAddr.Address.Segment == 0xF) { - PciAddr.Address.Segment = 0; - Dct = (UINT8) ((PciAddr.Address.Register >> 10) & 1); - Offset = PciAddr.Address.Register & 0x3FF; - BOffset = PciAddr.Address.Register & 0xFF; - if ((PciAddr.Address.Register & 0x800) == 0) { - if (((BOffset >= 1) && (BOffset <= 3)) || - ((BOffset >= 5) && (BOffset <= 7)) || - ((Offset >= 0x10) && (Offset <= 0x2B)) || - ((Offset >= 0x30) && (Offset <= 0x4A))) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tF2_%d9C_%03x = %08x\n", Dct, Offset, Value); - //MemNS3SetCSR - SpecialCases[0].Restore (AccessS3SaveWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - } - } - } - } else { - Dct = (UINT8) ((PciAddr.Address.Register >> 8) & 1); - Offset = PciAddr.Address.Register & 0xFF; - - if (PciAddr.Address.Function == 2) { - if ((Offset >= 0x40) && (Offset < 0x60) && ((Value & 4) != 0)) { - // If TestFail bit is set, set CsTestFail - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((Offset - 0x40) >> 2); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBad CS:%d\n", ((Offset - 0x40) >> 2)); - } else if (Offset == 0x80) { - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - if (Temp != Value) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - } else if (Offset == 0x90) { - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - if ((Temp & 0x0001F000) != (Value & 0x0001F000)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - } else if (Offset == 0x94) { - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - if ((Temp & 0x00061000) != (Value & 0x00061000)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.TargetSpeed) != ((Value & 7) + 1))) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: MemClk has changed\n"); - RetVal = FALSE; - } - // Restore ZqcsInterval - Temp &= 0xFFFFF3FF; - Temp |= (Value & 0x00000C00); - LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - } else if (Offset == 0x78) { - // Program MaxRdLat - LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - Temp &= 0x0009BF0F; - Temp |= (Value & 0xFFC00000); - LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader); - } else if (PciAddr.Address.Register == 0x110) { - if ((NBPtr->MCTPtr->NodeMemSize != 0) && (Value == 0x00000100)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n"); - RetVal = FALSE; - } - } - } - } - - if (RetVal == FALSE) { - NBPtr->SwitchDCT (NBPtr, 0); - NBPtr->DCTPtr->Timings.CsTrainFail = 0; - NBPtr->SwitchDCT (NBPtr, 1); - NBPtr->DCTPtr->Timings.CsTrainFail = 0; - } - - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Create S3 NB Block. - * - * @param[in,out] MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * @param[out] S3NBPtr - Pointer to the S3 NB Block pointer - * - */ -VOID -STATIC -MemMCreateS3NbBlock ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr, - OUT S3_MEM_NB_BLOCK **S3NBPtr - ) -{ - UINT8 Node; - UINT8 i; - MEM_NB_BLOCK *NBArray; - MEM_NB_BLOCK *DummyNBs; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - NBArray = MemMainPtr->NBPtr; - - *S3NBPtr = NULL; - - // Allocate heap for S3 NB Blocks - AllocHeapParams.RequestedBufferSize = (MemMainPtr->DieCount * (sizeof (S3_MEM_NB_BLOCK) + sizeof (MEM_NB_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &(MemMainPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) { - *S3NBPtr = (S3_MEM_NB_BLOCK *) AllocHeapParams.BufferPtr; - DummyNBs = (MEM_NB_BLOCK *) (AllocHeapParams.BufferPtr + MemMainPtr->DieCount * sizeof (S3_MEM_NB_BLOCK)); - - // Initialize S3 NB Blocks - for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { - (*S3NBPtr)[Node].NBPtr = &DummyNBs[Node]; - - for (i = 0; memNBInstalled[i].MemS3ResumeConstructNBBlock != 0; i++) { - if (memNBInstalled[i].MemS3ResumeConstructNBBlock (&(*S3NBPtr)[Node], NBArray[BSP_DIE].MemPtr, Node)) { - break; - } - }; - if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) { - *S3NBPtr = NULL; - break; - } - } - } -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmNodeInterleave.c deleted file mode 100644 index f5965ad976..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmNodeInterleave.c +++ /dev/null @@ -1,145 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmNodeInterleave.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemMInterleaveNodes ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and enable node interleaving on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMInterleaveNodes ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - UINT8 NodeCnt; - BOOLEAN RetVal; - MEM_NB_BLOCK *NBPtr; - - NBPtr = MemMainPtr->NBPtr; - NodeCnt = 0; - RetVal = TRUE; - - if (NBPtr->RefPtr->EnableNodeIntlv) { - if (!MemFeatMain.MemClr (MemMainPtr)) { - PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_WARNING, NBPtr->MCTPtr); - return FALSE; - } - - MemMainPtr->mmSharedPtr->NodeIntlv.IsValid = FALSE; - MemMainPtr->mmSharedPtr->NodeIntlv.NodeIntlvSel = 0; - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (!NBPtr[Node].FeatPtr->CheckInterleaveNodes (&NBPtr[Node])) { - break; - } - if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { - NodeCnt ++; - } - } - - if ((Node == MemMainPtr->DieCount) && (NodeCnt != 0) && ((NodeCnt & (NodeCnt - 1)) == 0)) { - MemMainPtr->mmSharedPtr->NodeIntlv.NodeCnt = NodeCnt; - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (NBPtr[Node].MCTPtr->NodeMemSize != 0) { - NBPtr[Node].FeatPtr->InterleaveNodes (&NBPtr[Node]); - } - } - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - } else { - // - // If all nodes cannot be interleaved - // - PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_WARNING, NBPtr->MCTPtr); - } - } - - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmOnlineSpare.c deleted file mode 100644 index ef775b0953..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmOnlineSpare.c +++ /dev/null @@ -1,164 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmOnlineSpare.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMONLINESPARE_FILECODE -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemMOnlineSpare ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check and enable online spare on all nodes. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMOnlineSpare ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT8 Node; - BOOLEAN IsEnabled; - UINT8 FirstEnabledNode; - UINT32 BottomIO; - BOOLEAN RetVal; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *RefPtr; - - AGESA_TESTPOINT (TpProcMemOnlineSpareInit, &(MemMainPtr->MemPtr->StdHeader)); - FirstEnabledNode = 0; - IsEnabled = FALSE; - RetVal = TRUE; - NBPtr = MemMainPtr->NBPtr; - RefPtr = NBPtr[BSP_DIE].RefPtr; - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (NBPtr[Node].FeatPtr->OnlineSpare (&NBPtr[Node])) { - if (!IsEnabled) { - // Record the first node that has spared dimm enabled - FirstEnabledNode = Node; - IsEnabled = TRUE; - } - } - } - - if (IsEnabled) { - NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0; - BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8; - // If the first node that has spared dimms does not have a system base smaller - // than bottomIO, then we don't need to reset the GStatus, as we don't need to - // remap memory hole. - if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) { - RefPtr->GStatus[GsbHWHole] = FALSE; - RefPtr->GStatus[GsbSpIntRemapHole] = FALSE; - RefPtr->GStatus[GsbSoftHole] = FALSE; - RefPtr->HoleBase = 0; - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - if (Node >= FirstEnabledNode) { - // Remap memory on nodes with node number larger than the first node that has spared dimms. - NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE; - NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE; - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0); - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - NBPtr[Node].HtMemMapInit (&NBPtr[Node]); - } else { - // No change is needed in the memory map of this node. - // Need to adjust the current system base for other nodes processed later. - NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0; - // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0. - // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base - // and DramMemHoistValid. - // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well - // DramHoleValid. - if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) { - NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0); - } - } - } - - for (Node = 0; Node < MemMainPtr->DieCount; Node++) { - NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]); - RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL); - } - NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]); - } - return RetVal; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmParallelTraining.c deleted file mode 100644 index 03c2f055be..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmParallelTraining.c +++ /dev/null @@ -1,287 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmNodeInterleave.c - * - * Main Memory Feature implementation file for Node Interleaving - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuApicUtilities.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "mu.h" -#include "mfParallelTraining.h" -#include "GeneralServices.h" -#include "heapManager.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE - -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemMParallelTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMParallelTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - DIE_INFO TrainInfo[MAX_NODES_SUPPORTED]; - AP_DATA_TRANSFER ReturnData; - AGESA_STATUS Status; - UINT8 ApSts; - UINT8 Die; - UINT8 Socket; - UINT32 Module; - UINT32 LowCore; - UINT32 HighCore; - UINT32 Time; - UINT32 TimeOut; - UINT32 TargetApicId; - BOOLEAN StillTraining; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT8 *BufferPtr; - BOOLEAN TimeoutEn; - - NBPtr = mmPtr->NBPtr; - MemPtr = mmPtr->MemPtr; - StdHeader = &(mmPtr->MemPtr->StdHeader); - Time = 0; - TimeOut = PARALLEL_TRAINING_TIMEOUT; - TimeoutEn = TRUE; - IDS_TIMEOUT_CTL (&TimeoutEn); - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart parallel training\n"); - AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, StdHeader); - // - // Initialize Training Info Array - // - for (Die = 0; Die < mmPtr->DieCount; Die ++) { - Socket = TrainInfo[Die].Socket = NBPtr[Die].MCTPtr->SocketId; - Module = NBPtr[Die].MCTPtr->DieId; - GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); - TrainInfo[Die].Core = (UINT8) (LowCore & 0x000000FF); - IDS_HDT_CONSOLE (MEM_FLOW, "\tLaunch core %d of socket %d\n", LowCore, Socket); - TrainInfo[Die].Training = FALSE; - } - // - // Start Training on Each remote die. - // - for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { - if (Die != BSP_DIE) { - NBPtr[Die].BeforeDqsTraining (&(mmPtr->NBPtr[Die])); - if (NBPtr[Die].MCTPtr->NodeMemSize != 0) { - if (!NBPtr[Die].FeatPtr->Training (&(mmPtr->NBPtr[Die]))) { - // Fail to launch code on AP - PutEventLog (AGESA_ERROR, MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr[Die].MCTPtr); - if (!MemPtr->ErrorHandling (NBPtr[Die].MCTPtr, EXCLUDE_ALL_DCT, EXCLUDE_ALL_CHIPSEL, &MemPtr->StdHeader)) { - ASSERT (FALSE); - } - } else { - TrainInfo[Die].Training = TRUE; - } - } - } - } - // - // Call training on BSP - // - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NBPtr[BSP_DIE].Node); - NBPtr[BSP_DIE].BeforeDqsTraining (&(mmPtr->NBPtr[BSP_DIE])); - NBPtr[BSP_DIE].TrainingFlow (&(mmPtr->NBPtr[BSP_DIE])); - NBPtr[BSP_DIE].AfterDqsTraining (&(mmPtr->NBPtr[BSP_DIE])); - - // - // Get Results from remote processors training - // - do { - StillTraining = FALSE; - for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { - // - // For each Die that is training, read the status - // - if (TrainInfo[Die].Training == TRUE) { - GetLocalApicIdForCore (TrainInfo[Die].Socket, TrainInfo[Die].Core, &TargetApicId, StdHeader); - ApSts = ApUtilReadRemoteControlByte (TargetApicId, StdHeader); - if ((ApSts & 0x80) == 0) { - // - // Allocate buffer for received data - // - AllocHeapParams.RequestedBufferSize = ( - sizeof (DIE_STRUCT) + - NBPtr[Die].DctCount * ( - sizeof (DCT_STRUCT) + ( - NBPtr[Die].ChannelCount * ( - sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + ( - (NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount * - NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount * - NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ) - ) - ) - ) - ) + 3; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Die, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - // - // Receive Training Results - // - - ReturnData.DataPtr = AllocHeapParams.BufferPtr; - ReturnData.DataSizeInDwords = (UINT16) AllocHeapParams.RequestedBufferSize / 4; - ReturnData.DataTransferFlags = 0; - Status = ApUtilReceiveBuffer (TrainInfo[Die].Socket, TrainInfo[Die].Core, &ReturnData, StdHeader); - if (Status != AGESA_SUCCESS) { - SetMemError (Status, NBPtr[Die].MCTPtr); - } - - BufferPtr = AllocHeapParams.BufferPtr; - LibAmdMemCopy (NBPtr[Die].MCTPtr, BufferPtr, sizeof (DIE_STRUCT), StdHeader); - BufferPtr += sizeof (DIE_STRUCT); - LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData, - BufferPtr, - NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)), - StdHeader); - BufferPtr += NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)); - LibAmdMemCopy ( NBPtr[Die].PSBlock, - BufferPtr, - NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK), - StdHeader); - BufferPtr += NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK); - LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData[0].ChData[0].RcvEnDlys, - BufferPtr, - (NBPtr[Die].DctCount * NBPtr[Die].ChannelCount) * - ((NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount * - NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount * - NUMBER_OF_DELAY_TABLES) + - (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES) - ), - StdHeader); - - HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); - - NBPtr[Die].AfterDqsTraining (&(mmPtr->NBPtr[Die])); - TrainInfo[Die].Training = FALSE; - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA, NBPtr[Die].Node, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, NBPtr[Die].MCTPtr); - ASSERT(FALSE); // Insufficient Heap Space allocation for parallel training buffer - } - } else if (ApSts == CORE_IDLE) { - // AP does not have buffer to transmit to BSP - // AP fails to locate a buffer for data transfer - TrainInfo[Die].Training = FALSE; - } else { - // Signal to loop through again - StillTraining = TRUE; - } - } - } - // Wait for 1 us - MemUWait10ns (100, NBPtr->MemPtr); - Time ++; - } while ((StillTraining) && ((Time < TimeOut) || !TimeoutEn)); // Continue until all Dies are finished - // if cannot finish in 1 s, do fatal exit - - if (StillTraining && TimeoutEn) { - // Parallel training time out, do fatal exit, as there is at least one AP hangs. - PutEventLog (AGESA_FATAL, MEM_ERROR_PARALLEL_TRAINING_TIME_OUT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr); - ASSERT(FALSE); // Timeout occurred while still training - } - - for (Die = 0; Die < mmPtr->DieCount; Die ++ ) { - if (NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { - return FALSE; - } - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmStandardTraining.c deleted file mode 100644 index b126dda809..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmStandardTraining.c +++ /dev/null @@ -1,241 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmStandardTraining.c - * - * Main Memory Feature implementation file for Standard Training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "Porting.h" -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE -/* features */ -#include "mftds.h" -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemMStandardTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -BOOLEAN -MemMStandardTrainingUsingAdjacentDies ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[]; -/* -----------------------------------------------------------------------------*/ -/** - * - * MemMStandardTraining - * - * This function implements standard memory training whereby training functions - * for all nodes are run by the BSP. - * - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMStandardTraining ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - UINT8 Die; - // - // Run Northbridge-specific Standard Training feature for each die. - // - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart serial training\n"); - for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die); - AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader)); - mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]); - mmPtr->NBPtr[Die].Execute1dMaxRdLatTraining = TRUE; - mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]); - mmPtr->NBPtr[Die].TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (mmPtr->NBPtr[Die].TechPtr, NULL); - mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]); - if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { - break; - } - } - return (BOOLEAN) (Die == mmPtr->DieCount); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * MemMStandardTrainingUsingAdjacentDies - * - * This function implements standard memory training whereby training functions - * for all nodes are run by the BSP while enabling other dies to eable argressor channel - * - * - * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemMStandardTrainingUsingAdjacentDies ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ) -{ - UINT8 Die; - UINT8 AdjacentDie; - UINT32 AdjacentSocketNum; - UINT32 TargetSocketNum; - UINT32 ModuleNum; - UINT8 i; - UINT8 Dct; - UINT8 ChipSel; - BOOLEAN FirstCsFound; - // - // Run Northbridge-specific Standard Training feature for each die. - // - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart standard serial training\n"); - for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die); - AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader)); - mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]); - mmPtr->NBPtr[Die].Execute1dMaxRdLatTraining = FALSE; - mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]); - if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { - break; - } - } - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart training with agressors\n"); - for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) { - IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die); - AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader)); - GetSocketModuleOfNode (Die, &TargetSocketNum, &ModuleNum, &(mmPtr->MemPtr->StdHeader)); - for (AdjacentDie = 0; AdjacentDie < mmPtr->DieCount; AdjacentDie++) { - mmPtr->NBPtr[Die].DieEnabled[AdjacentDie] = FALSE; - GetSocketModuleOfNode (AdjacentDie, &AdjacentSocketNum, &ModuleNum, &(mmPtr->MemPtr->StdHeader)); - if (TargetSocketNum == AdjacentSocketNum) { - if (AdjacentDie != Die) { - if (mmPtr->NBPtr[AdjacentDie].MCTPtr->NodeMemSize != 0) { - mmPtr->NBPtr[Die].AdjacentDieNBPtr = &mmPtr->NBPtr[AdjacentDie]; - mmPtr->NBPtr[Die].DieEnabled[AdjacentDie] = TRUE; - } - } else { - if (mmPtr->NBPtr[Die].MCTPtr->NodeMemSize != 0) { - mmPtr->NBPtr[Die].DieEnabled[Die] = TRUE; - } - } - // Determine the initial target CS, Max Dimms and max CS number for all DCTs (potential aggressors) - if (mmPtr->NBPtr[AdjacentDie].MCTPtr->NodeMemSize != 0) { - for (Dct = 0; Dct < mmPtr->NBPtr[AdjacentDie].DctCount; Dct++) { - FirstCsFound = FALSE; - mmPtr->NBPtr[AdjacentDie].SwitchDCT (&mmPtr->NBPtr[AdjacentDie], Dct); - for (ChipSel = 0; ChipSel < mmPtr->NBPtr[AdjacentDie].CSPerChannel (&mmPtr->NBPtr[AdjacentDie]); ChipSel = ChipSel + mmPtr->NBPtr[AdjacentDie].CSPerDelay (&mmPtr->NBPtr[AdjacentDie]) ) { - if ((mmPtr->NBPtr[AdjacentDie].DCTPtr->Timings.CsEnabled & ((UINT16) 1 << ChipSel)) != 0) { - if (FirstCsFound == FALSE) { - // Set Initial CS value for Current Aggressor CS - mmPtr->NBPtr[AdjacentDie].InitialAggressorCSTarget[Dct] = ChipSel; - mmPtr->NBPtr[AdjacentDie].CurrentAggressorCSTarget[Dct] = mmPtr->NBPtr[AdjacentDie].InitialAggressorCSTarget[Dct]; - FirstCsFound = TRUE; - } - mmPtr->NBPtr[AdjacentDie].MaxAggressorCSEnabled[Dct] = ChipSel; - mmPtr->NBPtr[AdjacentDie].MaxAggressorDimms[Dct]++; - } - } - } - } - } - } - if (mmPtr->NBPtr[Die].MCTPtr->NodeMemSize != 0) { - //Execute Technology specific training features - i = 0; - while (memTrainSequenceDDR3[i].TrainingSequenceEnabled != 0) { - if (memTrainSequenceDDR3[i].TrainingSequenceEnabled (&mmPtr->NBPtr[Die])) { - mmPtr->NBPtr[Die].TrainingSequenceIndex = i; - // Execute RdDqs Training - memTrainSequenceDDR3[i].MemTechFeatBlock->RdDqs__Training (mmPtr->NBPtr[Die].TechPtr); - // Execute MaxRdLat Training After training - do { - if (memTrainSequenceDDR3[i].MemTechFeatBlock->MaxRdLatencyTraining (mmPtr->NBPtr[Die].TechPtr)) { - MemFInitTableDrive (&mmPtr->NBPtr[Die], MTAfterMaxRdLatTrn); - } - } while (mmPtr->NBPtr->ChangeNbFrequency (&mmPtr->NBPtr[Die])); - break; - } - i++; - } - } - mmPtr->NBPtr[Die].TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (mmPtr->NBPtr[Die].TechPtr, NULL); - mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]); - if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) { - break; - } - } - return (BOOLEAN) (Die == mmPtr->DieCount); -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c deleted file mode 100644 index 16f59ae385..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c +++ /dev/null @@ -1,246 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmUmaAlloc.c - * - * Main Memory Feature implementation file for UMA allocation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "heapManager.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "Ids.h" -#include "mport.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMUMAALLOC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemMUmaAlloc ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * UMA allocation mechanism. - * - * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK - * - */ -BOOLEAN -MemMUmaAlloc ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ) -{ - UINT32 TOM; - UINT32 TOM2; - UINT32 UmaSize; - UINT32 TopOfChIntlv; - UINT32 DctSelHi; - UINT32 UmaAlignment; - UINT32 UmaAbove4GBase; - UINT32 UmaBelow4GBase; - BOOLEAN DctSelIntLvEn; - BOOLEAN UmaAbove4GEn; - S_UINT64 SMsr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UMA_INFO *UmaInfoPtr; - - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - MEM_PARAMETER_STRUCT *RefPtr; - - MemPtr = MemMainPtr->MemPtr; - NBPtr = &(MemMainPtr->NBPtr[BSP_DIE]); - RefPtr = NBPtr->RefPtr; - - TOM2 = 0; - SMsr.lo = SMsr.hi = 0; - UmaAbove4GBase = 0; - RefPtr->UmaBase = 0; - UmaAlignment = (UINT32) UserOptions.CfgUmaAlignment; - UmaAbove4GEn = UserOptions.CfgUmaAbove4G; - DctSelIntLvEn = (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) ? TRUE : FALSE; - TopOfChIntlv = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr) << (27 - 16); - DctSelHi = NBPtr->GetBitField (NBPtr, BFDctSelHi); - - // Allocate heap for UMA_INFO - AllocHeapParams.RequestedBufferSize = sizeof (UMA_INFO); - AllocHeapParams.BufferHandle = AMD_UMA_INFO_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { - ASSERT(FALSE); // Could not allocate heap for Uma information. - return FALSE; - } - UmaInfoPtr = (UMA_INFO *) AllocHeapParams.BufferPtr; - // Default all the fields of UMA_INFO - UmaInfoPtr->UmaMode = (UINT8) UMA_NONE; - UmaInfoPtr->UmaSize = 0; - UmaInfoPtr->UmaBase = 0; - UmaInfoPtr->UmaAttributes = 0; - UmaInfoPtr->MemClock = NBPtr->DCTPtr->Timings.TargetSpeed; - - switch (RefPtr->UmaMode) { - case UMA_NONE: - UmaSize = 0; - break; - case UMA_SPECIFIED: - UmaSize = RefPtr->UmaSize; - break; - case UMA_AUTO: - UmaSize = NBPtr->GetUmaSize (NBPtr); - break; - default: - UmaSize = 0; - IDS_ERROR_TRAP; - } - - if (UmaSize != 0) { - //TOM scaled from [47:0] to [47:16] - LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); - TOM = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16)); - - UmaBelow4GBase = (TOM - UmaSize) & UmaAlignment; - // Initialize Ref->UmaBase to UmaBelow4GBase - RefPtr->UmaBase = UmaBelow4GBase; - - // Uma Above 4G support - if (UmaAbove4GEn) { - //TOM2 scaled from [47:0] to [47:16] - LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); - TOM2 = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16)); - if (TOM2 != 0) { - UmaAbove4GBase = (TOM2 - UmaSize) & UmaAlignment; - //Set UmaAbove4GBase to 0 if UmaAbove4GBase is below 4GB - if (UmaAbove4GBase < _4GB_RJ16) { - UmaAbove4GBase = 0; - } - if (UmaAbove4GBase != 0) { - RefPtr->UmaBase = UmaAbove4GBase; - // 1. TopOfChIntlv == 0 indicates that whole DCT0 and DCT1 memory are interleaved. - // 2. TopOfChIntlv >= TOM tells us : - // -All or portion of Uma region that above 4G is NOT interleaved. - // -Whole Uma region that below 4G is interleaved. - if (DctSelIntLvEn && (TopOfChIntlv >= TOM)) { - RefPtr->UmaBase = UmaBelow4GBase; - } - } - } - } - - UmaInfoPtr->UmaMode = (UINT8) (RefPtr->UmaMode); - UmaInfoPtr->UmaBase = (UINT64) ((UINT64) RefPtr->UmaBase << 16); - - if (RefPtr->UmaBase >= _4GB_RJ16) { - // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it. - RefPtr->UmaSize = TOM2 - UmaAbove4GBase; - // Uma Typing - MemNSetMTRRUmaRegionUCNb (NBPtr, &UmaAbove4GBase, &TOM2); - if (DctSelIntLvEn && (TopOfChIntlv == 0)) { - UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; - } else { - // Entire UMA region is in the high DCT - UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; - } - } else { - // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it. - RefPtr->UmaSize = TOM - UmaBelow4GBase; - // Uma Typing - NBPtr->UMAMemTyping (NBPtr); - if (DctSelIntLvEn && ((TopOfChIntlv == 0) || (TopOfChIntlv >= TOM))) { - UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; - } else { - if (UmaBelow4GBase >= TopOfChIntlv) { - // Entire UMA region is in the high DCT - UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; - } else if (TopOfChIntlv >= TOM) { - // Entire UMA region is in the low DCT - UmaInfoPtr->UmaAttributes = (DctSelHi == 1) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1; - } else { - // UMA region is in both DCT0 and DCT1 - UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1; - } - } - } - UmaInfoPtr->UmaSize = (RefPtr->UmaSize) << 16; - IDS_HDT_CONSOLE (MEM_FLOW, "UMA is allocated:\n\tBase: %x0000\n\tSize: %x0000\n", RefPtr->UmaBase, RefPtr->UmaSize); - } - - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c deleted file mode 100644 index f202cf1ded..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmflow.c +++ /dev/null @@ -1,395 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmflow.c - * - * Main Memory Flow Entrypoint file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "AdvancedApi.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MMFLOW_FILECODE -/* features */ - -extern MEM_NB_SUPPORT memNBInstalled[]; -extern MEM_TECH_CONSTRUCTOR* memTechInstalled[]; -extern MEM_FEAT_BLOCK_MAIN MemFeatMain; -extern MEM_FLOW_CFG* memFlowControlInstalled[]; - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -MemSPDDataProcess ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function is the main memory configuration function for DR DDR3 - * - * Requirements: - * - * Run-Time Requirements: - * 1. Complete Hypertransport Bus Configuration - * 2. AmdMemInitDataStructDef must be run to set default values - * 3. MSR bit to allow access to high PCI regs set on all nodes - * 4. BSP in Big Real Mode - * 5. Stack available - * 6. MCG_CTL=-1, MC4_EN=0 for all CPUs - * 7. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry - * 8. All var MTRRs reset to zero - * 9. State of NB_CFG.DisDatMsk set properly on all CPUs - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - * @return AGESA_STATUS - * - AGESA_ALERT - * - AGESA_FATAL - * - AGESA_SUCCESS - * - AGESA_WARNING - */ -AGESA_STATUS -AmdMemAuto ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - MEM_SHARED_DATA mmSharedData; - MEM_MAIN_DATA_BLOCK mmData; - MEM_NB_BLOCK *NBPtr; - MEM_TECH_BLOCK *TechPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - AGESA_STATUS Retval; - UINT8 i; - UINT8 Die; - UINT8 DieCount; - UINT8 Tab; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - ASSERT (MemPtr != NULL); - - AGESA_TESTPOINT (TpProcMemAmdMemAuto, &MemPtr->StdHeader); - - IDS_HDT_CONSOLE (MEM_FLOW, "MEM PARAMS:\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBottomIo : %04x\n", MemPtr->ParameterListPtr->BottomIo); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemHoleRemap : %d\n", MemPtr->ParameterListPtr->MemHoleRemapping); - IDS_HDT_CONSOLE (MEM_FLOW, "\tLimitBelow1TB : %d\n", MemPtr->ParameterListPtr->LimitMemoryToBelow1Tb); - IDS_HDT_CONSOLE (MEM_FLOW, "\tUserTimingMode : %d\n", MemPtr->ParameterListPtr->UserTimingMode); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClockValue : %d\n", MemPtr->ParameterListPtr->MemClockValue); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBankIntlv : %d\n", MemPtr->ParameterListPtr->EnableBankIntlv); - IDS_HDT_CONSOLE (MEM_FLOW, "\tNodeIntlv : %d\n", MemPtr->ParameterListPtr->EnableNodeIntlv); - IDS_HDT_CONSOLE (MEM_FLOW, "\tChannelIntlv : %d\n", MemPtr->ParameterListPtr->EnableChannelIntlv); - IDS_HDT_CONSOLE (MEM_FLOW, "\tEccFeature : %d\n", MemPtr->ParameterListPtr->EnableEccFeature); - IDS_HDT_CONSOLE (MEM_FLOW, "\tPowerDown : %d\n", MemPtr->ParameterListPtr->EnablePowerDown); - IDS_HDT_CONSOLE (MEM_FLOW, "\tOnLineSpare : %d\n", MemPtr->ParameterListPtr->EnableOnLineSpareCtl); - IDS_HDT_CONSOLE (MEM_FLOW, "\tParity : %d\n", MemPtr->ParameterListPtr->EnableParity); - IDS_HDT_CONSOLE (MEM_FLOW, "\tBankSwizzle : %d\n", MemPtr->ParameterListPtr->EnableBankSwizzle); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClr : %d\n", MemPtr->ParameterListPtr->EnableMemClr); - IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaMode : %d\n", MemPtr->ParameterListPtr->UmaMode); - IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaSize : %d\n", MemPtr->ParameterListPtr->UmaSize); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemRestoreCtl : %d\n", MemPtr->ParameterListPtr->MemRestoreCtl); - IDS_HDT_CONSOLE (MEM_FLOW, "\tSaveMemContextCtl : %d\n", MemPtr->ParameterListPtr->SaveMemContextCtl); - IDS_HDT_CONSOLE (MEM_FLOW, "\tExternalVrefCtl : %d\n", MemPtr->ParameterListPtr->ExternalVrefCtl ); - IDS_HDT_CONSOLE (MEM_FLOW, "\tForceTrainMode : %d\n\n", MemPtr->ParameterListPtr->ForceTrainMode ); - - //---------------------------------------------------------------------------- - // Get TSC rate, which will be used later in Wait10ns routine - //---------------------------------------------------------------------------- - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &MemPtr->TscRate, &MemPtr->StdHeader); - - //---------------------------------------------------------------------------- - // Read In SPD Data - //---------------------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemBeforeSpdProcessing, &MemPtr->StdHeader); - MemSPDDataProcess (MemPtr); - - //---------------------------------------------------------------- - // Initialize Main Data Block - //---------------------------------------------------------------- - mmData.MemPtr = MemPtr; - mmData.mmSharedPtr = &mmSharedData; - LibAmdMemFill (&mmSharedData, 0, sizeof (mmSharedData), &MemPtr->StdHeader); - mmSharedData.DimmExcludeFlag = NORMAL; - mmSharedData.NodeIntlv.IsValid = FALSE; - //---------------------------------------------------------------- - // Discover populated CPUs - // - //---------------------------------------------------------------- - Retval = MemSocketScan (&mmData); - if (Retval == AGESA_FATAL) { - return Retval; - } - DieCount = mmData.DieCount; - //---------------------------------------------------------------- - // - // Allocate Memory for NB and Tech Blocks - // - // NBPtr[Die]----+ - // | - // V - // +---+---+---+---+---+---+---+---+ - // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | NB Blocks - // +---+---+---+---+---+---+---+---+ - // | | | | | | | | - // | | | | | | | | - // v v v v v v v v - // +---+---+---+---+---+---+---+---+ - // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Tech Blocks - // +---+---+---+---+---+---+---+---+ - // - // - //---------------------------------------------------------------- - AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK) + sizeof (MEM_TECH_BLOCK))); - AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) { - ASSERT(FALSE); // NB and Tech Block Heap allocate error - return AGESA_FATAL; - } - NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr; - TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[DieCount]); - mmData.NBPtr = NBPtr; - mmData.TechPtr = TechPtr; - - //---------------------------------------------------------------- - // Create NB Blocks - // - //---------------------------------------------------------------- - for (Die = 0 ; Die < DieCount ; Die++ ) { - i = 0; - while (memNBInstalled[i].MemConstructNBBlock != 0) { - if (memNBInstalled[i].MemConstructNBBlock (&NBPtr[Die], MemPtr, memNBInstalled[i].MemFeatBlock, &mmSharedData, Die) == TRUE) { - break; - } - i++; - } - // Couldn't find a NB which supported this family - if (memNBInstalled[i].MemConstructNBBlock == 0) { - return AGESA_FATAL; - } - } - //---------------------------------------------------------------- - // Create Technology Blocks - // - //---------------------------------------------------------------- - for (Die = 0 ; Die < DieCount ; Die++ ) { - i = 0; - while (memTechInstalled[i] != NULL) { - if (memTechInstalled[i] (&TechPtr[Die], &NBPtr[Die])) { - NBPtr[Die].TechPtr = &TechPtr[Die]; - break; - } - i++; - } - // Couldn't find a Tech block which supported this family - if (memTechInstalled[i] == NULL) { - return AGESA_FATAL; - } - } - //---------------------------------------------------------------- - // - // MEMORY INITIALIZATION TASKS - // - //---------------------------------------------------------------- - i = 0; - while (memFlowControlInstalled[i] != NULL) { - Retval = memFlowControlInstalled[i] (&mmData); - if (MemPtr->IsFlowControlSupported == TRUE) { - break; - } - i++; - } - - //---------------------------------------------------------------- - // Deallocate NB register tables - //---------------------------------------------------------------- - for (Tab = 0; Tab < NumberOfNbRegTables; Tab++) { - HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Tab, 0, 0), &MemPtr->StdHeader); - } - - //---------------------------------------------------------------- - // Check for errors and return - //---------------------------------------------------------------- - AGESA_TESTPOINT (TpProcMemEnd, &MemPtr->StdHeader); - for (Die = 0; Die < DieCount; Die++) { - if (NBPtr[Die].MCTPtr->ErrCode > Retval) { - Retval = NBPtr[Die].MCTPtr->ErrCode; - } - } - return Retval; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function fills a default SPD buffer with SPD values for all DIMMs installed in the system - * - * The SPD Buffer is populated with a Socket-Channel-Dimm centric view of the Dimms. At this - * point, the Memory controller type is not known, and the platform BIOS does not know the anything - * about which DIMM is on which DCT. So the DCT relationship is abstracted from the arrangement - * of SPD information here. We use the utility functions GetSpdSocketIndex(), GetMaxChannelsPerSocket(), - * and GetMaxDimmsPerChannel() to Map the SPD data according to which Socket-relative channel the DIMMs - * are connected to. The functions rely on either the maximum values in the - * PlatformSpecificOverridingTable or if unspecified, the absolute maximums in AGESA.H. - * - * This mapping is translated in the Northbridge object Constructor and the Technology block constructor. - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - */ - -VOID -STATIC -MemSPDDataProcess ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT8 Socket; - UINT8 Channel; - UINT8 Dimm; - UINT8 DimmIndex; - UINT32 AgesaStatus; - UINT8 MaxSockets; - UINT8 MaxChannelsPerSocket; - UINT8 MaxDimmsPerChannel; - SPD_DEF_STRUCT *DimmSPDPtr; - PSO_TABLE *PsoTable; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - AGESA_READ_SPD_PARAMS SpdParam; - - ASSERT (MemPtr != NULL); - MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ()); - PsoTable = MemPtr->ParameterListPtr->PlatformMemoryConfiguration; - // - // Allocate heap for the table - // - AllocHeapParams.RequestedBufferSize = (GetSpdSocketIndex (PsoTable, MaxSockets, &MemPtr->StdHeader) * sizeof (SPD_DEF_STRUCT)); - AllocHeapParams.BufferHandle = AMD_MEM_SPD_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) { - MemPtr->SpdDataStructure = (SPD_DEF_STRUCT *) AllocHeapParams.BufferPtr; - // - // Initialize SpdParam Structure - // - LibAmdMemCopy ((VOID *)&SpdParam, (VOID *)MemPtr, (UINTN)sizeof (SpdParam.StdHeader), &MemPtr->StdHeader); - // - // Populate SPDDataBuffer - // - SpdParam.MemData = MemPtr; - DimmIndex = 0; - for (Socket = 0; Socket < (UINT16)MaxSockets; Socket++) { - MaxChannelsPerSocket = GetMaxChannelsPerSocket (PsoTable, Socket, &MemPtr->StdHeader); - SpdParam.SocketId = Socket; - for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { - SpdParam.MemChannelId = Channel; - MaxDimmsPerChannel = GetMaxDimmsPerChannel (PsoTable, Socket, Channel); - for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++) { - SpdParam.DimmId = Dimm; - DimmSPDPtr = &(MemPtr->SpdDataStructure[DimmIndex++]); - SpdParam.Buffer = DimmSPDPtr->Data; - AGESA_TESTPOINT (TpProcMemBeforeAgesaReadSpd, &MemPtr->StdHeader); - AgesaStatus = AgesaReadSpd (0, &SpdParam); - AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader); - if (AgesaStatus == AGESA_SUCCESS) { - DimmSPDPtr->DimmPresent = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, (intptr_t)SpdParam.Buffer); - } else { - DimmSPDPtr->DimmPresent = FALSE; - } - } - } - } - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, 0, 0, 0, 0, &MemPtr->StdHeader); - // - // Assert here if unable to allocate heap for SPDs - // - IDS_ERROR_TRAP; - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.c deleted file mode 100644 index 00e1308052..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.c +++ /dev/null @@ -1,256 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * HyperTransport features and sequence implementation. - * - * Implements the external AmdHtInitialize entry point. - * Contains routines for directing the sequence of available features. - * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be - * contained in this file, and not in the feature code. - * - * From a build option perspective, it may be that a few lines could be removed - * from compilation in this file for certain options. It is considered that - * the code savings from this are too small to be of concern and this file - * should not have any explicit build option implementation. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "mu.h" -#include "Filecode.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -VOID -MemUWriteCachelines ( - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -MemUReadCachelines ( - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -MemUDummyCLRead ( - IN UINT32 Address - ); - -VOID -MemUMFenceInstr ( - VOID - ); - -VOID -MemUFlushPattern ( - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -AlignPointerTo16Byte ( - IN OUT UINT8 **BufferPtrPtr - ); -*/ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - - - -//---------------------------------------------------------------------------- - -VOID -MemUWriteCachelines ( - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - UINTN Index; - CHAR8 *Position; - __m128i *Src = (void *) Pattern; - __m128i *Dest = (void *) (size_t)Address; - - Position = (void *) Pattern; - - // ssd - important: without this, the src data may get evicted from cache - _mm_mfence (); - - for (Index = 0; Index < ClCount * 4; Index++){ - _mm_stream_si128_fs (Dest, Src); - Src++; - Dest++; - } - - // ssd - might not be required, but no measurable boot time impact - _mm_mfence (); -} - - -//---------------------------------------------------------------------------- -// MemUReadCachelines: -// -// Read a pattern of 72 bit times (per DQ), to test dram functionality. The -// pattern is a stress pattern which exercises both ISI and crosstalk. The number -// of cache lines to fill is dependent on DCT width mode and burstlength. -// -// In: Buffer - pointer to a buffer where read data will be stored -// Address - Physical address to be read -// ClCount - number of cachelines to be read - -VOID -MemUReadCachelines ( - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - UINTN Index; - UINT32 *Dest; - - for (Index = 0; Index < ClCount * 16; Index++) { - Dest = (void *) &Buffer [Index * 4]; - *Dest = __readfsdword (Address + Index * 4); - _mm_mfence (); - } -} - -//---------------------------------------------------------------------------- -// MemUDummyCLRead: -// -// Perform a single cache line read from a given physical address. -// -// In: Address - Physical address to be read -// ClCount - number of cachelines to be read - -//FUNC_ATTRIBUTE (noinline) -VOID -MemUDummyCLRead ( - IN UINT32 Address - ) -{ - _mm_sfence (); - __readfsbyte (Address); -} - -//---------------------------------------------------------------------------- - -VOID -MemUMFenceInstr ( - VOID - ) -{ - _mm_mfence (); -} - -//---------------------------------------------------------------------------- -// MemUFlushPattern: -// -// Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used -// to ensure cache miss on the next read training. -// -// In: Address - Physical address to be flushed -// ClCount - number of cachelines to be flushed -//FUNC_ATTRIBUTE(noinline) -VOID -MemUFlushPattern ( - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - UINTN Index; - - // ssd - theory: a tlb flush is needed to avoid problems with clflush - __writemsr (0x20F, __readmsr (0x20F)); - - for (Index = 0; Index < ClCount; Index++) { - // mfence prevents speculative execution of the clflush - _mm_mfence (); - _mm_clflush_fs ((void *) (size_t) (Address + Index * 64)); - } -} - -//---------------------------------------------------------------------------- - -//FUNC_ATTRIBUTE(noinline) -VOID -AlignPointerTo16Byte ( - IN OUT UINT8 **BufferPtrPtr - ) -{ - size_t Address = (size_t) *BufferPtrPtr; - Address += 15; - Address -= Address % 16; - *BufferPtrPtr = (void *) Address; -} - -//---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c deleted file mode 100644 index 84a1c81ba7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c +++ /dev/null @@ -1,721 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * muc.c - * - * Utility functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "cpuServices.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Ids.h" -#include "mport.h" -#include "mu.h" -#include "cpuFamilyTranslation.h" -#include "cpuCacheInit.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_MAIN_MUC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -CONST UINT32 Pattern2[16] = { - 0x12345678, 0x87654321, 0x23456789, 0x98765432, - 0x59385824, 0x30496724, 0x24490795, 0x99938733, - 0x40385642, 0x38465245, 0x29432163, 0x05067894, - 0x12349045, 0x98723467, 0x12387634, 0x34587623 -}; - -CONST UINT32 MaxLatPat[48] = { - 0x6E0E3FAC, 0x0C3CFF52, - 0x4A688181, 0x49C5B613, - 0x7C780BA6, 0x5C1650E3, - 0x0C4F9D76, 0x0C6753E6, - 0x205535A5, 0xBABFB6CA, - 0x610E6E5F, 0x0C5F1C87, - 0x488493CE, 0x14C9C383, - 0xF5B9A5CD, 0x9CE8F615, - - 0xAAD714B5, 0xC38F1B4C, - 0x72ED647C, 0x669F7562, - 0x5233F802, 0x4A898B30, - 0x10A40617, 0x3326B465, - 0x55386E04, 0xC807E3D3, - 0xAB49E193, 0x14B4E63A, - 0x67DF2495, 0xEA517C45, - 0x7624CE51, 0xF8140C51, - - 0x4824BD23, 0xB61DD0C9, - 0x072BCFBE, 0xE8F3807D, - 0x919EA373, 0x25E30C47, - 0xFEB12958, 0x4DA80A5A, - 0xE9A0DDF8, 0x792B0076, - 0xE81C73DC, 0xF025B496, - 0x1DB7E627, 0x808594FE, - 0x82668268, 0x655C7783 -}; - -CONST UINT8 PatternJD[9] = {0x44, 0xA6, 0x38, 0x4F, 0x4B, 0x2E, 0xEF, 0xD5, 0x54}; - -CONST UINT8 PatternJD_256[256] = { - 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, - 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, - 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, - 0xFF, 0xFF, 0x00, 0xF7, 0x08, 0xF7, 0x00, 0xFF, - 0x00, 0xF7, 0x00, 0xFF, 0x00, 0xF7, 0x00, 0xF7, - 0x08, 0xF7, 0x08, 0xFF, 0x00, 0xFF, 0x08, 0xFF, - 0x00, 0xFF, 0x08, 0xFF, 0x08, 0xF7, 0xFB, 0x04, - 0xFB, 0xFB, 0x04, 0xFB, 0xFB, 0xFB, 0x04, 0xFB, - 0xFB, 0xFB, 0xFB, 0x04, 0xFB, 0x04, 0x04, 0xFB, - 0x04, 0x04, 0x04, 0xFB, 0x04, 0x04, 0x04, 0x04, - 0xFB, 0x7F, 0x80, 0x7F, 0x00, 0xFF, 0x00, 0x7F, - 0x00, 0xFF, 0x00, 0x7F, 0x00, 0x7F, 0x80, 0x7F, - 0x80, 0xFF, 0x00, 0xFF, 0x80, 0xFF, 0x00, 0xFF, - 0x80, 0xFF, 0x80, 0x7F, 0xBF, 0x40, 0xBF, 0xBF, - 0x40, 0xBF, 0xBF, 0xBF, 0x40, 0xBF, 0xBF, 0xBF, - 0xBF, 0x40, 0xBF, 0x40, 0x40, 0xBF, 0x40, 0x40, - 0x40, 0xBF, 0x40, 0x40, 0x40, 0x40, 0xBF, 0xFD, - 0x02, 0xFD, 0x00, 0xFF, 0x00, 0xFD, 0x00, 0xFF, - 0x00, 0xFD, 0x00, 0xFD, 0x02, 0xFD, 0x02, 0xFF, - 0x00, 0xFF, 0x02, 0xFF, 0x00, 0xFF, 0x02, 0xFF, - 0x02, 0xFD, 0xFE, 0x01, 0xFE, 0xFE, 0x01, 0xFE, - 0xFE, 0xFE, 0x01, 0xFE, 0xFE, 0xFE, 0xFE, 0x01, - 0xFE, 0x01, 0x01, 0xFE, 0x01, 0x01, 0x01, 0xFE, - 0x01, 0x01, 0x01, 0x01, 0xFE, 0xDF, 0x20, 0xDF, - 0x00, 0xFF, 0x00, 0xDF, 0x00, 0xFF, 0x00, 0xDF, - 0x00, 0xDF, 0x20, 0xDF, 0x20, 0xFF, 0x00, 0xFF, - 0x20, 0xFF, 0x00, 0xFF, 0x20, 0xFF, 0x20, 0xDF, - 0xEF, 0x10, 0xEF, 0xEF, 0x10, 0xEF, 0xEF, 0xEF, - 0x10, 0xEF, 0xEF, 0xEF, 0xEF, 0x10, 0xEF, 0x10, - 0x10, 0xEF, 0x10, 0x10, 0x10, 0xEF, 0x10, 0x10, - 0x10, 0x10, 0xEF, 0xF7, 0x00, 0xFF, 0x04, 0x7F, - 0x00, 0xFF, 0x40, 0xFD, 0x00, 0xFF, 0x01, 0xDF -}; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the (index)th UINT8 - * from an indicated test pattern. - * - * @param[in] Pattern - encoding of test pattern type - * @param[in] Buffer[] - buffer to be filled - * @param[in] Size - Size of the buffer - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUFillTrainPattern ( - IN TRAIN_PATTERN Pattern, - IN UINT8 Buffer[], - IN UINT16 Size - ) -{ - UINT8 Result; - UINT8 i; - UINT8 Mask; - UINT16 Index; - UINT16 k; - - for (Index = 0; Index < Size; Index++) { - k = Index; - // get one byte from Pattern - switch (Pattern) { - case TestPattern0: - Result = 0xAA; - break; - case TestPattern1: - Result = 0x55; - break; - case TestPattern2: - ASSERT (Index < sizeof (Pattern2)); - Result = ((UINT8 *)Pattern2)[Index]; - break; - case TestPatternML: - if (Size != 6 * 64) { - Result = ((UINT8 *)MaxLatPat)[Index]; - } else { - Result = ((UINT8 *)MaxLatPat)[Index & 0xF7]; - } - break; - case TestPatternJD256B: - k >>= 1; - // break is not being used here because TestPatternJD256B also need - // to run TestPatternJD256A sequence. - case TestPatternJD256A: - k >>= 3; - ASSERT (k < sizeof (PatternJD_256)); - Result = PatternJD_256[k]; - break; - case TestPatternJD1B: - k >>= 1; - // break is not being used here because TestPatternJD1B also need - // to run TestPatternJD1A sequence. - case TestPatternJD1A: - k >>= 3; - i = (UINT8) (k >> 3); - Mask = (UINT8) (0x80 >> (k & 7)); - - if (i == 0) { - Result = 0; - } else { - Result = (UINT16)1 << (i - 1); - } - - ASSERT (i < sizeof (PatternJD)); - if (PatternJD[i] & Mask) { - Result = ~Result; - } - break; - case TestPattern3: - Result = 0x36; - break; - case TestPattern4: - Result = 0xC9; - break; - default: - Result = 0; - IDS_ERROR_TRAP; - } - - // fill in the Pattern buffer - Buffer[Index] = Result; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function flushes cache lines - * - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] ClCount - Number of cache lines - * @param[in] Address - System Address [47:16] - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUProcIOClFlush ( - IN UINT32 Address, - IN UINT16 ClCount, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - MemUSetTargetWTIO (Address, MemPtr); - MemUFlushPattern (MemUSetUpperFSbase (Address, MemPtr), ClCount); - MemUResetTargetWTIO (MemPtr); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector. - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] Address - System Address [47:16] - * - * @return Address - Lowest 32-bit of physical address - * ---------------------------------------------------------------------------- - */ - -UINT32 -MemUSetUpperFSbase ( - IN UINT32 Address, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - S_UINT64 SMsr; - - SMsr.lo = 0; - SMsr.hi = Address >> 16; - LibAmdMsrWrite (FS_BASE, (UINT64 *)&SMsr, &MemPtr->StdHeader); - return Address << 16; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function resets the target address space to Write Through IO by disabling IORRs - * - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUResetTargetWTIO ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - S_UINT64 SMsr; - SMsr.hi = 0; - SMsr.lo = 0; - LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the target range to WT IO (using an IORR overlapping - * the already existing - * - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] Address - System Address [47:16] - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUSetTargetWTIO ( - IN UINT32 Address, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - S_UINT64 SMsr; - - SMsr.lo = Address << 16; - SMsr.hi = Address >> 16; - LibAmdMsrWrite (IORR0_BASE,(UINT64 *)&SMsr, &MemPtr->StdHeader); // IORR0 Base - SMsr.hi = 0xFFFF; - SMsr.lo = 0xFC000800; - LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 64MB Mask -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Waits specified number of 10ns cycles - * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE - * @param[in] Count - Number of 10ns cycles to wait; Note that Count must not exceed 1000000 - * - * ---------------------------------------------------------------------------- - */ - -VOID -MemUWait10ns ( - IN UINT32 Count, - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT64 TargetTsc; - UINT64 CurrentTsc; - - ASSERT (Count <= 1000000); - - MemUMFenceInstr (); - - LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); - TargetTsc = CurrentTsc + ((Count * MemPtr->TscRate + 99) / 100); - do { - LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); - } while (CurrentTsc < TargetTsc); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Find the entry of platform specific overriding table. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] EntryType - Entry type - * @param[in] SocketID - Physical socket ID - * @param[in] ChannelID - Physical channel ID - * @param[in] DimmID - Physical Dimm ID - * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID - * @param[in,out] *StdHeader - Pointer of AMD_CONFIG_PARAMS - * - If both *LogicalIdPtr and *StdHeader are "NULL" input, - * that means, the "EntryType" are not CPU family dependent, - * ex. PSO_MAX_DIMMS for NUMBER_OF_DIMMS_SUPPORTED macro. - * - * - * @return NULL - entry could not be found. - * @return Pointer - points to the entry's data. - * - * ---------------------------------------------------------------------------- - */ - -VOID * -FindPSOverrideEntry ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN PSO_ENTRY EntryType, - IN UINT8 SocketID, - IN UINT8 ChannelID, - IN UINT8 DimmID, - IN CPU_LOGICAL_ID *LogicalIdPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *Buffer; - CPU_LOGICAL_ID LogicalCpuId; - UINT32 RawCpuId; - - LogicalCpuId.Family = AMD_FAMILY_UNKNOWN; - LogicalCpuId.Revision = 0; - RawCpuId = 0; - - Buffer = PlatformMemoryConfiguration; - // - // Do not need to look for CPU family specific PSO if LogicalIdPtr and StdHeader are NULL. - // - if ((LogicalIdPtr != NULL) && (StdHeader != NULL)) { - // - // Looking for the CPU family signature followed by CPUID value. - // And check to see if the CPUID value is matched with current CPU's : - // - If matched, Buffer points to following PSO macros' start address. - // - If not matched, Buffer points to PlatformMemoryConfiguration for global PSO parsing. - // - while (Buffer[0] != PSO_END) { - if (Buffer[0] == PSO_CPU_FAMILY_TO_OVERRIDE) { - RawCpuId = *(UINT32 *)&Buffer[2]; - GetLogicalIdFromCpuid (RawCpuId, &LogicalCpuId, StdHeader); - if ((LogicalCpuId.Family & LogicalIdPtr->Family) != 0) { - if ((LogicalCpuId.Revision & LogicalIdPtr->Revision) != 0) { - Buffer += Buffer[1] + 2; - break; - } - } - } - Buffer += Buffer[1] + 2; - } - // - // If no CPU family specific PSO macros exist, Buffer points to PlatformMemoryConfiguration again - // - if (Buffer[0] == PSO_END) { - Buffer = PlatformMemoryConfiguration; - } - } - - while ((Buffer[0] != PSO_END) && (Buffer[0] != PSO_CPU_FAMILY_TO_OVERRIDE)) { - if (Buffer[0] == EntryType) { - if ((Buffer[2] & ((UINT8) 1 << SocketID)) != 0 ) { - if ((Buffer[3] & ((UINT8) 1 << ChannelID)) != 0 ) { - if ((Buffer[4] & ((UINT8) 1 << DimmID)) != 0 ) { - return &Buffer[5]; - } - } - } - } - Buffer += Buffer[1] + 2; - } - - return NULL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the max dimms for a given memory channel on a given - * processor. It first searches the platform override table for the max dimms - * value. If it is not provided, the AGESA default value is returned. The target - * socket must be a valid present socket. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor that owns the channel - * @param[in] ChannelID - Channel to get max dimms for - * - * - * @return UINT8 - Max Number of Dimms for that channel - */ -UINT8 -GetMaxDimmsPerChannel ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID - ) -{ - UINT8 *DimmsPerChPtr; - UINT8 MaxDimmPerCH; - - DimmsPerChPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmPerCH = *DimmsPerChPtr; - } else { - MaxDimmPerCH = MAX_DIMMS_PER_CHANNEL; - } - // Maximum number of dimms per channel cannot be larger than its default value. - ASSERT (MaxDimmPerCH <= MAX_DIMMS_PER_CHANNEL); - - return MaxDimmPerCH; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the max memory channels on a given processor. - * It first searches the platform override table for the max channels value. - * If it is not provided, the AGESA default value is returned. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] StdHeader - Header for library and services - * - * - * @return UINT8 - Max Number of Channels on that Processor - */ -UINT8 -GetMaxChannelsPerSocket ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *ChannelsPerSocketPtr; - UINT8 MaxChannelsPerSocket; - - if (IsProcessorPresent (SocketID, StdHeader)) { - ChannelsPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHNLS, SocketID, 0, 0, NULL, NULL); - if (ChannelsPerSocketPtr != NULL) { - MaxChannelsPerSocket = *ChannelsPerSocketPtr; - } else { - MaxChannelsPerSocket = MAX_CHANNELS_PER_SOCKET; - } - // Maximum number of channels per socket cannot be larger than its default value. - ASSERT (MaxChannelsPerSocket <= MAX_CHANNELS_PER_SOCKET); - } else { - MaxChannelsPerSocket = 0; - } - - return MaxChannelsPerSocket; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the max number of chip select on a given channel of - * a given processor. It first searches the platform override table for the max - * chip select value. If it is not provided, the AGESA default value is returned. - * The target socket must be a valid present socket. - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] ChannelID - ID of a channel - * - * - * @return UINT8 - Max Number of chip selects on the channel of the Processor - */ -UINT8 -GetMaxCSPerChannel ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID - ) -{ - UINT8 *CSPerSocketPtr; - UINT8 MaxCSPerChannel; - - CSPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHIPSELS, SocketID, ChannelID, 0, NULL, NULL); - if (CSPerSocketPtr != NULL) { - MaxCSPerChannel = *CSPerSocketPtr; - } else { - MaxCSPerChannel = MAX_CS_PER_CHANNEL; - } - // Max chip select per channel cannot be larger than its default value - ASSERT (MaxCSPerChannel <= MAX_CS_PER_CHANNEL); - - return MaxCSPerChannel; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the index of the first Dimm SPD structure for a - * given processor socket. It checks the Max Dimms per channel for every memory - * channel on every processor up to the current one, and adds them together. - * - * This function may also be used to calculate the maximum dimms per system - * by passing the total number of dimm sockets - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] StdHeader - Header for library and services - * - * @return UINT8 - SPD Index - */ -UINT8 -GetSpdSocketIndex ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 SpdSocketIndex; - UINT8 Socket; - UINT8 Channel; - UINT8 MaxChannelsPerSocket; - - SpdSocketIndex = 0; - for (Socket = 0; Socket < SocketID; Socket++) { - MaxChannelsPerSocket = GetMaxChannelsPerSocket (PlatformMemoryConfiguration, Socket, StdHeader); - for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) { - SpdSocketIndex = SpdSocketIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, Socket, Channel); - } - } - return SpdSocketIndex; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the index of the first Dimm SPD structure for a - * given channel relative to the processor socket. It checks the Max Dimms per - * channel for every memory channel on that processor up to the current one, - * and adds them together. - * - * This function may also be used to calculate the maximum dimms per system - * by passing the total number of DIMM sockets - * - * @param[in] PlatformMemoryConfiguration - Platform config table - * @param[in] SocketID - ID of the processor - * @param[in] ChannelID - ID of the Channel - * @param[in] StdHeader - Header for library and services - * - * @return UINT8 - SPD Index - */ -UINT8 -GetSpdChannelIndex ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 SpdChannelIndex; - UINT8 Channel; - - SpdChannelIndex = 0; - ASSERT (ChannelID < GetMaxChannelsPerSocket (PlatformMemoryConfiguration, SocketID, StdHeader)) - for (Channel = 0; Channel < ChannelID; Channel++) { - SpdChannelIndex = SpdChannelIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, SocketID, Channel); - } - return SpdChannelIndex; -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function returns the upper 32 bits mask for variable MTRR based on - * the CPU_LOGICAL_ID. - * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID - * @param[in] StdHeader - Header for library and services - * - * @return UINT32 - MTRR mask for upper 32 bits - * - */ -UINT32 -GetVarMtrrHiMsk ( - IN CPU_LOGICAL_ID *LogicalIdPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 TempNotCare; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - CONST CACHE_INFO *CacheInfoPtr; - - GetCpuServicesFromLogicalId (LogicalIdPtr, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &TempNotCare, StdHeader); - return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32); -} - - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function returns number of memclk converted from ns - * @param[in] Speed - memclk frequency - * @param[in] NumberOfns - number of ns to be converted - * - * @return UINT32 - number of memclk - * - */ -UINT32 -MemUnsToMemClk ( - IN MEMORY_BUS_SPEED Speed, - IN UINT32 NumberOfns - ) -{ - return (UINT32) ((NumberOfns * Speed + 999) / 1000); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/Makefile.inc deleted file mode 100644 index 4a99c81f3d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -libagesa-y += mnParTrainc32.c -libagesa-y += mnS3c32.c -libagesa-y += mnc32.c -libagesa-y += mndctc32.c -libagesa-y += mnflowc32.c -libagesa-y += mnidendimmc32.c -libagesa-y += mnmctc32.c -libagesa-y += mnotc32.c -libagesa-y += mnphyc32.c -libagesa-y += mnprotoc32.c -libagesa-y += mnregc32.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnParTrainc32.c deleted file mode 100644 index c04438339b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnParTrainc32.c +++ /dev/null @@ -1,228 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnParTrainc32.c - * - * Feature which performs Memory DQS training on each node with each node training - * its own memory through code running on a core in the associated processor. - * This way memory can be trained in parallel by more than one processor. - * - * This file contains the C32 specific parallel training function. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 54775 $ @e \$Date: 2011-06-12 21:05:26 -0600 (Sun, 12 Jun 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnc32.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemFParallelTrainingC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -STATIC -MemConstructRemoteNBBlockC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN DIE_STRUCT *MCTPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr -); -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the training function which set up the environment for remote - * training on the ap and launches the remote routine. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Launch training on AP successfully. - * @return FALSE - Fail to launch training on AP. - */ -BOOLEAN -MemFParallelTrainingC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - DIE_STRUCT *MCTPtr; - REMOTE_TRAINING_ENV *EnvPtr; - AP_TASK TrainingTask; - UINT8 Socket; - UINT8 Module; - UINT8 APCore; - UINT8 p; - UINT32 LowCore; - UINT32 HighCore; - UINT32 BspSocket; - UINT32 BspModule; - UINT32 BspCore; - AGESA_STATUS Status; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT16 MctDataSize; - StdHeader = &(NBPtr->MemPtr->StdHeader); - MCTPtr = NBPtr->MCTPtr; - Socket = MCTPtr->SocketId; - Module = MCTPtr->DieId; - - // - // Allocate buffer for REMOTE_TRAINING_ENV - // - MctDataSize = MAX_DCTS_PER_NODE_C32 * ( - sizeof (DCT_STRUCT) + ( - MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) - ) - ); - AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); - - // - // Setup Remote training environment - // - LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; - } - EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; - EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockC32; - EnvPtr->FeatPtr = NBPtr->FeatPtr; - EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; - EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; - EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize; - EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; - EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; - EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; - - LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); - - // - // Get Socket, Core of the BSP - // - IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); - EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); - EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); - - // - // Set up the remote task structure - // - TrainingTask.DataTransfer.DataPtr = EnvPtr; - TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4; - TrainingTask.DataTransfer.DataTransferFlags = 0; - TrainingTask.ExeFlags = 0; - TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; - - // - // Get Target AP Core - // - GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); - APCore = (UINT8) (LowCore & 0x000000FF); - - // - // Launch Remote Training - // - ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); - - HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); - - return TRUE; - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" - return FALSE; - } -} - -BOOLEAN -STATIC -MemConstructRemoteNBBlockC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN DIE_STRUCT *MCTPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - NBPtr->MCTPtr = MCTPtr; - NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; - - MemNInitNBDataC32 (NBPtr); - - FeatPtr->InitCPG (NBPtr); - NBPtr->FeatPtr = FeatPtr; - FeatPtr->InitHwRxEn (NBPtr); - MemNSwitchDCTNb (NBPtr, 0); - - //---------------------------------------------------------------------------- - // Get TSC rate of the this AP - //---------------------------------------------------------------------------- - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.c deleted file mode 100644 index fda4f405e5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.c +++ /dev/null @@ -1,746 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mns3c32.c - * - * C32 memory specific function to support S3 resume - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 59560 $ @e \$Date: 2011-09-26 11:43:44 -0600 (Mon, 26 Sep 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "mnc32.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "mnS3c32.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_NB_C32_MNS3C32_FILECODE - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemS3ResumeConstructNBBlockC32 ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -UINT16 -STATIC -MemNS3GetRegLstPtrC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ); - -AGESA_STATUS -STATIC -MemNS3GetDeviceRegLstC32 ( - IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader - ); - -VOID -STATIC -MemNS3SetSpecialPCIRegC32 ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -STATIC -MemNS3ExitSelfRefRegC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -PCI_SPECIAL_CASE PciSpecialCaseFuncC32[] = { - {MemNS3GetCSRNb, MemNS3SetCSRNb}, - {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegC32}, - {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} -}; - -PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorC32[] = { - {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, - {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, - {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, - {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, - {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, - {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, - {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, - {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, - {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, - {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, - {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, - {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} -}; - -CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefC32 = { - 0, - (sizeof (S3PciPreSelfRefDescriptorC32) / sizeof (PCI_REG_DESCRIPTOR)), - S3PciPreSelfRefDescriptorC32, - NULL -}; - -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorC32[] = { - // DCT 0 - {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0xA4, 0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - //errata 322 - {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - //errata 263 - {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - - // DCT 1 - {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - // errata 322 - {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - // errata 263 - {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - - // Restore F2x[1,0]94 right before exit self refresh - {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} -}; - -CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefC32 = { - 0, - (sizeof (S3CPciPreSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), - S3CPciPreSelfDescriptorC32, - PciSpecialCaseFuncC32 -}; - -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorC32[] = { - // DCT0 - {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - - // DCT1 - {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - - // DllShutDown - {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, - - // Restore scrubber related registers after restoring training related registers - {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK} -}; - -CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefC32 = { - 0, - (sizeof (S3CPciPostSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), - S3CPciPostSelfDescriptorC32, - PciSpecialCaseFuncC32 -}; - -MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorC32[] = { - {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, - {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, - {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, - {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} -}; - -CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefC32 = { - 0, - (sizeof (S3MSRPreSelfRefDescriptorC32) / sizeof (MSR_REG_DESCRIPTOR)), - S3MSRPreSelfRefDescriptorC32, - NULL -}; - -VOID *MemS3RegListC32[] = { - (VOID *)&S3PciPreSelfRefC32, - NULL, - (VOID *)&S3CPciPreSelfRefC32, - (VOID *)&S3CPciPostSelfRefC32, - (VOID *)&S3MSRPreSelfRefC32, - NULL, - NULL, - NULL -}; - -CONST UINT16 ROMDATA SpecialCasePCIRegC32[] = { - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) -}; -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for S3 resume - * - * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. - * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. - * @param[in] NodeID - Node ID of the target node. - * - * @return BOOLEAN - * TRUE - This is the correct constructor for the targeted node. - * FALSE - This isn't the correct constructor for the targeted node. - */ - -BOOLEAN -MemS3ResumeConstructNBBlockC32 ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - INT32 i; - MEM_NB_BLOCK *NBPtr; - - NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->MemPtr = MemPtr; - NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; - InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable); - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Dct = 0; - NBPtr->Channel = 0; - NBPtr->Ganged = FALSE; - NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32; - NBPtr->DctCount = MAX_DCTS_PER_NODE_C32; - - for (i = 0; i < EnumSize; i++) { - NBPtr->IsSupported[i] = FALSE; - } - - for (i = 0; i < NumberOfHooks; i++) { - NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; - } - - LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); - - NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; - NBPtr->SwitchDCT = MemNSwitchDCTNb; - NBPtr->SwitchChannel = MemNSwitchChannelNb; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->SetBitField = MemNSetBitFieldNb; - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32; - NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedC32; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegC32; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrC32; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstC32; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)) * sizeof (UINT32); - - MemNSwitchDCTNb (NBPtr, 0); - - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the register list for each device for C32 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP - * @return UINT16 - size of the device descriptor on the target node. - */ -UINT16 -STATIC -MemNS3GetRegLstPtrC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ) -{ - UINT8 i; - UINT16 Size; - Size = 0; - for (i = PRESELFREF; i <= POSTSELFREF; i ++) { - DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); - DescriptPtr->PCIDevice[i].Node = NBPtr->Node; - DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; - if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[PCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { - DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_C32 + i; - Size += sizeof (PCI_DEVICE_DESCRIPTOR); - } - DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); - DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; - DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; - if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CPCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { - DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_C32 + i; - Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); - } - DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); - DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; - if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[MSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { - DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_C32 + i; - Size += sizeof (MSR_DEVICE_DESCRIPTOR); - } - DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); - DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; - if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CMSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { - DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_C32 + i; - Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); - } - } - return Size; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function return the register list according to the register ID. - * - * @param[in] RegisterLstID - value of the Register list ID. - * @param[out] **RegisterHeader - pointer to the address of the register list. - * @return none - */ -AGESA_STATUS -STATIC -MemNS3GetDeviceRegLstC32 ( - IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader - ) -{ - if (RegisterLstID >= (sizeof (MemS3RegListC32) / sizeof (VOID *))) { - ASSERT(FALSE); // RegisterListID exceeded size of Register list - return AGESA_FATAL; - } - if (MemS3RegListC32[RegisterLstID] != NULL) { - *RegisterHeader = MemS3RegListC32[RegisterLstID]; - return AGESA_SUCCESS; - } - ASSERT(FALSE); // Device register list error - return AGESA_FATAL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function stores special case register on the heap. - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -STATIC -MemNS3SetSpecialPCIRegC32 ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - LOCATE_HEAP_PTR LocateBufferPtr; - UINT8 i; - UINT8 NodeID; - UINT8 Offset; - S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; - - Offset = 0; - LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { - SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; - // Get the node ID of the target die. - NodeID = (UINT8) (Address.Address.Device - 24); - for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) { - if (SpecialHeapHeader[i].Node == NodeID) { - // Get the offset in the heap for the target die. - Offset = SpecialHeapHeader[i].Offset; - break; - } - } - ASSERT (i < MAX_NODES_SUPPORTED_C32); - // Save the value in the heap at appropriate offset based on the index - // of the target register in the special case array. - if (Offset != 0) { - for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) { - if (SpecialCasePCIRegC32[i] == Address.Address.Register) { - *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; - } - } - } - } -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function stores special case register on the heap. - * - * @param[in,out] *NBPtr - Pointer to the northbridge block. - * @param[in,out] *StdHeader - Config handle for library and services. - * @return none - */ -VOID -STATIC -MemNS3ExitSelfRefRegC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - LOCATE_HEAP_PTR LocateBufferPtr; - UINT8 i; - PCI_ADDR PciAddr; - UINT32 Value; - UINT8 NodeID; - UINT8 Offset; - S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; - - Offset = 0; - PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; - PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; - PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; - PciAddr.Address.Function = 2; - LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { - SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; - // Get the node ID of the target die. - NodeID = (UINT8) (PciAddr.Address.Device - 24); - for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) { - if (SpecialHeapHeader[i].Node == NodeID) { - // Get the offset in the heap for the target die. - Offset = SpecialHeapHeader[i].Offset; - break; - } - } - ASSERT (i < MAX_NODES_SUPPORTED_C32); - // Restore the value one by one in the sequence of the special case register array. - if (Offset != 0) { - for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) { - PciAddr.Address.Register = SpecialCasePCIRegC32[i]; - Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); - MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); - } - } - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.h deleted file mode 100644 index 7c273afe75..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.h +++ /dev/null @@ -1,84 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnS3c32.h - * - * S3 resume memory related function for C32. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _MNS3C32_H_ -#define _MNS3C32_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ -/// ID for register list of C32 -typedef enum { - PCI_LST_ESR_C32, ///< Assign 0x0000 for PCI register list for pre exit self refresh. - PCI_LST_C32, ///< Assign 0x0001 for PCI register list for post exist self refresh. - CPCI_LST_ESR_C32, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. - CPCI_LST_C32, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. - MSR_LST_ESR_C32, ///< Assign 0x0004 for MSR register list for pre exit self refresh. - MSR_LST_C32, ///< Assign 0x0005 for MSR register list for post exit self refresh. - CMSR_LST_ESR_C32, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. - CMSR_LST_C32 ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. -} RegisterListIDC32; - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -#endif //_MNS3C32_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c deleted file mode 100644 index 4df1a63c3f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c +++ /dev/null @@ -1,493 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnc32.c - * - * Common Northbridge functions for C32 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnc32.h" -#include "mu.h" -#include "S3.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_C32_MNC32_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB - * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA - * @param[in] NodeID - UINT8 indicating node ID of the NB object. - * - * @return Boolean indicating that this is the correct memory - * controller type for the node number that was passed in. - */ - -BOOLEAN -MemConstructNBBlockC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *SharedPtr, - IN UINT8 NodeID - ) -{ - UINT8 Dct; - UINT8 Channel; - UINT8 SpdSocketIndex; - UINT8 SpdChannelIndex; - DIE_STRUCT *MCTPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->MemPtr = MemPtr; - NBPtr->RefPtr = MemPtr->ParameterListPtr; - NBPtr->SharedPtr = SharedPtr; - - MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->MCTPtr = MCTPtr; - NBPtr->MCTPtr->NodeId = NodeID; - NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; - NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - - // - // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs - // - AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_C32 * ( - sizeof (DCT_STRUCT) + ( - MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) - ) - ); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs - return FALSE; - } - - MCTPtr->DctCount = MAX_DCTS_PER_NODE_C32; - MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_C32 * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { - MCTPtr->DctData[Dct].Dct = Dct; - MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_C32; - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; - MCTPtr->DctData[Dct].ChData[0].Dct = Dct; - AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_C32 * sizeof (CH_DEF_STRUCT); - } - NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; - - // - // Initialize Socket List - // - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { - MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]); - MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings); - MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; - } - - MemNInitNBDataC32 (NBPtr); - - FeatPtr->InitCPG (NBPtr); - NBPtr->FeatPtr = FeatPtr; - FeatPtr->InitHwRxEn (NBPtr); - // - // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel - // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that - // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the - // dimm types(QR or not) are known. This is done in the Technology block constructor. - // - // Calculate the SpdSocketIndex separately from the SpdChannelIndex. - // This will facilitate modifications due to some processors that might - // map the DCT-CHANNEL differently. - // - SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); - // - // Traverse the Dct/Channel structures - // - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { - for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_C32; Channel++) { - // - // Calculate the number of Dimms on this channel using the - // die/dct/channel to Socket/channel conversion. - // - SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, - NBPtr->MCTPtr->SocketId, - MemNGetSocketRelativeChannelC32 (NBPtr, Dct, Channel), - &MemPtr->StdHeader); - NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); - } - } - - MemNSwitchDCTNb (NBPtr, 0); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes member functions and variables of NB block. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitNBDataC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->DctCachePtr = NBPtr->DctCache; - NBPtr->PsPtr = NBPtr->PSBlock; - - InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable); - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Dct = 0; - NBPtr->Channel = 0; - NBPtr->DctCount = MAX_DCTS_PER_NODE_C32; - NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_C32; - NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32; - NBPtr->Ganged = FALSE; - NBPtr->PosTrnPattern = POS_PATTERN_256B; - NBPtr->MemCleared = FALSE; - NBPtr->StartupSpeed = DDR800_FREQUENCY; - NBPtr->RcvrEnDlyLimit = 0x1FF; - NBPtr->DefDctSelIntLvAddr = 3; - NBPtr->CsRegMsk = 0x1FF83FE0; - - LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); - - NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; - NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; - NBPtr->InitializeMCT = MemNInitializeMctC32; - NBPtr->FinalizeMCT = MemNFinalizeMctC32; - NBPtr->SendMrsCmd = MemNSendMrsCmdC32; - NBPtr->sendZQCmd = MemNSendZQCmdNb; - NBPtr->WritePattern = MemNWritePatternC32; - NBPtr->ReadPattern = MemNReadPatternC32; - NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; - NBPtr->CompareTestPattern = MemNCompareTestPatternNb; - NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; - NBPtr->StitchMemory = MemNStitchMemoryNb; - NBPtr->AutoConfig = MemNAutoConfigC32; - NBPtr->PlatformSpec = MemNPlatformSpecNb; - NBPtr->InitMCT = MemNInitMCTNb; - NBPtr->DisableDCT = MemNDisableDCTNb; - NBPtr->StartupDCT = MemNStartupDCTNb; - NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; - NBPtr->ChangeFrequency = MemNChangeFrequencyNb; - NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; - NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse; - NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; - NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; - NBPtr->HtMemMapInit = MemNHtMemMapInitNb; - NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; - NBPtr->CpuMemTyping = MemNCPUMemTypingNb; - NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingC32; - NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->OtherTiming = MemNOtherTimingC32; - NBPtr->UMAMemTyping = MemNUMAMemTypingNb; - NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32; - NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32; - NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb; - NBPtr->TrainingFlow = (VOID (*) (MEM_NB_BLOCK *)) MemNTrainingFlowNb; - MemNInitNBDataNb (NBPtr); - - NBPtr->PollBitField = MemNPollBitFieldNb; - NBPtr->BrdcstCheck = MemNBrdcstCheckNb; - NBPtr->BrdcstSet = MemNBrdcstSetNb; - NBPtr->GetTrainDly = MemNGetTrainDlyNb; - NBPtr->SetTrainDly = MemNSetTrainDlyNb; - NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; - NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; - NBPtr->RankEnabled = MemNRankEnabledNb; - NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitC32; - NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; - NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; - NBPtr->MemNInitPhyComp = MemNInitPhyCompC32; - NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecC32; - NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitC32; - NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, INT16 *)) memDefRet; - NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; - NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; - NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; - NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; - NBPtr->CSPerChannel = MemNCSPerChannelNb; - NBPtr->CSPerDelay = MemNCSPerDelayNb; - NBPtr->FlushPattern = MemNFlushPatternNb; - NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; - NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->GetUmaSize = MemNGetUmaSizeNb; - NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; - NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet; - NBPtr->WaitXMemClks = MemNWaitXMemClksNb; - NBPtr->MemNGetDramTerm = MemNGetDramTermNb; - NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; - NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; - NBPtr->MemNGetMR0WR = MemNGetMR0WRNb; - NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; - NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; - NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - - NBPtr->IsSupported[SetSpareEn] = TRUE; - NBPtr->IsSupported[CheckSpareEn] = TRUE; - NBPtr->IsSupported[SetDllShutDown] = TRUE; - NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE; - NBPtr->IsSupported[CheckMaxDramRate] = TRUE; - NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE; - NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; - NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; - NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE; - NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE; - NBPtr->IsSupported[CheckODTControls] = TRUE; - NBPtr->IsSupported[CheckDummyCLRead] = TRUE; - NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE; - NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; - NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; - - NBPtr->FamilySpecificHook[InitExtMMIOAddr] = MemNInitExtMMIOAddrC32; - NBPtr->FamilySpecificHook[ForceLvDimmVoltage] = MemNForceLvDimmVoltageC32; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the default values in the MEM_DATA_STRUCT - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - */ -VOID -MemNInitDefaultsC32 ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT8 Socket; - UINT8 Channel; - MEM_PARAMETER_STRUCT *RefPtr; - ASSERT (MemPtr != NULL); - RefPtr = MemPtr->ParameterListPtr; - - // Memory Map/Mgt. - // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB - RefPtr->BottomIo = 0xE0; - RefPtr->UmaMode = UserOptions.CfgUmaMode; - RefPtr->UmaSize = UserOptions.CfgUmaSize; - RefPtr->MemHoleRemapping = TRUE; - RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb; - // - - - // Dram Timing - RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; - RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; - for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { - for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { - MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; - MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; - } - } - - // Memory Clear - RefPtr->EnableMemClr = TRUE; - - // TableBasedAlterations - RefPtr->TableBasedAlterations = NULL; - - // Platform config table - RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; - - // Memory Restore - RefPtr->MemRestoreCtl = FALSE; - RefPtr->SaveMemContextCtl = FALSE; - AmdS3ParamsInitializer (&RefPtr->MemContext); - - // Dram Configuration - RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; - RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; - RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; - RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; - RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; - RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; - - // Dram Power - RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; - - // Vref - RefPtr->ExternalVrefCtl = UserOptions.CfgExternalVrefCtlFeature; - - //Training Mode - RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode; -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function writes training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Pattern[] - Pattern to write - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNWritePatternC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUWriteCachelines (Address, Pattern, ClCount); -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function reads training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer to fill - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNReadPatternC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUReadCachelines (Buffer, Address, ClCount); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates DQS training for Server NB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -memNEnableTrainSequenceC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BOOLEAN Retval; - Retval = TRUE; - if (!MemNIsIdSupportedC32 (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { - Retval = FALSE; - } - return Retval; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.h deleted file mode 100644 index cd687f03f0..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnc32.h +++ /dev/null @@ -1,212 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnc32.h - * - * Northbridge C32 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 47408 $ @e \$Date: 2011-02-18 09:56:31 -0700 (Fri, 18 Feb 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _MNC32_H_ -#define _MNC32_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ -#define MAX_CHANNELS_PER_SOCKET_C32 2 -#define MAX_DCTS_PER_NODE_C32 2 -#define MAX_CHANNELS_PER_DCT_C32 1 -#define MAX_NODES_SUPPORTED_C32 8 - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemConstructNBBlockC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *SharedPtr, - IN UINT8 NodeID - ); - -VOID -MemNInitNBDataC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitDefaultsC32 ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -BOOLEAN -MemNInitializeMctC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNFinalizeMctC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNSendMrsCmdC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNAutoConfigC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNOtherTimingC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitPhyCompC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNWritePatternC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -MemNReadPatternC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -InitNBRegTableC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT TSEFO NBRegTable[] - ); - -UINT8 -MemNGetSocketRelativeChannelC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct, - IN UINT8 Channel - ); - -BOOLEAN -MemNIsIdSupportedC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID *LogicalIdPtr - ); - -VOID -MemNBeforeDramInitC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNPlatformSpecificFormFactorInitC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNEnDLLShutDownC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -UINT32 -MemNCmnGetSetFieldC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ); - -VOID -MemNBeforePlatformSpecC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -memNEnableTrainSequenceC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNInitExtMMIOAddrC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -VOID -MemNBeforeDQSTrainingC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNForceLvDimmVoltageC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *MemMainPtr - ); - -#endif /* _MNC32_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mndctc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mndctc32.c deleted file mode 100644 index af946cc341..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mndctc32.c +++ /dev/null @@ -1,454 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mndctc32.c - * - * Northbridge DCT support for C32 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnc32.h" -#include "merrhdl.h" -#include "cpuFamRegisters.h" -#include "PlatformMemoryConfiguration.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_NB_C32_MNDCTC32_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs the memory controller with configuration parameters - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_ERROR may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred - * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value - */ - -BOOLEAN -MemNAutoConfigC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 PowerDownMode; - UINT32 Value32; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_PARAMETER_STRUCT *RefPtr; - - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - //====================================================================== - // Build Dram Control Register Value (F2x78) - //====================================================================== - // - //It is recommended that these bits remain in the default state. - //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5); - - MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1); - - //====================================================================== - // Build Dram Config Lo Register Value - //====================================================================== - // - - if (MCTPtr->Status[SbParDimms]) { - // - // SbParDimms should be set for all DDR3 RDIMMS - // Cannot turn off ParEn for DDR3 - // - //@attention - add debug option for parity control - MemNSetBitFieldNb (NBPtr, BFParEn, 1); - } - - if (MCTPtr->GangedMode) { - MemNSetBitFieldNb (NBPtr, BFWidth128, 1); - } - - MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF); - - if (!MCTPtr->Status[SbRegistered]) { - MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); - } - - if (MCTPtr->Status[SbEccDimms]) { - MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); - } - - //====================================================================== - // Build Dram Config Hi Register Value - //====================================================================== - // - - MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed)); - - if (MCTPtr->Status[SbRegistered]) { - if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) { - MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1); - } - } - - if (RefPtr->EnableBankSwizzle) { - MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); - } - - if (DCTPtr->Timings.DimmQrPresent) { - if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) { - MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1); - } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) { - MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1); - } - } - - MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF); - MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1); - //====================================================================== - // Build Dram Config Misc Register Value - //====================================================================== - // - if (MCTPtr->Status[SbRegistered]) { - if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { - MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1); - } - } - //====================================================================== - // Build Dram Config Misc 2 Register Value - //====================================================================== - // - // - // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms - // - if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) { - MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1); - } - // - // DTaxTxFifpWrDly - // - Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit); - if ((Value32 >= 2) && (Value32 <= 5)) { - MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32)); - } - - // - // ProgOdtEn - // - if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { - MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1); - } else { - MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0); - } - // - // OdtSwizzle - // - if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) { - PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode); - IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); - if (PowerDownMode == 1) { - MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1); - } - } - - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sends an MRS command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSendMrsCmdC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSwapBitsNb (NBPtr); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n", - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); - - // 1.Set SendMrsCmd=1 - MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); - - // 2.Wait for SendMrsCmd=0 - MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes before DRAM init - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNBeforeDramInitC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - //Set PllLockTime and DllLockTime to default. - MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0); - MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190); - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Enable DLL Shut down - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNEnDLLShutDownC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - BOOLEAN DllShutDownEn; - - DllShutDownEn = TRUE; - IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader)); - - if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) { - if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C); - MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D); - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); - } - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Workaround for erratum 322 and 263 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNBeforePlatformSpecC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // Errata 263 - if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) { - MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800); - } else { - MemNSetBitFieldNb (NBPtr, BFErr263, 0); - } - - // Errata 322 - // 1.Write 00000000h to F2x[1,0]9C_xD08E000 - MemNSetBitFieldNb (NBPtr, BFErr322I, 0); - // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is - // greater than or equal to 011b (DDR-800 and higher), - // then write 00000080h to F2x[1,0]9C_xD02E001, - // else write 00000090h to F2x[1,0]9C_xD02E001. - MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Initializes extended MMIO address space - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - */ -BOOLEAN -MemNInitExtMMIOAddrC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Index; - UINT32 Value; - PCI_ADDR PciAddr; - - if (NBPtr->RefPtr->SysLimit >= _1TB_RJ16) { - // Initialize all indices of F1x114_x2 and F1x114_x3. - for (Index = 0; Index < 32; Index++) { - PciAddr = NBPtr->PciAddr; - PciAddr.Address.Function = 1; - - PciAddr.Address.Register = 0x110; - Value = 0x20000000 | Index; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - - PciAddr.Address.Register = 0x114; - Value = 0; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - - PciAddr.Address.Register = 0x110; - Value = 0x30000000 | Index; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - - PciAddr.Address.Register = 0x114; - Value = 0; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Force LvDimm voltage to 1.5V for D0 part - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemMainPtr - Pointer to MEM_MAIN_DATA_BLOCK - * - * @return TRUE - */ -BOOLEAN -MemNForceLvDimmVoltageC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *MemMainPtr - ) -{ - MEM_PARAMETER_STRUCT *ParameterPtr; - MEM_SHARED_DATA *mmSharedPtr; - - mmSharedPtr = ((MEM_MAIN_DATA_BLOCK *) MemMainPtr)->mmSharedPtr; - ParameterPtr = ((MEM_MAIN_DATA_BLOCK *) MemMainPtr)->MemPtr->ParameterListPtr; - - if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D0) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\n\nC32 D0 on socket %d.\n", NBPtr->MCTPtr->SocketId); - if (((1 << CONVERT_VDDIO_TO_ENCODED (VOLT1_5)) & mmSharedPtr->VoltageMap) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nDimms are 1.5V capable. Adjust voltage to 1.5V.\n"); - ParameterPtr->DDR3Voltage = VOLT1_5; - } else { - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_LVDIMM_VOLT1_5_SUPPORT, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nDimms are not 1.5V capable. Adjust voltage to 1.5V based on customer's choice.\n\n"); - ParameterPtr->DDR3Voltage = VOLT1_5; - } else { - IDS_HDT_CONSOLE (MEM_FLOW, "\nDimms are not 1.5V capable. Do not adjust voltage based on customer's choice.\n\n"); - PutEventLog (AGESA_FATAL, MEM_ERROR_VDDIO_UNSUPPORTED, NBPtr->Node, 0, 0, 0, &(NBPtr->MemPtr->StdHeader)); - SetMemError (AGESA_FATAL, NBPtr->MCTPtr); - } - } - } - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c deleted file mode 100644 index f479ce0211..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c +++ /dev/null @@ -1,135 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnflowc32.c - * - * C32 initializer for MCT and DCT - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mnc32.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_C32_MNFLOWC32_FILECODE -/* features */ - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the platform specific block - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - AGESA_SUCCESS at least one dorm factor was found - * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found - */ - -BOOLEAN -MemNPlatformSpecificFormFactorInitC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 f; - UINT8 ErrUnSuppFFCount; - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->ChannelPtr->ChDimmValid != 0) { - ErrUnSuppFFCount = 0; - for (f = 0; f < MAX_FF_TYPES; f++) { - ASSERT (memPlatSpecFFInstalledC32[f] != NULL); - if (memPlatSpecFFInstalledC32[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { - ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors - } else { - break; - } - } - if (ErrUnSuppFFCount == MAX_FF_TYPES) { - return FALSE; // No FF types are supported - } - } - } - return TRUE; -} - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnidendimmc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnidendimmc32.c deleted file mode 100644 index 434e30ee21..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnidendimmc32.c +++ /dev/null @@ -1,140 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnidendimmc32.c - * - * C32 northbridge constructor for dimm identification translator. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnc32.h" -#include "mfidendimm.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for dimm identification translator - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in,out] NodeID - ID of current node to construct - * @return TRUE - This is the correct constructor for the targeted node. - * @return FALSE - This isn't the correct constructor for the targeted node. - */ - -BOOLEAN -MemNIdentifyDimmConstructorC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32; - NBPtr->DctCount = MAX_DCTS_PER_NODE_C32; - NBPtr->CsRegMsk = 0x1FF83FE0; - NBPtr->MemPtr = MemPtr; - NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Ganged = FALSE; - InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable); - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32; - NBPtr->SetBitField = MemNSetBitFieldNb; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32; - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnmctc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnmctc32.c deleted file mode 100644 index 1790a093c1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnmctc32.c +++ /dev/null @@ -1,214 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnmctc32.c - * - * Northbridge C32 MCT supporting functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnc32.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_C32_MNMCTC32_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets final values in BUCFG and BUCFG2 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNFinalizeMctC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - DRAM_PREFETCH_MODE DramPrefetchMode; - S_UINT64 SMsr; - UINT16 Speed; - UINT32 ExtMctCfgLoRegVal; - - MemPtr = NBPtr->MemPtr; - DramPrefetchMode = MemPtr->PlatFormConfig->PlatformProfile.AdvancedPerformanceProfile.DramPrefetchMode; - Speed = NBPtr->DCTPtr->Timings.Speed; - MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40); - - ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg); - ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001; - - ExtMctCfgLoRegVal &= 0x0FFFFFFF; - if (Speed == DDR667_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x40000000; - } else if (Speed == DDR800_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x50000000; - } else if (Speed == DDR1066_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x60000000; - } else if (Speed == DDR1333_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x80000000; - } else { - ExtMctCfgLoRegVal |= 0x90000000; - } - // - // PrefFiveConf, PrefFourConf - // - ExtMctCfgLoRegVal |= 0x0FC00000; - // - // EnSplitDctLimits - // - if (!NBPtr->Ganged) { - ExtMctCfgLoRegVal |= 0x00001000; - } - MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal); - - if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_IO || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { - MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 1); - } - - if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_CPU || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { - MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1); - } - - if (NBPtr->Node == BSP_DIE) { - if (!NBPtr->ClToNbFlag) { - LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis - LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - } - - LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis - LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - } - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets initial values in BUCFG and BUCFG2 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNInitializeMctC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - S_UINT64 SMsr; - - MemPtr = NBPtr->MemPtr; - - if (NBPtr->Node == BSP_DIE) { - LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - if (SMsr.lo & ((UINT32)1 << 15)) { - NBPtr->ClToNbFlag = 1; - } - SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis - LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis - LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnotc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnotc32.c deleted file mode 100644 index c2c0ffbdca..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnotc32.c +++ /dev/null @@ -1,246 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnotc32.c - * - * Northbridge Non-SPD timings for C32 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnc32.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_C32_MNOTC32_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -MemNSetOtherTimingC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/* -UINT32 -STATIC -MemNGetODTDelaysC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -*/ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the non-SPD timings - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNOtherTimingC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSwitchDCTNb (NBPtr, 0); - if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { - MemNSetOtherTimingC32 (NBPtr); - MemNPowerDownCtlNb (NBPtr); - MemNEnDLLShutDownC32 (NBPtr); - } - - MemNSwitchDCTNb (NBPtr, 1); - if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) { - MemNSetOtherTimingC32 (NBPtr); - MemNPowerDownCtlNb (NBPtr); - MemNEnDLLShutDownC32 (NBPtr); - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the non-SPD timings in PCI registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemNSetOtherTimingC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - - MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the ODT delays - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -/* -UINT32 -STATIC -MemNGetODTDelaysC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - INT8 Ld; - UINT32 ODTDelays; - // - // On revision D processors, the BIOS must additionally configure the ODT pattern - // and the ODT switching delays. - // - // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length. - // -Read the Burst Length from F2x[1, 0]84[BurstCtrl]. - // -Value of 2, BL = 4 else assume BL=8. - // -Initialize ODTDelays based on BL value - // -WrOdtOnDuration [14:12] = BL / 2 + 1 - // -WrOdtTrnOnDly [10:8] = 0 - // -RdOdtOnDuration [6:4] = BL / 2 + 1 - // - ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050; - - // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1) - // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0] - Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); - if (Ld < 0) { - Ld = 0; - } - if (Ld > 7) { - Ld = 7; - } - ODTDelays += Ld; - return ODTDelays; -} -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function enables power down mode - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -/* -VOID -STATIC -MemNPowerDownCtlC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_PARAMETER_STRUCT *RefPtr; - UINT8 PowerDownMode; - - RefPtr = NBPtr->RefPtr; - - // we can't enable powerdown mode when doing WL - if (RefPtr->EnablePowerDown) { - MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); - PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; - IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); - if (PowerDownMode) { - MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); - } - } -} -*/ \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnphyc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnphyc32.c deleted file mode 100644 index 74317d7ac1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnphyc32.c +++ /dev/null @@ -1,222 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnphyc32.c - * - * Northbridge Phy support for C32 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnc32.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_C32_MNPHYC32_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DDR phy compensation logic - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitPhyCompC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2}; - CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2}; - CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2}; - CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3}; - UINT8 i; - UINT8 j; - UINT8 CurrDct; - CurrDct = NBPtr->Dct; - // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1 - // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. - // DisAutoComp will be cleared after Dram init has completed - // - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); - MemUWait10ns (500, NBPtr->MemPtr); - MemNSwitchDCTNb (NBPtr, CurrDct); - - // 3. For each normalized driver strength code read from - // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the - // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal]. - // - // 4. For each normalized driver strength code read from - // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding - // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal, - // D3Cmp2PCal]. - // - j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren); - i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren); - - MemNSwitchDCTNb (NBPtr, 0); - ASSERT (j <= 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]); - - if ((NBPtr->ChannelPtr->Dimms == 3) && - ((NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) || - (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY))) { - // - // Special Case for 3 Dimms @ 800MHz or 1066MHz - // - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 1); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 1); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 1); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 1); - } else { - ASSERT (i <= 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]); - } - MemNSwitchDCTNb (NBPtr, CurrDct); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes before DRAM training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNBeforeDQSTrainingC32 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 ChipSel; - UINT32 TestAddrRJ16; - UINT32 RealAddr; - - MemTBeginTraining (NBPtr->TechPtr); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) { - - RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr); - - MemUDummyCLRead (RealAddr); - - MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); - MemUWait10ns (60, NBPtr->MemPtr); // Wait 300ns - MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); - MemUWait10ns (400, NBPtr->MemPtr); // Wait 2us - MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr); - break; - } - } - } - if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) { - if (!NBPtr->MCTPtr->Status[SbEccDimms]) { - MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010); - } - if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) { - MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080); - } - } - } - - MemTEndTraining (NBPtr->TechPtr); - - MemNSetBitFieldNb (NBPtr, BFDisDatMsk, 1); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnprotoc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnprotoc32.c deleted file mode 100644 index f9f49d09ef..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnprotoc32.c +++ /dev/null @@ -1,66 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnprotoc32.c - * - * Northbridge support functions for Errata and early samples - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - - -#include "AGESA.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_C32_MNPROTOC32_FILECODE - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c deleted file mode 100644 index 953dd4cf00..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c +++ /dev/null @@ -1,636 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnregc32.c - * - * Common Northbridge register related functions for C32 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/C32) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnc32.h" -#include "merrhdl.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_C32_MNREGC32_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*-----------------------------------------------------------------------------*/ -/** - * MemNIsIdSupportedC32 - * This function matches the CPU_LOGICAL_ID with certain criteria to - * determine if it is supported by this NBBlock. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID - * - * @return TRUE - This node is a C32. - * @return FALSE - This node is not a C32. - * - */ -BOOLEAN -MemNIsIdSupportedC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID *LogicalIdPtr - ) -{ - if (((LogicalIdPtr->Family & AMD_FAMILY_10_C32) != 0) && ((LogicalIdPtr->Revision & AMD_F10_C32_ALL) != 0)) { - return TRUE; - } else { - return FALSE; - } -} - -/*-----------------------------------------------------------------------------*/ -/** - * This function calculates the memory channel index relative to the - * socket, taking the Die number, the Dct, and the channel. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Dct - * @param[in] Channel - * - */ -UINT8 -MemNGetSocketRelativeChannelC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct, - IN UINT8 Channel - ) -{ - return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_C32) + Dct); -} -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets or sets a value to a bit field in a PCI register. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Bit Field to be programmed - * @param[in] Field - Value to be programmed - * @param[in] IsSet - Indicates if the function will set or get - * - * @return value read, if the function is used as a "get" - */ - -UINT32 -MemNCmnGetSetFieldC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ) -{ - TSEFO Address; - PCI_ADDR PciAddr; - UINT8 Type; - UINT8 IsLinked; - UINT32 Value; - UINT32 Highbit; - UINT32 Lowbit; - UINT32 Mask; - - Value = 0; - if (FieldName < BFEndOfList) { - Address = NBPtr->NBRegTable[FieldName]; - if (Address) { - Lowbit = TSEFO_END (Address); - Highbit = TSEFO_START (Address); - Type = (UINT8) TSEFO_TYPE (Address); - IsLinked = (UINT8) TSEFO_LINKED (Address); - - // If Fn2 and DCT1 selected, set Address to be 1xx - if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { - if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) { - Address |= 0x0100; - } - } - - ASSERT ((Address & ((UINT32) 1) << 28) == 0); // Phy direct access method is not supported - - if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { - // Special DCT Phy access - Address &= 0x0FFFFFFF; - Lowbit = 0; - Highbit = 16; - IsLinked = 0; - } else { - // Normal DCT Phy access - Address = TSEFO_OFFSET (Address); - } - - if (Type == NB_ACCESS) { - PciAddr.AddressValue = Address; - PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; - PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; - PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; - Address = PciAddr.AddressValue; - LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && - (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); - } - } else if (Type == DCT_PHY_ACCESS) { - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); - } else if (Type == DCT_EXTRA) { - MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg); - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); - } else { - IDS_ERROR_TRAP; - } - - if (IsSet) { - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - if ((Highbit - Lowbit) != 31) { - Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); - } else { - Mask = (UINT32)0xFFFFFFFF; - } - Value &= ~(Mask << Lowbit); - Value |= (Field & Mask) << Lowbit; - - if (Type == NB_ACCESS) { - PciAddr.AddressValue = Address; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && - (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); - } - } else if (Type == DCT_PHY_ACCESS) { - MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); - } else if (Type == DCT_EXTRA) { - MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); - } else { - IDS_ERROR_TRAP; - } - if (IsLinked) { - MemNCmnGetSetFieldC32 (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); - } - } else { - Value = Value >> Lowbit; // Shift - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - if ((Highbit - Lowbit) != 31) { - Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); - } - if (IsLinked) { - Value |= MemNCmnGetSetFieldC32 (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); - } - } - } - } else { - IDS_ERROR_TRAP; // Invalid bit field index - } - return Value; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes bit field translation table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] NBRegTable[] - Pointer to the bit field data structure - * - */ - -VOID -InitNBRegTableC32 ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT TSEFO NBRegTable[] - ) -{ - UINT16 i; - - // Allocate heap for NB register table - if (!MemNAllocateNBRegTableNb (NBPtr, NbRegTabC32)) { - return; // escape if fails - } - NBRegTable = NBPtr->NBRegTable; - - for (i = 0; i < BFEndOfList; i++) { - NBRegTable[i] = 0; - } - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31, 0, BFExtMctCfgLoReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFReserved00B); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFReserved001); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 7, 7, BFProgOdtEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 12, 12, BFEnSplitDctLimits); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 24, 22, BFPrefFourConf); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 27, 25, BFPrefFiveConf); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x602, 31, 0, BFUSPLLCtlAll); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x603, 31, 0, BFDSPLLCtlAll); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x606, 0, 0, BFUSNibbleAlignEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x690, 2, 2, BFChnLinitClkEn); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFPhyRODTCSLow); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x181, 31, 0, BFPhyRODTCSHigh); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x183, 31, 0, BFPhyWODTCSHigh); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 31, 30, BFTSLinkSelect); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 9, 9, BFTS2BitLockEn); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 8, 8, BFTS2En); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 4, 4, BFTS1En); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 1, 1, BFTS0LinkStarEn); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 0, 0, BFTS0En); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800002, 15, 0, BFLinkTrainData); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 17, 17, BFRstRxFifoPtrs); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 16, 16, BFRxFifoPtrInit); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 1, 1, BFRstTxFifoPtrs); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 0, 0, BFTxFifoPtrInit); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 31, 24, BFLpbkCount); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 21, 20, BFLpbkMap); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 16, 16, BFSendLpbkMaintCmd); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 15, 0, BFLpbkData); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 20, 16, BFMbRdPtrEn); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 9, 4, BFLnkLpBkLat); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 1, 1, BFLpbkRndTripLatDone); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 0, 0, BFLnkLatTrainEn); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 1, 1, BFDsPhyReset); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 0, 0, BFLinkReset); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II); - - LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); - LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); - LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); - -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/Makefile.inc deleted file mode 100644 index 1114ad4eb8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -libagesa-y += mnParTrainHy.c -libagesa-y += mnS3hy.c -libagesa-y += mndcthy.c -libagesa-y += mnflowhy.c -libagesa-y += mnhy.c -libagesa-y += mnidendimmhy.c -libagesa-y += mnmcthy.c -libagesa-y += mnothy.c -libagesa-y += mnphyhy.c -libagesa-y += mnprotohy.c -libagesa-y += mnreghy.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c deleted file mode 100644 index fca7a61bcf..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c +++ /dev/null @@ -1,228 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnParTrainHy.c - * - * Feature which performs Memory DQS training on each node with each node training - * its own memory through code running on a core in the associated processor. - * This way memory can be trained in parallel by more than one processor. - * - * This file contains the Hydra specific parallel training function. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/HCTRN) - * @e \$Revision: 54775 $ @e \$Date: 2011-06-12 21:05:26 -0600 (Sun, 12 Jun 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnhy.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemFParallelTrainingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -STATIC -MemConstructRemoteNBBlockHY ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN DIE_STRUCT *MCTPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr -); -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the training function which set up the environment for remote - * training on the ap and launches the remote routine. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Launch training on AP successfully. - * @return FALSE - Fail to launch training on AP. - */ -BOOLEAN -MemFParallelTrainingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - DIE_STRUCT *MCTPtr; - REMOTE_TRAINING_ENV *EnvPtr; - AP_TASK TrainingTask; - UINT8 Socket; - UINT8 Module; - UINT8 APCore; - UINT8 p; - UINT32 LowCore; - UINT32 HighCore; - UINT32 BspSocket; - UINT32 BspModule; - UINT32 BspCore; - AGESA_STATUS Status; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT16 MctDataSize; - StdHeader = &(NBPtr->MemPtr->StdHeader); - MCTPtr = NBPtr->MCTPtr; - Socket = MCTPtr->SocketId; - Module = MCTPtr->DieId; - - // - // Allocate buffer for REMOTE_TRAINING_ENV - // - MctDataSize = MAX_DCTS_PER_NODE_HY * ( - sizeof (DCT_STRUCT) + ( - MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) - ) - ); - AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); - - // - // Setup Remote training environment - // - LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; - } - EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; - EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockHY; - EnvPtr->FeatPtr = NBPtr->FeatPtr; - EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; - EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; - EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize; - EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; - EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; - EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; - - LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); - - // - // Get Socket, Core of the BSP - // - IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); - EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); - EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); - - // - // Set up the remote task structure - // - TrainingTask.DataTransfer.DataPtr = EnvPtr; - TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4; - TrainingTask.DataTransfer.DataTransferFlags = 0; - TrainingTask.ExeFlags = 0; - TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; - - // - // Get Target AP Core - // - GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); - APCore = (UINT8) (LowCore & 0x000000FF); - - // - // Launch Remote Training - // - ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); - - HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); - - return TRUE; - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" - return FALSE; - } -} - -BOOLEAN -STATIC -MemConstructRemoteNBBlockHY ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN DIE_STRUCT *MCTPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - NBPtr->MCTPtr = MCTPtr; - NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; - - MemNInitNBDataHy (NBPtr); - - FeatPtr->InitCPG (NBPtr); - NBPtr->FeatPtr = FeatPtr; - FeatPtr->InitHwRxEn (NBPtr); - MemNSwitchDCTNb (NBPtr, 0); - - //---------------------------------------------------------------------------- - // Get TSC rate of the this AP - //---------------------------------------------------------------------------- - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c deleted file mode 100644 index 3d6ec1d727..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c +++ /dev/null @@ -1,746 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mns3hy.c - * - * HY memory specific function to support S3 resume - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 50673 $ @e \$Date: 2011-04-12 21:18:06 -0600 (Tue, 12 Apr 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "mnhy.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "mnS3hy.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_NB_HY_MNS3HY_FILECODE - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemS3ResumeConstructNBBlockHy ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -UINT16 -STATIC -MemNS3GetRegLstPtrHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ); - -AGESA_STATUS -STATIC -MemNS3GetDeviceRegLstHy ( - IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader - ); - -VOID -STATIC -MemNS3ExitSelfRefRegHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -MemNS3SetSpecialPCIRegHy ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ); - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -PCI_SPECIAL_CASE PciSpecialCaseFuncHy[] = { - {MemNS3GetCSRNb, MemNS3SetCSRNb}, - {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegHy}, - {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} -}; - -PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorHy[] = { - {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, - {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, - {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, - {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, - {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, - {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, - {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, - {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, - {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, - {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, - {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, - {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} -}; - -CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefHy = { - 0, - (sizeof (S3PciPreSelfRefDescriptorHy) / sizeof (PCI_REG_DESCRIPTOR)), - S3PciPreSelfRefDescriptorHy, - NULL -}; - -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorHy[] = { - // DCT 0 - {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0xA4, 0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - //errata 322 - {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - //errata 263 - {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - - // DCT 1 - {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - // errata 322 - {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - // errata 263 - {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - - // Restore F2x[1,0]94 right before exit self refresh - {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} -}; - -CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefHy = { - 0, - (sizeof (S3CPciPreSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), - S3CPciPreSelfDescriptorHy, - PciSpecialCaseFuncHy -}; - -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorHy[] = { - // DCT0 - {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - - // DCT1 - {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - - // DllShutDown - {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, - - // Restore scrubber related registers after restoring training related registers - {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK} -}; - -CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefHy = { - 0, - (sizeof (S3CPciPostSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), - S3CPciPostSelfDescriptorHy, - PciSpecialCaseFuncHy -}; - -MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorHy[] = { - {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, - {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, - {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, - {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} -}; - -CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefHy = { - 0, - (sizeof (S3MSRPreSelfRefDescriptorHy) / sizeof (MSR_REG_DESCRIPTOR)), - S3MSRPreSelfRefDescriptorHy, - NULL -}; - -VOID *MemS3RegListHy[] = { - (VOID *)&S3PciPreSelfRefHy, - NULL, - (VOID *)&S3CPciPreSelfRefHy, - (VOID *)&S3CPciPostSelfRefHy, - (VOID *)&S3MSRPreSelfRefHy, - NULL, - NULL, - NULL -}; - -CONST UINT16 ROMDATA SpecialCasePCIRegHy[] = { - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) -}; - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for S3 resume - * - * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. - * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. - * @param[in] NodeID - Node ID of the target node. - * - * @return BOOLEAN - * TRUE - This is the correct constructor for the targeted node. - * FALSE - This isn't the correct constructor for the targeted node. - */ - -BOOLEAN -MemS3ResumeConstructNBBlockHy ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - INT32 i; - MEM_NB_BLOCK *NBPtr; - - NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->MemPtr = MemPtr; - NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; - InitNBRegTableHy (NBPtr, NBPtr->NBRegTable); - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Dct = 0; - NBPtr->Channel = 0; - NBPtr->Ganged = FALSE; - NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; - NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; - - for (i = 0; i < EnumSize; i++) { - NBPtr->IsSupported[i] = FALSE; - } - - for (i = 0; i < NumberOfHooks; i++) { - NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; - } - - LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); - - NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; - NBPtr->SwitchDCT = MemNSwitchDCTNb; - NBPtr->SwitchChannel = MemNSwitchChannelNb; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->SetBitField = MemNSetBitFieldNb; - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; - NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedHy; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegHy; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrHy; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstHy; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)) * sizeof (UINT32); - - MemNSwitchDCTNb (NBPtr, 0); - - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the register list for each device for HY - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP - * @return UINT16 - size of the device descriptor on the target node. - */ -UINT16 -STATIC -MemNS3GetRegLstPtrHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ) -{ - UINT8 i; - UINT16 Size; - Size = 0; - for (i = PRESELFREF; i <= POSTSELFREF; i ++) { - DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); - DescriptPtr->PCIDevice[i].Node = NBPtr->Node; - DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; - if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[PCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { - DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_HY + i; - Size += sizeof (PCI_DEVICE_DESCRIPTOR); - } - DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); - DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; - DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; - if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CPCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { - DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_HY + i; - Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); - } - DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); - DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; - if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[MSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { - DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_HY + i; - Size += sizeof (MSR_DEVICE_DESCRIPTOR); - } - DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); - DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; - if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CMSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { - DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_HY + i; - Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); - } - } - return Size; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function return the register list according to the register ID. - * - * @param[in] RegisterLstID - value of the Register list ID. - * @param[out] **RegisterHeader - pointer to the address of the register list. - * @return none - */ -AGESA_STATUS -STATIC -MemNS3GetDeviceRegLstHy ( - IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader - ) -{ - if (RegisterLstID >= (sizeof (MemS3RegListHy) / sizeof (VOID *))) { - ASSERT(FALSE); // RegisterListID exceeded size of Register list - return AGESA_FATAL; - } - if (MemS3RegListHy[RegisterLstID] != NULL) { - *RegisterHeader = MemS3RegListHy[RegisterLstID]; - return AGESA_SUCCESS; - } - ASSERT(FALSE); // Device register list error - return AGESA_FATAL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function stores special case register on the heap. - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -STATIC -MemNS3SetSpecialPCIRegHy ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - LOCATE_HEAP_PTR LocateBufferPtr; - UINT8 i; - UINT8 NodeID; - UINT8 Offset; - S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; - - Offset = 0; - LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { - SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; - // Get the node ID of the target die. - NodeID = (UINT8) (Address.Address.Device - 24); - for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) { - if (SpecialHeapHeader[i].Node == NodeID) { - // Get the offset in the heap for the target die. - Offset = SpecialHeapHeader[i].Offset; - break; - } - } - ASSERT (i < MAX_NODES_SUPPORTED_HY); - // Save the value in the heap at appropriate offset based on the index - // of the target register in the special case array. - if (Offset != 0) { - for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) { - if (SpecialCasePCIRegHy[i] == Address.Address.Register) { - *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; - } - } - } - } -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function stores special case register on the heap. - * - * @param[in,out] *NBPtr - Pointer to the northbridge block. - * @param[in,out] *StdHeader - Config handle for library and services. - * @return none - */ -VOID -STATIC -MemNS3ExitSelfRefRegHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - LOCATE_HEAP_PTR LocateBufferPtr; - UINT8 i; - PCI_ADDR PciAddr; - UINT32 Value; - UINT8 NodeID; - UINT8 Offset; - S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; - - Offset = 0; - PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; - PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; - PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; - PciAddr.Address.Function = 2; - LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { - SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; - // Get the node ID of the target die. - NodeID = (UINT8) (PciAddr.Address.Device - 24); - for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) { - if (SpecialHeapHeader[i].Node == NodeID) { - // Get the offset in the heap for the target die. - Offset = SpecialHeapHeader[i].Offset; - break; - } - } - ASSERT (i < MAX_NODES_SUPPORTED_HY); - // Restore the value one by one in the sequence of the special case register array. - if (Offset != 0) { - for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) { - PciAddr.Address.Register = SpecialCasePCIRegHy[i]; - Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); - MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); - } - } - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.h deleted file mode 100644 index f644e7d349..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.h +++ /dev/null @@ -1,84 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnS3hy.h - * - * S3 resume memory related function for HY. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _MNS3HY_H_ -#define _MNS3HY_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ -/// ID for register list of HY -typedef enum { - PCI_LST_ESR_HY, ///< Assign 0x0000 for PCI register list for pre exit self refresh. - PCI_LST_HY, ///< Assign 0x0001 for PCI register list for post exist self refresh. - CPCI_LST_ESR_HY, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. - CPCI_LST_HY, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. - MSR_LST_ESR_HY, ///< Assign 0x0004 for MSR register list for pre exit self refresh. - MSR_LST_HY, ///< Assign 0x0005 for MSR register list for post exit self refresh. - CMSR_LST_ESR_HY, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. - CMSR_LST_HY ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. -} RegisterListIDHy; - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -#endif //_MNS3HY_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c deleted file mode 100644 index f808280184..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c +++ /dev/null @@ -1,456 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mndctHy.c - * - * Northbridge DCT support for Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnhy.h" -#include "merrhdl.h" -#include "cpuFamRegisters.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNDCTHY_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs the memory controller with configuration parameters - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value - */ - -BOOLEAN -MemNAutoConfigHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 PowerDownMode; - UINT32 Value32; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_PARAMETER_STRUCT *RefPtr; - - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - //====================================================================== - // Build Dram Control Register Value (F2x78) - //====================================================================== - // - //It is recommended that these bits remain in the default state. - //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5); - - MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1); - - //====================================================================== - // Build Dram Config Lo Register Value - //====================================================================== - // - - if (MCTPtr->Status[SbParDimms]) { - // - // SbParDimms should be set for all DDR3 RDIMMS - // Cannot turn off ParEn for DDR3 - // - //@attention - add debug option for parity control - MemNSetBitFieldNb (NBPtr, BFParEn, 1); - } - - - if (MCTPtr->GangedMode) { - MemNSetBitFieldNb (NBPtr, BFWidth128, 1); - } - - MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF); - - if (!MCTPtr->Status[SbRegistered]) { - MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); - } - - if (MCTPtr->Status[SbEccDimms]) { - MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); - } - - //====================================================================== - // Build Dram Config Hi Register Value - //====================================================================== - // - - MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed)); - - if (MCTPtr->Status[SbRegistered]) { - if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) { - MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1); - } - } - - if (RefPtr->EnableBankSwizzle) { - MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); - } - - if (DCTPtr->Timings.DimmQrPresent) { - if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) { - MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1); - } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) { - MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1); - } - } - - MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF); - MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1); - //====================================================================== - // Build Dram Config Misc Register Value - //====================================================================== - // - if (MCTPtr->Status[SbRegistered]) { - if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { - MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1); - } - } - //====================================================================== - // Build Dram Config Misc 2 Register Value - //====================================================================== - // - // - // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms - // - if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) { - MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1); - } - // - // DTaxTxFifpWrDly - // - Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit); - if ((Value32 >= 2) && (Value32 <= 5)) { - MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32)); - } - - // - // ProgOdtEn - // - if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { - MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1); - } else { - MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0); - } - // - // OdtSwizzle - // - if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) { - PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode); - IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); - if (PowerDownMode == 1) { - MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1); - } - } - - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sends an MRS command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSendMrsCmdHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSwapBitsNb (NBPtr); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n", - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); - - // 1.Set SendMrsCmd=1 - MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); - - // 2.Wait for SendMrsCmd=0 - MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sends an MRS command to all CS of all channels - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *DummyPtr - Unused pointer - * - * @return TRUE - */ - -BOOLEAN -MemNSendMrsCmdPerCsHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *DummyPtr - ) -{ - UINT8 Dct; - UINT8 ChipSel; - UINT32 Dummy; - - if (!NBPtr->MCTPtr->Status[SbRegistered]) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); - // if chip select present - NBPtr->TechPtr->SendAllMRCmds (NBPtr->TechPtr, ChipSel); - // NOTE: wait 512 clocks for DLL-relock - MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us - } - } - } - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes before DRAM init - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNBeforeDramInitHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - //Set PllLockTime and DllLockTime to default. - MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0); - MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190); - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Enable DLL Shut down - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNEnDLLShutDownHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - BOOLEAN DllShutDownEn; - - DllShutDownEn = TRUE; - IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader)); - - if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) { - if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C); - MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D); - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); - } - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Workaround for erratum 322 and 263 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNBeforePlatformSpecHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // Errata 263 - if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) { - MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800); - } else { - MemNSetBitFieldNb (NBPtr, BFErr263, 0); - } - - // Errata 322 - // 1.Write 00000000h to F2x[1,0]9C_xD08E000 - MemNSetBitFieldNb (NBPtr, BFErr322I, 0); - // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is - // greater than or equal to 011b (DDR-800 and higher), - // then write 00000080h to F2x[1,0]9C_xD02E001, - // else write 00000090h to F2x[1,0]9C_xD02E001. - MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * Initializes extended MMIO address space - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - */ -BOOLEAN -MemNInitExtMMIOAddrHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Index; - UINT32 Value; - PCI_ADDR PciAddr; - - if (NBPtr->RefPtr->SysLimit >= _1TB_RJ16) { - // Initialize all indices of F1x114_x2 and F1x114_x3. - for (Index = 0; Index < 32; Index++) { - PciAddr = NBPtr->PciAddr; - PciAddr.Address.Function = 1; - - PciAddr.Address.Register = 0x110; - Value = 0x20000000 | Index; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - - PciAddr.Address.Register = 0x114; - Value = 0; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - - PciAddr.Address.Register = 0x110; - Value = 0x30000000 | Index; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - - PciAddr.Address.Register = 0x114; - Value = 0; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - } - } - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c deleted file mode 100644 index 588f27a824..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c +++ /dev/null @@ -1,134 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnflowhy.c - * - * Hydra initializer for MCT and DCT - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mnhy.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNFLOWHY_FILECODE -/* features */ - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the platform specific block - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - AGESA_SUCCESS at least one dorm factor was found - * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found - */ - -BOOLEAN -MemNPlatformSpecificFormFactorInitHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 f; - UINT8 ErrUnSuppFFCount; - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->ChannelPtr->ChDimmValid != 0) { - ErrUnSuppFFCount = 0; - for (f = 0; f < MAX_FF_TYPES; f++) { - ASSERT (memPlatSpecFFInstalledHy[f] != NULL); - if (memPlatSpecFFInstalledHy[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { - ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors - } else { - break; - } - } - if (ErrUnSuppFFCount == MAX_FF_TYPES) { - return FALSE; // No FF types are supported - } - } - } - return TRUE; -} -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c deleted file mode 100644 index 16f6b13c94..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c +++ /dev/null @@ -1,496 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnhy.c - * - * Common Northbridge functions for Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnhy.h" -#include "mu.h" -#include "S3.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNHY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -#define SPLIT_CHANNEL (UINT32) 0x20000000 -#define CHANNEL_SELECT (UINT32) 0x10000000 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB - * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA - * @param[in] NodeID - UINT8 indicating node ID of the NB object. - * - * @return Boolean indicating that this is the correct memory - * controller type for the node number that was passed in. - */ - -BOOLEAN -MemConstructNBBlockHY ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *SharedPtr, - IN UINT8 NodeID - ) -{ - UINT8 Dct; - UINT8 Channel; - UINT8 SpdSocketIndex; - UINT8 SpdChannelIndex; - DIE_STRUCT *MCTPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->MemPtr = MemPtr; - NBPtr->RefPtr = MemPtr->ParameterListPtr; - NBPtr->SharedPtr = SharedPtr; - - MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->MCTPtr = MCTPtr; - NBPtr->MCTPtr->NodeId = NodeID; - NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; - NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - - // - // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs - // - AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_HY * ( - sizeof (DCT_STRUCT) + ( - MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) - ) - ); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs - return FALSE; - } - - MCTPtr->DctCount = MAX_DCTS_PER_NODE_HY; - MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_HY * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { - MCTPtr->DctData[Dct].Dct = Dct; - MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_HY; - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; - MCTPtr->DctData[Dct].ChData[0].Dct = Dct; - AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_HY * sizeof (CH_DEF_STRUCT); - } - NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; - - // - // Initialize Socket List - // - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { - MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]); - MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings); - MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; - } - - MemNInitNBDataHy (NBPtr); - - FeatPtr->InitCPG (NBPtr); - NBPtr->FeatPtr = FeatPtr; - FeatPtr->InitHwRxEn (NBPtr); - // - // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel - // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that - // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the - // dimm types(QR or not) are known. This is done in the Technology block constructor. - // - // Calculate the SpdSocketIndex separately from the SpdChannelIndex. - // This will facilitate modifications due to some processors that might - // map the DCT-CHANNEL differently. - // - SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); - // - // Traverse the Dct/Channel structures - // - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { - for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_HY; Channel++) { - // - // Calculate the number of Dimms on this channel using the - // die/dct/channel to Socket/channel conversion. - // - SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, - NBPtr->MCTPtr->SocketId, - MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), - &MemPtr->StdHeader); - NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); - } - } - - MemNSwitchDCTNb (NBPtr, 0); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes member functions and variables of NB block. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitNBDataHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->DctCachePtr = NBPtr->DctCache; - NBPtr->PsPtr = NBPtr->PSBlock; - - InitNBRegTableHy (NBPtr, NBPtr->NBRegTable); - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Dct = 0; - NBPtr->Channel = 0; - NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; - NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_HY; - NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; - NBPtr->Ganged = FALSE; - NBPtr->PosTrnPattern = POS_PATTERN_256B; - NBPtr->MemCleared = FALSE; - NBPtr->StartupSpeed = DDR800_FREQUENCY; - NBPtr->RcvrEnDlyLimit = 0x1FF; - NBPtr->DefDctSelIntLvAddr = 3; - NBPtr->CsRegMsk = 0x1FF83FE0; - - LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); - - NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; - NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; - NBPtr->InitializeMCT = MemNInitializeMctHy; - NBPtr->FinalizeMCT = MemNFinalizeMctHy; - NBPtr->SendMrsCmd = MemNSendMrsCmdHy; - NBPtr->sendZQCmd = MemNSendZQCmdNb; - NBPtr->WritePattern = MemNWritePatternHy; - NBPtr->ReadPattern = MemNReadPatternHy; - NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; - NBPtr->CompareTestPattern = MemNCompareTestPatternNb; - NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; - NBPtr->StitchMemory = MemNStitchMemoryNb; - NBPtr->AutoConfig = MemNAutoConfigHy; - NBPtr->PlatformSpec = MemNPlatformSpecNb; - NBPtr->InitMCT = MemNInitMCTNb; - NBPtr->DisableDCT = MemNDisableDCTNb; - NBPtr->StartupDCT = MemNStartupDCTNb; - NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; - NBPtr->ChangeFrequency = MemNChangeFrequencyNb; - NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; - NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse; - NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; - NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; - NBPtr->HtMemMapInit = MemNHtMemMapInitNb; - NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; - NBPtr->CpuMemTyping = MemNCPUMemTypingNb; - NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingHy; - NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->OtherTiming = MemNOtherTimingHy; - NBPtr->UMAMemTyping = MemNUMAMemTypingNb; - NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy; - NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; - NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb; - NBPtr->TrainingFlow = (VOID (*) (MEM_NB_BLOCK *)) MemNTrainingFlowNb; - MemNInitNBDataNb (NBPtr); - NBPtr->PollBitField = MemNPollBitFieldNb; - NBPtr->BrdcstCheck = MemNBrdcstCheckNb; - NBPtr->BrdcstSet = MemNBrdcstSetNb; - NBPtr->GetTrainDly = MemNGetTrainDlyNb; - NBPtr->SetTrainDly = MemNSetTrainDlyNb; - NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; - NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; - NBPtr->RankEnabled = MemNRankEnabledNb; - NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitHy; - NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; - NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; - NBPtr->MemNInitPhyComp = MemNInitPhyCompHy; - NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecHy; - NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitHy; - NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, INT16 *)) memDefRet; - NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; - NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; - NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; - NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; - NBPtr->CSPerChannel = MemNCSPerChannelNb; - NBPtr->CSPerDelay = MemNCSPerDelayNb; - NBPtr->FlushPattern = MemNFlushPatternNb; - NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; - NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->GetUmaSize = MemNGetUmaSizeNb; - NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; - NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet; - NBPtr->WaitXMemClks = MemNWaitXMemClksNb; - NBPtr->MemNGetDramTerm = MemNGetDramTermNb; - NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; - NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; - NBPtr->MemNGetMR0WR = MemNGetMR0WRNb; - NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; - NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; - NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - - NBPtr->IsSupported[SetSpareEn] = TRUE; - NBPtr->IsSupported[CheckSpareEn] = TRUE; - NBPtr->IsSupported[SetDllShutDown] = TRUE; - NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE; - NBPtr->IsSupported[CheckMaxDramRate] = TRUE; - NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE; - NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; - NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; - NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE; - NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE; - NBPtr->IsSupported[CheckODTControls] = TRUE; - NBPtr->IsSupported[CheckDummyCLRead] = TRUE; - NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE; - NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; - NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; - - NBPtr->FamilySpecificHook[SendMrsCmdsPerCs] = MemNSendMrsCmdPerCsHy; - NBPtr->FamilySpecificHook[InitExtMMIOAddr] = MemNInitExtMMIOAddrHy; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the default values in the MEM_DATA_STRUCT - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - */ -VOID -MemNInitDefaultsHY ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT8 Socket; - UINT8 Channel; - MEM_PARAMETER_STRUCT *RefPtr; - ASSERT (MemPtr != NULL); - RefPtr = MemPtr->ParameterListPtr; - - // Memory Map/Mgt. - // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB - RefPtr->BottomIo = 0xE0; - RefPtr->UmaMode = UserOptions.CfgUmaMode; - RefPtr->UmaSize = UserOptions.CfgUmaSize; - RefPtr->MemHoleRemapping = TRUE; - RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb; - // - - - // Dram Timing - RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; - RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; - for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { - for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { - MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; - MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; - } - } - - // Memory Clear - RefPtr->EnableMemClr = TRUE; - - // TableBasedAlterations - RefPtr->TableBasedAlterations = NULL; - - // Platform config table - RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; - - // Memory Restore - RefPtr->MemRestoreCtl = FALSE; - RefPtr->SaveMemContextCtl = FALSE; - AmdS3ParamsInitializer (&RefPtr->MemContext); - - // Dram Configuration - RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; - RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; - RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; - RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; - RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; - RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; - - // Dram Power - RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; - - // ECC - RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; - - // Vref - RefPtr->ExternalVrefCtl = UserOptions.CfgExternalVrefCtlFeature; - - //Training Mode - RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode; -} -/*-----------------------------------------------------------------------------*/ -/** - * - * This function writes training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Pattern[] - Pattern to write - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNWritePatternHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUWriteCachelines (Address, Pattern, ClCount); -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function reads training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer to fill - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNReadPatternHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUReadCachelines (Buffer, Address, ClCount); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates DQS training for Server NB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -memNEnableTrainSequenceHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BOOLEAN Retval; - Retval = TRUE; - if (!MemNIsIdSupportedHy (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { - Retval = FALSE; - } - return Retval; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h deleted file mode 100644 index a2379fc26d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h +++ /dev/null @@ -1,212 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnhy.h - * - * Northbridge Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 47408 $ @e \$Date: 2011-02-18 09:56:31 -0700 (Fri, 18 Feb 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _MNHY_H_ -#define _MNHY_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ -#define MAX_CHANNELS_PER_SOCKET_HY 4 -#define MAX_DCTS_PER_NODE_HY 2 -#define MAX_CHANNELS_PER_DCT_HY 1 -#define MAX_NODES_SUPPORTED_HY 8 - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemConstructNBBlockHY ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *SharedPtr, - IN UINT8 NodeID - ); - -VOID -MemNInitNBDataHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitDefaultsHY ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -BOOLEAN -MemNInitializeMctHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNFinalizeMctHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNSendMrsCmdHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNAutoConfigHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNOtherTimingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitPhyCompHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNWritePatternHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -MemNReadPatternHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -InitNBRegTableHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT TSEFO NBRegTable[] - ); - -UINT8 -MemNGetSocketRelativeChannelHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct, - IN UINT8 Channel - ); - -BOOLEAN -MemNIsIdSupportedHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID *LogicalIdPtr - ); - -VOID -MemNBeforeDramInitHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNPlatformSpecificFormFactorInitHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNEnDLLShutDownHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -UINT32 -MemNCmnGetSetFieldHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ); - -VOID -MemNBeforePlatformSpecHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -memNEnableTrainSequenceHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNSendMrsCmdPerCsHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *DummyPtr - ); - -BOOLEAN -MemNInitExtMMIOAddrHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -VOID -MemNBeforeDQSTrainingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MNHY_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c deleted file mode 100644 index fdfa5ead3c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c +++ /dev/null @@ -1,140 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnidendimmhy.c - * - * Hy northbridge constructor for dimm identification translator. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 45911 $ @e \$Date: 2011-01-24 13:55:11 -0700 (Mon, 24 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnhy.h" -#include "mfidendimm.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for dimm identification translator - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in,out] NodeID - ID of current node to construct - * @return TRUE - This is the correct constructor for the targeted node. - * @return FALSE - This isn't the correct constructor for the targeted node. - */ - -BOOLEAN -MemNIdentifyDimmConstructorHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; - NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; - NBPtr->CsRegMsk = 0x1FF83FE0; - NBPtr->MemPtr = MemPtr; - NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Ganged = FALSE; - InitNBRegTableHy (NBPtr, NBPtr->NBRegTable); - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->SetBitField = MemNSetBitFieldNb; - NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy; - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c deleted file mode 100644 index 91580b745d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c +++ /dev/null @@ -1,213 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnmcthy.c - * - * Northbridge Hydra MCT supporting functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnhy.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNMCTHY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets final values in BUCFG and BUCFG2 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNFinalizeMctHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - DRAM_PREFETCH_MODE DramPrefetchMode; - S_UINT64 SMsr; - UINT16 Speed; - UINT32 ExtMctCfgLoRegVal; - - MemPtr = NBPtr->MemPtr; - DramPrefetchMode = MemPtr->PlatFormConfig->PlatformProfile.AdvancedPerformanceProfile.DramPrefetchMode; - Speed = NBPtr->DCTPtr->Timings.Speed; - MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40); - - ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg); - ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001; - - ExtMctCfgLoRegVal &= 0x0FFFFFFF; - if (Speed == DDR667_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x40000000; - } else if (Speed == DDR800_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x50000000; - } else if (Speed == DDR1066_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x60000000; - } else if (Speed == DDR1333_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x80000000; - } else { - ExtMctCfgLoRegVal |= 0x90000000; - } - // - // PrefFiveConf, PrefFourConf - // - ExtMctCfgLoRegVal |= 0x0FC00000; - // - // EnSplitDctLimits - // - if (!NBPtr->Ganged) { - ExtMctCfgLoRegVal |= 0x00001000; - } - MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal); - if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_IO || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { - MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 1); - } - - if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_CPU || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { - MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1); - } - - if (NBPtr->Node == BSP_DIE) { - if (!NBPtr->ClToNbFlag) { - LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis - LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - } - - LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis - LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - } - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets initial values in BUCFG and BUCFG2 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNInitializeMctHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - S_UINT64 SMsr; - - MemPtr = NBPtr->MemPtr; - - if (NBPtr->Node == BSP_DIE) { - LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - if (SMsr.lo & ((UINT32)1 << 15)) { - NBPtr->ClToNbFlag = 1; - } - SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis - LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis - LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c deleted file mode 100644 index 1c6cab087c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c +++ /dev/null @@ -1,247 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnothy.c - * - * Northbridge Non-SPD timings for Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnhy.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNOTHY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -MemNSetOtherTimingHY ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/* -UINT32 -STATIC -MemNGetODTDelaysHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -*/ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the non-SPD timings - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNOtherTimingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSwitchDCTNb (NBPtr, 0); - if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { - MemNSetOtherTimingHY (NBPtr); - MemNPowerDownCtlNb (NBPtr); - MemNEnDLLShutDownHy (NBPtr); - } - - MemNSwitchDCTNb (NBPtr, 1); - if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) { - MemNSetOtherTimingHY (NBPtr); - MemNPowerDownCtlNb (NBPtr); - MemNEnDLLShutDownHy (NBPtr); - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the non-SPD timings in PCI registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemNSetOtherTimingHY ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - - MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the ODT delays - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -/* -UINT32 -STATIC -MemNGetODTDelaysHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - INT8 Ld; - UINT32 ODTDelays; - // - // On revision D processors, the BIOS must additionally configure the ODT pattern - // and the ODT switching delays. - // - // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length. - // -Read the Burst Length from F2x[1, 0]84[BurstCtrl]. - // -Value of 2, BL = 4 else assume BL=8. - // -Initialize ODTDelays based on BL value - // -WrOdtOnDuration [14:12] = BL / 2 + 1 - // -WrOdtTrnOnDly [10:8] = 0 - // -RdOdtOnDuration [6:4] = BL / 2 + 1 - // - ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050; - - // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1) - // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0] - Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); - if (Ld < 0) { - Ld = 0; - } - if (Ld > 7) { - Ld = 7; - } - ODTDelays += Ld; - return ODTDelays; -} -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function enables power down mode - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -/* -VOID -STATIC -MemNPowerDownCtlHY ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_PARAMETER_STRUCT *RefPtr; - UINT8 PowerDownMode; - - RefPtr = NBPtr->RefPtr; - - // we can't enable powerdown mode when doing WL - if (RefPtr->EnablePowerDown) { - MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); - PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; - IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); - if (PowerDownMode) { - MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); - } - } -} -*/ \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c deleted file mode 100644 index d7b587b492..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c +++ /dev/null @@ -1,238 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnphyHy.c - * - * Northbridge Phy support for Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "ma.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnhy.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNPHYHY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DDR phy compensation logic - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitPhyCompHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2}; - CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2}; - CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2}; - CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3}; - UINT8 i; - UINT8 j; - UINT8 CurrDct; - UINT8 MaxDimmsPerChannel; - UINT8 *DimmsPerChPtr; - - CurrDct = NBPtr->Dct; - - // - // Get Platform Information - // - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmsPerChannel = *DimmsPerChPtr; - } else { - MaxDimmsPerChannel = 2; - } - - // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1 - // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. - // DisAutoComp will be cleared after Dram init has completed - // - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); - MemUWait10ns (500, NBPtr->MemPtr); - MemNSwitchDCTNb (NBPtr, CurrDct); - - // 3. For each normalized driver strength code read from - // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the - // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal]. - // - // 4. For each normalized driver strength code read from - // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding - // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal, - // D3Cmp2PCal]. - // - j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren); - i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren); - - MemNSwitchDCTNb (NBPtr, 0); - ASSERT (j <= 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]); - - ASSERT (i <= 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]); - - // - // Special Case for certain configs - // - // 3DPCH Fully populated. - if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) { - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 5); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 5); - } - - MemNSwitchDCTNb (NBPtr, CurrDct); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes before DRAM training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNBeforeDQSTrainingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 ChipSel; - UINT32 TestAddrRJ16; - UINT32 RealAddr; - - MemTBeginTraining (NBPtr->TechPtr); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) { - - RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr); - - MemUDummyCLRead (RealAddr); - - MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); - MemUWait10ns (60, NBPtr->MemPtr); // Wait 300ns - MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); - MemUWait10ns (400, NBPtr->MemPtr); // Wait 2us - MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr); - break; - } - } - } - if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) { - if (!NBPtr->MCTPtr->Status[SbEccDimms]) { - MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010); - } - if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) { - MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080); - } - } - } - - MemTEndTraining (NBPtr->TechPtr); - - MemNSetBitFieldNb (NBPtr, BFDisDatMsk, 1); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnprotohy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnprotohy.c deleted file mode 100644 index 62288a4fe6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnprotohy.c +++ /dev/null @@ -1,66 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnprotohy.c - * - * Northbridge support functions for Errata and early samples - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - - -#include "AGESA.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNPROTOHY_FILECODE - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c deleted file mode 100644 index 5177cec4bd..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c +++ /dev/null @@ -1,639 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnreghy.c - * - * Common Northbridge register related functions for Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnhy.h" -#include "merrhdl.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNREGHY_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*-----------------------------------------------------------------------------*/ -/** - * MemNIsIdSupportedHy - * This function matches the CPU_LOGICAL_ID with certain criteria to - * determine if it is supported by this NBBlock. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID - * - * @return TRUE - This node is a Hydra. - * @return FALSE - This node is not a Hydra. - * - */ -BOOLEAN -MemNIsIdSupportedHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID *LogicalIdPtr - ) -{ - if (((LogicalIdPtr->Family & AMD_FAMILY_10_HY) != 0) - && ((LogicalIdPtr->Revision & AMD_F10_HY_ALL) != 0)) { - return TRUE; - } else { - return FALSE; - } -} - -/*-----------------------------------------------------------------------------*/ -/** - * This function calculates the memory channel index relative to the - * socket, taking the Die number, the Dct, and the channel. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Dct - * @param[in] Channel - * - */ -UINT8 -MemNGetSocketRelativeChannelHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct, - IN UINT8 Channel - ) -{ - return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_HY) + Dct); -} -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets or sets a value to a bit field in a PCI register. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Bit Field to be programmed - * @param[in] Field - Value to be programmed - * @param[in] IsSet - Indicates if the function will set or get - * - * @return value read, if the function is used as a "get" - */ - -UINT32 -MemNCmnGetSetFieldHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ) -{ - TSEFO Address; - PCI_ADDR PciAddr; - UINT8 Type; - UINT8 IsLinked; - UINT32 Value; - UINT32 Highbit; - UINT32 Lowbit; - UINT32 Mask; - - Value = 0; - if (FieldName < BFEndOfList) { - Address = NBPtr->NBRegTable[FieldName]; - if (Address) { - Lowbit = TSEFO_END (Address); - Highbit = TSEFO_START (Address); - Type = (UINT8) TSEFO_TYPE (Address); - IsLinked = (UINT8) TSEFO_LINKED (Address); - - // If Fn2 and DCT1 selected, set Address to be 1xx - if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { - if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) { - Address |= 0x0100; - } - } - - ASSERT ((Address & ((UINT32) 1) << 28) == 0); // Phy direct access method is not supported - - if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { - // Special DCT Phy access - Address &= 0x0FFFFFFF; - Lowbit = 0; - Highbit = 16; - IsLinked = 0; - } else { - // Normal DCT Phy access - Address = TSEFO_OFFSET (Address); - } - - if (Type == NB_ACCESS) { - PciAddr.AddressValue = Address; - PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; - PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; - PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; - Address = PciAddr.AddressValue; - LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && - (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); - } - } else if (Type == DCT_PHY_ACCESS) { - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); - } else if (Type == DCT_EXTRA) { - MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg); - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); - } else { - IDS_ERROR_TRAP; - } - - if (IsSet) { - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - if ((Highbit - Lowbit) != 31) { - Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); - } else { - Mask = (UINT32)0xFFFFFFFF; - } - Value &= ~(Mask << Lowbit); - Value |= (Field & Mask) << Lowbit; - - if (Type == NB_ACCESS) { - PciAddr.AddressValue = Address; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && - (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); - } - } else if (Type == DCT_PHY_ACCESS) { - MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); - } else if (Type == DCT_EXTRA) { - MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); - } else { - IDS_ERROR_TRAP; - } - if (IsLinked) { - MemNCmnGetSetFieldHy (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); - } - } else { - Value = Value >> Lowbit; // Shift - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - if ((Highbit - Lowbit) != 31) { - Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); - } - if (IsLinked) { - Value |= MemNCmnGetSetFieldHy (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); - } - } - } - } else { - IDS_ERROR_TRAP; // Invalid bit field index - } - return Value; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes bit field translation table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] NBRegTable[] - Pointer to the bit field data structure - * - */ - -VOID -InitNBRegTableHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT TSEFO NBRegTable[] - ) -{ - UINT16 i; - - // Allocate heap for NB register table - if (!MemNAllocateNBRegTableNb (NBPtr, NbRegTabHY)) { - return; // escape if fails - } - NBRegTable = NBPtr->NBRegTable; - - for (i = 0; i < BFEndOfList; i++) { - NBRegTable[i] = 0; - } - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31, 0, BFExtMctCfgLoReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFReserved00B); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFReserved001); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 7, 7, BFProgOdtEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 12, 12, BFEnSplitDctLimits); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 24, 22, BFPrefFourConf); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 27, 25, BFPrefFiveConf); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x602, 31, 0, BFUSPLLCtlAll); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x603, 31, 0, BFDSPLLCtlAll); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x606, 0, 0, BFUSNibbleAlignEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x690, 2, 2, BFChnLinitClkEn); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFPhyRODTCSLow); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x181, 31, 0, BFPhyRODTCSHigh); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x183, 31, 0, BFPhyWODTCSHigh); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 31, 30, BFTSLinkSelect); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 9, 9, BFTS2BitLockEn); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 8, 8, BFTS2En); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 4, 4, BFTS1En); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 1, 1, BFTS0LinkStarEn); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 0, 0, BFTS0En); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800002, 15, 0, BFLinkTrainData); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 17, 17, BFRstRxFifoPtrs); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 16, 16, BFRxFifoPtrInit); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 1, 1, BFRstTxFifoPtrs); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 0, 0, BFTxFifoPtrInit); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 31, 24, BFLpbkCount); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 21, 20, BFLpbkMap); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 16, 16, BFSendLpbkMaintCmd); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 15, 0, BFLpbkData); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 20, 16, BFMbRdPtrEn); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 9, 4, BFLnkLpBkLat); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 1, 1, BFLpbkRndTripLatDone); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 0, 0, BFLnkLatTrainEn); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 1, 1, BFDsPhyReset); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 0, 0, BFLinkReset); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime); - - LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); - LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); - LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); - -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/Makefile.inc deleted file mode 100644 index eb029c2692..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -libagesa-y += mn.c -libagesa-y += mnS3.c -libagesa-y += mndct.c -libagesa-y += mnfeat.c -libagesa-y += mnflow.c -libagesa-y += mnmct.c -libagesa-y += mnphy.c -libagesa-y += mnreg.c -libagesa-y += mntrain3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/Makefile.inc deleted file mode 100644 index 8a8963e347..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -libagesa-y += mndctor.c -libagesa-y += mnflowor.c -libagesa-y += mnidendimmor.c -libagesa-y += mnmctor.c -libagesa-y += mnor.c -libagesa-y += mnotor.c -libagesa-y += mnpartrainor.c -libagesa-y += mnphyor.c -libagesa-y += mnprotoor.c -libagesa-y += mnregor.c -libagesa-y += mns3or.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnS3or.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnS3or.h deleted file mode 100644 index e40b25c739..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnS3or.h +++ /dev/null @@ -1,85 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnS3or.h - * - * S3 resume memory related function for OR. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/OR) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _MNS3OR_H_ -#define _MNS3OR_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ -/// ID for register list of OR -typedef enum { - PCI_LST_ESR_OR, ///< Assign 0x0000 for PCI register list for pre exit self refresh. - PCI_LST_OR, ///< Assign 0x0001 for PCI register list for post exist self refresh. - CPCI_LST_ESR_OR, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. - CPCI_LST_OR, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. - MSR_LST_ESR_OR, ///< Assign 0x0004 for MSR register list for pre exit self refresh. - MSR_LST_OR, ///< Assign 0x0005 for MSR register list for post exit self refresh. - CMSR_LST_ESR_OR, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. - CMSR_LST_OR ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. -} RegisterListIDOr; - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define SET_S3_NB_PSTATE_OFFSET(Offset, NBPstate) ((NBPstate << 10) | Offset) - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -#endif //_MNS3OR_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mndctor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mndctor.c deleted file mode 100644 index 5283ecd363..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mndctor.c +++ /dev/null @@ -1,975 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mndctOr.c - * - * Northbridge DCT support for Orochi - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/OR) - * @e \$Revision: 60556 $ @e \$Date: 2011-10-17 20:19:58 -0600 (Mon, 17 Oct 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnor.h" -#include "merrhdl.h" -#include "cpuFamRegisters.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuCommonF15Utilities.h" -#include "F15PackageType.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_NB_OR_MNDCTOR_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 -#define MAX_RD_DQS_DLY 0x1F - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -UINT32 -STATIC -MemNTotalSyncComponentsOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs the memory controller with configuration parameters - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value - */ - -BOOLEAN -MemNAutoConfigOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - UINT8 NumDimmslots; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_PARAMETER_STRUCT *RefPtr; - MEM_PS_BLOCK * PsPtr; - BOOLEAN ExtraAddrBits; - BOOLEAN RankMultEn; - UINT8 ROOD; - - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - PsPtr = NBPtr->PsPtr; - - ExtraAddrBits = FALSE; - RankMultEn = FALSE; - - ROOD = DEFAULT_RD_ODT_OR; - // - // Check for Extra Address bit requirement for LRDIMMs - // - if (MCTPtr->Status[SbLrdimms]) { - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if (PsPtr->LrdimmRowAddrBits[i] > 16) { - ExtraAddrBits = TRUE; - } - if (NBPtr->ChannelPtr->LrDimmRankMult[i] > 1) { - RankMultEn = TRUE; - } - } - } - - NumDimmslots = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, - MCTPtr->SocketId, - NBPtr->ChannelPtr->ChannelID); - // - //====================================================================== - // Build Dram Config Lo Register Value - //====================================================================== - // - // Disable Parity Prior to Dram init - // - MemNSetBitFieldNb (NBPtr, BFParEn, 0); - // - // LRDIMMS Extended Parity - // - MemNSetBitFieldNb (NBPtr, BFExtendedParityEn, 0); - // - // X4Dimm - // - MemNSetBitFieldNb (NBPtr, BFX4Dimm, NBPtr->ChannelPtr->DimmNibbleAccess & 0xF); - // - // UnBuffDimm - // - if (!(MCTPtr->Status[SbRegistered] || MCTPtr->Status[SbLrdimms])) { - MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); - } - // - // DimmEccEn - // - if (MCTPtr->Status[SbEccDimms]) { - MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); - } - // - // PendRefPayback, StatgRefEn, TStag[0:4] - // - MemNSetBitFieldNb (NBPtr, BFPendRefPaybackS3En, 1); - MemNSetBitFieldNb (NBPtr, BFStagRefEn, 1); - for (i = 0; i < 4; i++) { - MemNSetBitFieldNb (NBPtr, BFTstag0 + i, 0x14); - } - // - //====================================================================== - // Build Dram Config Hi Register Value - //====================================================================== - // - // - // MemClkFreq - // - MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, DCTPtr->Timings.Speed)); - // - // FourRankRDimm0 , FourRankRDimm1 ( Reset Values are 0) - // - //====================================================================== - // Build Dram MRS Register Value (Not used for MRS command) - //====================================================================== - // - // PchgPDModeSel - This is done here so that the value can be used by - // MR0 function - // - if (NBPtr->IsSupported[PchgPDMode]) { - MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, 1); - } - MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 0); - - //====================================================================== - // Build Dram Config Misc Register Value - //====================================================================== - // - // - // LRDIMMs CSMux45 and CSMux67 - // - if (MCTPtr->Status[SbLrdimms]) { - if (NumDimmslots == 3) { - MemNSetBitFieldNb (NBPtr, BFCSMux45, 0); - MemNSetBitFieldNb (NBPtr, BFCSMux67, ExtraAddrBits ? 1 : 0); - } else if (NumDimmslots <= 2) { - MemNSetBitFieldNb (NBPtr, BFCSMux45, (PsPtr->LrdimmRowAddrBits[0] > 16) ? 1 : 0); - MemNSetBitFieldNb (NBPtr, BFCSMux67, (PsPtr->LrdimmRowAddrBits[1] > 16) ? 1 : 0); - } - } - // - // LrDimmMrsCtrl - // - MemNSetBitFieldNb (NBPtr, BFLrDimmMrsCtrl, RankMultEn ? 1 : 0); - // - // BFLrDimmEnhRefEn - // - MemNSetBitFieldNb (NBPtr, BFLrDimmEnhRefEn, RankMultEn ? 1 : 0); - // - // SubMemclkRegDly - // - MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, (MCTPtr->Status[SbRegistered] || MCTPtr->Status[SbLrdimms])? 1 : 0); - //====================================================================== - // Other Registers - //====================================================================== - // - // - // Non-SPD Timings - // - MemNSetBitFieldNb (NBPtr, BFTrwtWB, 0x17); - MemNSetBitFieldNb (NBPtr, BFTrwtTO, 0x16); - MemNSetBitFieldNb (NBPtr, BFTwrrd, 0xB ); - - MemNSetBitFieldNb (NBPtr, BFTrdrdSdSc, 0xB); - MemNSetBitFieldNb (NBPtr, BFTrdrdSdDc, 0xB); - MemNSetBitFieldNb (NBPtr, BFTrdrdDd, 0xB); - - MemNSetBitFieldNb (NBPtr, BFTwrwrSdSc, 0xB); - MemNSetBitFieldNb (NBPtr, BFTwrwrSdDc, 0xB); - MemNSetBitFieldNb (NBPtr, BFTwrwrDd, 0xB); - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - ROOD = ROOD + (UINT8) (MemNCalBufDatDelaySkewOr (NBPtr, GetBufDatDlySkew)); - } - MemNSetBitFieldNb (NBPtr, BFWrOdtOnDuration, DEFAULT_WR_ODT_OR); - MemNSetBitFieldNb (NBPtr, BFRdOdtOnDuration, ROOD); - MemNSetBitFieldNb (NBPtr, BFWrOdtTrnOnDly, 0); - - MemNSetBitFieldNb (NBPtr, BFTmrd, (NBPtr->MCTPtr->Status[SbLrdimms] ? 6 : 4)); - - MemNSetBitFieldNb (NBPtr, BFFlushWrOnS3StpGnt, 1); - MemNSetBitFieldNb (NBPtr, BFFastSelfRefEntryDis, 0); - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function caps speed based on battery life check. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - */ -VOID -MemNCapSpeedBatteryLifeOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT16 SupportedFreq[] = { - DDR1866_FREQUENCY, - DDR1600_FREQUENCY, - DDR1333_FREQUENCY, - DDR1066_FREQUENCY, - DDR800_FREQUENCY, - DDR667_FREQUENCY - }; - - UINT32 FreqNumeratorInMHz; - UINT32 FreqDivisor; - UINT32 VoltageInuV; - UINT32 NBFreq; - UINT16 DdrFreq; - UINT16 j; - INT8 NbPs; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - FamilySpecificServices = NULL; - GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &(NBPtr->MemPtr->StdHeader)); - - // Find the lowest supported NB Pstate - NBFreq = 0; - for (NbPs = 3; NbPs >= 0; NbPs--) { - if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, - NBPtr->MemPtr->PlatFormConfig, - &NBPtr->PciAddr, - (UINT32) NbPs, - &FreqNumeratorInMHz, - &FreqDivisor, - &VoltageInuV, - &(NBPtr->MemPtr->StdHeader))) { - NBFreq = FreqNumeratorInMHz / FreqDivisor; - break; - } - } - - ASSERT (NBFreq > 0); - - // Pick Max MEMCLK that is less than or equal to (NCLK / 2) - DdrFreq = DDR800_FREQUENCY; - for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) { - if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) { - DdrFreq = SupportedFreq[j]; - break; - } - } - - // Cap MemClk frequency to lowest NCLK frequency - if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) { - NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq; - } - - // Initialize NbPsCtlReg - NBPtr->NbPsCtlReg = 0; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function retrieves the Max latency parameters - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @param[in] *MinDlyPtr - Pointer to variable to store the Minimum Delay value - * @param[in] *MaxDlyPtr - Pointer to variable to store the Maximum Delay value - * @param[in] *DlyBiasPtr - Pointer to variable to store Delay Bias value - * @param[in] MaxRcvEnDly - Maximum receiver enable delay value - */ - -VOID -MemNGetMaxLatParamsOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxRcvEnDly, - IN OUT UINT16 *MinDlyPtr, - IN OUT UINT16 *MaxDlyPtr, - IN OUT UINT16 *DlyBiasPtr - ) -{ - UINT32 N; - UINT32 T; - UINT32 P; - UINT32 MemClkPeriod; - - // 1. P = N = T = 0. - P = N = T = 0; - - // Get all sync components BKDG steps 3,4,6,7 - P = MemNTotalSyncComponentsOr (NBPtr); - - // 8. P = P + CEIL(MAX(D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] + - // D18F2x9C_x0000_0[3:0]0[7:5]_dct[1:0][RdDqsTime] PCLKs)) - P = P + (MaxRcvEnDly + 31) / 32; - - // 10. T = T + 800 ps - T += 800; - - // 11. N = (P/(MemClkFreq * 2) + T) * NclkFreq; Convert from PCLKs plus time to NCLKs. - MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; - N = ((((P * MemClkPeriod + 1) / 2) + T) * NBPtr->NBClkFreq + 999999) / 1000000; - - // 13. D18F2x210_dct[1:0]_nbp[3:0][MaxRdLatency] = CEIL(N) - 1 - N = N - 1; - - // Calculate a starting MaxRdLatency delay value with steps 5, 9, and 12 excluded - *MinDlyPtr = (UINT16) N; - - *MaxDlyPtr = 0x3FF; - - // Left edge of MaxRdLat will be added with 1 NCLK and 3 PCLK - N = 1; - P = 3; - N += (((P * MemClkPeriod + 1) / 2) * NBPtr->NBClkFreq + 999999) / 1000000; - *DlyBiasPtr = (UINT16) N; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the maximum round-trip latency in the system from the processor to the DRAM - * devices and back. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] MaxRcvEnDly - Maximum receiver enable delay value - * - */ - -VOID -MemNSetMaxLatencyOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxRcvEnDly - ) -{ - UINT32 N; - UINT32 T; - UINT32 P; - UINT32 MemClkPeriod; - - AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader)); - - // - // Initial value for MaxRdLat used in training - // - N = 0x55; - - if (MaxRcvEnDly != 0xFFFF) { - // 1. P = N = T = 0. - P = N = T = 0; - - // Get all sync components BKDG steps 3,4,6,7 - P = MemNTotalSyncComponentsOr (NBPtr); - - // 5. P = P + 5 - P += 5; - - // 8. P = P + CEIL(MAX(D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] + - // D18F2x9C_x0000_0[3:0]0[7:5]_dct[1:0][RdDqsTime] PCLKs)) - P = P + ((MaxRcvEnDly + MAX_RD_DQS_DLY) + 31) / 32; - - // 9. P = P + 5 - P += 5; - - // 10. T = T + 800 ps - T += 800; - - // 11. N = (P/(MemClkFreq * 2) + T) * NclkFreq; Convert from PCLKs plus time to NCLKs. - MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; - N = ((((P * MemClkPeriod + 1) / 2) + T) * NBPtr->NBClkFreq + 999999) / 1000000; - - // 12. N = N - 1. See step 9. - N = N - 1; - - // 13. D18F2x210_dct[1:0]_nbp[3:0][MaxRdLatency] = CEIL(N) - 1 - N = N - 1; - } - - NBPtr->DCTPtr->Timings.MaxRdLat = (UINT16) N; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", N); - MemNSetBitFieldNb (NBPtr, BFMaxLatency, N); -} - -/*----------------------------------------------------------------------------- - * - * - * This function set MaxRdLat after HW receiver enable training is completed - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNExitPhyAssistedTrainingOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Dct; - UINT8 ChipSel; - MEM_TECH_BLOCK *TechPtr; - - TechPtr = NBPtr->TechPtr; - - MemNReEnablePhyCompNb (NBPtr, NULL); - - // Calculate Max Latency for both channels to prepare for position training - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - // - // For Orochi, we need to reset DisAutoRefresh and ZqcsInterval for - // Position training. - // - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); - MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); - } - - if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) { - NBPtr->SetMaxLatency (NBPtr, TechPtr->MaxDlyForMaxRdLat); - } - } - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*----------------------------------------------------------------------------- - * - * This function send control words after MEMCLK frequency change - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNAfterMemClkFreqChgOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Dct; - MEM_TECH_BLOCK *TechPtr; - - TechPtr = NBPtr->TechPtr; - - // Reprogram the DIMMs' buffers right after MEMCLK frequency change - if (!(TechPtr->TechnologySpecificHook[LrdimmFreqChgCtrlWrd] (TechPtr, NULL))) { - if (NBPtr->MCTPtr->Status[SbRegistered]) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - TechPtr->FreqChgCtrlWrd (TechPtr); - } - } - } - } - - return TRUE; -} - -/*----------------------------------------------------------------------------- - * - * This function modifies CS tri-state bit map - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] CsTriBitmap - Bitmap of chipselects to be tristated - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNBeforeSetCsTriOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *CsTriBitmap - ) -{ - // - // The tri-state of CS[7:4] for LrDIMM should be determined by - // D18F2xA8_dct[1:0][CsMux45]/[CsMux67] - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - if (MemNGetBitFieldNb (NBPtr, BFCSMux45) == 1) { - *(UINT8*) CsTriBitmap &= 0xCF; - } - if (MemNGetBitFieldNb (NBPtr, BFCSMux67) == 1) { - *(UINT8*) CsTriBitmap &= 0x3F; - } - } - - return TRUE; -} -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the total of sync components for Max Read Latency calculation - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Total in PCLKs - */ -UINT32 -STATIC -MemNTotalSyncComponentsOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 P; - - P = 0; - - // 3. If (D18F2x9C_x0000_0004_dct[1:0][AddrCmdSetup] = 0 & D18F2x9C_x0000_0004_dct[1:0][CsOdt- - // Setup] = 0 & D18F2x9C_x0000_0004_dct[1:0][CkeSetup] = 0) - // then P = P + 1 - // else P = P + 2 - if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) { - P += 1; - } else { - P += 2; - } - - // 4. P = P + (8 - D18F2x210_dct[1:0]_nbp[3:0][RdPtrInit]) + 1 - P = P + (8 - (UINT16) MemNGetBitFieldNb (NBPtr, BFRdPtrInit)) + 1; - - // 6. If (D18F2xA8_dct[1:0][SubMemclkRegDly] = 0 & D18F2x90_dct[1:0][UnbuffDimm] = 0) - // then P = P + 2 - if ((MemNGetBitFieldNb (NBPtr, BFSubMemclkRegDly) == 0) && (MemNGetBitFieldNb (NBPtr, BFUnBuffDimm) == 0)) { - P += 2; - } - - // 7. P = P + (2 * (D18F2x200_dct[1:0][Tcl] - 1 clocks)) - P = P + (2 * (MemNGetBitFieldNb (NBPtr, BFTcl) - 1)); - - return P; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function is used to calculate BufDatDelay and BufDatDelaySkew value. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] GetDelay - Get either BufDatDly or BufDatDlySkew value - * - * @return BufDatDly or BufDatDlySkew value - */ -UINT32 -MemNCalBufDatDelaySkewOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 GetDelay - ) -{ - UINT8 SpdOffset; - UINT8 Dimm; - UINT8 i; - UINT8 j; - UINT32 MinModuleDly; - UINT32 MaxModuleDly; - UINT8 SyncDelay; - UINT32 SmallestModuleDly; - UINT32 LargestModuleDly; - UINT32 BufDatDly; - UINT32 BufDatDlySkew; - MEM_TECH_BLOCK *TechPtr; - UINT8 *SpdBufferPtr; - - TechPtr = NBPtr->TechPtr; - - i = 0; - j = 0; - SmallestModuleDly = 0; - LargestModuleDly = 0; - SyncDelay = 0; - BufDatDly = 0; - BufDatDlySkew = 0; - MinModuleDly = 0xFF; - MaxModuleDly = 0; - SpdOffset = (UINT8) (2 * CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, Dimm)) { - if ((SpdBufferPtr[90 + SpdOffset] & 0x7F) < (UINT8) MinModuleDly) { - MinModuleDly = SpdBufferPtr[90 + SpdOffset] & 0x7F; - i = Dimm; - } - if ((SpdBufferPtr[91 + SpdOffset] & 0x7F) > (UINT8) MaxModuleDly) { - MaxModuleDly = SpdBufferPtr[91 + SpdOffset] & 0x7F; - j = Dimm; - } - } - } - if (!(MinModuleDly >= 0x3C && MinModuleDly <= 0x58)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tMinModuleDly out of range (0x3C - 0x58): %02x\n", MinModuleDly); - } - if (!(MaxModuleDly >= 0x3C && MaxModuleDly <= 0x58)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tMaxModuleDly out of range (0x3C - 0x58): %02x\n", MaxModuleDly); - } - // - //Calculate BufDatDly - // - //SmallestModuleDelay = MinimumModuleDelay * .000125 us * 400 MHz * 0x40. - //MinimumModuleDelay is the minimum SPD module delay across all DIMMs on a channel. - // - SmallestModuleDly = (UINT32) (MinModuleDly * 125 * 400 * 0x40 / 1000000); - // - //SyncDelay = (F0RC2[AddrCmdPrelaunch] ? 0x30 - (2*F1RC12[QCAPrelaunchDelay]) : 0x20) + 0x10. - //SyncDelay is calculated from the SPD values of the MinimumModuleDelay DIMM. - // - TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, i); - SyncDelay = (UINT8) ((((SpdBufferPtr[67] & 0x01) == 1) ? (0x30 - 2 * (SpdBufferPtr[70] & 0x07)) : 0x20) + 0x10); - // - //BufDatDelay = FLOOR((((SmallestModuleDelay - SynchDelay) * (MemClkFreq/400 MHz)) + SynchDelay)/0x40). - // - BufDatDly = (((SmallestModuleDly - SyncDelay) * NBPtr->DCTPtr->Timings.Speed / 400) + SyncDelay) / 0x40; - - if (GetDelay == GetBufDatDly) { - return BufDatDly; - } - // - //Calculate BufDatDlySkew - // - //LargestModuleDelay = MaximumModuleDelay * .000125 us * 400 MHz * 0x40. - //MaximumModuleDelay is the maximum SPD module delay across all DIMMs on a channel. - // - LargestModuleDly = (UINT32) (MaxModuleDly * 125 * 400 * 0x40 / 1000000); - // - //SyncDelay = (F0RC2[AddrCmdPrelaunch] ? 0x30 - (2*F1RC12[QCAPrelaunchDelay]) : 0x20) + 0x10. - //SyncDelay is calculated from the SPD values of the MaximumModuleDelay DIMM. - // - TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, j); - SyncDelay = (UINT8) ((((SpdBufferPtr[67] & 0x01) == 1) ? (0x30 - 2 * (SpdBufferPtr[70] & 0x07)) : 0x20) + 0x10); - // - //BufDatDelaySkew = FLOOR((((LargestModuleDelay - SynchDelay) * (MemClkFreq/400 MHz)) + SynchDelay)/0x40) - BufDatDelay. - // - BufDatDlySkew = ((((((LargestModuleDly - SyncDelay) * NBPtr->DCTPtr->Timings.Speed + 200) / 400) + SyncDelay) - (BufDatDly * 0x40) + 0x20) / 0x40); - - return BufDatDlySkew ; -} -/*----------------------------------------------------------------------------- - * - * This function Enables parity on both DCTs if Parity is supported. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *OptParam - Unused - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNEnableParityAfterMemRstOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - DIE_STRUCT *MCTPtr; - MEM_PS_BLOCK * PsPtr; - UINT8 i; - - MCTPtr = NBPtr->MCTPtr; - PsPtr = NBPtr->PsPtr; - - if (NBPtr->MCTPtr->Status[SbParDimms]) { - // - // SbParDimms should be set for all DDR3 RDIMMS - // Cannot turn off ParEn for DDR3 - // - MemNSetBitFieldNb (NBPtr, BFParEn, 1); - // - // LRDIMMS Extended Parity - // - if (MCTPtr->Status[SbLrdimms]) { - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if (PsPtr->LrdimmRowAddrBits[i] > 16) { - MemNSetBitFieldNb (NBPtr, BFExtendedParityEn, 1); - break; - } - } - } - } - return TRUE; -} - -/*----------------------------------------------------------------------------- - * - * - * This function calculates RdOdtTrnOnDly and RdOdtOnDuration when LrDimms - * are present - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *OptParam - Not Used - * - * @return TRUE - always - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNProgOdtControlOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - DCT_STRUCT *DCTPtr; - UINT8 Tcwl; - UINT8 RdOdtTrnOnDly; - UINT8 RdOdtOnDuration; - - DCTPtr = NBPtr->DCTPtr; - Tcwl = (UINT8) (DCTPtr->Timings.Speed / 133) + 2; - RdOdtTrnOnDly = (DCTPtr->Timings.CasL > Tcwl) ? (DCTPtr->Timings.CasL - Tcwl) : 0; - RdOdtOnDuration = 6; - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - RdOdtTrnOnDly = RdOdtTrnOnDly + (UINT8) MemNCalBufDatDelaySkewOr (NBPtr, GetBufDatDly); - RdOdtOnDuration = RdOdtOnDuration + (UINT8) MemNCalBufDatDelaySkewOr (NBPtr, GetBufDatDlySkew); - } - MemNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, RdOdtTrnOnDly); - MemNSetBitFieldNb (NBPtr, BFRdOdtOnDuration, RdOdtOnDuration); - IDS_HDT_CONSOLE (MEM_FLOW,"\n\t\t\tRdOdtTrnOnDly = %x",RdOdtTrnOnDly); - IDS_HDT_CONSOLE (MEM_FLOW,"\n\t\t\tRdOdtOnDuration = %x\n",RdOdtOnDuration); - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes before DRAM init - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNBeforeDramInitOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_OR; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - // - // 2.10.6.6 DCT Training Specific Configuration - // - MemNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); - MemNSetBitFieldNb (NBPtr, BFForceAutoPchg, 0); - MemNSetBitFieldNb (NBPtr, BFDynPageCloseEn, 0); - MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 0); - MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0); - MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 0); - MemNSetBitFieldNb (NBPtr, BFDisSimulRdWr, 0); - MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0); - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0); - MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, 0); - MemNSetBitFieldNb (NBPtr, BFBwCapEn, 0); - MemNSetBitFieldNb (NBPtr, BFODTSEn, 0); - MemNSetBitFieldNb (NBPtr, BFDctSelIntLvEn, 0); - MemNSetBitFieldNb (NBPtr, BFL3Scrub, 0); - MemNSetBitFieldNb (NBPtr, BFDramScrub, 0); - MemNSetBitFieldNb (NBPtr, BFScrubReDirEn, 0); - MemNSetBitFieldNb (NBPtr, BFL3ScrbRedirDis, 1); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function releases the NB P-state force. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - */ -BOOLEAN -MemNReleaseNbPstateOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - // 6. Restore the initial D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0] values. - MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, (MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFF9FFF) | (NBPtr->NbPsCtlReg & 0x6000)); - - // 7. Restore the initial D18F5x170[NbPstateThreshold, NbPstateHi] values. - MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, (MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFFF13F) | (NBPtr->NbPsCtlReg & 0x0EC0)); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Sets Power Down options and enables Power Down - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * The following registers are set: - * BFPowerDownMode BFPrtlChPDEnhEn - * BFTxp BFAggrPDDelay - * BFTxpDll BFAggrPDEn - * BFPchgPDEnDelay BFPowerDownEn - * - * NOTE: Delay values must be set before turning on the associated Enable bit - */ -VOID -MemNPowerDownCtlOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 PowerDownMode; - UINT8 Tmod; - CONST UINT32 PwrMngm1[] = {0, 0, 0x05050403, 0x05050403, 0x06060403, 0x07070504, 0x08080504, 0x0A0A0605, 0x0B0B0706}; - UINT8 i; - UINT16 Speed; - UINT32 PackageType; - - if (NBPtr->RefPtr->EnablePowerDown) { - PackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader)); - // - // PowerDownMode - // - PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; - PowerDownMode = (!NBPtr->IsSupported[ChannelPDMode]) ? PowerDownMode : 0; - IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); - if (PowerDownMode == 1) { - MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); - } - // - // Txp - // - MemNSetTxpNb (NBPtr); - // - // PchgPDModeSel is set elswhere. - // - Tmod = (UINT8) MemNGetBitFieldNb (NBPtr, BFTmod); - // - // Partial Channel Power Down - // - MemNSetBitFieldNb (NBPtr, BFPrtlChPDDynDly, 2); - MemNSetBitFieldNb (NBPtr, BFPrtlChPDEnhEn, 1); - // - // Aggressive PowerDown - // PchgPDEnDelay: IF (D18F2xA8_dct[1:0][AggrPDEn]) THEN 1 ELSE 0 ENDIF. - // - MemNSetBitFieldNb (NBPtr, BFAggrPDDelay, 0); - if (PackageType != PACKAGE_TYPE_AM3r2) { - MemNSetBitFieldNb (NBPtr, BFAggrPDEn, 1); - MemNSetBitFieldNb (NBPtr, BFPchgPDEnDelay, 1); - } - - // Program DRAM Power Management 1 register - Speed = NBPtr->DCTPtr->Timings.Speed; - i = (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133)); - ASSERT ((i > 1) && (i < sizeof (PwrMngm1))); - MemNSetBitFieldNb (NBPtr, BFDramPwrMngm1Reg, PwrMngm1[i]); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c deleted file mode 100644 index 563c5e8e2d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c +++ /dev/null @@ -1,134 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnflowor.c - * - * Orochi initializer for MCT and DCT - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 51276 $ @e \$Date: 2011-04-20 16:02:17 -0600 (Wed, 20 Apr 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mnor.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_NB_OR_MNFLOWOR_FILECODE -/* features */ - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_TECH_LRDIMM memLrdimmSupported; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function selects appropriate Tech functions for the NB. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNTechBlockSwitchOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - - TechPtr = NBPtr->TechPtr; - - // Specify Dimm-Byte training for Nb - MemTDimmByteTrainInit (TechPtr); - - // Remove the following functions because they are not needed for OR - TechPtr->SetDramMode = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; - TechPtr->SpdCalcWidth = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; - TechPtr->SetDqsEccTmgs = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue; - TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyRdDqsDlyByteUnb; - TechPtr->ResetDCTWrPtr = MemTResetRcvFifoUnb; - - // Initialize LRDIMMs - memLrdimmSupported.MemTInitializeLrdimm (TechPtr); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c deleted file mode 100644 index 26ec28d372..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c +++ /dev/null @@ -1,218 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnidendimmor.c - * - * Or northbridge constructor for dimm identification translator. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/OR) - * @e \$Revision: 51640 $ @e \$Date: 2011-04-26 03:42:21 -0600 (Tue, 26 Apr 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnor.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemNIdentifyDimmConstructorOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -BOOLEAN -STATIC -MemNFixupSysAddrOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *SysAddrPtr - ); - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for dimm identification translator - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in,out] NodeID - ID of current node to construct - * @return TRUE - This is the correct constructor for the targeted node. - * @return FALSE - This isn't the correct constructor for the targeted node. - */ - -BOOLEAN -MemNIdentifyDimmConstructorOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedOr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->NodeCount = MAX_NODES_SUPPORTED_OR; - NBPtr->DctCount = MAX_DCTS_PER_NODE_OR; - NBPtr->CsRegMsk = 0x7FF83FE0; - NBPtr->MemPtr = MemPtr; - NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Ganged = FALSE; - MemNInitNBRegTableOr (NBPtr, NBPtr->NBRegTable); - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldOr; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->SetBitField = MemNSetBitFieldNb; - NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelOr; - NBPtr->FamilySpecificHook[DCTSelectSwitch] = MemNDctCfgSelectUnb; - NBPtr->FamilySpecificHook[FixupSysAddr] = MemNFixupSysAddrOr; - - NBPtr->Dct = 0; - MemNSetBitFieldNb (NBPtr, BFDctCfgSel, 0); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is used to workaround erratum 637 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *SysAddrPtr - Pointer SysAddr variable - * - */ - -BOOLEAN -STATIC -MemNFixupSysAddrOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *SysAddrPtr - ) -{ - UINT64 SysAddr; - UINT8 SourceNode; - UINT8 CoreStateSaveDestNode; - UINT64 Cc6BaseAddress; - UINT32 IntlvEn; - UINT32 IntlvSel; - PCI_ADDR PciAddr; - - // Save NBPtr->PciAddr, so it can be used later to access different node. - PciAddr = NBPtr->PciAddr; - - SysAddr = *((UINT64 *) SysAddrPtr); - if ((SysAddr >> 24) == 0xFDF7) { - // Calculate the address of the source node - SourceNode = (UINT8) ((SysAddr >> 20) & 0x7); - - // Find CoreStateSaveDestNode based on the access source - NBPtr->PciAddr.Address.Device = 0x18 + SourceNode; - CoreStateSaveDestNode = (UINT8) NBPtr->GetBitField (NBPtr, BFCoreStateSaveDestNode); - - // Calculate Cc6BaseAddress from the destination node's DRAM Limit System Address - NBPtr->PciAddr.Address.Device = 0x18 + CoreStateSaveDestNode; - Cc6BaseAddress = ((UINT64) NBPtr->GetBitField (NBPtr, BFDramLimitAddr) << 27); - IntlvEn = NBPtr->GetBitField (NBPtr, BFDramIntlvEn); - - // Check if Node Interleaving is enabled - if (IntlvEn != 0) { - // Node Interleaving is enabled, obtain the interleave position - IntlvSel = NBPtr->GetBitField (NBPtr, BFDramIntlvSel); - *((UINT64 *) SysAddrPtr) = Cc6BaseAddress | ((IntlvEn ^ 0x7) << 24) | ((SysAddr & 0xFFF000) * (IntlvEn + 1)) | (IntlvSel << 12) | (SysAddr & 0xFFF); - } else { - // Node Interleaving is disabled - *((UINT64 *) SysAddrPtr) = Cc6BaseAddress | (0x7 << 24) | (SysAddr & 0xFFFFFF); - } - } - - // Restore NBPtr->PciAddr - NBPtr->PciAddr = PciAddr; - - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnmctor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnmctor.c deleted file mode 100644 index 09480816a3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnmctor.c +++ /dev/null @@ -1,340 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnmctor.c - * - * Northbridge Orochi MCT supporting functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/OR) - * @e \$Revision: 51634 $ @e \$Date: 2011-04-26 03:12:52 -0600 (Tue, 26 Apr 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "cpuFeatures.h" -#include "mnor.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_NB_OR_MNMCTOR_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets final values for specific registers. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNFinalizeMctOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - MEM_PARAMETER_STRUCT *RefPtr; - DRAM_PREFETCH_MODE DramPrefetchMode; - UINT16 Speed; - UINT32 Value32; - UINT8 DcqBwThrotWm; - UINT8 DcqBwThrotWm1; - UINT8 DcqBwThrotWm2; - UINT8 Dct; - - MemPtr = NBPtr->MemPtr; - RefPtr = MemPtr->ParameterListPtr; - DramPrefetchMode = MemPtr->PlatFormConfig->PlatformProfile.AdvancedPerformanceProfile.DramPrefetchMode; - Speed = NBPtr->DCTPtr->Timings.Speed; - // - // F2x11C - // - // FlushWrOnStpGnt = 0 - // PrefThreeConf = 110b - // PrefTwoConf = 011b - // PrefOneConf = 10b - // PrefConfSat = 00b - // PrefIoDis = 0 - // PrefCpuDis = 0 - // MctWrLimit = 10h - // DctWrLimit = 01b - Value32 = MemNGetBitFieldNb (NBPtr, BFMctCfgHiReg); - Value32 &= 0xD003CF80; - Value32 |= 0x0CE00041; - MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, Value32); - - if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_IO || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { - MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 1); - } - - if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_CPU || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { - MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1); - } - - if (Speed == DDR667_FREQUENCY) { - DcqBwThrotWm = 0; - DcqBwThrotWm1 = 3; - DcqBwThrotWm2 = 4; - } else if (Speed == DDR800_FREQUENCY) { - DcqBwThrotWm = 0; - DcqBwThrotWm1 = 3; - DcqBwThrotWm2 = 5; - } else if (Speed == DDR1066_FREQUENCY) { - DcqBwThrotWm = 0; - DcqBwThrotWm1 = 4; - DcqBwThrotWm2 = 6; - } else if (Speed == DDR1333_FREQUENCY) { - DcqBwThrotWm = 0; - DcqBwThrotWm1 = 5; - DcqBwThrotWm2 = 8; - } else if (Speed == DDR1600_FREQUENCY) { - DcqBwThrotWm = 0; - DcqBwThrotWm1 = 6; - DcqBwThrotWm2 = 9; - } else if (Speed == DDR1866_FREQUENCY) { - DcqBwThrotWm = 0; - DcqBwThrotWm1 = 7; - DcqBwThrotWm2 = 10; - } else { - DcqBwThrotWm = 0; - DcqBwThrotWm1 = 8; - DcqBwThrotWm2 = 12; - } - - // - // F2x1B0 - // - // DcqBwThrotWm - // PrefFiveConf = 111b - // PrefFourConf = 111b - // EnSplitDctLimits = 1 - // CohPrefPrbLmt = IF (PrbFltrEn) THEN 000b ELSE 001b ENDIF - // AdapPrefNegativeStep = 00b - // AdapPrefPositiveStep = 00b - // AdapPrefMissRatio = 01b - Value32 = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg); - Value32 &= 0x003FE8C0; - Value32 |= 0x0FC01001; - Value32 |= (UINT32) DcqBwThrotWm << 28; - MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, Value32); - - // - // F2x1B4 - // - // DcqBwThrotWm2 - // DcqBwThrotWm1 - Value32 = MemNGetBitFieldNb (NBPtr, BFExtMctCfgHiReg); - Value32 &= 0xF7FFFC00; - Value32 |= (((UINT32) DcqBwThrotWm2 << 5) | (UINT32) DcqBwThrotWm1); - // FlushWrOnS3StpGnt to 1 - Value32 |= (UINT32) 1 << 27; - MemNSetBitFieldNb (NBPtr, BFExtMctCfgHiReg, Value32); - - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_OR; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - // - // Phy Power Saving - // - MemNPhyPowerSavingUnb (NBPtr); - // - // Power Down Enable - // - if (NBPtr->RefPtr->EnablePowerDown) { - MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); - } - } - } - - // Set LockDramCfg - if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { - IDS_SKIP_HOOK (IDS_TRACE_MODE, NBPtr, &NBPtr->MemPtr->StdHeader) { - MemNSetBitFieldNb (NBPtr, BFLockDramCfg, 1); - } - } - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - /*----------------------------------------------------------------------------- - * - * - * This function handles scrubber register settings for orochi. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - If the function is called before scrub rate is set or after - * TRUE function is called before scrub rate is set - * FALSE function is called after scrub rate is set - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNScrubberErratumOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 L3Scrub; - UINT8 DramScrub; - - if (*(BOOLEAN *) OptParam == TRUE) { - MemNSwitchDCTNb (NBPtr, 0); - } else { - ASSERT (NBPtr->Dct == 0); - L3Scrub = (UINT8) MemNGetBitFieldNb (NBPtr, BFL3Scrub); - DramScrub = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramScrub); - - // Set scrubber for DCT1 - MemNSwitchDCTNb (NBPtr, 1); - MemNSetBitFieldNb (NBPtr, BFL3Scrub, L3Scrub); - MemNSetBitFieldNb (NBPtr, BFDramScrub, DramScrub); - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function changes DataTxFifoWrDly based on training result of WrDatDly - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - */ - -BOOLEAN -MemNDataTxFifoWrDlyOverrideOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 i; - UINT8 Dct; - UINT8 ByteLane; - UINT16 CsEnabled; - BOOLEAN DataTxFifoWrDly; - - // This should be done only after DQS Position training - if (NBPtr->NbFreqChgState <= 1) { - return TRUE; - } - - // Set DataTxFifoWrDly based on WrDatDly - // if all WrDatDly of populated dimms on a DCT are equal to 7h - // Set DataTxFifoWrDly to >= 2h - for (Dct = 0; Dct < 2; Dct ++) { - MemNSwitchDCTNb (NBPtr, Dct); - DataTxFifoWrDly = TRUE; - CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { - if ((CsEnabled & (UINT16) (3 << (i << 1))) != 0) { - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - if ((GetTrainDlyFromHeapNb (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (i, ByteLane)) >> 5) != 7) { - DataTxFifoWrDly = FALSE; - break; - } - } - if (!DataTxFifoWrDly) { - break; - } - } - } - - if (DataTxFifoWrDly) { - if (MemNGetBitFieldNb (NBPtr, BFDataTxFifoWrDly) < 2) { - MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 2); - } - } - } - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.c deleted file mode 100644 index 4715de68d2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.c +++ /dev/null @@ -1,640 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnor.c - * - * Common Northbridge functions for Orochi - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/OR) - * @e \$Revision: 52421 $ @e \$Date: 2011-05-05 21:03:23 -0600 (Thu, 05 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnor.h" -#include "mu.h" -#include "S3.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "F15PackageType.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_NB_OR_MNOR_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -#define SPLIT_CHANNEL (UINT32) 0x20000000 -#define CHANNEL_SELECT (UINT32) 0x10000000 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/** - * @todo: Add Comments with field descriptions - */ -CONST MEM_FREQ_CHANGE_PARAM FreqChangeParamOr = {0x0190, 7, 7, 14, 3, 18, 470, 946}; - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; -extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB - * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA - * @param[in] NodeID - UINT8 indicating node ID of the NB object. - * - * @return Boolean indicating that this is the correct memory - * controller type for the node number that was passed in. - */ - -BOOLEAN -MemConstructNBBlockOR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *SharedPtr, - IN UINT8 NodeID - ) -{ - UINT8 Dct; - UINT8 Channel; - UINT8 SpdSocketIndex; - UINT8 SpdChannelIndex; - DIE_STRUCT *MCTPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedOr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->MemPtr = MemPtr; - NBPtr->RefPtr = MemPtr->ParameterListPtr; - NBPtr->SharedPtr = SharedPtr; - - MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->MCTPtr = MCTPtr; - NBPtr->MCTPtr->NodeId = NodeID; - NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; - NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - - // - // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs - // - AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_OR * ( - sizeof (DCT_STRUCT) + ( - MAX_CHANNELS_PER_DCT_OR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) - ) - ); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs - return FALSE; - } - - MCTPtr->DctCount = MAX_DCTS_PER_NODE_OR; - MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_OR * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_OR; Dct++) { - MCTPtr->DctData[Dct].Dct = Dct; - MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_OR; - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; - MCTPtr->DctData[Dct].ChData[0].Dct = Dct; - AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_OR * sizeof (CH_DEF_STRUCT); - } - NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; - - // - // Initialize Socket List - // - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_OR; Dct++) { - MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]); - MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings); - MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; - } - - MemNInitNBDataOr (NBPtr); - - FeatPtr->InitCPG (NBPtr); - FeatPtr->InitHwRxEn (NBPtr); - FeatPtr->InitEarlySampleSupport (NBPtr); - NBPtr->FeatPtr = FeatPtr; - - - // - // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel - // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that - // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the - // dimm types(QR or not) are known. This is done in the Technology block constructor. - // - // Calculate the SpdSocketIndex separately from the SpdChannelIndex. - // This will facilitate modifications due to some processors that might - // map the DCT-CHANNEL differently. - // - SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); - // - // Traverse the Dct/Channel structures - // - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_OR; Dct++) { - for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_OR; Channel++) { - // - // Calculate the number of Dimms on this channel using the - // die/dct/channel to Socket/channel conversion. - // - SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, - NBPtr->MCTPtr->SocketId, - MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), - &MemPtr->StdHeader); - NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); - } - } - - // - // Initialize Dct and DctCfgSel bit - // - MemNSetBitFieldNb (NBPtr, BFDctCfgSel, 0); - MemNSwitchDCTNb (NBPtr, 0); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes member functions and variables of NB block. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitNBDataOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 PackageType; - - NBPtr->DctCachePtr = NBPtr->DctCache; - NBPtr->PsPtr = NBPtr->PSBlock; - - MemNInitNBRegTableOr (NBPtr, NBPtr->NBRegTable); - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Dct = 0; - NBPtr->Channel = 0; - NBPtr->DctCount = MAX_DCTS_PER_NODE_OR; - NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_OR; - NBPtr->NodeCount = MAX_NODES_SUPPORTED_OR; - NBPtr->Ganged = FALSE; - NBPtr->PosTrnPattern = POS_PATTERN_256B; - NBPtr->MemCleared = FALSE; - NBPtr->StartupSpeed = DDR667_FREQUENCY; - NBPtr->RcvrEnDlyLimit = 0x1FF; - NBPtr->DefDctSelIntLvAddr = 3; - NBPtr->NbFreqChgState = 0; - NBPtr->MaxRxEnSeedTotal = 0x3FF; - NBPtr->MinRxEnSeedGross = 0; - NBPtr->FreqChangeParam = (MEM_FREQ_CHANGE_PARAM *) &FreqChangeParamOr; - NBPtr->CsRegMsk = 0x7FF83FE0; - NBPtr->TotalMaxVrefRange = 0x20; - NBPtr->TotalRdDQSDlyRange = 0x40; - NBPtr->MaxSeedCount = MAX____DQS_SEED_COUNT; - NBPtr->PhaseLaneMask = 0x3FFFF; - NBPtr->MaxDiamondStep = 3; - - LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); - - NBPtr->SetMaxLatency = MemNSetMaxLatencyOr; - NBPtr->getMaxLatParams = MemNGetMaxLatParamsOr; - NBPtr->InitializeMCT = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue; - NBPtr->FinalizeMCT = MemNFinalizeMctOr; - NBPtr->SendMrsCmd = MemNSendMrsCmdUnb; - NBPtr->sendZQCmd = MemNSendZQCmdNb; - NBPtr->WritePattern = MemNWritePatternOr; - NBPtr->ReadPattern = MemNReadPatternOr; - NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; - NBPtr->CompareTestPattern = MemNCompareTestPatternNb; - NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; - NBPtr->StitchMemory = MemNStitchMemoryNb; - NBPtr->AutoConfig = MemNAutoConfigOr; - NBPtr->PlatformSpec = MemNPlatformSpecUnb; - NBPtr->InitMCT = MemNInitMCTNb; - NBPtr->DisableDCT = MemNDisableDCTUnb; - NBPtr->StartupDCT = MemNStartupDCTUnb; - NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; - NBPtr->ChangeFrequency = MemNChangeFrequencyUnb; - NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; - NBPtr->ChangeNbFrequency = MemNChangeNbFrequencyUnb; - NBPtr->ChangeNbFrequencyWrap = MemNChangeNbFrequencyWrapUnb; - NBPtr->ProgramNbPsDependentRegs = MemNProgramNbPstateDependentRegistersUnb; - NBPtr->ProgramCycTimings = MemNProgramCycTimingsUnb; - NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; - NBPtr->HtMemMapInit = MemNHtMemMapInitNb; - NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; - NBPtr->CpuMemTyping = MemNCPUMemTypingNb; - NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingOr; - NBPtr->AfterDqsTraining = MemNAfterDQSTrainingOr; - NBPtr->OtherTiming = MemNOtherTimingOr; - NBPtr->UMAMemTyping = MemNUMAMemTypingNb; - NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelOr; - NBPtr->TechBlockSwitch = MemNTechBlockSwitchOr; - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldOr; - NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb; - NBPtr->TrainingFlow = (VOID (*) (MEM_NB_BLOCK *)) MemNTrainingFlowUnb; - MemNInitNBDataNb (NBPtr); - NBPtr->PollBitField = MemNPollBitFieldNb; - NBPtr->BrdcstCheck = MemNBrdcstCheckNb; - NBPtr->BrdcstSet = MemNBrdcstSetNb; - NBPtr->GetTrainDly = MemNGetTrainDlyNb; - NBPtr->SetTrainDly = MemNSetTrainDlyNb; - NBPtr->PhyFenceTraining = MemNPhyFenceTrainingUnb; - NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; - NBPtr->RankEnabled = MemNRankEnabledNb; - NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitOr; - NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyUnb; - NBPtr->MemPPhyFenceTrainingNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->MemNInitPhyComp = MemNInitPhyCompOr; - NBPtr->MemNBeforePlatformSpecNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitTblDrvNb; - NBPtr->MemNPFenceAdjustNb = MemNPFenceAdjustOr; - NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsUnb; - NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; - NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; - NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; - NBPtr->CSPerChannel = MemNCSPerChannelNb; - NBPtr->CSPerDelay = MemNCSPerDelayNb; - NBPtr->FlushPattern = MemNFlushPatternNb; - NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; - NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeOr; - NBPtr->GetUmaSize = MemNGetUmaSizeNb; - NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdUnb; - NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb; - NBPtr->WaitXMemClks = MemNWaitXMemClksNb; - NBPtr->MemNGetDramTerm = MemNGetDramTermTblDrvNb; - NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermTblDrvNb; - NBPtr->MemNGetMR0CL = MemNGetMR0CLTblDrvNb; - NBPtr->MemNGetMR0WR = MemNGetMR0WRTblDrvNb; - NBPtr->MemNSaveMR0 = MemNSaveMR0Or; - NBPtr->MemNGetMR2CWL = MemNGetMR2CWLUnb; - NBPtr->AllocateC6Storage = MemNAllocateC6StorageUnb; - NBPtr->InPhaseCompareRdDqs__Pattern = MemNInPhaseCompareRdDqs__PatternUnb; - NBPtr->Phase180CompareRdDqs__Pattern = MemN180CompareRdDqs__PatternUnb; - NBPtr->AgressorContinuousWrites = MemNAgressorContinuousWritesUnb; - NBPtr->GetPrbs__RdDqsSeed = MemNGetPrbs__RdDqsSeedUnb; - NBPtr->InitializeRdDqs__VictimContinuousWrites = MemNInitializeRdDqs__VictimContinuousWritesUnb; - NBPtr->FinalizeRdDqs__VictimContinuousWrites = MemNFinalizeRdDqs__VictimContinuousWritesUnb; - NBPtr->InitializeRdDqs__VictimChipSelContinuousWrites = MemNInitializeRdDqs__VictimChipSelContinuousWritesUnb; - NBPtr->StartRdDqs__VictimContinuousWrites = MemNStartRdDqs__VictimContinuousWritesUnb; - - NBPtr->IsSupported[SetSpareEn] = TRUE; - NBPtr->IsSupported[CheckSpareEn] = TRUE; - NBPtr->IsSupported[SetDllShutDown] = TRUE; - NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE; - NBPtr->IsSupported[DimmBasedOnSpeed] = FALSE; - NBPtr->IsSupported[CheckMaxDramRate] = TRUE; - NBPtr->IsSupported[Check1GAlign] = FALSE; - NBPtr->IsSupported[CheckDisDllShutdownSR] = FALSE; - NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE; - NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; - NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; - NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE; - NBPtr->IsSupported[CheckGetMCTSysAddr] = FALSE; - NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE; - NBPtr->IsSupported[CheckFindPSDct] = FALSE; - NBPtr->IsSupported[FenceTrnBeforeDramInit] = TRUE; - NBPtr->IsSupported[UnifiedNbFence] = TRUE; - NBPtr->IsSupported[CheckODTControls] = TRUE; - NBPtr->IsSupported[CheckDummyCLRead] = TRUE; - NBPtr->IsSupported[CheckDllStdBy] = FALSE; - NBPtr->IsSupported[CheckSlewWithMarginImprv] = FALSE; - NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE; - NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; - NBPtr->IsSupported[CheckDllRegDis] = FALSE; - NBPtr->IsSupported[PchgPDMode] = TRUE; - NBPtr->IsSupported[EccByteTraining] = TRUE; - NBPtr->IsSupported[CheckDramTerm] = TRUE; - NBPtr->IsSupported[CheckDramTermDyn] = TRUE; - NBPtr->IsSupported[CheckQoff] = TRUE; - NBPtr->IsSupported[CheckDrvImpCtrl] = TRUE; - NBPtr->IsSupported[CheckSetSameDctODTsEn] = TRUE; - NBPtr->IsSupported[WLSeedAdjust] = TRUE; - NBPtr->IsSupported[WLNegativeDelay] = TRUE; - NBPtr->IsSupported[TwoStageDramInit] = TRUE; - NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; - NBPtr->IsSupported[ProgramCsrComparator] = TRUE; - NBPtr->IsSupported[SetTDqsForx8DimmOnly] = TRUE; - NBPtr->IsSupported[WlRttNomFor1of3Cfg] = TRUE; - - NBPtr->FamilySpecificHook[ExitPhyAssistedTraining] = MemNExitPhyAssistedTrainingOr; - NBPtr->FamilySpecificHook[DCTSelectSwitch] = MemNDctCfgSelectUnb; - NBPtr->FamilySpecificHook[ScrubberErratum] = MemNScrubberErratumOr; - NBPtr->FamilySpecificHook[AfterSaveRestore] = MemNAfterSaveRestoreUnb; - NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] = MemNDataTxFifoWrDlyOverrideOr; - NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemNOverrideRcvEnSeedOr; - NBPtr->FamilySpecificHook[OverrideRcvEnSeedPassN] = MemNOverrideRcvEnSeedPassNOr; - NBPtr->FamilySpecificHook[OverrideWLSeed] = MemNOverrideWLSeedOr; - NBPtr->FamilySpecificHook[AfterMemClkFreqChg] = MemNAfterMemClkFreqChgOr; - NBPtr->FamilySpecificHook[CalcWrDqDqsEarly] = MemNCalcWrDqDqsEarlyUnb; - NBPtr->FamilySpecificHook[TrainWlPerNibble] = MemNTrainWlPerNibbleOr; - NBPtr->FamilySpecificHook[TrainWlPerNibbleAdjustWLDly] = MemNTrainWlPerNibbleAdjustWLDlyOr; - NBPtr->FamilySpecificHook[TrainWlPerNibbleSeed] = MemNTrainWlPerNibbleSeedOr; - NBPtr->FamilySpecificHook[TrainRxEnPerNibble] = MemNTrainRxEnPerNibbleOr; - NBPtr->FamilySpecificHook[TrainRxEnAdjustDlyPerNibble] = MemNTrainRxEnAdjustDlyPerNibbleOr; - NBPtr->FamilySpecificHook[TrainRxEnGetAvgDlyPerNibble] = MemNTrainRxEnGetAvgDlyPerNibbleOr; - NBPtr->FamilySpecificHook[InitPerNibbleTrn] = MemNInitPerNibbleTrnOr; - NBPtr->FamilySpecificHook[TrainingNibbleZero] = MemNTrainingNibbleZeroOr; - NBPtr->FamilySpecificHook[BeforeSetCsTri] = MemNBeforeSetCsTriOr; - NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] = MemNAdjustRdDqsDlyOffsetUnb; - NBPtr->FamilySpecificHook[EnableParityAfterMemRst] = MemNEnableParityAfterMemRstOr; - NBPtr->FamilySpecificHook[GetDdrMaxRate] = MemNGetMaxDdrRateUnb; - NBPtr->FamilySpecificHook[ProgOdtControl] = MemNProgOdtControlOr; - NBPtr->FamilySpecificHook[SetSkewMemClk] = MemNSetSkewMemClkUnb; - NBPtr->FamilySpecificHook[ReleaseNbPstate] = MemNReleaseNbPstateOr; - NBPtr->FamilySpecificHook[InitializeRxEnSeedlessTraining] = MemNInitializeRxEnSeedlessTrainingUnb; - NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrNoWindBLError] = MemNTrackRxEnSeedlessRdWrNoWindBLErrorUnb; - NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrSmallWindBLError] = MemNTrackRxEnSeedlessRdWrSmallWindBLErrorUnb; - NBPtr->FamilySpecificHook[InitialzeRxEnSeedlessByteLaneError] = MemNInitialzeRxEnSeedlessByteLaneErrorUnb; - NBPtr->FamilySpecificHook[AdjustWrDqsBeforeSeedScaling] = MemNAdjustWrDqsBeforeSeedScalingOr; - NBPtr->FamilySpecificHook[Adjust2DPhaseMaskBasedOnEcc] = MemNAdjust2DPhaseMaskBasedOnEccUnb; - - PackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader)); - if (PackageType == PACKAGE_TYPE_AM3r2) { - // AM3r2 does not support 1.35V - NBPtr->IsSupported[PerformanceOnly] = TRUE; - - // AM3r2 does not support Dll shutdown - NBPtr->IsSupported[SetDllShutDown] = FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the default values in the MEM_DATA_STRUCT - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - */ -VOID -MemNInitDefaultsOR ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT8 Socket; - UINT8 Channel; - MEM_PARAMETER_STRUCT *RefPtr; - ASSERT (MemPtr != NULL); - RefPtr = MemPtr->ParameterListPtr; - - // Memory Map/Mgt. - // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB - RefPtr->BottomIo = 0xE0; - RefPtr->UmaMode = UserOptions.CfgUmaMode; - RefPtr->UmaSize = UserOptions.CfgUmaSize; - RefPtr->MemHoleRemapping = TRUE; - RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb; - // - - - // Dram Timing - RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; - RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; - for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { - for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { - MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; - MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; - } - } - - // Memory Clear - RefPtr->EnableMemClr = TRUE; - - // TableBasedAlterations - RefPtr->TableBasedAlterations = NULL; - - // Platform config table - RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; - - // Memory Restore - RefPtr->MemRestoreCtl = FALSE; - RefPtr->SaveMemContextCtl = FALSE; - AmdS3ParamsInitializer (&RefPtr->MemContext); - - // Dram Configuration - RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; - RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; - RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; - RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; - RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; - RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; - - // Dram Power - RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; - - // ECC - RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; - - // Vref - RefPtr->ExternalVrefCtl = UserOptions.CfgExternalVrefCtlFeature; - - //Training Mode - RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode; -} -/*-----------------------------------------------------------------------------*/ -/** - * - * This function writes training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Pattern[] - Pattern to write - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNWritePatternOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUWriteCachelines (Address, Pattern, ClCount); -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function reads training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer to fill - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNReadPatternOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUReadCachelines (Buffer, Address, ClCount); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates DQS training for Unified NB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -memNEnableTrainSequenceOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BOOLEAN Retval; - Retval = TRUE; - if (!MemNIsIdSupportedOr (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { - Retval = FALSE; - } - return Retval; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function save the MR0 value sent to memory during initialization - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] MrsAddress - MR0 value to be saved - * @return none - */ -VOID -MemNSaveMR0Or ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 MrsAddress - ) -{ - AGESA_STATUS Status; - LOCATE_HEAP_PTR LocateHeapStructPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT32 ChipSel; - MR0_DATA_ARRAY_PTR pMR0Data; - - ChipSel = NBPtr->GetBitField (NBPtr, BFMrsChipSel); - LocateHeapStructPtr.BufferHandle = AMD_MEM_S3_MR0_DATA_HANDLE; - LocateHeapStructPtr.BufferPtr = NULL; - Status = HeapLocateBuffer (&LocateHeapStructPtr, &NBPtr->MemPtr->StdHeader); - if (Status == AGESA_SUCCESS) { - // MR0 data already present in heap - pMR0Data = (MR0_DATA_ARRAY_PTR) (LocateHeapStructPtr.BufferPtr); - ASSERT (pMR0Data != NULL); - } else { - AllocHeapParams.RequestedBufferSize = sizeof (MR0_DATA_STRUCT) * MAX_NODES_SUPPORTED_OR * MAX_DCTS_PER_NODE_OR; - AllocHeapParams.BufferHandle = AMD_MEM_S3_MR0_DATA_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - - // - // Allocate data buffer in heap - // - Status = HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader); - ASSERT (Status == AGESA_SUCCESS); - pMR0Data = (MR0_DATA_ARRAY_PTR) (AllocHeapParams.BufferPtr); - ASSERT (pMR0Data != NULL); - LibAmdMemFill (pMR0Data, 0, sizeof (MR0_DATA_STRUCT) * MAX_NODES_SUPPORTED_OR * MAX_DCTS_PER_NODE_OR, &NBPtr->MemPtr->StdHeader); - } - (*pMR0Data)[NBPtr->Node][NBPtr->Dct].MR0Value = (UINT16) MrsAddress; - (*pMR0Data)[NBPtr->Node][NBPtr->Dct].ChipSelEnMap |= (((UINT16)1) << ChipSel); - IDS_HDT_CONSOLE (MEM_FLOW, "\tLog last MR0\n\t\tNode: %d, Dct: %d, CS: %d, MR0: %08X\n", NBPtr->Node, NBPtr->Dct, ChipSel, MrsAddress); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.h deleted file mode 100644 index 7ac0dc95bb..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.h +++ /dev/null @@ -1,361 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnor.h - * - * Northbridge Orochi - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 60556 $ @e \$Date: 2011-10-17 20:19:58 -0600 (Mon, 17 Oct 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _MNOR_H_ -#define _MNOR_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ -#define MAX_CHANNELS_PER_SOCKET_OR 4 -#define MAX_DCTS_PER_NODE_OR 2 -#define MAX_CHANNELS_PER_DCT_OR 1 -#define MAX_NODES_SUPPORTED_OR 8 - -#define DEFAULT_WR_ODT_OR 6 -#define DEFAULT_RD_ODT_OR 6 - -#define GetBufDatDly 0 -#define GetBufDatDlySkew 1 - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ -/// Data Structure of Parameters for MR0 PPD set during S3 resume -typedef struct { - UINT16 MR0Value; ///< MRO Value saved during memory initialization - UINT16 ChipSelEnMap; ///< Bitmap of Enabled Chip Select per DCT -} MR0_DATA_STRUCT; - -typedef MR0_DATA_STRUCT (*MR0_DATA_ARRAY_PTR)[MAX_NODES_SUPPORTED_OR][MAX_DCTS_PER_NODE_OR]; -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemConstructNBBlockOR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *SharedPtr, - IN UINT8 NodeID - ); - -VOID -MemNInitNBDataOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitDefaultsOR ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -BOOLEAN -MemNFinalizeMctOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNAutoConfigOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNOtherTimingOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitPhyCompOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNWritePatternOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -MemNReadPatternOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -MemNInitNBRegTableOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT TSEFO NBRegTable[] - ); - -UINT8 -MemNGetSocketRelativeChannelOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct, - IN UINT8 Channel - ); - -BOOLEAN -MemNIsIdSupportedOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID *LogicalIdPtr - ); - -UINT32 -MemNCmnGetSetFieldOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ); - -BOOLEAN -memNEnableTrainSequenceOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNTechBlockSwitchOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNScrubberErratumOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -VOID -MemNAfterDQSTrainingOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNDataTxFifoWrDlyOverrideOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -VOID -MemNCapSpeedBatteryLifeOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNGetMaxLatParamsOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxRcvEnDly, - IN OUT UINT16 *MinDlyPtr, - IN OUT UINT16 *MaxDlyPtr, - IN OUT UINT16 *DlyBiasPtr - ); - -VOID -MemNSetMaxLatencyOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxRcvEnDly - ); - -BOOLEAN -MemNExitPhyAssistedTrainingOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -MemNOverrideRcvEnSeedOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *SeedPtr - ); - -BOOLEAN -MemNOverrideRcvEnSeedPassNOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *SeedTotal - ); - -BOOLEAN -MemNOverrideWLSeedOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *SeedPtr - ); - -BOOLEAN -MemNAfterMemClkFreqChgOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - - -BOOLEAN -MemNTrainWlPerNibbleOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *Dimm - ); - -BOOLEAN -MemNTrainWlPerNibbleAdjustWLDlyOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *Delay - ); - -VOID -MemNBeforeDQSTrainingOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNTrainRxEnPerNibbleOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *ChipSel - ); - -BOOLEAN -MemNTrainRxEnAdjustDlyPerNibbleOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *RcvEnDly - ); - -BOOLEAN -MemNTrainRxEnGetAvgDlyPerNibbleOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -MemNInitPerNibbleTrnOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -MemNTrainWlPerNibbleSeedOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *WrDqsDly - ); - -BOOLEAN -MemNTrainingNibbleZeroOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *ChipSel - ); - -BOOLEAN -MemNBeforeSetCsTriOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *CsTriBitmap - ); - -BOOLEAN -MemNEnableParityAfterMemRstOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -MemNProgOdtControlOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -VOID -MemNBeforeDramInitOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNPFenceAdjustOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT INT16 *Value16 - ); - -BOOLEAN -MemNReleaseNbPstateOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -VOID -MemNSaveMR0Or ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 MrsAddress - ); - -UINT32 -MemNCalBufDatDelaySkewOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 GetDelay - ); - -VOID -MemNPowerDownCtlOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNAdjustWrDqsBeforeSeedScalingOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *WrDqsBias - ); - -#endif /* _MNOR_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnotor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnotor.c deleted file mode 100644 index ef7934cce1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnotor.c +++ /dev/null @@ -1,280 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnotor.c - * - * Northbridge Non-SPD timings for Orochi - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/OR) - * @e \$Revision: 51485 $ @e \$Date: 2011-04-23 15:12:38 -0600 (Sat, 23 Apr 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnor.h" -#include "mu.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_NB_OR_MNOTOR_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -MemNSetOtherTimingOR ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the non-SPD timings - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNOtherTimingOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Programming of Non-SPD Timings.\n"); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { - MemNSetOtherTimingOR (NBPtr); - } - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the non-SPD timings in PCI registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemNSetOtherTimingOR ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - INT8 ROD; - INT8 WOD; - INT8 LD; - INT8 WrEarly; - BOOLEAN FourRankRDimms; - INT8 CDDTrdrdSdDc; - INT8 CDDTrdrdDd; - INT8 CDDTwrwrDd; - INT8 CDDTwrwrSdDc; - INT8 CDDTrwtTO; - INT8 CDDTwrrd; - UINT8 TrdrdSdDc; - UINT8 TrdrdDd; - UINT8 TwrwrSdDc; - UINT8 TwrwrDd; - UINT8 TrdrdSdSc; - UINT8 TwrwrSdSc; - UINT8 Twrrd; - UINT8 TrwtTO; - UINT8 BufDatDelay; - - CH_DEF_STRUCT *ChannelPtr; - ChannelPtr = NBPtr->ChannelPtr; - // - // Latency Difference (LD) = Tcl - Tcwl - // - LD = (INT8) (MemNGetBitFieldNb (NBPtr, BFTcl)) - (INT8) (MemNGetBitFieldNb (NBPtr, BFTcwl)); - - // - // Read ODT Delay (ROD) = MAX ( 0, (RdOdtOnDuration - 6)) - // - ROD = MAX (0, (INT8) (MemNGetBitFieldNb (NBPtr, BFRdOdtOnDuration) - 6)); - // - // Write ODT Delay (WOD) = MAX (0, (WrOdtOnDuration - 6)) - // - WOD = MAX (0, (INT8) (MemNGetBitFieldNb (NBPtr, BFWrOdtOnDuration) - 6)); - // - // WrEarly = ABS (WrDqDqsEarly) - This is in half clocks to preserve precision. Must be converted to whole clocks when used in equations below. - // - WrEarly = (INT8) MemNGetBitFieldNb (NBPtr, BFWrDqDqsEarly); - // - // BufDatDelay = IF LRDIMM [LRDIMM Module Delay Time SPD Bytes] ELSE 0 ENDIF. - // - BufDatDelay = (NBPtr->MCTPtr->Status[SbLrdimms]) ? (UINT8) MemNCalBufDatDelaySkewOr (NBPtr, GetBufDatDly): 0; - // - // FourRankRDimms - // - FourRankRDimms = ((MemNGetBitFieldNb (NBPtr, BFFourRankRDimm1) == 1) || - (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm0) == 1)) ? TRUE : FALSE; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tLD: %d ROD: %d WOD: %d WrEarly: %d\n\n", LD, ROD, WOD, WrEarly); - // - // Read to Read Timing (TrdrdSdSc, TrdrdScDc, TrdrdDd) - // - // TrdrdSdSc = 1. - // TrdrdSdDc = MAX(TrdrdSdSc, 3 + (IF (D18F2x94_dct[1:0][FourRankRDimm1] | D18F2x94_dct[1:0][FourRankRDimm0]) - // THEN (CEIL(CDDTrdrdSdDc / 2 ) + 0.5) ELSE 0 ENDIF.)) - // TrdrdDd = MAX(TrdrdSdDc, CEIL(MAX(ROD + 3, CDDTrdrdDd / 2 + 3.5))). - TrdrdSdSc = 1; - - CDDTrdrdSdDc = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, TRUE, FALSE); - TrdrdSdDc = MAX (TrdrdSdSc, (FourRankRDimms ? (CDDTrdrdSdDc + 7 + 1) / 2 : 3)); - - CDDTrdrdDd = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, FALSE, TRUE); - TrdrdDd = (UINT8) MAX (TrdrdSdDc, MAX (ROD + 3, (CDDTrdrdDd + 7 + 1) / 2 )); - - MemNSetBitFieldNb (NBPtr, BFTrdrdDd, (UINT32) TrdrdDd); - MemNSetBitFieldNb (NBPtr, BFTrdrdSdDc, (UINT32) TrdrdSdDc); - MemNSetBitFieldNb (NBPtr, BFTrdrdSdSc, (UINT32) TrdrdSdSc); - // - // Write to Write Timing (TwrwrSdSc, TwrwrScDc, TwrwrDd - // - // TwrwrSdSc = 1. - // TwrwrSdDc = MAX(TwrwrSdSc, CEIL(MAX(WOD + 3, CDDTwrwrSdDc / 2 + - // (IF (D18F2x94_dct[1:0][FourRankRDimm1] | D18F2x94_dct[1:0][FourRankRDimm0]) - // THEN 3.5 ELSE 3 ENDIF)))). - // TwrwrDd = MAX(TwrwrSdDc, CEIL(MAX(WOD + 3, CDDTwrwrDd / 2 + 3.5))). - // - TwrwrSdSc = 1; - CDDTwrwrSdDc = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, TRUE, FALSE); - TwrwrSdDc = (UINT8) MAX (WOD + 3, (CDDTwrwrSdDc + (FourRankRDimms ? 7 : 6) + 1 ) / 2) ; - CDDTwrwrDd = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, FALSE, TRUE); - TwrwrDd = MAX ( TwrwrSdDc, MAX ((UINT8) (WOD + 3), (CDDTwrwrDd + 7 + 1) / 2)); - - MemNSetBitFieldNb (NBPtr, BFTwrwrDd, (UINT32) TwrwrDd); - MemNSetBitFieldNb (NBPtr, BFTwrwrSdDc, (UINT32) TwrwrSdDc); - MemNSetBitFieldNb (NBPtr, BFTwrwrSdSc, (UINT32) TwrwrSdSc); - // - // Write to Read DIMM Termination Turn-around - // - // IF (LRDIMM) THEN - // Twrrd (in MEMCLKs) = MAX(1, CEIL(MAX(WOD - BufDatDelay, CDDTwrrd / 2 + 0.5 - WrEarly, (DdrRate >= 1866 ? 1 : 0)) - LD + 3)) - // ELSE - // Twrrd = MAX ( 1, CEIL (MAX (WOD, (CDDTwrrd / 2) + 0.5 - WrEarly) - LD + 3)) - CDDTwrrd = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, FALSE, TRUE); - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - Twrrd = MAX (1, MAX (WOD - BufDatDelay, MAX ((CDDTwrrd + 1 + 1 - WrEarly) / 2, (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY ? 1 : 0))) - LD + 3); - } else { - Twrrd = MAX (1, MAX (WOD, (CDDTwrrd + 1 + 1 - WrEarly) / 2) - LD + 3); - } - - MemNSetBitFieldNb (NBPtr, BFTwrrd, (UINT32) Twrrd); - // - // Read to Write Turnaround for Data, DQS Contention - // - // TrwtTO = CEIL (MAX (ROD, (CDDTrwtTO / 2) - 0.5 + WrEarly) + LD + 3) - // - CDDTrwtTO = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessWrDqsDly, TRUE, TRUE); - - TrwtTO = MAX ( (ChannelPtr->Dimms == 1 ? 0 : ROD + BufDatDelay) , ((CDDTrwtTO - 1 + 1 + WrEarly) / 2) ) + LD + 3; - - MemNSetBitFieldNb (NBPtr, BFTrwtTO, (UINT32) TrwtTO); - // - // Read to Write Turnaround for opportunistic Write Bursting - // - // TrwtWB = TrwtTO + 1 - // - MemNSetBitFieldNb (NBPtr, BFTrwtWB, (UINT32) TrwtTO + 1); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t TrdrdSdSc : %02x\n", TrdrdSdSc); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrdrdSdDc : %02x TrdrdSdDc : %02x\n", CDDTrdrdSdDc, TrdrdSdDc); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrdrdDd : %02x TrdrdDd : %02x\n\n", CDDTrdrdDd, TrdrdDd); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t TwrwrSdSc : %02x\n", TwrwrSdSc); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrwrSdDc : %02x TwrwrSdDc : %02x\n", CDDTwrwrSdDc, TwrwrSdDc ); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrwrDd : %02x TwrwrDd : %02x\n\n", CDDTwrwrDd, TwrwrDd); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t TrwtWB : %02x\n", TrwtTO + 1); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrrd : %02x Twrrd : %02x\n", (UINT8) CDDTwrrd, (UINT8) Twrrd ); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrwtTO : %02x TrwtTO : %02x\n\n", (UINT8) CDDTrwtTO, (UINT8) TrwtTO ); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnpartrainor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnpartrainor.c deleted file mode 100644 index eb5ccb3bb4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnpartrainor.c +++ /dev/null @@ -1,219 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnParTrainOr.c - * - * Feature which performs Memory DQS training on each node with each node training - * its own memory through code running on a core in the associated processor. - * This way memory can be trained in parallel by more than one processor. - * - * This file contains the Orochi specific parallel training function. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/HCTRN) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnor.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemFParallelTrainingOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -STATIC -MemConstructRemoteNBBlockOR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN DIE_STRUCT *MCTPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr -); -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the training function which set up the environment for remote - * training on the ap and launches the remote routine. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Launch training on AP successfully. - * @return FALSE - Fail to launch training on AP. - */ -BOOLEAN -MemFParallelTrainingOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - DIE_STRUCT *MCTPtr; - REMOTE_TRAINING_ENV *EnvPtr; - AP_TASK TrainingTask; - UINT8 Socket; - UINT8 Module; - UINT8 APCore; - UINT8 p; - UINT32 LowCore; - UINT32 HighCore; - UINT32 BspSocket; - UINT32 BspModule; - UINT32 BspCore; - AGESA_STATUS Status; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT16 MctDataSize; - StdHeader = &(NBPtr->MemPtr->StdHeader); - MCTPtr = NBPtr->MCTPtr; - Socket = MCTPtr->SocketId; - Module = MCTPtr->DieId; - - // - // Allocate buffer for REMOTE_TRAINING_ENV - // - MctDataSize = MAX_DCTS_PER_NODE_OR * ( - sizeof (DCT_STRUCT) + ( - MAX_CHANNELS_PER_DCT_OR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) - ) - ); - AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); - - // - // Setup Remote training environment - // - LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; - } - EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; - EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockOR; - EnvPtr->FeatPtr = NBPtr->FeatPtr; - EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; - EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; - EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize; - EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; - EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; - EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; - - LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); - - // - // Get Socket, Core of the BSP - // - IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); - EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); - EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); - - // - // Set up the remote task structure - // - TrainingTask.DataTransfer.DataPtr = EnvPtr; - TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4; - TrainingTask.DataTransfer.DataTransferFlags = 0; - TrainingTask.ExeFlags = 0; - TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; - - // - // Get Target AP Core - // - GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); - APCore = (UINT8) (LowCore & 0x000000FF); - - // - // Launch Remote Training - // - ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); - - HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); - - return TRUE; - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" - return FALSE; - } -} - -BOOLEAN -STATIC -MemConstructRemoteNBBlockOR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN DIE_STRUCT *MCTPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr - ) -{ - NBPtr->MCTPtr = MCTPtr; - NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; - - MemNInitNBDataOr (NBPtr); - - FeatPtr->InitCPG (NBPtr); - NBPtr->FeatPtr = FeatPtr; - FeatPtr->InitHwRxEn (NBPtr); - MemNSwitchDCTNb (NBPtr, 0); - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c deleted file mode 100644 index d154e2f2cc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c +++ /dev/null @@ -1,849 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnphyor.c - * - * Northbridge Phy support for Orochi - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/OR) - * @e \$Revision: 58126 $ @e \$Date: 2011-08-21 23:38:29 -0600 (Sun, 21 Aug 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "ma.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnor.h" -#include "cpuRegisters.h" -#include "PlatformMemoryConfiguration.h" -#include "F15PackageType.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_NB_OR_MNPHYOR_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 - - -/// The structure of TxPrePN tables -typedef struct { - UINT32 Speed; ///< Applied memory speed - UINT16 TxPrePNVal[4]; ///< Table values -} TXPREPN_STRUCT; - -/// The entry of individual TxPrePN tables -typedef struct { - UINT8 TxPrePNTblSize; ///< Total Table size - CONST TXPREPN_STRUCT *TxPrePNTblPtr; ///< Pointer to the table -} TXPREPN_ENTRY; - -/// Type of an entry for processing phy init compensation for Orochi -typedef struct { - BIT_FIELD_NAME IndexBitField; ///< Bit field on which the value is decided - BIT_FIELD_NAME StartTargetBitField; ///< First bit field to be modified - BIT_FIELD_NAME EndTargetBitField; ///< Last bit field to be modified - UINT16 ExtraValue; ///< Extra value needed to be written to bit field - CONST TXPREPN_ENTRY *TxPrePN; ///< Pointer to slew rate table -} PHY_COMP_INIT_NB; -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DDR phy compensation logic - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitPhyCompOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // - // Phy Predriver Calibration Codes for Data/DQS - // - CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV15Or[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.5V - {DDR667 + DDR800, {0x924, 0x924, 0x924, 0x924}}, - {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}, - {DDR1600 + DDR1866, {0xFF6, 0xFF6, 0xFF6, 0xFF6}} - }; - CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV135Or[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.35V - {DDR667 + DDR800, {0xFF6, 0xB6D, 0xB6D, 0x924}}, - {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}, - {DDR1600 + DDR1866, {0xFF6, 0xFF6, 0xFF6, 0xFF6}} - }; - CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV125Or[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.25V - {DDR667 + DDR800, {0xFF6, 0xDAD, 0xDAD, 0x924}}, - {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}, - {DDR1600 + DDR1866, {0xFF6, 0xFF6, 0xFF6, 0xFF6}} - }; - CONST STATIC TXPREPN_ENTRY TxPrePNDataDqsOr[] = { - {GET_SIZE_OF (TxPrePNDataDqsV15Or), (TXPREPN_STRUCT *)&TxPrePNDataDqsV15Or}, - {GET_SIZE_OF (TxPrePNDataDqsV135Or), (TXPREPN_STRUCT *)&TxPrePNDataDqsV135Or}, - {GET_SIZE_OF (TxPrePNDataDqsV125Or), (TXPREPN_STRUCT *)&TxPrePNDataDqsV125Or} - }; - - // - // Phy Predriver Calibration Codes for Data/DQS - // - CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV15OrB1[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.5V - {DDR667 + DDR800, {0xB6D, 0x6DB, 0x492, 0x492}}, - {DDR1066 + DDR1333, {0xFFF, 0x924, 0x6DB, 0x6DB}}, - {DDR1600 + DDR1866, {0xFFF, 0xFFF, 0xFFF, 0xB6D}} - }; - CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV135OrB1[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.35V - {DDR667 + DDR800, {0xFFF, 0x924, 0x6DB, 0x492}}, - {DDR1066 + DDR1333, {0xFFF, 0xDB6, 0xB6D, 0x6DB}}, - {DDR1600 + DDR1866, {0xFFF, 0xFFF, 0xFFF, 0xDB6}} - }; - CONST STATIC TXPREPN_STRUCT TxPrePNDataDqsV125OrB1[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.25V - {DDR667 + DDR800, {0xFFF, 0xB6D, 0x924, 0x6DB}}, - {DDR1066 + DDR1333, {0xFFF, 0xFFF, 0xDB6, 0x924}}, - {DDR1600 + DDR1866, {0xFFF, 0xFFF, 0xFFF, 0xFFF}} - }; - CONST STATIC TXPREPN_ENTRY TxPrePNDataDqsOrB1[] = { - {GET_SIZE_OF (TxPrePNDataDqsV15OrB1), (TXPREPN_STRUCT *)&TxPrePNDataDqsV15OrB1}, - {GET_SIZE_OF (TxPrePNDataDqsV135OrB1), (TXPREPN_STRUCT *)&TxPrePNDataDqsV135OrB1}, - {GET_SIZE_OF (TxPrePNDataDqsV125OrB1), (TXPREPN_STRUCT *)&TxPrePNDataDqsV125OrB1} - }; - - // - // Phy Predriver Calibration Codes for Cmd/Addr - // - CONST STATIC TXPREPN_STRUCT TxPrePNCmdAddrV15Or[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.5V - {DDR667 + DDR800, {0x492, 0x492, 0x492, 0x492}}, - {DDR1066 + DDR1333, {0x6DB, 0x6DB, 0x6DB, 0x6DB}}, - {DDR1600 + DDR1866, {0xB6D, 0xB6D, 0xB6D, 0xB6D}} - }; - CONST STATIC TXPREPN_STRUCT TxPrePNCmdAddrV135Or[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.35V - {DDR667 + DDR800, {0x492, 0x492, 0x492, 0x492}}, - {DDR1066 + DDR1333, {0x924, 0x6DB, 0x6DB, 0x6DB}}, - {DDR1600 + DDR1866, {0xB6D, 0xB6D, 0x924, 0x924}} - }; - CONST STATIC TXPREPN_STRUCT TxPrePNCmdAddrV125Or[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.25V - {DDR667 + DDR800, {0x492, 0x492, 0x492, 0x492}}, - {DDR1066 + DDR1333, {0xDAD, 0x924, 0x6DB, 0x492}}, - {DDR1600 + DDR1866, {0xFF6, 0xDAD, 0xB64, 0xB64}} - }; - CONST STATIC TXPREPN_ENTRY TxPrePNCmdAddrOr[] = { - {GET_SIZE_OF (TxPrePNCmdAddrV15Or), (TXPREPN_STRUCT *)&TxPrePNCmdAddrV15Or}, - {GET_SIZE_OF (TxPrePNCmdAddrV135Or), (TXPREPN_STRUCT *)&TxPrePNCmdAddrV135Or}, - {GET_SIZE_OF (TxPrePNCmdAddrV125Or), (TXPREPN_STRUCT *)&TxPrePNCmdAddrV125Or} - }; - - // - // Phy Predriver Calibration Codes for Clock - // - CONST STATIC TXPREPN_STRUCT TxPrePNClockV15Or[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.5V - {DDR667 + DDR800, {0x924, 0x924, 0x924, 0x924}}, - {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xB6D}}, - {DDR1600 + DDR1866, {0xFF6, 0xFF6, 0xFF6, 0xFF6}} - }; - CONST STATIC TXPREPN_STRUCT TxPrePNClockV135Or[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.35V - {DDR667 + DDR800, {0xDAD, 0xDAD, 0x924, 0x924}}, - {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xDAD}}, - {DDR1600 + DDR1866, {0xFF6, 0xFF6, 0xFF6, 0xDAD}} - }; - CONST STATIC TXPREPN_STRUCT TxPrePNClockV125Or[] = { - //{TxPreP, TxPreN}[Speed][Drive Strength] at 1.25V - {DDR667 + DDR800, {0xDAD, 0xDAD, 0x924, 0x924}}, - {DDR1066 + DDR1333, {0xFF6, 0xFF6, 0xFF6, 0xFF6}}, - {DDR1600 + DDR1866, {0xFF6, 0xFF6, 0xFF6, 0xFF6}} - }; - CONST STATIC TXPREPN_ENTRY TxPrePNClockOr[] = { - {GET_SIZE_OF (TxPrePNClockV15Or), (TXPREPN_STRUCT *)&TxPrePNClockV15Or}, - {GET_SIZE_OF (TxPrePNClockV135Or), (TXPREPN_STRUCT *)&TxPrePNClockV135Or}, - {GET_SIZE_OF (TxPrePNClockV125Or), (TXPREPN_STRUCT *)&TxPrePNClockV125Or} - }; - - // - // Tables to describe the relationship between drive strength bit fields, PreDriver Calibration bit fields and also - // the extra value that needs to be written to specific PreDriver bit fields - // - CONST PHY_COMP_INIT_NB PhyCompInitBitFieldOr[] = { - // 3. Program TxPreP/TxPreN for Data and DQS according toTable 46 if VDDIO is 1.5V or Table 47 if 1.35V. - // A. Program D18F2x9C_x0D0F_0[F,8:0]0[A,6]_dct[1:0]={0000b, TxPreP, TxPreN}. - // B. Program D18F2x9C_x0D0F_0[F,8:0]0[A,6]_dct[1:0]={0000b, TxPreP, TxPreN}. - {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, TxPrePNDataDqsOr}, - {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, TxPrePNDataDqsOr}, - {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, TxPrePNDataDqsOr}, - // 4. Program TxPreP/TxPreN for Cmd/Addr according to Table 49 if VDDIO is 1.5V or Table 50 if 1.35V. - // A. Program D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[1:0]={0000b, TxPreP, TxPreN}. - // B. Program D18F2x9C_x0D0F_[C,8][1:0]02_dct[1:0]={1000b, TxPreP, TxPreN}. - {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, TxPrePNCmdAddrOr}, - {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, TxPrePNCmdAddrOr}, - {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, TxPrePNCmdAddrOr}, - {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, TxPrePNCmdAddrOr}, - {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, TxPrePNCmdAddrOr}, - // 5. Program TxPreP/TxPreN for Clock according to Table 52 if VDDIO is 1.5V or Table 53 if 1.35V. - // A. Program D18F2x9C_x0D0F_2[2:0]02_dct[1:0]={1000b, TxPreP, TxPreN}. - {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock2TxPreDriverCalPad0, 8, TxPrePNClockOr} - }; - - BIT_FIELD_NAME CurrentBitField; - UINT16 SpeedMask; - UINT8 SizeOfTable; - UINT8 Voltage; - UINT8 i; - UINT8 j; - UINT8 k; - UINT8 Dct; - CONST TXPREPN_STRUCT *TblPtr; - - Dct = NBPtr->Dct; - NBPtr->SwitchDCT (NBPtr, 0); - // 1. Program D18F2x[1,0]9C_x0D0F_E003[DisAutoComp, DisablePreDriverCal] = {1b, 1b}. - MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x6000); - NBPtr->SwitchDCT (NBPtr, Dct); - - SpeedMask = (UINT16) 1 << (NBPtr->DCTPtr->Timings.Speed / 66); - Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage); - - for (j = 0; j < GET_SIZE_OF (PhyCompInitBitFieldOr); j ++) { - i = (UINT8) MemNGetBitFieldNb (NBPtr, PhyCompInitBitFieldOr[j].IndexBitField); - TblPtr = (PhyCompInitBitFieldOr[j].TxPrePN[Voltage]).TxPrePNTblPtr; - SizeOfTable = (PhyCompInitBitFieldOr[j].TxPrePN[Voltage]).TxPrePNTblSize; - - // Uses different TxPrePNDataDqsOr table for OR B1 and later - if (((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F15_OR_LT_B1) == 0) && - (PhyCompInitBitFieldOr[j].TxPrePN == TxPrePNDataDqsOr)) { - ASSERT (Voltage < sizeof (TxPrePNDataDqsOrB1) / sizeof (TxPrePNDataDqsOrB1[0])); - TblPtr = TxPrePNDataDqsOrB1[Voltage].TxPrePNTblPtr; - SizeOfTable = TxPrePNDataDqsOrB1[Voltage].TxPrePNTblSize; - } - - for (k = 0; k < SizeOfTable; k++, TblPtr++) { - if ((TblPtr->Speed & SpeedMask) != 0) { - for (CurrentBitField = PhyCompInitBitFieldOr[j].StartTargetBitField; CurrentBitField <= PhyCompInitBitFieldOr[j].EndTargetBitField; CurrentBitField ++) { - MemNSetBitFieldNb (NBPtr, CurrentBitField, ((PhyCompInitBitFieldOr[j].ExtraValue << 12) | TblPtr->TxPrePNVal[i])); - } - break; - } - } - // Asserting if no table is found corresponding to current memory speed. - ASSERT (k < SizeOfTable); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes before DRAM training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNBeforeDQSTrainingOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT32 PackageType; - - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_OR; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - // - // 2.10.6.8.2 - BIOS should program D18F2x210_dct[1:0]_nbp[3:0][MaxRdLatency] to 55h. - // - MemNSetBitFieldNb (NBPtr, BFMaxLatency, 0x55); - } - MemNSetBitFieldNb (NBPtr, BFTraceModeEn, 0); - } - - // DisDatMsk: Reset: 0. BIOS: IF (G34r1 || C32r1) THEN 1 ELSE 0 ENDIF. - PackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader)); - if (PackageType != PACKAGE_TYPE_AM3r2) { - MemNSetBitFieldNb (NBPtr, BFDisDatMsk, 1); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a function that executes after DRAM training for Orochi - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNAfterDQSTrainingOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 Dimm; - UINT8 Byte; - UINT16 Dly; - BOOLEAN DllShutDownEn; - - DllShutDownEn = TRUE; - IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader)); - - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_OR; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - // - // 2.10.6.6 DCT Training Specific Configuration - // - MemNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 1); - MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0); - if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) { - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); - } - MemNSetBitFieldNb (NBPtr , BFForceAutoPchg, 0); - MemNSetBitFieldNb (NBPtr , BFDynPageCloseEn, 0); - if (NBPtr->RefPtr->EnableBankSwizzle) { - MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); - } - MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0x0F); - MemNPowerDownCtlOr (NBPtr); - MemNSetBitFieldNb (NBPtr, BFDisSimulRdWr, 0); - MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2); - // - // Post Training values for BFRxMaxDurDllNoLock, BFTxMaxDurDllNoLock, - // and BFEnRxPadStandby are handled by Power savings code - // - // BFBwCapEn and BFODTSEn are handled by OnDimmThermal Code - // - // BFDctSelIntLvEn is programmed by Interleaving feature - // - // BFL3Scrub, BFDramScrub, and DramScrubReDirEn are programmed by ECC Feature code - // - // - MemNSetBitFieldNb (NBPtr, BFL3ScrbRedirDis, 0); - // Doing DataTxFifoWrDly override for NB PState 0 - MemNDataTxFifoWrDlyOverrideOr (NBPtr, NBPtr); - } - } - - // - // Synch RdDqs__Dly to RdDqsDly for S3 Save/Restore - // - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_OR; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - if (!(NBPtr->DctCachePtr->Is__x4)) { - // Only synch when 1D training has been performed or training with x8 DIMMs - for (Dimm = 0; Dimm < 4; Dimm++) { - for (Byte = 0; Byte < 9; Byte++) { - Dly = (UINT16) MemNGetTrainDlyNb (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, Byte)); - MemNSetTrainDlyNb (NBPtr, AccessRdDqs__Dly, DIMM_NBBL_ACCESS (Dimm, Byte * 2), Dly); - MemNSetTrainDlyNb (NBPtr, AccessRdDqs__Dly, DIMM_NBBL_ACCESS (Dimm, (Byte * 2) + 1), Dly); - NBPtr->ChannelPtr->RdDqs__Dlys[(Dimm * MAX_NUMBER_LANES) + (Byte * 2)] = (UINT8) Dly; - NBPtr->ChannelPtr->RdDqs__Dlys[(Dimm * MAX_NUMBER_LANES) + (Byte * 2) + 1] = (UINT8) Dly; - } - } - } - } - } -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the seed for hardware based RcvEn training of Orochi. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *SeedPtr - Pointer to the seed value. - * - * @return TRUE - */ - -BOOLEAN -MemNOverrideRcvEnSeedOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *SeedPtr - ) -{ - UINT16 *SeedPointer; - SeedPointer = (UINT16*) SeedPtr; - - // - // Get seed value saved in PS block - // - *SeedPointer = NBPtr->PsPtr->HWRxENSeedVal; - *SeedPointer -= (0x20 * (UINT16) MemNGetBitFieldNb (NBPtr, BFWrDqDqsEarly)); - - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the seed for Pass N hardware based RcvEn training of Orochi. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *SeedTotal - Pointer to the SeedTotal - * - * @return TRUE - */ - -BOOLEAN -MemNOverrideRcvEnSeedPassNOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *SeedTotal - ) -{ - UINT16 RegisterDelay; - UINT16 SeedTotalPreScaling; - UINT8 *SpdBufferPtr; - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - // LRDIMMs - NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, (NBPtr->TechPtr->ChipSel >> 1)); - RegisterDelay = 0x10 + (((SpdBufferPtr[67] & 1) == 0) ? (0x30 - (SpdBufferPtr[70] & 7)): 0x30); - } else if (NBPtr->MCTPtr->Status[SbRegistered]) { - // Registered - RegisterDelay = ((NBPtr->ChannelPtr->CtrlWrd02[(NBPtr->TechPtr->ChipSel >> 1)] & BIT0) == 0) ? 0x20: 0x30; - } else { - // UDIMMs - RegisterDelay = 0; - } - if (NBPtr->TechPtr->PrevPassRcvEnDly[NBPtr->TechPtr->Bytelane] < (0x20 + RegisterDelay)) { - SeedTotalPreScaling = 0x20 + RegisterDelay; - } else { - SeedTotalPreScaling = NBPtr->TechPtr->PrevPassRcvEnDly[NBPtr->TechPtr->Bytelane] - 0x20 - RegisterDelay; - } - *(UINT16*) SeedTotal = ((UINT16) (((UINT32) SeedTotalPreScaling * NBPtr->DCTPtr->Timings.Speed) / NBPtr->TechPtr->PrevSpeed)) + RegisterDelay; - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the seed for write leveing training of Orochi. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *SeedPtr - Pointer to the seed value. - * - * @return TRUE - */ - -BOOLEAN -MemNOverrideWLSeedOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *SeedPtr - ) -{ - DIE_STRUCT *MCTPtr; - CH_DEF_STRUCT *ChannelPtr; - UINT8 RCW2; - - MCTPtr = NBPtr->MCTPtr; - ChannelPtr = NBPtr->ChannelPtr; - RCW2 = ChannelPtr->CtrlWrd02[NBPtr->TechPtr->TargetDIMM]; - - // - // Get the default value of seed - // - if (ChannelPtr->SODimmPresent != 0) { - // - // SODIMMM - // - *(UINT8*) SeedPtr = 0x12; - } else { - // - // Get seed value saved in PS block - // - *(UINT8*) SeedPtr = NBPtr->PsPtr->WLSeedVal; - - if (MCTPtr->Status[SbRegistered]) { - *(UINT8*) SeedPtr += ((RCW2 & BIT0) == 0) ? 0 : 0x10; - } - } - - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function enables nibble based training for Write Levelization for Orochi. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *Dimm - Pointer to DIMM to be trained - * - * @return TRUE - */ - -BOOLEAN -MemNTrainWlPerNibbleOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *Dimm - ) -{ - UINT8 ByteLane; - if ((NBPtr->ChannelPtr->Dimmx4Present & (1 << *(UINT16*) Dimm)) != 0) { - if (NBPtr->TechPtr->TrnNibble <= NIBBLE_1) { - //For x4 DIMMs, BIOS trains both nibbles of a byte lane by programming - //D18F2x9C_x0000_0008_dct[1:0][TrNibbleSel] to specify the nibble. BIOS repeats steps 3 through - //5 and uses the average of the trained values for the delay setting. - if (NBPtr->TechPtr->TrnNibble == NIBBLE_1) { - NBPtr->SetBitField (NBPtr, BFTrNibbleSel, NBPtr->TechPtr->TrnNibble); - } - return FALSE; - } else { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrDqs: "); - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8) ; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", NBPtr->TechPtr->WlNibbleDly[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, " <<< Nibble AVG\n\n"); - return FALSE; - } - } else { - return TRUE; - } -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function adjusts the WL DQS Delay based on nibble traning results for Orochi. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *Delay - Pointer to Wr Dqs Delay - * - * @return FALSE - Supported - * @return TRUE - Not supported - */ -BOOLEAN -MemNTrainWlPerNibbleAdjustWLDlyOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *Delay - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 Bytelane; - TechPtr = NBPtr->TechPtr; - Bytelane = TechPtr->Bytelane; - if ((NBPtr->ChannelPtr->DimmNibbleAccess & (1 << TechPtr->TargetDIMM)) != 0) { - if (TechPtr->TrnNibble == NIBBLE_1) { - *(UINT8*) Delay = (TechPtr->WlNibbleDly[Bytelane] + *(UINT8*) Delay + 1) / 2; - if (Bytelane == (NBPtr->MCTPtr->Status[SbEccDimms] ? 8 : 7)) { - IDS_HDT_CONSOLE (MEM_FLOW, " <<< Nibble 1"); - } - } else { - if (Bytelane == (NBPtr->MCTPtr->Status[SbEccDimms] ? 8 : 7)) { - IDS_HDT_CONSOLE (MEM_FLOW, " <<< Nibble 0"); - } - } - TechPtr->WlNibbleDly[Bytelane] = *(UINT8*) Delay; - return FALSE; - } else { - return TRUE; - } -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the correct seed for Nibble based Write Levelization. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *WrDqsDly - Pointer to WrDqs value - * - * @return FALSE - Supported - * @return TRUE - Not supported - */ - -BOOLEAN -MemNTrainWlPerNibbleSeedOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *WrDqsDly - ) -{ - if (NBPtr->TechPtr->TrnNibble == NIBBLE_0) { - NBPtr->TechPtr->WlNibble0Seed[NBPtr->TechPtr->Bytelane] = *(UINT16*) WrDqsDly; - } else { - *(UINT16*) WrDqsDly = NBPtr->TechPtr->WlNibble0Seed[NBPtr->TechPtr->Bytelane]; - } - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes nibble based Receiver Enable Training for Orochi. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *OptParam - Optional paramater - * - * @return FALSE - Supported - * @return TRUE - Not supported - */ -BOOLEAN -MemNInitPerNibbleTrnOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - // Program D18F2x9C_x0000_0008_dct[1:0][TrNibbleSel]=0 - NBPtr->TechPtr->TrnNibble = NIBBLE_0; - NBPtr->SetBitField (NBPtr, BFTrNibbleSel, NIBBLE_0); - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function enables nibble based Receiver Enable Training for Orochi. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *ChipSel - Pointer to ChipSel to be trained - * - * @return FALSE - Supported - * @return TRUE - Not supported - */ - -BOOLEAN -MemNTrainRxEnPerNibbleOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *ChipSel - ) -{ - if ((NBPtr->ChannelPtr->DimmNibbleAccess & (1 << (*(UINT16*) ChipSel >> 1))) != 0) { - if (NBPtr->TechPtr->TrnNibble == NIBBLE_1) { - // For x4 DIMMs, BIOS trains both nibbles of a byte lane by programming - // D18F2x9C_x0000_0008_dct[1:0][TrNibbleSel] to specify the nibble. BIOS repeats steps 2 through - // 7 and uses the average of the trained values for the delay setting. - NBPtr->SetBitField (NBPtr, BFTrNibbleSel, NBPtr->TechPtr->TrnNibble); - } - return FALSE; - } else { - return TRUE; - } -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function adjusts the RxEn Delay based on nibble traning results for Orochi. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *RcvEnDly - Pointer to RcvEn Dqs Delay - * - * @return FALSE - Supported - * @return TRUE - Not supported - */ -BOOLEAN -MemNTrainRxEnAdjustDlyPerNibbleOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *RcvEnDly - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 Bytelane; - TechPtr = NBPtr->TechPtr; - Bytelane = TechPtr->Bytelane; - if ((NBPtr->ChannelPtr->DimmNibbleAccess & (1 << (TechPtr->ChipSel >> 1))) != 0) { - if (TechPtr->TrnNibble == NIBBLE_1) { - *(UINT16*) RcvEnDly = (TechPtr->RxEnNibbleDly[Bytelane] + *(UINT16*) RcvEnDly + 1) / 2; - if (Bytelane == (NBPtr->MCTPtr->Status[SbEccDimms] ? 8 : 7)) { - IDS_HDT_CONSOLE (MEM_FLOW, " <<< Nibble 1"); - } - TechPtr->RxEnNibbleDly[Bytelane] = *(UINT16*) RcvEnDly; - return TRUE; - } else { - if (Bytelane == (NBPtr->MCTPtr->Status[SbEccDimms] ? 8 : 7)) { - IDS_HDT_CONSOLE (MEM_FLOW, " <<< Nibble 0"); - } - TechPtr->RxEnNibbleDly[Bytelane] = *(UINT16*) RcvEnDly; - return FALSE; - } - } else { - return TRUE; - } -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the average nibble based Receiver Enable Training for Orochi. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *OptParam - Optional parameter - * - * @return FALSE - Supported - * @return TRUE - Not supported - */ - -BOOLEAN -MemNTrainRxEnGetAvgDlyPerNibbleOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 ByteLane; - if ((NBPtr->ChannelPtr->DimmNibbleAccess & (1 << (NBPtr->TechPtr->ChipSel >> 1))) != 0) { - if (NBPtr->TechPtr->TrnNibble == NIBBLE_1) { - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t RxEn: "); - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8) ; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", NBPtr->TechPtr->RxEnNibbleDly[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, " <<< Nibble AVG\n\n"); - return TRUE; - } else { - return FALSE; - } - } else { - return TRUE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns false if nibble training is being used and nibble 1 - * is being trained. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *ChipSel - Pointer to ChipSel to be trained - * - * @return FALSE - Supported - * @return TRUE - Not supported - */ - -BOOLEAN -MemNTrainingNibbleZeroOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *ChipSel - ) -{ - if (((NBPtr->ChannelPtr->DimmNibbleAccess & (1 << (NBPtr->TechPtr->ChipSel >> 1))) != 0) && - (NBPtr->TechPtr->TrnNibble == NIBBLE_1)) { - return FALSE; - } else { - return TRUE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function adjusts Avg PRE value of Phy fence training for OR. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *Value16 - Pointer to the value that we want to adjust - * - */ -VOID -MemNPFenceAdjustOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT INT16 *Value16 - ) -{ - *Value16 += 2; //The Avg PRE value is subtracted by 6 only. - if (*Value16 < 0) { - *Value16 = 0; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function adjusts WrDqsBias before seed scaling - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *WrDqsBias - Pointer to WrDqsBias - * - * @return FALSE - Supported - * @return TRUE - Not supported - */ - -BOOLEAN -MemNAdjustWrDqsBeforeSeedScalingOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *WrDqsBias - ) -{ - // Subtract (0x20 * WrDqDqsEarly) since it is a non-scalable component - * (INT16 *) WrDqsBias = (INT16) (0x20 * MemNGetBitFieldNb (NBPtr, BFWrDqDqsEarly)); - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c deleted file mode 100644 index 65addd5da0..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c +++ /dev/null @@ -1,99 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnprotoor.c - * - * Northbridge support functions for Errata and early samples - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/OR) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "Filecode.h" -#include "cpuRegisters.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_NB_OR_MNPROTOOR_FILECODE - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -MemNInitEarlySampleSupportOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes early sample support for Orochi - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNInitEarlySampleSupportOr ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F15_OR_Ax) != 0) { - NBPtr->IsSupported[PchgPDMode] = FALSE; // Erratum 506 - NBPtr->IsSupported[ChannelPDMode] = TRUE; // Erratum 506 - NBPtr->NBRegTable[BFReserved00C] = 0; // Erratum 473 - } -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c deleted file mode 100644 index a29093f072..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c +++ /dev/null @@ -1,922 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnregor.c - * - * Common Northbridge register related functions for Orochi - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/OR) - * @e \$Revision: 58126 $ @e \$Date: 2011-08-21 23:38:29 -0600 (Sun, 21 Aug 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnor.h" -#include "merrhdl.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_NB_OR_MNREGOR_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define PHY_DIRECT_ADDRESS_MASK 0x0D000000 - -STATIC CONST UINT8 InstancesPerTypeOR[8] = {9, 3, 1, 0, 2, 0, 1, 1}; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*-----------------------------------------------------------------------------*/ -/** - * MemNIsIdSupportedOr - * This function matches the CPU_LOGICAL_ID with certain criteria to - * determine if it is supported by this NBBlock. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID - * - * @return TRUE - This node is a Orochi. - * @return FALSE - This node is not a Orochi. - * - */ -BOOLEAN -MemNIsIdSupportedOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID *LogicalIdPtr - ) -{ - if (((LogicalIdPtr->Family & AMD_FAMILY_15_OR) != 0) - && ((LogicalIdPtr->Revision & AMD_F15_ALL) != 0)) { - return TRUE; - } else { - return FALSE; - } -} - -/*-----------------------------------------------------------------------------*/ -/** - * This function calculates the memory channel index relative to the - * socket, taking the Die number, the Dct, and the channel. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Dct - * @param[in] Channel - * - */ -UINT8 -MemNGetSocketRelativeChannelOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct, - IN UINT8 Channel - ) -{ - return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_OR) + Dct); -} -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets or sets a value to a bit field in a PCI register. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Bit Field to be programmed - * @param[in] Field - Value to be programmed - * @param[in] IsSet - Indicates if the function will set or get - * - * @return value read, if the function is used as a "get" - */ - -UINT32 -MemNCmnGetSetFieldOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ) -{ - TSEFO Address; - PCI_ADDR PciAddr; - UINT8 Type; - UINT8 IsLinked; - UINT32 Value; - UINT32 Highbit; - UINT32 Lowbit; - UINT32 Mask; - UINT8 IsPhyDirectAccess; - UINT8 IsWholeRegAccess; - UINT8 NumOfInstances; - UINT8 Instance; - - Value = 0; - if (FieldName < BFEndOfList) { - Address = NBPtr->NBRegTable[FieldName]; - if (Address) { - Lowbit = TSEFO_END (Address); - Highbit = TSEFO_START (Address); - Type = (UINT8) TSEFO_TYPE (Address); - IsLinked = (UINT8) TSEFO_LINKED (Address); - IsPhyDirectAccess = (UINT8) TSEFO_DIRECT_EN (Address); - IsWholeRegAccess = (UINT8) TSEFO_WHOLE_REG_ACCESS (Address); - - ASSERT ((Address & ((UINT32) 1) << 29) == 0); // Old Phy direct access method is not supported - - Address = TSEFO_OFFSET (Address); - - // By default, a bit field has only one instance - NumOfInstances = 1; - - if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { - Address |= PHY_DIRECT_ADDRESS_MASK; - if (IsWholeRegAccess) { - // In the case of whole regiter access (bit 0 to 15), - // HW broadcast and nibble mask will be used. - Address |= Lowbit << 16; - Lowbit = 0; - Highbit = 15; - } else { - // In the case only some bits on a register is accessed, - // BIOS will do read-mod-write to all chiplets manually. - // And nibble mask will be 1111b always. - Address |= 0x000F0000; - Field >>= Lowbit; - if ((Address & 0x0F00) == 0x0F00) { - // Broadcast mode - // Find out how many instances to write to - NumOfInstances = InstancesPerTypeOR[(Address >> 13) & 0x7]; - if (!IsSet) { - // For read, only read from instance 0 in broadcast mode - NumOfInstances = 1; - } - } - } - } - - ASSERT (NumOfInstances > 0); - - for (Instance = 0; Instance < NumOfInstances; Instance++) { - if (Type == NB_ACCESS) { - PciAddr.AddressValue = Address; - PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; - PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; - PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; - Address = PciAddr.AddressValue; - LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn%d_%03x = %x\n", - NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0x7, Address & 0xFFF, Value); - } - } else if (Type == DCT_PHY_ACCESS) { - if (IsPhyDirectAccess && (NumOfInstances > 1)) { - Address = (Address & 0x0FFFF0FF) | (((UINT32) Instance) << 8); - } - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn2_9C_%x = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, Address & 0x0FFFFFFF, Value); - } else if (Type == DCT_EXTRA) { - MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); - // @attention: DctExtraAccessDone not implemented in Orochi - //MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg); - } else { - IDS_ERROR_TRAP; - } - - if (IsSet) { - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - if ((Highbit - Lowbit) != 31) { - Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); - } else { - Mask = (UINT32)0xFFFFFFFF; - } - Value &= ~(Mask << Lowbit); - Value |= (Field & Mask) << Lowbit; - - if (Type == NB_ACCESS) { - PciAddr.AddressValue = Address; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn%d_%03x [%d:%d] = %x\n", - NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); - } - } else if (Type == DCT_PHY_ACCESS) { - MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn2_9C_%x [%d:%d] = %x\n", - NBPtr->PciAddr.Address.Device, NBPtr->Dct, - Address & 0x0FFFFFFF, Highbit, Lowbit, Field); - } else if (Type == DCT_EXTRA) { - MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); - // @attention: DctExtraAccessDone not implemented in Orochi - //MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - } else { - IDS_ERROR_TRAP; - } - if (IsLinked) { - MemNCmnGetSetFieldOr (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); - } - } else { - Value = Value >> Lowbit; // Shift - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - if ((Highbit - Lowbit) != 31) { - Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); - } - if (IsLinked) { - Value |= MemNCmnGetSetFieldOr (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); - } - // For direct phy access, shift the bit back for compatibility reason. - if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { - Value <<= Lowbit; - } - } - } - } - } else { - IDS_ERROR_TRAP; // Invalid bit field index - } - return Value; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes bit field translation table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] NBRegTable[] - Pointer to the bit field data structure - * - */ - -VOID -MemNInitNBRegTableOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT TSEFO NBRegTable[] - ) -{ - UINT16 i; - - // Allocate heap for NB register table - if (!MemNAllocateNBRegTableNb (NBPtr, NbRegTabOR)) { - return; // escape if fails - } - NBRegTable = NBPtr->NBRegTable; - - for (i = 0; i < BFEndOfList; i++) { - NBRegTable[i] = 0; - } - // --------------------------------------------------------------------------- - // - // FUNCTION 0 - // - // --------------------------------------------------------------------------- - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); - - // --------------------------------------------------------------------------- - // - // FUNCTION 1 - // - // --------------------------------------------------------------------------- - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 2, 2, BFDramHtHoleValid); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x10C), 5, 4, BFNbPsSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x10C), 0, 0, BFDctCfgSel); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 23, 21, BFDramIntlvEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); - // --------------------------------------------------------------------------- - // - // FUNCTION 2 - // - // --------------------------------------------------------------------------- - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 1, 0, BFRankDef0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 1, 0, BFRankDef1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 1, 0, BFRankDef2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 1, 0, BFRankDef3); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 17, 17, BFAddrCmdTriEn); ///< Orochi - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFReserved001); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFReserved002); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 23, 21, BFMrsChipSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 20, 18, BFMrsBank); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 17, 0, BFMrsAddress); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 17, 13, BFMrsAddressHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 29, 24, BFMemClkDis); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 25, 25, BFPendRefPaybackS3En); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 24, 24, BFStagRefEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 20, 20, BFDynPageCloseEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankRDimm1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 13, 13, BFDisSimulRdWr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 7, 7, BFMemClkFreqVal); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 4, 0, BFMemClkFreq); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); ///< Orochi Read Only - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 31, BFRcvParErr); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 11, 11, BFBwCapEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 29, 29, BFRefChCmdMgtDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 28, 28, BFFastSelfRefEntryDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 27, 27, BFCSMux67); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 26, 26, BFCSMux45); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 25, 24, BFWrDqDqsEarly); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 22, 22, BFPrtlChPDEnhEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 21, 21, BFAggrPDEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 7, 7, BFLrDimmMrsCtrl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFLrDimmErrOutMonEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 4, 4, BFExtendedParityEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 3, 3, BFLrDimmEnhRefEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFCSTimingMux67); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xC0), 0, 0, BFTraceModeEn); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 0, 0, BFIntLvRgnSwapEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 9, 3, BFIntLvRgnBaseAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 17, 11, BFIntLvRgnLmtAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 26, 20, BFIntLvRgnSize); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 19, 19, BFLockDramCfg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 18, 18, BFCC6SaveEn); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31, 0, BFExtMctCfgLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B4), 31, 0, BFExtMctCfgHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B4), 27, 27, BFFlushWrOnS3StpGnt); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200), 29, 24, BFTras); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200), 20, 16, BFTrp); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200), 12, 8, BFTrcd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x200), 4, 0, BFTcl); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204), 27, 24, BFTrtp); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204), 21, 16, BFFourActWindow); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204), 11, 8, BFTrrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x204), 5, 0, BFTrc); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208), 26, 24, BFTrfc3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208), 18, 16, BFTrfc2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208), 10, 8, BFTrfc1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x208), 2, 0, BFTrfc0); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x20C), 11, 8, BFTwtr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x20C), 4, 0, BFTcwl); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x210), 31, 22, BFMaxLatency); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x210), 18, 16, BFDataTxFifoWrDly); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x210), 3, 0, BFRdPtrInit); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x214), 19, 16, BFTwrwrSdSc); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x214), 11, 8, BFTwrwrSdDc); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x214), 3, 0, BFTwrwrDd); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218), 27, 24, BFTrdrdSdSc); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218), 19, 16, BFTrdrdSdDc); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218), 11, 8, BFTwrrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x218), 3, 0, BFTrdrdDd); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x21C), 20, 16, BFTrwtWB); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x21C), 12, 8, BFTrwtTO); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x220), 12, 8, BFTmod); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x220), 3, 0, BFTmrd); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x224), 10, 8, BFTzqcs); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x224), 3, 0, BFTzqoper); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228), 31, 24, BFTstag3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228), 23, 16, BFTstag2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228), 15, 8, BFTstag1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x228), 7, 0, BFTstag0); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x22C), 4, 0, BFTwrDDR3); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x230), 31, 0, BFPhyRODTCSLow); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x234), 31, 0, BFPhyRODTCSHigh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x238), 31, 0, BFPhyWODTCSLow); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x23C), 31, 0, BFPhyWODTCSHigh); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240), 14, 12, BFWrOdtOnDuration); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240), 10, 8, BFWrOdtTrnOnDly); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240), 7, 4, BFRdOdtOnDuration); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x240), 3, 0, BFRdOdtTrnOnDly); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x244), 3, 0, BFPrtlChPDDynDly); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248), 29, 24, BFAggrPDDelay); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248), 21, 16, BFPchgPDEnDelay); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248), 12, 8, BFTxpdll); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x248), 3, 0, BFTxp); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x24C), 31, 0, BFDramPwrMngm1Reg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 12, 12, BFCmdSendInProg ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 11, 11, BFSendCmd ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 10, 10, BFTestStatus ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 9, 8, BFCmdTgt ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 7, 5, BFCmdType ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 4, 4, BFStopOnErr ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 3, 3, BFResetAllErr ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 2, 2, BFCmdTestEnable ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 13, 13, BFReserved003 ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x250), 7, 3, BFReserved004 ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x254), 26, 24, BFTgtChipSelectA ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x254), 23, 21, BFTgtBankA ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x254), 9, 0, BFTgtAddressA ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x258), 26, 24, BFTgtChipSelectB ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x258), 23, 21, BFTgtBankB ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x258), 9, 0, BFTgtAddressB ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x25C), 31, 22, BFReserved008 ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x25C), 21, 12, BFReserved007 ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x25C), 7, 0, BFReserved006 ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x25C), 31, 0, BFReserved005 ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x260), 20, 0, BFCmdCount ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x264), 31, 25, BFErrDqNum ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x264), 24, 0, BFErrCnt ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x268), 17, 0, BFNibbleErrSts ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x26C), 17, 0, BFNibbleErr180Sts ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x270), 18, 0, BFDataPrbsSeed ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x274), 31, 0, BFDramDqMaskLow ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x278), 31, 0, BFDramDqMaskHigh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x27C), 7, 0, BFDramEccMask ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 31, 31, BFSendActCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 30, 30, BFSendPchgCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 29, 22, BFCmdChipSelect ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 21, 19, BFCmdBank ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 17, 0, BFCmdAddress ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x28C), 31, 0, BFDramCommand2 ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x290), 26, 24, BFErrBeatNum ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x290), 20, 0, BFErrCmdNum ); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x294), 31, 0, BFDQErrLow ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x298), 31, 0, BFDQErrHigh ); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x29C), 7, 0, BFEccErr ); - - // --------------------------------------------------------------------------- - // - // DCT PHY REGISTERS - // - // --------------------------------------------------------------------------- - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 2, 0, BFCkeDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 6, 4, BFCsOdtDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 10, 8, BFAddrCmdDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 14, 12, BFClkDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 18, 16, BFDataDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 22, 20, BFDqsDrvStren); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 31, 0, BFDramPhyCtlReg); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 7, 6, BFFenceTrSel); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 2, 2, BFTrNibbleSel); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0B, 31, 0, BFDramPhyStatusReg); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 31, 0, BFDRAMPhyDLLControl); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 25, 24, BFRxDLLWakeupTime); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 22, 20, BFRxCPUpdPeriod); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 19, 16, BFRxMaxDurDllNoLock); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 9, 8, BFTxDLLWakeupTime); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 6, 4, BFTxCPUpdPeriod); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 3, 0, BFTxMaxDurDllNoLock); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x50, 31, 0, BFRstRcvFifo); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13, 14, 14, BFProcOdtAdv); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13, 7, 0, BFPhy0x0D0F0F13); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0830, 4, 4, BFEccDLLPwrDnConf); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE013, 15, 0, BFPllRegWaitTime); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE006, 15, 0, BFPllLockTime); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F04, 13, 13, BFTriDM); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0F, 14, 12, BFAlwaysEnDllClks); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F02, 15, 0, BFDataByteTxPreDriverCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F06, 11, 0, BFDataByteTxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0A, 11, 0, BFDataByteTxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8006, 11, 0, BFCmdAddr0TxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F800A, 11, 0, BFCmdAddr0TxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8106, 11, 0, BFCmdAddr1TxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F810A, 11, 0, BFCmdAddr1TxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC006, 11, 0, BFAddrTxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00A, 11, 0, BFAddrTxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00E, 11, 0, BFAddrTxPreDriverCal2Pad3); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC012, 11, 0, BFAddrTxPreDriverCal2Pad4); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8002, 15, 15, BFCmdAddr0TxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8102, 15, 15, BFCmdAddr1TxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC002, 15, 15, BFAddrTxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2002, 15, 15, BFClock0TxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2102, 15, 15, BFClock1TxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2202, 15, 15, BFClock2TxPreDriverCalPad0); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F812F, 7, 0, BFAddrCmdTri); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10, 12, 12, BFEnRxPadStandby); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE003, 14, 13, BFDisablePredriverCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE00A, 4, 4, BFSkewMemClk); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2030, 4, 4, BFPhyClkConfig0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2130, 4, 4, BFPhyClkConfig1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2230, 4, 4, BFPhyClkConfig2); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC000, 8, 8, BFReserved00C); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F, 4, 3, BFDataRxVioLvl); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1F, 4, 3, BFClkRxVioLvl); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 3, 2, BFCsrComparator); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 15, 14, BFCmpVioLvl); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F, 4, 3, BFCmdRxVioLvl); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F, 4, 3, BFAddrRxVioLvl); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F31, 14, 0, BFDataFence2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F31, 4, 0, BFClkFence2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F31, 4, 0, BFCmdFence2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC031, 4, 0, BFAddrFence2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F30, 8, 8, BFBlockRxDqsLock); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F04, 13, 13, BFDataByteDMConf); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4007, 1, 0, BFReserved8_0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4007, 6, 2, BFReserved8_1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0020, 4, 0, BFReserved4_0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0020, 12, 8, BFReserved4_1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0120, 4, 0, BFReserved4_2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0120, 12, 8, BFReserved4_3); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0220, 4, 0, BFReserved4_4); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0220, 12, 8, BFReserved4_5); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0320, 4, 0, BFReserved4_6); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0320, 12, 8, BFReserved4_7); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0420, 4, 0, BFReserved4_8); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0420, 12, 8, BFReserved4_9); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0520, 4, 0, BFReserved4_A); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0520, 12, 8, BFReserved4_B); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0620, 4, 0, BFReserved4_C); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0620, 12, 8, BFReserved4_D); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0720, 4, 0, BFReserved4_E); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0720, 12, 8, BFReserved4_F); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0820, 4, 0, BFReserved4_10); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0820, 12, 8, BFReserved4_11); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F20, 15, 0, BFReserved4_12); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0021, 4, 0, BFReserved5_0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0021, 12, 8, BFReserved5_1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0121, 4, 0, BFReserved5_2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0121, 12, 8, BFReserved5_3); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0221, 4, 0, BFReserved5_4); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0221, 12, 8, BFReserved5_5); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0321, 4, 0, BFReserved5_6); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0321, 12, 8, BFReserved5_7); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0421, 4, 0, BFReserved5_8); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0421, 12, 8, BFReserved5_9); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0521, 4, 0, BFReserved5_A); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0521, 12, 8, BFReserved5_B); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0621, 4, 0, BFReserved5_C); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0621, 12, 8, BFReserved5_D); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0721, 4, 0, BFReserved5_E); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0721, 12, 8, BFReserved5_F); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0821, 4, 0, BFReserved5_10); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0821, 12, 8, BFReserved5_11); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F21, 15, 0, BFReserved5_12); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0022, 4, 0, BFReserved6_0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0022, 12, 8, BFReserved6_1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0122, 4, 0, BFReserved6_2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0122, 12, 8, BFReserved6_3); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0222, 4, 0, BFReserved6_4); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0222, 12, 8, BFReserved6_5); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0322, 4, 0, BFReserved6_6); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0322, 12, 8, BFReserved6_7); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0422, 4, 0, BFReserved6_8); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0422, 12, 8, BFReserved6_9); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0522, 4, 0, BFReserved6_A); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0522, 12, 8, BFReserved6_B); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0622, 4, 0, BFReserved6_C); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0622, 12, 8, BFReserved6_D); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0722, 4, 0, BFReserved6_E); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0722, 12, 8, BFReserved6_F); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0822, 4, 0, BFReserved6_10); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0822, 12, 8, BFReserved6_11); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F22, 15, 0, BFReserved6_12); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0023, 4, 0, BFReserved7_0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0023, 12, 8, BFReserved7_1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0123, 4, 0, BFReserved7_2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0123, 12, 8, BFReserved7_3); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0223, 4, 0, BFReserved7_4); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0223, 12, 8, BFReserved7_5); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0323, 4, 0, BFReserved7_6); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0323, 12, 8, BFReserved7_7); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0423, 4, 0, BFReserved7_8); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0423, 12, 8, BFReserved7_9); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0523, 4, 0, BFReserved7_A); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0523, 12, 8, BFReserved7_B); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0623, 4, 0, BFReserved7_C); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0623, 12, 8, BFReserved7_D); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0723, 4, 0, BFReserved7_E); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0723, 12, 8, BFReserved7_F); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0823, 4, 0, BFReserved7_10); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0823, 12, 8, BFReserved7_11); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F23, 15, 0, BFReserved7_12); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F3E, 0, 0, BFReserved00A); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4010, 31, 0, BFReserved009); - - // --------------------------------------------------------------------------- - // - // FUNCTION 3 - // - // --------------------------------------------------------------------------- - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 29, 29, BFMultiNodeCpu); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFReserved00B); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x1B8), 4, 4, BFL3ScrbRedirDis); - - // --------------------------------------------------------------------------- - // - // FUNCTION 4 - // - // --------------------------------------------------------------------------- - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x128), 17, 12, BFCoreStateSaveDestNode); - - // --------------------------------------------------------------------------- - // - // FUNCTION 5 - // - // --------------------------------------------------------------------------- - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x84), 20, 16, BFDdrMaxRate); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 31, 0, BFNbPstateCtlReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 14, 14, BFSwNbPstateLoDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 7, 6, BFNbPstateHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 4, 3, BFNbPstateLo); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x170), 1, 0, BFNbPstateMaxVal); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x174), 20, 19, BFCurNbPstate); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (5, 0x174), 0, 0, BFNbPstateDis); ///< Orochi Read Only - - IDS_OPTION_HOOK (IDS_INIT_MEM_REG_TABLE, NBPtr, &NBPtr->MemPtr->StdHeader); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mns3or.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mns3or.c deleted file mode 100644 index ee6b714aaa..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mns3or.c +++ /dev/null @@ -1,1257 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mns3or.c - * - * OR memory specific function to support S3 resume - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/OR) - * @e \$Revision: 59560 $ @e \$Date: 2011-09-26 11:43:44 -0600 (Mon, 26 Sep 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "mnor.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "F15PackageType.h" -#include "mnS3or.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_NB_OR_MNS3OR_FILECODE - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemS3ResumeConstructNBBlockOr ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -UINT16 -STATIC -MemNS3GetRegLstPtrOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ); - -AGESA_STATUS -STATIC -MemNS3GetDeviceRegLstOr ( - IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader - ); - -VOID -STATIC -MemNS3SetDfltPllLockTimeOr ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetDynModeChangeOr ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SaveMR0Or ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3RestoreMR0SetPPDOr ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -STATIC -MemNS3GetCSROr ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -STATIC -MemNS3SetCSROr ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -PCI_SPECIAL_CASE PciSpecialCaseFuncOr[] = { - {MemNS3GetCSROr, MemNS3SetCSROr}, - {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}, - {MemNS3GetNBPStateDepRegUnb, MemNS3SetNBPStateDepRegUnb}, - { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDfltPllLockTimeOr}, - { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDisAutoCompUnb}, - { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDynModeChangeOr}, - { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3DisableChannelNb}, - {MemNS3SaveNBRegiserUnb, MemNS3RestoreNBRegiserUnb}, - {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb}, - { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValUnb}, - {MemNS3SaveMR0Or, MemNS3RestoreMR0SetPPDOr} -}; - -PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorOr[] = { - {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFF8E7}, - {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF0703}, - {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF0703}, - {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF0703}, - {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF0703}, - {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF0703}, - {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF0703}, - {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF0703}, - {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF0703}, - {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, - {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0707}, - {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF0707}, - {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF0707}, - {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF0707}, - {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF0707}, - {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF0707}, - {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF0707}, - {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF0707}, - {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, - {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF87}, - {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, - {{0, 0, 0}, FUNC_1, 0x124, 0x00FFFFFF}, - {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9}, - {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, - {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, - {{0, 0, 0}, FUNC_2, 0x11C, 0xAFFFFFFF}, - {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}, - {{0, 2, 0}, FUNC_2, 0x1B4, 0x000003FF} -}; - -CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefOr = { - 0, - (sizeof (S3PciPreSelfRefDescriptorOr) / sizeof (PCI_REG_DESCRIPTOR)), - S3PciPreSelfRefDescriptorOr, - NULL -}; - -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorOr[] = { - // DCT 0 - {{7, 0, 1}, DCT0, 0x40, 0x7FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x44, 0x7FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x48, 0x7FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x4C, 0x7FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x50, 0x7FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x54, 0x7FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x58, 0x7FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x5C, 0x7FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x60, 0x7FF83FE3, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x64, 0x7FF83FE3, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x68, 0x7FF83FE3, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x6C, 0x7FF83FE3, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x78, 0x00020000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 2, 1}, DCT0, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x84, 0x00800003, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x88, 0x3F000000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x8C, 0x00070000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x90, 0x0BFDF100, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0xA4, 0x00F07900, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0xA8, 0x3F60FFBC, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x200, 0x3F1F1F1F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x204, 0x0F3F0F3F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x208, 0x07070707, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 2, 1}, DCT0, 0x20C, 0x00000F1F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 0), 0xFFCF000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 1), 0xFFCF000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 2), 0xFFCF000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 3), 0xFFCF000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x214, 0x000F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x218, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x21C, 0x001F1F00, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 2, 1}, DCT0, 0x220, 0x00001F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 2, 1}, DCT0, 0x224, 0x0000070F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x228, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 1, 1}, DCT0, 0x22C, 0x0000001F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x230, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x234, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x238, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x23C, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 2, 1}, DCT0, 0x240, 0x000077FF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 1, 1}, DCT0, 0x244, 0x0000000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x248, 0x3F3F1F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x24C, 0x3F3F3F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - - // DCT 1 - {{7, 0, 1}, DCT1, 0x40, 0x7FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x44, 0x7FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x48, 0x7FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x4C, 0x7FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x50, 0x7FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x54, 0x7FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x58, 0x7FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x5C, 0x7FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x60, 0x7FF83FE3, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x64, 0x7FF83FE3, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x68, 0x7FF83FE3, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x6C, 0x7FF83FE3, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x78, 0x00020000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 2, 1}, DCT1, 0x80, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x84, 0x00800003, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x88, 0x3F000000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x8C, 0x00070000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x90, 0x0BFDF102, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0xA8, 0x3F60FFBC, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x200, 0x3F1F1F1F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x204, 0x0F3F0F3F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x208, 0x07070707, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 2, 1}, DCT1, 0x20C, 0x00000F1F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 0), 0xFFC7000F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 1), 0xFFC7000F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 2), 0xFFC7000F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 3), 0xFFC7000F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x214, 0x000F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x218, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x21C, 0x001F1F00, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 2, 1}, DCT1, 0x220, 0x00001F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 2, 1}, DCT1, 0x224, 0x0000070F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x228, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 1, 1}, DCT1, 0x22C, 0x0000001F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x230, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x234, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x238, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x23C, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 2, 1}, DCT1, 0x240, 0x000077FF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 1, 1}, DCT1, 0x244, 0x0000000F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x248, 0x3F3F1F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x24C, 0x3F3F3F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - - // DCT 0 - // Phy Initialization - {{5, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFPllRegWaitTime, 0, DCT0_MASK, ANY_DIMM_MASK}, - // 3. Phy voltage related - {{1, 1, 1}, DCT0, BFDataRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFClkRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFCmpVioLvl, 0x0000C000, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFCmdRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFCsrComparator, 0x0000000C, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFAddrRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, - // DCT 1 - // Phy Initialization - {{5, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFPllRegWaitTime, 0, DCT1_MASK, ANY_DIMM_MASK}, - // 3. Phy voltage related - {{1, 1, 1}, DCT1, BFDataRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFClkRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFCmpVioLvl, 0x0000C000, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFCmdRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFAddrRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, - - // 4. Frequency Change - // Check if a channel needs to be disabled - {{1, 1, 1}, DCT0, BFCKETri, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{6, 3, 1}, DCT0, 0, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFCKETri, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{6, 3, 1}, DCT1, 0, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - - {{3, 3, 1}, DCT0, BFPllLockTime, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{3, 3, 1}, DCT1, BFPllLockTime, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{7, 0, 1}, DCT0, 0x94, 0x0FFFEC1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{7, 0, 1}, DCT1, 0x94, 0x0FFFEC1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, - - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFProcOdtAdv, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFProcOdtAdv, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFSkewMemClk, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFSkewMemClk, 0, DCT1_MASK, ANY_DIMM_MASK}, - - {{9, 0, 1}, DCT0, 0x94, 0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{9, 0, 1}, DCT1, 0x94, 0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFPllLockTime, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFPllLockTime, 0, DCT1_MASK, ANY_DIMM_MASK}, - - // DCT 0 - // 5. Phy Fence - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFDataFence2, 0x00007FFF, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFClkFence2, 0x0000000F, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFCmdFence2, 0x0000000F, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFAddrFence2, 0x0000000F, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777, DCT0_MASK, ANY_DIMM_MASK}, - - // 6. Phy Compensation Init - {{4, 3, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT0, BFDataByteTxPreDriverCal, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad3, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad4, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT0, BFAddrTxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT0, BFClock0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT0, BFClock1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT0, BFClock2TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - // DCT 1 - // 5. Phy Fence - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x7FFF0FFF, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFDataFence2, 0x00007FFF, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFClkFence2, 0x0000000F, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFCmdFence2, 0x0000000F, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFAddrFence2, 0x0000000F, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x70777777, DCT1_MASK, ANY_DIMM_MASK}, - // 6. Phy Compensation Init - {{1, 2, 1}, DCT1, BFDataByteTxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFDataByteTxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT1, BFDataByteTxPreDriverCal, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad3, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad4, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT1, BFAddrTxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT1, BFClock0TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT1, BFClock1TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{8, 2, 1}, DCT1, BFClock2TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, - - {{1, 2, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK} -}; - -CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefOr = { - 0, - (sizeof (S3CPciPreSelfDescriptorOr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), - S3CPciPreSelfDescriptorOr, - PciSpecialCaseFuncOr -}; - -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorOr[] = { - // DCT0 MR0 value and CS Enable map - {{10, 0, 1}, DCT0, 0, 0, DCT0_MASK, ANY_DIMM_MASK}, - // DCT1 MR0 value and CS Enable map - {{10, 0, 1}, DCT1, 0, 0, DCT1_MASK, ANY_DIMM_MASK}, - // DCT0 - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x03FF03FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x03FF03FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x03FF03FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x03FF03FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x03FF03FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x03FF03FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x03FF03FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x03FF03FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0xFFFFFFFF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0xFFFFFFFF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0xFFFFFFFF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0xFFFFFFFF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x3E3E3E3E, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x3E3E3E3E, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3E3E3E3E, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3E3E3E3E, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x3E3E3E3E, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3E3E3E3E, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x3E3E3E3E, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x037F037F, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFPhyClkConfig0, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFPhyClkConfig1, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFPhyClkConfig2, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFPhyClkConfig3, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFPhy0x0D0F0F13, 0x00000083, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFAddrCmdTri, 0x0000000A1, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFReserved00C, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFEnRxPadStandby, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFEccDLLPwrDnConf, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT0, BFTriDM, 0, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFReserved4_0, 0x0000001F, DCT0_MASK, 0x01}, - {{1, 2, 1}, DCT0, BFReserved4_1, 0x00001F00, DCT0_MASK, 0x01}, - {{1, 1, 1}, DCT0, BFReserved4_2, 0x0000001F, DCT0_MASK, 0x01}, - {{1, 2, 1}, DCT0, BFReserved4_3, 0x00001F00, DCT0_MASK, 0x01}, - {{1, 1, 1}, DCT0, BFReserved4_4, 0x0000001F, DCT0_MASK, 0x01}, - {{1, 2, 1}, DCT0, BFReserved4_5, 0x00001F00, DCT0_MASK, 0x01}, - {{1, 1, 1}, DCT0, BFReserved4_6, 0x0000001F, DCT0_MASK, 0x01}, - {{1, 2, 1}, DCT0, BFReserved4_7, 0x00001F00, DCT0_MASK, 0x01}, - {{1, 1, 1}, DCT0, BFReserved4_8, 0x0000001F, DCT0_MASK, 0x01}, - {{1, 2, 1}, DCT0, BFReserved4_9, 0x00001F00, DCT0_MASK, 0x01}, - {{1, 1, 1}, DCT0, BFReserved4_A, 0x0000001F, DCT0_MASK, 0x01}, - {{1, 2, 1}, DCT0, BFReserved4_B, 0x00001F00, DCT0_MASK, 0x01}, - {{1, 1, 1}, DCT0, BFReserved4_C, 0x0000001F, DCT0_MASK, 0x01}, - {{1, 2, 1}, DCT0, BFReserved4_D, 0x00001F00, DCT0_MASK, 0x01}, - {{1, 1, 1}, DCT0, BFReserved4_E, 0x0000001F, DCT0_MASK, 0x01}, - {{1, 2, 1}, DCT0, BFReserved4_F, 0x00001F00, DCT0_MASK, 0x01}, - {{1, 1, 1}, DCT0, BFReserved4_10, 0x0000001F, DCT0_MASK, 0x01}, - {{1, 2, 1}, DCT0, BFReserved4_11, 0x00001F00, DCT0_MASK, 0x01}, - {{1, 1, 1}, DCT0, BFReserved5_0, 0x0000001F, DCT0_MASK, 0x04}, - {{1, 2, 1}, DCT0, BFReserved5_1, 0x00001F00, DCT0_MASK, 0x04}, - {{1, 1, 1}, DCT0, BFReserved5_2, 0x0000001F, DCT0_MASK, 0x04}, - {{1, 2, 1}, DCT0, BFReserved5_3, 0x00001F00, DCT0_MASK, 0x04}, - {{1, 1, 1}, DCT0, BFReserved5_4, 0x0000001F, DCT0_MASK, 0x04}, - {{1, 2, 1}, DCT0, BFReserved5_5, 0x00001F00, DCT0_MASK, 0x04}, - {{1, 1, 1}, DCT0, BFReserved5_6, 0x0000001F, DCT0_MASK, 0x04}, - {{1, 2, 1}, DCT0, BFReserved5_7, 0x00001F00, DCT0_MASK, 0x04}, - {{1, 1, 1}, DCT0, BFReserved5_8, 0x0000001F, DCT0_MASK, 0x04}, - {{1, 2, 1}, DCT0, BFReserved5_9, 0x00001F00, DCT0_MASK, 0x04}, - {{1, 1, 1}, DCT0, BFReserved5_A, 0x0000001F, DCT0_MASK, 0x04}, - {{1, 2, 1}, DCT0, BFReserved5_B, 0x00001F00, DCT0_MASK, 0x04}, - {{1, 1, 1}, DCT0, BFReserved5_C, 0x0000001F, DCT0_MASK, 0x04}, - {{1, 2, 1}, DCT0, BFReserved5_D, 0x00001F00, DCT0_MASK, 0x04}, - {{1, 1, 1}, DCT0, BFReserved5_E, 0x0000001F, DCT0_MASK, 0x04}, - {{1, 2, 1}, DCT0, BFReserved5_F, 0x00001F00, DCT0_MASK, 0x04}, - {{1, 1, 1}, DCT0, BFReserved5_10, 0x0000001F, DCT0_MASK, 0x04}, - {{1, 2, 1}, DCT0, BFReserved5_11, 0x00001F00, DCT0_MASK, 0x04}, - {{1, 1, 1}, DCT0, BFReserved6_0, 0x0000001F, DCT0_MASK, 0x10}, - {{1, 2, 1}, DCT0, BFReserved6_1, 0x00001F00, DCT0_MASK, 0x10}, - {{1, 1, 1}, DCT0, BFReserved6_2, 0x0000001F, DCT0_MASK, 0x10}, - {{1, 2, 1}, DCT0, BFReserved6_3, 0x00001F00, DCT0_MASK, 0x10}, - {{1, 1, 1}, DCT0, BFReserved6_4, 0x0000001F, DCT0_MASK, 0x10}, - {{1, 2, 1}, DCT0, BFReserved6_5, 0x00001F00, DCT0_MASK, 0x10}, - {{1, 1, 1}, DCT0, BFReserved6_6, 0x0000001F, DCT0_MASK, 0x10}, - {{1, 2, 1}, DCT0, BFReserved6_7, 0x00001F00, DCT0_MASK, 0x10}, - {{1, 1, 1}, DCT0, BFReserved6_8, 0x0000001F, DCT0_MASK, 0x10}, - {{1, 2, 1}, DCT0, BFReserved6_9, 0x00001F00, DCT0_MASK, 0x10}, - {{1, 1, 1}, DCT0, BFReserved6_A, 0x0000001F, DCT0_MASK, 0x10}, - {{1, 2, 1}, DCT0, BFReserved6_B, 0x00001F00, DCT0_MASK, 0x10}, - {{1, 1, 1}, DCT0, BFReserved6_C, 0x0000001F, DCT0_MASK, 0x10}, - {{1, 2, 1}, DCT0, BFReserved6_D, 0x00001F00, DCT0_MASK, 0x10}, - {{1, 1, 1}, DCT0, BFReserved6_E, 0x0000001F, DCT0_MASK, 0x10}, - {{1, 2, 1}, DCT0, BFReserved6_F, 0x00001F00, DCT0_MASK, 0x10}, - {{1, 1, 1}, DCT0, BFReserved6_10, 0x0000001F, DCT0_MASK, 0x10}, - {{1, 2, 1}, DCT0, BFReserved6_11, 0x00001F00, DCT0_MASK, 0x10}, - {{1, 1, 1}, DCT0, BFReserved7_0, 0x0000001F, DCT0_MASK, 0x40}, - {{1, 2, 1}, DCT0, BFReserved7_1, 0x00001F00, DCT0_MASK, 0x40}, - {{1, 1, 1}, DCT0, BFReserved7_2, 0x0000001F, DCT0_MASK, 0x40}, - {{1, 2, 1}, DCT0, BFReserved7_3, 0x00001F00, DCT0_MASK, 0x40}, - {{1, 1, 1}, DCT0, BFReserved7_4, 0x0000001F, DCT0_MASK, 0x40}, - {{1, 2, 1}, DCT0, BFReserved7_5, 0x00001F00, DCT0_MASK, 0x40}, - {{1, 1, 1}, DCT0, BFReserved7_6, 0x0000001F, DCT0_MASK, 0x40}, - {{1, 2, 1}, DCT0, BFReserved7_7, 0x00001F00, DCT0_MASK, 0x40}, - {{1, 1, 1}, DCT0, BFReserved7_8, 0x0000001F, DCT0_MASK, 0x40}, - {{1, 2, 1}, DCT0, BFReserved7_9, 0x00001F00, DCT0_MASK, 0x40}, - {{1, 1, 1}, DCT0, BFReserved7_A, 0x0000001F, DCT0_MASK, 0x40}, - {{1, 1, 1}, DCT0, BFReserved7_B, 0x00001F00, DCT0_MASK, 0x40}, - {{1, 2, 1}, DCT0, BFReserved7_C, 0x0000001F, DCT0_MASK, 0x40}, - {{1, 1, 1}, DCT0, BFReserved7_D, 0x00001F00, DCT0_MASK, 0x40}, - {{1, 2, 1}, DCT0, BFReserved7_E, 0x0000001F, DCT0_MASK, 0x40}, - {{1, 1, 1}, DCT0, BFReserved7_F, 0x00001F00, DCT0_MASK, 0x40}, - {{1, 2, 1}, DCT0, BFReserved7_10, 0x0000001F, DCT0_MASK, 0x40}, - {{1, 1, 1}, DCT0, BFReserved7_11, 0x00001F00, DCT0_MASK, 0x40}, - {{1, 1, 1}, DCT0, BFReserved8_0, 0x00000003, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT0, BFReserved8_1, 0x0000007C, DCT0_MASK, ANY_DIMM_MASK}, - - // DCT1 - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x03FF03FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x03FF03FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x03FF03FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x03FF03FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x03FF03FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x03FF03FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x03FF03FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x03FF03FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x03FF03FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x03FF03FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x03FF03FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x03FF03FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x03FF03FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x03FF03FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x03FF03FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x03FF03FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x03FF03FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x03FF03FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x03FF03FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x03FF03FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0xFFFFFFFF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0xFFFFFFFF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0xFFFFFFFF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0xFFFFFFFF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0xFFFFFFFF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0xFFFFFFFF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0xFFFFFFFF, DCT1_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0xFFFFFFFF, DCT1_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0xFFFFFFFF, DCT1_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0xFFFFFFFF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0xFFFFFFFF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0xFFFFFFFF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3E3E3E3E, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3E3E3E3E, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x3E3E3E3E, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3E3E3E3E, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3E3E3E3E, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x3E3E3E3E, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3E3E3E3E, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3E3E3E3E, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x3E3E3E3E, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3E3E3E3E, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3E3E3E3E, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x3E3E3E3E, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x037F037F, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFPhyClkConfig0, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFPhyClkConfig1, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFPhyClkConfig2, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFPhyClkConfig3, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFPhy0x0D0F0F13, 0x00000083, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFAddrCmdTri, 0x0000000A1, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFReserved00C, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFEnRxPadStandby, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFEccDLLPwrDnConf, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 2, 1}, DCT1, BFTriDM, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFDisDllShutdownSR, 0, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFReserved4_0, 0x0000001F, DCT1_MASK, 0x02}, - {{1, 2, 1}, DCT1, BFReserved4_1, 0x00001F00, DCT1_MASK, 0x02}, - {{1, 1, 1}, DCT1, BFReserved4_2, 0x0000001F, DCT1_MASK, 0x02}, - {{1, 2, 1}, DCT1, BFReserved4_3, 0x00001F00, DCT1_MASK, 0x02}, - {{1, 1, 1}, DCT1, BFReserved4_4, 0x0000001F, DCT1_MASK, 0x02}, - {{1, 2, 1}, DCT1, BFReserved4_5, 0x00001F00, DCT1_MASK, 0x02}, - {{1, 1, 1}, DCT1, BFReserved4_6, 0x0000001F, DCT1_MASK, 0x02}, - {{1, 2, 1}, DCT1, BFReserved4_7, 0x00001F00, DCT1_MASK, 0x02}, - {{1, 1, 1}, DCT1, BFReserved4_8, 0x0000001F, DCT1_MASK, 0x02}, - {{1, 2, 1}, DCT1, BFReserved4_9, 0x00001F00, DCT1_MASK, 0x02}, - {{1, 1, 1}, DCT1, BFReserved4_A, 0x0000001F, DCT1_MASK, 0x02}, - {{1, 2, 1}, DCT1, BFReserved4_B, 0x00001F00, DCT1_MASK, 0x02}, - {{1, 1, 1}, DCT1, BFReserved4_C, 0x0000001F, DCT1_MASK, 0x02}, - {{1, 2, 1}, DCT1, BFReserved4_D, 0x00001F00, DCT1_MASK, 0x02}, - {{1, 1, 1}, DCT1, BFReserved4_E, 0x0000001F, DCT1_MASK, 0x02}, - {{1, 2, 1}, DCT1, BFReserved4_F, 0x00001F00, DCT1_MASK, 0x02}, - {{1, 1, 1}, DCT1, BFReserved4_10, 0x0000001F, DCT1_MASK, 0x02}, - {{1, 2, 1}, DCT1, BFReserved4_11, 0x00001F00, DCT1_MASK, 0x02}, - {{1, 1, 1}, DCT1, BFReserved5_0, 0x0000001F, DCT1_MASK, 0x08}, - {{1, 2, 1}, DCT1, BFReserved5_1, 0x00001F00, DCT1_MASK, 0x08}, - {{1, 1, 1}, DCT1, BFReserved5_2, 0x0000001F, DCT1_MASK, 0x08}, - {{1, 2, 1}, DCT1, BFReserved5_3, 0x00001F00, DCT1_MASK, 0x08}, - {{1, 1, 1}, DCT1, BFReserved5_4, 0x0000001F, DCT1_MASK, 0x08}, - {{1, 2, 1}, DCT1, BFReserved5_5, 0x00001F00, DCT1_MASK, 0x08}, - {{1, 1, 1}, DCT1, BFReserved5_6, 0x0000001F, DCT1_MASK, 0x08}, - {{1, 2, 1}, DCT1, BFReserved5_7, 0x00001F00, DCT1_MASK, 0x08}, - {{1, 1, 1}, DCT1, BFReserved5_8, 0x0000001F, DCT1_MASK, 0x08}, - {{1, 2, 1}, DCT1, BFReserved5_9, 0x00001F00, DCT1_MASK, 0x08}, - {{1, 1, 1}, DCT1, BFReserved5_A, 0x0000001F, DCT1_MASK, 0x08}, - {{1, 2, 1}, DCT1, BFReserved5_B, 0x00001F00, DCT1_MASK, 0x08}, - {{1, 1, 1}, DCT1, BFReserved5_C, 0x0000001F, DCT1_MASK, 0x08}, - {{1, 2, 1}, DCT1, BFReserved5_D, 0x00001F00, DCT1_MASK, 0x08}, - {{1, 1, 1}, DCT1, BFReserved5_E, 0x0000001F, DCT1_MASK, 0x08}, - {{1, 2, 1}, DCT1, BFReserved5_F, 0x00001F00, DCT1_MASK, 0x08}, - {{1, 1, 1}, DCT1, BFReserved5_10, 0x0000001F, DCT1_MASK, 0x08}, - {{1, 2, 1}, DCT1, BFReserved5_11, 0x00001F00, DCT1_MASK, 0x08}, - {{1, 1, 1}, DCT1, BFReserved6_0, 0x0000001F, DCT1_MASK, 0x20}, - {{1, 2, 1}, DCT1, BFReserved6_1, 0x00001F00, DCT1_MASK, 0x20}, - {{1, 1, 1}, DCT1, BFReserved6_2, 0x0000001F, DCT1_MASK, 0x20}, - {{1, 2, 1}, DCT1, BFReserved6_3, 0x00001F00, DCT1_MASK, 0x20}, - {{1, 1, 1}, DCT1, BFReserved6_4, 0x0000001F, DCT1_MASK, 0x20}, - {{1, 2, 1}, DCT1, BFReserved6_5, 0x00001F00, DCT1_MASK, 0x20}, - {{1, 1, 1}, DCT1, BFReserved6_6, 0x0000001F, DCT1_MASK, 0x20}, - {{1, 2, 1}, DCT1, BFReserved6_7, 0x00001F00, DCT1_MASK, 0x20}, - {{1, 1, 1}, DCT1, BFReserved6_8, 0x0000001F, DCT1_MASK, 0x20}, - {{1, 2, 1}, DCT1, BFReserved6_9, 0x00001F00, DCT1_MASK, 0x20}, - {{1, 1, 1}, DCT1, BFReserved6_A, 0x0000001F, DCT1_MASK, 0x20}, - {{1, 2, 1}, DCT1, BFReserved6_B, 0x00001F00, DCT1_MASK, 0x20}, - {{1, 1, 1}, DCT1, BFReserved6_C, 0x0000001F, DCT1_MASK, 0x20}, - {{1, 2, 1}, DCT1, BFReserved6_D, 0x00001F00, DCT1_MASK, 0x20}, - {{1, 1, 1}, DCT1, BFReserved6_E, 0x0000001F, DCT1_MASK, 0x20}, - {{1, 2, 1}, DCT1, BFReserved6_F, 0x00001F00, DCT1_MASK, 0x20}, - {{1, 1, 1}, DCT1, BFReserved6_10, 0x0000001F, DCT1_MASK, 0x20}, - {{1, 2, 1}, DCT1, BFReserved6_11, 0x00001F00, DCT1_MASK, 0x20}, - {{1, 1, 1}, DCT1, BFReserved7_0, 0x0000001F, DCT1_MASK, 0x80}, - {{1, 2, 1}, DCT1, BFReserved7_1, 0x00001F00, DCT1_MASK, 0x80}, - {{1, 1, 1}, DCT1, BFReserved7_2, 0x0000001F, DCT1_MASK, 0x80}, - {{1, 2, 1}, DCT1, BFReserved7_3, 0x00001F00, DCT1_MASK, 0x80}, - {{1, 1, 1}, DCT1, BFReserved7_4, 0x0000001F, DCT1_MASK, 0x80}, - {{1, 2, 1}, DCT1, BFReserved7_5, 0x00001F00, DCT1_MASK, 0x80}, - {{1, 1, 1}, DCT1, BFReserved7_6, 0x0000001F, DCT1_MASK, 0x80}, - {{1, 2, 1}, DCT1, BFReserved7_7, 0x00001F00, DCT1_MASK, 0x80}, - {{1, 1, 1}, DCT1, BFReserved7_8, 0x0000001F, DCT1_MASK, 0x80}, - {{1, 2, 1}, DCT1, BFReserved7_9, 0x00001F00, DCT1_MASK, 0x80}, - {{1, 1, 1}, DCT1, BFReserved7_A, 0x0000001F, DCT1_MASK, 0x80}, - {{1, 1, 1}, DCT1, BFReserved7_B, 0x00001F00, DCT1_MASK, 0x80}, - {{1, 2, 1}, DCT1, BFReserved7_C, 0x0000001F, DCT1_MASK, 0x80}, - {{1, 1, 1}, DCT1, BFReserved7_D, 0x00001F00, DCT1_MASK, 0x80}, - {{1, 2, 1}, DCT1, BFReserved7_E, 0x0000001F, DCT1_MASK, 0x80}, - {{1, 1, 1}, DCT1, BFReserved7_F, 0x00001F00, DCT1_MASK, 0x80}, - {{1, 2, 1}, DCT1, BFReserved7_10, 0x0000001F, DCT1_MASK, 0x80}, - {{1, 1, 1}, DCT1, BFReserved7_11, 0x00001F00, DCT1_MASK, 0x80}, - {{1, 1, 1}, DCT1, BFReserved8_0, 0x00000003, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 1, 1}, DCT1, BFReserved8_1, 0x0000007C, DCT1_MASK, ANY_DIMM_MASK}, - - {{0, 0, 0}, FUNC_2, 0x1B4, 0x08000000, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x180, 0x02000000, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x58, 0x1F00001F, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x5C, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x80, 0xE7E7E7E7, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x84, 0xE7E7E7E7, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x1B8, 0x00000010, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x44, 0x00400004, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_4, 0x128, 0x0003F000, ANY_DIMM_MASK, ANY_DIMM_MASK}, - // Release NB P-state force - {{0, 2, 0}, FUNC_5, 0x170, 0x00006EDB, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x118, 0x00040000, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK}, -}; - -CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefOr = { - 0, - (sizeof (S3CPciPostSelfDescriptorOr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), - S3CPciPostSelfDescriptorOr, - PciSpecialCaseFuncOr -}; - -MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorOr[] = { - {{0, 0, 0}, 0xC0010010, 0x00000000007F0000}, - {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, - {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, - {{0, 0, 0}, 0xC001001F, 0x0044601080000600} -}; - -CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefOr = { - 0, - (sizeof (S3MSRPreSelfRefDescriptorOr) / sizeof (MSR_REG_DESCRIPTOR)), - S3MSRPreSelfRefDescriptorOr, - NULL -}; - -VOID *MemS3RegListOr[] = { - (VOID *)&S3PciPreSelfRefOr, - NULL, - (VOID *)&S3CPciPreSelfRefOr, - (VOID *)&S3CPciPostSelfRefOr, - (VOID *)&S3MSRPreSelfRefOr, - NULL, - NULL, - NULL -}; - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for S3 resume - * - * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. - * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. - * @param[in] NodeID - Node ID of the target node. - * - * @return BOOLEAN - * TRUE - This is the correct constructor for the targeted node. - * FALSE - This isn't the correct constructor for the targeted node. - */ -BOOLEAN -MemS3ResumeConstructNBBlockOr ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - UINT32 PackageType; - INT32 i; - MEM_NB_BLOCK *NBPtr; - - NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; - - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedOr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->MemPtr = MemPtr; - NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; - MemNInitNBRegTableOr (NBPtr, NBPtr->NBRegTable); - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Dct = 0; - NBPtr->Channel = 0; - NBPtr->Ganged = FALSE; - NBPtr->NodeCount = MAX_NODES_SUPPORTED_OR; - NBPtr->DctCount = MAX_DCTS_PER_NODE_OR; - - for (i = 0; i < EnumSize; i++) { - NBPtr->IsSupported[i] = FALSE; - } - - for (i = 0; i < NumberOfHooks; i++) { - NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; - } - - LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); - - NBPtr->SwitchDCT = MemNSwitchDCTNb; - NBPtr->SwitchChannel = MemNSwitchChannelNb; - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldOr; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->SetBitField = MemNSetBitFieldNb; - NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedOr; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = (VOID (*) (MEM_NB_BLOCK *, AMD_CONFIG_PARAMS *)) memDefRet; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskUnb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeUNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrOr; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstOr; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = 0; - NBPtr->FamilySpecificHook[DCTSelectSwitch] = MemNS3DctCfgSelectUnb; - - // AM3r2 does not support Dll shutdown - PackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader)); - if (PackageType != PACKAGE_TYPE_AM3r2) { - NBPtr->IsSupported[SetDllShutDown] = TRUE; - } - - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the register list for each device for OR - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP - * @return UINT16 - size of the device descriptor on the target node. - */ -UINT16 -STATIC -MemNS3GetRegLstPtrOr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ) -{ - UINT8 i; - UINT16 Size; - Size = 0; - for (i = PRESELFREF; i <= POSTSELFREF; i ++) { - DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); - DescriptPtr->PCIDevice[i].Node = NBPtr->Node; - DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; - if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListOr[PCI_LST_ESR_OR - PCI_LST_ESR_OR + i] != NULL) { - DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_OR + i; - Size += sizeof (PCI_DEVICE_DESCRIPTOR); - } - DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); - DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; - DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; - if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListOr[CPCI_LST_ESR_OR - PCI_LST_ESR_OR + i] != NULL) { - DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_OR + i; - Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); - } - DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); - DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; - if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListOr[MSR_LST_ESR_OR - PCI_LST_ESR_OR + i] != NULL) { - DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_OR + i; - Size += sizeof (MSR_DEVICE_DESCRIPTOR); - } - DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); - DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; - if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListOr[CMSR_LST_ESR_OR - PCI_LST_ESR_OR + i] != NULL) { - DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_OR + i; - Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); - } - } - return Size; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function return the register list according to the register ID. - * - * @param[in] RegisterLstID - value of the Register list ID. - * @param[out] **RegisterHeader - pointer to the address of the register list. - * @return none - */ -AGESA_STATUS -STATIC -MemNS3GetDeviceRegLstOr ( - IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader - ) -{ - if (RegisterLstID >= (sizeof (MemS3RegListOr) / sizeof (VOID *))) { - ASSERT(FALSE); // RegisterListID exceeded size of Register list - return AGESA_FATAL; - } - if (MemS3RegListOr[RegisterLstID] != NULL) { - *RegisterHeader = MemS3RegListOr[RegisterLstID]; - return AGESA_SUCCESS; - } - ASSERT(FALSE); // Device register list error - return AGESA_FATAL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function that set PllLockTime to default state. - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -STATIC -MemNS3SetDfltPllLockTimeOr ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT16 RegValue; - - RegValue = 0x190; - MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets bit 31 [DynModeChange] of F2x9C_xB - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetDynModeChangeOr ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT8 Dct; - UINT32 RegValue; - UINT32 Temp; - UINT32 TempValue; - - IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { - Temp = Address.Address.Register; - Dct = ((Temp & 0x400) == 0) ? 0 : 1; - - // Switch Dct - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - TempValue = Dct; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); - - Address.Address.Function = FUNC_2; - Address.Address.Register = Temp; - RegValue = 0x80000000; - MemNS3SetCSRNb (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function saves the heap data of MR0 and chipsel enable map before S3 - * entry - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SaveMR0Or ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - LOCATE_HEAP_PTR LocateHeapStructPtr; - MR0_DATA_ARRAY_PTR pMR0Data; - UINT32 Node; - UINT32 Dct; - - Node = Address.Address.Device - 0x18; - Dct = Address.Address.Function; - - // Get original MR0 from heap - LocateHeapStructPtr.BufferHandle = AMD_MEM_S3_MR0_DATA_HANDLE; - LocateHeapStructPtr.BufferPtr = NULL; - Status = HeapLocateBuffer (&LocateHeapStructPtr, ConfigPtr); - ASSERT (Status == AGESA_SUCCESS); - pMR0Data = (MR0_DATA_ARRAY_PTR) (LocateHeapStructPtr.BufferPtr); - ASSERT (pMR0Data != NULL); - - IDS_HDT_CONSOLE (MEM_FLOW, "\tSave MR0 for S3 resume\n\t\tNode: %d, Dct: %d, ChipSelEnMap: %04X, MR0: %04X\n", Node, Dct, (*pMR0Data)[Node][Dct].ChipSelEnMap, (*pMR0Data)[Node][Dct].MR0Value); - *(UINT32*) Value = (*pMR0Data)[Node][Dct].MR0Value; - *(UINT32*) Value <<= 16; - *(UINT32*) Value |= (*pMR0Data)[Node][Dct].ChipSelEnMap; -} - -/** - * - * - * This function send an MRS command to set MR0[PPD] after exit self-refresh - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3RestoreMR0SetPPDOr ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 Node; - UINT32 Dct; - UINT16 ChipSelEnMap; - UINT16 MR0Value; - UINT32 TempValue; - UINT32 PowerDownMode; - UINT32 PchgPDModeSel; - UINT8 ChipSel; - - Node = Address.Address.Device - 0x18; - Dct = Address.Address.Function; - ChipSelEnMap = (UINT16) ((*(UINT32*) Value) & 0xFFFF); - MR0Value = (UINT16) (((*(UINT32*) Value) >> 16) & 0xFFFF); - - Address.Address.Register = BFPowerDownMode; - MemNS3GetBitFieldNb (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); - PowerDownMode = TempValue; - - Address.Address.Register = BFPchgPDModeSel; - MemNS3GetBitFieldNb (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); - PchgPDModeSel = TempValue; - - // Check if Fast exit pre-charge powerdown mode is desired - // D18F2x84[PowerDownMode] = 0 - // D18F2x94[PchgPDModeSel] = 0 - // MR0[PPD] = 1 - if (PowerDownMode == 0 && PchgPDModeSel == 0 && (MR0Value & 0x1000) == 0x1000) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if (((ChipSelEnMap >> ChipSel) & 1) != 0) { - // if chip select present - Address.Address.Register = BFMrsChipSel; - MemNS3SetBitFieldNb (AccessS3SaveWidth32, Address, &ChipSel, ConfigPtr); - // BA2=0,BA1=0,BA0=0 - TempValue = 0; - Address.Address.Register = BFMrsBank; - MemNS3SetBitFieldNb (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); - Address.Address.Register = BFMrsAddress; - MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &MR0Value, ConfigPtr); - // Bit swapping is not needed here because hardware bit swapping does not occur for commands - // sent via D18F2x7C_dct[1:0][SendMrsCmd] when D18F2x7C_dct[1:0][EndDramInit] = 0 - TempValue = 1; - Address.Address.Register = BFSendMrsCmd; - MemNS3SetBitFieldNb (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\tIssue MRS Command after ESR\n\t\tNode: %d, Dct: %d, CS: %d, MR0: %08X\n", Node, Dct, ChipSel, MR0Value); - Address.Address.Register = BFSendMrsCmd; - MemNS3GetBitFieldNb (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); - while (TempValue != 0) { - MemNS3GetBitFieldNb (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); - } - WaitMicroseconds (500, ConfigPtr); - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function read the value of CSR register. - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -STATIC -MemNS3GetCSROr ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 ExtendOffset; - UINT32 ValueRead; - UINT32 TempFunc; - UINT32 TempValue; - - ValueRead = 0; - ExtendOffset = Address.Address.Register; - TempFunc = Address.Address.Function; - - // Switch Dct - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - TempValue = 0; - if (ExtendOffset & 0x400) { - TempValue = 1; - } - LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); - Address.Address.Function = TempFunc; - - Address.Address.Register = 0x98; - ExtendOffset &= 0x3FF; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); - while (((ValueRead >> 31) & 1) == 0) { - LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr); - } - Address.Address.Register = 0x9C; - LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function write to a CSR register - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -STATIC -MemNS3SetCSROr ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 ExtendOffset; - UINT32 ValueRead; - UINT32 ValueWrite; - UINT32 TempFunc; - UINT32 TempValue; - - ValueRead = 0; - ExtendOffset = Address.Address.Register; - TempFunc = Address.Address.Function; - // Switch Dct - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - TempValue = 0; - if (ExtendOffset & 0x400) { - TempValue = 1; - } - LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); - - Address.Address.Function = TempFunc; - Address.Address.Register = 0x9C; - - ExtendOffset &= 0x3FF; - ExtendOffset |= 0x40000000; - switch (AccessWidth) { - case AccessS3SaveWidth8: - ValueWrite = *(UINT8 *) Value; - break; - case AccessS3SaveWidth16: - ValueWrite = *(UINT16 *) Value; - break; - case AccessS3SaveWidth32: - ValueWrite = *(UINT32 *) Value; - break; - default: - ASSERT (FALSE); - } - LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr); - Address.Address.Register = 0x98; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); - while (((ValueRead >> 31) & 1) == 0) { - LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mn.c deleted file mode 100644 index dafff2d546..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mn.c +++ /dev/null @@ -1,530 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mn.c - * - * Common Northbridge functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_MN_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemNDefaultFamilyHookNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[]; - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes member functions and variables of NB block. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitNBDataNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - INT32 i; - UINT8 *BytePtr; - - NBPtr->DctCachePtr = NBPtr->DctCache; - NBPtr->PsPtr = NBPtr->PSBlock; - - BytePtr = (UINT8 *) (NBPtr->DctCache); - for (i = 0; i < sizeof (NBPtr->DctCache); i++) { - *BytePtr++ = 0; - } - - for (i = 0; i < EnumSize; i++) { - NBPtr->IsSupported[i] = FALSE; - } - - for (i = 0; i < NumberOfHooks; i++) { - NBPtr->FamilySpecificHook[i] = MemNDefaultFamilyHookNb; - } - - for (i = 0; i < NBPtr->DctCount; i++) { - NBPtr->PSBlock[i].MemPGetPass1Seeds = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue; - } - - NBPtr->SwitchDCT = MemNSwitchDCTNb; - NBPtr->SwitchChannel = MemNSwitchChannelNb; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->SetBitField = MemNSetBitFieldNb; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Get System address of Chipselect RJ 16 bits (Addr[47:16]) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Receiver - Chipselect to be targeted [0-7] - * @param[out] AddrPtr - Pointer to System Address [47:16] - * - * @return TRUE - Address is valid - * @return FALSE - Address is not valid - */ - -BOOLEAN -MemNGetMCTSysAddrNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Receiver, - OUT UINT32 *AddrPtr - ) -{ - S_UINT64 SMsr; - UINT32 CSBase; - UINT32 HoleBase; - UINT32 DctSelBaseAddr; - UINT32 BottomUma; - DIE_STRUCT *MCTPtr; - MEM_DATA_STRUCT *MemPtr; - - MCTPtr = NBPtr->MCTPtr; - MemPtr = NBPtr->MemPtr; - - ASSERT (Receiver < 8); - - CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver); - if (CSBase & 1) { - ASSERT ((CSBase & 0xE0) == 0); // Should not enable CS interleaving before DQS training. - - // Scale base address from [39:8] to [47:16] - CSBase >>= 8; - - HoleBase = MCTPtr->NodeHoleBase ? MCTPtr->NodeHoleBase : 0x7FFFFFFF; - - if ((MemNGetBitFieldNb (NBPtr, BFDctSelHiRngEn) == 1) && (NBPtr->Dct == MemNGetBitFieldNb (NBPtr, BFDctSelHi))) { - DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr) << (27 - 16); - if (DctSelBaseAddr > HoleBase) { - DctSelBaseAddr -= _4GB_RJ16 - HoleBase; - } - CSBase += DctSelBaseAddr; - } else { - CSBase += MCTPtr->NodeSysBase; - } - - if (CSBase >= HoleBase) { - CSBase += _4GB_RJ16 - HoleBase; - } - - CSBase += (UINT32)1 << (21 - 16); // Add 2MB offset to avoid compat area. - if ((CSBase >= (MCT_TRNG_KEEPOUT_START >> 8)) && (CSBase <= (MCT_TRNG_KEEPOUT_END >> 8))) { - CSBase += (((MCT_TRNG_KEEPOUT_END >> 8) - CSBase) + 0x0F) & 0xFFFFFFF0; - } - - if (MCTPtr->Status[SbHWHole]) { - if (MCTPtr->Status[SbSWNodeHole]) { - LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - if ((CSBase >= (SMsr.lo >> 16)) && (CSBase < _4GB_RJ16)) { - return FALSE; - } - } - } - - BottomUma = NBPtr->RefPtr->Sub4GCacheTop >> 16; - if (BottomUma && (CSBase >= BottomUma) && (CSBase < _4GB_RJ16)) { - return FALSE; - } - *AddrPtr = CSBase; - return TRUE; - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines if a Rank is enabled. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Receiver - Receiver to check - * @return - FALSE - * - */ - -BOOLEAN -MemNRankEnabledNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Receiver - ) -{ - UINT32 CSBase; - CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver); - if (CSBase & 1) { - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the EccSymbolSize bit depending upon configurations - * and system override. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSetEccSymbolSizeNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 X4DimmsOnly; - BOOLEAN Size; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - - ASSERT (NBPtr != NULL); - - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - - // Determine if this node has only x4 DRAM parts - X4DimmsOnly = (UINT16) ((!(DCTPtr->Timings.Dimmx8Present | DCTPtr->Timings.Dimmx16Present)) && DCTPtr->Timings.Dimmx4Present); - // - // Check if EccSymbolSize BKDG value is overridden - // - if (UserOptions.CfgEccSymbolSize != ECCSYMBOLSIZE_USE_BKDG) { - Size = (UserOptions.CfgEccSymbolSize == ECCSYMBOLSIZE_FORCE_X4) ? FALSE : TRUE; - } else { - if (X4DimmsOnly && MCTPtr->GangedMode) { - Size = FALSE; - } else { - Size = TRUE; - } - } - IDS_OPTION_HOOK (IDS_ECCSYMBOLSIZE, &Size, &(NBPtr->MemPtr->StdHeader)); - MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the training control flow - * The DDR3 mode bit must be set prior to calling this function - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - */ -BOOLEAN -MemNTrainingFlowNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { - memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr); - } else { - memNTrainFlowControl[DDR2_TRAIN_FLOW] (NBPtr); - } - return TRUE; -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function flushes the training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNFlushPatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - // Due to speculative execution during MemUReadCachelines, we must - // flush one more cache line than we read. - MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function compares test pattern with data in buffer and - * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] ByteCount - Byte count - * - * @return PASS - Bitmap of results of comparison - */ - -UINT16 -MemNCompareTestPatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - UINT16 i; - UINT16 Pass; - UINT8 ColumnCount; - UINT8 FailingBitMask[8]; - - ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64)); - - ColumnCount = NBPtr->ChannelPtr->ColumnCount; - Pass = 0xFFFF; - // - // Clear Failing Bit Mask - // - for (i = 0; i < sizeof (FailingBitMask); i++) { - FailingBitMask[i] = 0; - } - - if (NBPtr->Ganged && (NBPtr->Dct != 0)) { - i = 8; // DCT 1 in ganged mode - } else { - i = 0; - } - - for (; i < ByteCount; i++) { - if (Buffer[i] != Pattern[i]) { - // if bytelane n fails - Pass &= ~((UINT16)1 << (i % 8)); // clear bit n - FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i]); - } - - if (NBPtr->Ganged && ((i & 7) == 7)) { - i += 8; // if ganged, skip over other Channel's Data - } - } - // - // Accumulate Failing bit data - // - for (i = 0; i < sizeof (FailingBitMask); i++) { - NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &= - FailingBitMask[i]; - } - - return Pass; -} - -/*----------------------------------------------------------------------------- - * - * - * This function compares test pattern with data in buffer and - * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] ByteCount - Byte count - * - * @retval PASS - Bitmap of results of comparison - * ---------------------------------------------------------------------------- - */ -UINT16 -MemNInsDlyCompareTestPatternNb ( - IN MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - UINT16 i; - UINT16 Pass; - UINT16 BeatOffset; - UINT16 BeatCnt; - UINT8 ColumnCount; - UINT8 FailingBitMask[8]; - - ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64)); - - ColumnCount = NBPtr->ChannelPtr->ColumnCount; - Pass = 0xFFFF; - // - // Clear Failing Bit Mask - // - for (i = 0; i < sizeof (FailingBitMask); i++) { - FailingBitMask[i] = 0; - } - - if (NBPtr->Ganged && (NBPtr->Dct != 0)) { - i = 8; // DCT 1 in ganged mode - } else { - i = 0; - } - - if (NBPtr->Ganged) { - BeatOffset = 16; - } else { - BeatOffset = 8; - } - - BeatCnt = 0; - for (; i < ByteCount; i++) { - - if (Buffer[i] != Pattern[i + BeatOffset]) { - // if bytelane n fails - Pass &= ~((UINT16)1 << (i % 8)); // clear bit n - FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i + BeatOffset]); - } - - if ((i & 7) == 7) { - if (NBPtr->Ganged) { - i += 8; // if ganged, skip over other Channel's Data - } - BeatCnt++; - } - - if ((BeatCnt & 3) == 3) { - // Skip last data beat of a 4-beat burst. - BeatCnt++; - i = i + BeatOffset; - } - } - // - // Accumulate Failing bit data - // - for (i = 0; i < sizeof (FailingBitMask); i++) { - NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &= - FailingBitMask[i]; - } - - return Pass; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the training control flow for UNB - * The DDR3 mode bit must be set prior to calling this function - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - */ -BOOLEAN -MemNTrainingFlowUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr); - return TRUE; -} -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * - * - * This function is an empty function used to intialize FamilySpecificHook array - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - always - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemNDefaultFamilyHookNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnS3.c deleted file mode 100644 index aa1b6f52a8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnS3.c +++ /dev/null @@ -1,1356 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnS3.c - * - * Common Northbridge S3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 51373 $ @e \$Date: 2011-04-21 13:10:59 -0600 (Thu, 21 Apr 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "cpuFamilyTranslation.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_NB_MNS3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -MemNS3GetSetBitField ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN BOOLEAN IsSet, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -BOOLEAN -STATIC -MemNS3GetDummyReadAddr ( - IN OUT MEM_NB_BLOCK *NBPtr, - OUT UINT64 *TestAddr - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes the S3 resume for a node - * - * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK - * @param[in] NodeID - The Node id of the target die - * - * @return BOOLEAN - * TRUE - This is the correct constructor for the targeted node. - * FALSE - This isn't the correct constructor for the targeted node. - */ - -BOOLEAN -MemNS3ResumeNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ) -{ - UINT8 DCT; - BOOLEAN GangedEn; - UINT64 TestAddr; - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - - NBPtr = S3NBPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - GangedEn = (MemNGetBitFieldNb (NBPtr, BFDctGangEn) == 1) ? TRUE : FALSE; - - // Errata before S3 resume sequence - - // Resume Sequence - // 1. Program F2x[1,0]9C_x08[DisAutoComp]=1 - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); - - // Program F2x[1, 0]94[MemClkFreqVal] = 1. - // 2. Wait for F2x[1,0]94[FreqChgInPrg]=0 - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) { - MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1); - while (MemNGetBitFieldNb (NBPtr, BFFreqChgInProg) != 0) {} - } - } - - // Program F2x9C_x08[DisAutoComp]=0 - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); - // BIOS must wait 750 us for the phy compensation engine - // to reinitialize. - MemFS3Wait10ns (75000, NBPtr->MemPtr); - - // 3. Restore F2x[1,0]90_x00, F2x9C_x0A, and F2x[1,0]9C_x0C - // 4. Restore F2x[1,0]9C_x04 - // Get the register value from the heap. - S3NBPtr->MemS3ExitSelfRefReg (NBPtr, &MemPtr->StdHeader); - - // Add a hook here - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) { - } - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - - // 5. Set F2x[1,0]90[ExitSelfRef] - // 6. Wait for F2x[1,0]90[ExitSelfRef]=0 - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) { - MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1); - while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {} - } - if ((MemNGetBitFieldNb (NBPtr, BFMemClkFreq) == DDR1333_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) { - MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000)); - if (DCT == 0) { - MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000)); - } - // NOTE: wait 512 clocks for DLL-relock - MemFS3Wait10ns (50000, NBPtr->MemPtr); // wait 500us - } - } - - // Errata After S3 resume sequence - // Errata 350 - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) { - if (!((DCT == 1) && GangedEn)) { - if (MemNS3GetDummyReadAddr (NBPtr, &TestAddr)) { - // Do dummy read - Read64Mem8 (TestAddr); - // Flush the cache line - LibAmdCLFlush (TestAddr, 1); - } - } - MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); - MemFS3Wait10ns (60, NBPtr->MemPtr); // Wait 300ns - MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); - MemFS3Wait10ns (400, NBPtr->MemPtr); // Wait 2us - } - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes the S3 resume for a node on a client NB - * - * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK - * @param[in] NodeID - The Node id of the target die - * - * @return BOOLEAN - * TRUE - This is the correct constructor for the targeted node. - * FALSE - This isn't the correct constructor for the targeted node. - */ -BOOLEAN -MemNS3ResumeClientNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ) -{ - UINT8 DCT; - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - - NBPtr = S3NBPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - // Errata before S3 resume sequence - - // Add a hook here - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) { - } - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - - NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); - //Override the NB Pstate if needed - IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, S3NBPtr->NBPtr, &MemPtr->StdHeader); - // Set F2x[1,0]90[ExitSelfRef] - // Wait for F2x[1,0]90[ExitSelfRef]=0 - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) { - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); - MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1); - while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {} - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); - } - } - - // Errata After S3 resume sequence - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes the S3 resume for a node on a UNB - * - * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK - * @param[in] NodeID - The Node id of the target die - * - * @return BOOLEAN - * TRUE - This is the correct constructor for the targeted node. - * FALSE - This isn't the correct constructor for the targeted node. - */ -BOOLEAN -MemNS3ResumeUNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ) -{ - UINT8 DCT; - MEM_NB_BLOCK *NBPtr; - MEM_DATA_STRUCT *MemPtr; - - NBPtr = S3NBPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - // Errata before S3 resume sequence - - // Add a hook here - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) { - } - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); - - //Override the NB Pstate if needed - IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, S3NBPtr->NBPtr, &MemPtr->StdHeader); - // Set F2x[1,0]90[ExitSelfRef] - // Wait for F2x[1,0]90[ExitSelfRef]=0 - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) { - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); - MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1); - while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {} - if (NBPtr->IsSupported[SetDllShutDown]) { - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); - } - } - } - - // Errata After S3 resume sequence - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the conditional PCI device mask - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP - * @return none - */ -VOID -MemNS3GetConPCIMaskNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ) -{ - BIT_FIELD_NAME bitfield; - UINT32 RegVal; - UINT8 DCT; - UINT8 DimmMask; - UINT8 BadDimmMask; - UINT8 DctGangEn; - BOOLEAN IsDDR3; - - IsDDR3 = FALSE; - DimmMask = 0; - BadDimmMask = 0; - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - NBPtr->SwitchDCT (NBPtr, DCT); - if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) { - if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { - IsDDR3 = TRUE; - } - for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) { - RegVal = MemNGetBitFieldNb (NBPtr, bitfield); - if (RegVal & 0x3) { - DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); - } else if (RegVal & 0x4) { - BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); - } - } - } - } - - NBPtr->SwitchDCT (NBPtr, 0); - DctGangEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctGangEn); - // Set channel mask - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0; - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - if (DimmMask & (0x55 << DCT)) { - // Set mask before exit self refresh - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; - // Set mask after exit self refresh - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT; - // Set DDR3 mask if Dimms present are DDR3 - if (IsDDR3) { - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4); - } - } else if (BadDimmMask & (0x55 << DCT)) { - // Need to save function 2 registers for bad dimm - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; - } - } - - // Set dimm mask - DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; - if (DctGangEn) { - // Need to set channel mask bit to 1 on DCT1 in ganged mode as some registers - // need to be restored on both channels in ganged mode - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 2; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 2; - if (IsDDR3) { - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (2 << 4); - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (2 << 4); - } - // Before exit self refresh, do not copy dimm mask to DCT1 as registers restored - // in that time frame don't care about individual dimm population. We want to - // skip registers that are not needed to be restored for DCT1 in ganged mode. - // - // After exit self refresh, training registers will be restored and will only be - // restored for slots which have dimms on it. So dimm mask needs to be copied to DCT1. - // - DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 |= DimmMask << 1; - } - - // Adjust the mask if there is no dimm on the node - if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) && - (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) { - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the conditional PCI device mask - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP - * @return none - */ -VOID -MemNS3GetConPCIMaskUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ) -{ - BIT_FIELD_NAME bitfield; - UINT32 RegVal; - UINT8 DCT; - UINT8 DimmMask; - UINT8 BadDimmMask; - UINT8 NbPsCap; - - DimmMask = 0; - BadDimmMask = 0; - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - MemNSwitchDCTNb (NBPtr, DCT); - if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) { - for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) { - RegVal = MemNGetBitFieldNb (NBPtr, bitfield); - if (RegVal & 0x1) { - DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); - } else if (RegVal & 0x4) { - BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); - } - } - } - } - // Check if the system is capable of doing NB Pstate change - NbPsCap = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateDis); - - MemNSwitchDCTNb (NBPtr, 0); - // Set channel mask - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0; - for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { - if (DimmMask & (0x55 << DCT)) { - // Set mask before exit self refresh - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= ((NbPsCap == 0) ? 5 : 1) << DCT; - // Set mask after exit self refresh - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT; - // Set DDR3 mask if Dimms present are DDR3 - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4); - } else if (BadDimmMask & (0x55 << DCT)) { - // Need to save function 2 registers for bad dimm - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; - } - } - - // Set dimm mask - DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; - - // Adjust the mask if there is no dimm on the node - if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) && - (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) { - DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; - DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function read the value of CSR register. - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3GetCSRNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 ExtendOffset; - UINT32 ValueRead; - UINT8 DataPort; - - ValueRead = 0; - ExtendOffset = Address.Address.Register; - if (ExtendOffset & 0x800) { - Address.Address.Register = 0xF0; - DataPort = 0xF4; - } else { - Address.Address.Register = 0x98; - DataPort = 0x9C; - } - if (ExtendOffset & 0x400) { - Address.Address.Register |= 0x100; - } - ExtendOffset &= 0x3FF; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); - while (((ValueRead >> 31) & 1) == 0) { - LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr); - } - Address.Address.Register = (Address.Address.Register & 0xF00) | DataPort; - LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function write to a CSR register - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetCSRNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 ExtendOffset; - UINT32 ValueRead; - UINT32 ValueWrite; - UINT8 DataOffset; - - ValueRead = 0; - ExtendOffset = Address.Address.Register; - // Check the flag and see the type of the access - if (ExtendOffset & 0x800) { - Address.Address.Register = 0xF4; - DataOffset = 0xF0; - } else { - Address.Address.Register = 0x9C; - DataOffset = 0x98; - } - if (ExtendOffset & 0x400) { - Address.Address.Register |= 0x100; - } - ExtendOffset &= 0x3FF; - ExtendOffset |= 0x40000000; - switch (AccessWidth) { - case AccessS3SaveWidth8: - ValueWrite = *(UINT8 *) Value; - break; - case AccessS3SaveWidth16: - ValueWrite = *(UINT16 *) Value; - break; - case AccessS3SaveWidth32: - ValueWrite = *(UINT32 *) Value; - break; - default: - ASSERT (FALSE); - } - LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr); - Address.Address.Register = (Address.Address.Register & 0xF00) | DataOffset; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); - while (((ValueRead >> 31) & 1) == 0) { - LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function reads register bitfield - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3GetBitFieldNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function writes register bitfield - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetBitFieldNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function restores scrubber base register - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Node - The Node id of the target die - * - */ -VOID -MemNS3RestoreScrubNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Node - ) -{ - UINT32 ScrubAddrRJ16; - - ScrubAddrRJ16 = (MemNGetBitFieldNb (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8; - ScrubAddrRJ16 |= MemNGetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node) << 24; - MemNSetBitFieldNb (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16); - MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function disable NB Pstate Debug. - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3DisNbPsDbgNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 RegValue; - - LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); - // Clear NbPsDbgEn and NbPsCsrAccSel - if ((RegValue & 0xC0000000) != 0) { - RegValue &= 0x3FFFFFFF; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function that enable NB Pstate debug register to allow access to NB Pstate - * 1 registers without actually changing NB Pstate. - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3EnNbPsDbg1Nb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 RegValue; - - LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); - // Set NbPsDbgEn to 1 and NbPsCsrAccSel to 1 - if ((RegValue & 0xC0000000) != 0xC0000000) { - RegValue = (*(UINT32 *)Value & 0x3FFFFFFF) | 0xC0000000; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets bit 31 [DynModeChange] of F2x9C_xB - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetDynModeChangeNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 RegValue; - - RegValue = 0x80000000; - IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { - MemNS3SetCSRNb (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function does the channel disable sequence - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3DisableChannelNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - LOCATE_HEAP_PTR LocateBufferPtr; - S3_MEM_NB_BLOCK *S3NBPtr; - UINT32 RegValue; - UINT8 Die; - - // See which Node should be accessed - Die = (UINT8) (Address.Address.Device - 24); - - LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; - NBPtr = S3NBPtr[Die].NBPtr; - - // Function field contains the DCT number - NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function); - RegValue = MemNGetBitFieldNb (NBPtr, BFCKETri); - // if CKETri is 0b11, this channel is disabled - if (RegValue == 3) { - //Wait for 24 MEMCLKs, which is 60ns under 400MHz - MemFS3Wait10ns (6, NBPtr->MemPtr); - MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); - MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); - MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function disables auto compensation. - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetDisAutoCompUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT16 RegValue; - - MemNS3GetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); - RegValue = 0x6000 | RegValue; - MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function retores Pre Driver Calibration with pre driver calibration code - * code valid bit set. - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetPreDriverCalUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT16 RegValue; - - RegValue = 0x8000 | *(UINT16 *) Value; - MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is used by families that use a separate DctCfgSel bit to - * select the current DCT which will be accessed by function 2. - * NOTE: This function must be called BEFORE the NBPtr->Dct variable is - * updated. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Dct - Pointer to ID of the target DCT - * - */ - -BOOLEAN -MemNS3DctCfgSelectUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *Dct - ) -{ - // Set the DctCfgSel to new DCT - // - MemNSetBitFieldNb (NBPtr, BFDctCfgSel, *(UINT8*)Dct); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function write to a register that has one copy for each NB Pstate - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3GetNBPStateDepRegUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT8 NBPstate; - UINT8 TempValue; - UINT8 Dct; - UINT32 Temp; - - Temp = Address.Address.Register; - NBPstate = (UINT8) (Temp >> 10); - Dct = (UINT8) Address.Address.Function; - Temp &= 0x3FF; - - // Switch Dct - // Function field contains DCT value - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - TempValue = (TempValue & 0xCE) | ((NBPstate << 4) | Dct); - LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - - Address.Address.Function = FUNC_2; - Address.Address.Register = Temp; - LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); - - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - TempValue = 0; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function write to a register that has one copy for each NB Pstate - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetNBPStateDepRegUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT8 NBPstate; - UINT8 TempValue; - UINT8 Dct; - UINT32 Temp; - - Temp = Address.Address.Register; - NBPstate = (UINT8) (Temp >> 10); - Dct = (UINT8) Address.Address.Function; - Temp &= 0x3FF; - - // Switch Dct - // Function field contains DCT value - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - TempValue = (TempValue & 0xCE) | ((NBPstate << 4) | Dct); - LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - - Address.Address.Function = FUNC_2; - Address.Address.Register = Temp; - LibAmdPciWrite (AccessWidth, Address, Value, ConfigPtr); - - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - TempValue = 0; - LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function read the value of Function 2 PCI register. - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the NB register in PCI_ADDR format. - * @param[in] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SaveNBRegiserUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT8 TempValue; - UINT8 Dct; - UINT32 Temp; - - Temp = Address.Address.Register; - Dct = (UINT8) Address.Address.Function; - - // Switch Dct - // Function field contains DCT value - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - TempValue = (TempValue & 0xFE) | Dct; - LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - - Address.Address.Register = Temp; - Address.Address.Function = FUNC_2; - LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function set the value of Function 2 PCI register. - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the NB register in PCI_ADDR format. - * @param[in] *Value - Pointer to the value be write. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3RestoreNBRegiserUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT8 TempValue; - UINT8 Dct; - UINT32 Temp; - - Temp = Address.Address.Register; - Dct = (UINT8) Address.Address.Function; - - // Switch Dct - // Function field contains DCT value - Address.Address.Function = FUNC_1; - Address.Address.Register = 0x10C; - LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - TempValue = (TempValue & 0xFE) | Dct; - LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); - - Address.Address.Register = Temp; - Address.Address.Function = FUNC_2; - LibAmdPciWrite (AccessWidth, Address, Value, ConfigPtr); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function reads and writes register bitfield - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in] IsSet - if this is a register read or write - * @param[in, out] *Value - Pointer to the value be read or written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -STATIC -MemNS3GetSetBitField ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN BOOLEAN IsSet, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - BIT_FIELD_NAME BitField; - MEM_NB_BLOCK *NBPtr; - LOCATE_HEAP_PTR LocateBufferPtr; - S3_MEM_NB_BLOCK *S3NBPtr; - UINT32 RegValue; - UINT8 Die; - - RegValue = 0; - // See which Node should be accessed - Die = (UINT8) (Address.Address.Device - 24); - - LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; - NBPtr = S3NBPtr[Die].NBPtr; - - // Function field contains the DCT number - NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function); - - // Get the bitfield name to be accessed - // Register field contains the bitfield name - BitField = (BIT_FIELD_NAME) Address.Address.Register; - - if (IsSet) { - switch (AccessWidth) { - case AccessS3SaveWidth8: - RegValue = *(UINT8 *) Value; - break; - case AccessS3SaveWidth16: - RegValue = *(UINT16 *) Value; - break; - case AccessS3SaveWidth32: - RegValue = *(UINT32 *) Value; - break; - default: - ASSERT (FALSE); - } - MemNSetBitFieldNb (NBPtr, BitField, RegValue); - } else { - RegValue = MemNGetBitFieldNb (NBPtr, BitField); - - switch (AccessWidth) { - case AccessS3SaveWidth8: - *(UINT8 *) Value = (UINT8) RegValue; - break; - case AccessS3SaveWidth16: - *(UINT16 *) Value = (UINT16) RegValue; - break; - case AccessS3SaveWidth32: - *(UINT32 *) Value = RegValue; - break; - default: - ASSERT (FALSE); - } - } - } else { - ASSERT (FALSE); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the dummy read address for a channel of a node. - * - * @param[in, out] *NBPtr - Pointer to northbridge block - * @param[out] *TestAddr - Pointer to the test address - * - * @retval TRUE - Dummy read address can be found - * @retval FALSE - Dummy read address cannot be found - * - */ -BOOLEAN -STATIC -MemNS3GetDummyReadAddr ( - IN OUT MEM_NB_BLOCK *NBPtr, - OUT UINT64 *TestAddr - ) -{ - BOOLEAN DctSelIntlvEn; - UINT8 DramIntlvEn; - UINT8 DctSelIntlvAddr; - UINT8 IntLvRgnBaseAddr; - UINT8 IntLvRgnLmtAddr; - UINT8 IntLvRgnSize; - UINT32 DctSelBaseAddr; - UINT64 TOM; - BOOLEAN AddrFound; - - AddrFound = TRUE; - // Check if Node interleaving is enabled - DramIntlvEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramIntlvEn); - if (DramIntlvEn != 0) { - // Set the address bits that identify the node - *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramIntlvSel) << 12; - } else { - *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramBaseAddr) << 27; - } - - // Check if channel interleaving is enabled - DctSelIntlvEn = (BOOLEAN) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvEn); - DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr); - if (!DctSelIntlvEn) { - if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) { - *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF); - } - } else { - DctSelIntlvAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvAddr); - // Set the address bits that identify the channel - if ((DctSelIntlvAddr == 0) || (DctSelIntlvAddr == 2)) { - *TestAddr |= (UINT64) NBPtr->Dct << 6; - } else if (DctSelIntlvAddr == 1) { - *TestAddr |= (UINT64) NBPtr->Dct << (12 + LibAmdBitScanReverse (DramIntlvEn + 1)); - } else if (DctSelIntlvAddr == 3) { - *TestAddr |= (UINT64) NBPtr->Dct << 9; - } - } - // Adding 2M to avoid conflict - *TestAddr += 0x200000; - - // If memory hoisting is disabled, the address can fall into MMIO area - // Need to find an address out of MMIO area but belongs to the channel - // If the whole channel is in MMIO, then do not do dummy read. - // - LibAmdMsrRead (TOP_MEM, &TOM, &NBPtr->MemPtr->StdHeader); - if ((*TestAddr >= TOM) && (*TestAddr < ((UINT64) _4GB_RJ16 << 16))) { - if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) { - // This is the DCT that goes to high address range - if (DctSelBaseAddr >= (_4GB_RJ16 >> (27 - 16))) { - // When DctSelBaseAddr is higher than 4G, choose DctSelBaseAddr as the dummy read addr - if (DctSelIntlvEn) { - *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF); - } - } else if (MemNGetBitFieldNb (NBPtr, BFDramLimitAddr) > (UINT32) (_4GB_RJ16 >> (27 - 16))) { - // if DctSelBase is smaller than 4G, but Dram limit is larger than 4G, then choose 4G as - // dummy read address - *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF); - } else { - AddrFound = FALSE; - } - } else { - // This is the DCT that only goes to low address range - if (DctSelBaseAddr > (_4GB_RJ16 >> (27 - 16))) { - // When DctSelBaseAddr is larger than 4G, choose 4G as the dummy read address - // Keep the lower bits for node and channel selection - *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF); - } else { - AddrFound = FALSE; - } - } - } - - // Interleaved Swap Region handling - if ((BOOLEAN) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSwapEn)) { - IntLvRgnBaseAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr); - IntLvRgnLmtAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr); - IntLvRgnSize = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSize); - ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1)); - if (((*TestAddr >> 34) == 0) && - ((((*TestAddr >> 27) >= IntLvRgnBaseAddr) && ((*TestAddr >> 27) <= IntLvRgnLmtAddr)) - || ((*TestAddr >> 27) < IntLvRgnSize))) { - *TestAddr ^= (UINT64) IntLvRgnBaseAddr << 27; - } - } - - return AddrFound; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets bit 7 [MemClkFreqVal] of F2x94_dct[1:0] - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetMemClkFreqValUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT32 TempValue; - - // 1. Program F2x94_dct[1:0][MemClkFreqVal] = 1 - MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr); - TempValue |= 0x80; - MemNS3RestoreNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr); - - // 2. Wait for F2x94_dct[1:0][FreqChgInPrg] = 0 - MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr); - while ((TempValue & 0x200000) != 0) { - MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function changes memory Pstate context - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. Target MemPState is in - * Address.Address.Register. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -VOID -MemNS3ChangeMemPStateContextNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - LOCATE_HEAP_PTR LocateBufferPtr; - S3_MEM_NB_BLOCK *S3NBPtr; - UINT8 Die; - - // See which Node should be accessed - Die = (UINT8) (Address.Address.Device - 24); - - LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { - S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; - NBPtr = S3NBPtr[Die].NBPtr; - MemNChangeMemPStateContextNb (NBPtr, Address.Address.Register); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function retores Phy Clk DLL fine delay - * - * @param[in] AccessWidth - Access width of the register. - * @param[in] Address - address in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value to be written. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -MemNS3SetPhyClkDllFineClientNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - UINT16 RegValue; - - RegValue = 0x4000 | *(UINT16 *) Value; - MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); - RegValue = 0xBFFF & *(UINT16 *) Value; - MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c deleted file mode 100644 index 666e7fd289..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c +++ /dev/null @@ -1,3453 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mndct.c - * - * Common Northbridge DCT support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 60556 $ @e \$Date: 2011-10-17 20:19:58 -0600 (Mon, 17 Oct 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "mftds.h" -#include "merrhdl.h" -#include "cpuFamilyTranslation.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_MNDCT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemNAfterStitchMemNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -UINT8 -MemNGet1KTFawTkNb ( - IN UINT8 k - ); - -UINT8 -MemNGet2KTFawTkNb ( - IN UINT8 k - ); - -VOID -STATIC -MemNQuarterMemClk2NClkNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT UINT16 *SubTotalPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function combines all the memory into a contiguous map. - * Requires that Mask values for each bank be programmed first and that - * the chip-select population indicator is correctly set. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - */ - -BOOLEAN -MemNStitchMemoryNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BOOLEAN DSpareEn; - UINT32 NxtCSBase; - UINT32 CurCSBase; - UINT32 CsSize; - UINT32 BiggestBank; - UINT8 p; - UINT8 q; - UINT8 BiggestDimm; - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - DSpareEn = FALSE; - if (NBPtr->IsSupported[SetSpareEn]) { - DSpareEn = FALSE; - if (RefPtr->GStatus[GsbEnDIMMSpareNW]) { - DSpareEn = TRUE; - } - } - - DCTPtr->Timings.CsEnabled = 0; - NxtCSBase = 0; - for (p = 0; p < MAX_CS_PER_CHANNEL; p++) { - BiggestBank = 0; - BiggestDimm = 0; - for (q = 0; q < MAX_CS_PER_CHANNEL; q++) { - if (((DCTPtr->Timings.CsPresent & ~DCTPtr->Timings.CsTestFail) & ((UINT16)1 << q)) != 0) { - if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) { - // (CSEnable|Spare==1)bank is not enabled yet - CsSize = MemNGetBitFieldNb (NBPtr, BFCSMask0Reg + (q >> 1)); - if (CsSize != 0) { - CsSize += ((UINT32)1 << 19); - CsSize &= 0xFFF80000; - } - if (CsSize > BiggestBank) { - BiggestBank = CsSize; - BiggestDimm = q; - } - } - } - } - - if (BiggestBank != 0) { - CurCSBase = NxtCSBase; - if (NBPtr->IsSupported[CheckSpareEn]) { - if (DSpareEn) { - CurCSBase = ((UINT32)1 << BFSpare); - DSpareEn = FALSE; - } else { - CurCSBase |= ((UINT32)1 << BFCSEnable); - NxtCSBase += BiggestBank; - } - } else { - CurCSBase |= ((UINT32)1 << BFCSEnable); - NxtCSBase += BiggestBank; - } - if ((BiggestDimm & 1) != 0) { - if (!(MCTPtr->Status[SbLrdimms])) { - // For LRDIMMS, On Dimm Mirroring is enabled after SDI - if ((DCTPtr->Timings.DimmMirrorPresent & (1 << (BiggestDimm >> 1))) != 0) { - CurCSBase |= ((UINT32)1 << BFOnDimmMirror); - } - } - } - MemNSetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + BiggestDimm, CurCSBase); - DCTPtr->Timings.CsEnabled |= (1 << BiggestDimm); - } - if ((DCTPtr->Timings.CsTestFail & ((UINT16)1 << p)) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "Node %d Dct %d exclude CS %d\n", NBPtr->Node, NBPtr->Dct, p); - MemNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + p), (UINT32)1 << BFTestFail); - } - } - - if (NxtCSBase != 0) { - DCTPtr->Timings.DctMemSize = NxtCSBase >> 8; // Scale base address from [39:8] to [47:16] - MemNAfterStitchMemNb (NBPtr); - } - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets platform specific config/timing values from the interface layer and - * programs them into DCT. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - */ - -BOOLEAN -MemNPlatformSpecNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST BIT_FIELD_NAME ChipletPDRegs[] = { - BFPhyClkConfig0, - BFPhyClkConfig3, - BFPhyClkConfig1, - BFPhyClkConfig2 - }; - CONST UINT8 ChipletPDClkDisMap[][2] = { - //F2[1, 0]x9C_x0D0F2030 -> F2x[1, 0]88[MemClkDis[1:0]] - {0, 1}, - //F2[1, 0]x9C_x0D0F2330 -> F2x[1, 0]88[MemClkDis[7:6]] - {6, 7}, - //F2x09C_x0D0F2130 -> F2x88[MemClkDis[5:4]] - {4, 5}, - //F2x09C_x0D0F2230 -> F2x88[MemClkDis[3:2]] - {2, 3}, - //F2x19C_x0D0F2130 -> F2x188[MemClkDis[5:2]] - {2, 5}, - //F2x19C_x0D0F2230 -> F2x188[MemClkDis[4:3]] - {3, 4} - }; - - UINT8 MemClkDis; - UINT8 i; - UINT8 MemoryAllClocks; - UINT8 *MemClkDisMap; - UINT16 CsPresent; - UINT8 RegIndex; - UINT8 Cs1; - UINT8 Cs2; - - if (!MemNGetPlatformCfgNb (NBPtr)) { - IDS_ERROR_TRAP; - } - - if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) { - IDS_ERROR_TRAP; - } - MemNProgramPlatformSpecNb (NBPtr); - - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS); - - if (NBPtr->MCTPtr->GangedMode) { - MemNSwitchDCTNb (NBPtr, 1); - if (!MemNGetPlatformCfgNb (NBPtr)) { - IDS_ERROR_TRAP; - } - MemNProgramPlatformSpecNb (NBPtr); - MemNSwitchDCTNb (NBPtr, 0); - } - - //====================================================================== - // Disable unused MemClk to save power - //====================================================================== - // - MemClkDis = 0; - MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn; - IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader)); - if (!MemoryAllClocks) { - // Special Jedec SPD diagnostic bit - "enable all clocks" - if (!NBPtr->MCTPtr->Status[SbDiagClks]) { - MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0), 0, - &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader)); - if (MemClkDisMap == NULL) { - MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap; - } - - // Turn off the unused CS clocks - CsPresent = NBPtr->DCTPtr->Timings.CsPresent; - - if (NBPtr->IsSupported[CheckMemClkCSPresent]) { - if (NBPtr->ChannelPtr->RegDimmPresent != 0) { - // All DDR3 RDIMM use only one MEMCLOCK from edge finger to the register - // regardless of how many Ranks are on the DIMM (Single, Dual or Quad) - CsPresent = (CsPresent | (CsPresent >> 1)) & 0x5555; - } - } - for (i = 0; i < 8; i++) { - if ((CsPresent & MemClkDisMap[i]) == 0) { - MemClkDis |= (UINT8) (1 << i); - } - } - //Chiplet power down - for (RegIndex = 0; RegIndex < GET_SIZE_OF (ChipletPDRegs); RegIndex++) { - if ((NBPtr->Dct == 1) && (RegIndex >= 2)) { - Cs1 = MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][0]]; - Cs2 = MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][1]]; - } else { - Cs1 = MemClkDisMap[ChipletPDClkDisMap[RegIndex][0]]; - Cs2 = MemClkDisMap[ChipletPDClkDisMap[RegIndex][1]]; - } - if ((CsPresent & (UINT16) (Cs1 | Cs2)) == 0) { - MemNSetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex], (MemNGetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex]) | 0x10)); - } - } - } - } - MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis); - - AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNInitPhyComp (NBPtr); - - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); - - // Program DramTerm for DDR2 - if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) == 0) { - MemNSetBitFieldNb (NBPtr, BFDramTerm, NBPtr->PsPtr->DramTerm); - } else { - // Dynamic Dynamic DramTerm for DDR3 - // Dram Term for DDR3 may vary based on chip selects - MemNSetBitFieldNb (NBPtr, BFDramTermDyn, NBPtr->PsPtr->DynamicDramTerm); - } - - MemFInitTableDrive (NBPtr, MTAfterPlatformSpec); - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets platform specific config/timing values from the interface layer and - * programs them into DCT. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - */ - -BOOLEAN -MemNPlatformSpecUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 MemClkDis; - UINT8 i; - UINT8 MemoryAllClocks; - UINT8 *MemClkDisMap; - UINT16 CsPresent; - - if (!MemNGetPlatformCfgNb (NBPtr)) { - IDS_ERROR_TRAP; - } - - if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tDisable DCT%d due to unsupported DIMM configuration\n", NBPtr->Dct); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - NBPtr->DisableDCT (NBPtr); - } else { - - MemNProgramPlatformSpecNb (NBPtr); - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS); - - //====================================================================== - // Disable unused MemClk to save power - //====================================================================== - // - MemClkDis = 0; - MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn; - IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader)); - if (!MemoryAllClocks) { - // Special Jedec SPD diagnostic bit - "enable all clocks" - if (!NBPtr->MCTPtr->Status[SbDiagClks]) { - MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, NBPtr->Dct, 0, - &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader)); - if (MemClkDisMap == NULL) { - MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap; - } - - // Turn off unused clocks - CsPresent = NBPtr->DCTPtr->Timings.CsPresent; - - for (i = 0; i < 8; i++) { - if ((CsPresent & MemClkDisMap[i]) == 0) { - MemClkDis |= (UINT8) (1 << i); - } - } - - // Turn off unused chiplets - for (i = 0; i < 3; i++) { - if (((MemClkDis >> (i * 2)) & 0x3) == 0x3) { - MemNSetBitFieldNb (NBPtr, BFPhyClkConfig0 + i, 0x0010); - } - } - } - } - MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis); - MemFInitTableDrive (NBPtr, MTAfterPlatformSpec); - } - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function disables the DCT and mem clock - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNDisableDCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03); - MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F); - MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF); - - // To maximize power savings when DisDramInterface=1b, - // all of the MemClkDis bits should also be set. - // - MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); - MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function disables the DCT and mem clock for client NB - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNDisableDCTClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03); - MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F); - MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF); - - //Wait for 24 MEMCLKs - MemNWaitXMemClksNb (NBPtr, 24); - - // To maximize power savings when DisDramInterface=1b, - // all of the MemClkDis bits should also be set. - // - MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); - - MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000); - - MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function disables the DCT and mem clock for UNB - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNDisableDCTUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSetBitFieldNb (NBPtr, BFExtendedParityEn, 0); - MemNSetBitFieldNb (NBPtr, BFParEn, 0); - MemNSetBitFieldNb (NBPtr, BFCKETri, 0x0F); - - //Wait for 24 MEMCLKs - MemNWaitXMemClksNb (NBPtr, 24); - - // To maximize power savings when DisDramInterface=1b, - // all of the MemClkDis bits should also be set. - // - MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); - - MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); - - if (NBPtr->Dct == 0) { - MemNSetBitFieldNb (NBPtr, BFPhyPSMasterChannel, 0x100); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DRAM devices on all DCTs at the same time - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNStartupDCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // 1. Ensure F2x[1, 0]9C_x08[DisAutoComp] = 1. - // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. - // DisAutoComp is still being set since InitPhyComp - - if (NBPtr->MCTPtr->NodeMemSize != 0) { - // Init MemClk frequency - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); - - - AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNBeforeDramInitNb (NBPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", NBPtr->DCTPtr->Timings.Speed); - AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader)); - NBPtr->FeatPtr->DramInit (NBPtr->TechPtr); - } - - // 7. Program F2x[1, 0]9C_x08[DisAutoComp] = 0. - // 8. BIOS must wait 750 us for the phy compensation engine - // to reinitialize. - // DisAutoComp will be cleared after DramEnabled turns to 1 - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DRAM devices on all DCTs at the same time - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNStartupDCTUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT16 FinalPllLockTime; - - if (NBPtr->MCTPtr->NodeMemSize != 0) { - // Update NB frequency for startup DDR speed - NBPtr->ChangeNbFrequency (NBPtr); - - if (NBPtr->FamilySpecificHook[ForcePhyToM0] (NBPtr, NULL)) { - // Program D18F2x[1,0]9C_x0000_000B = 80000000h. #109999. - MemNBrdcstSetNb (NBPtr, BFDramPhyStatusReg, 0x80000000); - - // Program D18F2x[1,0]9C_x0D0F_E013[PllRegWaitTime] = 0118h. #194060. - MemNBrdcstSetNb (NBPtr, BFPllRegWaitTime, 0x118); - } - - // Phy Voltage Level Programming - MemNPhyVoltageLevelNb (NBPtr); - - // Run frequency change sequence - MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); - MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); - NBPtr->FamilySpecificHook[SetSkewMemClk] (NBPtr, NULL); - NBPtr->ProgramNbPsDependentRegs (NBPtr); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if ((NBPtr->DCTPtr->Timings.DctMemSize != 0)) { - MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1); - MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - } - } - FinalPllLockTime = 0xF; - NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &FinalPllLockTime); - if (!NBPtr->IsSupported[CsrPhyPllPdEn]) { - // IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program - // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh - MemNBrdcstSetNb (NBPtr, BFPllLockTime, FinalPllLockTime); - } - - NBPtr->FamilySpecificHook[BeforePhyFenceTraining] (NBPtr, NBPtr); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - - // Phy fence programming - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - NBPtr->PhyFenceTraining (NBPtr); - - // Phy compensation initialization - AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNInitPhyComp (NBPtr); - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); - } - } - - AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNBeforeDramInitNb (NBPtr); - - AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", NBPtr->DCTPtr->Timings.Speed); - NBPtr->FeatPtr->DramInit (NBPtr->TechPtr); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * MemNChangeFrequencyHy: - * - * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNChangeFrequencyNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 Dct; - UINT8 ChipSel; - - TechPtr = NBPtr->TechPtr; - if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) { - // #107421 - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1); - } - - //Program F2x[1,0]90[EnterSelfRefresh]=1. - //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0. - MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - - //Program F2x9C_x08[DisAutoComp]=1 - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); - - //Program F2x[1, 0]94[MemClkFreqVal] = 0. - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0); - - //Program F2x[1, 0]94[MemClkFreq] to specify the target MEMCLK frequency. - MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); - - IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader)); - //Program F2x[1, 0]94[MemClkFreqVal] = 1. - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); - - //Wait until F2x[1, 0]94[FreqChgInProg]=0. - MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE); - - if (NBPtr->IsSupported[CheckPhyFenceTraining]) { - //Perform Phy Fence retraining after frequency changed - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - MemNPhyFenceTrainingNb (NBPtr); - } - } - } - - //Program F2x9C_x08[DisAutoComp]=0 - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); - - //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs. - //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. - MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - - if (NBPtr->MCTPtr->Status[SbRegistered]) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - TechPtr->FreqChgCtrlWrd (TechPtr); - } - } - } - - //wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns - MemNWaitXMemClksNb (NBPtr, 500); - - if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) { - // #107421 - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0); - } - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - - //9.Configure the DCT to send initialization MR commands: - // BIOS must reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency. - // Program F2x[1, 0]7C similar to step #2 in Pass 1 above for the new Dimm values. - TechPtr->AutoCycTiming (TechPtr); - if (!MemNPlatformSpecNb (NBPtr)) { - IDS_ERROR_TRAP; - } - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if (NBPtr->IsSupported[CheckGetMCTSysAddr]) { - if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) { - // if chip select present - TechPtr->SendAllMRCmds (TechPtr, ChipSel); - // NOTE: wait 512 clocks for DLL-relock - MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us - } - } - if (NBPtr->IsSupported[CheckSendAllMRCmds]) { - if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) { - - // if chip select present - TechPtr->SendAllMRCmds (TechPtr, ChipSel); - } - } - } - if ((NBPtr->DCTPtr->Timings.Speed == DDR1600_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) { - MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000)); - MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000)); - if (Dct == 0) { - MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000)); - } - // NOTE: wait 512 clocks for DLL-relock - MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us - } - } - } - // Re-enable phy compensation since it had been disabled during InitPhyComp - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); - - MemFInitTableDrive (NBPtr, MTAfterFreqChg); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function ramp up frequency the next level if it have not reached - * its TargetSpeed yet. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNRampUpFrequencyNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT16 FreqList[] = { - DDR400_FREQUENCY, - DDR533_FREQUENCY, - DDR667_FREQUENCY, - DDR800_FREQUENCY, - DDR1066_FREQUENCY, - DDR1333_FREQUENCY, - DDR1600_FREQUENCY, - DDR1866_FREQUENCY - }; - UINT8 Dct; - UINT8 i; - UINT16 NewSpeed; - DIE_STRUCT *MCTPtr; - - MCTPtr = NBPtr->MCTPtr; - - // Do not change frequency when it is already at TargetSpeed - if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { - return TRUE; - } - - // Find the next supported frequency level - NewSpeed = NBPtr->DCTPtr->Timings.TargetSpeed; - for (i = 0; i < (GET_SIZE_OF (FreqList) - 1); i++) { - if (NBPtr->DCTPtr->Timings.Speed == FreqList[i]) { - NewSpeed = FreqList[i + 1]; - break; - } - } - ASSERT (i < (GET_SIZE_OF (FreqList) - 1)); - ASSERT (NewSpeed <= NBPtr->DCTPtr->Timings.TargetSpeed); - - // BIOS must program both DCTs to the same frequency. - IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq changed: %d MHz", NBPtr->DCTPtr->Timings.Speed); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->DCTPtr->Timings.Speed = NewSpeed; - } - IDS_HDT_CONSOLE (MEM_FLOW, " -> %d MHz", NewSpeed); - - NBPtr->ChangeFrequency (NBPtr); - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function ramp up frequency to target frequency - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNRampUpFrequencyUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - DIE_STRUCT *MCTPtr; - - MCTPtr = NBPtr->MCTPtr; - - // Do not change frequency when it is already at TargetSpeed - if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { - return TRUE; - } - - // BIOS must program both DCTs to the same frequency. - IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq changed: %d MHz", NBPtr->DCTPtr->Timings.Speed); - for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->DCTPtr->Timings.Speed = NBPtr->DCTPtr->Timings.TargetSpeed; - } - IDS_HDT_CONSOLE (MEM_FLOW, " -> %d MHz", NBPtr->DCTPtr->Timings.TargetSpeed); - - NBPtr->ChangeFrequency (NBPtr); - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function uses calculated values from DCT.Timings structure to - * program its registers. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramCycTimingsNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST CTENTRY TmgAdjTab[] = { - // BitField, Min, Max, Bias, Ratio_x2 - {BFTcl, 4, 12, 4, 2}, - {BFTrcd, 5, 12, 5, 2}, - {BFTrp, 5, 12, 5, 2}, - {BFTrtp, 4, 7, 4, 2}, - {BFTras, 15, 30, 15, 2}, - {BFTrc, 11, 42, 11, 2}, - {BFTwrDDR3, 5, 12, 4, 2}, - {BFTrrd, 4, 7, 4, 2}, - {BFTwtr, 4, 7, 4, 2}, - {BFFourActWindow, 16, 32, 14, 1} - }; - - DCT_STRUCT *DCTPtr; - UINT8 *MiniMaxTmg; - UINT8 *MiniMaxTrfc; - UINT8 Value8; - UINT8 j; - BIT_FIELD_NAME BitField; - - DCTPtr = NBPtr->DCTPtr; - - //====================================================================== - // Program turnaround timings to their max during DRAM init and training - //====================================================================== - // - MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF); - - MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A); - - //====================================================================== - // Program DRAM Timing values - //====================================================================== - // - MiniMaxTmg = &DCTPtr->Timings.CasL; - for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { - BitField = TmgAdjTab[j].BitField; - - if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { - MiniMaxTmg[j] = TmgAdjTab[j].Min; - } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { - MiniMaxTmg[j] = TmgAdjTab[j].Max; - } - - Value8 = (UINT8) MiniMaxTmg[j]; - - if (BitField == BFTwrDDR3) { - Value8 = (Value8 == 10) ? 9 : (Value8 >= 11) ? 10 : Value8; - } else if (BitField == BFTrtp) { - Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6; - } - - Value8 = Value8 - TmgAdjTab[j].Bias; - Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1; - - ASSERT ((BitField == BFTcl ) ? (Value8 <= 8) : - (BitField == BFTrcd) ? (Value8 <= 7) : - (BitField == BFTrp ) ? (Value8 <= 7) : - (BitField == BFTrtp) ? (Value8 <= 3) : - (BitField == BFTras) ? (Value8 <= 15) : - (BitField == BFTrc ) ? (Value8 <= 31) : - (BitField == BFTrrd) ? (Value8 <= 3) : - (BitField == BFTwtr) ? (Value8 <= 3) : - (BitField == BFTwrDDR3) ? ((Value8 >= 1) && (Value8 <= 6)) : - (BitField == BFFourActWindow) ? ((Value8 >= 1) && (Value8 <= 9)) : FALSE); - MemNSetBitFieldNb (NBPtr, BitField, Value8); - } - - MiniMaxTrfc = &DCTPtr->Timings.Trfc0; - for (j = 0; j < 4; j++) { - ASSERT (MiniMaxTrfc[j] <= 4); - MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); - } - - MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? - (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0)); - - MemNSetBitFieldNb (NBPtr, BFTref, 2); // 7.8 us - - //====================================================================== - // DRAM MRS Register, set ODT - //====================================================================== - // - // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7) - MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1); - - // burst length control - if (NBPtr->MCTPtr->Status[Sb128bitmode]) { - MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2); - } - - // ASR=1, auto self refresh; SRT=0 - MemNSetBitFieldNb (NBPtr, BFASR, 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function uses calculated values from DCT.Timings structure to - * program its registers. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramCycTimingsClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST CTENTRY TmgAdjTab[] = { - // BitField, Min, Max, Bias, Ratio_x2 - {BFTcl, 5, 14, 4, 2}, - {BFTrcd, 5, 14, 5, 2}, - {BFTrp, 5, 14, 5, 2}, - {BFTrtp, 4, 8, 4, 2}, - {BFTras, 15, 36, 15, 2}, - {BFTrc, 20, 49, 11, 2}, - {BFTwrDDR3, 5, 16, 4, 2}, - {BFTrrd, 4, 8, 4, 2}, - {BFTwtr, 4, 8, 4, 2}, - {BFFourActWindow, 16, 40, 14, 1} - }; - - DCT_STRUCT *DCTPtr; - UINT8 *MiniMaxTmg; - UINT8 *MiniMaxTrfc; - UINT8 Value8; - UINT8 j; - UINT8 Tcwl; - UINT8 Trcd; - INT32 TCK_ps; - BIT_FIELD_NAME BitField; - - DCTPtr = NBPtr->DCTPtr; - - //====================================================================== - // Program DRAM Timing values - //====================================================================== - // - MiniMaxTmg = &DCTPtr->Timings.CasL; - for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { - BitField = TmgAdjTab[j].BitField; - - if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { - MiniMaxTmg[j] = TmgAdjTab[j].Min; - } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { - MiniMaxTmg[j] = TmgAdjTab[j].Max; - } - - Value8 = (UINT8) MiniMaxTmg[j]; - - if (BitField == BFTwrDDR3) { - if (NBPtr->IsSupported[AdjustTwr]) { - Value8 ++; - } - Value8 = (Value8 >= 10) ? (((Value8 + 1) / 2) + 4) : Value8; - } - - if ((BitField == BFTrc) && NBPtr->IsSupported[AdjustTrc]) { - Value8 -= 5; - } - - Value8 = Value8 - TmgAdjTab[j].Bias; - Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1; - - ASSERT ((BitField == BFTcl ) ? ((Value8 >= 1) && (Value8 <= 10)) : - (BitField == BFTrcd) ? (Value8 <= 9) : - (BitField == BFTrp ) ? (Value8 <= 9) : - (BitField == BFTrtp) ? (Value8 <= 4) : - (BitField == BFTras) ? (Value8 <= 21) : - (BitField == BFTrc ) ? (NBPtr->IsSupported[AdjustTrc] ? ((Value8 >= 4) && (Value8 <= 38)) : ((Value8 >= 9) && (Value8 <= 38))) : - (BitField == BFTrrd) ? (Value8 <= 4) : - (BitField == BFTwtr) ? (Value8 <= 4) : - (BitField == BFTwrDDR3) ? (Value8 <= 7) : - (BitField == BFFourActWindow) ? ((Value8 >= 1) && (Value8 <= 13)) : FALSE); - MemNSetBitFieldNb (NBPtr, BitField, Value8); - } - - MiniMaxTrfc = &DCTPtr->Timings.Trfc0; - for (j = 0; j < 4; j++) { - ASSERT (MiniMaxTrfc[j] <= 5); - MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); - } - - Tcwl = (UINT8) (DCTPtr->Timings.Speed / 133) + 2; - MemNSetBitFieldNb (NBPtr, BFTcwl, ((Tcwl > 5) ? (Tcwl - 5) : 0)); - - MemNSetBitFieldNb (NBPtr, BFTref, 2); // Tref = 7.8 us - - // Skid buffer can only be programmed once before Dram init - if (NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) { - TCK_ps = 1000500 / DCTPtr->Timings.TargetSpeed; - Trcd = (UINT8) ((((1000 / 40) * (UINT32)DCTPtr->Timings.DIMMTrcd) + TCK_ps - 1) / TCK_ps); - MemNSetBitFieldNb (NBPtr, BFDbeSkidBufDis, (Trcd > 10) ? 0 : 1); - } - - MemNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, (DCTPtr->Timings.CasL > Tcwl) ? (DCTPtr->Timings.CasL - Tcwl) : 0); - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function uses calculated values from DCT.Timings structure to - * program its registers for UNB - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramCycTimingsUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST CTENTRY TmgAdjTab[] = { - // BitField, Min, Max, Bias, Ratio_x2 - {BFTcl, 5, 14, 0, 2}, - {BFTrcd, 2, 19, 0, 2}, - {BFTrp, 2, 19, 0, 2}, - {BFTrtp, 4, 10, 0, 2}, - {BFTras, 8, 40, 0, 2}, - {BFTrc, 10, 56, 0, 2}, - {BFTwrDDR3, 5, 16, 0, 2}, - {BFTrrd, 4, 9, 0, 2}, - {BFTwtr, 4, 9, 0, 2}, - {BFFourActWindow, 6, 42, 0, 2} - }; - - DCT_STRUCT *DCTPtr; - UINT8 *MiniMaxTmg; - UINT8 *MiniMaxTrfc; - UINT8 Value8; - UINT8 j; - UINT8 Tcwl; - UINT8 RdOdtTrnOnDly; - BIT_FIELD_NAME BitField; - - DCTPtr = NBPtr->DCTPtr; - - //====================================================================== - // Program DRAM Timing values - //====================================================================== - // - MiniMaxTmg = &DCTPtr->Timings.CasL; - for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { - BitField = TmgAdjTab[j].BitField; - - if (BitField == BFTrp) { - if (NBPtr->IsSupported[AdjustTrp]) { - MiniMaxTmg[j] ++; - if (MiniMaxTmg[j] < 5) { - MiniMaxTmg[j] = 5; - } - } - } - - if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { - MiniMaxTmg[j] = TmgAdjTab[j].Min; - } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { - MiniMaxTmg[j] = TmgAdjTab[j].Max; - } - - Value8 = (UINT8) MiniMaxTmg[j]; - - if (BitField == BFTwrDDR3) { - if ((Value8 > 8) && ((Value8 & 1) != 0)) { - ASSERT (FALSE); - } - } - - MemNSetBitFieldNb (NBPtr, BitField, Value8); - } - - MiniMaxTrfc = &DCTPtr->Timings.Trfc0; - for (j = 0; j < 4; j++) { - if ((NBPtr->DCTPtr->Timings.DctDimmValid & (1 << j)) != 0) { - ASSERT (MiniMaxTrfc[j] <= 4); - MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); - } - } - - Tcwl = (UINT8) (DCTPtr->Timings.Speed / 133) + 2; - MemNSetBitFieldNb (NBPtr, BFTcwl, ((Tcwl > 5) ? Tcwl : 5)); - - MemNSetBitFieldNb (NBPtr, BFTref, 2); // 7.8 us - - RdOdtTrnOnDly = (DCTPtr->Timings.CasL > Tcwl) ? (DCTPtr->Timings.CasL - Tcwl) : 0; - MemNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, RdOdtTrnOnDly); - NBPtr->FamilySpecificHook[ProgOdtControl] (NBPtr, NULL); - - // - // Program Tmod - // - MemNSetBitFieldNb (NBPtr, BFTmod, (DCTPtr->Timings.Speed < DDR1866_FREQUENCY) ? 0x0C : - (DCTPtr->Timings.Speed > DDR1866_FREQUENCY) ? 0x10 : 0x0E); - // - // Program Tzqcs and Tzqoper - // - // Tzqcs max(64nCK, 80ns) - MemNSetBitFieldNb (NBPtr, BFTzqcs, MIN (6, (MAX (64, MemUnsToMemClk (NBPtr->DCTPtr->Timings.Speed, 80)) + 15) / 16)); - // Tzqoper max(256nCK, 320ns) - MemNSetBitFieldNb (NBPtr, BFTzqoper, MIN (0xC, (MAX (256, MemUnsToMemClk (NBPtr->DCTPtr->Timings.Speed, 320)) + 31) / 32)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets platform specific settings for the current channel - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - All platform types defined have initialized successfully - * @return FALSE - At least one of the platform types gave not been initialized successfully - */ - -BOOLEAN -MemNGetPlatformCfgNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 p; - - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - ASSERT (NBPtr->MemPtr->GetPlatformCfg[p] != NULL); - if (NBPtr->MemPtr->GetPlatformCfg[p] (NBPtr->MemPtr, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr) == AGESA_SUCCESS) { - break; - } - } - return (p < MAX_PLATFORM_TYPES); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function retrieves the Max latency parameters - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @param[in] *MinDlyPtr - Pointer to variable to store the Minimum Delay value - * @param[in] *MaxDlyPtr - Pointer to variable to store the Maximum Delay value - * @param[in] *DlyBiasPtr - Pointer to variable to store Delay Bias value - * @param[in] MaxRcvEnDly - Maximum receiver enable delay value - */ - -VOID -MemNGetMaxLatParamsNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxRcvEnDly, - IN OUT UINT16 *MinDlyPtr, - IN OUT UINT16 *MaxDlyPtr, - IN OUT UINT16 *DlyBiasPtr - ) -{ - *MinDlyPtr = (MemNTotalSyncComponentsNb (NBPtr) + (MaxRcvEnDly >> 5)) * 2; - MemNQuarterMemClk2NClkNb (NBPtr, MinDlyPtr); - - *MaxDlyPtr = 0x3FF; - - *DlyBiasPtr = 4; - MemNQuarterMemClk2NClkNb (NBPtr, DlyBiasPtr); // 1 MEMCLK Margin - - *DlyBiasPtr += 1; // add 1 NCLK -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the maximum round-trip latency in the system from the processor to the DRAM - * devices and back. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] MaxRcvEnDly - Maximum receiver enable delay value - * - */ - -VOID -MemNSetMaxLatencyNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 MaxRcvEnDly - ) -{ - UINT16 SubTotal; - - AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader)); - - SubTotal = 0xC8; // init value for MaxRdLat used in training - - - if (MaxRcvEnDly != 0xFFFF) { - // Get all sync components BKDG steps 1-5 - SubTotal = MemNTotalSyncComponentsNb (NBPtr); - - // Add the maximum (worst case) delay value of DqsRcvEnGrossDelay - // that exists across all DIMMs and byte lanes. - // - SubTotal += MaxRcvEnDly >> 5; - - - // Add 14.5 to the sub-total. 14.5 represents part of the processor - // specific constant delay value in the DRAM clock domain. - // - SubTotal <<= 1; // scale 1/2 MemClk to 1/4 MemClk - SubTotal += 29; // add 14.5 1/2 MemClk - - // Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs) - // as follows (assuming DDR400 and assuming that no P-state or link speed - // changes have occurred). - // - MemNQuarterMemClk2NClkNb (NBPtr, &SubTotal); - - // Add 2 NCLKs to the sub-total. 2 represents part of the processor - // specific constant value in the northbridge clock domain. - // - SubTotal += 2; - } - - NBPtr->DCTPtr->Timings.MaxRdLat = SubTotal; - // Program the F2x[1, 0]78[MaxRdLatency] register with the total delay value - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", SubTotal); - MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sends the ZQCL command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSendZQCmdNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // 1.Program MrsAddress[10]=1 - MemNSetBitFieldNb (NBPtr, BFMrsAddress, (UINT32)1 << 10); - - // 2.Set SendZQCmd=1 - MemNSetBitFieldNb (NBPtr, BFSendZQCmd, 1); - - // 3.Wait for SendZQCmd=0 - MemNPollBitFieldNb (NBPtr, BFSendZQCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); - - // 4.Wait 512 MEMCLKs - MemNWaitXMemClksNb (NBPtr, 512); -} - - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function is used to create the DRAM map - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - */ - -VOID -STATIC -MemNAfterStitchMemNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (NBPtr->MCTPtr->GangedMode) { - NBPtr->MCTPtr->NodeMemSize = NBPtr->DCTPtr->Timings.DctMemSize; - NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1; - NBPtr->MCTPtr->DctData[1].Timings.CsPresent = NBPtr->DCTPtr->Timings.CsPresent; - NBPtr->MCTPtr->DctData[1].Timings.CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; - NBPtr->MCTPtr->DctData[1].Timings.DctMemSize = NBPtr->DCTPtr->Timings.DctMemSize; - } else { - // In unganged mode, add DCT0 and DCT1 to NodeMemSize - NBPtr->MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize; - NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1; - } -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Return the binary value of tfaw associated with - * the index k - * - * @param[in] k value - * - * @return F[k], in Binary MHz. - */ - -UINT8 -MemNGet1KTFawTkNb ( - IN UINT8 k - ) -{ - CONST UINT8 Tab1KTfawTK[] = {0, 8, 10, 13, 14, 19}; - ASSERT (k <= 5); - return Tab1KTfawTK[k]; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Return the binary value of the 2KTFaw associated with - * the index k - * - * @param[in] k value - * - * @return 2KTFaw converted based on k. - */ - -UINT8 -MemNGet2KTFawTkNb ( - IN UINT8 k - ) -{ - CONST UINT8 Tab2KTfawTK[] = {0, 10, 14, 17, 18, 24}; - ASSERT (k <= 5); - return Tab2KTfawTK[k]; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function converts the sub-total (in 1/4 MEMCLKs) to northbridge clocks (NCLKs) - * (assuming DDR400 and assuming that no P-state or link speed - * changes have occurred). - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *SubTotalPtr - pointer to Sub-Total - */ - -VOID -STATIC -MemNQuarterMemClk2NClkNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT UINT16 *SubTotalPtr - ) -{ - UINT32 NBFreq; - UINT32 MemFreq; - - // Multiply SubTotal by NB COF - NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200; - // Divide SubTotal by 4 times current MemClk frequency - MemFreq = NBPtr->DCTPtr->Timings.Speed * 4; - *SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq); // round up -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the total of sync components for Max Read Latency calculation - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Total in 1/2 MEMCLKs - */ - -UINT16 -MemNTotalSyncComponentsNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 SubTotal; - - // Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs UINTs. - SubTotal = (UINT16) MemNGetBitFieldNb (NBPtr, BFTcl) + 1; - if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) != 0) { - SubTotal += 3; - } - SubTotal *= 2; - - // If registered DIMMs are being used then add 1 MEMCLK to the sub-total. - if ((MemNGetBitFieldNb (NBPtr, BFUnBuffDimm)) == 0) { - SubTotal += 2; - } - - // If (F2x[1, 0]9C_x04[AddrCmdSetup] and F2x[1, 0]9C_x04[CsOdtSetup] and F2x[1, 0]9C_x04[Cke-Setup] = 0) then K = K + 1 - // If (F2x[1, 0]9C_x04[AddrCmdSetup] or F2x[1, 0]9C_x04[CsOdtSetup] or F2x[1, 0]9C_x04[CkeSetup] = 1) then K = K + 2 - if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) { - SubTotal += 1; - } else { - SubTotal += 2; - } - - // If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs, - // then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total. - // - SubTotal = SubTotal + (8 - (UINT16) MemNGetBitFieldNb (NBPtr, BFRdPtrInit)); - - return SubTotal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function swaps bits for OnDimmMirror support - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSwapBitsNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 ChipSel; - UINT32 MRSReg; - - ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel); - if ((ChipSel & 1) != 0) { - MRSReg = MemNGetBitFieldNb (NBPtr, BFDramInitRegReg); - if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) { - MRSReg = (MRSReg & 0xFFFCFE07) | ((MRSReg&0x100A8) << 1) | ((MRSReg&0x20150) >> 1); - MemNSetBitFieldNb (NBPtr, BFDramInitRegReg, MRSReg); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function swaps bits for OnDimmMirror support for Unb - * - * Dimm Mirroring Requires that, during MRS command cycles, the following - * bits are swapped by software - * - * A3 -> A4 A7 -> A8 - * A4 -> A3 BA0 -> BA1 - * A5 -> A6 BA1 -> BA0 - * A6 -> A5 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSwapBitsUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 ChipSel; - UINT32 MRSBank; - UINT32 MRSAddr; - - ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel); - if ((ChipSel & 1) != 0) { - if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) { - MRSBank = MemNGetBitFieldNb (NBPtr, BFMrsBank); - MRSAddr = MemNGetBitFieldNb (NBPtr, BFMrsAddress); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %05x swapped to ->", - (ChipSel & 0x7), - (MRSBank & 0x7), - (MRSAddr & 0x3FFFF)); - // - // Swap Mrs Bank bits 0 with 1 - MRSBank = (MRSBank & 0x0100) | ((MRSBank & 0x01) << 1) | ((MRSBank & 0x02) >> 1); - // - // Swap Mrs Address bits 3 with 4, 5 with 6, and 7 with 8 - MRSAddr = (MRSAddr & 0x03FE07) | ((MRSAddr&0x000A8) << 1) | ((MRSAddr&0x00150) >> 1); - MemNSetBitFieldNb (NBPtr, BFMrsBank, MRSBank); - MemNSetBitFieldNb (NBPtr, BFMrsAddress, MRSAddr); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Programs Address/command timings, driver strengths, and tri-state fields. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNProgramPlatformSpecNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT8 PinType[3] = {PSO_CKE_TRI, PSO_ODT_TRI, PSO_CS_TRI}; - CONST UINT8 TabSize[3] = { 2, 4, 8}; - CONST BIT_FIELD_NAME BitField[3] = { BFCKETri, BFODTTri, BFChipSelTri}; - UINT8 *TabPtr; - UINT8 i; - UINT8 k; - UINT8 Value; - //=================================================================== - // Tristate unused CKE, ODT and chip select to save power - //=================================================================== - // - TabPtr = NULL; - for (k = 0; k < sizeof (PinType); k++) { - if (NBPtr->IsSupported[CheckFindPSOverideWithSocket]) { - TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0), 0, - &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader)); - } - if (NBPtr->IsSupported[CheckFindPSDct]) { - TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, NBPtr->Dct, 0, - &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader)); - } - if (TabPtr == NULL) { - switch (k) { - case 0: - TabPtr = NBPtr->ChannelPtr->CKETriMap; - break; - case 1: - TabPtr = NBPtr->ChannelPtr->ODTTriMap; - break; - case 2: - TabPtr = NBPtr->ChannelPtr->ChipSelTriMap; - break; - default: - IDS_ERROR_TRAP; - } - } - ASSERT (TabPtr != NULL); - - Value = 0; - for (i = 0; i < TabSize[k]; i++) { - if ((NBPtr->DCTPtr->Timings.CsPresent & TabPtr[i]) == 0) { - Value |= (UINT8) (1 << i); - } - } - - if (PinType[k] == PSO_CS_TRI) { - NBPtr->FamilySpecificHook[BeforeSetCsTri] (NBPtr, &Value); - } - - ASSERT (k < GET_SIZE_OF (BitField)); - MemNSetBitFieldNb (NBPtr, BitField[k], Value); - } - NBPtr->MemNBeforePlatformSpecNb (NBPtr); - - //=================================================================== - // Program Address/Command timings and driver strength - //=================================================================== - // - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ADDRTMG, ALL_DIMMS); - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODCCONTROL, ALL_DIMMS); - - MemNSetBitFieldNb (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0); - MemNSetBitFieldNb (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl); - MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg); - NBPtr->FamilySpecificHook[SetDqsODT] (NBPtr, NBPtr); - - if (NBPtr->IsSupported[CheckODTControls]) { - MemNSetBitFieldNb (NBPtr, BFPhyRODTCSLow, NBPtr->ChannelPtr->PhyRODTCSLow); - MemNSetBitFieldNb (NBPtr, BFPhyRODTCSHigh, NBPtr->ChannelPtr->PhyRODTCSHigh); - MemNSetBitFieldNb (NBPtr, BFPhyWODTCSLow, NBPtr->ChannelPtr->PhyWODTCSLow); - MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh); - } -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the Trdrd value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Trdrd value - */ - -UINT8 -MemNGetTrdrdNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - DCT_STRUCT *DCTPtr; - INT8 Cgdd; - - DCTPtr = NBPtr->DCTPtr; - - // BIOS calculates Trdrd (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Trdrd] with the - // converted field value. BIOS rounds fractional values down. - // The Critical Gross Delay Difference (CGDD) for Trdrd on any given byte lane is the largest F2x[1, - // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any DIMM minus the F2x[1, - // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any other DIMM. - - Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly); - DCTPtr->Timings.Trdrd = (Cgdd / 2) + 3; - - // Transfer clk to reg definition, 2T is 00b, etc. - DCTPtr->Timings.Trdrd -= 2; - if (DCTPtr->Timings.Trdrd > 8) { - DCTPtr->Timings.Trdrd = 8; - } - - return DCTPtr->Timings.Trdrd; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the Twrwr value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Twrwr value - */ - -UINT8 -MemNGetTwrwrNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - DCT_STRUCT *DCTPtr; - INT8 Cgdd; - - DCTPtr = NBPtr->DCTPtr; - - // Twrwr (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Twrwr] with the - // converted field value. BIOS rounds fractional values down. - // On any given byte lane, the largest F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1, 0]9C_x[3:0][A, 7, 6, - // 0]3[WrDatGrossDlyByte] delay of any DIMM minus the F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1, - // 0]9C_x[3:0][A, 7, 6, 0]3[WrDatGrossDlyByte] delay of any other DIMM is equal to the Critical Gross - // Delay Difference (CGDD) for Twrwr. - - Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessWrDatDly); - DCTPtr->Timings.Twrwr = (Cgdd / 2) + 3; - NBPtr->TechPtr->AdjustTwrwr (NBPtr->TechPtr); - - return DCTPtr->Timings.Twrwr; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the Twrrd value. BIOS calculates Twrrd (in MEMCLKs) = CGDD / 2 - LD + 3 clocks and programs - * F2x[1, 0]8C[Twrrd] with the converted field value. BIOS rounds fractional - * values down. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Value to be programmed to Twrrd field - * pDCT->Timings.Twrrd updated - */ - -UINT8 -MemNGetTwrrdNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - INT8 Cgdd; - INT8 Ld; - INT8 Twrrd; - DCT_STRUCT *DCTPtr; - - DCTPtr = NBPtr->DCTPtr; - - // - // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS - // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive - // value. - // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1). - // - Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr); - - // On any given byte lane, the largest WrDatGrossDlyByte delay of any DIMM - // minus the DqsRcvEnGrossDelay delay of any other DIMM is - // equal to the Critical Gross Delay Difference (CGDD) for Twrrd. - Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessRcvEnDly); - Twrrd = (Cgdd / 2) - Ld + 3; - DCTPtr->Timings.Twrrd = (UINT8) ((Twrrd >= 0) ? Twrrd : 0); - NBPtr->TechPtr->AdjustTwrrd (NBPtr->TechPtr); - - return DCTPtr->Timings.Twrrd; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the TrwtTO value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return pDCT->Timings.TrwtTO updated - */ - -UINT8 -MemNGetTrwtTONb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - INT8 Cgdd; - INT8 Ld; - INT8 TrwtTO; - DCT_STRUCT *DCTPtr; - - DCTPtr = NBPtr->DCTPtr; - // - // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS - // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive - // value. - // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1). - // - Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr); - - // On any byte lane, the largest DqsRcvEnGrossDelay delay of any DIMM minus - // the WrDatGrossDlyByte delay of any other DIMM is equal to the Critical Gross - // Delay Difference (CGDD) for TrwtTO. - Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessWrDatDly); - TrwtTO = (Cgdd / 2) + Ld + 3; - TrwtTO -= 2; - DCTPtr->Timings.TrwtTO = (UINT8) ((TrwtTO > 1) ? TrwtTO : 1); - - return DCTPtr->Timings.TrwtTO; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the TrwtWB value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TrwtWB value - */ -UINT8 -MemNGetTrwtWBNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - DCT_STRUCT *DCTPtr; - - DCTPtr = NBPtr->DCTPtr; - - // TrwtWB ensures read-to-write data-bus turnaround. - // This value should be one more than the programmed TrwtTO. - return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function converts MemClk frequency in MHz to MemClkFreq value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Speed - MemClk frequency in MHz - * - * @return MemClkFreq value - */ -UINT8 -MemNGetMemClkFreqIdNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 Speed - ) -{ - return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function enables swapping interleaved region feature. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Base - Swap interleaved region base [47:27] - * @param[in] Limit - Swap interleaved region limit [47:27] - * - */ -VOID -MemNEnableSwapIntlvRgnNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Base, - IN UINT32 Limit - ) -{ - UINT32 Size; - UINT32 SizeOfAlign; - - // Swapped interleaving region must be below 16G - if (Limit < (1 << (34 - 27))) { - // Adjust Base and Size to meet : - // 1. The size of the swapped region must be less than or equal to the alignment of F2x10C[IntLvRegionBase]. - // 2. Entire UMA region is swapped with interleaving region. - Size = Limit - Base; - SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base); - while (SizeOfAlign <= Size) { - // In case of SizeOfAlign <= Size, UmaBase -= 128MB, SizeOfIntlvrgn += 128MB. - Base -= 1; - Size += 1; - SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base); - } - MemNSetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr, Base); - MemNSetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr, (Limit - 1)); - MemNSetBitFieldNb (NBPtr, BFIntLvRgnSize, Size); - MemNSetBitFieldNb (NBPtr, BFIntLvRgnSwapEn, 1); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function converts MemClk frequency in MHz to MemClkFreq value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Speed - MemClk frequency in MHz - * - * @return MemClkFreq value - */ -UINT8 -MemNGetMemClkFreqIdClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 Speed - ) -{ - return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55))); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function converts MemClk frequency in MHz to MemClkFreq value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Speed - MemClk frequency in MHz - * - * @return MemClkFreq value - */ -UINT8 -MemNGetMemClkFreqIdUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT16 Speed - ) -{ - return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55))); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function converts MemClkFreq Id value to MemClk frequency in MHz - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FreqId - FreqId from Register - * - * @return MemClk frequency in MHz - */ -UINT16 -MemNGetMemClkFreqUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 FreqId - ) -{ - UINT16 MemClkFreq; - if (FreqId > 2) { - MemClkFreq = (FreqId == 14) ? 667 : (300 + ((FreqId - 3) * 33) + (FreqId - 3) / 3); - } else if (FreqId == 2) { - MemClkFreq = 200; - } else { - MemClkFreq = 50 + (50 * FreqId); - } - return MemClkFreq; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed - * for client NB. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNChangeFrequencyClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 Dct; - UINT8 ChipSel; - UINT16 FinalPllLockTime; - BOOLEAN FrequencyChangeSuccess; - UINT64 OrgMMIOCfgBase; - UINT64 NewMMIOCfgBase; - - TechPtr = NBPtr->TechPtr; - - // Disable MMIO to prevent speculative DRAM reads during self refresh - LibAmdMsrRead (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - NewMMIOCfgBase = OrgMMIOCfgBase & (~(BIT0)); - LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &NewMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1); - - //Program F2x[1,0]90[EnterSelfRefresh]=1. - //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0. - MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - - if (NBPtr->ChangeNbFrequency (NBPtr)) { - // Reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency. - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - TechPtr->AutoCycTiming (TechPtr); - if (!MemNPlatformSpecUnb (NBPtr)) { - IDS_ERROR_TRAP; - } - } - } - - // 1. Program PllLockTime to Family-specific value - MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); - - // 2. Program D18F2x[1,0]94[MemClkFreqVal] = 0. - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0); - - // 3. Program D18F2x[1,0]94[MemClkFreq] to the desired DRAM frequency. - MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); - - // 4. Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator]. - // 5. Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1, - // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. See 2.10.3.2.2.1 [DCT Transmit Fifo Schedule - // Delay Programming]. - // 6. D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano) - // THEN 2 ELSE 3 ENDIF (Ontario) - NBPtr->ProgramNbPsDependentRegs (NBPtr); - - NBPtr->FamilySpecificHook[BeforeMemClkFreqVal] (NBPtr, NBPtr); - IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader)); - // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1. - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); - MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE); - FinalPllLockTime = 0xF; - NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &FinalPllLockTime); - - // 8. IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program - // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh. - if (!NBPtr->IsSupported[CsrPhyPllPdEn]) { - MemNBrdcstSetNb (NBPtr, BFPllLockTime, FinalPllLockTime); - } - - FrequencyChangeSuccess = TRUE; - } else { - // If NB frequency cannot be updated, use the current speed as the target speed - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - NBPtr->DCTPtr->Timings.Speed = NBPtr->TechPtr->PrevSpeed; - NBPtr->DCTPtr->Timings.TargetSpeed = NBPtr->TechPtr->PrevSpeed; - } - FrequencyChangeSuccess = FALSE; - } - - //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs. - //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. - MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0); - - if (FrequencyChangeSuccess) { - NBPtr->FamilySpecificHook[AfterMemClkFreqChg] (NBPtr, NULL); - - // Perform Phy Fence training and Phy comp init after frequency change - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - - // Phy fence programming - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - NBPtr->PhyFenceTraining (NBPtr); - - // Phy compensation initialization - AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNInitPhyComp (NBPtr); - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); - } - } - - //====================================================================== - // Calculate and program DRAM Timings at new frequency - //====================================================================== - // - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) { - // if chip select present - if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) { - TechPtr->SendAllMRCmds (TechPtr, ChipSel); - } - } - } - // Wait 512 clocks for DLL-relock - MemNWaitXMemClksNb (NBPtr, 512); - } - } - } - - // Restore MMIO setting - LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - - MemFInitTableDrive (NBPtr, MTAfterFreqChg); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed - * for UNB. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNChangeFrequencyUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 Dct; - UINT8 ChipSel; - UINT16 FinalPllLockTime; - BOOLEAN FrequencyChangeSuccess; - UINT64 OrgMMIOCfgBase; - UINT64 NewMMIOCfgBase; - - TechPtr = NBPtr->TechPtr; - - // Disable MMIO to prevent speculative DRAM reads during self refresh - LibAmdMsrRead (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - NewMMIOCfgBase = OrgMMIOCfgBase & (~(BIT0)); - LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &NewMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1); - - //Program F2x[1,0]90[EnterSelfRefresh]=1. - //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0. - MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - - if (NBPtr->ChangeNbFrequency (NBPtr)) { - // Reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency. - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - TechPtr->AutoCycTiming (TechPtr); - if (!MemNPlatformSpecUnb (NBPtr)) { - IDS_ERROR_TRAP; - } - } - } - - // 1. Program PllLockTime to Family-specific value - MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); - - // 2. Program D18F2x[1,0]94[MemClkFreqVal] = 0. - MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0); - - // 3. Program D18F2x[1,0]94[MemClkFreq] to the desired DRAM frequency. - MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); - - // 4. Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator]. - // 5. Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1, - // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. See 2.10.3.2.2.1 [DCT Transmit Fifo Schedule - // Delay Programming]. - // 6. D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano) - // THEN 2 ELSE 3 ENDIF (Ontario) - NBPtr->ProgramNbPsDependentRegs (NBPtr); - - IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader)); - // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1. - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if ((NBPtr->DCTPtr->Timings.DctMemSize != 0)) { - MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1); - MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - } - } - FinalPllLockTime = 0xF; - NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &FinalPllLockTime); - - // 8. IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program - // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh. - if (!NBPtr->IsSupported[CsrPhyPllPdEn]) { - MemNBrdcstSetNb (NBPtr, BFPllLockTime, FinalPllLockTime); - } - - FrequencyChangeSuccess = TRUE; - } else { - // If NB frequency cannot be updated, use the current speed as the target speed - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - NBPtr->DCTPtr->Timings.Speed = NBPtr->TechPtr->PrevSpeed; - NBPtr->DCTPtr->Timings.TargetSpeed = NBPtr->TechPtr->PrevSpeed; - } - FrequencyChangeSuccess = FALSE; - } - - if (FrequencyChangeSuccess) { - // Perform Phy Fence training and Phy comp init after frequency change - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - - // Phy fence programming - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - NBPtr->PhyFenceTraining (NBPtr); - - // Phy compensation initialization - AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNInitPhyComp (NBPtr); - MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); - } - } - } - - //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs. - //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. - MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1); - MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - if (NBPtr->IsSupported[SetDllShutDown]) { - MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0); - } - - if (FrequencyChangeSuccess) { - NBPtr->FamilySpecificHook[AfterMemClkFreqChg] (NBPtr, NULL); - - //====================================================================== - // Calculate and program DRAM Timings at new frequency - //====================================================================== - // - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) { - // if chip select present - if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) { - TechPtr->SendAllMRCmds (TechPtr, ChipSel); - } - } - } - // Wait 512 clocks for DLL-relock - MemNWaitXMemClksNb (NBPtr, 512); - } - } - } - - // Restore MMIO setting - LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &OrgMMIOCfgBase, &(NBPtr->MemPtr->StdHeader)); - - MemFInitTableDrive (NBPtr, MTAfterFreqChg); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates and programs NB P-state dependent registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramNbPstateDependentRegistersUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 RdPtrInit; - - RdPtrInit = (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 6 : 4; - MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); - - MemFInitTableDrive (NBPtr, MTAfterNbPstateChange); - - IDS_HDT_CONSOLE_DEBUG_CODE ( - RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit); - ); - - switch (RdPtrInit) { - case 4: - if (MemNGetBitFieldNb (NBPtr, BFNbPsSel) == 0) { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 2); - } else { - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - } - break; - case 5: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1); - break; - case 6: - MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0); - break; - default: - ASSERT (FALSE); - } - - NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] (NBPtr, NBPtr); - IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3}; -CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56}; - -/** - * - * This function calculates and programs NB P-state dependent registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNProgramNbPstateDependentRegistersClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - UINT8 Dct; - UINT8 NclkFid; - UINT16 MemClkDid; - UINT8 PllMult; - UINT8 NclkDiv; - UINT8 RdPtrInitMin; - UINT8 RdPtrInit; - UINT32 NclkPeriod; - UINT32 MemClkPeriod; - INT32 PartialSum2x; - INT32 PartialSumSlotI2x; - INT32 RdPtrInitRmdr2x; - INT32 TDataProp; - UINT8 NbPstate; - UINT8 SlowMode; - - NclkFid = (UINT8) (MemNGetBitFieldNb (NBPtr, BFMainPllOpFreqId) + 0x10); // NclkFid is in 100MHz - - MemClkDid = PllDivTab[NBPtr->DCTPtr->Timings.Speed / 133]; - NBPtr->FamilySpecificHook[OverridePllDiv] (NBPtr, &MemClkDid); - PllMult = PllMultTab[NBPtr->DCTPtr->Timings.Speed / 133]; - NBPtr->FamilySpecificHook[OverridePllMult] (NBPtr, &PllMult); - - if (NBPtr->NbFreqChgState == 2) { - MemNSetBitFieldNb (NBPtr, BFNbPsCsrAccSel, 1); - MemNSetBitFieldNb (NBPtr, BFNbPsDbgEn, 1); - NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs1NclkDiv); - // Divisors less than 8 are undefined. Maybe the CPU does not support NB P-states. - if (NclkDiv < 8) { - // Set a dummy divisor to prevent divide by zero exception below. - NclkDiv = 8; - } - NbPstate = 1; - } else { - NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs0NclkDiv); - NbPstate = 0; - } - NclkPeriod = (2500 * NclkDiv) / NclkFid; // (1,000,000 * 0.25 * NclkDiv) / (NclkFid * 100MHz) = ps - MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; - NBPtr->NBClkFreq = ((UINT32) NclkFid * 400) / NclkDiv; - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\tNB P%d Freq: %dMHz\n", NbPstate, NBPtr->NBClkFreq); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClk Freq: %dMHz\n", NBPtr->DCTPtr->Timings.Speed); - // D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano) - // THEN 2 ELSE 3 ENDIF (Ontario) - RdPtrInit = RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667; - NBPtr->FamilySpecificHook[AdjustRdPtrInit] (NBPtr, &RdPtrInit); - MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); - - // Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator]. - MemNBrdcstSetNb (NBPtr, BFDbeGskFifoNumerator, NclkFid * MemClkDid * 16); - MemNBrdcstSetNb (NBPtr, BFDbeGskFifoDenominator, PllMult * NclkDiv); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoNumerator: %d\n", NclkFid * MemClkDid * 16); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoDenominator: %d\n", PllMult * NclkDiv); - - // Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1, - // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. - // PartialSum = ((7 * NclkPeriod) + (1.5 * MemClkPeriod) + 520ps)*MemClkFrequency - tCWL - - // CmdSetup - PtrSeparation - 1. (Llano) - // PartialSum = ((5 * NclkPeriod) + MemClkPeriod) + 520ps)*MemClkFrequency - tCWL - - // CmdSetup - PtrSeparation - 1. (Ontario) - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - PartialSum2x = NBPtr->FreqChangeParam->NclkPeriodMul2x * NclkPeriod; - PartialSum2x += NBPtr->FreqChangeParam->MemClkPeriodMul2x * MemClkPeriod; - PartialSum2x += 520 * 2; - - // PtrSeparation = ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16)/2 + RdPtrInitRmdr - // If (D18F2x[1,0]94[MemClkFreq] >= 800 MHz) - // then RdPtrInitRmdr = (((4.5 * MemClkPeriod) - 990ps) MOD MemClkPeriod)/MemClkPeriod - // else RdPtrInitRmdr = (((4.5 * MemClkPeriod) - 1466ps) MOD MemClkPeriod)/MemClkPeriod - TDataProp = (NBPtr->DCTPtr->Timings.Speed >= DDR1600_FREQUENCY) ? - NBPtr->FreqChangeParam->TDataProp800orHigher : NBPtr->FreqChangeParam->TDataPropLower800; - RdPtrInitRmdr2x = ((NBPtr->FreqChangeParam->SyncTimeMul4x * MemClkPeriod) / 2) - 2 * (TDataProp + 520); - RdPtrInitRmdr2x %= MemClkPeriod; - PartialSum2x -= ((16 + RdPtrInitMin - RdPtrInit) % 16) * MemClkPeriod + RdPtrInitRmdr2x; - - // Convert PartialSum2x to PCLK - PartialSum2x = (PartialSum2x + MemClkPeriod - 1) / MemClkPeriod; // round-up here - PartialSum2x -= 2 * (MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); - if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) { - PartialSum2x -= 1; - } else { - PartialSum2x -= 2; - } - PartialSum2x -= 2; - - // If PartialSumSlotN is positive: - // DataTxFifoSchedDlySlotN=CEIL(PartialSumSlotN). - // DataTxFifoSchedDlyNegSlotN=0. - // Else if PartialSumSlotN is negative: - // DataTxFifoSchedDlySlotN=ABS(CEIL(PartialSumSlotN*MemClkPeriod/NclkPeriod)). - // DataTxFifoSchedDlyNegSlotN=1. - for (i = 0; i < 2; i++) { - PartialSumSlotI2x = PartialSum2x; - SlowMode = (UINT8) MemNGetBitFieldNb (NBPtr, BFSlowAccessMode); - if ((i == 0) && (SlowMode == 0)) { - PartialSumSlotI2x += 2; - } - if (NBPtr->IsSupported[SchedDlySlot1Extra] && (i == 1) && (SlowMode != 0)) { - PartialSumSlotI2x -= 2; - } - if (PartialSumSlotI2x > 0) { - MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 0); - MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, (PartialSumSlotI2x + 1) / 2); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: %d\n", i, (PartialSumSlotI2x + 1) / 2); - } else { - MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 1); - PartialSumSlotI2x = ((-PartialSumSlotI2x) * MemClkPeriod) / (2 * NclkPeriod); - MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, PartialSumSlotI2x); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: -%d\n", i, PartialSumSlotI2x); - } - } - - // Set ProcOdtAdv - if ((NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) && - ((!(NBPtr->IsSupported[EnProcOdtAdvForUDIMM])) || (NBPtr->ChannelPtr->SODimmPresent != 0))) { - MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0); - } else { - MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000); - } - } - } - - MemFInitTableDrive (NBPtr, MTAfterNbPstateChange); - if (NBPtr->NbFreqChgState == 2) { - MemNSetBitFieldNb (NBPtr, BFNbPsDbgEn, 0); - MemNSetBitFieldNb (NBPtr, BFNbPsCsrAccSel, 0); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the total of sync components for Max Read Latency calculation - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Total in ps - */ - -UINT32 -MemNTotalSyncComponentsClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 P; - UINT32 T; - UINT8 RdPtrInitMin; - UINT8 RdPtrInit; - UINT32 AddrTmgCtl; - UINT8 DbeGskMemClkAlignMode; - UINT32 MemClkPeriod; - - // P = P + ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16) - RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667; - RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit); - P = (16 + RdPtrInitMin - RdPtrInit) % 16; - - // IF (AddrCmdSetup != CkeSetup) THEN P = P + 1 - AddrTmgCtl = MemNGetBitFieldNb (NBPtr, BFAddrTmgControl); - if (((AddrTmgCtl >> 16) & 0x20) != (AddrTmgCtl & 0x20)) { - P += 1; - } - - // IF (DbeGskMemClkAlignMode==01b || (DbeGskMemClkAlignMode==00b && !(AddrCmdSetup==CsOdtSetup==CkeSetup))) - // THEN P = P + 1 - DbeGskMemClkAlignMode = (UINT8) MemNGetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode); - if ((DbeGskMemClkAlignMode == 1) || ((DbeGskMemClkAlignMode == 0) && - !((((AddrTmgCtl >> 16) & 0x20) == (AddrTmgCtl & 0x20)) && (((AddrTmgCtl >> 8) & 0x20) == (AddrTmgCtl & 0x20))))) { - P += 1; - } - - // IF (SlowAccessMode==1) THEN P = P + 2 - if (MemNGetBitFieldNb (NBPtr, BFSlowAccessMode) == 1) { - P += 2; - } - - // P = P + 2 - P += 2; - T = 0; - - // If (AddrCmdSetup==0 && CsOdtSetup==0 && CkeSetup==0) - // then P = P + 1 - // else P = P + 2 - if ((AddrTmgCtl & 0x0202020) == 0) { - P += 1; - } else { - P += 2; - } - - // P = P + (2 * (D18F2x[1,0]88[Tcl] clocks - 1)) - P += 2 * (NBPtr->DCTPtr->Timings.CasL - 1); - - // If (DisCutThroughMode==0) - // then P = P + 3 - // else P = P + 7 - if (MemNGetBitFieldNb (NBPtr, BFDisCutThroughMode) == 0) { - P += 3; - } else { - P += 7; - } - - MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; - return (((P * MemClkPeriod + 1) / 2) + T); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets up phy power saving for client NB - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNPhyPowerSavingClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyU] = 1b. - // 5. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyL] = 1b. - // 6. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[7:4] = 1010b. - MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13Bit0to7, 0xA3); - // 7. Program D18F2x[1,0]9C_x0D0F_812F[7, 5, 0] = {1b, 1b, 1b} to disable unused PAR and A[17:16] pins. - MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 0xA1); - // 8. Program D18F2x[1,0]9C_x0D0F_C000[LowPowerDrvStrengthEn] = 1. - if (!NBPtr->FamilySpecificHook[DisLowPwrDrvStr] (NBPtr, NULL)) { - MemNSetBitFieldNb (NBPtr, BFReserved00C, 0x100); - } - // 9. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]10[EnRxPadStandby]= IF (D18F2x[1,0]94[MemClkFreq] <= - // 800 MHz) THEN 1 ELSE 0 ENDIF. - MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0); - // 10. Program D18F2x[1,0]9C_x0000_000D as follows: - // TxMaxDurDllNoLock/RxMaxDurDllNoLock = 7h. - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 7); - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 7); - // TxCPUpdPeriod/RxCPUpdPeriod = 011b. - MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 3); - MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 3); - // TxDLLWakeupTime/RxDLLWakeupTime = 11b. - MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3); - MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3); - - IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets up phy power saving for UNB - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNPhyPowerSavingUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 MixedX4AndX8Dimms; - - // 4. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyU] = 1b. - // 5. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyL] = 1b. - MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 3); - // 6. D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][RxDqsUDllPowerDown] = (D18F2x90_dct[1:0][X4Dimm]!=0). - MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, MemNGetBitFieldNb (NBPtr, BFX4Dimm) == 0 ? (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x80) : (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) & 0xFF7F)); - // 7. D18F2x9C_x0D0F_812F_dct[1:0][PARTri] = ~D18F2x90_dct[1:0][ParEn]. - MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFParEn) == 0 ? (MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 1) : (MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) & 0xFFFE)); - // 8. D18F2x9C_x0D0F_812F_dct[1:0][Add17Tri, Add16Tri] = {1b, 1b} - MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 0xA0); - // 9. IF (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz && ~(mixed channel of x4 and x8 DIMMs)) THEN - // Program D18F2x9C_x0D0F_0[F,8:0]10_dct[1:0][EnRxPadStandby] = 1. - // ELSE - // Program D18F2x9C_x0D0F_0[F,8:0]10_dct[1:0][EnRxPadStandby] = 0. - // ENDIF. - MixedX4AndX8Dimms = NBPtr->DCTPtr->Timings.Dimmx4Present != 0 && NBPtr->DCTPtr->Timings.Dimmx8Present != 0; - MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) && !MixedX4AndX8Dimms ? 0x1000 : 0); - // 10. IF (~(mixed channel of x4 and x8 DIMMs)) THEN - if (MixedX4AndX8Dimms == FALSE) { - // Program D18F2x9C_x0000_000D_dct[1:0] as follows: - // TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h. - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 7); - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 7); - // TxCPUpdPeriod = RxCPUpdPeriod = 011b. - MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 3); - MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 3); - // TxDLLWakeupTime = RxDLLWakeupTime = 11b. - MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3); - MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3); - } else { - // ELSE - // Program D18F2x9C_x0000_000D_dct[1:0][TxMaxDurDllNoLock, RxMaxDurDllNoLock, TxCPUpdPeriod, - // RxCPUpdPeriod, TxDLLWakeupTime, RxDLLWakeupTime] = {0, 0, 0, 0, 0, 0}. - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0); - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0); - MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 0); - MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 0); - MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 0); - MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 0); - } - // 11. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][PwrDn] to disable unused ECC byte lane. - if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) { - if (!NBPtr->MCTPtr->Status[SbEccDimms]) { - MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010); - } - } - - // 12. Program D18F2x9C_x0D0F_0[F,8:0]04_dct[1:0][TriDM] = IF (LRDIMM & (D18F2x90_dct[1:0][X4Dimm] == 0)) THEN 1 ELSE 0. - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - MemNSetBitFieldNb (NBPtr, BFDataByteDMConf, (MemNGetBitFieldNb (NBPtr, BFX4Dimm) == 0) ? 0x2000 : 0); - } - - IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function overrides the ASR and SRT value in MRS command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNSetASRSRTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 MrsAddress; - UINT8 Dimm; - UINT8 *SpdBufferPtr; - - // Look for MR2 - if (NBPtr->GetBitField (NBPtr, BFMrsBank) == 2) { - MrsAddress = NBPtr->GetBitField (NBPtr, BFMrsAddress); - // Clear A6(ASR) and A7(SRT) - MrsAddress &= (UINT32) ~0xC0; - Dimm = (UINT8) (NBPtr->GetBitField (NBPtr, BFMrsChipSel) >> 1); - // Make sure we access SPD of the second logical dimm of QR dimm correctly - if ((Dimm >= 2) && ((NBPtr->ChannelPtr->DimmQrPresent & (UINT8) (1 << Dimm)) != 0)) { - Dimm -= 2; - } - if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, Dimm)) { - // Bit 2 is ASR - if (SpdBufferPtr[THERMAL_OPT] & 0x4) { - // when ASR is 1, set SRT to 0 - MrsAddress |= 0x40; - } else { - // Set SRT based on bit on of thermal byte - MrsAddress |= ((SpdBufferPtr[THERMAL_OPT] & 1) << 7); - } - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function changes NB frequency as below: - * NBP0-DDR800 -> NBP0-DDR1066 -> ... -> NBP0-DDRTarget -> NBP1-DDRTarget -> NBP0-DDRTarget - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemNChangeNbFrequencyNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BOOLEAN Status; - - Status = FALSE; - - // State machine to change NB frequency and NB Pstate - switch (NBPtr->NbFreqChgState) { - case 0: - // Starting up by not changing NB P state, but only updating NB frequency based on current MemClk frequency - Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); - ASSERT (Status); - - if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { - // When MemClk has been ramped up to its max, transition to next state, which changes NBPstate to P1 - NBPtr->NbFreqChgState = 1; - IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, NBPtr, &(NBPtr->MemPtr->StdHeader)); - } - break; - - case 1: - // Clear ForceCasToSlot0 after MaxRdLatency training is completed for NB-P0 - MemNBrdcstSetNb (NBPtr, BFForceCasToSlot0, 0); - - // Next state would be to change NBPstate back to P0 - NBPtr->NbFreqChgState = 2; - - // Update NB freq dependent registers - NBPtr->ProgramNbPsDependentRegs (NBPtr); - - // Change NB P-State to NBP1 for MaxRdLat training - if (NBPtr->ChangeNbFrequencyWrap (NBPtr, 1)) { - // Enable cut through mode for NB P1 - MemNBrdcstSetNb (NBPtr, BFDisCutThroughMode, 0); - - // Return TRUE to repeat MaxRdLat training - Status = TRUE; - - } else { - // If transition to NB-P1 fails, transition to exit state machine - NBPtr->NbFreqChgState = 3; - } - break; - - case 2: - // Clear ForceCasToSlot0 after MaxRdLatency training is completed for NB-P1 - MemNBrdcstSetNb (NBPtr, BFForceCasToSlot0, 0); - - // Change NB P-State back to NBP0 - Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); - ASSERT (Status); - - // Return FALSE to get out of MaxRdLat training loop - Status = FALSE; - - // Exit state machine - NBPtr->NbFreqChgState = 3; - break; - - default: - break; - } - - return Status; -} - -/*----------------------------------------------------------------------------- - * - * - * This function programs registers before phy fence training for CNB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNBeforePhyFenceTrainingClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign=0\n"); - MemNBrdcstSetNb (NBPtr, BFDbeGskMemClkAlignMode, 0); - - IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for both DCTs\n"); - MemNBrdcstSetNb (NBPtr, BFEnDramInit, 1); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function changes NB frequency foras below: - * NBP0-DDR800 -> NBP0-DDR1066 -> ... -> NBP0-DDRTarget -> NBP1-DDRTarget -> NBP2-DDRTarget -> NBP3-DDRTarget -> NBP0-DDRTarget - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemNChangeNbFrequencyUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BOOLEAN Status; - - Status = FALSE; - - // State machine to change NB frequency and NB Pstate - switch (NBPtr->NbFreqChgState) { - case 0: - // Do not change NB Pstate, just to save initial NB Pstate value - Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); - if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { - // When MemClk has been ramped up to its max, transition to next state, which changes NBPstate to P1 - NBPtr->NbFreqChgState = 1; - IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, NBPtr, &(NBPtr->MemPtr->StdHeader)); - } - break; - - case 1: - case 2: - case 3: - // Change NB P-State to NBP1 for MaxRdLat training - if (NBPtr->ChangeNbFrequencyWrap (NBPtr, NBPtr->NbFreqChgState)) { - // Next state is to try all NBPstates - NBPtr->NbFreqChgState++; - - // Return TRUE to repeat MaxRdLat training - Status = TRUE; - } else { - // If transition to any NBPs fails, transition to exit state machine - NBPtr->NbFreqChgState = 4; - } - break; - - case 4: - // Change NB P-State back to NBP0 - Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0); - ASSERT (Status); - - // Return FALSE to get out of MaxRdLat training loop - Status = FALSE; - - // Exit state machine - NBPtr->NbFreqChgState = 5; - break; - - default: - break; - } - - return Status; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets "Dram Term" value from data structure - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSel - Targeted chipsel - * - * @return Dram Term value - */ -UINT8 -MemNGetDramTermNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSel - ) -{ - UINT8 DramTerm; - - if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT16) (1 << (ChipSel >> 1)))) != 0) { - DramTerm = NBPtr->PsPtr->QR_DramTerm; - } else { - DramTerm = NBPtr->PsPtr->DramTerm; - } - - return DramTerm; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets "Dram Term" value from data structure for Unb - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSel - Targeted chipsel - * - * @return Dram Term value - */ -UINT8 -MemNGetDramTermTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSel - ) -{ - UINT8 RttNom; - RttNom = NBPtr->PsPtr->RttNom[ChipSel]; - IDS_OPTION_HOOK (IDS_MEM_DRAM_TERM, &RttNom, &NBPtr->MemPtr->StdHeader); - return RttNom; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets "Dynamic Dram Term" value from data structure - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSel - Targeted chipsel - * - * @return Dynamic Dram Term value - */ -UINT8 -MemNGetDynDramTermNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSel - ) -{ - return (NBPtr->PsPtr->DynamicDramTerm); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets "Dynamic Dram Term" value from data structure - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSel - Targeted chipsel - * - * @return Dynamic Dram Term value - */ -UINT8 -MemNGetDynDramTermTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSel - ) -{ - UINT8 RttWr; - RttWr = NBPtr->PsPtr->RttWr[ChipSel]; - IDS_OPTION_HOOK (IDS_MEM_DYN_DRAM_TERM, &RttWr, &NBPtr->MemPtr->StdHeader); - return RttWr; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns MR0[CL] value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[CL] value - */ -UINT32 -MemNGetMR0CLNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Tcl; - UINT32 Value32; - - Tcl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcl); - Value32 = (UINT32) ((Tcl < 8) ? (Tcl << 4) : (((Tcl - 8) << 4) | 4)); - - return Value32; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns MR0[WR] value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[WR] value - */ -UINT32 -MemNGetMR0WRNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 Value32; - - Value32 = MemNGetBitFieldNb (NBPtr, BFTwrDDR3) << 9; - - return Value32; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns MR0[WR] value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[WR] value - */ -UINT32 -MemNGetMR0WRTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return (UINT32) (NBPtr->PsPtr->MR0WR << 9); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns MR2[CWL] value - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[CWL] value - */ -UINT32 -MemNGetMR2CWLNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 Value32; - - Value32 = MemNGetBitFieldNb (NBPtr, BFTcwl) << 3; - - return Value32; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns MR2[CWL] value for UNB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[CWL] value - */ -UINT32 -MemNGetMR2CWLUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 Value32; - - Value32 = (MemNGetBitFieldNb (NBPtr, BFTcwl) - 5) << 3; - - return Value32; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets Txp and Txpdll - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return none - */ -VOID -MemNSetTxpNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT8 Txp[] = {0xFF, 0xFF, 3, 3, 4, 4, 5, 6, 7}; - CONST UINT8 Txpdll[] = {0xFF, 0xFF, 0xA, 0xA, 0xD, 0x10, 0x14, 0x17, 0x1A}; - UINT8 i; - UINT8 TxpVal; - UINT8 TxpdllVal; - UINT16 Speed; - - Speed = NBPtr->DCTPtr->Timings.Speed; - i = (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133)); - ASSERT (i < sizeof (Txp)); - ASSERT (i < sizeof (Txpdll)); - - TxpdllVal = Txpdll[i]; - - if ((NBPtr->MCTPtr->Status[SbLrdimms] || NBPtr->MCTPtr->Status[SbRegistered]) && - ((NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY)) && - (NBPtr->RefPtr->DDR3Voltage == VOLT1_25)) { - TxpVal = 4; - } else { - TxpVal = Txp[i]; - } - - if (TxpVal != 0xFF) { - MemNSetBitFieldNb (NBPtr, BFTxp, TxpVal); - } - if (TxpdllVal != 0xFF) { - NBPtr->FamilySpecificHook[AdjustTxpdll] (NBPtr, &TxpdllVal); - MemNSetBitFieldNb (NBPtr, BFTxpdll, TxpdllVal); - } -} - -/*----------------------------------------------------------------------------- - * - * - * This function adjust value of Txpdll to encoded value. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNAdjustTxpdllClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - *(UINT8 *) OptParam -= 10; - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is a wrapper to handle or switch NB Pstate for UNB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *NBPstate - NB Pstate - * - * @return TRUE - Succeed - * @return FALSE - Fail - */ - -BOOLEAN -MemNChangeNbFrequencyWrapUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 NBPstate - ) -{ - UINT8 TargetNbPs; - UINT32 FreqNumeratorInMHz; - UINT32 FreqDivisor; - UINT32 VoltageInuV; - UINT8 NbPstateMaxVal; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - if (NBPtr->NbFreqChgState == 0) { - // While in state 0, keep NB Pstate at the highest supported - TargetNbPs = 0; - if (NBPtr->NbPsCtlReg == 0) { - // Save NbPsCtl register on the first run - NBPtr->NbPsCtlReg = MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg); - } else { - // Do not need to switch NB Pstate again if it is already at highest - return TRUE; - } - } else if (NBPtr->NbFreqChgState < 4) { - // While in other states, go to the next lower NB Pstate - TargetNbPs = (UINT8) MemNGetBitFieldNb (NBPtr, BFCurNbPstate) + 1; - } else { - // When done with training, release NB Pstate force by restoring NbPsCtl register - NBPtr->FamilySpecificHook[ReleaseNbPstate] (NBPtr, NBPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\tRelease NB Pstate force\n"); - return TRUE; - } - - // Make sure target NB Pstate is enabled, else find next enabled NB Pstate - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); - for (; TargetNbPs < 4; TargetNbPs++) { - if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, - NBPtr->MemPtr->PlatFormConfig, - &NBPtr->PciAddr, - (UINT32) TargetNbPs, - &FreqNumeratorInMHz, - &FreqDivisor, - &VoltageInuV, - &(NBPtr->MemPtr->StdHeader))) { - // Record NCLK speed - NBPtr->NBClkFreq = FreqNumeratorInMHz / FreqDivisor; - break; - } - } - - if (TargetNbPs < 4) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tNB P%d: %dMHz\n", TargetNbPs, NBPtr->NBClkFreq); - - // 1.Program the configuration registers which contain multiple internal copies for each NB P-state. See - // D18F1x10C[NbPsSel]. - MemNSetBitFieldNb (NBPtr, BFNbPsSel, TargetNbPs); - - // Check to see if NB P-states have been disabled. @todo This should only be needed for - // bring up, but must be included in any releases that occur before NB P-state operation - // has been debugged/fixed. - if ((NBPtr->NbPsCtlReg & 0x00000003) != 0) { - // Set up RdPtrInit before transit to target NBPstate - if (TargetNbPs > 0) { - NBPtr->ProgramNbPsDependentRegs (NBPtr); - } - // 2.Program D18F5x170 to transition the NB P-state: - // NbPstateLo = NbPstateMaxVal. (HW requires an intermediate transition to low) - // SwNbPstateLoDis = NbPstateDisOnP0 = NbPstateThreshold = 0. - NbPstateMaxVal = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateMaxVal); - MemNSetBitFieldNb (NBPtr, BFNbPstateLo, NbPstateMaxVal); - MemNSetBitFieldNb (NBPtr, BFNbPstateCtlReg, MemNGetBitFieldNb (NBPtr, BFNbPstateCtlReg) & 0xFFFF91FF); - - // 3.Wait for D18F5x174[CurNbPstate] to equal NbPstateLo. - MemNPollBitFieldNb (NBPtr, BFCurNbPstate, NbPstateMaxVal, PCI_ACCESS_TIMEOUT, TRUE); - - // 4.Program D18F5x170 to force the NB P-state: - // NbPstateHi = target NB P-state. - // SwNbPstateLoDis = 1 (triggers the transition) - MemNSetBitFieldNb (NBPtr, BFNbPstateHi, TargetNbPs); - MemNSetBitFieldNb (NBPtr, BFSwNbPstateLoDis, 1); - - // 5.Wait for D18F5x174[CurNbPstate] to equal the target NB P-state. - MemNPollBitFieldNb (NBPtr, BFCurNbPstate, TargetNbPs, PCI_ACCESS_TIMEOUT, TRUE); - } - - // When NB frequency change succeeds, TSC rate may have changed. - // We need to update TSC rate - FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); - } else { - // Cannot find a supported NB Pstate to switch to - // Release NB Pstate force by restoring NbPsCtl register - NBPtr->FamilySpecificHook[ReleaseNbPstate] (NBPtr, NBPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\tRelease NB Pstate force\n"); - return FALSE; - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sends an MRS command for Unb - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSendMrsCmdUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSetASRSRTNb (NBPtr); - MemNSwapBitsUnb (NBPtr); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %05x\n", - (MemNGetBitFieldNb (NBPtr, BFMrsChipSel) & 0x7), - (MemNGetBitFieldNb (NBPtr, BFMrsBank) & 0x7), - (MemNGetBitFieldNb (NBPtr, BFMrsAddress) & 0x3FFFF)); - - // 1.Set SendMrsCmd=1 - MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); - - // 2.Wait for SendMrsCmd=0 - MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns MR0[CL] value with table driven support - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return MR0[CL] value - */ -UINT32 -MemNGetMR0CLTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return (UINT32) ((NBPtr->PsPtr->MR0CL31 << 4) | (NBPtr->PsPtr->MR0CL0 << 2)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function performs MaxRdLat training for slot 1 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] TestAddrRJ16 - Test address - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNSlot1MaxRdLatTrainClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *TestAddrRJ16 - ) -{ - UINT8 DummyBuffer[8]; - UINT16 MaxLatDly; - UINT8 i; - - // Perform slot1 specific training: - // A.Program D18F2x[1,0]78[SlotSel]=1. Force read CAS to fifo slot1 for training. - // B.Program D18F2x[1,0]78[MaxRdLatency] = TrainedMaxRdLatency. Set to last slot0 value that passed. - // C.Read the DIMM test addresses. - // D.Compare the values read against the pattern written. - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tTrain Slot 1: \n"); - MemNSetBitFieldNb (NBPtr, BFSlotSel, 1); - - MaxLatDly = (UINT16) (MemNGetBitFieldNb (NBPtr, BFMaxLatency) + 1); // Add 1 to get back to the last passing value - MemNSetBitFieldNb (NBPtr, BFMaxLatency, MaxLatDly); - - for (i = 0; i < 100; i++) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", MaxLatDly); - - NBPtr->ReadPattern (NBPtr, DummyBuffer, *(UINT32*)TestAddrRJ16, 6); - - if (NBPtr->CompareTestPattern (NBPtr, DummyBuffer, DummyBuffer, 6 * 64) == 0xFFFF) { - IDS_HDT_CONSOLE (MEM_FLOW, " P"); - break; - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - - if (i < 100) { - MemNSetBitFieldNb (NBPtr, BFSlot1ExtraClkEn, 0); - } else { - MemNSetBitFieldNb (NBPtr, BFSlot1ExtraClkEn, 1); - } - - MemNSetBitFieldNb (NBPtr, BFMaxSkipErrTrain, 0); - - return TRUE; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs dram power management timing related registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return none - * ---------------------------------------------------------------------------- - */ -VOID -MemNDramPowerMngTimingNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - STATIC CONST UINT8 Tckesr[] = {4, 4, 5, 5, 6, 7, 2, 2}; - UINT8 Tck; - - // These timings are based on DDR3 spec - // Tcksrx = max(5 nCK, 10 ns) - Tck = (UINT8) MAX (5, (MemUnsToMemClk (NBPtr->DCTPtr->Timings.Speed, 10))); - MemNSetBitFieldNb (NBPtr, BFTcksrx, MIN (0xE, MAX (Tck, 2))); - - // Tcksre = max(5 nCK, 10 ns) - MemNSetBitFieldNb (NBPtr, BFTcksre, MIN (0x27, MAX (Tck, 5))); - - // Tckesr = tCKE(min) + 1 nCK - // tCKE(min) - // DDR-800 7,5ns = 3nCk max(3nCK, 7.5ns) + 1 = 3nCK + 1nCK = 4nCK - // DDR-1066 5.625ns = 3nCK max(3nCK, 5.625ns) + 1 = 3nCL + 1nCK = 4nCK - // DDR-1333 5.625ns = 4nCK max(3nCK, 4nCK) + 1 = 4nCK + 1nCK = 5nCK - // DDR-1600 5ns = 4nCK max(3nCK, 4nCK) + 1 = 4nCK + 1nCK = 5nCK - // DDR-1866 5ns = 5nCK max(3nCK, 5nCK) + 1 = 5nCK + 1nCK = 6nCK - // DDR-2133 5ns = 6nCK max(3nCK, 6nCK) + 1 = 6nCK + 1nCK = 7nCK - MemNSetBitFieldNb (NBPtr, BFTckesr, Tckesr[(NBPtr->DCTPtr->Timings.Speed / 133) - 3]); - - // Tpd = tCKE(min) - MemNSetBitFieldNb (NBPtr, BFTpd, Tckesr[(NBPtr->DCTPtr->Timings.Speed / 133) - 3] - 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * The function resets Rcv Fifo - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dummy - Dummy parameter - * - */ - -VOID -MemTResetRcvFifoUnb ( - IN OUT struct _MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dummy - ) -{ - // Program D18F2x9C_x0000_0050_dct[1:0]=00000000h - MemNSetBitFieldNb (TechPtr->NBPtr, BFRstRcvFifo, 0); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnfeat.c deleted file mode 100644 index 0a58085b79..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnfeat.c +++ /dev/null @@ -1,1737 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnfeat.c - * - * Common Northbridge features - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "PlatformMemoryConfiguration.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_MNFEAT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define MAX_CL_CONT_READ 32 -#define MAX_CL_CONT_WRITE 32 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemNContWritePatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -STATIC -MemNContReadPatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -STATIC -MemNGenHwRcvEnReadsNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ); - -UINT16 -STATIC -MemNCompareTestPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ); - -UINT16 -STATIC -MemNInsDlyCompareTestPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ); - -VOID -STATIC -MemNContWritePatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -STATIC -MemNContReadPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -STATIC -MemNGenHwRcvEnReadsClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ); - -BOOLEAN -STATIC -MemNBeforeMemClrClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *UnUsed - ); - -VOID -STATIC -MemNGenHwRcvEnReadsUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ); - -VOID -STATIC -MemNContReadPatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -STATIC -MemNContWritePatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -STATIC -MemNEnableInfiniteWritePatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemNDisableInfiniteWritePatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitCPGNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitDqsTrainRcvrEnHwNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNDisableDqsTrainRcvrEnHwNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitCPGClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitCPGUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function assigns read/write function pointers to CPG read/write modules. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNInitCPGNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->WritePattern = MemNContWritePatternNb; - NBPtr->ReadPattern = MemNContReadPatternNb; - NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsNb; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes member functions of HW Rx En Training. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitDqsTrainRcvrEnHwNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->MemNPrepareRcvrEnDlySeed = MemNPrepareRcvrEnDlySeedNb; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function disables member functions of Hw Rx En Training. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNDisableDqsTrainRcvrEnHwNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->MemNPrepareRcvrEnDlySeed = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function writes 9 or 18 cache lines continuously using GH CPG engine - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Pattern - Array of bytes that will be written to DRAM - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ -VOID -STATIC -MemNContWritePatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - UINT16 ClDiff; - if (ClCount > MAX_CL_CONT_WRITE) { - ClDiff = ClCount - MAX_CL_CONT_WRITE; - ClCount = MAX_CL_CONT_WRITE; - } else { - ClDiff = 0; - } - - // Set F2x11C[MctWrLimit] to desired number of cachelines in the burst. - MemNSetBitFieldNb (NBPtr, BFMctWrLimit, MAX_CL_CONT_WRITE - ClCount); - - // Issue the stream of writes. When F2x11C[MctWrLimit] is reached (or when F2x11C[FlushWr] is set - // again), all the writes are written to DRAM. - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUWriteCachelines (Address, Pattern, ClCount); - - // Flush out prior writes by setting F2x11C[FlushWr]. - MemNSetBitFieldNb (NBPtr, BFFlushWr, 1); - // Wait for F2x11C[FlushWr] to clear, indicating prior writes have been flushed. - while (MemNGetBitFieldNb (NBPtr, BFFlushWr) != 0) {} - - // Set F2x11C[MctWrLimit] to 1Fh to disable write bursting. - MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 0x1F); - - if (ClDiff > 0) { - MemNContWritePatternNb (NBPtr, Address + (MAX_CL_CONT_WRITE * 64), Pattern + (MAX_CL_CONT_WRITE * 64), ClDiff); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function reads 9 or 18 cache lines continuously using GH CPG engine - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -STATIC -MemNContReadPatternNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - BOOLEAN DisAutoRefresh; - UINT16 ClDiff; - if (ClCount > MAX_CL_CONT_READ) { - ClDiff = ClCount - MAX_CL_CONT_READ; - ClCount = MAX_CL_CONT_READ; - } else { - ClDiff = 0; - } - - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - - // 1. BIOS ensures that the only accesses outstanding to the MCT are training reads. - // 2. If F2x[1, 0]90[BurstLength32]=1, then BIOS ensures that the DCTs and DRAMs are configured for 64 - // byte bursts (8-beat burst length). This requires that BIOS issue MRS commands to the devices - // to change to an 8-beat burst length and then to restore the desired burst length after training - // is complete. - - if (MemNGetBitFieldNb (NBPtr, BFDisAutoRefresh) == 0) { - DisAutoRefresh = FALSE; - // 3. BIOS programs F2x[1, 0]90[ForceAutoPchg] = 0 and F2x[1, 0]8C[DisAutoRefresh] = 1. - // 4. If necessary, BIOS programs F2x[1, 0]78[EarlyArbEn] = 1 at this time. See register description. - MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); - // MemNSetBitFieldNb (NBPtr, BFForceAutoPchg, 0); // ForceAutoPchg is 0 by default. - MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); - } else { - DisAutoRefresh = TRUE; - } - - MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0); - - // 5. BIOS sets F2x11C[MctPrefReqLimit] to the number of training reads (Ntrain) it wishes to generate in the - // training sequence. - MemNSetBitFieldNb (NBPtr, BFMctPrefReqLimit, ClCount - 1); - - // 6. BIOS sets F2x11C[PrefDramTrainMode] bit. - // 7. The act of setting F2x11C[PrefDramTrainMode] causes the MCT to flush out the prefetch stride predictor - // table (removing any existing prefetch stride patterns). - MemNSetBitFieldNb (NBPtr, BFPrefDramTrainMode, 1); - - // 8. BIOS issues an SFENCE (or other serializing instruction) to ensure that the prior write completes. - // 9. For revision C and earlier processors, BIOS generates two training reads. For revision D processors BIOS - // generates three training reads. Three are required to detect the stride with DCQ buddy enabled. These must - // be to consecutive cache lines (i.e. 64 bytes apart) and must not cross a naturally aligned 4 Kbyte boundary. - // 10. These reads set up a stride pattern which is detected by the prefetcher. The prefetcher then continues to - // issue prefetches until F2x11C[MctPrefReqLimit] is reached, at which point the MCT clears - // F2x11C[PrefDramTrainMode]. - MemUDummyCLRead (Address); - MemUDummyCLRead (Address + 0x40); - if (NBPtr->IsSupported[CheckDummyCLRead]) { - MemUDummyCLRead (Address + 0x80); - } - // 11. BIOS issues the remaining (Ntrain - 2 for revisions C and earlier or Ntrain - 3 for revision D) reads after - // checking that F2x11C[PrefDramTrainMode] is cleared. These reads must be to consecutive cache lines - // (i.e., 64 bytes apart) and must not cross a naturally aligned 4KB boundary. These reads hit the prefetches - // and read the data from the prefetch buffer. - while (MemNGetBitFieldNb (NBPtr, BFPrefDramTrainMode) != 0) {} - MemUReadCachelines (Buffer, Address, ClCount); - - // 14. BIOS restores the target values for F2x[1, 0]90[ForceAutoPchg], F2x[1, 0]8C[DisAutoRefresh] and - // F2x[1, 0]90[BurstLength32]. - if (!DisAutoRefresh) { - MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0); - MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2); - } - - if (ClDiff > 0) { - MemNContReadPatternNb (NBPtr, Buffer + (MAX_CL_CONT_READ * 64), Address + (MAX_CL_CONT_READ * 64), ClDiff); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function generates a continuous burst of reads during HW RcvEn training. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Address - System Address [47:16] - * - */ -VOID -STATIC -MemNGenHwRcvEnReadsNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ) -{ - UINT8 TempBuffer[12 * 64]; - UINT8 BurstCount; - - for (BurstCount = 0; BurstCount < 10; BurstCount++) { - NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 12); - NBPtr->FlushPattern (NBPtr, Address, 12); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function writes cache lines continuously using TCB CPG engine - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Pattern - Array of bytes that will be written to DRAM - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ -VOID -STATIC -MemNContWritePatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - UINT32 PatternHash; - UINT32 *DwordPtr; - UINT16 i; - UINT16 j; - UINT16 Multiplier; - - Multiplier = 1; - - // 1. Program D18F2x1C0[WrDramTrainMode]=1. - MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 1); - - PatternHash = ClCount << 24; - for (i = 0; i < 3; i ++) { - PatternHash |= (Pattern[i * ClCount * 24 + 9] << (8 * i)); - } - if (NBPtr->CPGInit != PatternHash) { - - if (ClCount == 3) { - // Double pattern length for MaxRdLat training - Multiplier = 2; - } - - // If write training buffer has not been initialized, initialize it - // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines. - MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount * Multiplier); - - // 3. Program D18F2x1D0[WrTrainBufAddr]=000h. - MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); - - // 4. Successively write each dword of the training pattern to D18F2x1D4. - DwordPtr = (UINT32 *) Pattern; - for (j = 0; j < Multiplier; j++) { - for (i = 0; i < (ClCount * 16); i++) { - MemNSetBitFieldNb (NBPtr, BFWrTrainBufDat, DwordPtr[i]); - } - } - - NBPtr->CPGInit = PatternHash; - } - - // 5. Program D18F2x1D0[WrTrainBufAddr]=000h - MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); - - // 6. Program the DRAM training address - MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6)); - MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3); - - // 7. Program D18F2x1C0[WrTrainGo]=1. - MemNSetBitFieldNb (NBPtr, BFWrTrainGo, 1); - - // 8. Wait for D18F2x1C0[WrTrainGo]=0. - while (MemNGetBitFieldNb (NBPtr, BFWrTrainGo) != 0) {} - - // 9. Program D18F2x1C0[WrDramTrainMode]=0. - MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function reads cache lines continuously using TCB CPG engine - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -STATIC -MemNContReadPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - UINT16 Multiplier; - - Multiplier = 1; - if (ClCount == 3) { - // Double pattern length for MaxRdLat training - Multiplier = 2; - } - - // 1. Program D18F2x1C0[RdDramTrainMode]=1. - MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 1); - - // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines. - MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount * Multiplier); - - // 3. Program the DRAM training address as follows: - MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6)); - MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3); - - // 4. Program D18F2x1D0[WrTrainBufAddr]=000h - MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); - - // 5. Program D18F2x1C0[RdTrainGo]=1. - MemNSetBitFieldNb (NBPtr, BFRdTrainGo, 1); - - // 6. Wait for D18F2x1C0[RdTrainGo]=0. - while (MemNGetBitFieldNb (NBPtr, BFRdTrainGo) != 0) {} - - // 7. Read D18F2x1E8[TrainCmpSts] and D18F2x1E8[TrainCmpSts2]. - // This step will be accomplished in Compare routine. - - // 8. Program D18F2x1C0[RdDramTrainMode]=0. - MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function generates a continuous burst of reads during HW RcvEn training. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Address - System Address [47:16] - * - */ -VOID -STATIC -MemNGenHwRcvEnReadsClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ) -{ - UINT8 TempBuffer[64]; - UINT8 Count; - - for (Count = 0; Count < 3; Count++) { - NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 64); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function assigns read/write function pointers to CPG read/write modules. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNInitCPGClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->WritePattern = MemNContWritePatternClientNb; - NBPtr->ReadPattern = MemNContReadPatternClientNb; - NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsClientNb; - NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet; - NBPtr->CompareTestPattern = MemNCompareTestPatternClientNb; - NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternClientNb; - NBPtr->FamilySpecificHook[BeforeMemClr] = MemNBeforeMemClrClientNb; - NBPtr->CPGInit = 0; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function compares test pattern with data in buffer and - * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] ByteCount - Byte count - * - * @return PASS - Bitmap of results of comparison - */ - -UINT16 -STATIC -MemNCompareTestPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts)); -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function compares test pattern with data in buffer and - * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] ByteCount - Byte count - * - * @retval Bitmap of results of comparison - */ -UINT16 -STATIC -MemNInsDlyCompareTestPatternClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts2)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates RcvEn seed value for each rank - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNPrepareRcvrEnDlySeedNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - CH_DEF_STRUCT *ChannelPtr; - DIE_STRUCT *MCTPtr; - UINT16 SeedTotal; - UINT16 SeedFine; - UINT16 SeedGross; - UINT16 SeedPreGross; - UINT16 SeedTotalPreScaling; - UINT8 ByteLane; - UINT16 Speed; - UINT16 PlatEst; - UINT8 ChipSel; - UINT8 Pass; - UINT16 *PlatEstSeed; - UINT16 SeedValue[9]; - UINT16 SeedTtl[9]; - UINT16 SeedPre[9]; - - TechPtr = NBPtr->TechPtr; - MCTPtr = NBPtr->MCTPtr; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - Speed = NBPtr->DCTPtr->Timings.Speed; - SeedTotalPreScaling = 0; - ChipSel = TechPtr->ChipSel; - Pass = TechPtr->Pass; - - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - TechPtr->Bytelane = ByteLane; - if (Pass == 1) { - // Get platform override seed - PlatEstSeed = (UINT16 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_RXEN_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID, ChipSel >> 1, - &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader)); - // For Pass1, BIOS starts with the delay value obtained from the first pass of write - // levelization training that was done in DDR3 Training and add a delay value of 3Bh. - PlatEst = 0x3B; - NBPtr->FamilySpecificHook[OverrideRcvEnSeed] (NBPtr, &PlatEst); - PlatEst = ((PlatEstSeed != NULL) ? PlatEstSeed[ByteLane] : PlatEst); - SeedTotal = ChannelPtr->WrDqsDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane] + PlatEst; - SeedValue[ByteLane] = PlatEst; - } else { - // For Pass2 - // SeedTotalPreScaling = (the total delay values in D18F2x[1,0]9C_x0000_00[24:10] from pass 1 of - // DQS receiver enable training) - 20h. Subtract 1UI to get back to preamble left edge. - if (((ChipSel & 1) == 0) && NBPtr->FamilySpecificHook[TrainingNibbleZero] (NBPtr, &ChipSel)) { - // Save Seed for odd CS SeedTotalPreScaling RxEn Value - TechPtr->PrevPassRcvEnDly[ByteLane] = ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane]; - } - NBPtr->FamilySpecificHook[OverridePrevPassRcvEnDly] (NBPtr, &TechPtr->PrevPassRcvEnDly[ByteLane]); - SeedTotalPreScaling = TechPtr->PrevPassRcvEnDly[ByteLane] - 0x20; - // SeedTotal = SeedTotalPreScaling*target frequency/lowest supported frequency. - SeedTotal = (UINT16) (((UINT32) SeedTotalPreScaling * Speed) / TechPtr->PrevSpeed); - NBPtr->FamilySpecificHook[OverrideRcvEnSeedPassN] (NBPtr, &SeedTotal); - } - SeedTtl[ByteLane] = SeedTotal; - - // SeedGross = SeedTotal DIV 32. - SeedGross = SeedTotal >> 5; - // SeedFine = SeedTotal MOD 32. - SeedFine = SeedTotal & 0x1F; - // Next, determine the gross component of SeedTotal. SeedGrossPass1=SeedTotal DIV 32. - // Then, determine the fine delay component of SeedTotal. SeedFinePass1=SeedTotal MOD 32. - // Use SeedGrossPass1 to determine SeedPreGrossPass1: - - if ((SeedGross & 0x1) != 0) { - //if SeedGross is odd - SeedPreGross = 1; - } else { - //if SeedGross is even - SeedPreGross = 2; - } - // (SeedGross - SeedPreGross) - TechPtr->DiffSeedGrossSeedPreGross[ByteLane] = (SeedGross - SeedPreGross) << 5; - - //BIOS programs registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 with SeedPreGrossPass1 - //and SeedFinePass1 from the preceding steps. - - NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), (SeedPreGross << 5) | SeedFine); - SeedPre[ByteLane] = (SeedPreGross << 5) | SeedFine; - - // 202688: Program seed value to RcvEnDly also. - NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), SeedGross << 5); - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - if (Pass == 1) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedValue: "); - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedValue[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedTotal: "); - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedTtl[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t SeedPRE: "); - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedPre[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - ); - - NBPtr->FamilySpecificHook[RegAccessFence] (NBPtr, NULL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Waits specified number of MEMCLKs - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] MemClkCount - Number of MEMCLKs - * - * ---------------------------------------------------------------------------- - */ -VOID -MemNWaitXMemClksNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 MemClkCount - ) -{ - MemUWait10ns ((MemClkCount * 100 + NBPtr->DCTPtr->Timings.Speed - 1) / NBPtr->DCTPtr->Timings.Speed, NBPtr->MemPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Issues dummy TCB write read to zero out CL that is used for MemClr - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *UnUsed - unused - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemNBeforeMemClrClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *UnUsed - ) -{ - UINT8 Pattern[64]; - UINT8 i; - - for (i = 0; i < 64; i++) { - Pattern[i] = 0; - } - - MemNContWritePatternClientNb (NBPtr, 0x20, Pattern, 1); - MemNContReadPatternClientNb (NBPtr, Pattern, 0x20, 1); - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function uses the PRBS generator in the DCT to send a DDR Activate command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSelect - Chip select 0-7 - * @param[in] Bank - Bank Address 0-7 - * @param[in] RowAddress - Row Address [17:0] - * - */ - -VOID -MemNRrwActivateCmd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSelect, - IN UINT8 Bank, - IN UINT32 RowAddress - ) -{ - // Set Chip select - MemNSetBitFieldNb (NBPtr, BFCmdChipSelect, (1 << ChipSelect)); - // Set Bank Address - MemNSetBitFieldNb (NBPtr, BFCmdBank, Bank); - // Set Row Address - MemNSetBitFieldNb (NBPtr, BFCmdAddress, RowAddress); - // Send the command - MemNSetBitFieldNb (NBPtr, BFSendActCmd, 1); - // Wait for command complete - MemNPollBitFieldNb (NBPtr, BFSendActCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); - // Wait 75 MEMCLKs - NBPtr->WaitXMemClks (NBPtr, 75); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function uses the PRBS generator in the DCT to send a DDR Precharge - * or Precharge All command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] ChipSelect - Chip select 0-7 - * @param[in] Bank - Bank Address 0-7, PRECHARGE_ALL_BANKS = Precharge All - * - * - */ - -VOID -MemNRrwPrechargeCmd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ChipSelect, - IN UINT8 Bank - ) -{ - // Wait 25 MEMCLKs - NBPtr->WaitXMemClks (NBPtr, 25); - // Set Chip select - NBPtr->SetBitField (NBPtr, BFCmdChipSelect, (1 << ChipSelect)); - if (Bank == PRECHARGE_ALL_BANKS) { - // Set Row Address, bit 10 - NBPtr->SetBitField (NBPtr, BFCmdAddress, NBPtr->GetBitField (NBPtr, BFCmdAddress) | (1 << 10) ); - } else { - // Clear Row Address, bit 10 - NBPtr->SetBitField (NBPtr, BFCmdAddress, NBPtr->GetBitField (NBPtr, BFCmdAddress) & (~(1 << 10)) ); - // Set Bank Address - NBPtr->SetBitField (NBPtr, BFCmdBank, Bank); - } - // Send the command - NBPtr->SetBitField (NBPtr, BFSendPchgCmd, 1); - // Wait for command complete - NBPtr->PollBitField (NBPtr, BFSendPchgCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); - // Wait 25 MEMCLKs - NBPtr->WaitXMemClks (NBPtr, 25); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function generates a continuous burst of reads for HW RcvEn - * training using the Unified Northbridge Reliable Read/Write Engine. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Address - Unused by this function - * - */ -VOID -STATIC -MemNGenHwRcvEnReadsUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address - ) -{ - VOID *DummyPtr; - DummyPtr = NULL; - // - // Issue Stream of Reads from the Target Rank - // - NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function generates a continuous stream of reads from DRAM using the - * Unified Northbridge Reliable Read/Write Engine. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] Buffer - Unused by this function - * @param[in] Address - Unused by this function - * @param[in] ClCount - Number of cache lines to read - * - * Assumptions: - * - * - * - */ - -VOID -STATIC -MemNContReadPatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - MEM_TECH_BLOCK *TechPtr; - RRW_SETTINGS *Rrw; - UINT8 CmdTgt; - UINT8 ChipSel; - - TechPtr = NBPtr->TechPtr; - Rrw = &NBPtr->RrwSettings; - - ChipSel = TechPtr->ChipSel; - CmdTgt = Rrw->CmdTgt; - // - // Wait for RRW Engine to be ready and turn it on - // - NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1); - // - // Depending upon the Cmd Target, send Row Activate and set Chipselect - // for the Row or Rows that will be used - // - MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA); - NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel); - if (CmdTgt == CMD_TGT_AB) { - MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressB, Rrw->TgtRowAddressB); - NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, ChipSel); - } - // Set Comparison Masks - NBPtr->SetBitField (NBPtr, BFDramDqMaskLow, Rrw->CompareMaskLow); - NBPtr->SetBitField (NBPtr, BFDramDqMaskHigh, Rrw->CompareMaskHigh); - // - // If All Dimms are ECC Capable Test ECC. Otherwise, mask it off - // - NBPtr->SetBitField (NBPtr, BFDramEccMask, (NBPtr->MCTPtr->Status[SbEccDimms] == TRUE) ? Rrw->CompareMaskEcc : 0xFF); - // - // Program the PRBS Seed - // - NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed); - // - // Set the Command Count - // - NBPtr->SetBitField (NBPtr, BFCmdCount, ClCount); - // - // Program the Bubble Count and CmdStreamLen - // - NBPtr->SetBitField (NBPtr, BFReserved007, 0); - NBPtr->SetBitField (NBPtr, BFReserved008, 0); - NBPtr->SetBitField (NBPtr, BFReserved006, 1); - // - // Program the Starting Address - // - NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA); - NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA); - if (CmdTgt == CMD_TGT_AB) { - NBPtr->SetBitField (NBPtr, BFTgtBankB, Rrw->TgtBankAddressB); - NBPtr->SetBitField (NBPtr, BFTgtAddressB, Rrw->TgtColAddressB); - } - // - // Reset All Errors and Disable StopOnErr - // - NBPtr->SetBitField (NBPtr, BFResetAllErr, 1); - NBPtr->SetBitField (NBPtr, BFStopOnErr, 0); - // - // Program the CmdTarget - // - NBPtr->SetBitField (NBPtr, BFCmdTgt, CmdTgt); - // - // Set CmdType to read - // - NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_READ); - // - // Start the Commands - // - AGESA_TESTPOINT (TpProcMemContinPatternGenRead, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SetBitField (NBPtr, BFSendCmd, 1); - // - // Commands have started, wait for the reads to complete then clear the command - // - NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFSendCmd, 0); - // - // Send the Precharge All Command - // - MemNRrwPrechargeCmd (NBPtr, ChipSel, PRECHARGE_ALL_BANKS); - // - // Turn Off the RRW Engine - // - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function generates a continuous stream of writes to DRAM using the - * Unified Northbridge Reliable Read/Write Engine. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] Address - Unused by this function - * @param[in] Pattern - Unused by this function - * @param[in] ClCount - Number of cache lines to write - * - */ - -VOID -STATIC -MemNContWritePatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - MEM_TECH_BLOCK *TechPtr; - RRW_SETTINGS *Rrw; - UINT8 CmdTgt; - UINT8 ChipSel; - - TechPtr = NBPtr->TechPtr; - Rrw = &NBPtr->RrwSettings; - - ChipSel = TechPtr->ChipSel; - CmdTgt = Rrw->CmdTgt; - // - // Wait for RRW Engine to be ready and turn it on - // - NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1); - // - // Depending upon the Cmd Target, send Row Activate and set Chipselect - // for the Row or Rows that will be used - // - MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA); - NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel); - if (CmdTgt == CMD_TGT_AB) { - MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressB, Rrw->TgtRowAddressB); - NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, ChipSel); - } - // - // Program the PRBS Seed - // - NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed); - // - // Set the Command Count - // - NBPtr->SetBitField (NBPtr, BFCmdCount, ClCount); - // - // Program the Bubble Count and CmdStreamLen - // - NBPtr->SetBitField (NBPtr, BFReserved007, 0); - NBPtr->SetBitField (NBPtr, BFReserved008, 0); - NBPtr->SetBitField (NBPtr, BFReserved006, 1); - // - // Program the Starting Address - // - NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA); - NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA); - if (CmdTgt == CMD_TGT_AB) { - NBPtr->SetBitField (NBPtr, BFTgtBankB, Rrw->TgtBankAddressB); - NBPtr->SetBitField (NBPtr, BFTgtAddressB, Rrw->TgtColAddressB); - } - // - // Program the CmdTarget - // - NBPtr->SetBitField (NBPtr, BFCmdTgt, CmdTgt); - // - // Set CmdType to Write - // - NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_WRITE); - // - // Start the Commands - // - AGESA_TESTPOINT (TpProcMemContinPatternGenWrite, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SetBitField (NBPtr, BFSendCmd, 1); - // - // Commands have started, wait for the writes to complete then clear the command - // - // Wait for TestStatus = 1 and CmdSendInProg = 0. - NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFSendCmd, 0); - // - // Send the Precharge All Command - // - MemNRrwPrechargeCmd (NBPtr, ChipSel, PRECHARGE_ALL_BANKS); - // - // Turn Off the RRW Engine - // - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function checks the Error status bits for comparison results - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Not used in this implementation - * @param[in] Pattern[] - Not used in this implementation - * @param[in] ByteCount - Not used in this implementation - * - * @return PASS - Bitmap of results of comparison - */ - -UINT16 -STATIC -MemNCompareTestPatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - - - UINT16 i; - UINT16 Pass; - UINT8 ChipSel; - UINT8 ColumnCount; - UINT8* FailingBitMaskPtr; - UINT8 FailingBitMask[9]; - UINT32 NibbleErrSts; - - ChipSel = NBPtr->TechPtr->ChipSel; - ColumnCount = NBPtr->ChannelPtr->ColumnCount; - // Calculate Failing Bitmask pointer - FailingBitMaskPtr = &(NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel)]); - - // - // Get Failing bit data - // - *((UINT32*)FailingBitMask) = NBPtr->GetBitField (NBPtr, BFDQErrLow); - *((UINT32*)&FailingBitMask[4]) = NBPtr->GetBitField (NBPtr, BFDQErrHigh); - FailingBitMask[8] = (UINT8)NBPtr->GetBitField (NBPtr, BFEccErr); - - Pass = 0x0000; - // - // Get Comparison Results - Convert Nibble Masks to Byte Masks - // - NibbleErrSts = NBPtr->GetBitField (NBPtr, BFNibbleErrSts); - - for (i = 0; i < ColumnCount ; i++) { - Pass |= ((NibbleErrSts & 0x03) > 0 ) ? (1 << i) : 0; - NibbleErrSts >>= 2; - FailingBitMaskPtr[i] = FailingBitMask[i]; - } - Pass = ~Pass; - return Pass; -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function checks the Error status bits for offset comparison results - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] ByteCount - Byte count - * - * @retval Bitmap of results of comparison - */ -UINT16 -STATIC -MemNInsDlyCompareTestPatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - UINT16 i; - UINT16 Pass; - UINT8 ColumnCount; - UINT32 NibbleErr180Sts; - - ColumnCount = NBPtr->ChannelPtr->ColumnCount; - Pass = 0x0000; - // - // Get Comparison Results - Convert Nibble Masks to Byte Masks - // - NibbleErr180Sts = NBPtr->GetBitField (NBPtr, BFNibbleErr180Sts); - - for (i = 0; i < ColumnCount ; i++) { - Pass |= ((NibbleErr180Sts & 0x03) > 0 ) ? (1 << i) : 0; - NibbleErr180Sts >>= 2; - } - Pass = ~Pass; - - return Pass; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function assigns read/write function pointers to CPG read/write modules. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNInitCPGUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->WritePattern = MemNContWritePatternUnb; - NBPtr->ReadPattern = MemNContReadPatternUnb; - NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsUnb; - NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet; - NBPtr->TrainingPatternInit = (AGESA_STATUS (*) (MEM_NB_BLOCK *)) memDefRetSuccess; - NBPtr->TrainingPatternFinalize = (AGESA_STATUS (*) (MEM_NB_BLOCK *)) memDefRetSuccess; - NBPtr->CompareTestPattern = MemNCompareTestPatternUnb; - NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternUnb; - NBPtr->FamilySpecificHook[SetupHwTrainingEngine] = MemNSetupHwTrainingEngineUnb; - NBPtr->EnableInfiniteWritePattern = MemNEnableInfiniteWritePatternUnb; - NBPtr->DisableInfiniteWritePattern = MemNDisableInfiniteWritePatternUnb; - NBPtr->CPGInit = 0; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function generates a continuous stream of writes infinite writes to DRAM using the - * Unified Northbridge Reliable Read/Write Engine. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemNEnableInfiniteWritePatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 ByteLane; - UINT32 WrDatValue; - UINT32 WrDqsValue; - MEM_TECH_BLOCK *TechPtr; - RRW_SETTINGS *Rrw; - UINT8 CmdTgt; - UINT8 ChipSel; - TechPtr = NBPtr->TechPtr; - Rrw = &NBPtr->RrwSettings; - ChipSel = TechPtr->ChipSel; - CmdTgt = Rrw->CmdTgt; - - // Ensure that DisAutoRefresh and ZqCals are disabled during the use of RRWM - if (MemNGetBitFieldNb (NBPtr, BFDisAutoRefresh) == 0) { - NBPtr->OrigDisAutoRefreshState = FALSE; - MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); - MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); - } else { - NBPtr->OrigDisAutoRefreshState = TRUE; - } - - // - // Enable I/O Skew mode - // - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8) ; ByteLane++) { - //Move WrDQS settings from current DIMM to DIMM 0 - WrDqsValue = NBPtr->ChannelPtr->WrDqsDlys[(NBPtr->TechPtr->ChipSel >> 1) * NBPtr->TechPtr->DlyTableWidth () + ByteLane]; - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (0, ByteLane), (UINT16)WrDqsValue); - //Move WrDat settings from current DIMM to DIMM 0 - WrDatValue = NBPtr->ChannelPtr->WrDatDlys[(NBPtr->TechPtr->ChipSel >> 1) * NBPtr->TechPtr->DlyTableWidth () + ByteLane]; - NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (0, ByteLane), (UINT16)WrDatValue); - } - NBPtr->SetBitField (NBPtr, BFReserved00A, 0x0001); - - - // - // Enable PRBS - // - - // - // Wait for RRW Engine to be ready and turn it on - // - NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1); - // - // Depending upon the Cmd Target, send Row Activate and set Chipselect - // for the Row or Rows that will be used - // - MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA); - NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel); - // - // Program the PRBS Seed - // - NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed); - // - // Set the Command Count - // - NBPtr->SetBitField (NBPtr, BFCmdCount, 0); - // - // Program the Bubble Count and CmdStreamLen - // - NBPtr->SetBitField (NBPtr, BFReserved007, 0); - NBPtr->SetBitField (NBPtr, BFReserved008, 0); - NBPtr->SetBitField (NBPtr, BFReserved006, 1); - // - // Program the Starting Address - // - NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA); - NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA); - // - // Program the CmdTarget - // - NBPtr->SetBitField (NBPtr, BFCmdTgt, CMD_TGT_A); - // - // Set CmdType to write - // - NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_WRITE); - // - // Start the Commands - // - NBPtr->SetBitField (NBPtr, BFSendCmd, 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function disables the infinite stream of writes to DRAM using the - * Unified Northbridge Reliable Read/Write Engine. - * - * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemNDisableInfiniteWritePatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 ByteLane; - UINT32 WrDatValue; - UINT32 WrDqsValue; - // - // Disable PRBS - NBPtr->SetBitField (NBPtr, BFCmdCount, 1); - //Wait for TestStatus = 1 and CmdSendInProg = 0 - NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFSendCmd, 0); - // - // Disable I/O Skew Mode - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8) ; ByteLane++) { - //Move WrDqs settings from DIMM 0 from saved area back to register - WrDqsValue = NBPtr->ChannelPtr->WrDqsDlys[0 * NBPtr->TechPtr->DlyTableWidth () + ByteLane]; - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (0, ByteLane), (UINT16)WrDqsValue); - //Move WrDat settings from DIMM 0 from saved area back to register - WrDatValue = NBPtr->ChannelPtr->WrDatDlys[0 * NBPtr->TechPtr->DlyTableWidth () + ByteLane]; - NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (0, ByteLane), (UINT16)WrDatValue); - } - NBPtr->SetBitField (NBPtr, BFReserved00A, 0x0000); - // - // Turn Off the RRW Engine - // - MemNRrwPrechargeCmd (NBPtr, NBPtr->TechPtr->ChipSel, PRECHARGE_ALL_BANKS); - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0); - // - // Restore DisAutoRefresh and ZQCals to original state - // - if (!NBPtr->OrigDisAutoRefreshState) { - MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0); - MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2); - } - -} -/*-----------------------------------------------------------------------------*/ -/** - * - * This function checks the 180 Error status bits for RD DQS training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] ByteCount - Byte count, - * - * @retval Bitmap of results of comparison - */ -UINT32 -MemN180CompareRdDqs__PatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - return NBPtr->GetBitField (NBPtr, BFNibbleErr180Sts); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function checks the In Phase Error status bits for comparison results for RDDQS training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Not used in this implementation - * @param[in] Pattern[] - Not used in this implementation - * @param[in] ByteCount - Not used in this implementation - * - * @return PASS - Bitmap of results of comparison - */ - -UINT32 -MemNInPhaseCompareRdDqs__PatternUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT16 ByteCount - ) -{ - return NBPtr->GetBitField (NBPtr, BFNibbleErrSts); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function starts the Victim for RdDqs Training Continuous Writes - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] SeedCount - Seed count - */ -VOID -MemNStartRdDqs__VictimContinuousWritesUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 SeedCount - ) -{ - // Program the PRBS Seed - NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, NBPtr->GetPrbs__RdDqsSeed (NBPtr, SeedCount)); - // - // Enable continuous writes on the victim channels - // - // Set the Command Count - NBPtr->SetBitField (NBPtr, BFCmdCount, 256); - NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_WRITE); - NBPtr->SetBitField (NBPtr, BFSendCmd, 1); - // Wait for TestStatus = 1 and CmdSendInProg = 0. - NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFSendCmd, 0); - // - // Enable continuous reads on the victim channels - // - // Set the Command Count - ASSERT (NBPtr->MaxAggressorDimms[NBPtr->Dct] != 0); - NBPtr->SetBitField (NBPtr, BFCmdCount, (25600 / NBPtr->MaxAggressorDimms[NBPtr->Dct])); - // Reset All Errors and Disable StopOnErr - NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_READ); - NBPtr->SetBitField (NBPtr, BFSendCmd, 1); - // Wait for TestStatus = 1 and CmdSendInProg = 0 - NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE); - //} - NBPtr->SetBitField (NBPtr, BFSendCmd, 0); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function Initializes the Victim chipSelects for RdDqs Training Continuous Writes - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - */ -VOID -MemNInitializeRdDqs__VictimChipSelContinuousWritesUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, NBPtr->TechPtr->ChipSel); - NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, NBPtr->TechPtr->ChipSel); - NBPtr->SetBitField (NBPtr, BFResetAllErr, 1); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finalizes the Victim for RdDqs Training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - */ -VOID -MemNFinalizeRdDqs__VictimContinuousWritesUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 InitialCS; - UINT8 ChipSel; - InitialCS = NBPtr->TechPtr->ChipSel; - NBPtr->SetBitField (NBPtr, BFReserved003, 0); - for (ChipSel = InitialCS; ChipSel < (InitialCS + 2); ChipSel++) { - // Ensure that Odd and Even CS are trained - if ((NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16) 1 << ChipSel)) == 0) { - continue; - } - NBPtr->TechPtr->ChipSel = ChipSel; - // Send the Precharge All Command - MemNRrwPrechargeCmd (NBPtr, ChipSel, PRECHARGE_ALL_BANKS); - } - // Turn Off the RRW Engine - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function Initializes the Victim for RdDqs Training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - */ -VOID -MemNInitializeRdDqs__VictimContinuousWritesUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - RRW_SETTINGS *Rrw; - UINT8 InitialCS; - UINT8 ChipSel; - InitialCS = NBPtr->TechPtr->ChipSel; - Rrw = &NBPtr->RrwSettings; - // Program the Bubble Count and CmdStreamLen - NBPtr->SetBitField (NBPtr, BFReserved007, 32); - NBPtr->SetBitField (NBPtr, BFReserved008, 0); - NBPtr->SetBitField (NBPtr, BFReserved006, 63); - // Set Comparison Masks - NBPtr->SetBitField (NBPtr, BFDramDqMaskLow, Rrw->CompareMaskLow); - NBPtr->SetBitField (NBPtr, BFDramDqMaskHigh, Rrw->CompareMaskHigh); - // If All Dimms are ECC Capable Test ECC. Otherwise, mask it off - NBPtr->SetBitField (NBPtr, BFDramEccMask, (NBPtr->MCTPtr->Status[SbEccDimms] == TRUE) ? Rrw->CompareMaskEcc : 0xFF); - // Program the Starting Address - NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA); - NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA); - NBPtr->SetBitField (NBPtr, BFTgtBankB, Rrw->TgtBankAddressB); - NBPtr->SetBitField (NBPtr, BFTgtAddressB, Rrw->TgtColAddressB); - NBPtr->SetBitField (NBPtr, BFCmdTgt, CMD_TGT_AB); - // Wait for RRW Engine to be ready and turn it on - NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); - NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1); - for (ChipSel = InitialCS; ChipSel < (InitialCS + 2); ChipSel++) { - // Ensure that Odd and Even CS are trained - if ((NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16) 1 << ChipSel)) == 0) { - continue; - } - NBPtr->TechPtr->ChipSel = ChipSel; - // Set Chip select - MemNSetBitFieldNb (NBPtr, BFCmdChipSelect, (1 << NBPtr->TechPtr->ChipSel)); - // Set Bank Address - MemNSetBitFieldNb (NBPtr, BFCmdBank, Rrw->TgtBankAddressA); - // Set Row Address - MemNSetBitFieldNb (NBPtr, BFCmdAddress, Rrw->TgtRowAddressA); - // Send the command - MemNSetBitFieldNb (NBPtr, BFSendActCmd, 1); - // Wait for command complete - MemNPollBitFieldNb (NBPtr, BFSendActCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); - // Set Chip select - MemNSetBitFieldNb (NBPtr, BFCmdChipSelect, (1 << NBPtr->TechPtr->ChipSel)); - // Set Bank Address - MemNSetBitFieldNb (NBPtr, BFCmdBank, Rrw->TgtBankAddressB); - // Set Row Address - MemNSetBitFieldNb (NBPtr, BFCmdAddress, Rrw->TgtRowAddressB); - // Send the command - MemNSetBitFieldNb (NBPtr, BFSendActCmd, 1); - // Wait for command complete - MemNPollBitFieldNb (NBPtr, BFSendActCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); - } - NBPtr->SetBitField (NBPtr, BFReserved003, 1); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function enables continuous writes on unused channels - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *SeedCount - seed index - * - * @return Prbs Seed - * - */ - -UINT32 -MemNGetPrbs__RdDqsSeedUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 SeedCount - ) -{ - UINT32 PrbsSeed; - ASSERT (SeedCount <= (NBPtr->MaxSeedCount - 1)) - PrbsSeed = ((UINT32)0x7ea05 << SeedCount) & 0x7FFFF; - ASSERT (PrbsSeed != 0); - return PrbsSeed; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function enables/disables continuous writes on unused agressor channels - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] SeedCount - Seed count - * @param[in] TurnOnInfinite - TRUE - Enable Infinite Mode - * TurnOnInfinite - FALSE - Disable Infinite Mode - * - */ -VOID -MemNAgressorContinuousWritesUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 SeedCount, - IN BOOLEAN TurnOnInfinite - ) -{ - UINT8 CurrChipSel; - UINT8 CurrDct; - UINT8 Dct; - UINT32 Address; - UINT8 Die; - MEM_NB_BLOCK *TargetNBPtr; - BOOLEAN SkipContinuous; - CurrDct = NBPtr->Dct; - CurrChipSel = NBPtr->TechPtr->ChipSel; - SkipContinuous = FALSE; - for (Die = 0; Die < NBPtr->NodeCount; Die++) { - if (NBPtr->DieEnabled[Die]) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - // Make sure that we are not targeting current DCT, current Node - if (Die == NBPtr->Node) { - if (CurrDct == Dct) { - SkipContinuous = TRUE; - } else { - SkipContinuous = FALSE; - } - } else { - SkipContinuous = FALSE; - } - // Enable/Disable continuous on aggressors - if (SkipContinuous == FALSE) { - if (Die == NBPtr->Node) { - TargetNBPtr = NBPtr; - } else { - ASSERT (NBPtr->AdjacentDieNBPtr != NULL); - TargetNBPtr = NBPtr->AdjacentDieNBPtr; - } - // All context switched at this point - TargetNBPtr->SwitchDCT (TargetNBPtr, Dct); - if (TargetNBPtr->DCTPtr->Timings.DctMemSize != 0) { - // Set Targets for agressors - TargetNBPtr->TechPtr->ChipSel = TargetNBPtr->CurrentAggressorCSTarget[Dct]; - TargetNBPtr->GetSysAddr (TargetNBPtr, TargetNBPtr->TechPtr->ChipSel, &Address); - TargetNBPtr->RrwSettings.DataPrbsSeed = TargetNBPtr->GetPrbs__RdDqsSeed (TargetNBPtr, 0); - if (TurnOnInfinite) { - // Enable continuous writes on aggressor channels - TargetNBPtr->EnableInfiniteWritePattern (TargetNBPtr); - } else { - // Disable continous writes on aggressor channels - TargetNBPtr->DisableInfiniteWritePattern (TargetNBPtr); - // Set the next target CS for aggressor channel - if (TargetNBPtr->CurrentAggressorCSTarget[Dct] == TargetNBPtr->MaxAggressorCSEnabled[Dct]) { - TargetNBPtr->CurrentAggressorCSTarget[Dct] = TargetNBPtr->InitialAggressorCSTarget[Dct]; - } else { - TargetNBPtr->CurrentAggressorCSTarget[Dct] = TargetNBPtr->CurrentAggressorCSTarget[Dct] + TargetNBPtr->CSPerDelay (TargetNBPtr); - } - } - } - } - } - } - } - // Restore Node, DCT and ChipSel - NBPtr->TechPtr->ChipSel = CurrChipSel; - NBPtr->SwitchDCT (NBPtr, CurrDct); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnflow.c deleted file mode 100644 index c2ec0112d2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnflow.c +++ /dev/null @@ -1,333 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnflow.c - * - * Common Northbridge initializer flow for MCT and DCT - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_MNFLOW_FILECODE -/* features */ -#include "mftds.h" - -extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[]; -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemNInitDCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemNCleanupDctRegsNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemNGetPORFreqLimitTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs the MCT with initial values - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - AGESA_FATAL error did not occur (it is possible to have an Error that is not AGESA_SUCCESS) - * @return FALSE - AGESA_FATAL error occurred - */ - -BOOLEAN -MemNInitMCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 Dct; - BOOLEAN Flag; - ID_INFO CallOutIdInfo; - - TechPtr = NBPtr->TechPtr; - // Switch Tech functions for Nb - NBPtr->TechBlockSwitch (NBPtr); - // Start Memory controller initialization sequence - Flag = FALSE; - if (TechPtr->DimmPresence (TechPtr)) { - AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader)); - if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) { - AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader)); - if (TechPtr->SpdCalcWidth (TechPtr)) { - AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader)); - if (TechPtr->SpdGetTargetSpeed (TechPtr)) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - - Flag |= MemNInitDCTNb (NBPtr); - } - - if (Flag && !NBPtr->IsSupported[TwoStageDramInit] && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) { - MemFInitTableDrive (NBPtr, MTBeforeDInit); - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); - CallOutIdInfo.IdField.SocketId = NBPtr->MCTPtr->SocketId; - CallOutIdInfo.IdField.ModuleId = NBPtr->MCTPtr->DieId; - IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS on Socket %d Module %d...\n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId); - AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, NBPtr->MemPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 : - (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 : - (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999); - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); - IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader)); - NBPtr->StartupDCT (NBPtr); - } - } - } - } - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the platform specific block for families that support - * table driven form factor - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - AGESA_SUCCESS - */ - -BOOLEAN -MemNPlatformSpecificFormFactorInitTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->PsPtr->MemPDoPs = MemPPSCFlow; - NBPtr->PsPtr->MemPGetPORFreqLimit = MemNGetPORFreqLimitTblDrvNb; - NBPtr->PsPtr->MemPGetPass1Seeds = MemPGetPSCPass1Seed; - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function selects appropriate Tech functions for the NB. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNTechBlockSwitchNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - - TechPtr = NBPtr->TechPtr; - - // Specify Dimm-Byte training for Nb - MemTDimmByteTrainInit (TechPtr); - - // Filter included for RcvrEn training. - // note: If you'd like to drop the filter, you have to comment out these two lines together. - TechPtr->MaxFilterDly = MAX_FILTER_DLY_DDR3; - TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByteFilter; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs the DCT with initial values - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Error did not occur - * @return FALSE - Error occurred - */ - -BOOLEAN -STATIC -MemNInitDCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - TechPtr = NBPtr->TechPtr; - TechPtr->SetDramMode (TechPtr); - - if (!NBPtr->MCTPtr->GangedMode || (NBPtr->MCTPtr->Dct == 0)) { - if (NBPtr->DCTPtr->Timings.DctDimmValid == 0) { - NBPtr->DisableDCT (NBPtr); - } else { - MemNCleanupDctRegsNb (NBPtr); - if (TechPtr->AutoCycTiming (TechPtr)) { - if (TechPtr->SpdSetBanks (TechPtr)) { - if (NBPtr->StitchMemory (NBPtr)) { - // if all dimms on a DCT are disabled, the DCT needs to be disabled. - if (NBPtr->DCTPtr->Timings.CsEnabled != 0) { - if (NBPtr->AutoConfig (NBPtr)) { - if (NBPtr->PlatformSpec (NBPtr)) { - return TRUE; - } - } - } else { - NBPtr->DisableDCT (NBPtr); - } - } - } - } - } - } - return FALSE; -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function clears DCT registers - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemNCleanupDctRegsNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BIT_FIELD_NAME BitField; - - for (BitField = BFCSBaseAddr0Reg; BitField <= BFCSBaseAddr7Reg; BitField++) { - MemNSetBitFieldNb (NBPtr, BitField, 0); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is function gets the POR speed limit for families supports table driven form factor - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemNGetPORFreqLimitTblDrvNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - - i = 0; - while (memPlatSpecFlowArray[i] != NULL) { - if ((memPlatSpecFlowArray[i])->MaxFrequency (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - break; - } - i++; - } -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnmct.c deleted file mode 100644 index 378575e5c8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnmct.c +++ /dev/null @@ -1,1286 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnmct.c - * - * Northbridge Common MCT supporting functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 58425 $ @e \$Date: 2011-08-29 08:29:04 -0600 (Mon, 29 Aug 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "GeneralServices.h" -#include "cpuFeatures.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_MNMCT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define _16MB_RJ16 0x0100 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemNSetMTRRrangeNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Base, - IN OUT UINT32 *LimitPtr, - IN UINT32 MtrrAddr, - IN UINT8 MtrrType - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * Get max frequency from OEM platform definition, from - * any user override (limiting) of max frequency, and - * from any Si Revision Specific information. Return - * the least of these three in DIE_STRUCT.Timings.TargetSpeed. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSyncTargetSpeedNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT16 DdrMaxRateTab[] = { - UNSUPPORTED_DDR_FREQUENCY, - DDR1600_FREQUENCY, - DDR1333_FREQUENCY, - DDR1066_FREQUENCY, - DDR800_FREQUENCY, - DDR667_FREQUENCY, - DDR533_FREQUENCY, - DDR400_FREQUENCY - }; - - UINT8 Dct; - UINT8 Channel; - UINT16 MinSpeed; - UINT16 DdrMaxRate; - DCT_STRUCT *DCTPtr; - USER_MEMORY_TIMING_MODE *ChnlTmgMod; - USER_MEMORY_TIMING_MODE Mode[MAX_CHANNELS_PER_SOCKET]; - MEMORY_BUS_SPEED MemClkFreq; - MEMORY_BUS_SPEED ProposedFreq; - - ASSERT (NBPtr->DctCount <= sizeof (Mode)); - MinSpeed = 16000; - DdrMaxRate = 16000; - if (NBPtr->IsSupported[CheckMaxDramRate]) { - // Check maximum DRAM data rate that the processor is designed to support. - DdrMaxRate = DdrMaxRateTab[MemNGetBitFieldNb (NBPtr, BFDdrMaxRate)]; - NBPtr->FamilySpecificHook[GetDdrMaxRate] (NBPtr, &DdrMaxRate); - IDS_OPTION_HOOK (IDS_SKIP_FUSED_MAX_RATE, &DdrMaxRate, &NBPtr->MemPtr->StdHeader); - } - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - - // Check if input user time mode is valid or not - ASSERT ((NBPtr->RefPtr->UserTimingMode == TIMING_MODE_SPECIFIC) || - (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_LIMITED) || - (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_AUTO)); - Mode[Dct] = NBPtr->RefPtr->UserTimingMode; - // Check if input clock value is valid or not - ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? - (NBPtr->RefPtr->MemClockValue >= DDR667_FREQUENCY) : - (NBPtr->RefPtr->MemClockValue <= DDR1066_FREQUENCY)); - MemClkFreq = NBPtr->RefPtr->MemClockValue; - if (DCTPtr->Timings.DctDimmValid != 0) { - Channel = MemNGetSocketRelativeChannelNb (NBPtr, Dct, 0); - ChnlTmgMod = (USER_MEMORY_TIMING_MODE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_BUS_SPEED, NBPtr->MCTPtr->SocketId, Channel, 0, - &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader)); - if (ChnlTmgMod != NULL) { - // Check if input user timing mode is valid or not - ASSERT ((ChnlTmgMod[0] == TIMING_MODE_SPECIFIC) || (ChnlTmgMod[0] == TIMING_MODE_LIMITED) || - (ChnlTmgMod[0] != TIMING_MODE_AUTO)); - if (ChnlTmgMod[0] != TIMING_MODE_AUTO) { - Mode[Dct] = ChnlTmgMod[0]; - // Check if input clock value is valid or not - ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? - ((MEMORY_BUS_SPEED)ChnlTmgMod[1] >= DDR667_FREQUENCY) : - ((MEMORY_BUS_SPEED)ChnlTmgMod[1] <= DDR1066_FREQUENCY)); - MemClkFreq = (MEMORY_BUS_SPEED)ChnlTmgMod[1]; - } - } - - ProposedFreq = UserOptions.CfgMemoryBusFrequencyLimit; - if (Mode[Dct] == TIMING_MODE_LIMITED) { - if (MemClkFreq < ProposedFreq) { - ProposedFreq = MemClkFreq; - } - } else if (Mode[Dct] == TIMING_MODE_SPECIFIC) { - ProposedFreq = MemClkFreq; - } - - if (Mode[Dct] == TIMING_MODE_SPECIFIC) { - DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq; - } else { - // "limit" mode - if (DCTPtr->Timings.TargetSpeed > ProposedFreq) { - DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq; - } - } - - NBPtr->MemNCapSpeedBatteryLife (NBPtr); - - if (DCTPtr->Timings.TargetSpeed > DdrMaxRate) { - if (Mode[Dct] == TIMING_MODE_SPECIFIC) { - PutEventLog (AGESA_ALERT, MEM_ALERT_USER_TMG_MODE_OVERRULED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ALERT, NBPtr->MCTPtr); - } - DCTPtr->Timings.TargetSpeed = DdrMaxRate; - } - - IDS_SKIP_HOOK (IDS_POR_MEM_FREQ, NBPtr, &NBPtr->MemPtr->StdHeader) { - // - //Call Platform POR Frequency Override - // - if (!MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SPEEDLIMIT, ALL_DIMMS)) { - // - // Get the POR frequency limit - // - NBPtr->PsPtr->MemPGetPORFreqLimit (NBPtr); - } - } - IDS_OPTION_HOOK (IDS_STRETCH_FREQUENCY_LIMIT, NBPtr, &NBPtr->MemPtr->StdHeader); - - if (MinSpeed > DCTPtr->Timings.TargetSpeed) { - MinSpeed = DCTPtr->Timings.TargetSpeed; - } - } - } - - if (MinSpeed == DDR667_FREQUENCY) { - NBPtr->StartupSpeed = DDR667_FREQUENCY; - } - - // Sync all DCTs to the same speed - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - NBPtr->DCTPtr->Timings.TargetSpeed = MinSpeed; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function waits for all DCTs to be ready - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNSyncDctsReadyNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (NBPtr->MCTPtr->DimmValid) { - MemNPollBitFieldNb (NBPtr, BFDramEnabled, 1, PCI_ACCESS_TIMEOUT, FALSE); - // Re-enable phy compensation engine after Dram init has completed - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); - } - // Wait 750 us for the phy compensation engine to reinitialize. - MemUWait10ns (75000, NBPtr->MemPtr); - - MemNSyncAddrMapToAllNodesNb (NBPtr); - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function create the HT memory map - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNHtMemMapInitNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 BottomIo; - UINT32 HoleOffset; - UINT32 DctSelBaseAddr; - UINT32 NodeSysBase; - UINT32 NodeSysLimit; - MEM_PARAMETER_STRUCT *RefPtr; - DIE_STRUCT *MCTPtr; - - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - // - // Physical addresses in this function are right adjusted by 16 bits ([47:16]) - // They are BottomIO, HoleOffset, DctSelBaseAddr, NodeSysBase, NodeSysLimit. - // - - // Enforce bottom of IO be be 128MB aligned - ASSERT ((RefPtr->BottomIo < (_4GB_RJ16 >> 8)) && (RefPtr->BottomIo != 0)); - BottomIo = (RefPtr->BottomIo & 0xF8) << 8; - - if (!MCTPtr->GangedMode) { - DctSelBaseAddr = MCTPtr->DctData[0].Timings.DctMemSize; - } else { - DctSelBaseAddr = 0; - } - - if (MCTPtr->NodeMemSize) { - NodeSysBase = NBPtr->SharedPtr->CurrentNodeSysBase; - NodeSysLimit = NodeSysBase + MCTPtr->NodeMemSize - 1; - DctSelBaseAddr += NodeSysBase; - - if ((NBPtr->IsSupported[ForceEnMemHoleRemapping]) || (RefPtr->MemHoleRemapping)) { - if ((NodeSysBase < BottomIo) && (NodeSysLimit >= BottomIo)) { - // HW Dram Remap - MCTPtr->Status[SbHWHole] = TRUE; - RefPtr->GStatus[GsbHWHole] = TRUE; - MCTPtr->NodeHoleBase = BottomIo; - RefPtr->HoleBase = BottomIo; - - HoleOffset = _4GB_RJ16 - BottomIo; - - NodeSysLimit += HoleOffset; - - if ((DctSelBaseAddr > 0) && (DctSelBaseAddr < BottomIo)) { - HoleOffset += DctSelBaseAddr; - } else { - if (DctSelBaseAddr >= BottomIo) { - DctSelBaseAddr += HoleOffset; - } - HoleOffset += NodeSysBase; - } - - MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8); - MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7); - MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1); - - } else if (NodeSysBase == BottomIo) { - // SW Node Hoist - MCTPtr->Status[SbSWNodeHole] = TRUE; - RefPtr->GStatus[GsbSpIntRemapHole] = TRUE; - RefPtr->GStatus[GsbSoftHole] = TRUE; - - RefPtr->HoleBase = NodeSysBase; - DctSelBaseAddr = _4GB_RJ16 + (DctSelBaseAddr - NodeSysBase); - NodeSysLimit = _4GB_RJ16 + (NodeSysLimit - NodeSysBase); - NodeSysBase = _4GB_RJ16; - - } else if ((NodeSysBase < HT_REGION_BASE_RJ16) && (NodeSysLimit >= HT_REGION_BASE_RJ16)) { - if (!NBPtr->SharedPtr->UndoHoistingAbove1TB) { - // SW Hoisting above 1TB to avoid HT Reserved region - DctSelBaseAddr = _1TB_RJ16 + (DctSelBaseAddr - NodeSysBase); - NodeSysLimit = _1TB_RJ16 + (NodeSysLimit - NodeSysBase); - NodeSysBase = _1TB_RJ16; - - if (RefPtr->LimitMemoryToBelow1Tb) { - // Flag to undo 1TB hoisting after training - NBPtr->SharedPtr->UndoHoistingAbove1TB = TRUE; - } - } - - } else { - // No Remapping. Normal Contiguous mapping - } - } else { - // No Remapping. Normal Contiguous mapping - } - - if (NBPtr->IsSupported[Check1GAlign]) { - if (UserOptions.CfgNodeMem1GBAlign) { - NBPtr->MemPNodeMemBoundaryNb (NBPtr, (UINT32 *)&NodeSysLimit); - } - } - - MCTPtr->NodeSysBase = NodeSysBase; - MCTPtr->NodeSysLimit = NodeSysLimit; - RefPtr->SysLimit = NodeSysLimit; - RefPtr->Sub1THoleBase = (NodeSysLimit < HT_REGION_BASE_RJ16) ? (NodeSysLimit + 1) : RefPtr->Sub1THoleBase; - IDS_OPTION_HOOK (IDS_MEM_SIZE_OVERLAY, NBPtr, &NBPtr->MemPtr->StdHeader); - - NBPtr->SharedPtr->TopNode = NBPtr->Node; - - NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase; - NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit & 0xFFFFFF00; - - MemNSetBitFieldNb (NBPtr, BFDramBaseAddr, NodeSysBase >> (27 - 16)); - MemNSetBitFieldNb (NBPtr, BFDramLimitAddr, NodeSysLimit >> (27 - 16)); - - if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) { - MemNSetBitFieldNb (NBPtr, BFDctSelBaseAddr, DctSelBaseAddr >> 11); - MemNSetBitFieldNb (NBPtr, BFDctSelHiRngEn, 1); - MemNSetBitFieldNb (NBPtr, BFDctSelHi, 1); - MemNSetBitFieldNb (NBPtr, BFDctSelBaseOffset, DctSelBaseAddr >> 10); - } - - NBPtr->SharedPtr->CurrentNodeSysBase = (NodeSysLimit + 1) & 0xFFFFFFF0; - } - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Program system DRAM map to this node - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSyncAddrMapToAllNodesNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Node; - UINT32 NodeSysBase; - UINT32 NodeSysLimit; - UINT8 WeReMask; - MEM_PARAMETER_STRUCT *RefPtr; - - RefPtr = NBPtr->RefPtr; - for (Node = 0; Node < NBPtr->NodeCount; Node++) { - NodeSysBase = NBPtr->SharedPtr->NodeMap[Node].SysBase; - NodeSysLimit = NBPtr->SharedPtr->NodeMap[Node].SysLimit; - if (NBPtr->SharedPtr->NodeMap[Node].IsValid) { - WeReMask = 3; - } else { - WeReMask = 0; - } - // Set the Dram base and set the WE and RE flags in the base. - MemNSetBitFieldNb (NBPtr, BFDramBaseReg0 + Node, (NodeSysBase << 8) | WeReMask); - MemNSetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node, NodeSysBase >> 24); - // Set the Dram limit and set DstNode. - MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, (NodeSysLimit << 8) | Node); - MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, NodeSysLimit >> 24); - - if (RefPtr->GStatus[GsbHWHole]) { - MemNSetBitFieldNb (NBPtr, BFDramMemHoistValid, 1); - MemNSetBitFieldNb (NBPtr, BFDramHoleBase, (RefPtr->HoleBase >> 8)); - } - } - - NBPtr->FamilySpecificHook[InitExtMMIOAddr] (NBPtr, NULL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function enables power down mode - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNPowerDownCtlNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_PARAMETER_STRUCT *RefPtr; - UINT8 PowerDownMode; - - RefPtr = NBPtr->RefPtr; - - // we can't enable powerdown mode when doing WL - if (RefPtr->EnablePowerDown) { - MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); - PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode); - IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); - if (PowerDownMode) { - MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the Optimal Critical Gross Delay Difference between - * the delay parameters across all Dimms on each bytelane. Then takes the - * largest of all the bytelanes. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly1 - Type of first Gross Delay parameter - * @param[in] TrnDly2 - Type of second Gross Delay parameter - * - * @return The largest difference between the largest and smallest - * of the two Gross delay types within a single bytelane - */ -INT8 -MemNGetOptimalCGDDNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly1, - IN TRN_DLY_TYPE TrnDly2 - ) -{ - INT8 CGDD; - INT8 GDD; - UINT8 Dimm1; - UINT8 Dimm2; - UINT8 ByteLane; - UINT16 CsEnabled; - BOOLEAN CGDDInit; - BOOLEAN SameDelayType; - - CGDD = 0; - CGDDInit = FALSE; - SameDelayType = (BOOLEAN) (TrnDly1 == TrnDly2); - CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; - - // If the two delay types compared are the same type, then no need to compare the same - // pair twice. Adjustments are made in the upper bound and lower bound of the loop to - // handle this. - for (Dimm1 = 0; Dimm1 < (SameDelayType ? (MAX_DIMMS_PER_CHANNEL - 1) : MAX_DIMMS_PER_CHANNEL); Dimm1 ++) { - if (CsEnabled & (UINT16) (3 << (Dimm1 << 1))) { - for (Dimm2 = (SameDelayType ? (Dimm1 + 1) : 0); Dimm2 < MAX_DIMMS_PER_CHANNEL; Dimm2 ++) { - if ((CsEnabled & (UINT16) (3 << (Dimm2 << 1)))) { - for (ByteLane = 0 ; ByteLane < 8 ; ByteLane++) { - // check each byte lane delay pair - GDD = (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly1, DIMM_BYTE_ACCESS (Dimm1, ByteLane)) >> 5) - - (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly2, DIMM_BYTE_ACCESS (Dimm2, ByteLane)) >> 5); - // If the 2 delay types to be compared are the same, then keep the absolute difference - if (SameDelayType && (GDD < 0)) { - GDD = (-GDD); - } - - // If CGDD is yet to be initialized, initialize it - // Otherwise, keep the largest difference so far - CGDD = (!CGDDInit) ? GDD : ((CGDD > GDD) ? CGDD : GDD); - if (!CGDDInit) { - CGDDInit = TRUE; - } - } - } - } - } - } - return CGDD; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the critical delay difference (CDD) - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDlyType1 - Type of first Gross Delay parameter - * @param[in] TrnDlyType2 - Type of second Gross Delay parameter - * @param[in] SameDimm - CDD of same DIMMs - * @param[in] DiffDimm - CDD of different DIMMs - * - * @return CDD term - in 1/2 MEMCLK - */ -INT16 -MemNCalcCDDNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDlyType1, - IN TRN_DLY_TYPE TrnDlyType2, - IN BOOLEAN SameDimm, - IN BOOLEAN DiffDimm - ) -{ - INT16 CDD; - INT16 CDDtemp; - UINT16 TrnDly1; - UINT16 TrnDly2; - UINT8 i; - UINT8 j; - UINT8 ByteLane; - UINT16 CsEnabled; - BOOLEAN SameDlyType; - - SameDlyType = (BOOLEAN) (TrnDlyType1 == TrnDlyType2); - CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; - CDD = -32000; - // If the two delay types compared are the same type, then no need to compare the same - // pair twice. Adjustments are made in the upper bound and lower bound of the loop to - // handle this. - for (i = 0; i < (SameDlyType ? (MAX_DIMMS_PER_CHANNEL - 1) : MAX_DIMMS_PER_CHANNEL); i++) { - if ((CsEnabled & (UINT16) (3 << (i << 1))) != 0) { - for (j = SameDlyType ? (i + 1) : 0; j < MAX_DIMMS_PER_CHANNEL; j++) { - if (((CsEnabled & (UINT16) (3 << (j << 1))) != 0) && ((SameDimm && (i == j)) || (DiffDimm && (i != j)))) { - for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { - /// @todo: Gross delay mask should not be constant. - TrnDly1 = GetTrainDlyFromHeapNb (NBPtr, TrnDlyType1, DIMM_BYTE_ACCESS (i, ByteLane)) >> 5; // Gross delay only - TrnDly2 = GetTrainDlyFromHeapNb (NBPtr, TrnDlyType2, DIMM_BYTE_ACCESS (j, ByteLane)) >> 5; // Gross delay only - - CDDtemp = TrnDly1 - TrnDly2; - // If the 2 delay types to be compared are the same, then keep the absolute difference - if ((SameDlyType) && (CDDtemp < 0)) { - CDDtemp = (-CDDtemp); - } - - CDD = (CDD < CDDtemp) ? CDDtemp : CDD; - } - } - } - } - } - - return CDD; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets DQS timing from data saved in heap. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDlyType - type of delay to be set - * @param[in] Drbn - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * - * @return value of the target timing. - */ -UINT16 -GetTrainDlyFromHeapNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDlyType, - IN DRBN Drbn - ) -{ - UINT8 Dimm; - UINT8 Byte; - UINT16 TrainDly; - CH_DEF_STRUCT *ChannelPtr; - MEM_TECH_BLOCK *TechPtr; - - Dimm = DRBN_DIMM (Drbn); - Byte = DRBN_BYTE (Drbn); - ChannelPtr = NBPtr->ChannelPtr; - TechPtr = NBPtr->TechPtr; - - ASSERT (Dimm < 4); - ASSERT (Byte <= ECC_DLY); - - if (NBPtr->MemPstate == MEMORY_PSTATE1) { - switch (TrnDlyType) { - case AccessRcvEnDly: - TrainDly = ChannelPtr->RcvEnDlysMemPs1[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - case AccessWrDqsDly: - TrainDly = ChannelPtr->WrDqsDlysMemPs1[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - case AccessWrDatDly: - TrainDly = ChannelPtr->WrDatDlysMemPs1[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - case AccessRdDqsDly: - TrainDly = ChannelPtr->RdDqsDlysMemPs1[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - default: - TrainDly = 0; - IDS_ERROR_TRAP; - } - } else { - switch (TrnDlyType) { - case AccessRcvEnDly: - TrainDly = ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - case AccessWrDqsDly: - TrainDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - case AccessWrDatDly: - TrainDly = ChannelPtr->WrDatDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - case AccessRdDqsDly: - TrainDly = ChannelPtr->RdDqsDlys[Dimm * TechPtr->DlyTableWidth () + Byte]; - break; - default: - TrainDly = 0; - IDS_ERROR_TRAP; - } - } - - return TrainDly; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the fixed MTRRs for common legacy ranges. - * It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - */ - -BOOLEAN -MemNCPUMemTypingNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 Bottom32bIO; - UINT32 Bottom40bIO; - UINT32 Cache32bTOP; - S_UINT64 SMsr; - - MEM_DATA_STRUCT *MemPtr; - MEM_PARAMETER_STRUCT *RefPtr; - RefPtr = NBPtr->RefPtr; - MemPtr = NBPtr->MemPtr; - - // - //====================================================================== - // Set temporary top of memory from Node structure data. - // Adjust temp top of memory down to accommodate 32-bit IO space. - //====================================================================== - //Bottom40bIO=top of memory, right justified 16 bits (defines dram versus IO space type) - //Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type) - //Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits - // - if (RefPtr->HoleBase != 0) { - Bottom32bIO = RefPtr->HoleBase; - } else if (RefPtr->BottomIo != 0) { - Bottom32bIO = (UINT32)RefPtr->BottomIo << (24 - 16); - } else { - Bottom32bIO = (UINT32)1 << (24 - 16); - } - - Cache32bTOP = RefPtr->SysLimit + 1; - if (Cache32bTOP < _4GB_RJ16) { - Bottom40bIO = 0; - if (Bottom32bIO >= Cache32bTOP) { - Bottom32bIO = Cache32bTOP; - } - } else { - Bottom40bIO = Cache32bTOP; - } - - Cache32bTOP = Bottom32bIO; - - - // - //====================================================================== - // Set default values for CPU registers - //====================================================================== - // - LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.lo |= 0x1C0000; // turn on modification enable bit and - // mtrr enable bits - LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - SMsr.lo = SMsr.hi = 0x1E1E1E1E; - LibAmdMsrWrite (0x250, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 0 - 512K = WB Mem - LibAmdMsrWrite (0x258, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 512K - 640K = WB Mem - - // - //====================================================================== - // Set variable MTRR values - //====================================================================== - // - MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6); - - RefPtr->Sub4GCacheTop = Cache32bTOP << 16; - - // - //====================================================================== - // Set TOP_MEM and TOM2 CPU registers - //====================================================================== - // - SMsr.hi = Bottom32bIO >> (32 - 16); - SMsr.lo = Bottom32bIO << 16; - LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM: %08x0000\n", Bottom32bIO); - - if (Bottom40bIO) { - SMsr.hi = Bottom40bIO >> (32 - 16); - SMsr.lo = Bottom40bIO << 16; - } else { - SMsr.hi = 0; - SMsr.lo = 0; - } - LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - if (Bottom40bIO) { - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", Bottom40bIO); - IDS_HDT_CONSOLE (MEM_FLOW, "Sub1THoleBase: %08x0000\n", RefPtr->Sub1THoleBase); - // Enable TOM2 - SMsr.lo |= 0x00600000; - } else { - // Disable TOM2 - SMsr.lo &= ~0x00600000; - } - SMsr.lo &= 0xFFF7FFFF; // turn off modification enable bit - LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges. - * It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNUMAMemTypingNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 Bottom32bIO; - UINT32 Bottom32bUMA; - UINT32 Cache32bTOP; - UINT32 Value32; - UINT8 BitCount; - UINT8 i; - - MEM_PARAMETER_STRUCT *RefPtr; - RefPtr = NBPtr->RefPtr; - BitCount = 0; - // - //====================================================================== - // Adjust temp top of memory down to accommodate UMA memory start - //====================================================================== - // Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type) - // Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits - // - Bottom32bIO = RefPtr->Sub4GCacheTop >> 16; - Bottom32bUMA = RefPtr->UmaBase; - - if (Bottom32bUMA < Bottom32bIO) { - Cache32bTOP = Bottom32bUMA; - RefPtr->Sub4GCacheTop = Bottom32bUMA << 16; - // - //====================================================================== - //Set variable MTRR values - //====================================================================== - // - Value32 = Cache32bTOP; - //Pre-check the bit count of bottom Uma to see if it is potentially running out of Mtrr while typing. - while (Value32 != 0) { - i = LibAmdBitScanForward (Value32); - Value32 &= ~ (1 << i); - BitCount++; - } - - if (BitCount > 5) { - NBPtr->RefPtr->GStatus[GsbMTRRshort] = TRUE; - MemNSetMTRRUmaRegionUCNb (NBPtr, &Cache32bTOP, &Bottom32bIO); - } else { - MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Program MTRRs to describe given range as given cache type. Use MTRR pairs - * starting with the given MTRRphys Base address, and use as many as is - * required up to (excluding) MSR 020C, which is reserved for OS. - * - * "Limit" in the context of this procedure is not the numerically correct - * limit, but rather the Last address+1, for purposes of coding efficiency - * and readability. Size of a region is then Limit-Base. - * - * 1. Size of each range must be a power of two - * 2. Each range must be naturally aligned (Base is same as size) - * - * There are two code paths: the ascending path and descending path (analogous - * to bsf and bsr), where the next limit is a function of the next set bit in - * a forward or backward sequence of bits (as a function of the Limit). We - * start with the ascending path, to ensure that regions are naturally aligned, - * then we switch to the descending path to maximize MTRR usage efficiency. - * Base=0 is a special case where we start with the descending path. - * Correct Mask for region is 2comp(Size-1)-1, - * which is 2comp(Limit-Base-1)-1 * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Base - Base address[47:16] of specified range. - * @param[in] *LimitPtr - Limit address[47:16] of specified range. - * @param[in] MtrrAddr - address of var MTRR pair to start using. - * @param[in] MtrrType - Cache type for the range. - * - * @return TRUE - No failure occurred - * @return FALSE - Failure occurred because run out of variable-size MTRRs before completion. - */ - -BOOLEAN -STATIC -MemNSetMTRRrangeNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Base, - IN OUT UINT32 *LimitPtr, - IN UINT32 MtrrAddr, - IN UINT8 MtrrType - ) -{ - S_UINT64 SMsr; - UINT32 CurBase; - UINT32 CurLimit; - UINT32 CurSize; - UINT32 CurAddr; - UINT32 Value32; - - CurBase = Base; - CurLimit = *LimitPtr; - CurAddr = MtrrAddr; - - while ((CurAddr >= 0x200) && (CurAddr < 0x20A) && (CurBase < *LimitPtr)) { - CurSize = CurLimit = (UINT32)1 << LibAmdBitScanForward (CurBase); - CurLimit += CurBase; - if ((CurBase == 0) || (*LimitPtr < CurLimit)) { - CurLimit = *LimitPtr - CurBase; - CurSize = CurLimit = (UINT32)1 << LibAmdBitScanReverse (CurLimit); - CurLimit += CurBase; - } - - // prog. MTRR with current region Base - SMsr.lo = (CurBase << 16) | (UINT32)MtrrType; - SMsr.hi = CurBase >> (32 - 16); - LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - - // prog. MTRR with current region Mask - CurAddr++; // other half of MSR pair - Value32 = CurSize - (UINT32)1; - Value32 = ~Value32; - SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk; - SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID); - LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - - CurBase = CurLimit; - CurAddr++; // next MSR pair - } - - if (CurLimit < *LimitPtr) { - // Announce failure - *LimitPtr = CurLimit; - IDS_ERROR_TRAP; - } - - while ((CurAddr >= 0x200) && (CurAddr < 0x20C)) { - SMsr.lo = SMsr.hi = 0; - LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - CurAddr++; - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Program one MTRR to describe Uma region as UC cache type if we detect running out of - * Mtrr circumstance. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *BasePtr - Base address[47:24] of specified range. - * @param[in] *LimitPtr - Limit address[47:24] of specified range. - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemNSetMTRRUmaRegionUCNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 *BasePtr, - IN OUT UINT32 *LimitPtr - ) -{ - S_UINT64 SMsr; - UINT32 Mtrr; - UINT32 Size; - UINT32 Value32; - - Size = *LimitPtr - *BasePtr; - // Check if Size is a power of 2 - if ((Size & (Size - 1)) != 0) { - for (Mtrr = 0x200; Mtrr < 0x20A; Mtrr += 2) { - LibAmdMsrRead (Mtrr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - if ((SMsr.lo & ((UINT32) 1 << 11)) == 0) { - MemNSetMTRRrangeNb (NBPtr, *BasePtr, LimitPtr, Mtrr, 0); - break; - } - } - if (Mtrr == 0x20A) { - // Run out of MTRRs - IDS_ERROR_TRAP; - } - } else { - Mtrr = 0x20A; //Reserved pair of MTRR for UMA region. - - // prog. MTRR with current region Base - SMsr.lo = *BasePtr << 16; - SMsr.hi = *BasePtr >> (32 - 16); - LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - - // prog. MTRR with current region Mask - Mtrr++; // other half of MSR pair - Value32 = Size - (UINT32)1; - Value32 = ~Value32; - SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk; - SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID); - LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Report the Uma size that is going to be allocated. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return Uma size [31:0] = Addr [47:16] - */ -UINT32 -MemNGetUmaSizeNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return 0; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function allocates 16MB of memory for C6 storage when it is requested to be enabled - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNAllocateC6StorageClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 SysLimit; - - if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { - SysLimit = NBPtr->RefPtr->SysLimit; - SysLimit -= _16MB_RJ16; - - // Set Dram Limit - NBPtr->MCTPtr->NodeSysLimit = SysLimit; - NBPtr->RefPtr->SysLimit = SysLimit; - MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((SysLimit << 8) & 0xFFFF0000)); - - // Set TOPMEM and MTRRs - MemNC6AdjustMSRs (NBPtr); - - // Set C6Base - MemNSetBitFieldNb (NBPtr, BFC6Base, (SysLimit + 1) >> (24 - 16)); - - // C6DramLock will be set in FinalizeMCT - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function allocates 16MB of memory for C6 storage when it is requested to be enabled - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNAllocateC6StorageUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Node; - UINT32 SysLimit; - UINT32 DramLimitReg; - - if (NBPtr->SharedPtr->C6Enabled || IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { - - SysLimit = NBPtr->RefPtr->SysLimit; - - // Calculate new SysLimit - if (!NBPtr->SharedPtr->C6Enabled) { - if (NBPtr->SharedPtr->NodeIntlv.NodeCnt >= 2) { - // Node Interleave is enabled, system memory available is reduced by 16MB * number of nodes - SysLimit -= _16MB_RJ16 * NBPtr->SharedPtr->NodeIntlv.NodeCnt; - } else { - // Otherwise, system memory available is reduced by 16MB - SysLimit -= _16MB_RJ16; - } - NBPtr->RefPtr->SysLimit = SysLimit; - NBPtr->SharedPtr->C6Enabled = TRUE; - - // Set TOPMEM and MTRRs (only need to be done once for BSC) - MemNC6AdjustMSRs (NBPtr); - } - - // Set Dram Limit - if (NBPtr->SharedPtr->NodeIntlv.NodeCnt >= 2) { - for (Node = 0; Node < NBPtr->NodeCount; Node++) { - DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0 + Node); - if ((DramLimitReg & 0xFFFF0000) != 0) { - MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, ((SysLimit << 8) & 0xFFFF0000) | (DramLimitReg & 0xFFFF)); - MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, SysLimit >> 24); - } - } - // Node Interleave is enabled, CoreStateSaveDestNode points to its own node - MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, NBPtr->Node); - NBPtr->MCTPtr->NodeSysLimit = SysLimit; - } else { - DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0 + NBPtr->SharedPtr->TopNode) & 0x0000FFFF; - MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + NBPtr->SharedPtr->TopNode, ((SysLimit << 8) & 0xFFFF0000) | DramLimitReg); - MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + NBPtr->SharedPtr->TopNode, SysLimit >> 24); - - // Node Interleave is not enabled, CoreStateSaveDestNode points to the node that contains top memory - MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, NBPtr->SharedPtr->TopNode); - - if (NBPtr->Node == NBPtr->SharedPtr->TopNode) { - NBPtr->MCTPtr->NodeSysLimit = SysLimit; - } - } - - // Set BFCC6SaveEn - MemNSetBitFieldNb (NBPtr, BFCC6SaveEn, 1); - - // LockDramCfg will be set in FinalizeMCT - } -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function readjusts TOPMEM and MTRRs after allocating storage for C6 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNC6AdjustMSRs ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT32 SysLimit; - UINT32 CurAddr; - S_UINT64 SMsr; - - SysLimit = NBPtr->RefPtr->SysLimit + 1; - SMsr.hi = SysLimit >> (32 - 16); - SMsr.lo = SysLimit << 16; - if (SysLimit < _4GB_RJ16) { - LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM: %08x0000\n", SysLimit); - // If there is no UMA buffer, then set top of cache and MTRR. - // Otherwise, top of cache and MTRR will be set when UMA buffer is set up. - if (NBPtr->RefPtr->UmaMode == UMA_NONE) { - NBPtr->RefPtr->Sub4GCacheTop = (SysLimit << 16); - // Find unused MTRR to set C6 region to UC - for (CurAddr = 0x200; CurAddr < 0x20C; CurAddr += 2) { - LibAmdMsrRead (CurAddr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - if ((SMsr.lo & ((UINT32) 1 << 11)) == 0) { - // Set region base as TOM - SMsr.hi = SysLimit >> (32 - 16); - SMsr.lo = SysLimit << 16; - LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - - // set region mask to 16MB - SMsr.hi = NBPtr->VarMtrrHiMsk; - SMsr.lo = 0xFF000800; - LibAmdMsrWrite (CurAddr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); - - break; - } - } - } - } else { - LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", SysLimit); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Family-specific hook to override the DdrMaxRate value for families with a - * non-GH-compatible encoding for BFDdrMaxRate - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *DdrMaxRate - Void pointer to DdrMaxRate. Used as INT16. - * - * @return TRUE - * - */ -BOOLEAN -MemNGetMaxDdrRateUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *DdrMaxRate - ) -{ - UINT8 DdrMaxRateEncoded; - - DdrMaxRateEncoded = (UINT8) MemNGetBitFieldNb (NBPtr, BFDdrMaxRate); - - if (DdrMaxRateEncoded == 0) { - * (UINT16 *) DdrMaxRate = UNSUPPORTED_DDR_FREQUENCY; - } else { - * (UINT16 *) DdrMaxRate = MemNGetMemClkFreqUnb (NBPtr, DdrMaxRateEncoded); - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function performs the action after save/restore execution - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * - */ - -BOOLEAN -MemNAfterSaveRestoreUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - // Sync. up DctCfgSel value with NBPtr->Dct - MemNSetBitFieldNb (NBPtr, BFDctCfgSel, NBPtr->Dct); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function performs the action before and after excluding dimms on CNB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *IsBefore - If the function is called before excluding dimms - * - * @return TRUE - * - */ - -BOOLEAN -MemNBfAfExcludeDimmClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *IsBefore - ) -{ - if (*(BOOLEAN *) IsBefore == TRUE) { - NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1); - NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - } else { - NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1); - NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - } - - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnphy.c deleted file mode 100644 index 532c04083b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnphy.c +++ /dev/null @@ -1,2041 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnphy.c - * - * Common Northbridge Phy support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 60556 $ @e \$Date: 2011-10-17 20:19:58 -0600 (Mon, 17 Oct 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "PlatformMemoryConfiguration.h" -#include "heapManager.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_NB_MNPHY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/// Type of an entry for processing phy init compensation for client NB -typedef struct { - BIT_FIELD_NAME IndexBitField; ///< Bit field on which the value is decided - BIT_FIELD_NAME StartTargetBitField; ///< First bit field to be modified - BIT_FIELD_NAME EndTargetBitField; ///< Last bit field to be modified - UINT16 ExtraValue; ///< Extra value needed to be written to bit field - CONST UINT16 (*TxPrePN)[3][5]; ///< Pointer to slew rate table -} PHY_COMP_INIT_CLIENTNB; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets a delay value a PCI register during training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - type of delay to be set - * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * - * @return Value read - */ - -UINT32 -MemNGetTrainDlyNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar - ) -{ - return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets a delay value a PCI register during training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - type of delay to be set - * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * @param[in] Field - Value to be programmed - * - */ - -VOID -MemNSetTrainDlyNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar, - IN UINT16 Field - ) -{ - NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes prototypical Phy fence training function. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNPhyFenceTrainingNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->MemPPhyFenceTrainingNb (NBPtr); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes prototypical Phy fence training function. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNPhyFenceTrainingUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 FenceThresholdTxDll; - UINT8 FenceThresholdRxDll; - UINT8 FenceThresholdTxPad; - UINT16 Fence2Data; - - // 1. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=10b. - // 2. Perform phy fence training. - // 3. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxDll]. - MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 2); - MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 26, BFPhyFence); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFenceThresholdTxDll\n"); - MemNTrainPhyFenceNb (NBPtr); - FenceThresholdTxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); - NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdTxDll); - - // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=001b. - MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x1000); - - // 5. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=01b. - // 6. Perform phy fence training. - // 7. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdRxDll]. - MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 1); - MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 25, 21, BFPhyFence); - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdRxDll\n"); - MemNTrainPhyFenceNb (NBPtr); - FenceThresholdRxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); - NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdRxDll); - - // 8. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=000b. - MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x0000); - - // 9. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=11b. - // 10. Perform phy fence training. - // 11. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxPad]. - MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 3); - MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdTxPad\n"); - MemNTrainPhyFenceNb (NBPtr); - FenceThresholdTxPad = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); - NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdTxPad); - - // Program Fence2 threshold for Clk, Cmd, and Addr - if (FenceThresholdTxPad < 16) { - MemNSetBitFieldNb (NBPtr, BFClkFence2, FenceThresholdTxPad | 0x10); - MemNSetBitFieldNb (NBPtr, BFCmdFence2, FenceThresholdTxPad | 0x10); - MemNSetBitFieldNb (NBPtr, BFAddrFence2, FenceThresholdTxPad | 0x10); - } else { - MemNSetBitFieldNb (NBPtr, BFClkFence2, 0); - MemNSetBitFieldNb (NBPtr, BFCmdFence2, 0); - MemNSetBitFieldNb (NBPtr, BFAddrFence2, 0); - } - - // Program Fence2 threshold for data - Fence2Data = 0; - if (FenceThresholdTxPad < 16) { - Fence2Data |= FenceThresholdTxPad | 0x10; - } - if (FenceThresholdRxDll < 16) { - Fence2Data |= (FenceThresholdRxDll | 0x10) << 10; - } - if (FenceThresholdTxDll < 16) { - Fence2Data |= (FenceThresholdTxDll | 0x10) << 5; - } - MemNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data); - NBPtr->FamilySpecificHook[ProgramFence2RxDll] (NBPtr, &Fence2Data); - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - // 18. If motherboard routing requires CS[7:6] to adopt address timings, e.g. 3 LRDIMMs/ch with CS[7:6] - // routed across all DIMM sockets, BIOS performs the following: - if (GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, - NBPtr->MCTPtr->SocketId, - NBPtr->ChannelPtr->ChannelID) == 3) { - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_NO_LRDIMM_CS67_ROUTING, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) == NULL) { - // A. Program D18F2xA8_dct[1:0][CSTimingMux67] = 1. - MemNSetBitFieldNb (NBPtr, BFCSTimingMux67, 1); - // B. Program D18F2x9C_x0D0F_8021_dct[1:0]: - // - DiffTimingEn = 1. - // - IF (D18F2x9C_x0000_0004_dct[1:0][AddrCmdFineDelay] >= - // D18F2x9C_x0D0F_E008_dct[1:0][FenceValue]) THEN Fence = 1 ELSE Fence = 0. - // - Delay = D18F2x9C_x0000_0004_dct[1:0][AddrCmdFineDelay]. - // - MemNSetBitFieldNb (NBPtr, BFDiffTimingEn, 1); - MemNSetBitFieldNb (NBPtr, BFFence, (MemNGetBitFieldNb (NBPtr, BFAddrCmdFineDelay) >= MemNGetBitFieldNb (NBPtr, BFFenceValue)) ? 1 : 0); - MemNSetBitFieldNb (NBPtr, BFDelay, (MemNGetBitFieldNb (NBPtr, BFAddrCmdFineDelay))); - } - } - } - - // 19. Reprogram F2x9C_04. - MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl)); - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function executes Phy fence training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNTrainPhyFenceNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Byte; - INT16 Avg; - UINT8 PREvalue; - - if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface)) { - return; - } - - // 1. BIOS first programs a seed value to the phase recovery - // engine registers. - // - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSeeds: "); - for (Byte = 0; Byte < MAX_BYTELANES_PER_CHANNEL; Byte++) { - // This includes ECC as byte 8 - MemNSetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte), 19); - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", 19); - } - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tPhyFenceTrEn = 1"); - // 2. Set F2x[1, 0]9C_x08[PhyFenceTrEn]=1. - MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 1); - - if (!NBPtr->IsSupported[UnifiedNbFence]) { - // 3. Wait 200 MEMCLKs. - MemNWaitXMemClksNb (NBPtr, 200); - } else { - // 3. Wait 2000 MEMCLKs. - MemNWaitXMemClksNb (NBPtr, 2000); - } - - // 4. Clear F2x[1, 0]9C_x08[PhyFenceTrEn]=0. - MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 0); - - // 5. BIOS reads the phase recovery engine registers - // F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52. - // 6. Calculate the average value of the fine delay and subtract 8. - // - Avg = 0; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t PRE: "); - for (Byte = 0; Byte < MAX_BYTELANES_PER_CHANNEL; Byte++) { - // - // This includes ECC as byte 8. ECC Byte lane (8) is ignored by MemNGetTrainDlyNb function where - // ECC is not supported. - // - PREvalue = (UINT8) (0x1F & MemNGetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte))); - Avg = Avg + ((INT16) PREvalue); - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", PREvalue); - } - Avg = ((Avg + 8) / 9); // round up - - Avg -= 8; - NBPtr->MemNPFenceAdjustNb (NBPtr, &Avg); - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFence: %02x\n", Avg); - - // 7. Write the value to F2x[1, 0]9C_x0C[PhyFence]. - MemNSetBitFieldNb (NBPtr, BFPhyFence, Avg); - - // 8. BIOS rewrites F2x[1, 0]9C_x04, DRAM Address/Command Timing Control - // Register delays for both channels. This forces the phy to recompute - // the fence. - // - MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DDR phy compensation logic - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitPhyCompNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2}; - CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2}; - CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2}; - CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3}; - UINT8 i; - UINT8 j; - UINT8 CurrDct; - UINT8 CurrChannel; - BOOLEAN MarginImprv; - MarginImprv = FALSE; - CurrDct = NBPtr->Dct; - CurrChannel = NBPtr->Channel; - if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) { - if (NBPtr->MCTPtr->GangedMode == FALSE) { - for (i = 0; i < NBPtr->DctCount; i++) { - MemNSwitchDCTNb (NBPtr, i); - for (j = 0; j < NBPtr->ChannelCount; j++) { - NBPtr->SwitchChannel (NBPtr, j); - if ((NBPtr->ChannelPtr->Dimms == 4) && ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY))) { - MarginImprv = TRUE; - } - } - } - MemNSwitchDCTNb (NBPtr, CurrDct); - NBPtr->SwitchChannel (NBPtr, CurrChannel); - } - } - - // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1 - // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. - // DisAutoComp will be cleared after Dram init has completed - // - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); - MemUWait10ns (500, NBPtr->MemPtr); - MemNSwitchDCTNb (NBPtr, CurrDct); - - // 3. For each normalized driver strength code read from - // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the - // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal]. - // - // 4. For each normalized driver strength code read from - // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding - // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal, - // D3Cmp2PCal]. - // - j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren); - i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren); - - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]); - - if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) { - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]); - } - if (NBPtr->IsSupported[CheckSlewWithoutMarginImprv]) { - ASSERT (i <= 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]); - } - MemNSwitchDCTNb (NBPtr, CurrDct); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes before DRAM training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNBeforeDQSTrainingNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 ChipSel; - UINT32 TestAddrRJ16; - UINT32 RealAddr; - - MemTBeginTraining (NBPtr->TechPtr); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) { - - RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr); - - MemUDummyCLRead (RealAddr); - - MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); - MemUWait10ns (60, NBPtr->MemPtr); // Wait 300ns - MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); - MemUWait10ns (400, NBPtr->MemPtr); // Wait 2us - MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr); - break; - } - } - } - if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) { - if (!NBPtr->MCTPtr->Status[SbEccDimms]) { - MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010); - } - if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) { - MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080); - } - } - } - - MemTEndTraining (NBPtr->TechPtr); -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * Returns the parameters for a requested delay value to be used in training - * The correct Min, Max and Mask are determined based on the type of Delay, - * and the frequency - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - Type of delay - * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct - * - */ - -VOID -MemNGetTrainDlyParmsNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly, - IN OUT TRN_DLY_PARMS *Parms - ) -{ - Parms->Min = 0; - - if (TrnDly == AccessWrDatDly) { - Parms->Max = 0x1F; - Parms->Mask = 0x01F; - } else if (TrnDly == AccessRdDqsDly) { - if ( (NBPtr->IsSupported[CheckMaxRdDqsDlyPtr]) && (NBPtr->DCTPtr->Timings.Speed > DDR667_FREQUENCY) ) { - Parms->Max = 0x3E; - Parms->Mask = 0x03E; - } else { - Parms->Max = 0x1F; - Parms->Mask = 0x01F; - } - } -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * Returns the parameters for a requested delay value to be used in training - * The correct Min, Max and Mask are determined based on the type of Delay, - * and the frequency - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - Type of delay - * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct - * - */ - -VOID -MemNGetTrainDlyParmsClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly, - IN OUT TRN_DLY_PARMS *Parms - ) -{ - Parms->Min = 0; - - if (TrnDly == AccessWrDatDly) { - Parms->Max = 0x1F; - Parms->Mask = 0x01F; - } else if (TrnDly == AccessRdDqsDly) { - Parms->Max = 0x3E; - Parms->Mask = 0x03E; - } -} -/*-----------------------------------------------------------------------------*/ -/** - * - * Returns the parameters for a requested delay value to be used in training - * The correct Min, Max and Mask are determined based on the type of Delay, - * and the frequency - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - Type of delay - * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct - * - */ - -VOID -MemNGetTrainDlyParmsUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN TRN_DLY_TYPE TrnDly, - IN OUT TRN_DLY_PARMS *Parms - ) -{ - Parms->Min = 0; - - if ((TrnDly == AccessWrDatDly) || (TrnDly == AccessRdDqsDly)) { - Parms->Max = 0x1F; - Parms->Mask = 0x01F; - } -} -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets or set DQS timing during training. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - type of delay to be set - * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * @param[in] Field - Value to be programmed - * @param[in] IsSet - Indicates if the function will set or get - * - * @return value read, if the function is used as a "get" - */ - -UINT32 -MemNcmnGetSetTrainDlyNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar, - IN UINT16 Field - ) -{ - UINT16 Index; - UINT16 Offset; - UINT32 Value; - UINT32 Address; - UINT8 Dimm; - UINT8 Rank; - UINT8 Byte; - UINT8 Nibble; - - Dimm = DRBN_DIMM (DrbnVar); - Rank = DRBN_RANK (DrbnVar); - Byte = DRBN_BYTE (DrbnVar); - Nibble = DRBN_NBBL (DrbnVar); - - ASSERT (Dimm < 4); - ASSERT (Byte <= ECC_DLY); - - switch (TrnDly) { - case AccessRcvEnDly: - Index = 0x10; - break; - case AccessWrDqsDly: - Index = 0x30; - break; - case AccessWrDatDly: - Index = 0x01; - break; - case AccessRdDqsDly: - Index = 0x05; - break; - case AccessPhRecDly: - Index = 0x50; - break; - default: - Index = 0; - IDS_ERROR_TRAP; - } - - switch (TrnDly) { - case AccessRcvEnDly: - case AccessWrDqsDly: - Index += (Dimm * 3); - if (Byte & 0x04) { - // if byte 4,5,6,7 - Index += 0x10; - } - if (Byte & 0x02) { - // if byte 2,3,6,7 - Index++; - } - if (Byte > 7) { - Index += 2; - } - Offset = 16 * (Byte % 2); - Index |= (Rank << 8); - Index |= (Nibble << 9); - break; - - case AccessRdDqsDly: - case AccessWrDatDly: - - if (NBPtr->IsSupported[DimmBasedOnSpeed]) { - if (NBPtr->DCTPtr->Timings.Speed < DDR800_FREQUENCY) { - // if DDR speed is below 800, use DIMM 0 delays for all DIMMs. - Dimm = 0; - } - } - - Index += (Dimm * 0x100); - if (Nibble) { - if (Rank) { - Index += 0xA0; - } else { - Index += 0x70; - } - } else if (Rank) { - Index += 0x60; - } - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. - case AccessPhRecDly: - Index += (Byte / 4); - Offset = 8 * (Byte % 4); - break; - default: - Offset = 0; - IDS_ERROR_TRAP; - } - - Address = Index; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - - if (TrnDly == AccessRdDqsDly) { - NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] (NBPtr, &Offset); - } - - if (IsSet) { - if (TrnDly == AccessPhRecDly) { - Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; - } - - Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset))); - MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - - if (TrnDly == AccessPhRecDly) { - NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; - } - } else { - Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF); - } - - return Value; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets or set DQS timing during training. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] IsSet - Indicates if the function will set or get - * @param[in] TrnDly - type of delay to be set - * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * @param[in] Field - Value to be programmed - * - * @return value read, if the function is used as a "get" - */ -UINT32 -MemNcmnGetSetTrainDlyClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar, - IN UINT16 Field - ) -{ - UINT16 Index; - UINT16 Offset; - UINT32 Value; - UINT32 Address; - UINT8 Dimm; - UINT8 Byte; - - Dimm = DRBN_DIMM (DrbnVar); - Byte = DRBN_BYTE (DrbnVar); - - ASSERT (Dimm < 2); - ASSERT (Byte <= ECC_DLY); - - if ((Byte > 7)) { - // Llano does not support ECC delay, so: - if (IsSet) { - // On write, ignore - return 0; - } else { - // On read, redirect to byte 0 to correct fence averaging - Byte = 0; - } - } - - switch (TrnDly) { - case AccessRcvEnDly: - Index = 0x10; - break; - case AccessWrDqsDly: - Index = 0x30; - break; - case AccessWrDatDly: - Index = 0x01; - break; - case AccessRdDqsDly: - Index = 0x05; - break; - case AccessPhRecDly: - Index = 0x50; - break; - default: - Index = 0; - IDS_ERROR_TRAP; - } - - switch (TrnDly) { - case AccessRcvEnDly: - case AccessWrDqsDly: - Index += (Dimm * 3); - if (Byte & 0x04) { - // if byte 4,5,6,7 - Index += 0x10; - } - if (Byte & 0x02) { - // if byte 2,3,6,7 - Index++; - } - Offset = 16 * (Byte % 2); - break; - - case AccessRdDqsDly: - case AccessWrDatDly: - Index += (Dimm * 0x100); - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. - case AccessPhRecDly: - Index += (Byte / 4); - Offset = 8 * (Byte % 4); - break; - default: - Offset = 0; - IDS_ERROR_TRAP; - } - - Address = Index; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - - if (IsSet) { - if (TrnDly == AccessPhRecDly) { - Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; - } - - Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset))); - MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - - if (TrnDly == AccessPhRecDly) { - NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; - } - // Gross WrDatDly and WrDqsDly cannot be larger than 4 - ASSERT (((TrnDly == AccessWrDatDly) || (TrnDly == AccessWrDqsDly)) ? (NBPtr->IsSupported[WLNegativeDelay] || (Field < 0xA0)) : TRUE); - } else { - Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF); - } - - return Value; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets or set DQS timing during training. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - type of delay to be set - * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * @param[in] Field - Value to be programmed - * @param[in] IsSet - Indicates if the function will set or get - * - * @return value read, if the function is used as a "get" - */ - -UINT32 -MemNcmnGetSetTrainDlyUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar, - IN UINT16 Field - ) -{ - UINT16 Index; - UINT16 Offset; - UINT32 Value; - UINT32 Address; - UINT8 Dimm; - UINT8 Rank; - UINT8 Byte; - UINT8 Nibble; - UINT8 DimmNibble; - - Dimm = DRBN_DIMM (DrbnVar); - Rank = DRBN_RANK (DrbnVar); - Byte = DRBN_BYTE (DrbnVar); - Nibble = DRBN_NBBL (DrbnVar); - DimmNibble = DRBN_DIMM_NBBL (DrbnVar); - - ASSERT (Dimm < 4); - ASSERT (Byte <= ECC_DLY); - if ((Byte == ECC_DLY) && !NBPtr->MCTPtr->Status[SbEccDimms]) { - // When ECC is not enabled - if (IsSet) { - // On write, ignore - return 0; - } else { - // On read, redirect to byte 0 to correct fence averaging - Byte = 0; - } - } - - switch (TrnDly) { - case AccessRcvEnDly: - Index = 0x10; - break; - case AccessWrDqsDly: - Index = 0x30; - break; - case AccessWrDatDly: - Index = 0x01; - break; - case AccessRdDqsDly: - Index = 0x05; - break; - case AccessRdDqs__Dly: - Index = 0x00; - break; - case AccessPhRecDly: - Index = 0x50; - break; - default: - Index = 0; - IDS_ERROR_TRAP; - } - - switch (TrnDly) { - case AccessRcvEnDly: - case AccessWrDqsDly: - Index += (Dimm * 3); - if (Byte & 0x04) { - // if byte 4,5,6,7 - Index += 0x10; - } - if (Byte & 0x02) { - // if byte 2,3,6,7 - Index++; - } - if (Byte > 7) { - Index += 2; - } - Offset = 16 * (Byte % 2); - Index |= (Rank << 8); - Index |= (Nibble << 9); - Address = Index; - break; - - case AccessRdDqsDly: - case AccessWrDatDly: - - if (NBPtr->IsSupported[DimmBasedOnSpeed]) { - if (NBPtr->DCTPtr->Timings.Speed < DDR800_FREQUENCY) { - // if DDR speed is below 800, use DIMM 0 delays for all DIMMs. - Dimm = 0; - } - } - - Index += (Dimm * 0x100); - if (Nibble) { - if (Rank) { - Index += 0xA0; - } else { - Index += 0x70; - } - } else if (Rank) { - Index += 0x60; - } - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. - case AccessPhRecDly: - Index += (Byte / 4); - Offset = 8 * (Byte % 4); - Address = Index; - break; - case AccessRdDqs__Dly: - Address = 0x0D0F0000; - Index += (DimmNibble >> 1) * 0x100; - Index += 0x20; - Index = Index + Dimm; - Offset = 4 * ((DimmNibble & 0x01) * 2); - Address += Index; - break; - default: - Offset = 0; - IDS_ERROR_TRAP; - Address = Index; - } - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - if (TrnDly == AccessRdDqsDly) { - NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] (NBPtr, &Offset); - } - - if (IsSet) { - if (TrnDly == AccessPhRecDly) { - Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; - } - if (TrnDly != AccessRdDqs__Dly) { - Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x3FF : 0xFF) << Offset))); - } else { - Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) 0x1F << Offset))); - } - MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - if (TrnDly == AccessPhRecDly) { - NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; - } - } else { - if (TrnDly != AccessRdDqs__Dly) { - Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x3FF : 0xFF); - } else { - Value = (Value >> Offset) & (UINT32) (0x1F); - } - } - return Value; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes the training pattern. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return AGESA_STATUS - Result - * AGESA_SUCCESS - Training pattern is ready to use - * AGESA_ERROR - Unable to initialize the pattern. - */ - -AGESA_STATUS -MemNTrainingPatternInitNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - TRAIN_PATTERN TrainPattern; - AGESA_STATUS Status; - - TechPtr = NBPtr->TechPtr; - TrainPattern = 0; - // - // Check the training type - // - if (TechPtr->TrainingType == TRN_DQS_POSITION) { - // - // DQS Position Training - // - if (NBPtr->PosTrnPattern == POS_PATTERN_256B) { - // - // 256 Bit pattern - // - if (NBPtr->MCTPtr->Status[Sb128bitmode]) { - TrainPattern = TestPatternJD256B; - TechPtr->PatternLength = 64; - } else { - TrainPattern = TestPatternJD256A; - TechPtr->PatternLength = 32; - } - } else { - // - // 72 bit pattern will be used if PosTrnPattern is not specified - // - if (NBPtr->MCTPtr->Status[Sb128bitmode]) { - TrainPattern = TestPatternJD1B; - TechPtr->PatternLength = 18; - } else { - TrainPattern = TestPatternJD1A; - TechPtr->PatternLength = 9; - } - } - } else if (TechPtr->TrainingType == TRN_MAX_READ_LATENCY) { - // - // Max Read Latency Training - // - TrainPattern = TestPatternML; - TechPtr->PatternLength = (NBPtr->MCTPtr->Status[Sb128bitmode]) ? 6 : 3; - } else { - // - // Error - TechPtr->Training Type must be set to one of the types handled in this function - // - ASSERT (FALSE); - } - // - // Allocate training buffer - // - AllocHeapParams.RequestedBufferSize = (TechPtr->PatternLength * 64 * 2) + 16; - AllocHeapParams.BufferHandle = AMD_MEM_TRAIN_BUFFER_HANDLE; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader); - ASSERT (Status == AGESA_SUCCESS); - if (Status != AGESA_SUCCESS) { - return Status; - } - TechPtr->PatternBufPtr = AllocHeapParams.BufferPtr; - AlignPointerTo16Byte (&TechPtr->PatternBufPtr); - TechPtr->TestBufPtr = TechPtr->PatternBufPtr + (TechPtr->PatternLength * 64); - - // Prepare training pattern - MemUFillTrainPattern (TrainPattern, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64); - - return Status; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determined the settings for the Reliable Read/Write engine - * for each specific type of training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *OptParam - Pointer to an Enum of TRAINING_TYPE - * - * @return TRUE - */ - -BOOLEAN -MemNSetupHwTrainingEngineUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *OptParam - ) -{ - TRAINING_TYPE TrnType; - RRW_SETTINGS *Rrw; - - TrnType = *(TRAINING_TYPE*) OptParam; - Rrw = &NBPtr->RrwSettings; - // - // Common Settings - // - Rrw->TgtBankAddressA = CPG_BANK_ADDRESS_A; - Rrw->TgtRowAddressA = CPG_ROW_ADDRESS_A; - Rrw->TgtColAddressA = CPG_COL_ADDRESS_A; - Rrw->TgtBankAddressB = CPG_BANK_ADDRESS_B; - Rrw->TgtRowAddressB = CPG_ROW_ADDRESS_B; - Rrw->TgtColAddressB = CPG_COL_ADDRESS_B; - Rrw->CompareMaskHigh = CPG_COMPARE_MASK_HI; - Rrw->CompareMaskLow = CPG_COMPARE_MASK_LOW; - Rrw->CompareMaskEcc = CPG_COMPARE_MASK_ECC; - - switch (TrnType) { - case TRN_RCVR_ENABLE: - // - // Receiver Enable Training - // - NBPtr->TechPtr->PatternLength = 192; - break; - case TRN_MAX_READ_LATENCY: - // - // Max Read Latency Training - // - Rrw->CmdTgt = CMD_TGT_A; - NBPtr->TechPtr->PatternLength = 32; - Rrw->DataPrbsSeed = PRBS_SEED_32; - break; - case TRN_DQS_POSITION: - // - // Read/Write DQS Position training - // - Rrw->CmdTgt = CMD_TGT_AB; - NBPtr->TechPtr->PatternLength = 256; - Rrw->DataPrbsSeed = PRBS_SEED_256; - break; - default: - ASSERT (FALSE); - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finalizes the training pattern. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Index - Index of Write Data Delay Value - * @param[in,out] *Value - Write Data Delay Value - * @return BOOLEAN - TRUE - Use the value returned. - * FALSE - No more values in table. - */ - -BOOLEAN -MemNGetApproximateWriteDatDelayNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Index, - IN OUT UINT8 *Value - ) -{ - CONST UINT8 WriteDatDelayValue[] = {0x10, 0x4, 0x8, 0xC, 0x14, 0x18, 0x1C, 0x1F}; - if (Index < GET_SIZE_OF (WriteDatDelayValue)) { - *Value = WriteDatDelayValue[Index]; - return TRUE; - } - return FALSE; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finalizes the training pattern. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return AGESA_STATUS - Result - * AGESA_SUCCESS - Training pattern has been finalized. - * AGESA_ERROR - Unable to initialize the pattern. - */ - -AGESA_STATUS -MemNTrainingPatternFinalizeNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - AGESA_STATUS Status; - // - // Deallocate training buffer - // - Status = HeapDeallocateBuffer (AMD_MEM_TRAIN_BUFFER_HANDLE, &NBPtr->MemPtr->StdHeader); - ASSERT (Status == AGESA_SUCCESS); - return Status; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the number of chipselects per channel. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return - */ - -UINT8 -MemNCSPerChannelNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return MAX_CS_PER_CHANNEL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the number of Chipselects controlled by each set - * of Delay registers under current conditions. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return - */ - -UINT8 -MemNCSPerDelayNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - return MAX_CS_PER_DELAY; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the minimum data eye width in 32nds of a UI for - * the type of data eye(Rd/Wr) that is being trained. This value will - * be the minimum number of consecutive delays that yield valid data. - * Uses TechPtr->Direction to determine read or write. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return - */ - -UINT8 -MemNMinDataEyeWidthNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 MinRdDataeye; - UINT8 MinWrDataeye; - UINT8 *MinRdWrDataeyePtr; - - MinRdWrDataeyePtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MIN_RD_WR_DATAEYE_WIDTH, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, - &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader)); - - if (NBPtr->TechPtr->Direction == DQS_READ_DIR) { - if (MinRdWrDataeyePtr != NULL) { - MinRdDataeye = MinRdWrDataeyePtr[0]; - return MinRdDataeye; - } else { - return MIN_RD_DATAEYE_WIDTH_NB; - } - } else { - if (MinRdWrDataeyePtr != NULL) { - MinWrDataeye = MinRdWrDataeyePtr[1]; - return MinWrDataeye; - } else { - return MIN_WR_DATAEYE_WIDTH_NB; - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs the phy registers according to the desired phy VDDIO voltage level - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNPhyVoltageLevelNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BIT_FIELD_NAME BitField; - BIT_FIELD_NAME BFEnd; - UINT16 BFValue; - UINT16 RegValue; - - BFValue = (UINT16) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage) << 3; - BFEnd = NBPtr->IsSupported[ProgramCsrComparator] ? BFCsrComparator : BFCmpVioLvl; - - for (BitField = BFDataRxVioLvl; BitField <= BFEnd; BitField++) { - RegValue = BFValue; - if (BitField == BFCsrComparator) { - RegValue >>= (3 - 2); - // Setting this bit in DCT0 adjusts the comparator for DCT0 and DCT1. Setting this bit in DCT1 has no effect. - NBPtr->SwitchDCT (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BitField, RegValue); - break; - } else if (BitField == BFCmpVioLvl) { - RegValue <<= (14 - 3); - // Must set this bit on DCT0 even when DCT0 has no memory - NBPtr->SwitchDCT (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BitField, RegValue); - } - MemNBrdcstSetNb (NBPtr, BitField, RegValue); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function adjusts Avg PRE value of Phy fence training according to specific CPU family. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *Value16 - Pointer to the value that we want to adjust - * - */ -VOID -MemNPFenceAdjustUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT INT16 *Value16 - ) -{ - *Value16 += 2; //The Avg PRE value is subtracted by 6 only. -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DDR phy compensation logic - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitPhyCompClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // Slew rate table array [x][y][z] - // array[0]: slew rate for VDDIO 1.5V - // array[1]: slew rate for VDDIO 1.35V - // array[2]: slew rate for VDDIO 1.25V - // array[x][y]: slew rate for a certain frequency - // array[x][y][0]: frequency mask for current entry - CONST STATIC UINT16 TxPrePNDataDqs[3][3][5] = { - {{ (UINT16) DDR800, 0x924, 0x924, 0x924, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}, - {{ (UINT16) DDR800, 0xFF6, 0xB6D, 0xB6D, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}, - {{ (UINT16) DDR800, 0xFF6, 0xDAD, 0xDAD, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}} - }; - CONST STATIC UINT16 TxPrePNCmdAddr[3][3][5] = { - {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492}, - { (UINT16) (DDR1066 + DDR1333), 0x6DB, 0x6DB, 0x6DB, 0x6DB}, - { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0xB6D, 0xB6D}}, - {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492}, - { (UINT16) (DDR1066 + DDR1333), 0x924, 0x6DB, 0x6DB, 0x6DB}, - { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0x924, 0x924}}, - {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492}, - { (UINT16) (DDR1066 + DDR1333), 0xDAD, 0x924, 0x6DB, 0x492}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xDAD, 0xB64, 0xB64}} - }; - CONST STATIC UINT16 TxPrePNClock[3][3][5] = { - {{ (UINT16) DDR800, 0x924, 0x924, 0x924, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xB6D}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}, - {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xDAD}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xDAD}}, - {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924}, - { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, - { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}} - }; - - CONST PHY_COMP_INIT_CLIENTNB PhyCompInitBitField[] = { - // 3. Program TxPreP/TxPreN for Data and DQS according toTable 14 if VDDIO is 1.5V or Table 15 if 1.35V. - // A. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0[A,6]={0000b, TxPreP, TxPreN}. - // B. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]02={1000b, TxPreP, TxPreN}. - {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, TxPrePNDataDqs}, - {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, TxPrePNDataDqs}, - {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, TxPrePNDataDqs}, - // 4. Program TxPreP/TxPreN for Cmd/Addr according toTable 16 if VDDIO is 1.5V or Table 17 if 1.35V. - // A. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0][12,0E,0A,06]={0000b, TxPreP, TxPreN}. - // B. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0]02={1000b, TxPreP, TxPreN}. - {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, TxPrePNCmdAddr}, - {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, TxPrePNCmdAddr}, - {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, TxPrePNCmdAddr}, - {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, TxPrePNCmdAddr}, - {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, TxPrePNCmdAddr}, - // 5. Program TxPreP/TxPreN for Clock according toTable 18 if VDDIO is 1.5V or Table 19 if 1.35V. - // A. Program D18F2x[1,0]9C_x0D0F_2[1:0]02={1000b, TxPreP, TxPreN}. - {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock1TxPreDriverCalPad0, 8, TxPrePNClock} - }; - - BIT_FIELD_NAME CurrentBitField; - UINT16 SpeedMask; - CONST UINT16 (*TxPrePNArray)[5]; - UINT8 Voltage; - UINT8 i; - UINT8 j; - UINT8 k; - UINT8 Dct; - - Dct = NBPtr->Dct; - NBPtr->SwitchDCT (NBPtr, 0); - // 1. Program D18F2x[1,0]9C_x0D0F_E003[DisAutoComp, DisablePreDriverCal] = {1b, 1b}. - MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x6000); - NBPtr->SwitchDCT (NBPtr, Dct); - - SpeedMask = (UINT16) 1 << (NBPtr->DCTPtr->Timings.Speed / 66); - Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage); - - for (j = 0; j < GET_SIZE_OF (PhyCompInitBitField); j ++) { - i = (UINT8) MemNGetBitFieldNb (NBPtr, PhyCompInitBitField[j].IndexBitField); - TxPrePNArray = PhyCompInitBitField[j].TxPrePN[Voltage]; - for (k = 0; k < 3; k ++) { - if ((TxPrePNArray[k][0] & SpeedMask) != 0) { - for (CurrentBitField = PhyCompInitBitField[j].StartTargetBitField; CurrentBitField <= PhyCompInitBitField[j].EndTargetBitField; CurrentBitField ++) { - MemNSetBitFieldNb (NBPtr, CurrentBitField, ((PhyCompInitBitField[j].ExtraValue << 12) | TxPrePNArray[k][i + 1])); - } - break; - } - } - ASSERT (k < 3); - } - - NBPtr->FamilySpecificHook[ForceAutoComp] (NBPtr, NBPtr); -} - -/*----------------------------------------------------------------------------- - * - * - * This function re-enable phy compensation. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNReEnablePhyCompNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Dct; - - Dct = NBPtr->Dct; - - NBPtr->SwitchDCT (NBPtr, 0); - // Clear DisableCal and set DisablePredriverCal - MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x2000); - NBPtr->SwitchDCT (NBPtr, Dct); - - return TRUE; -} - -/*----------------------------------------------------------------------------- - * - * - * This function calculates the value of WrDqDqsEarly and programs it into - * the DCT and adds it to the WrDqsGrossDelay of each byte lane on each - * DIMM of the channel. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNCalcWrDqDqsEarlyUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - MEM_TECH_BLOCK *TechPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - UINT8 Dimm; - UINT8 ByteLane; - UINT8 *WrDqsDlysPtr; - UINT8 WrDqDqsEarly; - - ASSERT ((NBPtr->IsSupported[WLSeedAdjust]) && (NBPtr->IsSupported[WLNegativeDelay])); - - TechPtr = NBPtr->TechPtr; - ChannelPtr = NBPtr->ChannelPtr; - DCTPtr = NBPtr->DCTPtr; - - ASSERT (NBPtr != NULL); - ASSERT (ChannelPtr != NULL); - ASSERT (DCTPtr != NULL); - // - // For each DIMM: - // - The Critical Gross Delay (CGD) is the minimum GrossDly of all byte lanes and all DIMMs. - // - If (CGD < 0) Then - // - D18F2xA8_dct[1:0][WrDqDqsEarly] = ABS(CGD) - // - WrDqsGrossDly = GrossDly + WrDqDqsEarly - // - Else - // - D18F2xA8_dct[1:0][WrDqDqsEarly] = 0. - // - WrDqsGrossDly = GrossDly - // - WrDqDqsEarly = 0; - if (TechPtr->WLCriticalDelay < 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCalculating WrDqDqsEarly, adjusting WrDqs.\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMin. Critical Delay: %x\n", TechPtr->WLCriticalDelay); - // We've saved the entire negative delay value, so take the ABS and convert to GrossDly. - WrDqDqsEarly = (UINT8) (0x00FF &((((ABS (TechPtr->WLCriticalDelay)) + 0x1F) / 0x20))); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tWrDqDqsEarly : %02x\n\n", WrDqDqsEarly); - // - // Loop through All WrDqsDlys on all DIMMs - // - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((NBPtr->MCTPtr->Status[SbLrdimms]) ? ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << Dimm)) != 0) : - ((DCTPtr->Timings.CsEnabled & ((UINT16) 3 << (Dimm << 1))) != 0)) { - // - // If LRDIMMs, only include the physical dimms, not logical Dimms - // - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDimm %x:", Dimm); - WrDqsDlysPtr = &(ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ())]); - for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) { - WrDqsDlysPtr[ByteLane] += (WrDqDqsEarly << 5); - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDlysPtr[ByteLane]); - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", WrDqsDlysPtr[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - } - } - MemNSetBitFieldNb (NBPtr, BFWrDqDqsEarly, WrDqDqsEarly); - return TRUE; -} - -/*----------------------------------------------------------------------------- - * - * - * This function forces phy to M0 state - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *OptParam - Optional parameter - * - * @return FALSE - always - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNForcePhyToM0Unb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - // 1. Program D18F2x9C_x0D0F_E013_dct[1:0] = 0118h. - MemNBrdcstSetNb (NBPtr, BFPllRegWaitTime, 0x118); - // 2. Force the phy to M0 with the following sequence: - // A. Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 190h. Restore the default PLL lock time. - MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); - // B. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80800000h. - MemNBrdcstSetNb (NBPtr, BFDramPhyStatusReg, 0x80800000); - NBPtr->SwitchDCT (NBPtr, 0); - // C. Program D18F2x9C_x0D0F_E018_dct[0][PhyPSMasterChannel] = 0. - MemNSetBitFieldNb (NBPtr, BFPhyPSMasterChannel, 0); - // D. Program D18F2x9C_x0000_000B_dct[0] = 40000000h. CH0 only; - MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x40000000); - // E. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80000000h. - MemNBrdcstSetNb (NBPtr, BFDramPhyStatusReg, 0x80000000); - - return FALSE; -} - -/*----------------------------------------------------------------------------- - * - * - * This function sets SkewMemClk before enabling MemClk - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *OptParam - Optional parameter - * - * @return TRUE - always - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNSetSkewMemClkUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Dct; - - // SkewMemClk is set to 1 if all DCTs are enabled, else 0. - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize == 0) { - break; - } - } - MemNSwitchDCTNb (NBPtr, 0); - if (Dct == NBPtr->DctCount) { - MemNSetBitFieldNb (NBPtr, BFSkewMemClk, 0x10); - } else { - MemNSetBitFieldNb (NBPtr, BFSkewMemClk, 0); - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function masks the RdDqsDly Bit 0 before writing to register for UNB. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *Offset - Bit offset of the field to be programmed - * - * @return TRUE - */ -BOOLEAN -MemNAdjustRdDqsDlyOffsetUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *Offset - ) -{ - *(UINT16*) Offset = *(UINT16*) Offset + 1; - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function delays MEMCLK to prevent WrDqs skew due to negative PRE result. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNCalcWrDqDqsEarlyClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - MEM_TECH_BLOCK *TechPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - UINT8 Dimm; - UINT8 ByteLane; - UINT8 *WrDqsDlysPtr; - UINT8 NewClkDllDelay; - UINT16 ClkDllFineDly; - UINT32 AddrCmdTmg; - - TechPtr = NBPtr->TechPtr; - ChannelPtr = NBPtr->ChannelPtr; - DCTPtr = NBPtr->DCTPtr; - - ASSERT (NBPtr != NULL); - ASSERT (ChannelPtr != NULL); - ASSERT (DCTPtr != NULL); - - if (NBPtr->IsSupported[WLNegativeDelay]) { - if (TechPtr->WLCriticalDelay < 0) { - NewClkDllDelay = (UINT8) ABS (TechPtr->WLCriticalDelay); - - // Prepare new delay for MEMCLK - ClkDllFineDly = (UINT16) ((MemNGetBitFieldNb (NBPtr, BFPhyClkDllFine0) & 0xBF60) | NewClkDllDelay); - - // Program bit 7(FenceBit) = 1 if NewClkDllDelay >= > F2x9C[FenceThresholdTxPad], else 0. - ClkDllFineDly |= (NewClkDllDelay >= MemNGetBitFieldNb (NBPtr, BFPhyFence)) ? 0x80 : 0; - - // Apply new delay to both chiplets - MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine0, ClkDllFineDly | 0x4000); - MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine0, ClkDllFineDly); - MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine1, ClkDllFineDly | 0x4000); - MemNSetBitFieldNb (NBPtr, BFPhyClkDllFine1, ClkDllFineDly); - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tShift MemClk, AddrCmd, CsOdt, Cke by %d to eliminate negative WL\n", NewClkDllDelay); - - // - // Adjust AddrCmd/CsOdt/Cke timing by amount MemClk was delayed - // - AddrCmdTmg = MemNGetBitFieldNb (NBPtr, BFAddrTmgControl); - AddrCmdTmg += (NewClkDllDelay << 16) | (NewClkDllDelay << 8) | NewClkDllDelay; - AddrCmdTmg &= 0x003F3F3F; - MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, AddrCmdTmg); - - // - // Adjust all WrDqsDlys on all DIMMs of the current channel - // - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCS%d\n\t\t\tWrDqs:", Dimm << 1); - WrDqsDlysPtr = &(ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ())]); - for (ByteLane = 0; ByteLane < 8; ByteLane++) { - WrDqsDlysPtr[ByteLane] = (UINT8) (WrDqsDlysPtr[ByteLane] + NewClkDllDelay); - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDlysPtr[ByteLane]); - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", WrDqsDlysPtr[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - } - } - } - - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes RxEn Delays for RxEn seedless training - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNInitializeRxEnSeedlessTrainingUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 ByteLane; - // Save original PRE based RxEnDly for RxEn Seedless training - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - NBPtr->TechPtr->RxOrig[ByteLane] = NBPtr->ChannelPtr->RcvEnDlys[(NBPtr->TechPtr->ChipSel >> 1) * NBPtr->TechPtr->DlyTableWidth () + ByteLane]; - } - return TRUE; -} -/*----------------------------------------------------------------------------- - * - * - * This function checks each bytelane for no window error. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNTrackRxEnSeedlessRdWrNoWindBLErrorUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - MemTTrackRxEnSeedlessRdWrNoWindBLError (NBPtr->TechPtr, OptParam); - return TRUE; -} -/*----------------------------------------------------------------------------- - * - * - * This function checks each bytelane for small window error. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNTrackRxEnSeedlessRdWrSmallWindBLErrorUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - MemTTrackRxEnSeedlessRdWrSmallWindBLError (NBPtr->TechPtr, OptParam); - return TRUE; -} -/*----------------------------------------------------------------------------- - * - * - * This function initializes a ByteLaneError error. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNInitialzeRxEnSeedlessByteLaneErrorUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 ByteLane; - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - NBPtr->TechPtr->ByteLaneError[ByteLane] = FALSE; // All Bytelanes have no errors - } - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets phy power saving related settings in different MPstate context. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return none - * ---------------------------------------------------------------------------- - */ -VOID -MemNPhyPowerSavingMPstateUnb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - STATIC UINT8 Sequence[] = {8, 4, 3, 5, 2, 6, 1, 7, 0}; - UINT16 DllPower[9]; - UINT8 NumLanes; - UINT8 DllWakeTime; - UINT8 MaxRxStggrDly; - UINT8 MinRcvEnGrossDly; - UINT8 MinWrDatGrossDly; - UINT8 dRxStggrDly; - UINT8 dTxStggrDly; - UINT8 TempStggrDly; - UINT8 MaxTxStggrDly; - UINT8 Tcwl; - UINT8 i; - - IDS_HDT_CONSOLE (MEM_FLOW, "Start Phy power saving setting for memory Pstate %d\n", NBPtr->MemPstate); - // 4. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyU] = 1b. - // 5. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyL] = 1b. - // 6. D18F2x9C_x0D0F_0[F,7:0][53,13]_dct[1:0][RxDqsUDllPowerDown] = 1. - MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x83); - // 7. D18F2x9C_x0D0F_812F_dct[1:0][PARTri] = ~D18F2x90_dct[1:0][ParEn]. - // 8. D18F2x9C_x0D0F_812F_dct[1:0][Add17Tri, Add16Tri] = {1b, 1b} - if (NBPtr->MemPstate == MEMORY_PSTATE0) { - MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 0xA1); - } - // 9. IF (DimmsPopulated == 1)&& ((D18F2x9C_x0000_0000_dct[1:0]_mp[1:0][CkeDrvStren]==010b) || - // (D18F2x9C_x0000_0000_dct[1:0]_mp[1:0][CkeDrvStren]==011b)) THEN THEN - // program D18F2x9C_x0D0F_C0[40,00]_dct[1:0][LowPowerDrvStrengthEn] = 1 - // ELSE program D18F2x9C_x0D0F_C0[40,00]_dct[1:0][LowPowerDrvStrengthEn] = 0 ENDIF. - if ((NBPtr->ChannelPtr->Dimms == 1) && ((MemNGetBitFieldNb (NBPtr, BFCkeDrvStren) == 2) || (MemNGetBitFieldNb (NBPtr, BFCkeDrvStren) == 3))) { - MemNSetBitFieldNb (NBPtr, BFReserved00C, 0x100); - } - // 10. Program D18F2x9C_x0D0F_0[F,7:0][50,10]_dct[1:0][EnRxPadStandby] = IF - // (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz) THEN 1 ELSE 0 ENDIF. - MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0); - // 11. Program D18F2x9C_x0000_000D_dct[1:0]_mp[1:0] as follows: - // If (DDR rate < = 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h - // else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h. - if (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) { - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 8); - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 8); - } else { - MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 7); - MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 7); - } - // TxCPUpdPeriod = RxCPUpdPeriod = 011b. - MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 3); - MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 3); - // TxDLLWakeupTime = RxDLLWakeupTime = 11b. - MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3); - MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3); - - if (NBPtr->IsSupported[DllStaggerEn]) { - // 12. Program D18F2x9C_x0D0F_0[F,7:0][5C,1C]_dct[1:0] as follows. - // Let Numlanes = 8. = 9 with ECC. - NumLanes = (NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8; - // RxDllStggrEn = TxDllStggrEn = 1. - for (i = 0; i < 9; i ++) { - DllPower[i] = 0x8080; - } - // If (DDR rate > = 1866) DllWakeTime = 1, Else DllWakeTime = 0. - DllWakeTime = (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY) ? 1 : 0; - // Let MaxRxStggrDly = (Tcl*2) + MIN(DqsRcvEnGrossDelay for all byte lanes (see D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 4. - MinRcvEnGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessRcvEnDly, FALSE); - ASSERT ((NBPtr->DCTPtr->Timings.CasL * 2 + MinRcvEnGrossDly) >= 4); - MaxRxStggrDly = NBPtr->DCTPtr->Timings.CasL * 2 + MinRcvEnGrossDly - 4; - // Let (real) dRxStggrDly = (MaxRxStggrDly - DllWakeTime) / (Numlanes - 1). - ASSERT (MaxRxStggrDly >= DllWakeTime); - dRxStggrDly = (MaxRxStggrDly - DllWakeTime) / (NumLanes - 1); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMinimum RcvEnGrossDly: 0x%02x MaxRxStggrDly: 0x%02x dRxStggrDly: 0x%02x\n", MinRcvEnGrossDly, MaxRxStggrDly, dRxStggrDly); - // For each byte lane in the ordered sequence {8, 4, 3, 5, 2, 6, 1, 7, 0}, program RxDllStggrDly[5:0] = an - // increasing value, starting with 0 for the first byte lane in the sequence and increasing at a rate of dRxStggrDly - // for each subsequent byte lane. Convert the real to integer by rounding down or using C (int) typecast after linearization. - i = 9 - NumLanes; - TempStggrDly = 0; - for (; i < 9; i ++) { - DllPower[Sequence[i]] |= ((TempStggrDly & 0x3F) << 8); - TempStggrDly = TempStggrDly + dRxStggrDly; - } - - // Let MaxTxStggrDly = (Tcwl*2) + MIN(MIN (WrDatGrossDly for all byte lanes (see - // D18F2x9C_x0000_0[3:0]0[2:1]_dct[1:0]_mp[1:0])), MIN(DqsRcvEnGrossDelay for all byte lanes (see - // D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 4. - Tcwl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcwl); - MinWrDatGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessWrDatDly, FALSE); - MaxTxStggrDly = Tcwl * 2 + MIN (MinRcvEnGrossDly, MinWrDatGrossDly) - 4; - // Let dTxStggrDly = (MaxTxStggrDly - DllWakeTime) / (Numlanes - 1). - ASSERT (MaxTxStggrDly >= DllWakeTime); - dTxStggrDly = (MaxTxStggrDly - DllWakeTime) / (NumLanes - 1); - // For each byte lane in the ordered sequence {8, 4, 3, 5, 2, 6, 1, 7, 0}, program TxDllStggrDly[5:0] = an - // increasing integer value, starting with 0 for the first byte lane in the sequence and increasing at a rate of - // dTxStggrDly for each subsequent byte lane. - IDS_HDT_CONSOLE (MEM_FLOW, "\tMinimum WrDatGrossDly: 0x%02x MaxTxStggrDly: 0x%02x dTxStggrDly: 0x%02x\n", MinWrDatGrossDly, MaxTxStggrDly, dTxStggrDly); - i = 9 - NumLanes; - TempStggrDly = 0; - for (; i < 9; i ++) { - DllPower[Sequence[i]] |= (TempStggrDly & 0x3F); - TempStggrDly = TempStggrDly + dTxStggrDly; - } - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tByte Lane : ECC 07 06 05 04 03 02 01 00\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tDll Power : %04x %04x %04x %04x %04x %04x %04x %04x %04x\n", - DllPower[8], DllPower[7], DllPower[6], DllPower[5], DllPower[4], DllPower[3], DllPower[2], DllPower[1], DllPower[0]); - - for (i = 0; i < NumLanes; i ++) { - MemNSetBitFieldNb (NBPtr, BFDataByteDllPowerMgnByte0 + i, (MemNGetBitFieldNb (NBPtr, BFDataByteDllPowerMgnByte0 + i) & 0x4040) | DllPower[i]); - } - } - // 13. Program D18F2x248_dct[1:0]_mp[1:0] and then D18F2x9C_x0D0F_0[F,7:0][53,13]_dct[1:0] as follows: - // For M1 context program RxChMntClkEn=RxSsbMntClkEn=0. - // For M0 context program RxChMntClkEn=RxSsbMntClkEn=1. - if (NBPtr->MemPstate == MEMORY_PSTATE1) { - MemNSetBitFieldNb (NBPtr, BFRxChMntClkEn, 0); - MemNSetBitFieldNb (NBPtr, BFRxSsbMntClkEn, 0); - } else { - MemNSetBitFieldNb (NBPtr, BFRxChMntClkEn, 1); - MemNSetBitFieldNb (NBPtr, BFRxSsbMntClkEn, 0x100); - } - - IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function resets RxFifo pointer during Read DQS training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *OptParam - Optional parameter - * - * @return TRUE - */ - -BOOLEAN -MemNResetRxFifoPtrClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - if (NBPtr->TechPtr->Direction == DQS_READ_DIR) { - MemNSetBitFieldNb (NBPtr, BFRxPtrInitReq, 1); - MemNPollBitFieldNb (NBPtr, BFRxPtrInitReq, 0, PCI_ACCESS_TIMEOUT, FALSE); - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * This function adjusts the Phase Mask based on ECC. - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNAdjust2DPhaseMaskBasedOnEccUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - NBPtr->PhaseLaneMask = NBPtr->PhaseLaneMask & (UINT32) (NBPtr->MCTPtr->Status[SbEccDimms] ? 0x0FFFF : 0x3FFFF); - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnreg.c deleted file mode 100644 index cbf2dc78e1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnreg.c +++ /dev/null @@ -1,551 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnreg.c - * - * Common Northbridge register access functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "merrhdl.h" -#include "heapManager.h" -#include "Filecode.h" -#include "GeneralServices.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_MNREG_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the current DCT to work on. - * Should be called before accessing a certain DCT - * All data structures will be updated to point to the current DCT - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Dct - ID of the target DCT - * - */ - -VOID -MemNSwitchDCTNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct - ) -{ - ASSERT (NBPtr->DctCount > Dct); - // - // Set the DctCfgSel to new DCT - // - NBPtr->FamilySpecificHook[DCTSelectSwitch] (NBPtr, &Dct); - NBPtr->Dct = Dct; - NBPtr->MCTPtr->Dct = NBPtr->Dct; - NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]); - NBPtr->PsPtr = &(NBPtr->PSBlock[NBPtr->Dct]); - NBPtr->DctCachePtr = &(NBPtr->DctCache[NBPtr->Dct]); - - MemNSwitchChannelNb (NBPtr, NBPtr->Channel); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is used by families that use a separate DctCfgSel bit to - * select the current DCT which will be accessed by function 2. - * NOTE: This function must be called BEFORE the NBPtr->Dct variable is - * updated. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Dct - Pointer to ID of the target DCT - * - */ - -BOOLEAN -MemNDctCfgSelectUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *Dct - ) -{ - // - // Sanity check the current DctCfgSel setting - // - ASSERT (NBPtr->Dct == NBPtr->GetBitField (NBPtr, BFDctCfgSel)); - // - // Set the DctCfgSel to new DCT - // - NBPtr->SetBitField (NBPtr, BFDctCfgSel, *(UINT8*)Dct); - - return TRUE; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the current channel to work on. - * Should be called before accessing a certain channel - * All data structures will be updated to point to the current channel - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Channel - ID of the target channel - * - */ - -VOID -MemNSwitchChannelNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Channel - ) -{ - NBPtr->Channel = Channel ? 1 : 0; - NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets a bit field from PCI register - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Field name - * - * @return Bit field value - */ - -UINT32 -MemNGetBitFieldNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN BIT_FIELD_NAME FieldName - ) -{ - UINT32 Value; - - ASSERT (FieldName < BFEndOfList); - Value = NBPtr->MemNCmnGetSetFieldNb (NBPtr, 0, FieldName, 0); - return Value; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets a bit field from PCI register - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Field name - * @param[in] Field - Value to be stored in PCT register - * - */ - -VOID -MemNSetBitFieldNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ) -{ - ASSERT (FieldName < BFEndOfList); - NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Check if bitfields of all enabled DCTs on a die have the expected value. Ignore - * DCTs that are disabled. - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Bit Field name - * @param[in] Field - Value to be checked - * - * @return TRUE - All enabled DCTs have the expected value on the bitfield. - * @return FALSE - Not all enabled DCTs have the expected value on the bitfield. - * - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemNBrdcstCheckNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ) -{ - UINT8 Dct; - UINT8 CurrentDCT; - Dct = NBPtr->Dct; - for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) { - MemNSwitchDCTNb (NBPtr, CurrentDCT); - if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) { - if (MemNGetBitFieldNb (NBPtr, FieldName) != Field) { - MemNSwitchDCTNb (NBPtr, Dct); - return FALSE; - } - } - } - MemNSwitchDCTNb (NBPtr, Dct); - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Set bitfields of all enabled DCTs on a die to a value. Ignore - * DCTs that are disabled. - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Bit Field name - * @param[in] Field - Value to be set - * - * ---------------------------------------------------------------------------- - */ -VOID -MemNBrdcstSetNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ) -{ - UINT8 Dct; - UINT8 CurrentDCT; - Dct = NBPtr->Dct; - for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) { - MemNSwitchDCTNb (NBPtr, CurrentDCT); - if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) { - MemNSetBitFieldNb (NBPtr, FieldName, Field); - } - } - MemNSwitchDCTNb (NBPtr, Dct); -} - -/*-----------------------------------------------------------------------------*/ -/** - * This function calculates the memory channel index relative to the - * socket, taking the Die number, the Dct, and the channel. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Dct - * @param[in] Channel - * - */ -UINT8 -MemNGetSocketRelativeChannelNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct, - IN UINT8 Channel - ) -{ - return ((NBPtr->MCTPtr->DieId * NBPtr->DctCount) + Dct); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Poll a bitfield. If the bitfield does not get set to the target value within - * specified microseconds, it times out. - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Bit Field name - * @param[in] Field - Value to be set - * @param[in] MicroSecond - Number of microsecond to wait - * @param[in] IfBroadCast - Need to broadcast to both DCT or not - * - * ---------------------------------------------------------------------------- - */ -VOID -MemNPollBitFieldNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field, - IN UINT32 MicroSecond, - IN BOOLEAN IfBroadCast - ) -{ - BOOLEAN ErrorRecovery; - BOOLEAN IgnoreErr; - UINT8 ExcludeDCT; - UINT16 ExcludeChipSelMask; - UINT32 EventInfo; - UINT64 InitTSC; - UINT64 CurrentTSC; - UINT64 TimeOut; - AGESA_STATUS EventClass; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - BOOLEAN TimeoutEn; - - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - ExcludeDCT = EXCLUDE_ALL_DCT; - ExcludeChipSelMask = EXCLUDE_ALL_CHIPSEL; - TimeoutEn = TRUE; - IDS_TIMEOUT_CTL (&TimeoutEn); - - CurrentTSC = 0; - LibAmdMsrRead (TSC, &InitTSC, &MemPtr->StdHeader); - TimeOut = InitTSC + ((UINT64) MicroSecond * MemPtr->TscRate); - - while ((CurrentTSC < TimeOut) || !TimeoutEn) { - if (IfBroadCast) { - if (NBPtr->BrdcstCheck (NBPtr, FieldName, Field)) { - break; - } - } else { - if (MemNGetBitFieldNb (NBPtr, FieldName) == Field) { - break; - } - } - LibAmdMsrRead (TSC, &CurrentTSC, &MemPtr->StdHeader); - } - - if ((CurrentTSC >= TimeOut) && TimeoutEn) { - ErrorRecovery = TRUE; - IgnoreErr = FALSE; - IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, &MemPtr->StdHeader); - IDS_OPTION_HOOK (IDS_MEM_IGNORE_ERROR, &IgnoreErr, &MemPtr->StdHeader); - - // Default event class - // If different event class is needed in one entry, override it. - EventClass = AGESA_ERROR; - switch (FieldName) { - case BFDramEnabled: - EventInfo = MEM_ERROR_DRAM_ENABLED_TIME_OUT; - IDS_HDT_CONSOLE (MEM_FLOW, "\tDramEnabled bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFDctAccessDone: - EventInfo = MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - IDS_HDT_CONSOLE (MEM_FLOW, "\tDctAccessDone bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFSendCtrlWord: - EventInfo = MEM_ERROR_SEND_CTRL_WORD_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - IDS_HDT_CONSOLE (MEM_FLOW, "\tSendCtrlWord bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFPrefDramTrainMode: - EventInfo = MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - IDS_HDT_CONSOLE (MEM_FLOW, "\tPrefDramTrainMode bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFEnterSelfRef: - EventInfo = MEM_ERROR_ENTER_SELF_REF_TIME_OUT; - IDS_HDT_CONSOLE (MEM_FLOW, "\tEnterSelfRef bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFFreqChgInProg: - EventInfo = MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - IDS_HDT_CONSOLE (MEM_FLOW, "\tFreqChgInProg bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFExitSelfRef: - EventInfo = MEM_ERROR_EXIT_SELF_REF_TIME_OUT; - IDS_HDT_CONSOLE (MEM_FLOW, "\tExitSelfRef bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFSendMrsCmd: - EventInfo = MEM_ERROR_SEND_MRS_CMD_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - IDS_HDT_CONSOLE (MEM_FLOW, "\tSendMrsCmd bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFSendZQCmd: - EventInfo = MEM_ERROR_SEND_ZQ_CMD_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - IDS_HDT_CONSOLE (MEM_FLOW, "\tSendZQCmd bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFDctExtraAccessDone: - EventInfo = MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - IDS_HDT_CONSOLE (MEM_FLOW, "\tDctExtraAccessDone bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFMemClrBusy: - EventInfo = MEM_ERROR_MEM_CLR_BUSY_TIME_OUT; - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClrBusy bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFMemCleared: - EventInfo = MEM_ERROR_MEM_CLEARED_TIME_OUT; - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemCleared bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - case BFFlushWr: - EventInfo = MEM_ERROR_FLUSH_WR_TIME_OUT; - ExcludeDCT = NBPtr->Dct; - IDS_HDT_CONSOLE (MEM_FLOW, "\tFlushWr bitfield times out.\n"); - ASSERT (ErrorRecovery || IgnoreErr); - break; - default: - EventClass = 0; - EventInfo = 0; - IDS_ERROR_TRAP; - } - - PutEventLog (EventClass, EventInfo, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &MemPtr->StdHeader); - SetMemError (EventClass, MCTPtr); - if (!MemPtr->ErrorHandling (MCTPtr, ExcludeDCT, ExcludeChipSelMask, &MemPtr->StdHeader)) { - ASSERT (FALSE); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function changes memory Pstate context - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] MemPstate - Target Memory Pstate - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -VOID -MemNChangeMemPStateContextNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSTATE MemPstate - ) -{ - UINT8 PSMasterChannel; - UINT8 Dct; - - ASSERT ((MemPstate == 0) || (MemPstate == 1)); - ASSERT (NBPtr->MemPstate == ((MemNGetBitFieldNb (NBPtr, BFMemPsSel) == 0) ? MEMORY_PSTATE0 : MEMORY_PSTATE1)); - - IDS_HDT_CONSOLE (MEM_FLOW, "\nGo to Memory Pstate Conext %d\n", MemPstate); - Dct = NBPtr->Dct; - MemNSwitchDCTNb (NBPtr, 0); - // Figure out what is the master channel - PSMasterChannel = (UINT8) (MemNGetBitFieldNb (NBPtr, BFPhyPSMasterChannel) >> 8); - - // Switch to the master channel to change PStateToAccess - // PStateToAccess is only effective on the master channel - MemNSwitchDCTNb (NBPtr, PSMasterChannel); - MemNSetBitFieldNb (NBPtr, BFMemPsSel, MemPstate); - MemNSetBitFieldNb (NBPtr, BFPStateToAccess, MemPstate << 8); - - NBPtr->MemPstate = (MemPstate == 0) ? MEMORY_PSTATE0 : MEMORY_PSTATE1; - MemNSwitchDCTNb (NBPtr, Dct); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function allocates buffer for NB register table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Handle - Handle for heap allocation for NBRegTable - * - * @return TRUE - Successfully allocates buffer the first time - * @return FALSE - Buffer already allocated or fails to allocate - */ - -BOOLEAN -MemNAllocateNBRegTableNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN NB_REG_TAB_HANDLE Handle - ) -{ - ALLOCATE_HEAP_PARAMS AllocHeapParams; - LOCATE_HEAP_PTR LocHeap; - - // If NBRegTable for this family exists, use it - LocHeap.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Handle, 0, 0); - if (HeapLocateBuffer (&LocHeap, &(NBPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) { - NBPtr->NBRegTable = (TSEFO *) LocHeap.BufferPtr; - return FALSE; - } - - // Allocate new buffer for NBRegTable if it has not been allocated - AllocHeapParams.RequestedBufferSize = sizeof (TSEFO) * BFEndOfList; - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Handle, 0, 0); - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &(NBPtr->MemPtr->StdHeader))) { - ASSERT(FALSE); // NB and Tech Block Heap allocate error - return FALSE; - } - NBPtr->NBRegTable = (TSEFO *)AllocHeapParams.BufferPtr; - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain2.c deleted file mode 100644 index 92d500dc25..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain2.c +++ /dev/null @@ -1,132 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mntrain2.c - * - * Common Northbridge function for training flow for DDR2 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_MNTRAIN2_FILECODE -/* features */ -#include "mftds.h" -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates DQS training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemNDQSTiming2Nb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - - TechPtr = NBPtr->TechPtr; - if (TechPtr->NBPtr->MCTPtr->NodeMemSize) { - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); - AgesaHookBeforeDQSTraining (NBPtr->MCTPtr->SocketId, TechPtr->NBPtr->MemPtr); - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); - //Execute Technology specific training features - if (memTechTrainingFeatDDR2.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) { - if (memTechTrainingFeatDDR2.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn); - if (memTechTrainingFeatDDR2.NonOptimizedSRdWrPosTraining (TechPtr)) { - if (memTechTrainingFeatDDR2.OptimizedSRdWrPosTraining (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn); - if (memTechTrainingFeatDDR2.MaxRdLatencyTraining (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn); - } - } - } - } - } - MemTMarkTrainFail (TechPtr); - } - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain3.c deleted file mode 100644 index d124619455..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mntrain3.c +++ /dev/null @@ -1,244 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mntrain3.c - * - * Common Northbridge function for training flow for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB) - * @e \$Revision: 59563 $ @e \$Date: 2011-09-26 12:06:49 -0600 (Mon, 26 Sep 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_MNTRAIN3_FILECODE -/* features */ -#include "mftds.h" -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemNHwWlPart2Nb ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[]; -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates DQS training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -MemNDQSTiming3Nb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 i; - BOOLEAN Retval; - TechPtr = NBPtr->TechPtr; - Retval = TRUE; - if (TechPtr->NBPtr->MCTPtr->NodeMemSize) { - //Execute Technology specific training features - i = 0; - while (memTrainSequenceDDR3[i].TrainingSequenceEnabled != 0) { - if (memTrainSequenceDDR3[i].TrainingSequenceEnabled (NBPtr)) { - NBPtr->TrainingSequenceIndex = i; - Retval = memTrainSequenceDDR3[i].TrainingSequence (NBPtr); - break; - } - i++; - } - } - return Retval; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates DQS training for Server NB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -memNSequenceDDR3Nb ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_TECH_BLOCK *TechPtr; - UINT8 i; - TechPtr = NBPtr->TechPtr; - i = NBPtr->TrainingSequenceIndex; - if (TechPtr->NBPtr->MCTPtr->NodeMemSize != 0) { - AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); - IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS...\n"); - if (AgesaHookBeforeDQSTraining (NBPtr->MCTPtr->SocketId, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) { - // Right now we do not have anything to do if the callout is implemented - } - AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); - //Execute Technology specific training features - if (memTrainSequenceDDR3[i].MemTechFeatBlock->EnterHardwareTraining (TechPtr)) { - TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL); - if (memTrainSequenceDDR3[i].MemTechFeatBlock->SwWLTraining (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterSwWLTrn); - if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart1 (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1); - if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1); - // If target speed is higher than start-up speed, do frequency change and second pass of WL - do { - if (MemNHwWlPart2Nb (TechPtr)) { - if (memTrainSequenceDDR3[i].MemTechFeatBlock->TrainExitHwTrn (TechPtr)) { - IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &(NBPtr->MemPtr->StdHeader)); - if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) { - if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn); - if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSRdWrPosTraining (TechPtr)) { - if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSRdWrPosTraining (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn); - if (!NBPtr->FamilySpecificHook[MemPstateStageChange] (NBPtr, NULL)) { - continue; - } - if (NBPtr->Execute1dMaxRdLatTraining) { - do { - if (memTrainSequenceDDR3[i].MemTechFeatBlock->MaxRdLatencyTraining (TechPtr)) { - MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn); - } - } while (NBPtr->ChangeNbFrequency (NBPtr)); - } else { - // If not running MRL training, set everything back for training - memTrainSequenceDDR3[i].MemTechFeatBlock->TrainExitHwTrn (TechPtr); - } - } - } - } - } - } - } - } while (NBPtr->MemPstateStage == MEMORY_PSTATE_2ND_STAGE); - } - } - } - } - MemTMarkTrainFail (TechPtr); - } - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes HW WL at multiple speeds - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @return TRUE - No errors occurred - * FALSE - errors occurred - */ - -BOOLEAN -STATIC -MemNHwWlPart2Nb ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - BOOLEAN retVal; - UINT8 i; - retVal = TRUE; - i = TechPtr->NBPtr->TrainingSequenceIndex; - while ((TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed > TechPtr->NBPtr->DCTPtr->Timings.Speed) && (TechPtr->NBPtr->MemPstateStage != MEMORY_PSTATE_1ST_STAGE)) { - TechPtr->PrevSpeed = TechPtr->NBPtr->DCTPtr->Timings.Speed; - if (TechPtr->NBPtr->RampUpFrequency (TechPtr->NBPtr)) { - TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL); - if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart2 (TechPtr)) { - retVal = FALSE; - break; - } - MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwWLTrnP2); - if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart2 (TechPtr)) { - retVal = FALSE; - break; - } - MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwRxEnTrnP2); - } else { - retVal = FALSE; - break; - } - } - return retVal; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/Makefile.inc deleted file mode 100644 index 209b77f445..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += mprc32_3.c -libagesa-y += mpuc32_3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c deleted file mode 100644 index 802a48e4fa..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c +++ /dev/null @@ -1,325 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprc32_3.c - * - * Platform specific settings for C32 DDR3 R-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_C32_MPRC32_3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsRC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemPGetPORFreqLimitRC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -/* - * ODT Settings for 1 or 2 Dimms Per Channel - * - * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm - */ -STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm2D[] = { - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}, - {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, - {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1}, - {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, - {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1} -}; -/* - * ODT Settings for 3 Dimms Per Channel - * - * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm - */ -STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm3D[] = { - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2}, - {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, - {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit1D[] = { - {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit2D[] = { - {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0}, - {SR_DIMM0 + SR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, - {QR_DIMM0 + ANY_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}, - {ANY_DIMM0 + QR_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit3D[] = { - {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {SR_DIMM0 + SR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, - {QR_DIMM1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, 0}, - {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}, - {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR800_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR667_FREQUENCY, DDR667_FREQUENCY, 0} - -}; -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor platform specific settings for R DIMM-DDR3 C32 DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsRC32_3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsRC32_3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRC32_3; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for R-DDR3 C32 DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsRC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST DRAM_TERM_ENTRY *DramTermPtr; - UINT8 MaxDimmsPerChannel; - UINT8 *DimmsPerChPtr; - UINT8 DramTermSize; - - DramTermSize = 0; - DramTermPtr = NULL; - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmsPerChannel = *DimmsPerChPtr; - } else { - MaxDimmsPerChannel = 2; - } - - if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) { - DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm2D); - DramTermPtr = C32RDdr3DramTerm2D; - } else if (MaxDimmsPerChannel == 3) { - DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm3D); - DramTermPtr = C32RDdr3DramTerm3D; - } else { - IDS_ERROR_TRAP; - } - - if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { - return FALSE; - } - // - // Special Cases for certain configs not covered by the table - // - // SR-SR-SR 1.5v @1066 (Currently only 3DPCH config at 1066) - if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3) && - (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY)) { - NBPtr->PsPtr->DramTerm = 5; //30 Ohms - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function gets the POR speed limit for R-DDR3 C32 DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * - */ -VOID -STATIC -MemPGetPORFreqLimitRC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 *DimmsPerChPtr; - UINT8 MaxDimmPerCH; - UINT8 FreqLimitSize; - UINT16 SpeedLimit; - CONST POR_SPEED_LIMIT *FreqLimitPtr; - DCT_STRUCT *DCTPtr; - - DCTPtr = NBPtr->DCTPtr; - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmPerCH = *DimmsPerChPtr; - } else { - MaxDimmPerCH = 2; - } - - if (MaxDimmPerCH == 4) { - DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - return; - } else if (MaxDimmPerCH == 3) { - FreqLimitPtr = C32RDdr3PSPorFreqLimit3D; - FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit3D); - } else if (MaxDimmPerCH == 2) { - FreqLimitPtr = C32RDdr3PSPorFreqLimit2D; - FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit2D); - } else { - FreqLimitPtr = C32RDdr3PSPorFreqLimit1D; - FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit1D); - } - - SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr); - - if (SpeedLimit != 0) { - if (DCTPtr->Timings.TargetSpeed > SpeedLimit) { - DCTPtr->Timings.TargetSpeed = SpeedLimit; - } - } else { - DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - } -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c deleted file mode 100644 index 2dbc362bfc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c +++ /dev/null @@ -1,204 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpuc32_3.c - * - * Platform specific settings for C32 DDR3 U-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "PlatformMemoryConfiguration.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_C32_MPUC32_3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsUC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemPGetPORFreqLimitUC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -STATIC CONST DRAM_TERM_ENTRY C32UDdr3DramTerm[] = { - {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} -}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor for the platform specific settings for U-DDR3 C32 DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsUC32_3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsUC32_3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUC32_3; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for U-DDR3 C32 DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsUC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (C32UDdr3DramTerm), C32UDdr3DramTerm)) { - return FALSE; - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function gets the POR speed limit for SO-DDR3 C32 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * - */ -VOID -STATIC -MemPGetPORFreqLimitUC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 MaxSpeed; - // - // For 2/2 or 2/3 DPCH where one is a DR, Max Speed is 1066 - // - if ( (NBPtr->ChannelPtr->Dimms >= 2) && ((NBPtr->ChannelPtr->DimmDrPresent & 0x07) != 0) ) { - MaxSpeed = DDR1066_FREQUENCY; - } else { - // - // Highest POR supported speed for Unbuffered dimm is 1333 - // - MaxSpeed = DDR1333_FREQUENCY; - } - if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) { - NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed; - } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) { - // Unbuffered DDR3 at 333MHz is not supported - NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - } -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/Makefile.inc deleted file mode 100644 index fa2029006c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -libagesa-y += mprhy3.c -libagesa-y += mpshy3.c -libagesa-y += mpuhy3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c deleted file mode 100644 index 24d4384e05..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c +++ /dev/null @@ -1,324 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprhy3.c - * - * Platform specific settings for HY DDR3 R-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support L1 */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_HY_MPRHY3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsRHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemPGetPORFreqLimitRHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -/* - * ODT Settings for 1 Dimm or 2 Dimms Per Channel - * - * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm - */ -STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm2D[] = { - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}, - {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, - {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1}, - {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, - {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1} -}; -/* - * ODT Settings for 3 Dimms Per Channel - * - * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm - */ -STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm3D[] = { - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2}, - {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, - {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit1D[] = { - {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit2D[] = { - {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM0 + ANY_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}, - {ANY_DIMM0 + QR_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit3D[] = { - {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM1, 1, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, - {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR800_FREQUENCY, 0}, - {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR667_FREQUENCY, 0} -}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor platform specific settings for R DIMM-DDR3 HY DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsRHy3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsRHy3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRHy3; - - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for R-DDR3 HY DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsRHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST DRAM_TERM_ENTRY *DramTermPtr; - UINT8 MaxDimmsPerChannel; - UINT8 *DimmsPerChPtr; - UINT8 DramTermSize; - - DramTermSize = 0; - DramTermPtr = NULL; - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmsPerChannel = *DimmsPerChPtr; - } else { - MaxDimmsPerChannel = 2; - } - - if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) { - DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm2D); - DramTermPtr = HyRDdr3DramTerm2D; - } else if (MaxDimmsPerChannel == 3) { - DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm3D); - DramTermPtr = HyRDdr3DramTerm3D; - } else { - IDS_ERROR_TRAP; - } - - if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { - return FALSE; - } - // - // Special Cases for certain configs not covered by the table - // - // 3DPCH Fully populated. - if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) { - NBPtr->PsPtr->DramTerm = 5; //30 Ohms - NBPtr->PsPtr->QR_DramTerm = 1; // 60 Ohms - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function gets the POR speed limit for R-DDR3 HY - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * - */ -VOID -STATIC -MemPGetPORFreqLimitRHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 *DimmsPerChPtr; - UINT8 MaxDimmPerCH; - UINT8 FreqLimitSize; - UINT16 SpeedLimit; - CONST POR_SPEED_LIMIT *FreqLimitPtr; - DCT_STRUCT *DCTPtr; - - DCTPtr = NBPtr->DCTPtr; - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmPerCH = *DimmsPerChPtr; - } else { - MaxDimmPerCH = 2; - } - - if (MaxDimmPerCH == 4) { - DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - return; - } else if (MaxDimmPerCH == 3) { - FreqLimitPtr = HyRDdr3PSPorFreqLimit3D; - FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit3D); - } else if (MaxDimmPerCH == 2) { - FreqLimitPtr = HyRDdr3PSPorFreqLimit2D; - FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit2D); - } else { - FreqLimitPtr = HyRDdr3PSPorFreqLimit1D; - FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit1D); - } - - SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr); - - if (SpeedLimit != 0) { - if (DCTPtr->Timings.TargetSpeed > SpeedLimit) { - DCTPtr->Timings.TargetSpeed = SpeedLimit; - } - } else { - DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - } -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c deleted file mode 100644 index 10595418eb..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c +++ /dev/null @@ -1,220 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpshy3.c - * - * Platform specific settings for HY DDR3 SO-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support L1 */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_HY_MPSHY3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsSHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemPGetPORFreqLimitSHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm1D[] = { - {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0}, - {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0} -}; - -STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = { - {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} -}; -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsSHy3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsSHy3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSHy3; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for S-DDR3 HY DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsSHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST DRAM_TERM_ENTRY *DramTermPtr; - UINT8 MaxDimmsPerChannel; - UINT8 *DimmsPerChPtr; - UINT8 DramTermSize; - - DramTermSize = 0; - DramTermPtr = NULL; - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmsPerChannel = *DimmsPerChPtr; - } else { - MaxDimmsPerChannel = 2; - } - - if (MaxDimmsPerChannel == 1) { - DramTermSize = GET_SIZE_OF (HySDdr3DramTerm1D); - DramTermPtr = HySDdr3DramTerm1D; - } else if (MaxDimmsPerChannel == 2) { - DramTermSize = GET_SIZE_OF (HySDdr3DramTerm2D); - DramTermPtr = HySDdr3DramTerm2D; - } else { - IDS_ERROR_TRAP; - } - - if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { - return FALSE; - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function gets the POR speed limit for SO-DDR3 HY - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * - */ -VOID -STATIC -MemPGetPORFreqLimitSHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 MaxSpeed; - // - // Highest POR supported speed for SODimm is 1333 - // - MaxSpeed = DDR1333_FREQUENCY; - if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) { - NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed; - } -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c deleted file mode 100644 index 1aa93587d3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c +++ /dev/null @@ -1,198 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpuhy3.c - * - * Platform specific settings for HY DDR3 U-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support L1 */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "PlatformMemoryConfiguration.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_HY_MPUHY3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsUhy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemPGetPORFreqLimitUHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -STATIC CONST DRAM_TERM_ENTRY HyUDdr3DramTerm[] = { - {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} -}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor for the platform specific settings for U-DDR3 HY DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsUHy3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsUhy3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUHy3; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for U-DDR3 HY DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsUhy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (HyUDdr3DramTerm), HyUDdr3DramTerm)) { - return FALSE; - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function gets the POR speed limit for U-DDR3 HY - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * - */ -VOID -STATIC -MemPGetPORFreqLimitUHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 MaxSpeed; - // - // Highest POR supported speed for Unbuffered dimm is 1333 - // - MaxSpeed = DDR1333_FREQUENCY; - if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) { - NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed; - } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) { - // Unbuffered DDR3 at 333MHz is not supported - NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - } -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/Makefile.inc deleted file mode 100644 index 5eb7129f90..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -libagesa-y += mp.c -libagesa-y += mplribt.c -libagesa-y += mplrnlr.c -libagesa-y += mplrnpr.c -libagesa-y += mpmaxfreq.c -libagesa-y += mpmr0.c -libagesa-y += mpodtpat.c -libagesa-y += mprc10opspd.c -libagesa-y += mprc2ibt.c -libagesa-y += mprtt.c -libagesa-y += mps2d.c -libagesa-y += mpsao.c -libagesa-y += mpseeds.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/Makefile.inc deleted file mode 100644 index 45e839c04f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -libagesa-y += mpLorC3.c -libagesa-y += mpRorC3.c -libagesa-y += mpUorC3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpLorC3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpLorC3.c deleted file mode 100644 index 711acef9c6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpLorC3.c +++ /dev/null @@ -1,320 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpLorC3.c - * - * Platform specific settings for OR C32 DDR3 LRDIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/C32) - * @e \$Revision: 56315 $ @e \$Date: 2011-07-11 15:59:14 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - - -#define FILECODE PROC_MEM_PS_OR_C32_MPLORC3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrC32LRDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR800, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR1066, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x003C3C3C, 0x20112222}, - {1, DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x003A3A3A, 0x30112222}, - {1, DDR1600, V1_5, DIMM_LR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 0, 0x00393939, 0x30332222}, - {2, DDR667, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x00000000, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00393C39, 0x20112222}, - {2, DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00373A37, 0x30112222}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 0, 0x00363936, 0x30112222}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 0, 0x00383A38, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x00000000, 0x20222222}, - {3, DDR667, VOLT_ALL, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00380038, 0x30112222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00390039, 0x10332222}, - {3, DDR800, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x003A003A, 0x30222222}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00373C37, 0x20332222}, - {3, DDR1066, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x00383C38, 0x30222222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00353A35, 0x30332222}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 0x00333933, 0x30332222}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 0, 0x00363A36, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntLRC32 = { - {PSCFG_SAO, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32LRDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrC32LRDdr3SAO -}; -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrC32LRDdr3S__[] = { - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 1}, - {1, DDR1600, V1_5, DIMM_LR, NP, NP, 1}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 1}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_LR, DIMM_LR, NP, 1}, - {2, DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 1}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667 + DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 1}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_LR, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1}, - {3, DDR800, V1_25, NP + DIMM_LR, NP, DIMM_LR, 1}, - {3, DDR1066, VOLT_ALL, NP + DIMM_LR, NP, DIMM_LR, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 1}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 1}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 1}, - }; -CONST PSC_TBL_ENTRY S__TblEntLRC32 = { - {PSCFG_S__, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32LRDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrC32LRDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1LRDdr3OdtPat[] = { - {DIMM_LR, 0x00000000, 0x00000000, 0x00000101, 0x00000101} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntLRC32 = { - {PSCFG_ODT_PAT_1D, LRDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or1LRDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1LRDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2LRDdr3OdtPat[] = { - {NP, DIMM_LR, 0x00000000, 0x00000000, 0x02020000, 0x02020000}, - {DIMM_LR, DIMM_LR, 0x01010202, 0x01010202, 0x03030303, 0x03030303} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntLRC32 = { - {PSCFG_ODT_PAT___, LRDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or2LRDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2LRDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3LRDdr3OdtPat[] = { - {NP, NP, DIMM_LR, 0x00000000, 0x00000000, 0x00000404, 0x00000000}, - {DIMM_LR, NP, DIMM_LR, 0x00000101, 0x00000404, 0x00000505, 0x00000505}, - {DIMM_LR, DIMM_LR, DIMM_LR, 0x00000303, 0x05050606, 0x00000707, 0x07070707} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntLRC32 = { - {PSCFG_ODT_PAT_3D, LRDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3LRDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3LRDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, RttNom, RttWr -// -STATIC CONST PSCFG_LR_RTT_ENTRY DramTermOrC32LRDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_LR, NP, NP, 2, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 1, 0}, - {1, DDR1600, V1_5, DIMM_LR, NP, NP, 3, 0}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 3, 0}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_LR, NP, 2, 0}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 3, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 1, 0}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 3, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 5, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_LR, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 3, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 1}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 5, 2}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntLRC32 = { - {PSCFG_LR_RTT, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (DramTermOrC32LRDIMM) / sizeof (PSCFG_LR_RTT_ENTRY), - (VOID *)&DramTermOrC32LRDIMM -}; -// Max Freq. -// Format : -// DimmPerCh, Dimms, LR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_LR_MAXFREQ_ENTRY ROMDATA MaxFreqOrC32LRDIMM[] = { - {{1, 1, 1, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 1, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 1, 1, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 3, 3, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}} -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntLRC32 = { - {PSCFG_LR_MAXFREQ, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrC32LRDIMM) / sizeof (PSCFG_LR_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrC32LRDIMM -}; - -// IBT -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, F0RC8, F1RC0, F1RC1, F1RC2 -// -STATIC CONST PSCFG_L_IBT_ENTRY OrLRDdr3IBT[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_LR, NP, NP, 1, 1, 1, 1}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {1, DDR1600, V1_5, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 0, 0, 0, 0}, - {2, DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 0, 0, 0, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR800 + DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 0, 0, 0}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR800, V1_25, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1066, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 0, 0, 0}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, -}; -CONST PSC_TBL_ENTRY IBTTblEntLRC32 = { - {PSCFG_LR_IBT, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrLRDdr3IBT) / sizeof (PSCFG_L_IBT_ENTRY), - (VOID *)&OrLRDdr3IBT -}; - -// -// MemClkDis -// -STATIC CONST UINT8 ROMDATA Or3LRDdr3CLKDis[] = {0x03, 0x0C, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntLRC32 = { - {PSCFG_CLKDIS, LRDIMM_TYPE, _1DIMM + _2DIMM + _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3LRDdr3CLKDis) / sizeof (UINT8), - (VOID *)&Or3LRDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrC32LRDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0xF7} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntLRC32 = { - {PSCFG_WL_PASS1_SEED, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrC32LRDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrC32LRDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrC32LRDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_A, 0x132}, - {_1DIMM + _2DIMM + _3DIMM, CH_B, 0x122} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntLRC32 = { - {PSCFG_HWRXEN_PASS1_SEED, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrC32LRDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrC32LRDIMM -}; \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpRorC3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpRorC3.c deleted file mode 100644 index de25ec8de9..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpRorC3.c +++ /dev/null @@ -1,653 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpRorC3.c - * - * Platform specific settings for OR C32 DDR3 R-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/C32) - * @e \$Revision: 55134 $ @e \$Date: 2011-06-16 15:27:02 -0600 (Thu, 16 Jun 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" - -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_OR_C32_MPRORC3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrC32RDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR667, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x00000000, 0x00222222}, - {1, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR800, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x00000000, 0x10222222}, - {1, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x003C3C3C, 0x20112222}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x003C3C3C, 0x30222222}, - {1, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x003A3A3A, 0x30112222}, - {1, DDR1333, V1_5, DIMM_QR, NP, NP, 0, 0x003A3A3A, 0x30222222}, - {1, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, 0, 0x003A3A3A, 0x30222222}, - {1, DDR1600, V1_35, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00393939, 0x30332222}, - {2, DDR667, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x00222222}, - {2, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x00000000, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00393C39, 0x20112222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00393C39, 0x20222222}, - {2, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00373A37, 0x30112222}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, 0, 0x00373A37, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00363936, 0x30112222}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, 0, 0x00373A37, 0x30222222}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 0, 0x00383A38, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x20222222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x10222222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00380038, 0x30112222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x10332222}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00390039, 0x20222222}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x003A003A, 0x30222222}, - {3, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x003A003A, 0x20222222}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00373C37, 0x20332222}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, 0, 0x00373C37, 0x30222222}, - {3, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00383C38, 0x30222222}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00353A35, 0x30332222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, 0, 0x00363A36, 0x30222222}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00333933, 0x30332222}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00383C38, 0x30222222}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, 0, 0x00373C37, 0x30222222}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, 0, 0x00363A36, 0x30222222}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00303A30, 0x30112222}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00363A36, 0x30222222}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 0, 0x00363A36, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntRC32 = { - {PSCFG_SAO, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32RDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrC32RDdr3SAO -}; -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrC32RDdr3S__[] = { - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, NP, NP, 1}, - {1, DDR1333, V1_5, DIMM_SR + DIMM_DR + DIMM_QR, NP, NP, 1}, - {1, DDR1333, V1_35 + V1_25, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, 1}, - {1, DDR1600, V1_35, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 1}, - {2, DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR + DIMM_QR, NP, 1}, - {2, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, V1_5, NP, DIMM_SR + DIMM_DR + DIMM_QR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, 1}, - {2, DDR1333, V1_35 + V1_25, NP, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, 1}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1066, VOLT_ALL, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 1}, - }; -CONST PSC_TBL_ENTRY S__TblEntRC32 = { - {PSCFG_S__, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32RDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrC32RDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1RDdr3OdtPat[] = { - {DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001}, - {DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401}, - {DIMM_QR, 0x00000000, 0x00000000, 0x00000505, 0x00000505} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntRC32 = { - {PSCFG_ODT_PAT_1D, RDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or1RDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1RDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2RDdr3OdtPat[] = { - {NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000}, - {NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000}, - {NP, DIMM_QR, 0x00000000, 0x00000000, 0x020A0000, 0x080A0000}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603}, - {DIMM_SR + DIMM_DR, DIMM_QR, 0x01010000, 0x01010A0A, 0x01090000, 0x01030E0B}, - {DIMM_QR, DIMM_SR + DIMM_DR, 0x00000202, 0x05050202, 0x00000206, 0x0D070203}, - {DIMM_QR, DIMM_QR, 0x05050A0A, 0x05050A0A, 0x050D0A0E, 0x05070A0B} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntRC32 = { - {PSCFG_ODT_PAT___, RDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or2RDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2RDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3RDdr3OdtPat[] = { - {NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000004, 0x00000000}, - {DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x00000405}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000303, 0x05050606, 0x00000307, 0x0D070607}, - {NP, DIMM_QR, NP, 0x00000000, 0x00000000, 0x020A0000, 0x080A0000}, - {NP, DIMM_QR, DIMM_SR + DIMM_DR, 0x04040A0A, 0x04040000, 0x040C0A0E, 0x04060000}, - {DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, 0x05050B0B, 0x05050E0E, 0x050D0B0F, 0x05070E0F} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntRC32 = { - {PSCFG_ODT_PAT_3D, RDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3RDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3RDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr -// -STATIC CONST PSCFG_RTT_ENTRY DramTermOrC32RDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 2, 2}, - {1, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R1 + R3, 0, 2}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 1, 2}, - {1, DDR1333, V1_5, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 3, 2}, - {1, DDR1333, V1_5, DIMM_QR, NP, NP, DIMM_QR, R1 + R3, 0, 2}, - {1, DDR1600, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 3, 2}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, DIMM_QR, R1 + R3, 0, 2}, - {1, DDR1600, V1_35, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_35, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 2, 2}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 3, 2}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR1066, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 3, 2}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 2}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 2, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR + DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, VOLT_ALL, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntRC32 = { - {PSCFG_RTT, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (DramTermOrC32RDIMM) / sizeof (PSCFG_RTT_ENTRY), - (VOID *)&DramTermOrC32RDIMM -}; - -// POR Max Freq. -// Format : -// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrC32RDIMM[] = { - {{1, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 0, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 0, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 1, 1, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 1, 0, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{2, 2, 0, 2, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 0, 1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{2, 2, 0, 0, 2, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 0, 1, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 1, 1, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 1, 0, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 2, 0, 2, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 0, 1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 3, 3, 0, 0, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 3, 2, 1, 0, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 2, 0, 1, DDR667_FREQUENCY, DDR667_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 1, 2, 0, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 1, 1, 1, DDR667_FREQUENCY, DDR667_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 0, 3, 0, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 0, 2, 1, DDR667_FREQUENCY, DDR667_FREQUENCY, DDR667_FREQUENCY}} -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntRC32 = { - {PSCFG_MAXFREQ, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrC32RDIMM) / sizeof (PSCFG_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrC32RDIMM -}; - -// RC2[IBT] -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, NumOfReg, IBT -// -STATIC CONST PSCFG_MR2IBT_ENTRY OrRDdr3RC2IBT[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, 1, 1}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, 1, 1}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 0xF, 1}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 2, 1}, - {1, DDR1333, V1_5, DIMM_QR, NP, NP, DIMM_QR, 1, 0}, - {1, DDR1333, V1_5, DIMM_QR, NP, NP, DIMM_QR, 2, 1}, - {1, DDR1600, V1_5, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1600, V1_5, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, DIMM_QR, 1, 0}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, DIMM_QR, 2, 1}, - {1, DDR1600, V1_35, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1600, V1_35, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 0xF, 1}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {2, DDR1066, VOLT_ALL, DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR1066, VOLT_ALL, DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, 1, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, 1, 0}, - {2, DDR1066, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 0xF, 1}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR667, VOLT_ALL, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, NP + DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, 1, 0}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, 1, 0}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {3, DDR1066, V1_5, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_35 + V1_25, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, 1, 0}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, 1, 0}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, -}; -CONST PSC_TBL_ENTRY RC2IBTTblEntRC32 = { - {PSCFG_RC2IBT, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrRDdr3RC2IBT) / sizeof (PSCFG_MR2IBT_ENTRY), - (VOID *)&OrRDdr3RC2IBT -}; - -// RC10[OperatingSpeed] -// Format : -// DDRrate, Operating Speed -// -STATIC CONST PSCFG_OPSPD_ENTRY OrRDdr3OpSPD[] = { - {DDR667 + DDR800, 0}, - {DDR1066, 1}, - {DDR1333, 2}, - {DDR1600, 3} -}; -CONST PSC_TBL_ENTRY RC10OpSpdTblEntRC32 = { - {PSCFG_RC10OPSPD, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrRDdr3OpSPD) / sizeof (PSCFG_OPSPD_ENTRY), - (VOID *)&OrRDdr3OpSPD -}; - -// -// MemClkDis -// -STATIC CONST UINT8 ROMDATA Or3RDdr3CLKDis[] = {0x03, 0x0C, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntRC32 = { - {PSCFG_CLKDIS, RDIMM_TYPE, _1DIMM + _2DIMM + _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3RDdr3CLKDis) / sizeof (UINT8), - (VOID *)&Or3RDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrC32RDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0x3E} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntRC32 = { - {PSCFG_WL_PASS1_SEED, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrC32RDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrC32RDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrC32RDIMM[] = { - {_1DIMM + _2DIMM, CH_A, 0x3F}, - {_1DIMM + _2DIMM, CH_B, 0x3E}, - {_3DIMM, CH_A, 0x47}, - {_3DIMM, CH_B, 0x38} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntRC32 = { - {PSCFG_HWRXEN_PASS1_SEED, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrC32RDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrC32RDIMM -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpUorC3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpUorC3.c deleted file mode 100644 index 89d6da71d5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpUorC3.c +++ /dev/null @@ -1,343 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpUorC3.c - * - * Platform specific settings for OR C32 DDR3 U-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/C32) - * @e \$Revision: 55134 $ @e \$Date: 2011-06-16 15:27:02 -0600 (Thu, 16 Jun 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "PlatformMemoryConfiguration.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_OR_C32_MPUORC3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrC32UDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR667, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x003B0000, 0x00112222}, - {1, DDR800, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR800, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x003B0000, 0x10112222}, - {1, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00383837, 0x20112222}, - {1, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00363635, 0x30112222}, - {1, DDR1600, V1_5, DIMM_SR, NP, NP, 0, 0x00353533, 0x30112222}, - {1, DDR1600, V1_5, DIMM_DR, NP, NP, 1, 0x00003533, 0x30112222}, - {1, DDR1600, V1_35, DIMM_SR, NP, NP, 0, 0x00353533, 0x30112222}, - {1, DDR1600, V1_35, DIMM_DR, NP, NP, 1, 0x00003533, 0x30112222}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x00333330, 0x30332222}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003330, 0x30332222}, - {2, DDR667, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x003B0000, 0x00112222}, - {2, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x003B0000, 0x10112222}, - {2, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00383837, 0x20112222}, - {2, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x003A3A3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00363635, 0x30112222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, 1, 0x00003939, 0x30222222}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, 0, 0x00353533, 0x30112222}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, 1, 0x00003533, 0x30112222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, 1, 0x00003938, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00003938, 0x30222222}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 1, 0x00003939, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_SR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_DR, 0, 0x003B0000, 0x00332222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x10222222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_SR, 0, 0x00000000, 0x10332222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_DR, 0, 0x003B0000, 0x10332222}, - {3, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x20222222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00383837, 0x20332222}, - {3, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x003A3A3A, 0x30222222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00363635, 0x30332222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, 1, 0x00003939, 0x30222222}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, 0, 0x00353533, 0x30332222}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, 1, 0x00003533, 0x30332222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, 1, 0x00003938, 0x30222222}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 0x00003938, 0x30222222}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 1, 0x00003939, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntUC32 = { - {PSCFG_SAO, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32UDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrC32UDdr3SAO -}; -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrC32UDdr3S__[] = { - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066 + DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1600, V1_35, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, 1}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 1}, }; -CONST PSC_TBL_ENTRY S__TblEntUC32 = { - {PSCFG_S__, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32UDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrC32UDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1UDdr3OdtPat[] = { - {DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001}, - {DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntUC32 = { - {PSCFG_ODT_PAT_1D, UDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or1UDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1UDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2UDdr3OdtPat[] = { - {NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000}, - {NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntUC32 = { - {PSCFG_ODT_PAT___, UDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or2UDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2UDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3UDdr3OdtPat[] = { - {NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000004, 0x00000000}, - {DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x00000405} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntUC32 = { - {PSCFG_ODT_PAT_3D, UDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3UDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3UDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr -// -STATIC CONST PSCFG_RTT_ENTRY DramTermOrC32UDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0}, - {1, DDR1600, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1600, V1_35, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_35, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntUC32 = { - {PSCFG_RTT, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (DramTermOrC32UDIMM) / sizeof (PSCFG_RTT_ENTRY), - (VOID *)&DramTermOrC32UDIMM -}; - -// Max Freq. -// Format : -// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrC32UDIMM[] = { - {{1, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 1, 1, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 0, 2, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 1, 1, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 0, 2, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}} -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntUC32 = { - {PSCFG_MAXFREQ, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrC32UDIMM) / sizeof (PSCFG_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrC32UDIMM -}; - -// -// MemClkDis [1DPC & 2DPC] -// -STATIC CONST UINT8 ROMDATA OrUDdr3CLKDis[] = {0x01, 0x04, 0x02, 0x08, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntUC32 = { - {PSCFG_CLKDIS, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrUDdr3CLKDis) / sizeof (UINT8), - (VOID *)&OrUDdr3CLKDis -}; - -// -// MemClkDis [3DPC] -// -STATIC CONST UINT8 ROMDATA Or3UDdr3CLKDis[] = {0x01, 0x02, 0x10, 0x20, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMap3DEntUC32 = { - {PSCFG_CLKDIS, UDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3UDdr3CLKDis) / sizeof (UINT8), - (VOID *)&Or3UDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrC32UDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0x12} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntUC32 = { - {PSCFG_WL_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrC32UDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrC32UDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrC32UDIMM[] = { - {_1DIMM + _2DIMM, CH_A, 0x39}, - {_1DIMM + _2DIMM, CH_B, 0x32}, - {_3DIMM, CH_A, 0x45}, - {_3DIMM, CH_B, 0x37} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntUC32 = { - {PSCFG_HWRXEN_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrC32UDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrC32UDIMM -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/Makefile.inc deleted file mode 100644 index 173efca5b6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -libagesa-y += mpLorG3.c -libagesa-y += mpRorG3.c -libagesa-y += mpUorG3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpLorG3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpLorG3.c deleted file mode 100644 index 3b26f68407..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpLorG3.c +++ /dev/null @@ -1,336 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpLorG3.c - * - * Platform specific settings for OR G34 DDR3 LRDIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/G34) - * @e \$Revision: 58717 $ @e \$Date: 2011-09-05 23:20:11 -0600 (Mon, 05 Sep 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_PS_OR_G34_MPLORG3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrG34LRDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR800, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR1066, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x003C3C3C, 0x20112222}, - {1, DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x003A3A3A, 0x30112222}, - {1, DDR1600, V1_5, DIMM_LR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 0, 0x00393939, 0x30332222}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 0, 0x00393939, 0x30112222}, - {2, DDR667, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x00000000, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00393C39, 0x20112222}, - {2, DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00373A37, 0x30112222}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 0, 0x00363936, 0x30112222}, - {2, DDR1600, V1_5, DIMM_LR, DIMM_LR, NP, 0, 0x00353935, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x00000000, 0x20222222}, - {3, DDR667, VOLT_ALL, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00380038, 0x30112222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00390039, 0x10332222}, - {3, DDR800, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x003A003A, 0x30222222}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00373C37, 0x20332222}, - {3, DDR1066, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x00383C38, 0x30222222}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00353A35, 0x30332222}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 0, 0x00363A36, 0x30222222}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 0x00333933, 0x30332222}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00303A30, 0x30112222}, - {3, DDR1600, V1_5, DIMM_LR, NP, DIMM_LR, 0, 0x00343934, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntLRG34 = { - {PSCFG_SAO, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34LRDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrG34LRDdr3SAO -}; -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrG34LRDdr3S__[] = { - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_LR, NP, NP, 0}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_LR, DIMM_LR, NP, 0}, - {2, DDR1333, V1_5 + V1_35, NP + DIMM_LR, DIMM_LR, NP, 0}, - {2, DDR1333, V1_25, NP, DIMM_LR, NP, 0}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 0}, - {2, DDR1600, V1_5, DIMM_LR, DIMM_LR, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667, VOLT_ALL, NP, NP, DIMM_LR, 1}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_LR, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1}, - {3, DDR800, V1_25, NP + DIMM_LR, NP, DIMM_LR, 1}, - {3, DDR1066 + DDR1600, V1_5, NP, NP, DIMM_LR, 1}, - {3, DDR1066, V1_5, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1}, - {3, DDR1066, V1_35 + V1_25, NP + DIMM_LR, NP, DIMM_LR, 1}, - {3, DDR1333, V1_5 + V1_35, NP + DIMM_LR, NP, DIMM_LR, 1}, - {3, DDR1333, V1_25, NP, NP, DIMM_LR, 1}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 1}, - {3, DDR1066, V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 1}, - {3, DDR1333, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 1}, - {3, DDR1600, V1_5, DIMM_LR, NP, DIMM_LR, 1}, - }; -CONST PSC_TBL_ENTRY S__TblEntLRG34 = { - {PSCFG_S__, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34LRDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrG34LRDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1LRDdr3OdtPat[] = { - {DIMM_LR, 0x00000000, 0x00000000, 0x00000101, 0x00000101} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntLRG34 = { - {PSCFG_ODT_PAT_1D, LRDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or1LRDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1LRDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2LRDdr3OdtPat[] = { - {NP, DIMM_LR, 0x00000000, 0x00000000, 0x02020000, 0x02020000}, - {DIMM_LR, DIMM_LR, 0x01010202, 0x01010202, 0x03030303, 0x03030303} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntLRG34 = { - {PSCFG_ODT_PAT___, LRDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or2LRDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2LRDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3LRDdr3OdtPat[] = { - {NP, NP, DIMM_LR, 0x00000000, 0x00000000, 0x00000404, 0x00000000}, - {DIMM_LR, NP, DIMM_LR, 0x00000101, 0x00000404, 0x00000505, 0x00000505}, - {DIMM_LR, DIMM_LR, DIMM_LR, 0x00000303, 0x05050606, 0x00000707, 0x07070707} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntLRG34 = { - {PSCFG_ODT_PAT_3D, LRDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or3LRDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3LRDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, RttNom, RttWr -// -STATIC CONST PSCFG_LR_RTT_ENTRY DramTermOrG34LRDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_LR, NP, NP, 2, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 1, 0}, - {1, DDR1600 + DDR1866, V1_5, DIMM_LR, NP, NP, 3, 0}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_LR, NP, 2, 0}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 3, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 1, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 5, 2}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 3, 0}, - {2, DDR1600, V1_5, DIMM_LR, DIMM_LR, NP, 5, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_LR, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 3, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 1}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 5, 2}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 1}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1066, V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1333, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1600, V1_5, DIMM_LR, NP, DIMM_LR, 5, 1}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntLRG34 = { - {PSCFG_LR_RTT, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (DramTermOrG34LRDIMM) / sizeof (PSCFG_LR_RTT_ENTRY), - (VOID *)&DramTermOrG34LRDIMM -}; -// Max Freq. -// Format : -// DimmPerCh, Dimms, LR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_LR_MAXFREQ_ENTRY ROMDATA MaxFreqOrG34LRDIMM[] = { - {{1, 1, 1, DDR1866_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 1, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 1, 1, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 3, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}} -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntLRG34 = { - {PSCFG_LR_MAXFREQ, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrG34LRDIMM) / sizeof (PSCFG_LR_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrG34LRDIMM -}; - -// IBT -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, F0RC8, F1RC0, F1RC1, F1RC2 -// -STATIC CONST PSCFG_L_IBT_ENTRY OrLRDdr3IBT[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_LR, NP, NP, 1, 1, 1, 1}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {1, DDR1600 + DDR1866, V1_5, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 0, 0, 0, 0}, - {2, DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 0, 0, 0, 0}, - {2, DDR1600, V1_5, DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR800 + DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 0, 0, 0}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR800, V1_25, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1066, V1_5, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1066, V1_35 + V1_25, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 0, 0, 0}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1066, V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1333, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1600, V1_5, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, -}; -CONST PSC_TBL_ENTRY IBTTblEntLRG34 = { - {PSCFG_LR_IBT, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrLRDdr3IBT) / sizeof (PSCFG_L_IBT_ENTRY), - (VOID *)&OrLRDdr3IBT -}; - -// -// MemClkDis -// -STATIC CONST UINT8 ROMDATA Or3LRDdr3CLKDis[] = {0x03, 0x0C, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntLRG34 = { - {PSCFG_CLKDIS, LRDIMM_TYPE, _1DIMM + _2DIMM + _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or3LRDdr3CLKDis) / sizeof (UINT8), - (VOID *)&Or3LRDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrG34LRDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0xF7} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntLRG34 = { - {PSCFG_WL_PASS1_SEED, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrG34LRDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrG34LRDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrG34LRDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_A, 0x132}, - {_1DIMM + _2DIMM + _3DIMM, CH_B, 0x122}, - {_1DIMM + _2DIMM + _3DIMM, CH_C, 0x112}, - {_1DIMM + _2DIMM + _3DIMM, CH_D, 0x102} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntLRG34 = { - {PSCFG_HWRXEN_PASS1_SEED, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrG34LRDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrG34LRDIMM -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpRorG3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpRorG3.c deleted file mode 100644 index fb34f6f17f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpRorG3.c +++ /dev/null @@ -1,743 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpRorG3.c - * - * Platform specific settings for OR G34 DDR3 R-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/G34) - * @e \$Revision: 58716 $ @e \$Date: 2011-09-05 23:18:21 -0600 (Mon, 05 Sep 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - - -#define FILECODE PROC_MEM_PS_OR_G34_MPRORG3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrG34RDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR667, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x00000000, 0x00222222}, - {1, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR800, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x00000000, 0x10222222}, - {1, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x003C3C3C, 0x20112222}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x003C3C3C, 0x30222222}, - {1, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x003A3A3A, 0x30112222}, - {1, DDR1333, V1_5 + V1_35, DIMM_QR, NP, NP, 0, 0x003A3A3A, 0x30222222}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00393939, 0x30332222}, - {2, DDR667, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x00222222}, - {2, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x00000000, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00393C39, 0x20112222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00393C39, 0x20222222}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1066, V1_35 + V1_25, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00373A37, 0x30112222}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, 0, 0x00373A37, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00363936, 0x30112222}, - {2, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00353935, 0x30222222}, - {2, DDR1066, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1066, V1_25, DIMM_QR, DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, 0, 0x00373A37, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x20222222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x10222222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00380038, 0x30112222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x10332222}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00390039, 0x20222222}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x003A003A, 0x30222222}, - {3, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x003A003A, 0x20222222}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00373C37, 0x20332222}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, 0, 0x00373C37, 0x30222222}, - {3, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00383C38, 0x30222222}, - {3, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00353A35, 0x30332222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00363A36, 0x30222222}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 0, 0x00363A36, 0x30222222}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00333933, 0x30332222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00383C38, 0x30222222}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, 0, 0x00353A35, 0x30222222}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, 0, 0x00303A30, 0x30112222}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00303A30, 0x30112222}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00303A30, 0x30112222}, - {3, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00343934, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntRG34 = { - {PSCFG_SAO, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34RDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrG34RDdr3SAO -}; - -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrG34RDdr3S__[] = { -// DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, NP, NP, 0}, - {1, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR + DIMM_QR, NP, NP, 0}, - {1, DDR1333, V1_25, DIMM_SR + DIMM_DR, NP, NP, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, 0}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1066, V1_5, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1066, V1_35 + V1_25, NP, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1066, V1_35 + V1_25, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_5, NP, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_35, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_25, NP, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 0}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, 0}, - {2, DDR1066, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, NP, 0}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1066, V1_25, DIMM_QR, DIMM_QR, NP, 0}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, 0}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, 0}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_5, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_35, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1066 + DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, 1}, - {3, DDR1066, V1_5, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_35 + V1_25, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1333, V1_5 + V1_35, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1333, V1_25, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 1}, - {3, DDR800, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_DR, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - }; -CONST PSC_TBL_ENTRY S__TblEntRG34 = { - {PSCFG_S__, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34RDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrG34RDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1RDdr3OdtPat[] = { - {DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001}, - {DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401}, - {DIMM_QR, 0x00000000, 0x00000000, 0x00000505, 0x00000505} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntRG34 = { - {PSCFG_ODT_PAT_1D, RDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or1RDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1RDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2RDdr3OdtPat[] = { - {NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000}, - {NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000}, - {NP, DIMM_QR, 0x00000000, 0x00000000, 0x020A0000, 0x080A0000}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603}, - {DIMM_SR + DIMM_DR, DIMM_QR, 0x01010000, 0x01010A0A, 0x01090000, 0x01030E0B}, - {DIMM_QR, DIMM_SR + DIMM_DR, 0x00000202, 0x05050202, 0x00000206, 0x0D070203}, - {DIMM_QR, DIMM_QR, 0x05050A0A, 0x05050A0A, 0x050D0A0E, 0x05070A0B} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntRG34 = { - {PSCFG_ODT_PAT___, RDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or2RDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2RDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3RDdr3OdtPat[] = { - {NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000004, 0x00000000}, - {DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x0000405}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000303, 0x05050606, 0x00000307, 0x0D070607}, - {NP, DIMM_QR, NP, 0x00000000, 0x00000000, 0x020A0000, 0x080A0000}, - {NP, DIMM_QR, DIMM_SR + DIMM_DR, 0x04040A0A, 0x04040000, 0x040C0A0E, 0x04060000}, - {DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, 0x05050B0B, 0x05050E0E, 0x050D0B0F, 0x05070E0F} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntRG34 = { - {PSCFG_ODT_PAT_3D, RDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or3RDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3RDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr -// -STATIC CONST PSCFG_RTT_ENTRY DramTermOrG34RDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 2, 2}, - {1, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R1 + R3, 0, 2}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 1, 2}, - {1, DDR1333, V1_5 + V1_35, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 3, 2}, - {1, DDR1333, V1_5 + V1_35, DIMM_QR, NP, NP, DIMM_QR, R1 + R3, 0, 2}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 2, 2}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR1066, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 3, 2}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 4, 1}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 4, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1}, - {2, DDR1066, V1_35, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_35, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1066, V1_25, DIMM_QR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_25, DIMM_QR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1333, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1333, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 3, 2}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 2}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 2, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR + DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, NP + DIMM_SR + DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_SR + DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_SR + DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_DR + DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_DR + DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1066, V1_5, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5 + V1_35, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35 + V1_25, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_35 + V1_25, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 3, 2}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 4, 1}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntRG34 = { - {PSCFG_RTT, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (DramTermOrG34RDIMM) / sizeof (PSCFG_RTT_ENTRY), - (VOID *)&DramTermOrG34RDIMM -}; - -// Max Freq. -// Format : -// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrG34RDIMM[] = { - {{1, 1, 1, 0, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 1, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 0, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 1, 0, 1, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{2, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 0, 1, 1, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{2, 2, 0, 0, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 0, 1, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 1, 0, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 0, 1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 3, 3, 0, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 3, 2, 1, 0, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 2, 0, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 1, 2, 0, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 1, 1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 0, 3, 0, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 0, 2, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntRG34 = { - {PSCFG_MAXFREQ, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrG34RDIMM) / sizeof (PSCFG_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrG34RDIMM -}; - -// RC2[IBT] -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, NumOfReg, IBT -// -STATIC CONST PSCFG_MR2IBT_ENTRY OrRDdr3RC2IBT[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, 1, 1}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, 1, 1}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 0xF, 1}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 2, 1}, - {1, DDR1333, V1_5 + V1_35, DIMM_QR, NP, NP, DIMM_QR, 1, 0}, - {1, DDR1333, V1_5 + V1_35, DIMM_QR, NP, NP, DIMM_QR, 2, 1}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 0xF, 1}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {2, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR1066, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, VOLT_ALL, DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR1066, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, 1, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, 1, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR1066, V1_35, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, V1_35, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_35 + V1_25, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1066, V1_25, DIMM_QR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1333, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1333, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 0xF, 1}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR667, VOLT_ALL, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, NP + DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR800, V1_5 + V1_35, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_25, NP + DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, V1_25, NP, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR800, V1_25, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR800, V1_25, NP, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_25, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, 1, 0}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, 1, 0}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {3, DDR1066, V1_5 + V1_35, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1066, V1_5, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35 + V1_25, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35 + V1_25, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35 + V1_25, DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_25, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1333, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, 1, 0}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, 1, 0}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR1066, V1_5, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_QR, 2, 8}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR1066, V1_35, NP, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_35, NP, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, -}; -CONST PSC_TBL_ENTRY RC2IBTTblEntRG34 = { - {PSCFG_RC2IBT, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrRDdr3RC2IBT) / sizeof (PSCFG_MR2IBT_ENTRY), - (VOID *)&OrRDdr3RC2IBT -}; - -// RC10[OperatingSpeed] -// Format : -// DDRrate, Operating Speed -// -STATIC CONST PSCFG_OPSPD_ENTRY OrRDdr3OpSPD[] = { - {DDR667 + DDR800, 0}, - {DDR1066, 1}, - {DDR1333, 2}, - {DDR1600, 3}, - {DDR1866, 4} -}; -CONST PSC_TBL_ENTRY RC10OpSpdTblEntRG34 = { - {PSCFG_RC10OPSPD, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrRDdr3OpSPD) / sizeof (PSCFG_OPSPD_ENTRY), - (VOID *)&OrRDdr3OpSPD -}; - -// -// MemClkDis -// -STATIC CONST UINT8 ROMDATA Or3RDdr3CLKDis[] = {0x03, 0x0C, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntRG34 = { - {PSCFG_CLKDIS, RDIMM_TYPE, _1DIMM + _2DIMM + _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or3RDdr3CLKDis) / sizeof (UINT8), - (VOID *)&Or3RDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrG34RDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0x41} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntRG34 = { - {PSCFG_WL_PASS1_SEED, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrG34RDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrG34RDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrG34RDIMM[] = { - {_1DIMM, CH_A, 0x43}, - {_1DIMM, CH_B, 0x3F}, - {_1DIMM, CH_C, 0x3A}, - {_1DIMM, CH_D, 0x35}, - {_2DIMM, CH_A, 0x54}, - {_2DIMM, CH_B, 0x4D}, - {_2DIMM, CH_C, 0x45}, - {_2DIMM, CH_D, 0x40}, - {_3DIMM, CH_A, 0x6B}, - {_3DIMM, CH_B, 0x5E}, - {_3DIMM, CH_C, 0x4B}, - {_3DIMM, CH_D, 0x3D} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntRG34 = { - {PSCFG_HWRXEN_PASS1_SEED, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrG34RDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrG34RDIMM -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpUorG3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpUorG3.c deleted file mode 100644 index fee4e786f8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpUorG3.c +++ /dev/null @@ -1,351 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpUorG3.c - * - * Platform specific settings for OR G34 DDR3 U-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/G34) - * @e \$Revision: 56269 $ @e \$Date: 2011-07-11 12:37:42 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "PlatformMemoryConfiguration.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_PS_OR_G34_MPUORG3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrG34UDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR667, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x003B0000, 0x00112222}, - {1, DDR800, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR800, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x003B0000, 0x10112222}, - {1, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00383837, 0x20112222}, - {1, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00363635, 0x30112222}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x00353533, 0x30112222}, - {1, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003533, 0x30112222}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x00333330, 0x30332222}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003330, 0x30332222}, - {2, DDR667, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x003B0000, 0x00112222}, - {2, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x003B0000, 0x10112222}, - {2, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00383837, 0x20112222}, - {2, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x003A3A3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00363635, 0x30112222}, - {2, DDR1333, VOLT_ALL, DIMM_SR, DIMM_SR, NP, 1, 0x00003939, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, 1, 0x00003938, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00003938, 0x30222222}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, 0, 0x00353533, 0x30112222}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, 1, 0x00003533, 0x30112222}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, 1, 0x00003738, 0x30222222}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, 1, 0x00003737, 0x30222222}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00003737, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_SR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_DR, 0, 0x003B0000, 0x00332222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x10222222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_SR, 0, 0x00000000, 0x10332222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_DR, 0, 0x003B0000, 0x10332222}, - {3, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x20222222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00383837, 0x20332222}, - {3, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x003A3A3A, 0x30222222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00363635, 0x30332222}, - {3, DDR1333, VOLT_ALL, DIMM_SR, NP, DIMM_SR, 1, 0x00003939, 0x30222222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, 1, 0x00003938, 0x30222222}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 0x00003938, 0x30222222}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, 0, 0x00353533, 0x30332222}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, 1, 0x00003533, 0x30332222}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_SR, 1, 0x00003738, 0x30222222}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, 1, 0x00003737, 0x30222222}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 0x00003737, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntUG34 = { - {PSCFG_SAO, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34UDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrG34UDdr3SAO -}; -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrG34UDdr3S__[] = { - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066 + DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, 0}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_5 + V1_35, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_25, NP, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 0}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, 0}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5 + V1_35, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_25, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - }; -CONST PSC_TBL_ENTRY S__TblEntUG34 = { - {PSCFG_S__, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34UDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrG34UDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1UDdr3OdtPat[] = { - {DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001}, - {DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntUG34 = { - {PSCFG_ODT_PAT_1D, UDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or1UDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1UDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2UDdr3OdtPat[] = { - {NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000}, - {NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntUG34 = { - {PSCFG_ODT_PAT___, UDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or2UDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2UDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3UDdr3OdtPat[] = { - {NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000004, 0x00000000}, - {DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x00000405} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntUG34 = { - {PSCFG_ODT_PAT_3D, UDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or3UDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3UDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr -// -STATIC CONST PSCFG_RTT_ENTRY DramTermOrG34UDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 4, 1}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_SR, R0, 4, 1}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 4, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1333, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 4, 1}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntUG34 = { - {PSCFG_RTT, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (DramTermOrG34UDIMM) / sizeof (PSCFG_RTT_ENTRY), - (VOID *)&DramTermOrG34UDIMM -}; - -// Max Freq. -// Format : -// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrG34UDIMM[] = { - {{1, 1, 1, 0, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 1, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}} -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntUG34 = { - {PSCFG_MAXFREQ, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrG34UDIMM) / sizeof (PSCFG_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrG34UDIMM -}; - -// -// MemClkDis -// -STATIC CONST UINT8 ROMDATA OrUDdr3CLKDis[] = {0x01, 0x04, 0x02, 0x18, 0x20, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntUG34 = { - {PSCFG_CLKDIS, UDIMM_TYPE, _1DIMM + _2DIMM + _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrUDdr3CLKDis) / sizeof (UINT8), - (VOID *)&OrUDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrG34UDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0x0F} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntUG34 = { - {PSCFG_WL_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrG34UDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrG34UDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrG34UDIMM[] = { - {_1DIMM, CH_A, 0x3E}, - {_1DIMM, CH_B, 0x38}, - {_1DIMM, CH_C, 0x37}, - {_1DIMM, CH_D, 0x31}, - {_2DIMM, CH_A, 0x51}, - {_2DIMM, CH_B, 0x4A}, - {_2DIMM, CH_C, 0x46}, - {_2DIMM, CH_D, 0x3F}, - {_3DIMM, CH_A, 0x5E}, - {_3DIMM, CH_B, 0x52}, - {_3DIMM, CH_C, 0x48}, - {_3DIMM, CH_D, 0x3C} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntUG34 = { - {PSCFG_HWRXEN_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrG34UDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrG34UDIMM -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/Makefile.inc deleted file mode 100644 index 412f9dd1bd..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mpor3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c deleted file mode 100644 index f4464e938b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c +++ /dev/null @@ -1,228 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpor3.c - * - * Platform specific settings for OR - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "Filecode.h" - -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - - -#define FILECODE PROC_MEM_PS_OR_MPOR3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// -// Common tables of Orochi platform specific configuration -// - -// MR0[WR] -// Format : -// D18F2x22C_dct[1:0][Twr], MR0[WR] -// -CONST PSCFG_MR0WR_ENTRY MR0WR[] = { - {0x10, 0}, - {0x05, 1}, - {0x06, 2}, - {0x07, 3}, - {0x08, 4}, - {0x0A, 5}, - {0x0C, 6}, - {0x0E, 7} -}; -CONST PSC_TBL_ENTRY MR0WrTblEntry = { - {PSCFG_MR0WR, DT_DONT_CARE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (MR0WR) / sizeof (PSCFG_MR0WR_ENTRY), - (VOID *)&MR0WR -}; - -// MR0[CL] -// Format : -// D18F2x200_dct[1:0][Tcl], MR0[CL][3:1], MR0[CL][0] -// -CONST PSCFG_MR0CL_ENTRY MR0CL[] = { - {0x05, 1, 0}, - {0x06, 2, 0}, - {0x07, 3, 0}, - {0x08, 4, 0}, - {0x09, 5, 0}, - {0x0A, 6, 0}, - {0x0B, 7, 0}, - {0x0C, 0, 1}, - {0x0D, 1, 1}, - {0x0E, 2, 1}, - {0x0F, 3, 1}, - {0x10, 4, 1} -}; -CONST PSC_TBL_ENTRY MR0CLTblEntry = { - {PSCFG_MR0CL, DT_DONT_CARE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (MR0CL) / sizeof (PSCFG_MR0CL_ENTRY), - (VOID *)&MR0CL -}; - - -// -// CKE tri-state -// -STATIC CONST UINT8 ROMDATA OrDdr3CKETri[] = {0x55, 0xAA}; -CONST PSC_TBL_ENTRY OrDdr3CKETriEnt = { - {PSCFG_CKETRI, DT_DONT_CARE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrDdr3CKETri) / sizeof (UINT8), - (VOID *)&OrDdr3CKETri -}; - - -// -// ODT tri-state [UDIMM & RDIMM][1DPC & 2DPC] -// -// Bit 0: MEMODT[1,0][0] -// Bit 1: MEMODT[1,0][1] -// Bit 2: MEMODT[1,0][2] -// Bit 3: MEMODT[1,0][3] -// -// Dimm 0 : BP_MEMCSx[1:0], BP_MEMODTx[2, 0] -// Dimm 1 : BP_MEMCSx[3:2], BP_MEMODTx[3, 1] -STATIC CONST UINT8 ROMDATA OrDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08}; -CONST PSC_TBL_ENTRY OrDdr3ODTTriEnt = { - {PSCFG_ODTTRI, UDIMM_TYPE + RDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrDdr3ODTTri) / sizeof (UINT8), - (VOID *)&OrDdr3ODTTri -}; -// -// ODT tri-state [UDIMM & RDIMM][3DPC] -// -// Dimm 0: BP_MEMCSx[1:0], BP_MEMODTx[0] -// Dimm 1: BP_MEMCSx[7:6, 3:2], BP_MEMODTx[3, 1] -// Dimm 2: BP_MEMCSx[5:4], BP_MEMODTx[2] -STATIC CONST UINT8 ROMDATA OrDdr3ODTTri3D[] = {0x03, 0x44, 0x30, 0x88}; -CONST PSC_TBL_ENTRY OrDdr3ODTTri3DEnt = { - {PSCFG_ODTTRI, UDIMM_TYPE + RDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrDdr3ODTTri3D) / sizeof (UINT8), - (VOID *)&OrDdr3ODTTri3D -}; - - -// -// ODT tri-state [LRDIMM][1DPC & 2DPC] -// -// Bit 0: MEMODT[1,0][0] -// Bit 1: MEMODT[1,0][1] -// Bit 2: MEMODT[1,0][2] -// Bit 3: MEMODT[1,0][3] -// -// Dimm 0 : BP_MEMCSx[5:4, 1:0], BP_MEMODTx[2, 0] -// Dimm 1 : BP_MEMCSx[7:6, 3:2], BP_MEMODTx[3, 1] -// LR : Assert DIMM ODT0 only -STATIC CONST UINT8 ROMDATA OrLRDdr3ODTTri[] = {0x03, 0x0C, 0x00, 0x00}; -CONST PSC_TBL_ENTRY OrLRDdr3ODTTriEnt = { - {PSCFG_ODTTRI, LRDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrLRDdr3ODTTri) / sizeof (UINT8), - (VOID *)&OrLRDdr3ODTTri -}; - -// -// ODT tri-state [LRDIMM][3DPC] -// -// Dimm 0: BP_MEMCSx[1:0], BP_MEMODTx[0] -// Dimm 1: BP_MEMCSx[7:6, 3:2], BP_MEMODTx[3, 1] -// Dimm 2: BP_MEMCSx[5:4], BP_MEMODTx[2] -// LR : Assert DIMM ODT0 only -STATIC CONST UINT8 ROMDATA OrLRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC0}; -CONST PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt = { - {PSCFG_ODTTRI, LRDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrLRDdr3ODTTri3D) / sizeof (UINT8), - (VOID *)&OrLRDdr3ODTTri3D -}; - -// -// ChipSel tri-state [UDIMM] -// -STATIC CONST UINT8 ROMDATA OrUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}; -CONST PSC_TBL_ENTRY OrUDdr3CSTriEnt = { - {PSCFG_CSTRI, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrUDdr3CSTri) / sizeof (UINT8), - (VOID *)&OrUDdr3CSTri -}; -// -// ChipSel tri-state [RDIMM & LRDIMM] -// BIOS must not tri-state chip select pin corresponding to the second chip -// select of a single rank registered dimm -STATIC CONST UINT8 ROMDATA OrDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0}; -CONST PSC_TBL_ENTRY OrDdr3CSTriEnt = { - {PSCFG_CSTRI, LRDIMM_TYPE + RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrDdr3CSTri) / sizeof (UINT8), - (VOID *)&OrDdr3CSTri -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c deleted file mode 100644 index 92250693ef..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c +++ /dev/null @@ -1,1225 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mp.c - * - * Common platform specific configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 55046 $ @e \$Date: 2011-06-15 23:59:07 -0600 (Wed, 15 Jun 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MP_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define PSO_TYPE 0 -#define PSO_LENGTH 1 -#define PSO_DATA 2 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPPSCGen ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -BOOLEAN -STATIC -MemPCheckTblDrvOverrideConfig ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemPCheckTblDrvOverrideConfigSpeedLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -VOID -STATIC -MemPTblDrvOverrideSpeedLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -UINT8 -STATIC -MemPTblDrvOverrideODT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -VOID -STATIC -MemPTblDrvOverrideODTPattern ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -UINT8 -STATIC -MemPTblDrvOverrideRC2IBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer, - IN UINT8 NumOfReg - ); - -BOOLEAN -STATIC -MemPTblDrvOverrideMR0WR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemPTblDrvOverrideMR0CL ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemPTblDrvOverrideMR10OpSpeed ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is the default return function of the Platform Specific block. The function always - * returns AGESA_UNSUPPORTED - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_UNSUPPORTED AGESA status indicating that default is unsupported - * - */ - -AGESA_STATUS -MemPConstructPsUDef ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - return AGESA_UNSUPPORTED; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function will set the DramTerm and DramTermDyn in the structure of a channel. - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * @param[in] ArraySize Size of the array of DramTerm - * @param[in] *DramTermPtr Address the array of DramTerm - * - * @return TRUE - Find DramTerm and DramTermDyn for corresponding platform and dimm population. - * @return FALSE - Fail to find DramTerm and DramTermDyn for corresponding platform and dimm population. - * - */ -BOOLEAN -MemPGetDramTerm ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ArraySize, - IN CONST DRAM_TERM_ENTRY *DramTermPtr - ) -{ - UINT8 Dimms; - UINT8 QR_Dimms; - UINT8 i; - Dimms = NBPtr->ChannelPtr->Dimms; - QR_Dimms = 0; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { - if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) { - QR_Dimms ++; - } - } - - for (i = 0; i < ArraySize; i ++) { - if ((DramTermPtr[i].Speed & ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66))) != 0) { - if ((((UINT8) (1 << (Dimms - 1)) & DramTermPtr[i].Dimms) != 0) || (DramTermPtr[i].Dimms == ANY_NUM)) { - if (((QR_Dimms == 0) && (DramTermPtr[i].QR_Dimms == NO_DIMM)) || - ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & DramTermPtr[i].QR_Dimms) != 0)) || - (DramTermPtr[i].QR_Dimms == ANY_NUM)) { - NBPtr->PsPtr->DramTerm = DramTermPtr[i].DramTerm; - NBPtr->PsPtr->QR_DramTerm = DramTermPtr[i].QR_DramTerm; - NBPtr->PsPtr->DynamicDramTerm = DramTermPtr[i].DynamicDramTerm; - break; - } - } - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets the highest POR supported speed. - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * @param[in] FreqLimitSize Size of the array of Frequency Limit - * @param[in] *FreqLimitPtr Address the array of Frequency Limit - * - * @return UINT8 - frequency limit - * - */ -UINT16 -MemPGetPorFreqLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 FreqLimitSize, - IN CONST POR_SPEED_LIMIT *FreqLimitPtr - ) -{ - UINT8 i; - UINT8 j; - UINT8 DimmTpMatch; - UINT16 SpeedLimit; - UINT16 DIMMRankType; - UINT16 _DIMMRankType; - - SpeedLimit = 0; - DIMMRankType = MemAGetPsRankType (NBPtr->ChannelPtr); - for (i = 0; i < FreqLimitSize; i++, FreqLimitPtr++) { - if (NBPtr->ChannelPtr->Dimms != FreqLimitPtr->Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & FreqLimitPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j ++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == FreqLimitPtr->Dimms) { - if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { - SpeedLimit = FreqLimitPtr->SpeedLimit_1_5V; - break; - } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) { - SpeedLimit = FreqLimitPtr->SpeedLimit_1_25V; - break; - } else { - SpeedLimit = FreqLimitPtr->SpeedLimit_1_35V; - break; - } - } - } - - return SpeedLimit; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the default function for getting POR speed limit. When a - * package does not need to cap the speed, it should use this function to initialize - * the corresponding function pointer. - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - */ -VOID -MemPGetPORFreqLimitDef ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets the seed value of WL and HW RxEn pass 1 training. - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Entries are found - * @return FALSE - Entries are not found - * - */ -BOOLEAN -MemPGetPSCPass1Seed ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - UINT8 Dct; - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - i = 0; - while (memPlatSpecFlowArray[i] != NULL) { - if (!(memPlatSpecFlowArray[i])->TrainingSeedVal (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - return FALSE; - } - i++; - } - } - - return TRUE; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term, - * and so on. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Successfully execute platform specific configuration flow. - * @return FALSE - Fail to execute platform specific configuration flow. - * - */ -BOOLEAN -MemPPSCFlow ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - BOOLEAN Result; - - Result = TRUE; - i = 0; - while (memPlatSpecFlowArray[i] != NULL) { - if ((memPlatSpecFlowArray[i])->DramTerm (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->ODTPattern (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->SAO (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->MR0WrCL (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->RC2IBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->RC10OpSpeed (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->LRIBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->LRNPR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->LRNLR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if (MemPPSCGen (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - break; - } - } - } - } - } - } - } - } - } - } - i++; - } - - IDS_SKIP_HOOK (IDS_ENFORCE_PLAT_TABLES, NBPtr, &(NBPtr->MemPtr->StdHeader)) { - if (memPlatSpecFlowArray[i] == NULL) { - Result = FALSE; - } - } - return Result; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number - * of dimm in the table. - * - * @param[in] Dimm0 Rank type of Dimm0 - * @param[in] Dimm1 Rank type of Dimm1 - * @param[in] Dimm2 Rank type of Dimm2 - * @param[in, out] *RankTypeInTable Pointer to RankTypeInTable variable - * - * - */ -VOID -MemPConstructRankTypeMap ( - IN UINT16 Dimm0, - IN UINT16 Dimm1, - IN UINT16 Dimm2, - IN OUT UINT16 *RankTypeInTable - ) -{ - UINT8 i; - UINT16 RT; - UINT8 BitShift; - - *RankTypeInTable = 0; - RT = 0; - BitShift = 0; - - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - switch (i) { - case 0: - RT = (Dimm0 == 0) ? NP : Dimm0; - BitShift = 0; - break; - case 1: - RT = (Dimm1 == 0) ? NP : Dimm1; - BitShift = 4; - break; - case 2: - RT = (Dimm2 == 0) ? NP : Dimm2; - BitShift = 8; - break; - default: - // dimm3 is not used, fills nibble3 with "NP" - RT = NP; - BitShift = 12; - } - *RankTypeInTable |= RT << BitShift; - } -} - -/*-----------------------------------------------------------------------------*/ -/** - * MemPIsIdSupported - * This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to - * determine if it is supported by this NB type. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] LogicalId - CPU_LOGICAL_ID - * @param[in] PackageType - Package Type - * - * @return TRUE - NB type is matched ! - * @return FALSE - NB type is not matched ! - * - */ -BOOLEAN -MemPIsIdSupported ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID LogicalId, - IN UINT8 PackageType - ) -{ - CPUID_DATA CpuId; - UINT8 PkgType; - - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, &(NBPtr->MemPtr->StdHeader)); - PkgType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 - - if (((NBPtr->MCTPtr->LogicalCpuid.Family & LogicalId.Family) != 0) - && ((NBPtr->MCTPtr->LogicalCpuid.Revision & LogicalId.Revision) != 0)) { - if ((PackageType == PT_DONT_CARE) || (PackageType == PkgType)) { - return TRUE; - } - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the rank type map of a channel. - * - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return UINT16 - The map of rank type. - * - */ -UINT16 -MemPGetPsRankType ( - IN CH_DEF_STRUCT *CurrentChannel - ) -{ - UINT8 i; - UINT16 DIMMRankType; - - DIMMRankType = 0; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if (CurrentChannel->MCTPtr->Status[SbLrdimms]) { - // For LrDimm, we construct the map according to Dimm present bits rather than rank type bits - if ((CurrentChannel->LrDimmPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) DIMM_LR << (i << 2); - } else { - DIMMRankType |= (UINT16) NP << (i << 2); - } - } else { - if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) { - if (i < 2) { - DIMMRankType |= (UINT16) DIMM_QR << (i << 2); - } - } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) DIMM_DR << (i << 2); - } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) DIMM_SR << (i << 2); - } else { - DIMMRankType |= (UINT16) NP << (i << 2); - } - } - } - - return DIMMRankType; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function performs the action for the rest of platform specific configuration such as - * tri-state stuff - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - No error occurred. - * @return FALSE - Error occurred. - * - */ -BOOLEAN -STATIC -MemPPSCGen ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - PSCFG_TYPE PSCType; - DIMM_TYPE DimmType; - UINT8 MaxDimmPerCh; - UINT8 NOD; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - CH_DEF_STRUCT *CurrentChannel; - UINT32 EventInfo; - - CurrentChannel = NBPtr->ChannelPtr; - - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - for (PSCType = PSCFG_GEN_START + 1; PSCType < PSCFG_GEN_END; PSCType++) { - i = 0; - while (EntryOfTables->TblEntryOfGen[i] != NULL) { - if ((EntryOfTables->TblEntryOfGen[i])->Header.PSCType == PSCType) { - if (((EntryOfTables->TblEntryOfGen[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfGen[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfGen[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfGen[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - break; - } - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfGen[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s Table\n", (PSCType == PSCFG_CLKDIS) ? "ClkDis" : ((PSCType == PSCFG_CKETRI) ? "CkeTri" : ((PSCType == PSCFG_ODTTRI) ? "OdtTri" : "CsTri"))); - EventInfo = (PSCType == PSCFG_CLKDIS) ? MEM_ERROR_CLK_DIS_MAP_NOT_FOUND : ((PSCType == PSCFG_CKETRI) ? MEM_ERROR_CKE_TRI_MAP_NOT_FOUND : ((PSCType == PSCFG_ODTTRI) ? MEM_ERROR_ODT_TRI_MAP_NOT_FOUND : MEM_ERROR_CS_TRI_MAP_NOT_FOUND)); - PutEventLog (AGESA_ERROR, EventInfo, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - - // Perform the action for specific PSCType. - if (PSCType == PSCFG_CLKDIS) { - CurrentChannel->MemClkDisMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } else if (PSCType == PSCFG_CKETRI) { - CurrentChannel->CKETriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } else if (PSCType == PSCFG_ODTTRI) { - CurrentChannel->ODTTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } else if (PSCType == PSCFG_CSTRI) { - CurrentChannel->ChipSelTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } - } - - CurrentChannel->DctEccDqsLike = 0x0403; - CurrentChannel->DctEccDqsScale = 0x70; - - return TRUE; -} - - - /* -----------------------------------------------------------------------------*/ -/** - * - * This function proceeds Table Driven Overriding. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] PlatformMemoryConfiguration - Pointer to Platform config table - * @param[in] ProceededPSOType - Proceeded PSO type - * - * @return bit0 ~ bit7 - Overriding CS or DIMM map. - * @return bit15 - Invalid entry found if set. - * - */ -UINT16 -MemPProceedTblDrvOverride ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 ProceededPSOType - ) -{ - UINT8 *Buffer; - UINT8 *PSOStartPtr; - UINT8 NumOfReg; - UINT8 RetVal; - UINT16 RetVal16; - BOOLEAN ConfigMatched; - BOOLEAN FirstGoThrough; - BOOLEAN FindNewConfig; - BOOLEAN InvertRetVal; - BOOLEAN InvalidConfigDetected; - - - ASSERT (PlatformMemoryConfiguration != NULL); - ASSERT ((ProceededPSOType >= PSO_TBLDRV_START) && (ProceededPSOType <= PSO_TBLDRV_END)); - - NumOfReg = 0; - RetVal = 0; - RetVal16 = 0; - FirstGoThrough = TRUE; - InvertRetVal = FALSE; - InvalidConfigDetected = FALSE; - // - // << P E R S P E C T I V E >> - // - // PlatformMemoryConfiguration [] = { - // . . . . . . . . . . . . . . . . . . . - // . . . . . . . . . . . . . . . . . . . - // TBLDRV_CONFIG_TO_OVERRIDE (2, DDR1600, VOLT1_5_ + VOLT1_35_, SR_DIMM0 + DR_DIMM1), - // TBLDRV_CONFIG_ENTRY_RTTNOM (CS2_ + CS3_, 2), - // TBLDRV_CONFIG_ENTRY_RTTWR (CS2_, 2), - // TBLDRV_CONFIG_ENTRY_RTTWR (CS3_, 1), - // TBLDRV_CONFIG_ENTRY_ADDRTMG (0x003C3C3C), - // TBLDRV_CONFIG_ENTRY_ODCCTRL (0x20112222), - // - // TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE (2, 2, 0, 0) - // TBLDRV_CONFIG_ENTRY_SPEEDLIMIT (DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY), - // - // TBLDRV_CONFIG_TO_OVERRIDE (2, DDR1333, VOLT1_5_ + VOLT1_35_, SR_DIMM0 + DR_DIMM1), - // TBLDRV_CONFIG_ENTRY_RTTNOM (CS2_ + CS3_, 3), - // TBLDRV_CONFIG_ENTRY_RTTWR (CS2_ + CS3_, 0), - // - // TBLDRV_OVERRIDE_MR0_WR (3, 5) - // TBLDRV_OVERRIDE_MR0_WR (4, 6) - // - // TBLDRV_OVERRIDE_MR0_CL (3, 5) - // TBLDRV_OVERRIDE_MR0_CL (4, 6) - // . . . . . . . . . . . . . . . . . . . - // . . . . . . . . . . . . . . . . . . . - // - // PSO_END - // } - // - Buffer = PlatformMemoryConfiguration; - // Look for configuration descriptor and its sub-descriptor. - while (Buffer[PSO_TYPE] != PSO_END) { - FindNewConfig = FALSE; - ConfigMatched = FALSE; - if (Buffer[PSO_TYPE] == PSO_TBLDRV_CONFIG) { - // - // Config. descriptor is found, check its sub-descriptor to execute different checking routine. - // - if ((Buffer[PSO_DATA] == CONFIG_SPEEDLIMIT) && (ProceededPSOType == PSO_TBLDRV_SPEEDLIMIT)) { - if (MemPCheckTblDrvOverrideConfigSpeedLimit (NBPtr, &Buffer[PSO_DATA + 1])) { - ConfigMatched = TRUE; - } - } else if (Buffer[PSO_DATA] == CONFIG_DONT_CARE) { - ConfigMatched = TRUE; - } else { - if (MemPCheckTblDrvOverrideConfig (NBPtr, &Buffer[PSO_DATA + 1])) { - ConfigMatched = TRUE; - if ((Buffer[PSO_DATA] == CONFIG_RC2IBT) && (ProceededPSOType == PSO_TBLDRV_RC2_IBT)) { - NumOfReg = Buffer[PSO_DATA + 9]; - } - } - } - } - - if (ConfigMatched) { - // - // If config. is matched, parsing "Table Driven PSO" macros behinds this config. macro until PSO_END is reached. - // - PSOStartPtr = Buffer + (Buffer[PSO_LENGTH] + 2); - // Look for the current proceeded PSO type in PlatformMemoryConfiguration array. - while ((PSOStartPtr[PSO_TYPE] != PSO_END)) { - if (PSOStartPtr[PSO_TYPE] == PSO_TBLDRV_CONFIG) { - // - // If there is an additional config. macro existed, break this while loop, - // then check its content with real platform config. again. - // If matched, parsing "Table Driven PSO" macros behind it. - // - Buffer = PSOStartPtr; - FindNewConfig = TRUE; - break; - } else if (PSOStartPtr[PSO_TYPE] == PSO_TBLDRV_INVALID_TYPE) { - InvalidConfigDetected = TRUE; - break; - } - - if (PSOStartPtr[PSO_TYPE] == ProceededPSOType) { - // - // Pre-set overriding Cs/Dimm map to "0xFF" for the types which are regardless of Cs/Dimm - // for the first time going through the overriding routines. - // - if (FirstGoThrough) { - RetVal = 0xFF; - } - switch (ProceededPSOType) { - case PSO_TBLDRV_SPEEDLIMIT : - MemPTblDrvOverrideSpeedLimit (NBPtr, &PSOStartPtr[PSO_DATA]); - break; - - case PSO_TBLDRV_ODT_RTTNOM : - case PSO_TBLDRV_ODT_RTTWR : - // Mask off Cs overridng map to record which Cs has been overridden. - RetVal &= ~ MemPTblDrvOverrideODT (NBPtr, &PSOStartPtr[PSO_TYPE]); - // Indicate RetVal is inverted. - InvertRetVal = TRUE; - break; - - case PSO_TBLDRV_ODTPATTERN : - MemPTblDrvOverrideODTPattern (NBPtr, &PSOStartPtr[PSO_DATA]); - break; - - case PSO_TBLDRV_ADDRTMG : - NBPtr->ChannelPtr->DctAddrTmg = *(UINT32 *)&PSOStartPtr[PSO_DATA]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: AddrTmg = 0x%x for Dct%d\n\n", *(UINT32 *)&PSOStartPtr[PSO_DATA], NBPtr->Dct); - break; - - case PSO_TBLDRV_ODCCTRL : - NBPtr->ChannelPtr->DctOdcCtl = *(UINT32 *)&PSOStartPtr[PSO_DATA]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: OdcCtl = 0x%x for Dct%d\n\n", *(UINT32 *)&PSOStartPtr[PSO_DATA], NBPtr->Dct); - break; - - case PSO_TBLDRV_SLOWACCMODE : - NBPtr->ChannelPtr->SlowMode = (PSOStartPtr[PSO_DATA] == 1) ? TRUE : FALSE; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: Slow Access Mode = %d for Dct%d\n\n", PSOStartPtr[PSO_DATA], NBPtr->Dct); - break; - - case PSO_TBLDRV_RC2_IBT : - // Mask off Dimm overridng map to record which Dimm has been overridden. - RetVal &= ~ MemPTblDrvOverrideRC2IBT (NBPtr, &PSOStartPtr[PSO_DATA], NumOfReg); - // Indicate RetVal is inverted. - InvertRetVal = TRUE; - break; - - case PSO_TBLDRV_MR0_CL : - RetVal = 0; - if (MemPTblDrvOverrideMR0WR (NBPtr, &PSOStartPtr[PSO_DATA])) { - RetVal = 0xFF; - } - break; - - case PSO_TBLDRV_MR0_WR : - RetVal = 0; - if (MemPTblDrvOverrideMR0CL (NBPtr, &PSOStartPtr[PSO_DATA])) { - RetVal = 0xFF; - } - break; - - case PSO_TBLDRV_RC10_OPSPEED : - RetVal = 0; - if (MemPTblDrvOverrideMR10OpSpeed (NBPtr, &PSOStartPtr[PSO_DATA])) { - RetVal = 0xFF; - } - break; - - case PSO_TBLDRV_LRDIMM_IBT : - NBPtr->PsPtr->F0RC8 = PSOStartPtr[PSO_DATA]; - NBPtr->PsPtr->F1RC0 = PSOStartPtr[PSO_DATA + 1]; - NBPtr->PsPtr->F1RC1 = PSOStartPtr[PSO_DATA + 2]; - NBPtr->PsPtr->F1RC2 = PSOStartPtr[PSO_DATA + 3]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: LRDIMM IBT for Dct%d\n", NBPtr->Dct); - IDS_HDT_CONSOLE (MEM_FLOW, "\nF0RC8 = %d, F1RC0 = %d, F1RC1 = %d, F1RC2 = %d", PSOStartPtr[PSO_DATA], PSOStartPtr[PSO_DATA + 1], \ - PSOStartPtr[PSO_DATA + 2], PSOStartPtr[PSO_DATA + 3]); - break; - - case PSO_TBLDRV____TRAINING : - RetVal = 0x1; - NBPtr->Override__Training = (PSOStartPtr[PSO_DATA] == 1) ? TRUE : FALSE; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: Training = %d for Dct%d\n\n", PSOStartPtr[PSO_DATA], NBPtr->Dct); - break; - - default: - ASSERT (FALSE); - } - FirstGoThrough = FALSE; - } - PSOStartPtr += (PSOStartPtr[PSO_LENGTH] + 2); - } - - if (FindNewConfig) { - continue; - } - RetVal = (InvertRetVal) ? ~RetVal : RetVal; - RetVal16 = (UINT16) RetVal; - if (InvalidConfigDetected) { - RetVal16 |= INVALID_CONFIG_FLAG; - } - - return RetVal16; - } - Buffer += (Buffer[PSO_LENGTH] + 2); - } - - RetVal = (InvertRetVal) ? ~RetVal : RetVal; - RetVal16 = (UINT16) RetVal; - if (InvalidConfigDetected) { - RetVal16 |= INVALID_CONFIG_FLAG; - } - return RetVal16; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the speed limit. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - */ -VOID -STATIC -MemPTblDrvOverrideSpeedLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - UINT8 CurrentVoltage; - - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: Max. Memory Speed for Dct%d\n", NBPtr->Dct); - - LibAmdMemCopy (NBPtr->PsPtr->SpeedLimit, Buffer, 6, &(NBPtr->MemPtr->StdHeader)); - - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%s -> %dMHz\t", (CurrentVoltage == VOLT1_5_ENCODED_VAL) ? "1.5V" : ((CurrentVoltage == VOLT1_35_ENCODED_VAL) ? "1.35V" : "1.25V"), NBPtr->PsPtr->SpeedLimit[CurrentVoltage]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the ODTs (RttNom and RttWr). - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return Target CS overriding bit map - * - */ -UINT8 -STATIC -MemPTblDrvOverrideODT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - UINT16 i; - UINT8 TgtCS; - - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: ODT for Dct%d\n", NBPtr->Dct); - if (Buffer[0] == PSO_TBLDRV_ODT_RTTNOM) { - IDS_HDT_CONSOLE (MEM_FLOW, "RttNom = %d for ", Buffer[3]); - } else { - IDS_HDT_CONSOLE (MEM_FLOW, "RttWr = %d for ", Buffer[3]); - } - ); - - TgtCS = Buffer[2]; - for (i = 0; i < MAX_CS_PER_CHANNEL; i++) { - if ((NBPtr->DCTPtr->Timings.CsEnabled & (UINT16) (1 << i)) != 0) { - if ((TgtCS & (UINT8) 1 << i) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "CS%d ", i); - if (Buffer[0] == PSO_TBLDRV_ODT_RTTNOM) { - NBPtr->PsPtr->RttNom[i] = Buffer[3]; - } else { - NBPtr->PsPtr->RttWr[i] = Buffer[3]; - } - } - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - - return TgtCS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the ODT patterns. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - */ -VOID -STATIC -MemPTblDrvOverrideODTPattern ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: ODT pattern for Dct%d\n", NBPtr->Dct); - IDS_HDT_CONSOLE (MEM_FLOW, "\nRODTCSHigh = 0x%x\n", *(UINT32 *)&Buffer[0]); - IDS_HDT_CONSOLE (MEM_FLOW, "\nRODTCSLow = 0x%x\n", *(UINT32 *)&Buffer[4]); - IDS_HDT_CONSOLE (MEM_FLOW, "\nWODTCSHigh = 0x%x\n", *(UINT32 *)&Buffer[8]); - IDS_HDT_CONSOLE (MEM_FLOW, "\nWODTCSLow = 0x%x\n", *(UINT32 *)&Buffer[12]); - - CurrentChannel->PhyRODTCSHigh = *(UINT32 *)&Buffer[0]; - CurrentChannel->PhyRODTCSLow = *(UINT32 *)&Buffer[4]; - CurrentChannel->PhyWODTCSHigh = *(UINT32 *)&Buffer[8]; - CurrentChannel->PhyWODTCSLow = *(UINT32 *)&Buffer[12]; - - //WL ODTs need to be modified as well while overriding... - CurrentChannel->PhyWLODT[0] = (UINT8) (CurrentChannel->PhyWODTCSLow & 0x0F); - CurrentChannel->PhyWLODT[1] = (UINT8) ((CurrentChannel->PhyWODTCSLow >> 16) & 0x0F); - CurrentChannel->PhyWLODT[2] = (UINT8) (CurrentChannel->PhyWODTCSHigh & 0x0F); - CurrentChannel->PhyWLODT[3] = (UINT8) ((CurrentChannel->PhyWODTCSHigh >> 16) & 0x0F); - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the Ctrl Word 2 and 8. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * @param[in] NumOfReg - Number of registers - * - * @return Target DIMM overridng bit map - * - */ -UINT8 -STATIC -MemPTblDrvOverrideRC2IBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer, - IN UINT8 NumOfReg - ) -{ - UINT16 i; - UINT8 TgtDimm; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: RC2[IBT] for Dct%d\n", NBPtr->Dct); - IDS_HDT_CONSOLE (MEM_FLOW, "RC2[IBT] = %d for ", Buffer[1]); - - TgtDimm = Buffer[0]; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((CurrentChannel->ChDimmValid & (UINT16) (1 << i)) != 0) { - if (((TgtDimm & (UINT8) 1 << i) != 0) && (NBPtr->PsPtr->NumOfReg[i] == NumOfReg)) { - IDS_HDT_CONSOLE (MEM_FLOW, "DIMM%d ", i); - CurrentChannel->CtrlWrd02[i] = (Buffer[1] & 0x1) << 2; - CurrentChannel->CtrlWrd08[i] = (Buffer[1] & 0xE) >> 1; - } - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - - return TgtDimm; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides MR0[WR]. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return TRUE : Overridden - * @return FALSE : Not overriden - * - */ -BOOLEAN -STATIC -MemPTblDrvOverrideMR0WR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - if (Buffer[0] == (UINT8) NBPtr->GetBitField (NBPtr, BFTcl)) { - NBPtr->PsPtr->MR0CL31 = Buffer[1]; - NBPtr->PsPtr->MR0CL0 = Buffer[2]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: MR0[CL][3:1] = %d,\tMR0[CL][0] = %d for Dct%d\n", \ - Buffer[1], Buffer[2], NBPtr->Channel); - IDS_HDT_CONSOLE (MEM_FLOW, "Tcl = %d\n\n", (UINT8) NBPtr->GetBitField (NBPtr, BFTcl)); - return TRUE; - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides MR0[WR]. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return TRUE : Overridden - * @return FALSE : Not overriden - * - */ -BOOLEAN -STATIC -MemPTblDrvOverrideMR0CL ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - if (Buffer[0] == (UINT8) NBPtr->GetBitField (NBPtr, BFTwrDDR3)) { - NBPtr->PsPtr->MR0WR = Buffer[1]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: MR0[WR] = %d for Dct%d\n", Buffer[1], NBPtr->Dct); - IDS_HDT_CONSOLE (MEM_FLOW, "Twr = %d\n\n", (UINT8) NBPtr->GetBitField (NBPtr, BFTwrDDR3)); - return TRUE; - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides MR10[OperatingSpeed]. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return TRUE : Overridden - * @return FALSE : Not overriden - * - */ -BOOLEAN -STATIC -MemPTblDrvOverrideMR10OpSpeed ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - UINT32 CurDDRrate; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - - if ((Buffer[0] & CurDDRrate) != 0) { - NBPtr->PsPtr->RC10OpSpd = Buffer[1]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: MR10[OperatingSpeed] = %d for Dct%d\n", Buffer[1], NBPtr->Dct); - return TRUE; - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function checks if platform configuration is matched or not. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return TRUE : Configuration is matched - * @return FALSE : Configuration is not matched - * - */ -BOOLEAN -STATIC -MemPCheckTblDrvOverrideConfig ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - UINT8 MaxDimmPerCh; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - // Get platform configuration. - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemAGetPsRankType (CurrentChannel); - - if ((MaxDimmPerCh == Buffer[0]) && ((DDR3Voltage & Buffer[1]) != 0) && - ((CurDDRrate & *(UINT32 *)&Buffer[2]) != 0) && ((RankTypeOfPopulatedDimm & *(UINT16 *)&Buffer[6]) != 0)) { - return TRUE; - } - - return FALSE; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function checks if platform configuration is matched or not. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return TRUE : Configuration is matched - * @return FALSE : Configuration is not matched - * - */ -BOOLEAN -STATIC -MemPCheckTblDrvOverrideConfigSpeedLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - UINT8 MaxDimmPerCh; - UINT8 NumOfSR; - UINT8 NumOfDR; - UINT8 NumOfQR; - UINT8 NumOfLRDimm; - UINT8 i; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - NumOfSR = 0; - NumOfDR = 0; - NumOfQR = 0; - NumOfLRDimm = 0; - - // Get platform configuration. - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((CurrentChannel->DimmSRPresent & (UINT8) (1 << i)) != 0) { - NumOfSR += 1; - } else if ((CurrentChannel->DimmDrPresent & (UINT16) (1 << i)) != 0) { - NumOfDR += 1; - } else if ((CurrentChannel->DimmQrPresent & (UINT16) (1 << i)) != 0) { - if (i < 2) { - NumOfQR += 1; - } - } else if ((CurrentChannel->LrDimmPresent & (UINT16) (1 << i))) { - NumOfLRDimm += 1; - } - } - - if ((Buffer[0] == MaxDimmPerCh) && (Buffer[1] == CurrentChannel->Dimms)) { - if (NBPtr->MCTPtr->Status[SbLrdimms] == TRUE) { - if (Buffer[5] == NumOfLRDimm) { - return TRUE; - } - } else { - if ((Buffer[2] == NumOfSR) && (Buffer[3] == NumOfDR) && (Buffer[4] == NumOfQR)) { - return TRUE; - } - } - } - - return FALSE; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c deleted file mode 100644 index a8e43e3d26..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c +++ /dev/null @@ -1,206 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mplribt.c - * - * A sub-engine which extracts F0RC8, F1RC0, F1RC1 and F1RC2 value for LRDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPLRIBT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetLRIBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input - * table and stores extracted value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetLRIBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - UINT8 PsoMaskLRIBT; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_L_IBT_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - if (CurrentChannel->LrDimmPresent == 0) { - return TRUE; - } - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. - while (EntryOfTables->TblEntryOfLRIBT[i] != NULL) { - if (((EntryOfTables->TblEntryOfLRIBT[i])->Header.NumOfDimm & NOD) != 0) { - LogicalCpuid = (EntryOfTables->TblEntryOfLRIBT[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfLRIBT[i])->Header.PackageType; - // - // Determine if this is the expected NB Type - // - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_L_IBT_ENTRY *) ((EntryOfTables->TblEntryOfLRIBT[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfLRIBT[i])->TableSize; - break; - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfLRIBT[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - NBPtr->PsPtr->F0RC8 = (UINT8) TblPtr->F0RC8; - NBPtr->PsPtr->F1RC0 = (UINT8) TblPtr->F1RC0; - NBPtr->PsPtr->F1RC1 = (UINT8) TblPtr->F1RC1; - NBPtr->PsPtr->F1RC2 = (UINT8) TblPtr->F1RC2; - break; - } - } - } - } - TblPtr++; - } - // - // If there is no entry, check if overriding value existed. If not, return FALSE - // - PsoMaskLRIBT = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_LRDIMM_IBT); - if ((PsoMaskLRIBT == 0) && (i == TableSize)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_LR_IBT_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c deleted file mode 100644 index ed14c165f1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mplrnlr.c - * - * A sub-engine which extracts F0RC13[NumLogicalRanks] value for LRDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPLRNLR_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetLRNLR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input - * table and stores extracted value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetLRNLR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - return TRUE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c deleted file mode 100644 index bef6eba0f4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mplrnpr.c - * - * A sub-engine which extracts F0RC13[NumPhysicalRanks] value for LRDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPLRNPR_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetLRNPR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input - * table and stores extracted value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetLRNPR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - return TRUE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c deleted file mode 100644 index 4c93c10ebf..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c +++ /dev/null @@ -1,303 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpmaxfreq.c - * - * A sub-engine which extracts max. frequency limit value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52790 $ @e \$Date: 2011-05-11 15:31:24 -0600 (Wed, 11 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPMAXFREQ_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -typedef struct { - UINT16 DimmPerCh:3; - UINT16 Dimms:3; - UINT16 SR:3; - UINT16 DR:3; - UINT16 QR:4; -} CDNMaxFreq; - -typedef struct { - UINT16 DimmPerCh:3; - UINT16 Dimms:3; - UINT16 LR:10; -} CDNLMaxFreq; -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetMaxFreqSupported ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts the value of max frequency supported from a input table and - * compares it with DCTPtr->Timings.TargetSpeed - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetMaxFreqSupported ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - PSCFG_TYPE Type; - UINT16 CDN; - UINT16 MaxFreqSupported; - UINT16 *SpeedArray; - UINT8 DDR3Voltage; - UINT8 CurrentVoltage; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_MAXFREQ_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - BOOLEAN DisDct; - UINT8 PsoMaskMaxFreq; - UINT16 PsoMaskMaxFreq16; - PSC_TBL_ENTRY **TblEntryOfMaxFreq; - - CurrentChannel = NBPtr->ChannelPtr; - - DisDct = FALSE; - Type = PSCFG_MAXFREQ; - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - SpeedArray = NULL; - - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - TblEntryOfMaxFreq = EntryOfTables->TblEntryOfMaxFreq; - IDS_OPTION_HOOK (IDS_GET_STRETCH_FREQUENCY_LIMIT, &TblEntryOfMaxFreq, &NBPtr->MemPtr->StdHeader); - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (TblEntryOfMaxFreq[i] != NULL) { - if (((TblEntryOfMaxFreq[i])->Header.DimmType & DimmType) != 0) { - if (((TblEntryOfMaxFreq[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (TblEntryOfMaxFreq[i])->Header.LogicalCpuid; - PackageType = (TblEntryOfMaxFreq[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_MAXFREQ_ENTRY *) ((TblEntryOfMaxFreq[i])->TBLPtr); - TableSize = (TblEntryOfMaxFreq[i])->TableSize; - Type = (TblEntryOfMaxFreq[i])->Header.PSCType; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (TblEntryOfMaxFreq[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No MaxFreq table. This channel will be disabled.\n", NBPtr->Dct); - return FALSE; - } - - MaxFreqSupported = UNSUPPORTED_DDR_FREQUENCY; - CDN = 0; - DDR3Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage); - - // Construct the condition value - ((CDNMaxFreq *)&CDN)->DimmPerCh = MaxDimmPerCh; - ((CDNMaxFreq *)&CDN)->Dimms = CurrentChannel->Dimms; - if (Type == PSCFG_MAXFREQ) { - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((CurrentChannel->DimmSRPresent & (UINT8) (1 << i)) != 0) { - ((CDNMaxFreq *)&CDN)->SR += 1; - } - if ((CurrentChannel->DimmDrPresent & (UINT16) (1 << i)) != 0) { - ((CDNMaxFreq *)&CDN)->DR += 1; - } - if ((CurrentChannel->DimmQrPresent & (UINT16) (1 << i)) != 0) { - if (i < 2) { - ((CDNMaxFreq *)&CDN)->QR += 1; - } - } - } - } else { - ((CDNLMaxFreq *)&CDN)->LR = CurrentChannel->Dimms; - } - - for (i = 0; i < TableSize; i++) { - if (CDN == ((Type == PSCFG_MAXFREQ) ? TblPtr->MAXFREQ_ENTRY.CDN : - ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.CDN)) { - if (Type == PSCFG_MAXFREQ) { - SpeedArray = TblPtr->MAXFREQ_ENTRY.Speed; - } else { - SpeedArray = ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.Speed; - } - break; - } - TblPtr++; - } - - PsoMaskMaxFreq16 = MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_SPEEDLIMIT); - if ((PsoMaskMaxFreq16 & INVALID_CONFIG_FLAG) == 0) { - PsoMaskMaxFreq = (UINT8) PsoMaskMaxFreq16; - if (PsoMaskMaxFreq != 0) { - SpeedArray = NBPtr->PsPtr->SpeedLimit; - } - } else { - SpeedArray = NULL; - } - - if (SpeedArray != NULL) { - if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nCheck speed supported for each VDDIO for Node%d DCT%d: ", NBPtr->Node, NBPtr->Dct); - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (NBPtr->SharedPtr->VoltageMap & (1 << CurrentVoltage)) { - IDS_HDT_CONSOLE (MEM_FLOW, "%s -> %dMHz ", (CurrentVoltage == VOLT1_5_ENCODED_VAL) ? "1.5V" : ((CurrentVoltage == VOLT1_35_ENCODED_VAL) ? "1.35V" : "1.25V"), SpeedArray[CurrentVoltage]); - if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedArray[CurrentVoltage]) { - MaxFreqSupported = SpeedArray[CurrentVoltage]; - } else { - MaxFreqSupported = NBPtr->DCTPtr->Timings.TargetSpeed; - } - if (NBPtr->MaxFreqVDDIO[CurrentVoltage] > MaxFreqSupported) { - NBPtr->MaxFreqVDDIO[CurrentVoltage] = MaxFreqSupported; - } - } else { - NBPtr->MaxFreqVDDIO[CurrentVoltage] = 0; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - ASSERT (DDR3Voltage <= VOLT1_25_ENCODED_VAL); - MaxFreqSupported = SpeedArray[DDR3Voltage]; - } - - if (MaxFreqSupported == UNSUPPORTED_DDR_FREQUENCY) { - // No entry in the table for current dimm population is found - IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No entry is found in the Max Frequency table\n", NBPtr->Dct); - DisDct = TRUE; - } else if (MaxFreqSupported != 0) { - if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxFreqSupported) { - NBPtr->DCTPtr->Timings.TargetSpeed = MaxFreqSupported; - } - } else if (NBPtr->SharedPtr->VoltageMap == VDDIO_DETERMINED) { - // Dimm population is not supported at current voltage - // Also if there is no performance optimization, disable the DCT - DisDct = TRUE; - } - - if (DisDct) { - NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - } - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c deleted file mode 100644 index 1e1d5dfd29..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c +++ /dev/null @@ -1,194 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpmr0.c - * - * A sub-engine which extracts MR0[WR] and MR0[CL] value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPMR0_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetMR0WrCL ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetMR0WrCL ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - - UINT8 i; - UINT8 j; - UINT8 p; - UINT32 Value32; - UINT8 TableSize; - PSCFG_TYPE Type; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 PsoMaskMR0; - PSCFG_MR0CL_ENTRY *TblPtr; - PSC_TBL_ENTRY **ptr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - TblPtr = NULL; - TableSize = 0; - PsoMaskMR0 = 0; - - // Extract MR0[WR] value, then MR0[CL] value - for (i = 0; i < 2; i++) { - if (i == 0) { - ptr = EntryOfTables->TblEntryOfMR0WR; - Type = PSCFG_MR0WR; - } else { - ptr = EntryOfTables->TblEntryOfMR0CL; - Type = PSCFG_MR0CL; - } - - p = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (ptr[p] != NULL) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (ptr[p])->Header.LogicalCpuid; - PackageType = (ptr[p])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_MR0CL_ENTRY *) ((ptr[p])->TBLPtr); - TableSize = (ptr[p])->TableSize; - break; - } - p++; - } - - // Check whether no table entry is found. - if (ptr[p] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MR0 table\n"); - return FALSE; - } - - Value32 = (Type == PSCFG_MR0WR) ? NBPtr->GetBitField (NBPtr, BFTwrDDR3) : NBPtr->GetBitField (NBPtr, BFTcl); - for (j = 0; j < TableSize; j++, TblPtr++) { - if (Value32 == (UINT32) TblPtr->Timing) { - if (Type == PSCFG_MR0WR) { - NBPtr->PsPtr->MR0WR = (UINT8) TblPtr->Value; - break; - } else { - NBPtr->PsPtr->MR0CL31 = (UINT8) TblPtr->Value; - NBPtr->PsPtr->MR0CL0 = (UINT8) TblPtr->Value1; - break; - } - } - } - - // - // If there is no entry, check if overriding value existed. If not, return FALSE. - // - PsoMaskMR0 = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, ((i == 0) ? PSO_TBLDRV_MR0_WR : PSO_TBLDRV_MR0_CL)); - if ((PsoMaskMR0 == 0) && (j == TableSize)) { - IDS_HDT_CONSOLE (MEM_FLOW, (i == 0) ? "\nNo MR0[WR] entries\n" : "\nNo MR0[CL] entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_MR0_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - } - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c deleted file mode 100644 index ec0017749d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c +++ /dev/null @@ -1,213 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpodtpat.c - * - * A sub-engine which extracts ODT pattern value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPODTPAT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetODTPattern ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts ODT Pattern value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted per dimm population and ranks type. - * @return FALSE - Table values cannot be extracted per dimm population and ranks type. - * - */ -BOOLEAN -MemPGetODTPattern ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT16 RankTypeInTable; - UINT16 RankTypeOfPopulatedDimm; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - DIMM_TYPE DimmType; - UINT8 PsoMaskOdtPat; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_3D_ODTPAT_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfODTPattern[i] != NULL) { - if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfODTPattern[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfODTPattern[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_3D_ODTPAT_ENTRY *) ((EntryOfTables->TblEntryOfODTPattern[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfODTPattern[i])->TableSize; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfODTPattern[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT table\n"); - return FALSE; - } - - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - CurrentChannel->PhyRODTCSHigh = TblPtr->RdODTCSHigh; - CurrentChannel->PhyRODTCSLow = TblPtr->RdODTCSLow; - CurrentChannel->PhyWODTCSHigh = TblPtr->WrODTCSHigh; - CurrentChannel->PhyWODTCSLow = TblPtr->WrODTCSLow; - - //WL ODT - CurrentChannel->PhyWLODT[0] = (UINT8) (CurrentChannel->PhyWODTCSLow & 0x0F); - CurrentChannel->PhyWLODT[1] = (UINT8) ((CurrentChannel->PhyWODTCSLow >> 16) & 0x0F); - CurrentChannel->PhyWLODT[2] = (UINT8) (CurrentChannel->PhyWODTCSHigh & 0x0F); - CurrentChannel->PhyWLODT[3] = (UINT8) ((CurrentChannel->PhyWODTCSHigh >> 16) & 0x0F); - - break; - } - TblPtr++; - } - - // - // If there is no entry, check if overriding value existed. If not, return FALSE - // - PsoMaskOdtPat = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODTPATTERN); - if ((PsoMaskOdtPat == 0) && (i == TableSize)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_ODT_PATTERN_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - - return TRUE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c deleted file mode 100644 index 662e99e7b3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c +++ /dev/null @@ -1,184 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprc10opspd.c - * - * A sub-engine which extracts RC10 operating speed value for RDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPRC10OPSPD_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetRC10OpSpd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts RC10 operating speed value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetRC10OpSpd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 TableSize; - UINT32 CurDDRrate; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 PsoMaskRC10OpSpeed; - PSCFG_OPSPD_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - if (CurrentChannel->RegDimmPresent == 0) { - return TRUE; - } - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. - while (EntryOfTables->TblEntryOfRC10OpSpeed[i] != NULL) { - LogicalCpuid = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.PackageType; - // - // Determine if this is the expected NB Type - // - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_OPSPD_ENTRY *) ((EntryOfTables->TblEntryOfRC10OpSpeed[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->TableSize; - break; - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfRC10OpSpeed[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - - for (i = 0; i < TableSize; i++) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - NBPtr->PsPtr->RC10OpSpd = TblPtr->OPSPD; - break; - } - TblPtr++; - } - - // - // If there is no entry, check if overriding value existed. If not, return FALSE. - // - PsoMaskRC10OpSpeed = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_RC10_OPSPEED); - if ((PsoMaskRC10OpSpeed == 0) && (i == TableSize)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_RC10_OP_SPEED_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - - return TRUE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c deleted file mode 100644 index ee6771057d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c +++ /dev/null @@ -1,236 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprc2ibt.c - * - * A sub-engine which extracts RC2[IBT] value for RDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPRC2IBT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetRC2IBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts RC2[IBT] value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted for all present dimms/ranks - * @return FALSE - Table values cannot be extracted for all present dimms/ranks - * - */ -BOOLEAN -MemPGetRC2IBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 DimmIndex; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 TgtDimmType; - UINT8 NumOfReg; - UINT8 PsoDimmMaskRc2Ibt; - UINT8 NoEntryDimmMask; - PSCFG_MR2IBT_ENTRY *TblPtr; - PSCFG_MR2IBT_ENTRY *OrgTblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - if (CurrentChannel->RegDimmPresent == 0) { - return TRUE; - } - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - NoEntryDimmMask = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. - while (EntryOfTables->TblEntryOfRC2IBT[i] != NULL) { - if (((EntryOfTables->TblEntryOfRC2IBT[i])->Header.NumOfDimm & NOD) != 0) { - LogicalCpuid = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.PackageType; - // - // Determine if this is the expected NB Type - // - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_MR2IBT_ENTRY *) ((EntryOfTables->TblEntryOfRC2IBT[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfRC2IBT[i])->TableSize; - break; - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfRC2IBT[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - OrgTblPtr = TblPtr; - for (DimmIndex = 0; DimmIndex < MAX_DIMMS_PER_CHANNEL; DimmIndex++) { - TblPtr = OrgTblPtr; - NumOfReg = NBPtr->PsPtr->NumOfReg[DimmIndex]; - if ((CurrentChannel->ChDimmValid & (UINT8) (1 << DimmIndex)) != 0) { - if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << DimmIndex)) != 0) { - TgtDimmType = DIMM_QR; - } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << DimmIndex)) != 0) { - TgtDimmType = DIMM_DR; - } else { - TgtDimmType = DIMM_SR; - } - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - if ((TblPtr->Dimm & TgtDimmType) != 0) { - // If TblPtr->NumOfReg == 0x0F, that means the condition will be TRUE regardless of NumRegisters in DIMM - if ((TblPtr->NumOfReg == 0xF) || (TblPtr->NumOfReg == NumOfReg)) { - CurrentChannel->CtrlWrd02[DimmIndex] = (UINT8) ((TblPtr->IBT & 0x1) << 2); - CurrentChannel->CtrlWrd08[DimmIndex] = (UINT8) ((TblPtr->IBT & 0xE) >> 1); - break; - } - } - } - } - } - } - TblPtr++; - } - - if (i == TableSize) { - NoEntryDimmMask |= (UINT8) 1 << DimmIndex; - } - } - } - - // - // If there are no entries for certain Dimm(s), check if overriding value existed for them. If not, return FALSE. - // - PsoDimmMaskRc2Ibt = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_RC2_IBT); - if (NoEntryDimmMask != 0) { - if ((NoEntryDimmMask & PsoDimmMaskRc2Ibt) != NoEntryDimmMask) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_RC2_IBT_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - } - - return TRUE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c deleted file mode 100644 index 73bb81796b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c +++ /dev/null @@ -1,270 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprtt.c - * - * A sub-engine which extracts RttNom and RttWr (Dram Term and Dynamic Dram Term) value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MPRTT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define _DONT_CARE 0xFF - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetRttNomWr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts RttNom and RttWr value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted for all present dimms/ranks - * @return FALSE - Table values cannot be extracted for all present dimms/ranks - * - */ -BOOLEAN -MemPGetRttNomWr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 TgtDimmType; - UINT8 TgtRank; - UINT8 Chipsel; - UINT8 PsoCsMaskRtt; - UINT16 PsoCsMaskRtt16; - UINT8 NoEntryCsMask; - PSCFG_RTT_ENTRY *TblPtr; - PSCFG_RTT_ENTRY *OrgTblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - PsoCsMaskRtt = 0; - NoEntryCsMask = 0; - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfDramTerm[i] != NULL) { - if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfDramTerm[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfDramTerm[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_RTT_ENTRY *) ((EntryOfTables->TblEntryOfDramTerm[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfDramTerm[i])->TableSize; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfDramTerm[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RTT table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - OrgTblPtr = TblPtr; - for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel++) { - TblPtr = OrgTblPtr; - if ((NBPtr->DCTPtr->Timings.CsPresent & (UINT16) (1 << Chipsel)) != 0) { - if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) { - TgtDimmType = DIMM_QR; - TgtRank = (UINT8) ((Chipsel < 4) ? 1 << (Chipsel & 1) : 4 << (Chipsel & 1)); - } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) { - TgtDimmType = DIMM_DR; - TgtRank = (UINT8) 1 << (Chipsel & 1); - } else { - TgtDimmType = DIMM_SR; - TgtRank = (UINT8) 1 << (Chipsel & 1); - } - - if (DimmType == LRDIMM_TYPE) { - TgtDimmType = _DONT_CARE; - TgtRank = _DONT_CARE; - } - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - if (((TblPtr->Dimm & TgtDimmType) != 0) || (TgtDimmType == _DONT_CARE)) { - if (((TblPtr->Rank & TgtRank) != 0) || (TgtRank == _DONT_CARE)) { - NBPtr->PsPtr->RttNom[Chipsel] = (UINT8) TblPtr->RttNom; - NBPtr->PsPtr->RttWr[Chipsel] = (UINT8) TblPtr->RttWr; - break; - } - } - } - } - } - } - TblPtr++; - } - // Record which Cs(s) have no entries. Later on, we will check if there are overriding values for them. - if ((i == TableSize) && (NBPtr->SharedPtr->VoltageMap == VDDIO_DETERMINED)) { - NoEntryCsMask |= (UINT8) 1 << Chipsel; - } - } - } - - PsoCsMaskRtt16 = MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODT_RTTNOM); - PsoCsMaskRtt16 &= MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODT_RTTWR); - // - // Check to see if invalid entry exist ? - // - if ((PsoCsMaskRtt16 & INVALID_CONFIG_FLAG) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nInvalid entry is found\n\n"); - return FALSE; - } - - // - // If there are no entries for certain Cs(s), we need to check if overriding values (both RttNom and RttWr) existed for them. - // Otherwise, return FALSE. - // - PsoCsMaskRtt = (UINT8) PsoCsMaskRtt16; - if (NoEntryCsMask != 0) { - if ((PsoCsMaskRtt & NoEntryCsMask) != NoEntryCsMask) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo Rtt entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_RTT_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - } - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c deleted file mode 100644 index 5d762a9ce6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c +++ /dev/null @@ -1,220 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mps2d.c - * - * A sub-engine determine which configs should use training. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 45233 $ @e \$Date: 2011-01-13 21:58:29 -0600 (Thu, 13 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MPS___FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetS__ ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which determine if training should be run - * from a input table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted per dimm population and ranks type. - * @return FALSE - Table values cannot be extracted per dimm population and ranks type. - * - */ -BOOLEAN -MemPGetS__ ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - BOOLEAN FoundValue; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_S___ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - UINT16 P__TraingOveride; - - CurrentChannel = NBPtr->ChannelPtr; - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfS__[i] != NULL) { - if (((EntryOfTables->TblEntryOfS__[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfS__[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfS__[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfS__[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_S___ENTRY *) ((EntryOfTables->TblEntryOfS__[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfS__[i])->TableSize; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfS__[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo training Config table\n"); - return FALSE; - } - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - FoundValue = FALSE; - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - if (TblPtr->Enable__ == 1) { - FoundValue = TRUE; - break; - } - } - } - } - } - TblPtr++; - } - P__TraingOveride = MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV____TRAINING); - if (P__TraingOveride != 0) { - if (NBPtr->Override__Training) { - FoundValue = TRUE; - } else { - FoundValue = FALSE; - } - } - // - // If there is no entry, check if overriding training existed. If not, show no entry found. - // - if (FoundValue == FALSE || ((P__TraingOveride & INVALID_CONFIG_FLAG) != 0)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo training config entries\n"); - return FALSE; - } else { - return TRUE; - } -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c deleted file mode 100644 index b8cf2d9edc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c +++ /dev/null @@ -1,227 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpsao.c - * - * A sub-engine which extracts Slow access mode, Address timing and Output driver compensation value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MPSAO_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetSAO ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts Slow mode, Address timing and Output driver compensation value - * from a input table and store those value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted per dimm population and ranks type. - * @return FALSE - Table values cannot be extracted per dimm population and ranks type. - * - */ -BOOLEAN -MemPGetSAO ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - UINT8 PsoMaskSAO; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_SAO_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfSAO[i] != NULL) { - if (((EntryOfTables->TblEntryOfSAO[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfSAO[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfSAO[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfSAO[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_SAO_ENTRY *) ((EntryOfTables->TblEntryOfSAO[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfSAO[i])->TableSize; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfSAO[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowAccMode, AddrTmg and ODCCtrl table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - CurrentChannel->DctAddrTmg = TblPtr->AddTmgCtl; - CurrentChannel->DctOdcCtl = TblPtr->ODC; - CurrentChannel->SlowMode = (TblPtr->SlowMode == 1) ? TRUE : FALSE; - break; - } - } - } - } - TblPtr++; - } - - // - // If there is no entry, check if overriding values (SlowAccMode, AddrTmg and ODCCtrl) existed. If not, show no entry found. - // - PsoMaskSAO = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_SLOWACCMODE); - PsoMaskSAO &= (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODCCTRL); - PsoMaskSAO &= (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ADDRTMG); - if ((PsoMaskSAO == 0) && (i == TableSize)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowAccMode, AddrTmg and ODCCtrl entries\n"); - } else { - return TRUE; - } - - if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) { - return TRUE; - } - - PutEventLog (AGESA_ERROR, MEM_ERROR_SAO_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c deleted file mode 100644 index c5450f1e0c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c +++ /dev/null @@ -1,211 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpseeds.c - * - * A sub-engine extracts WL and HW RxEn seeds from PSCFG tables. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 45233 $ @e \$Date: 2011-01-13 21:58:29 -0600 (Thu, 13 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MPSEEDS_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetTrainingSeeds ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function extracts WL and HW RxEn seeds from PSCFG tables - * from a input table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return NBPtr->PsPtr->WLSeedVal - * @return NBPtr->PsPtr->HWRxENSeedVal - * - */ -BOOLEAN -MemPGetTrainingSeeds ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 Seedloop; - UINT8 CH; - PSC_TBL_ENTRY **TblEntryPtr; - PSCFG_SEED_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - TblEntryPtr = NULL; - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - CH = 1 << (CurrentChannel->ChannelID); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - // Get seed value of WL, then HW RxEn - for (Seedloop = 0; Seedloop < 2; Seedloop++) { - TblEntryPtr = (Seedloop == 0) ? EntryOfTables->TblEntryOfWLSeed : EntryOfTables->TblEntryOfHWRxENSeed; - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (TblEntryPtr[i] != NULL) { - if (((TblEntryPtr[i])->Header.DimmType & DimmType) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (TblEntryPtr[i])->Header.LogicalCpuid; - PackageType = (TblEntryPtr[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_SEED_ENTRY *) ((TblEntryPtr[i])->TBLPtr); - TableSize = (TblEntryPtr[i])->TableSize; - break; - } - } - i++; - } - - // Check whether no table entry is found. - if (TblEntryPtr[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s training seeds Config table\n", (Seedloop == 0) ? "WL" : "HW RxEn"); - return FALSE; - } - - for (i = 0; i < TableSize; i++) { - if ((TblPtr->DimmPerCh & NOD) != 0) { - if ((TblPtr->Channel & CH) != 0) { - if (Seedloop == 0) { - NBPtr->PsPtr->WLSeedVal = (UINT8) TblPtr->SeedVal; - } else { - NBPtr->PsPtr->HWRxENSeedVal = TblPtr->SeedVal; - } - break; - } - } - TblPtr++; - } - - if (i == TableSize) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s seed entries\n\n", (Seedloop == 0) ? "WL" : "HW RxEn"); - PutEventLog (AGESA_ERROR, MEM_ERROR_TRAINING_SEED_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - } - - return TRUE; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/Makefile.inc deleted file mode 100644 index e2af37d663..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -libagesa-y += mt3.c -libagesa-y += mtlrdimm3.c -libagesa-y += mtot3.c -libagesa-y += mtrci3.c -libagesa-y += mtsdi3.c -libagesa-y += mtspd3.c -libagesa-y += mttecc3.c -libagesa-y += mttwl3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.c deleted file mode 100644 index ffe6b3e37b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.c +++ /dev/null @@ -1,236 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mt3.c - * - * Common Technology functions for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mt3.h" -#include "mtspd3.h" -#include "mtot3.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -/* features */ -#define FILECODE PROC_MEM_TECH_DDR3_MT3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This function Constructs the technology block - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -BOOLEAN -MemConstructTechBlock3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - TECHNOLOGY_TYPE *TechTypePtr; - UINT8 Dct; - UINT8 Channel; - UINT8 i; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - UINT8 DimmSlots; - - - TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0, 0, NULL, NULL); - if (TechTypePtr != NULL) { - // Ensure the platform override value is valid - ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY)); - if (*TechTypePtr != DDR3_TECHNOLOGY) { - return FALSE; - } - } - - TechPtr->NBPtr = NBPtr; - TechPtr->RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - - TechPtr->SendAllMRCmds = MemTSendAllMRCmds3; - TechPtr->FreqChgCtrlWrd = FreqChgCtrlWrd3; - TechPtr->SetDramMode = MemTSetDramMode3; - TechPtr->DimmPresence = MemTDIMMPresence3; - TechPtr->SpdCalcWidth = MemTSPDCalcWidth3; - TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed3; - TechPtr->AutoCycTiming = MemTAutoCycTiming3; - TechPtr->SpdSetBanks = MemTSPDSetBanks3; - TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs; - TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr3; - TechPtr->AdjustTwrwr = MemTAdjustTwrwr3; - TechPtr->AdjustTwrrd = MemTAdjustTwrrd3; - TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer3; - TechPtr->GetLD = MemTGetLD3; - TechPtr->MaxFilterDly = 0; - - // - // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM. - // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples). - // - // DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array - // (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop - // on this array only) - // 2 DIMMS PER CHANNEL - // - // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] - // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1] - // DimmSpdPtr[2]------->NULL - // DimmSpdPtr[3]------->NULL - // - // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] - // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1] - // | DimmSpdPtr[2]------->NULL - // +----DimmSpdPtr[3] - // - // Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0] - // Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1] - // +-- | ---DimmSpdPtr[2] - // +----DimmSpdPtr[3] - // - // 3 DIMMS PER CHANNEL - // - // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] - // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1] - // Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2] - // DimmSpdPtr[3]------->NULL - // - // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0] - // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1] - // Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2] - // +----DimmSpdPtr[3] - // - // - // FOR LRDIMMS - // - // This code will assign SPD pointers on the basis of Physical ranks, even though - // an LRDIMM may only use one or two logical ranks, that determination will have to - // be made from downstream code. An LRDIMM with greater than 2 Physical ranks will have - // its DimmSpdPtr[] mapped as if it were a QR in the above diagrams. - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - ChannelPtr = NBPtr->ChannelPtr; - ChannelPtr->TechType = DDR3_TECHNOLOGY; - ChannelPtr->MCTPtr = MCTPtr; - ChannelPtr->DCTPtr = DCTPtr; - - DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, - MCTPtr->SocketId, - NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel) - ); - // - // Initialize the SPD pointers for each Dimm - // - for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) { - ChannelPtr->DimmSpdPtr[i] = NULL; - } - for (i = 0 ; i < DimmSlots; i++) { - ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]); - if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) { - if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) { - if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) { - ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]); - } - } - } - } - } - } - // Initialize Common technology functions - MemTCommonTechInit (TechPtr); - - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.h deleted file mode 100644 index de65e33315..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.h +++ /dev/null @@ -1,133 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mt3.h - * - * Common Technology - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MT3_H_ -#define _MT3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemConstructTechBlock3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT MEM_NB_BLOCK *NBPtr - ); -BOOLEAN -MemTSetDramMode3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -MemTDIMMPresence3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -MemTSPDCalcWidth3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -MemTSPDGetTargetSpeed3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -MemTAutoCycTiming3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -MemTSPDSetBanks3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -VOID -MemTGetCSIntLvAddr3 ( - IN UINT8 BankEnc, - OUT UINT8 *LowBit, - OUT UINT8 *HiBit - ); - -VOID -MemTSendAllMRCmds3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel - ); - -VOID -FreqChgCtrlWrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - - -BOOLEAN -MemTGetDimmSpdBuffer3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 **SpdBuffer, - IN UINT8 Dimm - ); -#endif /* _MT3_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c deleted file mode 100644 index 3ae45e6271..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c +++ /dev/null @@ -1,1448 +0,0 @@ -/** - * @file - * - * mtlrdimm3.c - * - * Technology initialization and control workd support for DDR3 LRDIMMS - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mt3.h" -#include "mtspd3.h" -#include "mtrci3.h" -#include "mtsdi3.h" -#include "mtlrdimm3.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemTSendMBCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Fn, - IN UINT8 Rcw, - IN UINT8 Value - ); - -VOID -STATIC -MemTSendExtMBCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT16 Addr, - IN UINT16 Data, - IN UINT8 Len - ); - -UINT8 -STATIC -MemTGetSpecialMBCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Fn, - IN UINT8 Rc - ); - -BOOLEAN -STATIC -MemTLrDimmControlRegInit3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -STATIC -MemTLrDimmFreqChgCtrlWrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -STATIC -MemTWLPrepareLrdimm3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *Wl - ); - -BOOLEAN -STATIC -MemTSendAllMRCmdsLR3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *CsPtr - ); - -VOID -STATIC -MemTEMRS1Lr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel, - IN UINT8 PhyRank - ); - -VOID -STATIC -MemTEMRS2Lr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel - ); - - -BOOLEAN -STATIC -MemTLrdimmRankMultiplication ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *DimmID - ); - -BOOLEAN -STATIC -MemTLrdimmBuf2DramTrain3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -STATIC -MemTLrdimmSyncTrainedDlys ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ); - -BOOLEAN -STATIC -MemTLrdimmPresence ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *DimmID - ); - -UINT32 -STATIC -MemTLrDimmGetBufferID ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm - ); - -VOID -STATIC -MemTLrdimmInitHook ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN LRDIMM_HOOK_ENTRYPOINT Entrypoint, - IN UINT8 Dimm, - IN OUT VOID *OptParam - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes LRDIMM functions. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -BOOLEAN -MemTLrdimmConstructor3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] = MemTSendAllMRCmdsLR3; - TechPtr->TechnologySpecificHook[LrdimmControlRegInit] = MemTLrDimmControlRegInit3; - TechPtr->TechnologySpecificHook[LrdimmFreqChgCtrlWrd] = MemTLrDimmFreqChgCtrlWrd3; - TechPtr->TechnologySpecificHook[WlTrainingPrepareLrdimm] = MemTWLPrepareLrdimm3; - TechPtr->TechnologySpecificHook[LrdimmRankMultiplication] = MemTLrdimmRankMultiplication; - TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] = MemTLrdimmBuf2DramTrain3; - TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] = MemTLrdimmSyncTrainedDlys; - TechPtr->TechnologySpecificHook[LrdimmPresence] = MemTLrdimmPresence; - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends a Control word command to an LRDIMM Memory Buffer - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Fn - control word function - * @param[in] Rcw - control word number - * @param[in] Value - value to send - * - */ - -VOID -STATIC -MemTSendMBCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Fn, - IN UINT8 Rcw, - IN UINT8 Value - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - ASSERT (Rcw != RCW_FN_SELECT); // RC7 can only be used for function select - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tF%dRC%d = %x\n", Fn, Rcw, Value); - // - // Select the MB Function by sending the Fn number - // to the Function Select Control Word - // - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, RCW_FN_SELECT, Fn); - // - // Send the value to the control word - // - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, Rcw, Value); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends a an Extended Control word command to an LRDIMM Memory Buffer - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Addr - Extended Control Word Address - * Addr[15:12] Extended Control Workd Function Select - * Addr[11:0] Extended Control Word CSR Address - * @param[in] Data - value to send - * @param[in] Len - Length of data. 1 or 2 bytes - * - */ - -VOID -STATIC -MemTSendExtMBCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT16 Addr, - IN UINT16 Data, - IN UINT8 Len - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - ASSERT ((Len == 1) || (Len == 2)); - if (Len == 2 ) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tExtRC_x%04x = %04x\n", Addr, Data); - } else { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tExtRC_x%04x = %02x\n", Addr, (UINT8) (Data & 0xFF) ); - } - // - // Select the MB Function by sending the Fn number - // to the Function Select Control Word - // - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, RCW_FN_SELECT, 13); - // - // Send address via control words - // - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, 9, (UINT8) (Addr >> 12)); - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, 10, (UINT8) (Addr & 0xF)); - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, 11, (UINT8) ((Addr >> 4) & 0x0F)); - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, 12, (UINT8) ((Addr >> 8) & 0x0F)); - // - // Send the Lower Byte of Data - // - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, 14, (UINT8) (Data & 0xF)); - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, 15, (UINT8) ((Data >> 4) & 0x0F)); - // - // Send the Upper Byte of Data - // - if (Len == 2) { - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, 10, (UINT8) ((Addr & 0xF) + 1)); - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, 14, (UINT8) ((Data >> 8) & 0xF)); - MemUWait10ns (800, NBPtr->MemPtr); - MemTSendCtlWord3 (TechPtr, 15, (UINT8) ((Data >> 12) & 0xF)); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets the value of special RCW - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dimm - Physical LR DIMM number - * @param[in] Fn - control word function - * @param[in] Rc - control word number - * - * @return Special RCW value - * - */ - -UINT8 -STATIC -MemTGetSpecialMBCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Fn, - IN UINT8 Rc - ) -{ - CONST UINT8 F0RC13PhyRankTab[] = {3, 2, 0, 1, 0}; - UINT8 PhyRanks; - UINT8 LogRanks; - UINT8 DramCap; - UINT8 Value8; - UINT8 *SpdBufferPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); - - Value8 = 0; - switch (Fn) { - case 0: - switch (Rc) { - case 8: - // F0RC8 - Value8 = NBPtr->PsPtr->F0RC8; - break; - case 10: - // F0RC10 - // 2:0 OperatingSpeed: operating speed. BIOS: Table 88. - if (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY) { - Value8 = 0; - } else { - Value8 = (UINT8) (NBPtr->DCTPtr->Timings.Speed / 133) - 3; - } - break; - case 11: - // F0RC11 - // 3:2 ParityCalculation: partiy calculation. BIOS: Table. - // 1:0 OperatingVoltage: operating voltage. BIOS: IF(VDDIO == 1.5) THEN 00b ELSEIF (VDDIO == - // 1.35) THEN 01b ELSE 10b ENDIF. - DramCap = SpdBufferPtr[SPD_DENSITY] & 0xF; - if (NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] > 16) { - Value8 = 8; - } else { - Value8 = 4; - } - Value8 |= CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage); - break; - case 13: - // F0RC13 - // 3:2 NumLogicalRanks: partiy calculation. BIOS: Table 90. - // 1:0 NumPhysicalRanks: operating voltage. BIOS: Table 89. - LogRanks = NBPtr->ChannelPtr->LrDimmLogicalRanks[Dimm] >> 1; - PhyRanks = F0RC13PhyRankTab[(SpdBufferPtr[SPD_RANKS] >> 3) & 7]; - Value8 = (LogRanks << 2) | PhyRanks; - break; - case 14: - // F0RC14 - // 3 DramBusWidth: DRAM bus width. BIOS: IF (DeviceWidth==0) THEN 0 ELSE 1 ENDIF. - // 2 MRSCommandControl: MRS command control. BIOS: IF (F0RC15[RankMultiplicationControl] - // > 0) THEN 1 ELSE 0 ENDIF. - // 1 RefreshPrechargeCommandControl: refresh and precharge command control. BIOS: IF - // (F0RC15[RankMultiplicationControl] > 0) THEN D18F2xA8_dct[1:0][LrDimmEnhRefEn] ELSE 0 ENDIF. - // 0 AddressMirror: address mirror. BIOS: RankMap. See D18F2x[5C:40]_dct[1:0][OnDimmMirror]. - if ((SpdBufferPtr[SPD_DEV_WIDTH] & 7) != 0) { - Value8 |= 8; - } - if (NBPtr->ChannelPtr->LrDimmRankMult[Dimm] > 1) { - Value8 |= 4; - if (NBPtr->GetBitField (NBPtr, BFLrDimmEnhRefEn) == 1) { - Value8 |= 2; - } - } - if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) { - Value8 |= 1; - } - break; - case 15: - // F0RC15 - // 3:0 RankMultiplicationControl: rank multiplication control. BIOS: Table 91. - DramCap = SpdBufferPtr[SPD_DENSITY] & 0xF; - ASSERT ((DramCap >= 2) && (DramCap <= 4)); // BKDG only lists 1Gb, 2Gb, and 4Gb - switch (NBPtr->ChannelPtr->LrDimmRankMult[Dimm]) { - case 1: - Value8 = 0; - break; - case 2: - Value8 = DramCap - 1; - break; - case 4: - Value8 = DramCap + 3; - break; - default: - ASSERT (FALSE); - } - break; - default: - ASSERT (FALSE); - } - break; - case 1: - switch (Rc) { - case 0: - // F1RC0 - Value8 = NBPtr->PsPtr->F1RC0; - Value8 |= (UINT8) NBPtr->GetBitField (NBPtr, BFCSTimingMux67) << 3; - break; - case 1: - // F1RC1 - Value8 = NBPtr->PsPtr->F1RC1; - break; - case 2: - // F1RC2 - Value8 = NBPtr->PsPtr->F1RC2; - break; - case 9: - // F1RC9 - if (NBPtr->GetBitField (NBPtr, BFLrDimmEnhRefEn) == 0) { - Value8 = 1; - } - break; - default: - ASSERT (FALSE); - } - break; - case 3: - switch (Rc) { - case 0: - // F3RC0 - // 3 TDQSControl: TDQS control. BIOS: 0. - // 2:0 RttNom: RttNom. BIOS: Table 57, Table 60 - Value8 = NBPtr->PsPtr->RttNom[Dimm << 1]; - break; - case 1: - // F3RC1 - // 3 Vref: Vref. BIOS: 0. - // 2:0 RttWr: RttWr. BIOS: Table 57, Table 60. - Value8 = NBPtr->PsPtr->RttWr[Dimm << 1]; - break; - case 6: - // F3RC6 - // IF (D18F2x90_dct[1:0][X4Dimm] == 0) THEN 1 ELSE 0 - if (NBPtr->GetBitField (NBPtr, BFX4Dimm) == 0) { - Value8 = 8; - } - break; - default: - ASSERT (FALSE); - } - break; - default: - ASSERT (FALSE); - } - - return Value8; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends LRDIMM Control Words to all LRDIMMS - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - */ - -BOOLEAN -STATIC -MemTLrDimmControlRegInit3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - CONST UINT8 RCWInitTable[] = { - // RCW, Mask, SPD - F0, RC0, 0x00, SPD_NONE, - F0, RC1, 0x00, SPD_NONE, - F0, RC2, 0x03, SPD_67, - F0, RC10, 0x00, SPECIAL_CASE, - F0, RC11, 0x00, SPECIAL_CASE, - - F1, RC8, 0x0F, SPD_69, - F1, RC11, 0xF0, SPD_69, - F1, RC12, 0x0F, SPD_70, - F1, RC13, 0xF0, SPD_70, - F1, RC14, 0x0F, SPD_71, - F1, RC15, 0xF0, SPD_71, - - WAIT_6US, 0, 0, 0, - - F0, RC3, 0xF0, SPD_67, - F0, RC4, 0x0F, SPD_68, - F0, RC5, 0xF0, SPD_68, - - F0, RC6, 0x00, SPD_NONE, - F0, RC8, 0x00, SPECIAL_CASE, - F0, RC9, 0x0C, SPD_NONE, - F0, RC13, 0x00, SPECIAL_CASE, - F0, RC14, 0x00, SPECIAL_CASE, - F0, RC15, 0x00, SPECIAL_CASE, - - F1, RC0, 0x00, SPECIAL_CASE, - F1, RC1, 0x00, SPECIAL_CASE, - F1, RC2, 0x00, SPECIAL_CASE, - F1, RC3, 0x00, SPD_NONE, - F1, RC9, 0x00, SPECIAL_CASE, - F1, RC10, 0x00, SPD_NONE, - - F2, RC0, 0x00, SPD_NONE, - F2, RC1, 0x00, SPD_NONE, - F2, RC2, 0x0F, SPD_NONE, - F2, RC3, 0x00, SPD_NONE, - - F3, RC0, 0x00, SPECIAL_CASE, - F3, RC1, 0x00, SPECIAL_CASE, - F3, RC2, 0x01, SPD_NONE, - F3, RC6, 0x00, SPECIAL_CASE - // - // F3 RC[8,9] are programmed in MDQ RC loop - // - // F[10:3] RC[11,10] are programmed in QxODT RC loop - // - // F[15,14] RC[15:0] are programmed in personality RC loop - }; - - UINT8 Dimm; - UINT16 i; - UINT16 DimmMask; - UINT8 Fn; - UINT8 Rc; - UINT8 Mask; - UINT8 Spd; - UINT8 *SpdBufferPtr; - UINT8 FreqDiffOffset; - UINT8 Value8; - UINT32 Temp32; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - DimmMask = (UINT16)1 << Dimm; - if ((NBPtr->ChannelPtr->LrDimmPresent & DimmMask) != 0) { - // - // Select the Target Chipselects - // - NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1)); - NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1)); - - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSending LRDIMM Control Words: Dimm %02x\n", Dimm); - - for (i = 0; i < sizeof (RCWInitTable) ; i += 4) { - Fn = RCWInitTable[i]; - Rc = RCWInitTable[i + 1]; - Mask = RCWInitTable[i + 2]; - Spd = RCWInitTable[i + 3]; - - if (Fn == WAIT_6US) { - MemUWait10ns (600, MemPtr); // wait 6us for TSTAB - } else { - if (Spd == SPD_NONE) { - Value8 = Mask; - } else if (Spd == SPECIAL_CASE) { - Value8 = MemTGetSpecialMBCtlWord3 (TechPtr, Dimm, Fn, Rc); - } else { - Value8 = (Mask > 0x0F) ? ((SpdBufferPtr[Spd] & Mask) >> 4) : (SpdBufferPtr[Spd] & Mask); - } - MemTSendMBCtlWord3 (TechPtr, Fn, Rc, Value8); - } - } - - FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2)); - // - // Send RCW to program MDQ termination and drive strength - // - for (Rc = 8; Rc <= 9; Rc++) { - Value8 = SpdBufferPtr[SPD_MDQ_800_1066 + FreqDiffOffset]; - Value8 = (Rc == 9) ? (Value8 >> 4) : Value8; - MemTSendMBCtlWord3 (TechPtr, 3, Rc, Value8 & 0x07); - } - // - // Send RCW to program QxODT - // - for (Fn = 3; Fn <= 10; Fn ++) { - for (Rc = 10; Rc <= 11; Rc++) { - Value8 = SpdBufferPtr[SPD_QXODT_800_1066 + FreqDiffOffset + ((Fn - 3) >> 1)]; - Value8 = (Rc == 11) ? (Value8 >> 4) : (Value8 & 0x0F); - Value8 = ((Fn & 1) == 0) ? (Value8 >> 2) : (Value8 & 0x03); - MemTSendMBCtlWord3 (TechPtr, Fn, Rc, Value8); - } - } - - MemTLrdimmInitHook (TechPtr, AFTER_TSTAB, Dimm, 0); - // - // Send Personality bytes from SPD - // - for (i = 0; i < 15; i ++) { - Value8 = SpdBufferPtr[SPD_PERSONALITY_BYTE + i]; - Fn = (UINT8) (14 + (i >> 3)); - Rc = (UINT8) ((i << 1) & 0x0F); - if ( i == 0) { - Value8 |= 0x01; - } else if ( i > 10) { - Rc += 2; - } - MemTSendMBCtlWord3 (TechPtr, Fn, Rc, (Value8 & 0x0F)); - if (i == 3) { - Fn++; - } else { - Rc++; - } - MemTSendMBCtlWord3 (TechPtr, Fn, Rc, (Value8 >> 4)); - } - // - // Send Extended Control Words to Buffer - // - // ExtRC_xAC - // - MemTSendExtMBCtlWord3 (TechPtr, 0x00AC, 0, 1); - // - // ExtRC_xB8-BF - // - Value8 = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset]; - for (i = 0x00B8; i < 0x00C0; i++) { - MemTSendExtMBCtlWord3 (TechPtr, i, Value8, 1); - if (i == 0xB9) { - // - // Phys ranks > 1, Rtt_nom = 0 - // - Value8 &= 0xE3; - } - } - // ExtRC_xC8 - Value8 = (UINT8) (NBPtr->MemNGetMR0CL (NBPtr) & 0x000000FF); - Value8 = ((Value8 & 0xE0) | ((Value8 & 0x04) << 1)); - Value8 |= 1<<2; // RBT - Value8 |= NBPtr->GetBitField (NBPtr, BFBurstCtrl); // BL - MemTSendExtMBCtlWord3 (TechPtr, 0x00C8 , Value8, 1); - // ExtRC_xC9 - // PPD - Value8 = (UINT8) (NBPtr->GetBitField (NBPtr, BFPchgPDModeSel) & 0x000000FF); - NBPtr->FamilySpecificHook[MR0_PPD] (NBPtr, &Value8); - IDS_OPTION_HOOK (IDS_MEM_MR0, &Value8, &TechPtr->NBPtr->MemPtr->StdHeader); - Value8 <<= 4; - // WR - Temp32 = NBPtr->MemNGetMR0WR (NBPtr); - Value8 |= (UINT8) ((Temp32 >> 8) & 0x000000FF); - MemTSendExtMBCtlWord3 (TechPtr, 0x00C9 , Value8, 1); - // ExtRC_xCA - MemTSendExtMBCtlWord3 (TechPtr, 0x00CA , 0, 1); - // ExtRC_xCB - MemTSendExtMBCtlWord3 (TechPtr, 0x00CB , 0, 1); - // ExtRC_xCC - // CWL - Value8 = (UINT8) (NBPtr->MemNGetMR2CWL (NBPtr) & 0x000000FF); - // SRT|ASR - Value8 |= 0x40; - MemTSendExtMBCtlWord3 (TechPtr, 0x00CC , Value8, 1); - // ExtRC_xCD - MemTSendExtMBCtlWord3 (TechPtr, 0x00CD , 0, 1); - // ExtRC_xCE - MemTSendExtMBCtlWord3 (TechPtr, 0x00CE , 0, 1); - // ExtRC_xCF - MemTSendExtMBCtlWord3 (TechPtr, 0x00CF , 0, 1); - } - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends LRDIMM Control Words to all LRDIMMS - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return FALSE - The current channel does not have LRDIMM populated - * TRUE - The current channel has LRDIMM populated - */ -BOOLEAN -STATIC -MemTLrDimmFreqChgCtrlWrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Dct; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - MemTLrDimmControlRegInit3 (TechPtr, NULL); - } - } - return TRUE; - } - return FALSE; -} - -/*----------------------------------------------------------------------------- - * - * - * This function prepares LRDIMMs for WL training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *Wl - Indicates if WL mode should be enabled - * - * @return TRUE - LRDIMMs present - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemTWLPrepareLrdimm3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *Wl - ) -{ - UINT8 Dimm; - UINT8 Value8; - UINT16 MrsAddress; - MEM_NB_BLOCK *NBPtr; - NBPtr = TechPtr->NBPtr; - MrsAddress = 0; - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if (*(BOOLEAN *) Wl == TRUE) { - // Program WrLvOdt - NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[Dimm]); - } - if ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << Dimm)) != 0) { - if (Dimm == TechPtr->TargetDIMM) { - if (*(BOOLEAN *) Wl == TRUE) { - // - // Select the Target Chipselects - // - NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1)); - NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1)); - // Program F0RC12 to 1h - MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0x01); - if (NBPtr->ChannelPtr->Dimms >= 2) { - // For two or more LRDIMMs per channel program the buffer RttNom to the - // corresponding specifed RttWr termination - Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, Dimm << 2); - } else { - // Program RttNom as normal - Value8 = NBPtr->MemNGetDramTerm (NBPtr, Dimm << 2); - } - if ((Value8 & ((UINT8) 1 << 2)) != 0) { - MrsAddress |= ((UINT16) 1 << 9); - } - if ((Value8 & ((UINT8) 1 << 1)) != 0) { - MrsAddress |= ((UINT16) 1 << 6); - } - if ((Value8 & ((UINT8) 1 << 0)) != 0) { - MrsAddress |= ((UINT16) 1 << 2); - } - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); - } else { - // Program F0RC12 to 0h - MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0x00); - } - } - } - } - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This send all MR commands to all physical ranks of an LRDIMM - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] *CsPtr - Target Chip Select - * - * @return FALSE - The current channel does not have LRDIMM populated - * TRUE - The current channel has LRDIMM populated - */ -BOOLEAN -STATIC -MemTSendAllMRCmdsLR3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *CsPtr - ) -{ - UINT8 *SpdBufferPtr; - UINT8 Rank; - UINT8 PhyRank; - UINT8 ChipSel; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - ChipSel = *((UINT8 *) CsPtr); - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - // - // For LRDIMMs, MR0, MR2, and MR3 can be broadcast to any physicall ranks behind - // each logical rank(CS) by setting MRSAddress[13]. MR1[Rtt_Nom] needs to be programmed - // differently per physical rank, so it must target a physical rank using MrsAddress[17:14]. - // The actual bits used to index the physical rank are determined by the DRAM Capacity. - // - // This function will be called once for each CS where CSPresent is set, so each time - // it only needs to handle the Physical ranks behind each CS. If a Dimm is not using some - // CS due to Rank Mux, those CSPresent bits will have been already cleared. - // - - // - // Select target chip select - // - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - // - // 13.Send EMRS(2) - // - MemTEMRS2Lr3 (TechPtr, ChipSel); - NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast - NBPtr->SendMrsCmd (NBPtr); - // - // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b - // - MemTEMRS33 (TechPtr); - NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast - NBPtr->SendMrsCmd (NBPtr); - // - // 15.Send EMRS(1). Send to each physical rank. - // - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1); - // - // Determine first physical rank relative to the LRDIMM for this CS - // - PhyRank = ((((ChipSel & NBPtr->ChannelPtr->LrDimmLogicalRanks[ChipSel >> 1]) >> 1) & 2) | (ChipSel & 1)); - for (Rank = 0; Rank < NBPtr->ChannelPtr->LrDimmRankMult[ChipSel >> 1]; Rank++) { - MemTEMRS1Lr3 (TechPtr, ChipSel, PhyRank); - // - // Set Address bit 14, 15, 16, or 17 to select physical rank, relative to the CS, according to the device size - // - NBPtr->SetBitField (NBPtr, BFMrsAddressHi, Rank << ((SpdBufferPtr[SPD_DENSITY] & 0xF) - 1 ) ); - NBPtr->SendMrsCmd (NBPtr); - // - // Index to the next physical rank - // - PhyRank = PhyRank + NBPtr->ChannelPtr->LrDimmLogicalRanks[ChipSel >> 1]; - } - // - // 16.Send MRS with MrsAddress[8]=1(reset the DLL) - // - MemTMRS3 (TechPtr); - NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast - NBPtr->SendMrsCmd (NBPtr); - // - // If LRDIMM, return TRUE to skip sending regular MR commands. - // - return TRUE; - } - // - // If not LRDIMM, send regular MR commands. - // - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS1 value for an LRDIMM - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ChipSel - Chip select number - * @param[in] PhyRank - Physical rank number - */ - -VOID -STATIC -MemTEMRS1Lr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel, - IN UINT8 PhyRank - ) -{ - UINT16 MrsAddress; - UINT8 Value8; - UINT8 *SpdBufferPtr; - UINT8 FreqDiffOffset; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1); - FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2)); - - // BA2=0,BA1=0,BA0=1 - NBPtr->SetBitField (NBPtr, BFMrsBank, 1); - - MrsAddress = 0; - - // program MrsAddress[5,1]=output driver impedance control (DIC): 01b - MrsAddress |= ((UINT16) 1 << 1); - - // program MrsAddress[5,1]=output driver impedance control (DIC): - // DIC is read from SPD byte 77, 83, or 89 depending on DDR speed - Value8 = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] & 3; - if ((Value8 & ((UINT8) 1 << 1)) != 0) { - MrsAddress |= ((UINT16) 1 << 5); - } - if ((Value8 & ((UINT8) 1 << 0)) != 0) { - MrsAddress |= ((UINT16) 1 << 1); - } - - // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT): - // RttNom is read from SPD byte 77, 83, or 89 depending on DDR speed - if (PhyRank <= 1) { - Value8 = (SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] >> 2) & 7; - if ((Value8 & ((UINT8) 1 << 2)) != 0) { - MrsAddress |= ((UINT16) 1 << 9); - } - if ((Value8 & ((UINT8) 1 << 1)) != 0) { - MrsAddress |= ((UINT16) 1 << 6); - } - if ((Value8 & ((UINT8) 1 << 0)) != 0) { - MrsAddress |= ((UINT16) 1 << 2); - } - } - - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS2 value for an LRDIMM - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ChipSel - Chip select number - */ - -VOID -STATIC -MemTEMRS2Lr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel - ) -{ - UINT8 RttWr; - UINT8 *SpdBufferPtr; - UINT8 FreqDiffOffset; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - // Save default RttWr - RttWr = NBPtr->PsPtr->RttWr[ChipSel]; - - // Override RttWr with the value read from SPD byte 77, 83, or 89 depending on DDR speed - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1); - FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2)); - NBPtr->PsPtr->RttWr[ChipSel] = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] >> 6; - - // Call EMRS2 calculation - MemTEMRS23 (TechPtr); - - // Restore RttWr - NBPtr->PsPtr->RttWr[ChipSel] = RttWr; -} - -/*----------------------------------------------------------------------------- - * - * - * This function to determine the Rank Multiplication to use for an LRDIMM - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *DimmID - Dimm ID - * - * @return TRUE - LRDIMM Support is installed and LRDIMMs are present - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemTLrdimmRankMultiplication ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *DimmID - ) -{ - BOOLEAN RetVal; - UINT8 *SpdBufferPtr; - UINT8 Dimm; - UINT8 NumDimmslots; - UINT8 DramCapacity; - UINT8 Ranks; - UINT8 Rows; - UINT8 RankMult; - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (TechPtr != NULL); - ASSERT (DimmID != NULL); - - Dimm = *(UINT8*)DimmID; - ASSERT (Dimm < MAX_DIMMS_PER_CHANNEL); - - NBPtr = TechPtr->NBPtr; - ChannelPtr = NBPtr->ChannelPtr; - RetVal = FALSE; - RankMult = 0; - - if (!MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm)) { - ASSERT (FALSE); - } - - NumDimmslots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, - NBPtr->MCTPtr->SocketId, - ChannelPtr->ChannelID); - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - RetVal = TRUE; - // - // Determine LRDIMM Rank Multiplication - // - Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1; - if (Ranks == 5) { - Ranks = 8; - } - DramCapacity = (SpdBufferPtr[SPD_DENSITY] & 0x0F); - Rows = 12 + ((SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7); - - if (Ranks < 4) { - RankMult = 1; - } else if (Ranks == 4) { - RankMult = (NumDimmslots < 3) ? 1 : 2; - } else if (Ranks == 8) { - RankMult = ((NumDimmslots < 3) && (DramCapacity < 4)) ? 2 : 4; - } - // - // Save Rank Information - // - ChannelPtr->LrDimmRankMult[Dimm] = RankMult; - ChannelPtr->LrDimmLogicalRanks[Dimm] = Ranks / RankMult; - NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] = Rows + (RankMult >> 1); - // - // Program RankDef - // - NBPtr->SetBitField (NBPtr, BFRankDef0 + Dimm, (RankMult == 4) ? 3 : RankMult); - // - // If LrdimmRowAddressBits > 16, then we must be using some CS signals for rank - // multiplication. If this is the case, then we want to clear the CSPresent bits - // that correspond to those chipselects. - // If there are 3 DIMMs per channel, then it will always be CS67, if there are - // 2DPCH, then DIMM0 will use CS45, and DIMM1 will use CS67. - // - if ((ChannelPtr->LrDimmLogicalRanks[Dimm] < 4) && (Dimm >= NumDimmslots)) { - NBPtr->DCTPtr->Timings.CsPresent &= ~(0x3 << (Dimm << 1)); - ChannelPtr->LrDimmRankMult[Dimm] = 0; - ChannelPtr->LrDimmLogicalRanks[Dimm] = 0; - NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] = 0; - } else { - IDS_HDT_CONSOLE_DEBUG_CODE ( - if (Dimm < NumDimmslots) { - IDS_HDT_CONSOLE (MEM_FLOW,"\tDimm %d: Log. Ranks:%d Phys. Ranks:%d RowAddrBits:%d RankMult:%d\n", - Dimm, - ChannelPtr->LrDimmLogicalRanks[Dimm], - ChannelPtr->LrdimmPhysicalRanks[Dimm], - NBPtr->PsPtr->LrdimmRowAddrBits[Dimm], - RankMult - ); - } - ); - } - } - return RetVal; -} - -/* ----------------------------------------------------------------------------- - * - * This function performs buffer to DRAM training for LRDIMMs - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - */ - -BOOLEAN -STATIC -MemTLrdimmBuf2DramTrain3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - UINT8 Dct; - UINT8 Dimm; - UINT8 ChipSel; - UINT16 DimmMask; - UINT8 i; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nStart Buffer to DRAM training\n"); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - // - // ODM needs to be set after Dram Init - // - if (NBPtr->StartupSpeed == NBPtr->DCTPtr->Timings.Speed) { - for (ChipSel = 1; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) { - if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) { - NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + ChipSel, ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + ChipSel)) | ((UINT32)1 << BFOnDimmMirror ))); - } - } - } - } - // - // Buffer to DRAM training - // - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - DimmMask = (UINT16)1 << Dimm; - if ((NBPtr->ChannelPtr->LrDimmPresent & DimmMask) != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\nDimm %d\n", Dimm); - // - // Select the Target Chipselects - // - NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1)); - NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1)); - - NBPtr->SetBitField (NBPtr, BFLrDimmErrOutMonEn, 1); - MemTSendMBCtlWord3 (TechPtr, F2, RC3, 8); - // Send F0RC12 with data = 0010b. - MemTSendMBCtlWord3 (TechPtr, F0, RC12, 2); - // - // Wait until D18F2xA0_dct[1:0][RcvParErr]=0 or tCAL * the number of physical ranks expires. - // - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tWaiting %d ms...\n", 10 * NBPtr->ChannelPtr->LrdimmPhysicalRanks[Dimm]); - for (i = 0; i < (NBPtr->ChannelPtr->LrdimmPhysicalRanks[Dimm] * 10); i++) { - MemUWait10ns (1000000, MemPtr); - // - // @todo: Provide option for polling RcvParErr to optimize DRAM bus timing. - // - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tRcvParErr = %02x\n", NBPtr->GetBitField (NBPtr, BFRcvParErr)); - NBPtr->SetBitField (NBPtr, BFLrDimmErrOutMonEn, 0); - MemTSendMBCtlWord3 (TechPtr, F2, RC3, 0); - // Configure for normal operation: Send F0RC12 with data = 0000b. - MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0); - } - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd Buffer to DRAM training\n"); - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function copies trained delays of the first rank of a QR LRDIMM to the third rank - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - */ - -BOOLEAN -STATIC -MemTLrdimmSyncTrainedDlys ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 i; - UINT8 Dimm; - UINT8 Dct; - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - UINT16 WrDqsDly; - UINT16 RcvEnDly; - UINT16 RdDqsDly; - UINT16 WrDatDly; - UINT8 RdDqs__Dly; - NBPtr = TechPtr->NBPtr; - - if (NBPtr->MCTPtr->Status[SbLrdimms]) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tSync LRDIMM Delays to remaining ranks.\n"); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < 2; Dimm++) { - if (ChannelPtr->LrDimmLogicalRanks[Dimm] > 2) { - // If logical QR LRDIMM, copy trained delays from first rank to third rank - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDimm %d -> Dimm %d\n",Dimm, Dimm + 2); - for (i = 0; i < TechPtr->DlyTableWidth (); i++) { - WrDqsDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + i]; - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i), WrDqsDly); - ChannelPtr->WrDqsDlys[(Dimm + 2) * TechPtr->DlyTableWidth () + i] = (UINT8)WrDqsDly; - - RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + i]; - NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm + 2, i), RcvEnDly); - ChannelPtr->RcvEnDlys[(Dimm + 2) * TechPtr->DlyTableWidth () + i] = RcvEnDly; - - RdDqsDly = ChannelPtr->RdDqsDlys[Dimm * TechPtr->DlyTableWidth () + i]; - NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i), RdDqsDly); - ChannelPtr->RdDqsDlys[(Dimm + 2) * TechPtr->DlyTableWidth () + i] = (UINT8)RdDqsDly; - - WrDatDly = ChannelPtr->WrDatDlys[Dimm * TechPtr->DlyTableWidth () + i]; - NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm + 2, i), WrDatDly); - ChannelPtr->WrDatDlys[(Dimm + 2) * TechPtr->DlyTableWidth () + i] = (UINT8)WrDatDly; - } - if ((ChannelPtr->DimmNibbleAccess & (1 << Dimm)) != 0) { - // - // If 2D x4 (Not Currently POR for LRDIMMs) - // - for (i = 0; i < MAX_NUMBER_LANES; i++) { - if (ChannelPtr->LrDimmLogicalRanks[Dimm] > 2) { - // If logical QR LRDIMM, copy trained delays from first rank to third rank - RdDqs__Dly = ChannelPtr->RdDqs__Dlys[Dimm * MAX_NUMBER_LANES + i]; - NBPtr->SetTrainDly (NBPtr, AccessRdDqs__Dly, DIMM_NBBL_ACCESS (Dimm + 2, i), - ChannelPtr->RdDqs__Dlys[Dimm * MAX_NUMBER_LANES + i]); - ChannelPtr->RdDqs__Dlys[(Dimm + 2) * MAX_NUMBER_LANES + i] = (UINT8)RdDqs__Dly; - } - } - } - } - } - } - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function performs LRDIMM specific tasks during Dimm Presence detection - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *DimmID - Dimm ID - * - * @return TRUE - * - */ - -BOOLEAN -STATIC -MemTLrdimmPresence ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *DimmID - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT32 BufferID; - UINT8 Dimm; - NBPtr = TechPtr->NBPtr; - Dimm = *(UINT8*) DimmID; - - BufferID = MemTLrDimmGetBufferID (TechPtr, Dimm); - if ((BufferID == 0x0020B304) || (BufferID == 0x0020B380)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tDimm %d: Unsupported LRDIMM Buffer Revision\n", Dimm); - PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_LRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, Dimm, &NBPtr->MemPtr->StdHeader); - NBPtr->DCTPtr->Timings.CsTestFail |= (UINT16)0x3 << (Dimm << 1); - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns LRDIMM Buffer ID Info from the SPD - * - * - * @param[in,out] *TechPtr - Pointer to the Technology Block - * @param[in] Dimm - Dimm number - * - * @return Buffer ID Information - * - */ - -UINT32 -STATIC -MemTLrDimmGetBufferID ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm - ) -{ - UINT8 *SpdBufferPtr; - UINT32 BufferID; - - BufferID = 0; - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); - BufferID = (SpdBufferPtr[64] << 16) | (SpdBufferPtr[66] << 8) | (SpdBufferPtr[65]); - return BufferID; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function implements special case Initialization hooks for LRDIMMs - * - * @param[in] TechPtr - Tech Block Pointer - * @param[in] Entrypoint - Entrypoint to indicate when this hook is called - * @param[in] Dimm - Dimm being configured when hook is called - * @param[in] OptParam - Not Used - */ - -VOID -STATIC -MemTLrdimmInitHook ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN LRDIMM_HOOK_ENTRYPOINT Entrypoint, - IN UINT8 Dimm, - IN OUT VOID *OptParam - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 i; - CONST UINT16 AfterTstabRcwTable[] = { - 0x0270, 0x0000, - 0x0122, 0x0074, - 0x0124, 0x009B, - 0x0126, 0x00C2, - 0x0128, 0x00E8, - 0x01D2, 0x5942, - 0x01D4, 0x836D, - 0x01CE, 0x5942, - 0x01D0, 0x836D, - 0x01D6, 0x017F, - 0x01D8, 0x0000, - 0x01F0, 0x008E, - 0x01F2, 0x00BA, - 0x01F4, 0x00E8, - 0x01F6, 0x0114, - 0x0B40, 0x7054, - 0x0B42, 0xA48A, - 0x0B3C, 0x7054, - 0x0B3E, 0xA48A, - 0x0B38, 0x0100, - 0x0B3A, 0x0000, - - 0x0274, 0x55AA, - 0x3012, 0x0080, - 0x3018, 0x6B80 - }; - if (MemTLrDimmGetBufferID (TechPtr, Dimm) != 0x0021B304) { - return; - } - NBPtr = TechPtr->NBPtr; - switch (Entrypoint) { - case AFTER_TSTAB: - MemTSendMBCtlWord3 (TechPtr, F14, RC0, 0xB); - for ( i = 0 ; i < (sizeof (AfterTstabRcwTable) / sizeof (UINT16)); i += 2 ) { - MemTSendExtMBCtlWord3 (TechPtr, AfterTstabRcwTable[i], AfterTstabRcwTable[i + 1], 2); - } - break; - default: - // - // If a hook entrypoint is called, it should have a case for it. - // - ASSERT (FALSE); - break; - } -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.h deleted file mode 100644 index 4a89c04b15..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * @file - * - * mtlrdimm3.h - * - * Definitions and declarations for DDR3 LRDIMM support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTLRDIMM3_H_ -#define _MTLRDIMM3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define RCW_FN_SELECT 7 - -#define F0 0 -#define F1 1 -#define F2 2 -#define F3 3 -#define F4 4 -#define F5 5 -#define F6 6 -#define F7 7 -#define F8 8 -#define F9 9 -#define F10 10 -#define F11 11 -#define F12 12 -#define F13 13 -#define F14 14 -#define F15 15 - -#define RC0 0 -#define RC1 1 -#define RC2 2 -#define RC3 3 -#define RC4 4 -#define RC5 5 -#define RC6 6 -#define RC7 7 -#define RC8 8 -#define RC9 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 - -#define SPD_NONE 0 -#define SPD_67 67 -#define SPD_68 68 -#define SPD_69 69 -#define SPD_70 70 -#define SPD_71 71 - -#define SPD_MDQ_800_1066 72 -#define SPD_QXODT_800_1066 73 -#define SPD_MR1_MR2_800_1066 77 -#define SPD_PERSONALITY_BYTE 102 -#define SPD_FREQ_DIFF_OFFSET 6 - -#define SPECIAL_CASE 0xFF -#define WAIT_6US 0xF6 - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/// LRDIMM SPECIALIZED HOOK ENTRY POINTS -typedef enum { - AFTER_TSTAB, ///< Time point after tStab - AFTER_RCW, ///< Time point after LrDimm Rcw commands are sent - BEFORE_BUFFERTRN, ///< Time point just before Buffer training - AFTER_BUFFERTRN, ///< Time point just after Buffer training - BEFORE_HOST_WL, ///< Time point before host WL - AFTER_HOST_WL ///< Time point after host WL -} LRDIMM_HOOK_ENTRYPOINT; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -#endif /* _MTLRDIMM3_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.c deleted file mode 100644 index a938de6e38..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.c +++ /dev/null @@ -1,168 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtot3.c - * - * Technology Non-SPD Timings for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mtot3.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_DDR3_MTOT3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function adjusts the Twrwr value for DDR3. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTAdjustTwrwr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - DCT_STRUCT *DCTPtr; - - DCTPtr = TechPtr->NBPtr->DCTPtr; - - // For DDR3, value 0000b-0001b and >= 1011b of Twrwr is reserved. - if (DCTPtr->Timings.Twrwr < 2) { - DCTPtr->Timings.Twrwr = 2; - } else if (DCTPtr->Timings.Twrwr > 10) { - DCTPtr->Timings.Twrwr = 10; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function adjusts the Twrrd value for DDR3. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTAdjustTwrrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - DCT_STRUCT *DCTPtr; - - DCTPtr = TechPtr->NBPtr->DCTPtr; - - // For DDR3, value 0000b, 0001b, and > 1010b of Twrrd is reserved. - if (DCTPtr->Timings.Twrrd < 2) { - DCTPtr->Timings.Twrrd = 2; - } else if (DCTPtr->Timings.Twrrd > 10) { - DCTPtr->Timings.Twrrd = 10; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets the LD value for DDR3. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return Value of LD - */ - -INT8 -MemTGetLD3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - INT8 LD; - MEM_NB_BLOCK *NBPtr; - NBPtr = TechPtr->NBPtr; - // - // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS - // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive - // value. - // - LD = ((INT8) NBPtr->GetBitField (NBPtr, BFTcl) + 4) - ((INT8) NBPtr->GetBitField (NBPtr, BFTcwl) + 5); - - return LD; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.h deleted file mode 100644 index a89b06e8b6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.h +++ /dev/null @@ -1,89 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtot3.h - * - * Technology Non-SPD timings for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTOT3_H_ -#define _MTOT3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - - -VOID -MemTAdjustTwrwr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -VOID -MemTAdjustTwrrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -INT8 -MemTGetLD3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -#endif /* _MTOT3_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c deleted file mode 100644 index 79fef4d84c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c +++ /dev/null @@ -1,319 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtrci3.c - * - * Technology Control word initialization for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mt3.h" -#include "mtrci3.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_DDR3_MTRCI3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends control words - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTDramControlRegInit3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 ChipSel; - UINT8 i; - UINT8 RawCard; - UINT8 Data; - UINT16 CsPresent; - - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - CsPresent = NBPtr->DCTPtr->Timings.CsPresent; - - MemUWait10ns (800, MemPtr); // wait 8us TACT must be changed to optimize to 8 MEM CLKs - - // Set EnDramInit to start DRAM initialization - - MemUWait10ns (600, MemPtr); // wait 6us for PLL LOCK - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - // - // If chip select present - // - if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) { - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - - // 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. - NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE)); - - RawCard = NBPtr->ChannelPtr->RefRawCard[ChipSel >> 1]; - - for (i = 0; i <= 15; i++) { - // wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs - MemUWait10ns (800, MemPtr); - if ((i != 6) && (i != 7)) { - Data = MemTGetCtlWord3 (TechPtr, i, RawCard, ChipSel); - MemTSendCtlWord3 (TechPtr, i, Data); - } - } - } - } - MemUWait10ns (600, MemPtr); // wait 6us for TSTAB -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the ControlRC value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] CtrlWordNum - control Word number. - * @param[in] RawCard - Raw Card - * @param[in] ChipSel - Target Chip Select - * @return Control Word value - */ - -UINT8 -MemTGetCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 CtrlWordNum, - IN UINT8 RawCard, - IN UINT8 ChipSel - ) -{ - UINT8 Data; - UINT8 PowerDownMode; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - - DCTPtr = TechPtr->NBPtr->DCTPtr; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Data = 0; //Default value for all control words is 0 - switch (CtrlWordNum) { - case 0: - Data = 0x02; // DA4=1 - break; - case 1: - if (DCTPtr->Timings.DimmSRPresent & ((UINT16) 1 << (ChipSel >> 1))) { - Data = 0x0C; // if single rank, set DBA1 and DBA0 - } - break; - case 2: - Data = ChannelPtr->CtrlWrd02[ChipSel >> 1]; - break; - case 3: - Data = ChannelPtr->CtrlWrd03[ChipSel >> 1]; - break; - case 4: - Data = ChannelPtr->CtrlWrd04[ChipSel >> 1]; - break; - case 5: - Data = ChannelPtr->CtrlWrd05[ChipSel >> 1]; - break; - case 8: - Data = ChannelPtr->CtrlWrd08[ChipSel >> 1]; - break; - case 9: - // RC9 = 0xD except when partial powerdown mode is enabled and mix SR/DR or SR/QR configurations, - // RC9 should be 0x9 for SR and and 0xD for DR or QR RDIMMs. - PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; - PowerDownMode = (!TechPtr->NBPtr->IsSupported[ChannelPDMode]) ? PowerDownMode : 0; - IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(TechPtr->NBPtr->MemPtr->StdHeader)); - if ((PowerDownMode == 1) && - (DCTPtr->Timings.DimmSRPresent & ((UINT16) 1 << (ChipSel >> 1))) && - ((DCTPtr->Timings.DimmDrPresent != 0) || (DCTPtr->Timings.DimmQrPresent != 0))) { - Data = 0x09; - } else { - Data = 0x0D; - } - break; - case 11: - Data = CONVERT_VDDIO_TO_ENCODED (TechPtr->RefPtr->DDR3Voltage); - break; - default:; - } - - return (Data & 0x0F); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends control word command - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] CmdNum - control number. - * @param[in] Value - value to send - * - */ - -VOID -MemTSendCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 CmdNum, - IN UINT8 Value - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - // 1. Program MrsBank and MrsAddress. - // n = [BA2, A2, A1, A0]. - // data = [BA1, BA0, A4, A3]. - // Set all other bits in MrsAddress to zero. - // - NBPtr->SetBitField (NBPtr, BFMrsBank, ((CmdNum & 8) >> 1) | (Value >> 2)); - NBPtr->SetBitField (NBPtr, BFMrsAddress, ((Value & 3) << 3) | (CmdNum & 7)); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d RC%02d %04x\n", (MemNGetBitFieldNb (NBPtr, BFMrsChipSel) & 7), CmdNum, Value); - - // 2.Set SendCtrlWord=1 - NBPtr->SetBitField (NBPtr, BFSendCtrlWord, 1); - // 3.Wait for BFSendCtrlWord=0 - NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sends specific control words commands before frequency change for certain DRAM buffers. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -FreqChgCtrlWrd3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 ChipSel; - UINT16 Speed; - UINT16 CsPresent; - - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - Speed = NBPtr->DCTPtr->Timings.Speed; - CsPresent = NBPtr->DCTPtr->Timings.CsPresent; - - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - // - // If chip select present. - // - if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) { - - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - // program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. - NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE)); - - //wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs - MemUWait10ns (800, MemPtr); - if (Speed == DDR800_FREQUENCY) { - MemTSendCtlWord3 (TechPtr, 0x0A, 0); - } else if (Speed == DDR1066_FREQUENCY) { - MemTSendCtlWord3 (TechPtr, 0x0A, 1); - } else if (Speed == DDR1333_FREQUENCY) { - MemTSendCtlWord3 (TechPtr, 0x0A, 2); - } else if (Speed == DDR1600_FREQUENCY) { - MemTSendCtlWord3 (TechPtr, 0x0A, 3); - } else if (Speed == DDR1866_FREQUENCY) { - MemTSendCtlWord3 (TechPtr, 0x0A, 4); - } else { - ASSERT (FALSE); - } - } - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.h deleted file mode 100644 index ce6a7c2977..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.h +++ /dev/null @@ -1,86 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtrci3.h - * - * Technology control word init for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTRCI3_H_ -#define _MTRCI3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -UINT8 -MemTGetCtlWord3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 CtrlWordNum, - IN UINT8 RawCard, - IN UINT8 ChipSel - ); - -VOID -MemTDramControlRegInit3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -#endif /* _MTRCI3_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.c deleted file mode 100644 index 6ce925694c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.c +++ /dev/null @@ -1,503 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtsdi3.c - * - * Technology Software DRAM Init for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mt3.h" -#include "mtsdi3.h" -#include "mtrci3.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_TECH_DDR3_MTSDI3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates software DRAM init for both DCTs - * at the same time. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -BOOLEAN -MemTDramInitSw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - UINT8 ChipSel; - - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Dram Init\n"); - // 3.Program F2x[1,0]7C[EnDramInit]=1 - IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for both DCTs\n"); - NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 1); - NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE); - - // 4.wait 200us - MemUWait10ns (20000, MemPtr); - - // 5.Program F2x[1, 0]7C[DeassertMemRstX] = 1. - NBPtr->BrdcstSet (NBPtr, BFDeassertMemRstX, 1); - - // 6.wait 500us - MemUWait10ns (50000, MemPtr); - - // Do Phy Fence training before sending MRS commands - if (!NBPtr->IsSupported[FenceTrnBeforeDramInit]) { - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->PhyFenceTraining (NBPtr); - } - } - } - - // 7.NOP or deselect & take CKE high - NBPtr->BrdcstSet (NBPtr, BFAssertCke, 1); - - // 8.wait 360ns - MemUWait10ns (36, MemPtr); - - // The following steps are performed once for each channel with unbuffered DIMMs - // and once for each chip select on registered DIMMs: - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - - // Enable Dram Parity if appropriate. - NBPtr->FamilySpecificHook[EnableParityAfterMemRst] (NBPtr, NULL); - - // The following steps are performed with registered DIMMs only and - // must be done for each chip select pair: - if (MCTPtr->Status[SbRegistered]) { - MemTDramControlRegInit3 (TechPtr); - } - - // Initialize LRDIMM's register - TechPtr->TechnologySpecificHook[LrdimmControlRegInit] (TechPtr, NULL); - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); - // if chip select present - if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) { - MemTSendAllMRCmds3 (TechPtr, ChipSel); - } - // NOTE: wait 512 clocks for DLL-relock - MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us - if (!(MCTPtr->Status[SbRegistered] || MCTPtr->Status[SbLrdimms])) { - break; - } - } - } - - // 17.Send two ZQCL commands (to even then odd chip select) - NBPtr->sendZQCmd (NBPtr); - NBPtr->sendZQCmd (NBPtr); - } - } - - // 18.Program F2x[1,0]7C[EnDramInit]=0 - NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 0); - NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE); - // - // For Unbuffered Dimms, Issue MRS for remaining CS without EnDramInit - // - NBPtr->FamilySpecificHook[SendMrsCmdsPerCs] (NBPtr, NBPtr); - - IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n"); - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS1 value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Wl - Indicates if WL mode should be enabled - * @param[in] TargetDIMM - DIMM target for WL - */ - -VOID -MemTEMRS13 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN BOOLEAN Wl, - IN UINT8 TargetDIMM - ) -{ - UINT16 MrsAddress; - UINT8 MaxDimmPerCH; - UINT8 ChipSel; - UINT8 Value8; - - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, - NBPtr->MCTPtr->SocketId, - NBPtr->ChannelPtr->ChannelID); - ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel)); - - // BA2=0,BA1=0,BA0=1 - NBPtr->SetBitField (NBPtr, BFMrsBank, 1); - - MrsAddress = 0; - - // program MrsAddress[5,1]=output driver impedance control (DIC): - // based on F2x[1,0]84[DrvImpCtrl] - if (!(NBPtr->IsSupported[CheckDrvImpCtrl])) { - Value8 = (UINT8)NBPtr->GetBitField (NBPtr, BFDrvImpCtrl); - if ((Value8 & ((UINT8) 1 << 1)) != 0) { - MrsAddress |= ((UINT16) 1 << 5); - } - if ((Value8 & ((UINT8) 1 << 0)) != 0) { - MrsAddress |= ((UINT16) 1 << 1); - } - } else { - MrsAddress |= ((UINT16) 1 << 1); - } - // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT): - // Different CS may have different RTT. - // - Value8 = NBPtr->MemNGetDramTerm (NBPtr, ChipSel); - - // - // If Write Leveling this DIMM - // - if (Wl) { - if ((ChipSel >> 1) == TargetDIMM) { - // Program MrsAddress[7] = 1 for Write leveling enable - MrsAddress |= ((UINT16) 1 << 7); - if (ChipSel & 1) { - // Output buffer disabled, MrsAddress[7] (Qoff = 1) - MrsAddress |= ((UINT16) 1 << 12); - } - // Set Rtt_Nom = Rtt_Wr if there are 2 or more dimms - if ((NBPtr->ChannelPtr->DimmQrPresent != 0) || (NBPtr->ChannelPtr->Dimms >= 2)) { - Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel); - } else if (NBPtr->IsSupported[WlRttNomFor1of3Cfg] && (MaxDimmPerCH == 3)) { - // For some family, set Rtt_Nom = Rtt_Wr in one of three DIMMs per channel configurations - Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel); - } - } - } - // - // Turn off Rtt_Nom (DramTerm=0) for certain CS in certain configs. - // - // All odd CS for 4 Dimm Systems - if (MaxDimmPerCH == 4) { - if (ChipSel & 0x01) { - Value8 = 0; - } - // CS 1 and 5 for 3 Dimm configs - } else if (MaxDimmPerCH == 3) { - if ((ChipSel == 1) || (ChipSel == 5)) { - Value8 = 0; - } - } - // All odd CS of any QR Dimms - if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) { - if (ChipSel & 0x01) { - Value8 = 0; - } - } - if ((Value8 & ((UINT8) 1 << 2)) != 0) { - MrsAddress |= ((UINT16) 1 << 9); - } - if ((Value8 & ((UINT8) 1 << 1)) != 0) { - MrsAddress |= ((UINT16) 1 << 6); - } - if ((Value8 & ((UINT8) 1 << 0)) != 0) { - MrsAddress |= ((UINT16) 1 << 2); - } - - // program MrsAddress[12]=output disable (QOFF): - // based on F2x[1,0]84[Qoff] - - if (!NBPtr->IsSupported[CheckQoff]) { - if (NBPtr->GetBitField (NBPtr, BFQoff) != 0) { - MrsAddress |= ((UINT16) 1 << 12); - } - } - - // program MrsAddress[11]=TDQS: - // based on F2x[1,0]94[RDqsEn] - - if ((NBPtr->DCTPtr->Timings.Dimmx4Present != 0) && (NBPtr->DCTPtr->Timings.Dimmx8Present != 0)) { - if (!(NBPtr->IsSupported[SetTDqsForx8DimmOnly]) || ((NBPtr->DCTPtr->Timings.Dimmx8Present & ((UINT8) 1 << (ChipSel >> 1))) != 0)) { - MrsAddress |= ((UINT16) 1 << 11); - } - } - - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS2 value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTEMRS23 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT32 MrsAddress; - UINT8 DramTermDyn; - UINT8 MaxDimmPerCH; - UINT8 ChipSel; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID ); - ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel)); - - // BA2=0,BA1=1,BA0=0 - NBPtr->SetBitField (NBPtr, BFMrsBank, 2); - - // program MrsAddress[5:3]=CAS write latency (CWL): - MrsAddress = NBPtr->MemNGetMR2CWL (NBPtr); - - // program MrsAddress[6]=auto self refresh method (ASR): - // program MrsAddress[7]=self refresh temperature range (SRT): - MrsAddress |= 1 << 6; - MrsAddress &= ( ~ (1 << 7)); - - // program MrsAddress[10:9]=dynamic termination during writes (RTT_WR): - DramTermDyn = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel); - // Special Case for 1 DR Unbuffered Dimm in 3 Dimm/Ch - if (!(NBPtr->MCTPtr->Status[SbRegistered])) { - if (MaxDimmPerCH == 3) { - if (NBPtr->ChannelPtr->Dimms == 1) { - if ((NBPtr->ChannelPtr->DimmDrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) { - DramTermDyn = 1; - } - } - } - } - MrsAddress |= (UINT16) DramTermDyn << 9; - - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the EMRS3 value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTEMRS33 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - // BA2=0,BA1=1,BA0=1 - NBPtr->SetBitField (NBPtr, BFMrsBank, 3); - - // program MrsAddress[1:0]=multi purpose register address location - // (MPR Location):based on F2x[1,0]84[MprLoc] - // program MrsAddress[2]=multi purpose register - // (MPR):based on F2x[1,0]84[MprEn] - NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This sets MRS value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTMRS3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT32 MrsAddress; - MEM_NB_BLOCK *NBPtr; - UINT32 Ppd; - - NBPtr = TechPtr->NBPtr; - - // BA2=0,BA1=0,BA0=0 - NBPtr->SetBitField (NBPtr, BFMrsBank, 0); - - // program MrsAddress[1:0]=burst length and control method - // (BL):based on F2x[1,0]84[BurstCtrl] - MrsAddress = NBPtr->GetBitField (NBPtr, BFBurstCtrl); - - // program MrsAddress[3]=1 (BT):interleaved - MrsAddress |= (UINT16) 1 << 3; - - // program MrsAddress[6:4,2]=read CAS latency - MrsAddress |= NBPtr->MemNGetMR0CL (NBPtr); - - // program MrsAddress[11:9]=write recovery for auto-precharge - MrsAddress |= NBPtr->MemNGetMR0WR (NBPtr); - - // program MrsAddress[12] (PPD):based on F2x[1,0]84[PChgPDModeSel] - Ppd = NBPtr->GetBitField (NBPtr, BFPchgPDModeSel); - NBPtr->FamilySpecificHook[MR0_PPD] (NBPtr, &Ppd); - IDS_OPTION_HOOK (IDS_MEM_MR0, &Ppd, &TechPtr->NBPtr->MemPtr->StdHeader); - MrsAddress |= Ppd << 12; - - // program MrsAddress[8]=1 (DLL):DLL reset - MrsAddress |= (UINT32) 1 << 8; - - // During memory initialization, the value sent to MR0 is saved for S3 resume - NBPtr->MemNSaveMR0 (NBPtr, MrsAddress); - - NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This send all MR commands to a rank in sequence 2-3-1-0 - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ChipSel - Target Chip Select - */ - -VOID -MemTSendAllMRCmds3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - - // 13.Send EMRS(2) - MemTEMRS23 (TechPtr); - AGESA_TESTPOINT (TpProcMemSendMRS2, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SendMrsCmd (NBPtr); - - // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b - MemTEMRS33 (TechPtr); - AGESA_TESTPOINT (TpProcMemSendMRS3, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SendMrsCmd (NBPtr); - - // 15.Send EMRS(1). - MemTEMRS13 (TechPtr, FALSE, (ChipSel >> 1)); - AGESA_TESTPOINT (TpProcMemSendMRS1, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SendMrsCmd (NBPtr); - - // 16.Send MRS with MrsAddress[8]=1(reset the DLL) - MemTMRS3 (TechPtr); - AGESA_TESTPOINT (TpProcMemSendMRS0, &(NBPtr->MemPtr->StdHeader)); - NBPtr->SendMrsCmd (NBPtr); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.h deleted file mode 100644 index 2447d9ebea..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.h +++ /dev/null @@ -1,95 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtsdi3.h - * - * Technology software DRAM init for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTSDI3_H_ -#define _MTSDI3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -VOID -MemTEMRS33 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -VOID -MemTMRS3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -VOID -MemTEMRS13 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN BOOLEAN Wl, - IN UINT8 TargetDIMM - ); - -VOID -MemTEMRS23 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -#endif /* _MTSDI3_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c deleted file mode 100644 index 83f7aac320..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c +++ /dev/null @@ -1,1191 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtspd3.c - * - * Technology SPD supporting functions for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 56379 $ @e \$Date: 2011-07-12 14:14:49 -0600 (Tue, 12 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mt3.h" -#include "mu.h" -#include "mtspd3.h" -#include "mftds.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_DDR3_MTSPD3_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemTCRCCheck3 ( - IN OUT UINT8 *SPDPtr - ); - -UINT8 -STATIC -MemTSPDGetTCL3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -STATIC -MemTCheckBankAddr3 ( - IN UINT8 Encode, - OUT UINT8 *Index - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the DRAM mode - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that the DRAM mode is set to DDR3 - */ - -BOOLEAN -MemTSetDramMode3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0); - TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFDdr3Mode, 1); - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines if DIMMs are present. It checks checksum and interrogates the SPDs - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that a FATAL error has not occurred - * @return FALSE - indicates that a FATAL error has occurred - */ - -BOOLEAN -MemTDIMMPresence3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - UINT8 Channel; - UINT8 i; - MEM_PARAMETER_STRUCT *RefPtr; - UINT8 *SpdBufferPtr = NULL; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - MEM_NB_BLOCK *NBPtr; - BOOLEAN SPDCtrl; - UINT8 Devwidth; - UINT8 MaxDimms; - UINT8 NumDimmslots; - UINT8 Value8; - UINT16 DimmMask; - UINT32 DimmValidMask; - - NBPtr = TechPtr->NBPtr; - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - - SPDCtrl = UserOptions.CfgIgnoreSpdChecksum; - DimmValidMask = 0; - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - ChannelPtr = NBPtr->ChannelPtr; - ChannelPtr->DimmQrPresent = 0; - // - // Get the maximum number of DIMMs - // - MaxDimms = MAX_DIMMS_PER_CHANNEL; - NumDimmslots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, - MCTPtr->SocketId, - ChannelPtr->ChannelID); - DimmValidMask |= (NumDimmslots == 3) ? 0x7 : 0x3; - - for (i = 0; i < MaxDimms; i++) { - // Bitmask representing dimm #i. - DimmMask = (UINT16)1 << i; - // - if (MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i)) { - MCTPtr->DimmPresent |= DimmMask; - // - // Check for valid checksum value - // - AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader)); - if (SpdBufferPtr[SPD_TYPE] == JED_DDR3SDRAM) { - ChannelPtr->ChDimmValid |= DimmMask; - MCTPtr->DimmValid |= DimmMask; - } else { - // Current socket is set up to only support DDR3 dimms. - IDS_ERROR_TRAP; - } - if (!MemTCRCCheck3 (SpdBufferPtr) && !SPDCtrl) { - // - // NV_SPDCHK_RESTRT is set to 0, - // cannot ignore faulty SPD checksum - // - // Indicate checksum error - ChannelPtr->DimmSpdCse |= DimmMask; - PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - } - // - // Check module type information. - // - if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_LRDIMM) { - // - // LRDIMMS - // - if (i < NumDimmslots) { - ChannelPtr->LrDimmPresent |= DimmMask; - MCTPtr->LrDimmPresent |= DimmMask; - - if (!UserOptions.CfgMemoryLRDimmCapable) { - PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_LRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - IDS_ERROR_TRAP; - } - TechPtr->TechnologySpecificHook[LrdimmPresence] (TechPtr, &i); - } - } - if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_RDIMM || SpdBufferPtr[SPD_DIMM_TYPE] == JED_MINIRDIMM) { - // - // RDIMMS - // - ChannelPtr->RegDimmPresent |= DimmMask; - MCTPtr->RegDimmPresent |= DimmMask; - if (!UserOptions.CfgMemoryRDimmCapable) { - PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_RDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - IDS_ERROR_TRAP; - } - } - if ((SpdBufferPtr[SPD_DIMM_TYPE] == JED_UDIMM) && !UserOptions.CfgMemoryUDimmCapable) { - PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - IDS_ERROR_TRAP; - } - if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_SODIMM) { - ChannelPtr->SODimmPresent |= DimmMask; - if (!UserOptions.CfgMemorySODimmCapable) { - PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_SODIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - IDS_ERROR_TRAP; - } - } - // - // Check error correction type - // - if ((SpdBufferPtr[SPD_ECCBITS] & JED_ECC) != 0) { - MCTPtr->DimmEccPresent |= DimmMask; // Dimm has ECC - } - // - // Get the Dimm width data - // - Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0x7; - switch (Devwidth) { - case 0: - ChannelPtr->Dimmx4Present |= DimmMask; - ChannelPtr->DimmNibbleAccess |= DimmMask; - Devwidth = 4; - break; - case 1: - ChannelPtr->Dimmx8Present |= DimmMask; - Devwidth = 8; - break; - case 2: - ChannelPtr->Dimmx16Present |= DimmMask; - Devwidth = 16; - break; - default: - IDS_ERROR_TRAP; - } - // - // Check for 'analysis probe installed' - // if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK) - // - // Determine the geometry of the DIMM module - // if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT) - // - // specify the number of ranks - // - Value8 = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1; - if (Value8 == 5) { - // Octal Rank - Value8 = 8; - } - // - // For LRDIMMS we will assume that if there are at least 4 Physical ranks, then it Could be used - // as a QR RDIMM with a rank Mux of x1 and therefore all four CS will be used. So an 8R LRDIMM will - // be marked as a QR even if Rank multiplication allows it to use only 2 logical ranks. - // - if ((ChannelPtr->LrDimmPresent & DimmMask) != 0) { - // - // LRDIMM Physical Ranks - // - ChannelPtr->LrdimmPhysicalRanks[i] = Value8; - } - if (Value8 > 2) { - if (!UserOptions.CfgMemoryQuadRankCapable) { - PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_QRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - } - // - // Mark this Dimm as Quad Rank - // - ChannelPtr->DimmQrPresent |= DimmMask; - Value8 = 2; - } else if (Value8 == 2) { - ChannelPtr->DimmDrPresent |= DimmMask; // Dual rank dimms - } else { - ChannelPtr->DimmSRPresent |= DimmMask; // Single rank dimms - } - // - // Calculate bus loading per Channel - if (Devwidth == 16) { - Devwidth = 4; - } else if (Devwidth == 4) { - Devwidth = 16; - } - // - // Double Addr bus load value for dual rank DIMMs (Unless LRDIMM) - // - if (((ChannelPtr->LrDimmPresent & DimmMask) == 0) && (Value8 == 2) ) { - Devwidth = Devwidth << 1; - } - // - ChannelPtr->Ranks = ChannelPtr->Ranks + Value8; - ChannelPtr->Loads = ChannelPtr->Loads + Devwidth; - if ((i < NumDimmslots) || ((ChannelPtr->DimmQrPresent & DimmMask) == 0)) { - ChannelPtr->Dimms++; - } - // - // Check address mirror support for Unbuffered Dimms or LRDimms - // - if ((ChannelPtr->RegDimmPresent & DimmMask) == 0) { - if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) { - ChannelPtr->DimmMirrorPresent |= DimmMask; - } - } - // - // Get byte62: Reference Raw Card information - // - ChannelPtr->RefRawCard[i] = SpdBufferPtr[SPD_RAWCARD] & 0x1F; - // - // Get control word values for RC3, RC4 and RC5 - // - ChannelPtr->CtrlWrd03[i] = SpdBufferPtr[SPD_CTLWRD03] >> 4; - ChannelPtr->CtrlWrd04[i] = SpdBufferPtr[SPD_CTLWRD04] & 0x0F; - ChannelPtr->CtrlWrd05[i] = SpdBufferPtr[SPD_CTLWRD05] >> 4; - // - // Temporarily store info. of SPD byte 63 into CtrlWrd02(s), - // and they will be used late to calculate real RC2 and RC8 value - // - ChannelPtr->CtrlWrd02[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03; - // - // Copy the number of registers to the Ps Block to persist across frequency changes - // - NBPtr->PsPtr->NumOfReg[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03; - // - // Workaround for early revisions of DIMMs which SPD byte 63 is 0 - // - if (NBPtr->PsPtr->NumOfReg[i] == JED_UNDEFINED) { - NBPtr->PsPtr->NumOfReg[i] = 1; - } - } // if DIMM present - } // Dimm loop - - // - // DimmNibbleAccess indicates that a DIMM will use nibble signaling and use nibble training. - // LRDIMMs will not use Nibble based signaling even if x4 parts are present. - // - if (ChannelPtr->LrDimmPresent != 0) { - ChannelPtr->DimmNibbleAccess = 0; - } - - if (Channel == 0) { - DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid; - DCTPtr->Timings.DimmMirrorPresent = ChannelPtr->DimmMirrorPresent; - DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse; - DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent; - DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent; - DCTPtr->Timings.DimmSRPresent = ChannelPtr->DimmSRPresent; - DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present; - DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present; - DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present; - } - if ((Channel != 1) || (Dct != 1)) { - MCTPtr->DimmPresent <<= 8; - MCTPtr->DimmValid <<= 8; - MCTPtr->RegDimmPresent <<= 8; - MCTPtr->LrDimmPresent <<= 8; - MCTPtr->DimmEccPresent <<= 8; - MCTPtr->DimmParPresent <<= 8; - DimmValidMask <<= 8; - } - } // Channel loop - } // DCT loop - - // If we have DIMMs, some further general characteristics checking - if (MCTPtr->DimmValid != 0) { - // If there are registered dimms, all the dimms must be registered - if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) { - // All dimms registered - MCTPtr->Status[SbRegistered] = TRUE; - MCTPtr->Status[SbParDimms] = TRUE; // All DDR3 RDIMMs are parity capable - TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgsRDdr3; // Change the function pointer for DQS ECC timing - } else if (MCTPtr->RegDimmPresent != 0) { - // We have an illegal DIMM mismatch - PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - } - // If there are LrDimms, all the dimms must be LrDimms - if (MCTPtr->LrDimmPresent == (MCTPtr->DimmValid & DimmValidMask)) { - // All dimms LRDIMMs - MCTPtr->Status[SbLrdimms] = TRUE; - MCTPtr->Status[SbParDimms] = TRUE; // All DDR3 RDIMMs are parity capable - } else if (MCTPtr->LrDimmPresent != 0) { - // We have an illegal DIMM mismatch - PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - } - - // check the ECC capability of the DIMMs - if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) { - MCTPtr->Status[SbEccDimms] = TRUE; // All dimms ECC capable - } - } else { - } - - NBPtr->SwitchDCT (NBPtr, 0); - NBPtr->SwitchChannel (NBPtr, 0); - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finds the maximum frequency that each channel is capable to run at. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that a FATAL error has not occurred - * @return FALSE - indicates that a FATAL error has occurred - */ - -BOOLEAN -MemTSPDGetTargetSpeed3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 *SpdBufferPtr = NULL; - UINT8 Dimm; - UINT8 Dct; - UINT8 Channel; - INT32 MTB_ps; - INT32 FTB_ps; - INT32 TCKmin_ps; - INT32 Value32; - MEM_NB_BLOCK *NBPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - TCKmin_ps = 0; - for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) { - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); - - // Determine tCKmin(all) which is the largest tCKmin - // value for all modules on the memory Channel (SPD byte 12). - // - MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR]; - FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF); - Value32 = (MTB_ps * SpdBufferPtr[SPD_TCK]) + (FTB_ps * (INT8) SpdBufferPtr[SPD_TCK_FTB]) ; - if (TCKmin_ps < Value32) { - TCKmin_ps = Value32; - } - } - } - } - if (TCKmin_ps <= 1071) { - DCTPtr->Timings.TargetSpeed = DDR1866_FREQUENCY; - } else if (TCKmin_ps <= 1250) { - DCTPtr->Timings.TargetSpeed = DDR1600_FREQUENCY; - } else if (TCKmin_ps <= 1500) { - DCTPtr->Timings.TargetSpeed = DDR1333_FREQUENCY; - } else if (TCKmin_ps <= 1875) { - DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY; - } else if (TCKmin_ps <= 2500) { - DCTPtr->Timings.TargetSpeed = DDR800_FREQUENCY; - } else { - DCTPtr->Timings.TargetSpeed = DDR667_FREQUENCY; - } - } - - // Ensure the target speed can be applied to all channels of the current node - NBPtr->SyncTargetSpeed (NBPtr); - - // Set the start-up frequency - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->DCTPtr->Timings.Speed = TechPtr->NBPtr->StartupSpeed; - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function check the symmetry of DIMM pairs (DIMM on Channel A matching with - * DIMM on Channel B), the overall DIMM population, and determine the width mode: - * 64-bit, 64-bit muxed, 128-bit. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that a FATAL error has not occurred - * @return FALSE - indicates that a FATAL error has occurred - */ - -BOOLEAN -MemTSPDCalcWidth3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 *SpdBufferAPtr = NULL; - UINT8 *SpdBufferBPtr = NULL; - MEM_NB_BLOCK *NBPtr; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - UINT8 i; - UINT16 DimmMask; - UINT8 UngangMode; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - UngangMode = UserOptions.CfgMemoryModeUnganged; - // Does not support ganged mode for DDR3 dimms - ASSERT (UngangMode); - IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader)); - - // Check symmetry of channel A and channel B dimms for 128-bit mode - // capability. - // - AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader)); - i = 0; - if (!UngangMode) { - if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) { - for (; i < MAX_DIMMS_PER_CHANNEL; i++) { - DimmMask = (UINT16)1 << i; - if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) { - NBPtr->SwitchDCT (NBPtr, 0); - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferAPtr, i); - NBPtr->SwitchDCT (NBPtr, 1); - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferBPtr, i); - // compare rows and columns - if ((SpdBufferAPtr[SPD_ROW_SZ]&0x3F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x3F)) { - break; - } - if ((SpdBufferAPtr[SPD_DENSITY]&0x0F) != (SpdBufferBPtr[SPD_DENSITY]&0x0F)) { - break; - } - // compare ranks and devwidth - if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) { - break; - } - } - } - } - if (i < MAX_DIMMS_PER_CHANNEL) { - PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ALERT, MCTPtr); - } else { - NBPtr->Ganged = TRUE; - MCTPtr->GangedMode = TRUE; - MCTPtr->Status[Sb128bitmode] = TRUE; - NBPtr->SetBitField (NBPtr, BFDctGangEn, 1); - } - } - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * Initialize DCT Timing registers as per DIMM SPD. - * For primary timing (T, CL) use best case T value. - * For secondary timing params., use most aggressive settings - * of slowest DIMM. - * - * Note: - * There are three components to determining "maximum frequency": SPD component, - * Bus load component, and "Preset" max frequency component. - * The SPD component is a function of the min cycle time specified by each DIMM, - * and the interaction of cycle times from all DIMMs in conjunction with CAS - * latency. The SPD component only applies when user timing mode is 'Auto'. - * - * The Bus load component is a limiting factor determined by electrical - * characteristics on the bus as a result of varying number of device loads. The - * Bus load component is specific to each platform but may also be a function of - * other factors. The bus load component only applies when user timing mode is - * ' Auto'. - * - * The Preset component is subdivided into three items and is the minimum of - * the set: Silicon revision, user limit setting when user timing mode is 'Auto' and - * memclock mode is 'Limit', OEM build specification of the maximum frequency. - * The Preset component only applies when user timing mode is 'Auto'. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that a FATAL error has not occurred - * @return FALSE - indicates that a FATAL error has occurred - */ - -BOOLEAN -MemTAutoCycTiming3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - CONST UINT8 SpdIndexes[] = { - SPD_TRCD, - SPD_TRP, - SPD_TRTP, - SPD_TRAS, - SPD_TRC, - SPD_TWR, - SPD_TRRD, - SPD_TWTR, - SPD_TFAW - }; - - CONST UINT8 SpdFTBIndexes[] = { - SPD_TRCD_FTB, - SPD_TRP_FTB, - 0, - 0, - SPD_TRC_FTB, - 0, - 0, - 0, - 0 - }; - - UINT8 *SpdBufferPtr = NULL; - INT32 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)]; - UINT8 MiniMaxTrfc[4]; - - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_NB_BLOCK *NBPtr; - UINT16 DimmMask; - INT32 Value32; - INT32 MTB_ps; - INT32 FTB_ps; - INT32 TCK_ps; - UINT8 i; - UINT8 j; - UINT8 Value8; - UINT8 *StatTmgPtr; - UINT16 *StatDimmTmgPtr; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - // initialize mini-max arrays - for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) { - MiniMaxTmg[j] = 0; - } - for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) { - MiniMaxTrfc[j] = 0; - } - - // ====================================================================== - // Get primary timing (CAS Latency and Cycle Time) - // ====================================================================== - // Get OEM specific load variant max - // - - //====================================================================== - // Gather all DIMM mini-max values for cycle timing data - //====================================================================== - // - DimmMask = 1; - for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) { - if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) { - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i); - MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR]; - FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF); - - for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) { - Value32 = (UINT16)SpdBufferPtr[SpdIndexes[j]]; - if (SpdIndexes[j] == SPD_TRC) { - Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRC] & 0xF0) << 4; - } else if (SpdIndexes[j] == SPD_TRAS) { - Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRAS] & 0x0F) << 8; - } else if (SpdIndexes[j] == SPD_TFAW) { - Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TFAW] & 0x0F) << 8; - } - - Value32 *= MTB_ps; - if (SpdFTBIndexes[j] != 0) { - Value32 += (FTB_ps * (INT8) SpdBufferPtr[SpdFTBIndexes[j]]) ; - } - if (MiniMaxTmg[j] < Value32) { - MiniMaxTmg[j] = Value32; - } - } - - // get Trfc0 - Trfc3 values - Value8 = SpdBufferPtr[SPD_DENSITY] & 0x0F; - if (MiniMaxTrfc[i] < Value8) { - MiniMaxTrfc[i] = Value8; - } - } - DimmMask <<= 1; - } - - // ====================================================================== - // Convert DRAM CycleTiming values and store into DCT structure - // ====================================================================== - // - TCK_ps = 1000500 / DCTPtr->Timings.Speed; - - StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd; - StatTmgPtr = &DCTPtr->Timings.Trcd; - for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) { - Value32 = MiniMaxTmg[j]; - - MiniMaxTmg[j] = (MiniMaxTmg[j] + TCK_ps - 1) / TCK_ps; - - StatDimmTmgPtr[j] = (UINT16) (Value32 / (1000 / 40)); - StatTmgPtr[j] = (UINT8) MiniMaxTmg[j]; - } - DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0]; - DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1]; - DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2]; - DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3]; - - DCTPtr->Timings.CasL = MemTSPDGetTCL3 (TechPtr); - - //====================================================================== - // Program DRAM Timing values - //====================================================================== - // - NBPtr->ProgramCycTimings (NBPtr); - - MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming); - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the bank addressing, program Mask values and build a chip-select population map. - * This routine programs PCI 0:24N:2x80 config register. - * This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3) - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - indicates that a FATAL error has not occurred - * @return FALSE - indicates that a FATAL error has occurred - */ - -BOOLEAN -MemTSPDSetBanks3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 *SpdBufferPtr = NULL; - UINT8 i; - UINT8 ChipSel; - UINT8 DimmID; - UINT8 Value8; - UINT8 Rows; - UINT8 Cols; - UINT8 Ranks; - UINT8 Banks; - UINT32 BankAddrReg; - UINT32 CsMask; - UINT16 CSSpdCSE; - UINT16 CSExclude; - UINT16 DimmQRDR; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - BankAddrReg = 0; - CSSpdCSE = 0; - CSExclude = 0; - - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - DimmID = ChipSel >> 1; - - DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent); - if ((DCTPtr->Timings.DimmSpdCse & ((UINT16) 1 << DimmID)) != 0) { - CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel; - } - if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) { - CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel; - } - - if ((DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) != 0) { - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, DimmID); - - // Get the basic data - Rows = (SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7; - Cols = SpdBufferPtr[SPD_COL_SZ] & 0x7; - Banks = (SpdBufferPtr[SPD_L_BANKS] >> 4) & 0x7; - Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1; - if (Ranks == 5) { - Ranks = 8; - } - // - // Configure the bank encoding - // Use a 6-bit key into a lookup table. - // Key (index) = RRRBCC, where CC is the number of Columns minus 9, - // RRR is the number of Rows minus 12, and B is the number of banks - // minus 3. - // - Value8 = Cols; - Value8 |= (Banks == 1) ? 4 : 0; - Value8 |= Rows << 3; - - if (MemTCheckBankAddr3 (Value8, &i)) { - // - // Mask value=(2pow(rows+cols+banks+3)-1)>>8, - // or 2pow(rows+cols+banks-5)-1 - // - Value8 = (Rows + 12) + (Cols + 9) + (Banks + 3) + 3 - 8; - if (MCTPtr->Status[Sb128bitmode]) { - Value8++; - } - - DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel; - - if (Ranks >= 2) { - DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1); - } - // - // Determine LRDIMM Rank Multiplication - // - if (TechPtr->TechnologySpecificHook[LrdimmRankMultiplication] (TechPtr, &DimmID)) { - // - // Increase the CS Size by the rank multiplication factor - // - Value8 += ((NBPtr->ChannelPtr->LrDimmRankMult[DimmID]) >> 1); - CsMask = ((UINT32)1 << Value8) - 1; - CsMask &= NBPtr->CsRegMsk; - CsMask |= (NBPtr->GetBitField (NBPtr, BFRankDef0 + DimmID) & 0x03); - } else { - CsMask = ((UINT32)1 << Value8) - 1; - CsMask &= NBPtr->CsRegMsk; - } - // - // Update the DRAM CS Mask and BankAddrReg for this chipselect - // - if ((DCTPtr->Timings.CsPresent & (UINT16)3 << ChipSel) != 0) { - NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask)); - BankAddrReg |= ((UINT32)i << (ChipSel << 1)); - } - } else { - // - // Dimm is not supported, as no address mapping is found. - // - DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel; - DCTPtr->Timings.CsTestFail |= (UINT16)1 << ChipSel; - if (Ranks >= 2) { - DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1); - DCTPtr->Timings.CsTestFail |= (UINT16)1 << (ChipSel + 1); - } - PutEventLog (AGESA_ERROR, MEM_ERROR_NO_ADDRESS_MAPPING, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, DimmID, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - } - } //if (MemTCheckBankAddr3 (Value8, &i) - } - // For ranks that need to be excluded, the loading of this rank should be considered - // in timing, so need to set CsPresent before setting CsTestFail - if ((CSSpdCSE != 0) || (CSExclude != 0)) { - if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - } - - // If there are no chip selects, we have an error situation. - if (DCTPtr->Timings.CsPresent == 0) { - PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - } - - NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg); - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the low bit that will be swapped to enable CS interleaving - * - * @param[in] BankEnc - AddrMap Bank encoding from F2x80 - * @param[in] *LowBit - pointer to low bit - * @param[in] *HiBit - pointer hight bit - * - */ - -VOID -MemTGetCSIntLvAddr3 ( - IN UINT8 BankEnc, - OUT UINT8 *LowBit, - OUT UINT8 *HiBit - ) -{ - CONST UINT8 ArrCodesLo[] = {0, 8, 8, 0, 0, 8, 9, 8, 9, 9, 8, 9}; - CONST UINT8 ArrCodesHi[] = {0, 20, 21, 0, 0, 22, 22, 23, 23, 24, 24, 25}; - ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo)); - ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi)); - // return ArrCodes[BankEnc]; - *LowBit = ArrCodesLo[BankEnc]; - *HiBit = ArrCodesHi[BankEnc]; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines if the checksum is correct - * - * @param[in] *SPDPtr - Pointer to SPD data - * - * @return TRUE - CRC check passes - * @return FALSE - CRC check fails - */ - -BOOLEAN -STATIC -MemTCRCCheck3 ( - IN OUT UINT8 *SPDPtr - ) -{ - UINT16 Crc; - INT16 i; - INT16 j; - INT16 Count; - - if (SPDPtr[SPD_TYPE] == JED_DDR3SDRAM) { - Count = (SPDPtr[SPD_BYTE_USED] & 0x80) ? 117 : 126; - Crc = 0; - for (j = 0; j < Count; j++) { - Crc = Crc ^ ((UINT16)SPDPtr[j] << 8); - for (i = 0; i < 8; i++) { - if (Crc & 0x8000) { - Crc = (Crc << 1) ^ 0x1021; - } else { - Crc = (Crc << 1); - } - } - } - if (*(UINT16 *) (SPDPtr + 126) == Crc) { - return TRUE; - } - } - - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed). - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return CAS Latency - */ - -UINT8 -STATIC -MemTSPDGetTCL3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 *SpdBufferPtr = NULL; - UINT8 CLdesired; - UINT8 CLactual; - UINT8 Dimm; - UINT8 Channel; - UINT16 CASLat; - UINT16 Mask16; - INT32 MTB_ps; - INT32 FTB_ps; - INT32 TAAmin_ps; - INT32 TCKproposed_ps; - INT32 Value32; - BOOLEAN CltFail; - MEM_NB_BLOCK *NBPtr; - DCT_STRUCT *DCTPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - DCTPtr = NBPtr->DCTPtr; - - CASLat = 0xFFFF; - TAAmin_ps = 0; - CltFail = FALSE; - - for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) { - NBPtr->SwitchChannel (NBPtr, Channel); - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) { - MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm); - - // Step 1: Determine the common set of supported CAS Latency - // values for all modules on the memory Channel using the CAS - // Latencies Supported in SPD bytes 14 and 15. - // - CASLat &= ((UINT16)SpdBufferPtr[SPD_CASHI] << 8) | SpdBufferPtr[SPD_CASLO]; - - // Step 2: Determine tAAmin(all) which is the largest tAAmin - // value for all modules on the memory Channel (SPD byte 16). - // - MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR]; - FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF); - Value32 = (MTB_ps * SpdBufferPtr[SPD_TAA]) + (FTB_ps * (INT8) SpdBufferPtr[SPD_TAA_FTB]) ; - if (TAAmin_ps < Value32) { - TAAmin_ps = Value32; - } - - // Step 3: Determine tCKmin(all) which is the largest tCKmin - // value for all modules on the memory Channel (SPD byte 12). - // * This step has been done in SPDGetTargetSpeed - } - } - } - - TCKproposed_ps = 1000500 / DCTPtr->Timings.Speed; - - // Step 4: For a proposed tCK value (tCKproposed) between tCKmin(all) and tCKmax, - // determine the desired CAS Latency. If tCKproposed is not a standard JEDEC - // value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the - // next lower standard tCK value for calculating CLdesired. - // CLdesired = ceiling ( tAAmin(all) / tCKproposed ) - // where tAAmin is defined in Byte 16. The ceiling function requires that the - // quotient be rounded up always. - // - CLdesired = (UINT8) ((TAAmin_ps + TCKproposed_ps - 1) / TCKproposed_ps); - - // Step 5: Choose an actual CAS Latency (CLactual) that is greater than or equal - // to CLdesired and is supported by all modules on the memory Channel as - // determined in step 1. If no such value exists, choose a higher tCKproposed - // value and repeat steps 4 and 5 until a solution is found. - // - CLactual = 4; - for (Mask16 = 1; Mask16 < 0x8000; Mask16 <<= 1) { - if (CASLat & Mask16) { - if (CLdesired <= CLactual) { - break; - } - } - CLactual++; - } - if (Mask16 == 0x8000) { - CltFail = TRUE; - } - - // Step 6: Once the calculation of CLactual is completed, the BIOS must also - // verify that this CAS Latency value does not exceed tAAmax, which is 20 ns - // for all DDR3 speed grades, by multiplying CLactual times tCKproposed. If - // not, choose a lower CL value and repeat steps 5 and 6 until a solution is found. - // - if ((TCKproposed_ps * CLactual) > 20000) { - CltFail = TRUE; - } - - if (!CltFail) { - DCTPtr->Timings.CasL = CLactual; - } else { - // Fail to find supported Tcl, use 6 clocks since it is required for all DDR3 speed bin. - DCTPtr->Timings.CasL = 6; - } - - return DCTPtr->Timings.CasL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the encoded value of bank address. - * - * @param[in] Encode - RRRBCC, where CC is the number of Columns minus 9, - * RRR is the number of Rows minus 12, and B is the number of banks - * minus 3. - * @param[out] *Index - index in bank address table - * @return TRUE - encoded value is found. - * FALSE - encoded value is not found. - */ - -BOOLEAN -STATIC -MemTCheckBankAddr3 ( - IN UINT8 Encode, - OUT UINT8 *Index - ) -{ - UINT8 i; - CONST UINT8 TabBankAddr[] = { - 0x3F, 0x01, 0x09, 0x3F, 0x3F, 0x11, - 0x0A, 0x19, 0x12, 0x1A, 0x21, 0x22 - }; - - for (i = 0; i < GET_SIZE_OF (TabBankAddr); i++) { - if (Encode == TabBankAddr[i]) { - *Index = i; - return TRUE; - } - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns a pointer to the SPD Buffer of a specific dimm on - * the current channel. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer - * @param[in] Dimm - Dimm number - * - * - * @return BOOLEAN - Value of DimmPresent - * TRUE = Dimm is present, pointer is valid - * FALSE = Dimm is not present, pointer has not been modified. - */ - -BOOLEAN -MemTGetDimmSpdBuffer3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 **SpdBuffer, - IN UINT8 Dimm - ) -{ - CH_DEF_STRUCT *ChannelPtr; - SPD_DEF_STRUCT *SPDPtr; - BOOLEAN DimmPresent; - - DimmPresent = FALSE; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) - SPDPtr = ChannelPtr->DimmSpdPtr[Dimm]; - - - if (SPDPtr != NULL) { - DimmPresent = SPDPtr->DimmPresent; - if (DimmPresent) { - *SpdBuffer = SPDPtr->Data; - } - } - return DimmPresent; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.h deleted file mode 100644 index 5ada01f0dd..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.h +++ /dev/null @@ -1,175 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtspd3.h - * - * Technology SPD support for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTSPD3_H_ -#define _MTSPD3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*=============================================================================== - * Jedec DDR III - *=============================================================================== - */ -#define SPD_BYTE_USED 0 -#define SPD_TYPE 2 /* SPD byte read location */ -#define JED_DDR_SDRAM 7 /* Jedec defined bit field */ -#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */ -#define JED_DDR3SDRAM 0xB /* Jedec defined bit field */ - -#define SPD_DIMM_TYPE 3 -#define SPD_ATTRIB 21 -#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */ -#define JED_RDIMM 1 -#define JED_MINIRDIMM 5 -#define JED_UDIMM 2 -#define JED_SODIMM 3 -#define JED_LRDIMM 0xB -#define JED_UNDEFINED 0 /* Undefined value */ - -#define SPD_L_BANKS 4 /* [7:4] number of [logical] banks on each device */ -#define SPD_DENSITY 4 /* bit 3:0 */ -#define SPD_ROW_SZ 5 /* bit 5:3 */ -#define SPD_COL_SZ 5 /* bit 2:0 */ -#define SPD_RANKS 7 /* bit 5:3 */ -#define SPD_DEV_WIDTH 7 /* bit 2:0 */ -#define SPD_ECCBITS 8 /* bit 4:3 */ -#define JED_ECC 8 -#define SPD_RAWCARD 62 /* bit 2:0 */ -#define SPD_ADDRMAP 63 /* bit 0 */ - -#define SPD_CTLWRD03 70 /* bit 7:4 */ -#define SPD_CTLWRD04 71 /* bit 3:0 */ -#define SPD_CTLWRD05 71 /* bit 7:4 */ - -#define SPD_FTB 9 - -#define SPD_DIVIDENT 10 -#define SPD_DIVISOR 11 - -#define SPD_TCK 12 -#define SPD_CASLO 14 -#define SPD_CASHI 15 -#define SPD_TAA 16 - -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 -#define SPD_TWR 17 -#define SPD_TWTR 26 -#define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ -#define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ - -#define SPD_TCK_FTB 34 -#define SPD_TAA_FTB 35 -#define SPD_TRCD_FTB 36 -#define SPD_TRP_FTB 37 -#define SPD_TRC_FTB 38 - -/*----------------------------- - * Jedec DDR II related equates - *----------------------------- - */ - -#define CL_DEF 4 /* Default value for failsafe operation. 4=CL 6.0 T */ -#define T_DEF 4 /* Default value for failsafe operation. 4=2.5ns (cycle time) */ - -#define BIAS_TRTP_T 4 -#define BIAS_TRCD_T 5 -#define BIAS_TRAS_T 15 -#define BIAS_TRC_T 11 -#define BIAS_TRRD_T 4 -#define BIAS_TWR_T 4 -#define BIAS_TRP_T 5 -#define BIAS_TWTR_T 4 -#define BIAS_TFAW_T 14 - -#define MIN_TRTP_T 4 -#define MAX_TRTP_T 7 -#define MIN_TRCD_T 5 -#define MAX_TRCD_T 12 -#define MIN_TRAS_T 15 -#define MAX_TRAS_T 30 -#define MIN_TRC_T 11 -#define MAX_TRC_T 42 -#define MIN_TRRD_T 4 -#define MAX_TRRD_T 7 -#define MIN_TWR_T 5 -#define MAX_TWR_T 12 -#define MIN_TRP_T 5 -#define MAX_TRP_T 12 -#define MIN_TWTR_T 4 -#define MAX_TWTR_T 7 -#define MIN_TFAW_T 16 -#define MAX_TFAW_T 32 - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - - -#endif /* _MTSPD3_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttecc3.c deleted file mode 100644 index 2bc3f3773b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttecc3.c +++ /dev/null @@ -1,164 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttecc3.c - * - * Technology ECC byte support for registered DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_DDR3_MTTECC3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the DQS ECC timings for registered DDR3 - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTSetDQSEccTmgsRDdr3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - UINT8 Dimm; - UINT8 i; - UINT8 *WrDqsDly; - UINT16 *RcvEnDly; - UINT8 *RdDqsDly; - UINT8 *WrDatDly; - UINT8 EccByte; - INT16 TempValue; - - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - EccByte = TechPtr->MaxByteLanes (); - NBPtr = TechPtr->NBPtr; - - if (NBPtr->MCTPtr->NodeMemSize) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm * 2))) { - i = Dimm * TechPtr->DlyTableWidth (); - WrDqsDly = &ChannelPtr->WrDqsDlys[i]; - RcvEnDly = &ChannelPtr->RcvEnDlys[i]; - RdDqsDly = &ChannelPtr->RdDqsDlys[i]; - WrDatDly = &ChannelPtr->WrDatDlys[i]; - // Receiver DQS Enable: - // Receiver DQS enable for ECC bytelane = Receiver DQS enable for bytelane 3 - - // [write DQS for bytelane 3 - write DQS for ECC] - - TempValue = (INT16) RcvEnDly[3] - (INT16) (WrDqsDly[3] - WrDqsDly[EccByte]); - if (TempValue < 0) { - TempValue = 0; - } - RcvEnDly[EccByte] = (UINT16) TempValue; - - // Read DQS: - // Read DQS for ECC bytelane = read DQS of byte lane 3 - // - RdDqsDly[EccByte] = RdDqsDly[3]; - - // Write Data: - // Write Data for ECC bytelane = Write DQS for ECC + - // [write data for bytelane 3 - Write DQS for bytelane 3] - TempValue = (INT16) (WrDqsDly[EccByte] + (INT8) (WrDatDly[3] - WrDqsDly[3])); - if (TempValue < 0) { - TempValue = 0; - } - WrDatDly[EccByte] = (UINT8) TempValue; - - NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RcvEnDly[EccByte]); - NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RdDqsDly[EccByte]); - NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, EccByte), WrDatDly[EccByte]); - } - } - } - } - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttwl3.c deleted file mode 100644 index f98956f04e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mttwl3.c +++ /dev/null @@ -1,719 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttwl3.c - * - * Technology Phy assisted write levelization for DDR3 - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech/DDR3) - * @e \$Revision: 57883 $ @e \$Date: 2011-08-15 10:41:06 -0600 (Mon, 15 Aug 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mp.h" -#include "mtsdi3.h" -#include "mtlrdimm3.h" -#include "merrhdl.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_DDR3_MTTWL3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[]; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemTWriteLevelizationHw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ); - -VOID -STATIC -MemTWLPerDimmHw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Pass - ); - -VOID -STATIC -MemTPrepareDIMMs3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 TargetDIMM, - IN BOOLEAN Wl - ); - -VOID -STATIC -MemTProcConfig3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Pass - ); - -VOID -STATIC -MemTBeginWLTrain3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes first pass of Phy assisted write levelization - * for a specific node (DDR800). - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTWriteLevelizationHw3Pass1 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return MemTWriteLevelizationHw3 (TechPtr, 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes second pass of Phy assisted write levelization - * for a specific node (DDR1066 and above). - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTWriteLevelizationHw3Pass2 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - // If current speed is higher than start-up speed, do second pass of WL - if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) { - return MemTWriteLevelizationHw3 (TechPtr, 2); - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function prepares for Phy assisted training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTPreparePhyAssistedTraining ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - // Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1. - TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisAutoRefresh, 1); - // Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b. - TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFZqcsInterval, 0); - // Attempt to get the seeds value from PSC tables for WL and RxEn pass1 training if applicable. - if (!TechPtr->NBPtr->PsPtr->MemPGetPass1Seeds (TechPtr->NBPtr)) { - ASSERT (FALSE); - } - - return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function revert to normal settings when exiting from Phy assisted training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTExitPhyAssistedTraining ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - NBPtr = TechPtr->NBPtr; - - // 13.Program F2x[1, 0]8C[DisAutoRefresh] = 0. - NBPtr->BrdcstSet (NBPtr, BFDisAutoRefresh, 0); - // 14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration. - NBPtr->BrdcstSet (NBPtr, BFZqcsInterval, 2); - NBPtr->FamilySpecificHook[ExitPhyAssistedTraining] (NBPtr, NBPtr); - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executed hardware based write levelization for a specific die - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz)) - * - * @pre Auto refresh and ZQCL must be disabled - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -STATIC -MemTWriteLevelizationHw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ) -{ - MEM_NB_BLOCK *NBPtr; - DCT_STRUCT *DCTPtr; - UINT8 Dct; - UINT8 Dimm; - - NBPtr = TechPtr->NBPtr; - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart write leveling\n"); - AGESA_TESTPOINT (TpProcMemWriteLevelizationTraining, &(NBPtr->MemPtr->StdHeader)); - // Begin DQS Write timing training - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - DCTPtr = NBPtr->DCTPtr; - - TechPtr->WLCriticalDelay = 0x00; - - //training for each Dimm - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) { - if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << Dimm)) != 0)) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Dimm << 1); - MemTWLPerDimmHw3 (TechPtr, Dimm, Pass); - } - } - } - - NBPtr->FamilySpecificHook[CalcWrDqDqsEarly] (NBPtr, NULL); - } - IDS_HDT_CONSOLE (MEM_FLOW, "End write leveling\n\n"); - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes per DIMM write levelization - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dimm - DIMM to be trained - * @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz)) - * - */ - -VOID -STATIC -MemTWLPerDimmHw3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Pass - ) -{ - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - ASSERT (Dimm < MAX_DIMMS_PER_CHANNEL); - - // 1. A. Specify the target Dimm that is to be trained by programming - // F2x[1, 0]9C_x08[TrDimmSel]. - NBPtr->SetBitField (NBPtr, BFTrDimmSel, Dimm); - - TechPtr->TargetDIMM = Dimm; - NBPtr->FamilySpecificHook[InitPerNibbleTrn] (NBPtr, NULL); - for (TechPtr->TrnNibble = NIBBLE_0; TechPtr->TrnNibble <= (NBPtr->FamilySpecificHook[TrainWlPerNibble] (NBPtr, &Dimm)? NIBBLE_0 : NIBBLE_1); TechPtr->TrnNibble++) { - // 2. Prepare the DIMMs for write levelization using DDR3-defined - // MR commands. - MemTPrepareDIMMs3 (TechPtr, Dimm, TRUE); - - // 3. After the DIMMs are configured, BIOS waits 40 MEMCLKs to - // satisfy DDR3-defined internal DRAM timing. - NBPtr->WaitXMemClks (NBPtr, 40); - - // 4. Configure the processor's DDR phy for write levelization training: - MemTProcConfig3 (TechPtr, Dimm, Pass); - - // 5. Begin write levelization training - MemTBeginWLTrain3 (TechPtr, Dimm); - } - // 7. Program the target Dimm back to normal operation - MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function prepares the DIMMS for Write Levelization - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] TargetDIMM - DIMM to be trained - * @param[in] Wl - Indicates if WL mode should be enabled - * - */ - -VOID -STATIC -MemTPrepareDIMMs3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 TargetDIMM, - IN BOOLEAN Wl - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 ChipSel; - - NBPtr = TechPtr->NBPtr; - - AGESA_TESTPOINT (TpProcMemWlPrepDimms, &(NBPtr->MemPtr->StdHeader)); - ASSERT (TargetDIMM < MAX_DIMMS_PER_CHANNEL); - TechPtr->TargetDIMM = TargetDIMM; - if (!(TechPtr->TechnologySpecificHook[WlTrainingPrepareLrdimm] (TechPtr, &Wl))) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) { - NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); - // Set MR1 to F2x7C[MrsAddress], F2x7C[MrsBank]=1 - MemTEMRS13 (TechPtr, Wl, TargetDIMM); - NBPtr->SendMrsCmd (NBPtr); - // Set MR2 to F2x7C[MrsAddress], F2x7C[MrsBank]=1 - MemTEMRS23 (TechPtr); - // Send command - NBPtr->SendMrsCmd (NBPtr); - } - } - if (Wl) { - // Program WrLvOdt for the Target DIMM (or CS) - NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[TargetDIMM]); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs seed values for Write Levelization - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dimm - DIMM to be trained - * @param[in] Pass - Pass for WL training (1 - 400Mhz or 2 - >400Mhz) - * - */ - -VOID -STATIC -MemTProcConfig3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Pass - ) -{ - DIE_STRUCT *MCTPtr; - CH_DEF_STRUCT *ChannelPtr; - MEM_NB_BLOCK *NBPtr; - UINT16 WrDqsDly; - // Memclk Delay incurred by register. - UINT8 MemClkRegDly; - UINT8 ByteLane; - UINT8 DefaultSeed; - UINT8 CurrentSeed; - UINT8 *Seed; - UINT8 RCW2; - UINT16 Speed; - INT16 WrDqsBias; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - AGESA_TESTPOINT (TpProcMemWlConfigDimms, &(NBPtr->MemPtr->StdHeader)); - RCW2 = ChannelPtr->CtrlWrd02[Dimm]; - Speed = TechPtr->NBPtr->DCTPtr->Timings.Speed; - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeeds: "); - // Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set - // the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz, - // BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency, - // use an initial total delay value. - if (Pass == 1) { - // - // Get the default value of seed - // - if (MCTPtr->Status[SbRegistered]) { - // - // RDIMM - // - if (Speed == DDR667_FREQUENCY) { - DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x3B : 0x4B; - } else { - DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x41 : 0x51; - } - } else if (ChannelPtr->SODimmPresent != 0) { - // - // SODIMMM - // - DefaultSeed = 0x12; - } else if (MCTPtr->Status[SbLrdimms]) { - // - // LRDIMM - // - DefaultSeed = 0xF7; - } else { - // - // UDIMMM - // - DefaultSeed = 0x1A; - } - - NBPtr->FamilySpecificHook[OverrideWLSeed] (NBPtr, &DefaultSeed); - ASSERT (Speed >= DDR667_FREQUENCY); - - // Get platform override seed - Seed = (UINT8 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID, Dimm, - &(NBPtr->MCTPtr->LogicalCpuid), &(NBPtr->MemPtr->StdHeader)); - for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) { - // This includes ECC as byte 8 - CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed); - ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = CurrentSeed; - - if (NBPtr->IsSupported[WLSeedAdjust]) { - if ((CurrentSeed & 0x20) != 0) { - // If (SeedGross is odd) then SeedPreGross = 1 - CurrentSeed = (CurrentSeed & 0x1F) | 0x20; - } else { - // If (SeedGross is even) then SeedPreGross = 2 - CurrentSeed = (CurrentSeed & 0x1F) | 0x40; - } - } - - NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed); - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", CurrentSeed); - } - } else { - //10.Multiply the previously saved delay values in Pass 1, step #5 by (target frequency)/400 to find - //the gross and fine delay initialization values at the target frequency. Use these values as the initial - //seed values when executing Pass 2, step #4. - for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) { - // This includes ECC as byte 8 - WrDqsDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane]; - TechPtr->Bytelane = ByteLane; - NBPtr->FamilySpecificHook[TrainWlPerNibbleSeed] (NBPtr, &WrDqsDly); - - if (MCTPtr->Status[SbRegistered]) { - // - // For Registered Dimms - // - MemClkRegDly = ((RCW2 & BIT0) == 0) ? 0x20 : 0x30; - } else { - // - // Unbuffered Dimms and LRDIMMs - // - MemClkRegDly = 0; - } - // - // Recover any adjustmen to delay for WrDqDqsEarly - // - WrDqsBias = 0; - NBPtr->FamilySpecificHook[AdjustWrDqsBeforeSeedScaling] (NBPtr, &WrDqsBias); - - // Scale WrDqsDly to the next speed - WrDqsDly = (UINT16) (MemClkRegDly + ((((INT32) WrDqsDly - MemClkRegDly - WrDqsBias) * Speed) / TechPtr->PrevSpeed)); - - ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = (UINT8) WrDqsDly; - - if (NBPtr->IsSupported[WLSeedAdjust]) { - if ((WrDqsDly & 0x20) != 0) { - // If (SeedGross is odd) then SeedPreGross = 1 - WrDqsDly = (WrDqsDly & 0x1F) | 0x20; - } else { - // If (SeedGross is even) then SeedPreGross = 2 - WrDqsDly = (WrDqsDly & 0x1F) | 0x40; - } - } - NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDly); - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", WrDqsDly); - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function begins WL training for a specific DIMM - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dimm - DIMM to be trained - * - */ - -VOID -STATIC -MemTBeginWLTrain3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm - ) -{ - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - MEM_NB_BLOCK *NBPtr; - UINT8 ByteLane; - UINT8 Seed; - UINT8 Delay; - INT16 Delay16; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - - AGESA_TESTPOINT (TpProcMemWlTrainTargetDimm, &(MemPtr->StdHeader)); - // Assert ODT pins for write leveling - NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 1); - - // Wait 10 MEMCLKs to allow for ODT signal settling. - NBPtr->WaitXMemClks (NBPtr, 10); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrtLvTrEn = 1\n"); - // Program F2x[1, 0]9C_x08[WrtLlTrEn]=1. - NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1); - - // Wait 200 MEMCLKs. - NBPtr->WaitXMemClks (NBPtr, 200); - - // Program F2x[1, 0]9C_x08[WrtLlTrEn]=0. - NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 0); - - // Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings - // for the target Dimm and save these values. - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t PRE: "); - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - // This includes ECC as byte 8 - Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane]; - Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane)); - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", Delay); - - TechPtr->Bytelane = ByteLane; - TechPtr->TargetDIMM = Dimm; - NBPtr->FamilySpecificHook[TrainWlPerNibbleAdjustWLDly] (NBPtr, &Delay); - - if (NBPtr->IsSupported[WLSeedAdjust]) { - // Recover WrDqsGrossDly: - // WrDqsGrossDly = SeedGross + PhRecGrossDlyByte - SeedPreGross - if ((Seed & 0x20) != 0) { - // If (SeedGross is odd) then SeedPreGross = 1 - if ((NBPtr->IsSupported[WLNegativeDelay]) && ((Seed & 0x80) != 0)) { - // If the seed was negative, save the most negative delay in WLCriticalDelay - TechPtr->WLCriticalDelay = MIN (TechPtr->WLCriticalDelay, (INT16)Delay - 0x40); - Delay -= 0x40; - } else { - Delay += (Seed & 0xE0) - 0x20; - } - } else { - // If (SeedGross is even) then SeedPreGross = 2 - if (((Seed & 0xE0) == 0) && (Delay < 0x40)) { - // If SeedGross is 0 and PhRecGrossDlyByte is less than SeedPreGross, - // we have a negative result and need to program the delay to 0 - if (NBPtr->IsSupported[WLNegativeDelay]) { - // - // Save the lowest negative delay value across all Dimms and Bytelanes - // - TechPtr->WLCriticalDelay = MIN (TechPtr->WLCriticalDelay, (INT16)Delay - 0x40); - Delay -= 0x40; - } else { - Delay = 0; - } - } else { - if (NBPtr->GetBitField (NBPtr, BFWrDqDqsEarly) != 0) { - Delay = Delay + (Seed & 0xE0); - Delay16 = Delay - 0x40; - Delay = (UINT8)Delay16; - TechPtr->WLCriticalDelay = MIN (TechPtr->WLCriticalDelay, Delay16); - } else { - Delay += (Seed & 0xE0) - 0x40; - } - } - } - } else if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) { - IDS_OPTION_HOOK (IDS_CHECK_NEGATIVE_WL, &Delay, &(TechPtr->NBPtr->MemPtr->StdHeader)); - // If seed has gross delay of 0 and PRE has gross delay of 3, - // then round the total delay of TxDqs to 0. - Delay = 0; - } - - if ((!NBPtr->IsSupported[WLNegativeDelay]) && ((Delay > (Seed + 0x20)) || (Seed > (Delay + 0x20)))) { - // - // If PRE comes back with more than Seed +/- 0x20, then this is an - // unexpected condition. Log the condition. - // - PutEventLog (AGESA_ERROR, MEM_ERROR_WL_PRE_OUT_OF_RANGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ((Seed << 8) + Delay), &NBPtr->MemPtr->StdHeader); - } - NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay); - NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane] = Delay; - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrDqs: "); - for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); - ); - - // Disable write leveling ODT pins - NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 0); - - // Wait 10 MEMCLKs to allow for ODT signal settling. - NBPtr->WaitXMemClks (NBPtr, 10); - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs register after Phy assisted training is finish. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTExitPhyAssistedTrainingClient3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 Dct; - UINT8 ChipSel; - NBPtr = TechPtr->NBPtr; - - NBPtr->FamilySpecificHook[ReEnablePhyComp] (NBPtr, NBPtr); - NBPtr->BrdcstSet (NBPtr, BFRxPtrInitReq, 1); - NBPtr->PollBitField (NBPtr, BFRxPtrInitReq, 0, PCI_ACCESS_TIMEOUT, TRUE); - NBPtr->BrdcstSet (NBPtr, BFDisDllShutdownSR, 1); - NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1); - NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign = 2\n"); - NBPtr->BrdcstSet (NBPtr, BFDbeGskMemClkAlignMode, 2); - NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1); - NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); - if (NBPtr->IsSupported[SetDllShutDown]) { - NBPtr->BrdcstSet (NBPtr, BFDisDllShutdownSR, 0); - } - - // Calculate Max Latency for both channels to prepare for position training - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) { - NBPtr->SetMaxLatency (NBPtr, TechPtr->MaxDlyForMaxRdLat); - } - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/Makefile.inc deleted file mode 100644 index fa6a130a16..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -libagesa-y += mt.c -libagesa-y += mthdi.c -libagesa-y += mttEdgeDetect.c -libagesa-y += mttdimbt.c -libagesa-y += mttecc.c -libagesa-y += mtthrc.c -libagesa-y += mtthrcSeedTrain.c -libagesa-y += mttml.c -libagesa-y += mttoptsrc.c -libagesa-y += mttsrc.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mt.c deleted file mode 100644 index de4a32f54a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mt.c +++ /dev/null @@ -1,263 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mt.c - * - * Common Technology file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "amdlib.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_MT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemTDefaultTechnologyHook ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the default return for non-training technology features - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - */ -BOOLEAN -MemTFeatDef ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the TestFail bit for all CS that fail training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - */ -VOID -MemTMarkTrainFail ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 Dct; - UINT8 ChipSel; - - NBPtr = TechPtr->NBPtr; - for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) { - NBPtr->SwitchDCT (NBPtr, Dct); - NBPtr->DCTPtr->Timings.CsEnabled &= ~NBPtr->DCTPtr->Timings.CsTrainFail; - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel ++) { - if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << ChipSel)) != 0) { - NBPtr->SetBitField (NBPtr, (BFCSBaseAddr0Reg + ChipSel), (UINT32)1 << BFTestFail); - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the initial controller environment before training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTBeginTraining ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - S_UINT64 SMsr; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg); - LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32)1 << 9)); // enable SSE2 - - LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); // HWCR - TechPtr->HwcrLo = SMsr.lo; - SMsr.lo |= 0x00020000; // turn on HWCR.wrap32dis - SMsr.lo &= 0xFFFF7FFF; // turn off HWCR.SSEDIS - LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); - - TechPtr->DramEcc = (UINT8) NBPtr->GetBitField (NBPtr, BFDramEccEn); - NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the final controller environment after training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTEndTraining ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - S_UINT64 SMsr; - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - - LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg); - - LibAmdMsrRead (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.lo = TechPtr->HwcrLo; - LibAmdMsrWrite (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets all the bytelanes/nibbles to the same delay value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dly - Delay value to set - * - */ - -VOID -MemTSetDQSDelayAllCSR ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dly - ) -{ - UINT8 i; - UINT8 MaxBytelanes; - MaxBytelanes = (TechPtr->NBPtr->MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8; - - for (i = 0; i < MaxBytelanes; i++) { - TechPtr->SetDQSDelayCSR (TechPtr, i, Dly); - } - TechPtr->NBPtr->FamilySpecificHook[RegAccessFence] (TechPtr->NBPtr, NULL); -} -/*----------------------------------------------------------------------------- - * - * - * This function is used to intialize common technology functions - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * ---------------------------------------------------------------------------- - */ -VOID -MemTCommonTechInit ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 i; - for (i = 0; i < NumberOfTechHooks; i++) { - TechPtr->TechnologySpecificHook[i] = MemTDefaultTechnologyHook; - } -} -/*----------------------------------------------------------------------------- - * - * - * This function is an empty function used to intialize TechnologySpecificHook array - * - * @param[in,out] *TechPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return FALSE - always - * ---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemTDefaultTechnologyHook ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - return FALSE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mthdi.c deleted file mode 100644 index 51081ed948..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mthdi.c +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mthdi.c - * - * Common technology hardware dram init support functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_MTHDI_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates Hardware based dram initialization for both DCTs - * at the same time. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTDramInitHw ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - - NBPtr->BrdcstSet (NBPtr, BFInitDram, 1); - // Phy fence training - AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->PhyFenceTraining (NBPtr); - } - } -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c deleted file mode 100644 index d78a3fcfdf..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c +++ /dev/null @@ -1,916 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttEdgeDetect.c - * - * DQS R/W position training utilizing Data Eye Edge Detection for optimization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 57884 $ @e \$Date: 2011-08-15 10:42:12 -0600 (Mon, 15 Aug 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - - - -#include "AGESA.h" -#include "amdlib.h" -#include "AdvancedApi.h" -#include "GeneralServices.h" -#include "Ids.h" -#include "heapManager.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "mport.h" -#include "mttEdgeDetect.h" -#include "OptionMemory.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G1_PEICC) - -#define FILECODE PROC_MEM_TECH_MTTEDGEDETECT_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -#define LAST_DELAY (-128) -#define INC_DELAY 1 -#define DEC_DELAY 0 - - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/** - * Sweep Table For Byte Training without insertion delay - * -*/ -DQS_POS_SWEEP_TABLE SweepTableByte[] = -{ - // Begin End Inc/Dec Step EndResult Edge - { 0x00, 0x1F, INC_DELAY, 4, 0xFFFF, LEFT_EDGE}, /// For Left Edge, start from 0 and Increment to 0x1F by 4 until all PASS - { LAST_DELAY, 0x00, DEC_DELAY, -1, 0xFE00, LEFT_EDGE}, /// Then go back down to 0x00 by 1 until all FAIL - { 0x1F, 0x00, DEC_DELAY, -4, 0xFFFF, RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS. - { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFE00, RIGHT_EDGE} /// Then go back up by 1 until all FAIL. -}; -/** - * Sweep Table For Byte Training with insertion delay - * -*/ -DQS_POS_SWEEP_TABLE InsSweepTableByte[] = -{ - // Begin End Inc/Dec Step EndResult Edge - { 0x00, -0x20, DEC_DELAY, -4, 0xFE00, LEFT_EDGE}, /// For Left Edge, start from 0 and Decrement to -0x20 by -4 until all FAIL - { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFFFF, LEFT_EDGE}, /// Then go back up to 0x1F by 1 until all PASS - { 0x1F, 0x00, DEC_DELAY, -4, 0xFFFF, RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS. - { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFE00, RIGHT_EDGE} /// Then go back up by 1 until all FAIL. -}; - -BOOLEAN -STATIC -MemTTrainDQSRdWrEdgeDetect ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -BOOLEAN -STATIC -MemTInitTestPatternAddress ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ); - -BOOLEAN -STATIC -MemTContinueSweep ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ); - -BOOLEAN -STATIC -MemTSetNextDelay ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ); - -UINT8 -STATIC -MemTScaleDelayVal ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN INT8 Delay - ); - -BOOLEAN -STATIC -MemTDataEyeSave ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr, - IN UINT8 ByteLane - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[]; -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes DQS position training for all a Memory channel using - * the Edge Detection algorithm. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -BOOLEAN -MemTTrainDQSEdgeDetectSw ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - BOOLEAN Status; - - Status = FALSE; - NBPtr = TechPtr->NBPtr; - TechPtr->TrainingType = TRN_DQS_POSITION; - // - // Initialize the Pattern - // - if (AGESA_SUCCESS == NBPtr->TrainingPatternInit (NBPtr)) { - // - // Setup hardware training engine (if applicable) - // - NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType); - // - // Start Edge Detection - // - Status |= MemTTrainDQSRdWrEdgeDetect (TechPtr); - // - // Finalize the Pattern - // - Status &= (AGESA_SUCCESS == NBPtr->TrainingPatternFinalize (NBPtr)); - } - return Status; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This Executes Read DQS and Write Data Position training on a chip select pair - * using the Edge Detection algorithm. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No Errors occurred - * @return FALSE - Errors occurred - - */ - -BOOLEAN -STATIC -MemTTrainDQSRdWrEdgeDetect ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - MEM_NB_BLOCK *NBPtr; - UINT8 WrDqDelay; - UINT8 Dct; - UINT8 CSPerChannel; - UINT8 CsPerDelay; - UINT8 ChipSel; - UINT8 i; - BOOLEAN Status; - UINT8 TimesFail; - UINT8 TimesRetrain; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - TimesRetrain = DEFAULT_TRAINING_TIMES; - IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); - // - // Set environment settings before training - // - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Read/Write Data Eye Edge Detection.\n"); - MemTBeginTraining (TechPtr); - // - // Do Rd DQS /Wr Data Position training for all Dcts/Chipselects - // - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - // - // Chip Select Loop - // - CSPerChannel = NBPtr->CSPerChannel (NBPtr); - CsPerDelay = NBPtr->CSPerDelay (NBPtr); - for (ChipSel = 0; ChipSel < CSPerChannel; ChipSel = ChipSel + CsPerDelay ) { - // - // Init Bit Error Masks - // - LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ], - 0xFF, - (MAX_BYTELANES_PER_CHANNEL * CsPerDelay), - &MemPtr->StdHeader); - if ( (NBPtr->MCTPtr->Status[SbLrdimms]) ? ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0) : - ((NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16) 1 << ChipSel)) != 0) ) { - - TechPtr->ChipSel = ChipSel; - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tIncrease WrDat, Train RdDqs:\n"); - - TechPtr->DqsRdWrPosSaved = 0; - // - // Use a list of Approximate Write Data delay values and train Read DQS Position for - // each until a valid Data eye is found. - // - Status = FALSE; - TimesFail = 0; - NBPtr->FamilySpecificHook[InitializeRxEnSeedlessTraining] (NBPtr, NBPtr); - ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) { - i = 0; - while (NBPtr->GetApproximateWriteDatDelay (NBPtr, i, &WrDqDelay)) { - TechPtr->SmallDqsPosWindow = FALSE; - // - // Set Write Delay approximation - // - TechPtr->Direction = DQS_WRITE_DIR; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrite Delay: %02x", WrDqDelay); - MemTSetDQSDelayAllCSR (TechPtr, WrDqDelay); - // - // Attempt Read Training - // - TechPtr->Direction = DQS_READ_DIR; - Status = memTrainSequenceDDR3[NBPtr->TrainingSequenceIndex].MemTechFeatBlock->RdPosTraining (TechPtr); - if (Status) { - // - // If Read DQS Training was successful, Train Write Data (DQ) Position - // - TechPtr->DqsRdWrPosSaved = 0; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tTrain WrDat:\n\n"); - TechPtr->Direction = DQS_WRITE_DIR; - if (NBPtr->FamilySpecificHook[BeforeWrDatTrn] (NBPtr, &ChipSel)) { - Status = MemTTrainDQSEdgeDetect (TechPtr); - } - break; - } - i++; - } - ERROR_HANDLE_RETRAIN_END ((Status == FALSE), TimesFail) - } - - // - // If we went through the table, Fail. - // - if (Status == FALSE) { - // On training failure, check and record whether training fails due to small window or no window - if (TechPtr->SmallDqsPosWindow) { - NBPtr->MCTPtr->ErrStatus[EsbSmallDqs] = TRUE; - } else { - NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE; - } - - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (TechPtr->Direction == DQS_READ_DIR) { - PutEventLog (AGESA_ERROR, MEM_ERROR_NO_DQS_POS_RD_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - } else { - PutEventLog (AGESA_ERROR, MEM_ERROR_NO_DQS_POS_WR_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - } - NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ChipSel; - // If the even chip select failed training always fail the odd, if present. - if ((ChipSel & 0x01) == 0) { - if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << (ChipSel + 1))) { - NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << (ChipSel + 1); - } - } - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - } - } else { - // - // Clear Bit Error Masks if these CS will not be trained. - // - LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ], - 0x00, - (MAX_BYTELANES_PER_CHANNEL * CsPerDelay), - &NBPtr->MemPtr->StdHeader); - } - } - } - // - // Restore environment settings after training - // - MemTEndTraining (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "End Read/Write Data Eye Edge Detection\n\n"); - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes DQS position training for both read and write, using - * the Edge Detection Algorithm. This method searches for the beginning and end - * of the Data Eye with out scanning every DSQ delay value. The following is a - * detailed description of the algorithm: - * - * Four-Stage Data Eye Sweep - * - * -Search starts at Delay value of 0. - * -Search left in steps of 4/32UI looking for all Byte lanes Passing. Left from zero rolls over to a negative value. - * -Negative values are translated to the high end of the delay range, but using Insertion delay comparison. - * -For each passing byte lane, freeze delay at first passing value, but set mask so next steps will not compare for byte lanes that previously passed - * -Switch to search right in steps of 1/32UI looking for fail. - * -For each lane, starting delay for 1/32 sweep right is first passing delay from 4/32 sweep left. - * -For each failing byte lane, freeze delay at first failing value, but set mask so next steps will not compare for byte lanes that previously failed - * -Search right until all byte lanes have failed - * -For each lane, right edge used by BIOS will be first failing delay value minus 1/32 - - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - All bytelanes pass - * @return FALSE - Some bytelanes fail -*/ -BOOLEAN -MemTTrainDQSEdgeDetect ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - DIE_STRUCT *MCTPtr; - DQS_POS_SWEEP_TABLE *SweepTablePtr; - UINT8 SweepTableSize; - SWEEP_INFO SweepData; - BOOLEAN Status; - UINT16 CurrentResult; - UINT16 AlignedResult; - UINT16 OffsetResult; - UINT8 StageIndex; - UINT8 CsIndex; - UINT8 CsPerDelay; - UINT8 i; - - Status = TRUE; - // - // Initialize Object Pointers - // - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - // - // Initialize stack variables - // - LibAmdMemFill (&SweepData, 0, sizeof (SWEEP_INFO), &NBPtr->MemPtr->StdHeader); - // - /// Get Pointer to Sweep Table - // - if (TechPtr->Direction == DQS_READ_DIR) { - SweepTablePtr = InsSweepTableByte; - SweepTableSize = GET_SIZE_OF (InsSweepTableByte); - } else { - SweepTablePtr = SweepTableByte; - SweepTableSize = GET_SIZE_OF (SweepTableByte); - } - // - // Get number of CS to train - // - CsPerDelay = NBPtr->CSPerDelay (NBPtr); - // - /// Set up the test Pattern, exit if no Memory - // - if (MemTInitTestPatternAddress (TechPtr, &SweepData) == FALSE) { - LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (TechPtr->ChipSel * MAX_BYTELANES_PER_CHANNEL) ], - 0, - (MAX_BYTELANES_PER_CHANNEL * CsPerDelay), - &NBPtr->MemPtr->StdHeader); - return FALSE; - } - // - // Clear Error Flag - // - SweepData.Error = FALSE; - NBPtr->FamilySpecificHook[InitialzeRxEnSeedlessByteLaneError] (NBPtr, NBPtr); - // - /// Process Sweep table, using entries from the table to determine Starting and Ending Delays - /// as well as the Step size and criteria for evaluating whether the correct result is found. - /// - /// Delay values at this level are an abstract range of values which gets scaled to the actual value - /// before it is written to the hardware. This allows NB specific code to handle the scaling as a - /// function of frequency or other conditions. - // - for (StageIndex = 0; (StageIndex < SweepTableSize) && (SweepData.Error == FALSE); StageIndex++) { - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSTAGE: %d\t", StageIndex); - // - /// Initialize SweepData variables - // - SweepData.BeginDelay = SweepTablePtr->BeginDelay; - SweepData.EndDelay = SweepTablePtr->EndDelay; - SweepData.Step = 0; /// Step Value will be 0 to start. - SweepData.EndResult = SweepTablePtr->EndResult; - if (!(MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining])) { - SweepData.EndResult |= 0x0100; - } - SweepData.Edge = SweepTablePtr->MinMax; - SweepData.InsertionDelayMsk = 0; - SweepData.ResultFound = 0x0000; - // - // Set Training Delays Pointer. - // - if (TechPtr->Direction == DQS_READ_DIR) { - SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->RdDqsMaxDlys : NBPtr->ChannelPtr->RdDqsMinDlys); - } else { - SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->WrDatMaxDlys : NBPtr->ChannelPtr->WrDatMinDlys); - }; - // - /// Set initial TrnDelay Values if necessary - // - IDS_HDT_CONSOLE (MEM_FLOW, "Sweeping %s DQS, %s from ", (TechPtr->Direction == DQS_READ_DIR) ?"Read":"Write", (SweepTablePtr->ScanDir == INC_DELAY) ? "incrementing":"decrementing"); - if (SweepData.BeginDelay != LAST_DELAY) { - IDS_HDT_CONSOLE (MEM_FLOW, "%02x", (UINT16) MemTScaleDelayVal (TechPtr, SweepData.BeginDelay)); - for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); i++) { - SweepData.TrnDelays[i] = SweepData.BeginDelay; - } - } else { - IDS_HDT_CONSOLE (MEM_FLOW, "Current Delay"); - SweepData.Step = SweepTablePtr->Step; - } - IDS_HDT_CONSOLE (MEM_FLOW, " by %02x, until all bytelanes %s.\n\n", (UINT16) MemTScaleDelayVal (TechPtr, ABS (SweepTablePtr->Step)), (SweepData.EndResult == 0xFFFF)?"PASS":"FAIL"); - - //------------------------------------------------------------------- - // Sweep DQS Delays - // MemTContinueSweep function returns false to break out of loop. - // There are no other breaks out of this loop. - //------------------------------------------------------------------- - while (MemTContinueSweep (TechPtr, &SweepData)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tByte Lane : 08 07 06 05 04 03 02 01 00\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tDQS Delays : %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", - (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[8]), - (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[7]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[6]), - (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[5]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[4]), - (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[3]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[2]), - (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[1]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[0]) - ); - // - /// Set Step Value - // - SweepData.Step = SweepTablePtr->Step; - CurrentResult = 0xFFFF; - // - /// Chip Select Loop: Test the Pattern for all populated CS that are controlled by the current delay registers - // - for (CsIndex = 0; CsIndex < CsPerDelay ; CsIndex++, TechPtr->ChipSel++) { - ASSERT (CsIndex < MAX_CS_PER_CHANNEL); - ASSERT (TechPtr->ChipSel < MAX_CS_PER_CHANNEL); - if (SweepData.CsAddrValid[CsIndex] == TRUE) { - // - /// If this is a Write Dqs sweep, Write the pattern now. - // - if (TechPtr->Direction == DQS_WRITE_DIR) { - NBPtr->WritePattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength); - } - // - /// Read the Pattern Back - // - NBPtr->ReadPattern (NBPtr, TechPtr->TestBufPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength); - // - /// Compare the Pattern and Merge the results using InsertionDelayMsk - // - AlignedResult = NBPtr->CompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64); - CurrentResult &= AlignedResult | SweepData.InsertionDelayMsk; - if (SweepData.InsertionDelayMsk != 0) { - OffsetResult = NBPtr->InsDlyCompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64); - CurrentResult &= (OffsetResult | (~SweepData.InsertionDelayMsk)); - } - // - /// Flush the Test Pattern - // - NBPtr->FlushPattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength); - NBPtr->FamilySpecificHook[ResetRxFifoPtr] (NBPtr, NBPtr); - } - } /// End Chip Select Loop - TechPtr->ChipSel = TechPtr->ChipSel - CsIndex; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c \n", - (SweepData.ResultFound & ((UINT16) 1 << (8))) ? ' ':(CurrentResult & ((UINT16) 1 << (8))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (5))) ? ' ':(CurrentResult & ((UINT16) 1 << (5))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (4))) ? ' ':(CurrentResult & ((UINT16) 1 << (4))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (3))) ? ' ':(CurrentResult & ((UINT16) 1 << (3))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (2))) ? ' ':(CurrentResult & ((UINT16) 1 << (2))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (1))) ? ' ':(CurrentResult & ((UINT16) 1 << (1))) ? 'P':'.', - (SweepData.ResultFound & ((UINT16) 1 << (0))) ? ' ':(CurrentResult & ((UINT16) 1 << (0))) ? 'P':'.' - ); - // - /// Merge current result into cumulative result and make it positive. - // - SweepData.ResultFound |= ~(CurrentResult ^ SweepData.EndResult); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResultFound : %c %c %c %c %c %c %c %c %c \n\n", - (SweepData.ResultFound & ((UINT16) 1 << (8))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (7))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (6))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (5))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (4))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (3))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (2))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (1))) ? 'Y':' ', - (SweepData.ResultFound & ((UINT16) 1 << (0))) ? 'Y':' ' - ); - } /// End of Delay Sweep - // - /// Place Final delay values at last passing delay. - // - if (SweepData.ResultFound == 0xFFFF) { - if ( ABS (SweepData.Step) == 1) { - for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) { - if ((SweepData.EndResult & ((UINT16) (1 << i))) == 0) { - SweepData.TrnDelays[i] = SweepData.TrnDelays[i] - SweepData.Step; - } - } - } - } - // - // Update Pointer to Sweep Table - // - SweepTablePtr++; - }///End of Edge Detect loop - // - /// If No Errors are detected, Calculate Data Eye Width and Center - // - if (SweepData.Error == FALSE) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tData Eye Results:\n\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tByte Left Right\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tLane Edge Edge Width Center\n"); - for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t %0d", i); - TechPtr->Bytelane = i; - if (!MemTDataEyeSave (TechPtr, &SweepData, i)) { - break; - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - if (SweepData.Error == TRUE) { - Status = FALSE; - } - } - } else { - Status = FALSE; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t--DATA EYE NOT FOUND--\n\n"); - NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrNoWindBLError] (NBPtr, &SweepData); - } - return Status; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * Initialize the Test Pattern Address for two chip selects and, if this - * is a Write Data Eye, write the initial test pattern. - * - * Test Address is stored in the Sweep info struct. If Memory is not present - * then return with False. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. - * - * @return BOOLEAN - * TRUE - Memory is present - * FALSE - No memory present on this Chip Select pair. - * -** - */ -BOOLEAN -STATIC -MemTInitTestPatternAddress ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 ChipSel; - UINT8 CsPerDelay; - UINT8 CsIndex; - BOOLEAN BanksPresent; - - NBPtr = TechPtr->NBPtr; - BanksPresent = FALSE; - CsPerDelay = NBPtr->CSPerDelay (NBPtr); - ChipSel = TechPtr->ChipSel; - for (CsIndex = 0; CsIndex < CsPerDelay; ChipSel++, CsIndex++, TechPtr->ChipSel++) { - ASSERT (CsIndex < MAX_CS_PER_CHANNEL); - ASSERT (ChipSel < MAX_CS_PER_CHANNEL); - ASSERT (TechPtr->ChipSel < MAX_CS_PER_CHANNEL); - // - /// If memory is present on this cs, get the test addr - // - if (NBPtr->GetSysAddr (NBPtr, ChipSel, &(SweepPtr->TestAddrRJ16[CsIndex]))) { - if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0)) { - BanksPresent = TRUE; - SweepPtr->CsAddrValid[CsIndex] = TRUE; - // - /// If this is a Read Dqs sweep, Write the pattern now. - // - if (TechPtr->Direction == DQS_READ_DIR) { - IDS_HDT_CONSOLE (MEM_FLOW, "\tTestAddr: %x0000\n", SweepPtr->TestAddrRJ16[CsIndex]); - NBPtr->WritePattern (NBPtr, SweepPtr->TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength); - } - } - } else { - SweepPtr->CsAddrValid[CsIndex] = FALSE; - } - } /// End Chip Select Loop - TechPtr->ChipSel = TechPtr->ChipSel - CsIndex; - // - /// return FALSE if no ChipSelects present. - // - return BanksPresent; -} - -/* -----------------------------------------------------------------------------*/ -/** - * Test Conditions for exiting the training loop, set the next delay value, - * and return status - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. - * - * @return BOOLEAN - * TRUE - Continue to test with next delay setting - * FALSE - Exit training loop. Either the result has been found or - * end of delay range has been reached. -*/ -BOOLEAN -STATIC -MemTContinueSweep ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ) -{ - BOOLEAN Status; - Status = FALSE; - if (SweepPtr->ResultFound != 0xFFFF) { - Status = MemTSetNextDelay (TechPtr, SweepPtr); - } - TechPtr->NBPtr->FamilySpecificHook[RegAccessFence] (TechPtr->NBPtr, NULL); - return Status; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the next delay value for each bytelane that needs to - * be advanced. It checks the bounds of the delay to see if we are at the - * end of the range. If we are to close to advance a whole step value, but - * not at the boundary, then we set the delay to the boundary. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. - * - */ - -BOOLEAN -STATIC -MemTSetNextDelay ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr - ) -{ - DIE_STRUCT *MCTPtr; - UINT8 i; - - MCTPtr = TechPtr->NBPtr->MCTPtr; - // - ///< Loop through bytelanes - // - for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) { - // - /// Skip Bytelanes that have already reached the desired result - // - if ( (SweepPtr->ResultFound & ((UINT16)1 << i)) == 0) { - // - /// If a bytelane has reached the end, flag an error and exit - // - if (SweepPtr->TrnDelays[i] == SweepPtr->EndDelay) { - if ((SweepPtr->EndResult & ((UINT16) (1 << i))) != 0) { - MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE; - SweepPtr->Error = TRUE; - } - return FALSE; - } - // - /// If the Current delay value is less than a step away from EndDelay, - // - if ( ABS (SweepPtr->EndDelay - SweepPtr->TrnDelays[i]) < ABS (SweepPtr->Step)) { - /// set to EndDelay. - // - SweepPtr->TrnDelays[i] = SweepPtr->EndDelay; - } else { - // - /// Otherwise, add the step value to it - SweepPtr->TrnDelays[i] = SweepPtr->TrnDelays[i] + SweepPtr->Step; - } - // - /// Set InsertionDelayMsk bit if Delay < 0 for this bytelane - // - if (SweepPtr->TrnDelays[i] < 0) { - SweepPtr->InsertionDelayMsk |= ((UINT16) 1 << i); - } else { - SweepPtr->InsertionDelayMsk &= ~((UINT16) 1 << i); - } - // - /// Write the scaled value to the Delay Register - // - TechPtr->SetDQSDelayCSR (TechPtr, i, MemTScaleDelayVal (TechPtr, SweepPtr->TrnDelays[i])); - } - } - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function accepts a delay value in 32nd of a UI and converts it to an - * actual register value, taking into consideration NB type, rd/wr, - * and frequency. - * - * Delay = (Min + (Delay * ( (Max - Min) / TRN_DELAY_MAX) )) & Mask - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] *Delay - INT8 of delay value; - * - * @return UINT8 of the adjusted delay value -*/ -UINT8 -STATIC -MemTScaleDelayVal ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN INT8 Delay - ) -{ - MEM_NB_BLOCK *NBPtr; - TRN_DLY_PARMS Parms; - TRN_DLY_TYPE DelayType; - UINT8 NewDelay; - INT8 Factor; - INT8 ScaledDelay; - - NBPtr = TechPtr->NBPtr; - // - // Determine Delay Type, Get Delay Parameters, and return scaled Delay value - // - DelayType = (TechPtr->Direction == DQS_WRITE_DIR) ? AccessWrDatDly : AccessRdDqsDly; - NBPtr->GetTrainDlyParms (NBPtr, DelayType, &Parms); - Factor = ((Parms.Max - Parms.Min) / TRN_DELAY_MAX); - ScaledDelay = Delay * Factor; - NewDelay = (Parms.Min + ScaledDelay) & Parms.Mask; - return NewDelay; -} - - - - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the Center of the Data eye for the specified byte lane - * and stores its DQS Delay value for reference. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure. - * @param[in] ByteLane - Bytelane number being targeted - * - */ -BOOLEAN -STATIC -MemTDataEyeSave ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT SWEEP_INFO *SweepPtr, - IN UINT8 ByteLane - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT8 EyeCenter; - UINT8 DlyMin; - UINT8 DlyMax; - UINT8 EyeWidth; - UINT8 Dimm; - CH_DEF_STRUCT *ChanPtr; - - NBPtr = TechPtr->NBPtr; - ChanPtr = NBPtr->ChannelPtr; - - ASSERT (ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8)); - // - // Calculate Data Eye edges, Width, and Center in real terms. - // - if (TechPtr->Direction == DQS_READ_DIR) { - DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMinDlys[ByteLane]); - DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMaxDlys[ByteLane]); - EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->RdDqsMaxDlys[ByteLane] - ChanPtr->RdDqsMinDlys[ByteLane])); - EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->RdDqsMinDlys[ByteLane] + ChanPtr->RdDqsMaxDlys[ByteLane] + 1) / 2)); - if (!NBPtr->FamilySpecificHook[RdDqsDlyRestartChk] (NBPtr, &EyeCenter)) { - return FALSE; - } - ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin; - ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax; - NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] (NBPtr, &EyeCenter); - } else { - DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMinDlys[ByteLane]); - DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMaxDlys[ByteLane]); - EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->WrDatMaxDlys[ByteLane] - ChanPtr->WrDatMinDlys[ByteLane])); - EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->WrDatMinDlys[ByteLane] + ChanPtr->WrDatMaxDlys[ByteLane] + 1) / 2)); - ChanPtr->WrDatMinDlys[ByteLane] = DlyMin; - ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax; - } - // - // Flag error for small window. - // - if (EyeWidth < MemTScaleDelayVal (TechPtr, NBPtr->MinDataEyeWidth (NBPtr))) { - TechPtr->SmallDqsPosWindow = TRUE; - SweepPtr->Error = TRUE; - NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrSmallWindBLError] (NBPtr, NULL); - } - - IDS_HDT_CONSOLE (MEM_FLOW, " %02x %02x %02x %02x", DlyMin, DlyMax, EyeWidth, EyeCenter); - - TechPtr->SetDQSDelayCSR (TechPtr, ByteLane, EyeCenter); - if (!SweepPtr->Error) { - TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane; - } - TechPtr->DqsRdWrPosSaved |= 0xFE00; - - Dimm = (TechPtr->ChipSel / 2) * TechPtr->DlyTableWidth () + ByteLane; - if (TechPtr->Direction == DQS_READ_DIR) { - ChanPtr->RdDqsDlys[Dimm] = EyeCenter; - } else { - ChanPtr->WrDatDlys[Dimm] = EyeCenter + ChanPtr->WrDqsDlys[Dimm]; - } - - return TRUE; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.h deleted file mode 100644 index 9c88fcdb9c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.h +++ /dev/null @@ -1,116 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttEdgeDetect.h - * - * Technology Common Training Header file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MTTEDGEDETECT_H_ -#define _MTTEDGEDETECT_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - - -#define SCAN_LEFT 0 ///< Scan Down -#define SCAN_RIGHT 1 ///< Scan Up -#define LEFT_EDGE 0 ///< searching for the left edge -#define RIGHT_EDGE 1 ///< searching for the right edge - -#define SweepStages 4 -#define TRN_DELAY_MAX 31 ///< Max Virtual delay value for DQS Position Training - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/** - * Sweep Table Structure. ROM based table defining parameters for DQS position - * training delay sweep. -*/ -typedef struct { - INT8 BeginDelay; ///< Starting Delay Value - INT8 EndDelay; ///< Ending Delay Value - BOOLEAN ScanDir; ///< Scan Direction. 0 = down, 1 = up - INT8 Step; ///< Amount to increment delay value - UINT16 EndResult; ///< Result value to stop sweeping (to compare with failure mask) - BOOLEAN MinMax; ///< Flag indicating lower (left edge) or higher(right edge) -} DQS_POS_SWEEP_TABLE; - -/** - * Sweep Information Struct - Used to track data through the DQS Delay Sweep - * -*/ -typedef struct _SWEEP_INFO { - BOOLEAN Error; ///< Indicates an Error has been found - UINT32 TestAddrRJ16[MAX_CS_PER_CHANNEL]; ///< System address of chipselects RJ 16 bits (Addr[47:16]) - BOOLEAN CsAddrValid[MAX_CS_PER_CHANNEL]; ///< Indicates which chipselects to test - INT8 BeginDelay; ///< Beginning Delay value (Virtual) - INT8 EndDelay; ///< Ending Delay value (Virtual) - INT8 Step; ///< Amount to Inc or Dec Virtual Delay value - BOOLEAN Edge; ///< Left or right edge (0 = LEFT, 1= RIGHT) - UINT16 EndResult; ///< Result value that will stop a Dqs Sweep - UINT16 InsertionDelayMsk; ///< Mask of Byte Lanes that should use ins. dly. comparison - UINT16 LaneMsk; ///< Mask indicating byte lanes to update - UINT16 ResultFound; ///< Mask indicating byte lanes where desired result was found on a sweep - INT8 *TrnDelays; ///< Delay Values for each byte (Virtual). Points into the delay values -} SWEEP_INFO; ///< stored in the CH_DEF_STRUCT. - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - - - -#endif /* _MTTEDGEDETECT_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttdimbt.c deleted file mode 100644 index 1339bf586a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttdimbt.c +++ /dev/null @@ -1,1424 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttdimmbt.c - * - * Technology Dimm Based Training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "GeneralServices.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_MTTDIMBT_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemTInitDqsPos4RcvrEnByte ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -VOID -STATIC -MemTSetRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly - ); - -VOID -STATIC -MemTLoadRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ); - -BOOLEAN -STATIC -MemTSaveRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly, - IN UINT16 CmpResultRank0, - IN UINT16 CmpResultRank1 - ); - -VOID -STATIC -MemTResetDctWrPtrByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ); - -UINT16 -STATIC -MemTCompare1ClPatternByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[] - ); - -VOID -STATIC -MemTSkipChipSelPass1Byte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 *ChipSelPtr - ); - -VOID -STATIC -MemTSkipChipSelPass2Byte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 *ChipSelPtr - ); - -UINT8 -STATIC -MemTMaxByteLanesByte ( VOID ); - -UINT8 -STATIC -MemTDlyTableWidthByte ( VOID ); - -VOID -STATIC -MemTSetDqsDelayCsrByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ByteLane, - IN UINT8 Dly - ); - -VOID -STATIC -MemTDqsWindowSaveByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ByteLane, - IN UINT8 DlyMin, - IN UINT8 DlyMax - ); - -BOOLEAN -STATIC -MemTFindMaxRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - OUT UINT8 *ChipSel - ); - -UINT16 -STATIC -MemTCompare1ClPatternOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT8 Side, - IN UINT8 Receiver, - IN BOOLEAN Side1En - ); - -VOID -STATIC -MemTLoadRcvrEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ); - -VOID -STATIC -MemTSetRcvrEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly - ); - -VOID -STATIC -MemTLoadInitialRcvEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ); - -UINT8 -STATIC -MemTFindMinMaxGrossDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN TRN_DLY_TYPE TrnDlyType, - IN BOOLEAN IfMax - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function enables byte based training if called - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -MemTDimmByteTrainInit ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - UINT8 Channel; - UINT8 DctCount; - UINT8 ChannelCount; - DIE_STRUCT *MCTPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - - TechPtr->InitDQSPos4RcvrEn = MemTInitDqsPos4RcvrEnByte; - TechPtr->SetRcvrEnDly = MemTSetRcvrEnDlyByte; - TechPtr->LoadRcvrEnDly = MemTLoadRcvrEnDlyByte; - TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByte; - TechPtr->SaveRcvrEnDlyFilter = MemTSaveRcvrEnDlyByteFilterOpt; - TechPtr->ResetDCTWrPtr = MemTResetDctWrPtrByte; - TechPtr->Compare1ClPattern = MemTCompare1ClPatternByte; - TechPtr->SkipChipSelPass1 = MemTSkipChipSelPass1Byte; - TechPtr->SkipChipSelPass2 = MemTSkipChipSelPass2Byte; - TechPtr->MaxByteLanes = MemTMaxByteLanesByte; - TechPtr->DlyTableWidth = MemTDlyTableWidthByte; - TechPtr->SetDQSDelayCSR = MemTSetDqsDelayCsrByte; - TechPtr->DQSWindowSave = MemTDqsWindowSaveByte; - TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyByte; - TechPtr->Compare1ClPatternOpt = MemTCompare1ClPatternOptByte; - TechPtr->LoadRcvrEnDlyOpt = MemTLoadRcvrEnDlyOptByte; - TechPtr->SetRcvrEnDlyOpt = MemTSetRcvrEnDlyOptByte; - TechPtr->InitializeVariablesOpt = MemTInitializeVariablesOptByte; - TechPtr->GetMaxValueOpt = MemTGetMaxValueOptByte; - TechPtr->SetSweepErrorOpt = MemTSetSweepErrorOptByte; - TechPtr->CheckRcvrEnDlyLimitOpt = MemTCheckRcvrEnDlyLimitOptByte; - TechPtr->LoadInitialRcvrEnDlyOpt = MemTLoadInitialRcvEnDlyOptByte; - TechPtr->GetMinMaxGrossDly = MemTFindMinMaxGrossDlyByte; - // Dynamically allocate buffers for storing trained timings. - DctCount = MCTPtr->DctCount; - ChannelCount = MCTPtr->DctData[0].ChannelCount; - AllocHeapParams.RequestedBufferSize = ((DctCount * ChannelCount) * - ((MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES) + - (MAX_DELAYS * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) + - (MAX_DIMMS * MAX_NUMBER_LANES) - ) - ); - - if (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE) { - AllocHeapParams.RequestedBufferSize *= 2; - } - - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, MCTPtr->NodeId, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader) == AGESA_SUCCESS) { - for (Dct = 0; Dct < DctCount; Dct++) { - for (Channel = 0; Channel < ChannelCount; Channel++) { - MCTPtr->DctData[Dct].ChData[Channel].RowCount = MAX_DIMMS; - MCTPtr->DctData[Dct].ChData[Channel].ColumnCount = MAX_DELAYS; - - MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2; - MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].RdDqs__Dlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_NUMBER_LANES); - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_CS_PER_CHANNEL * MAX_DELAYS); - if (NBPtr->MemPstateStage == MEMORY_PSTATE_1ST_STAGE) { - MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlysMemPs1 = (UINT16 *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2; - MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlysMemPs1 = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlysMemPs1 = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].WrDatDlysMemPs1 = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].RdDqs__DlysMemPs1 = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_NUMBER_LANES); - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlysMemPs1 = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlysMemPs1 = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlysMemPs1 = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlysMemPs1 = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS); - MCTPtr->DctData[Dct].ChData[Channel].FailingBitMaskMemPs1 = AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += (MAX_CS_PER_CHANNEL * MAX_DELAYS); - - } - } - } - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not dynamically allocate buffers for storing trained timings - } -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes the DQS Positions in preparation for Receiver Enable Training. - * Write Position is no delay, Read Position is 1/2 Memclock delay - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - */ - -VOID -STATIC -MemTInitDqsPos4RcvrEnByte ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dimm; - UINT8 ByteLane; - UINT8 WrDqs; - - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - for (ByteLane = 0; ByteLane < MAX_DELAYS; ByteLane++) { - WrDqs = TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane]; - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqs); - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), 0x3F); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs DqsRcvEnDly to additional index for DQS receiver enabled training - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * @param[in] RcvEnDly - receiver enable delay to be saved - */ - -VOID -STATIC -MemTSetRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly - ) -{ - UINT8 ByteLane; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) { - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), RcvEnDly); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function loads the DqsRcvEnDly from saved data and program to additional index - * for DQS receiver enabled training - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * - */ - -VOID -STATIC -MemTLoadRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ) -{ - UINT8 i; - UINT8 Dimm; - UINT16 Saved; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Dimm = Receiver >> 1; - Saved = TechPtr->DqsRcvEnSaved; - for (i = 0; i < MAX_BYTELANES; i++) { - if (Saved & 1) { - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i), - ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]); - } - Saved >>= 1; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function saves passing DqsRcvEnDly values to the stack - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * @param[in] RcvEnDly - receiver enable delay to be saved - * @param[in] CmpResultRank0 - compare result for Rank 0 - * @param[in] CmpResultRank1 - compare result for Rank 1 - * - * @return TRUE - All bytelanes pass - * @return FALSE - Some bytelanes fail - */ - -BOOLEAN -STATIC -MemTSaveRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly, - IN UINT16 CmpResultRank0, - IN UINT16 CmpResultRank1 - ) -{ - UINT8 i; - UINT8 Passed; - UINT8 Saved; - UINT8 Mask; - UINT8 Dimm; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF); - - Saved = (UINT8) (TechPtr->DqsRcvEnSaved & Passed); //@attention - false passes filter (subject to be replaced with a better solution) - Dimm = Receiver >> 1; - Mask = 1; - for (i = 0; i < MAX_BYTELANES; i++) { - if (Passed & Mask) { - if (!(Saved & Mask)) { - ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20; // @attention -1 pass only - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tBL %d = %02x", i, RcvEnDly + 0x20); - } - Saved |= Mask; - } - Mask <<= 1; - } - TechPtr->DqsRcvEnSaved = Saved; - - if (Saved == 0xFF) { - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function performs a filtering functionality and saves passing DqsRcvEnDly - * values to the stack - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * @param[in] RcvEnDly - receiver enable delay to be saved - * @param[in] CmpResultRank0 - compare result for Rank 0 - * @param[in] CmpResultRank1 - compare result for Rank 1 - * - * @return TRUE - All bytelanes pass - * @return FALSE - Some bytelanes fail - */ - -BOOLEAN -MemTSaveRcvrEnDlyByteFilter ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly, - IN UINT16 CmpResultRank0, - IN UINT16 CmpResultRank1 - ) -{ - UINT8 i; - UINT8 Passed; - UINT8 Saved; - UINT8 Mask; - UINT8 Dimm; - UINT8 MaxFilterDly; - CH_DEF_STRUCT *ChannelPtr; - MEM_DCT_CACHE *DctCachePtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - DctCachePtr = TechPtr->NBPtr->DctCachePtr; - - MaxFilterDly = TechPtr->MaxFilterDly; - Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF); - - Dimm = Receiver >> 1; - Saved = (UINT8) TechPtr->DqsRcvEnSaved; - Mask = 1; - for (i = 0; i < MAX_BYTELANES; i++) { - if ((Passed & Mask) != 0) { - DctCachePtr->RcvEnDlyCounts [i] += 1; - if ((Saved & Mask) == 0) { - ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20; - Saved |= Mask; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tBL %d = %02x", i, RcvEnDly + 0x20); - } - } else { - if (DctCachePtr->RcvEnDlyCounts [i] <= MaxFilterDly) { - DctCachePtr->RcvEnDlyCounts [i] = 0; - Saved &= ~Mask; - } - } - Mask <<= 1; - } - - //----------------------- - TechPtr->DqsRcvEnSaved = (UINT16) Saved; - - Saved = 0; - for (i = 0; i < MAX_BYTELANES; i++) { - if (DctCachePtr->RcvEnDlyCounts [i] >= MaxFilterDly) { - Saved |= (UINT8) 1 << i; - } - } - - if (Saved == 0xFF) { - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function compares test pattern with data in buffer and return a pass/fail bitmap - * for 8 Bytes - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * - * @return PASS - Bit map of results of comparison - */ - -UINT16 -STATIC -MemTCompare1ClPatternByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[] - ) -{ - UINT16 i; - UINT16 j; - UINT16 Pass; - DIE_STRUCT *MCTPtr; - - MCTPtr = TechPtr->NBPtr->MCTPtr; - if (MCTPtr->GangedMode && MCTPtr->Dct) { - j = 8; - } else { - j = 0; - } - - Pass = 0xFFFF; - IDS_HDT_CONSOLE (MEM_FLOW, " -"); - for (i = 0; i < 8; i++) { - if (Buffer[j] != Pattern[j]) { - // if bytelane n fails - Pass &= ~((UINT16)1 << (j % 8)); // clear bit n - } - IDS_HDT_CONSOLE (MEM_FLOW, " %c", (Buffer[j] == Pattern[j]) ? 'P' : '.'); - j++; - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t -"); - for (i = 0, j -= 8; i < 8; i++, j++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Buffer[j]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t -"); - for (i = 0, j -= 8; i < 8; i++, j++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Pattern[j]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); - ); - - return Pass; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * The function resets the DCT input buffer write pointer. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Chip select - * - */ - -VOID -STATIC -MemTResetDctWrPtrByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ) -{ - UINT8 i; - UINT16 RcvEnDly; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - for (i = 0; i < MAX_BYTELANES; i++) { - RcvEnDly = (UINT16) TechPtr->NBPtr->GetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i)); - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i), RcvEnDly); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function skips odd chip select if training at 800MT or above. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] *ChipSelPtr - Pointer to variable contains Chip select index - * - */ - -VOID -STATIC -MemTSkipChipSelPass1Byte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 *ChipSelPtr - ) -{ - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - // if the even chip select failed training, need to set CsTrainFail for odd chip select if present. - if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ((*ChipSelPtr) + 1))) { - if (NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << *ChipSelPtr)) { - NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((*ChipSelPtr) + 1); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - } - } - (*ChipSelPtr)++; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * MemTSkipChipSelPass2Byte: - * - * This function skips odd chip select if training at 800MT or above. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *ChipSelPtr - Pointer to variable contains Chip select index - * - */ - -VOID -STATIC -MemTSkipChipSelPass2Byte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT8 *ChipSelPtr - ) -{ - if (*ChipSelPtr & 1) { - *ChipSelPtr = MAX_CS_PER_CHANNEL; // skip all successions - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines the maximum number of byte lanes - * - * @return Max number of Bytelanes - */ - -UINT8 -STATIC -MemTMaxByteLanesByte ( VOID ) -{ - return MAX_BYTELANES; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) - * - * @return Delay table width in bytes - */ - -UINT8 -STATIC -MemTDlyTableWidthByte ( VOID ) -{ - return MAX_DELAYS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function writes the Delay value to a certain byte lane - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ByteLane - Bytelane number being targeted - * @param[in] Dly - Delay value - * - */ - -VOID -STATIC -MemTSetDqsDelayCsrByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ByteLane, - IN UINT8 Dly - ) -{ - UINT8 Reg; - UINT8 Dimm; - - ASSERT (ByteLane <= MAX_BYTELANES); - - if (!(TechPtr->DqsRdWrPosSaved & ((UINT8)1 << ByteLane))) { - Dimm = (TechPtr->ChipSel >> 1); - - if (TechPtr->Direction == DQS_WRITE_DIR) { - Dly = Dly + ((UINT8) TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane]); - Reg = AccessWrDatDly; - } else { - Reg = AccessRdDqsDly; - } - - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, Reg, DIMM_BYTE_ACCESS (Dimm, ByteLane), Dly); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs the trained DQS delay for the specified byte lane - * and stores its DQS window for reference. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ByteLane - Bytelane number being targeted - * @param[in] DlyMin - Minimum delay value - * @param[in] DlyMax- Maximum delay value - * - */ - -VOID -STATIC -MemTDqsWindowSaveByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ByteLane, - IN UINT8 DlyMin, - IN UINT8 DlyMax - ) -{ - UINT8 DqsDelay; - UINT8 Dimm; - CH_DEF_STRUCT *ChanPtr; - - ASSERT (ByteLane <= MAX_BYTELANES); - ChanPtr = TechPtr->NBPtr->ChannelPtr; - - DqsDelay = ((DlyMin + DlyMax + 1) / 2) & 0x3F; - MemTSetDqsDelayCsrByte (TechPtr, ByteLane, DqsDelay); - TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane; - TechPtr->DqsRdWrPosSaved |= 0xFF00; - - Dimm = (TechPtr->ChipSel / 2) * MAX_DELAYS + ByteLane; - if (TechPtr->Direction == DQS_READ_DIR) { - ChanPtr->RdDqsDlys[Dimm] = DqsDelay; - } else { - ChanPtr->WrDatDlys[Dimm] = DqsDelay + ChanPtr->WrDqsDlys[Dimm]; - } - - if (TechPtr->Direction == DQS_READ_DIR) { - ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin; - ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax; - } else { - ChanPtr->WrDatMinDlys[ByteLane] = DlyMin; - ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax; - } - -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finds the DIMM that has the largest receiver enable delay. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[out] *ChipSel - Pointer to the Chip select that has the largest receiver enable delay. - * - * @return TRUE - A chip select can be found. - * @return FALSE - A chip select cannot be found. - */ - -BOOLEAN -STATIC -MemTFindMaxRcvrEnDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - OUT UINT8 *ChipSel - ) -{ - UINT8 Dimm; - UINT8 ByteLane; - UINT16 RcvEnDly; - UINT16 MaxDly; - UINT8 MaxDlyDimm; - BOOLEAN RetVal; - - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - ChannelPtr = NBPtr->ChannelPtr; - - RetVal = FALSE; - MaxDly = 0; - MaxDlyDimm = 0; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16) 1 << (Dimm << 1))) != 0) { - if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) 3 << (Dimm << 1))) == 0) { - // Only choose the dimm that does not fail training - for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { - RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane]; - if (RcvEnDly > MaxDly) { - MaxDly = RcvEnDly; - MaxDlyDimm = Dimm; - RetVal = TRUE; - } - } - } - } - } - - if (NBPtr->MCTPtr->Status[Sb128bitmode] != 0) { - //The RcvrEnDlys of DCT1 DIMMs should also be considered while ganging. - NBPtr->SwitchDCT (NBPtr, 1); - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { - RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane]; - if (RcvEnDly > MaxDly) { - MaxDly = RcvEnDly; - MaxDlyDimm = Dimm; - } - } - } - NBPtr->SwitchDCT (NBPtr, 0); - } - - TechPtr->MaxDlyForMaxRdLat = MaxDly; - *ChipSel = (MaxDlyDimm * 2); - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[out] *ChipSel - Pointer to the Chip select that has the largest receiver enable delay - * + Read DQS Delay. - * - * @return TRUE - A chip select can be found. - * @return FALSE - A chip select cannot be found. - */ - -BOOLEAN -MemTFindMaxRcvrEnDlyRdDqsDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - OUT UINT8 *ChipSel - ) -{ - UINT8 Dimm; - UINT8 ByteLane; - UINT16 RcvEnDly; - UINT16 RdDqsDly; - UINT16 TotalDly; - UINT16 MaxDly; - UINT8 MaxDlyDimm; - BOOLEAN RetVal; - - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - ChannelPtr = NBPtr->ChannelPtr; - - RetVal = FALSE; - MaxDly = 0; - MaxDlyDimm = 0; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) 3 << (Dimm << 1))) == 0) { - // Only choose the dimm that does not fail training - for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) { - RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane]; - // Before Dqs Position Training, this value is 0. So the maximum value for - // RdDqsDly needs to be added later when calculating the MaxRdLatency value - // after RcvEnDly training but before DQS Position Training. - RdDqsDly = ChannelPtr->RdDqsDlys[Dimm * MAX_DELAYS + ByteLane]; - TotalDly = RcvEnDly + (RdDqsDly >> 1); - if (TotalDly > MaxDly) { - MaxDly = TotalDly; - MaxDlyDimm = Dimm; - RetVal = TRUE; - } - } - } - } - - TechPtr->MaxDlyForMaxRdLat = MaxDly; - *ChipSel = (MaxDlyDimm * 2); - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay for UNB - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[out] *ChipSel - Pointer to the Chip select that has the largest receiver enable delay - * + Read DQS Delay. - * - * @return TRUE - A chip select can be found. - * @return FALSE - A chip select cannot be found. - */ - -BOOLEAN -MemTFindMaxRcvrEnDlyRdDqsDlyByteUnb ( - IN OUT MEM_TECH_BLOCK *TechPtr, - OUT UINT8 *ChipSel - ) -{ - UINT8 Dimm; - UINT8 ByteLane; - UINT16 RcvEnDly; - UINT16 RdDqsDly; - UINT16 TotalDly; - UINT16 MaxDly; - UINT8 MaxDlyDimm; - BOOLEAN RetVal; - - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - ChannelPtr = NBPtr->ChannelPtr; - - RetVal = FALSE; - MaxDly = 0; - MaxDlyDimm = 0; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) 3 << (Dimm << 1))) == 0) { - // Only choose the dimm that does not fail training - for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { - RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane]; - // Before Dqs Position Training, this value is 0. So the maximum value for - // RdDqsDly needs to be added later when calculating the MaxRdLatency value - // after RcvEnDly training but before DQS Position Training. - RdDqsDly = ChannelPtr->RdDqsDlys[Dimm * MAX_DELAYS + ByteLane]; - TotalDly = RcvEnDly + RdDqsDly; - if (TotalDly > MaxDly) { - MaxDly = TotalDly; - MaxDlyDimm = Dimm; - RetVal = TRUE; - } - } - } - } - - TechPtr->MaxDlyForMaxRdLat = MaxDly; - *ChipSel = (MaxDlyDimm * 2); - return RetVal; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function finds the minimum or maximum gross dly among all the bytes. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] TrnDlyType - Target Dly type - * @param[in] IfMax - If this is for maximum value or minimum - * - * @return minimum gross dly - */ -UINT8 -STATIC -MemTFindMinMaxGrossDlyByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN TRN_DLY_TYPE TrnDlyType, - IN BOOLEAN IfMax - ) -{ - UINT8 i; - UINT8 ByteLane; - UINT16 CsEnabled; - UINT8 MinMaxGrossDly; - UINT8 TrnDly; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; - MinMaxGrossDly = IfMax ? 0 : 0xFF; - - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((CsEnabled & (UINT16) (3 << (i << 1))) != 0) { - for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) { - TrnDly = (UINT8) (GetTrainDlyFromHeapNb (NBPtr, TrnDlyType, DIMM_BYTE_ACCESS (i, ByteLane)) >> 5); - if ((IfMax && (TrnDly > MinMaxGrossDly)) || (!IfMax && (TrnDly < MinMaxGrossDly))) { - MinMaxGrossDly = TrnDly; - } - } - } - } - - return MinMaxGrossDly; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function compares test pattern with data in buffer and return a pass/fail bitmap - * for 8 Bytes for optimized receiver enable training - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare - * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against - * @param[in] Side - current side being targeted - * @param[in] Receiver - Current receiver value - * @param[in] Side1En - Indicates if the second side of the DIMM is being used - * @return PASS - Bit map of results of comparison - */ - -UINT16 -STATIC -MemTCompare1ClPatternOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Buffer[], - IN UINT8 Pattern[], - IN UINT8 Side, - IN UINT8 Receiver, - IN BOOLEAN Side1En - ) -{ - UINT16 i; - UINT16 j; - UINT16 Pass; - DIE_STRUCT *MCTPtr; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - MCTPtr = TechPtr->NBPtr->MCTPtr; - - if (MCTPtr->GangedMode && MCTPtr->Dct) { - j = 8; - } else { - j = 0; - } - - Pass = 0xFFFF; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDelay[BL] -"); - for (i = 0; i < 8; i++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", TechPtr->RcvrEnDlyOpt[i] & 0xFF); - if (Buffer[j] != Pattern[j]) { - // if bytelane n fails - Pass &= ~((UINT16)1 << (j % 8)); // clear bit n - TechPtr->DqsRcvEnFirstPassValOpt[i] = 0; - TechPtr->GetFirstPassValOpt[i] = FALSE; - TechPtr->IncBy1ForNextCountOpt[i] = FALSE; - TechPtr->DqsRcvEnSavedOpt[i] = FALSE; - if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) { - if (Side == ((Side1En ? 4 : 2) - 1)) { - TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT; - } - } - } else { - if (TechPtr->FilterSidePassCountOpt[i] == ((Side1En ? 4 : 2) - 1)) { - //Only apply filter if all sides have passed - if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) { - if (TechPtr->GetFirstPassValOpt[i] == FALSE) { - // This is the first Pass, mark the start of filter check - TechPtr->DqsRcvEnFirstPassValOpt[i] = TechPtr->RcvrEnDlyOpt[i]; - TechPtr->GetFirstPassValOpt[i] = TRUE; - TechPtr->IncBy1ForNextCountOpt[i] = FALSE; - TechPtr->RcvrEnDlyOpt[i]++; - } else { - if ((TechPtr->RcvrEnDlyOpt[i] - TechPtr->DqsRcvEnFirstPassValOpt[i]) < FILTER_WINDOW_SIZE) { - if (TechPtr->IncBy1ForNextCountOpt[i] == FALSE) { - TechPtr->RcvrEnDlyOpt[i] += FILTER_SECOND_STAGE_COUNT; - TechPtr->IncBy1ForNextCountOpt[i] = TRUE; - } else { - TechPtr->RcvrEnDlyOpt[i]++; - TechPtr->IncBy1ForNextCountOpt[i] = FALSE; - } - } else { - // End sweep and add offset to first pass - TechPtr->MaxRcvrEnDlyBlOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i]; - TechPtr->RcvrEnDlyOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i] + FILTER_OFFSET_VALUE; - TechPtr->FilterStatusOpt[i] = DONE_FILTER; - TechPtr->FilterCountOpt++; - } - } - } else { - TechPtr->FilterSidePassCountOpt[i]++; - } - } else { - if (TechPtr->GetFirstPassValOpt[i] == FALSE) { - if (Side == ((Side1En ? 4 : 2) - 1)) { - TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT; - } - } - TechPtr->FilterSidePassCountOpt[i]++; - } - TechPtr->DqsRcvEnSavedOpt[i] = TRUE; - ChannelPtr->RcvEnDlys[(Receiver >> 1) * MAX_DELAYS + i] = TechPtr->RcvrEnDlyOpt[i]; - } - if (Side == ((Side1En ? 4 : 2) - 1)) { - TechPtr->FilterSidePassCountOpt[i] = 0; - } - if (TechPtr->RcvrEnDlyOpt[i] >= TechPtr->RcvrEnDlyLimitOpt[i]) { - TechPtr->FilterCountOpt++; - } - - j++; - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tPass/Fail -"); - for (i = 0, j -= 8; i < 8; i++, j++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c", (Buffer[j] == Pattern[j]) ? 'P' : '.'); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Measured -"); - for (i = 0, j -= 8; i < 8; i++, j++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Buffer[j]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Expected -"); - for (i = 0, j -= 8; i < 8; i++, j++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Pattern[j]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); - ); - - return Pass; -} -/*----------------------------------------------------------------------------- - * - * This function initializes variables for optimized training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * ---------------------------------------------------------------------------- - */ -VOID -MemTInitializeVariablesOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 ByteLane; - for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { - TechPtr->RcvrEnDlyLimitOpt[ByteLane] = FILTER_MAX_REC_EN_DLY_VALUE; // @attention - limit depends on proc type - TechPtr->DqsRcvEnSavedOpt[ByteLane] = FALSE; - TechPtr->RcvrEnDlyOpt[ByteLane] = FILTER_NEW_RECEIVER_START_VALUE; - TechPtr->GetFirstPassValOpt[ByteLane] = FALSE; - TechPtr->DqsRcvEnFirstPassValOpt[ByteLane] = 0; - TechPtr->RevertPassValOpt[ByteLane] = FALSE; - TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] = 0; - TechPtr->FilterStatusOpt[ByteLane] = START_FILTER; - TechPtr->FilterCountOpt = 0; - TechPtr->FilterSidePassCountOpt[ByteLane] = 0; - TechPtr->IncBy1ForNextCountOpt[ByteLane] = FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function loads the DqsRcvEnDly from saved data and program to additional index - * for optimized DQS receiver enabled training - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * - */ - -VOID -STATIC -MemTLoadRcvrEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ) -{ - UINT8 i; - UINT8 Dimm; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Dimm = Receiver >> 1; - for (i = 0; i < 8; i++) { - if (TechPtr->DqsRcvEnSavedOpt[i]) { - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i), - ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function programs DqsRcvEnDly to additional index for DQS receiver enabled training - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * @param[in] RcvEnDly - receiver enable delay to be saved - */ - -VOID -STATIC -MemTSetRcvrEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly - ) -{ - UINT8 ByteLane; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - - for (ByteLane = 0; ByteLane < 8; ByteLane++) { - if (TechPtr->FilterStatusOpt[ByteLane] != DONE_FILTER) { - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), TechPtr->RcvrEnDlyOpt[ByteLane]); - } - } -} -/*----------------------------------------------------------------------------- - * - * This sets any Errors generated from Dly sweep - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] DCT - current DCT - * @param[in] Receiver - current receiver - * - * @return FALSE - Fatal error occurs. - * @return TRUE - No fatal error occurs. - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemTSetSweepErrorOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT8 Dct, - IN BOOLEAN ErrorCheck - ) -{ - UINT8 ByteLane; - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { - if (TechPtr->RcvrEnDlyOpt[ByteLane] == TechPtr->RcvrEnDlyLimitOpt[ByteLane]) { - // no passing window - if (ErrorCheck) { - return FALSE; - } - PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - } - if (TechPtr->RcvrEnDlyOpt[ByteLane] > (TechPtr->RcvrEnDlyLimitOpt[ByteLane] - 1)) { - // passing window too narrow, too far delayed - if (ErrorCheck) { - return FALSE; - } - PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - DCTPtr->Timings.CsTrainFail |= (UINT16) (3 << Receiver) & DCTPtr->Timings.CsPresent; - MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct; - if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &MemPtr->StdHeader)) { - ASSERT (FALSE); - return FALSE; - } - } - } - return TRUE; -} - -/*----------------------------------------------------------------------------- - * - * This function determines the maximum receiver delay value - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @retval MaxRcvrValue - Maximum receiver delay value for all bytelanes - * ---------------------------------------------------------------------------- - */ - -UINT16 -MemTGetMaxValueOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 ByteLane; - UINT16 MaxRcvrValue; - MaxRcvrValue = 0; - for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { - if (TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] > MaxRcvrValue) { - MaxRcvrValue = TechPtr->MaxRcvrEnDlyBlOpt[ByteLane]; - } - } - MaxRcvrValue += FILTER_OFFSET_VALUE; - return MaxRcvrValue; -} -/*----------------------------------------------------------------------------- - * - * This function determines if the sweep loop should complete. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @retval TRUE - All bytelanes pass - * FALSE - Some bytelanes fail - * ---------------------------------------------------------------------------- - */ - -BOOLEAN -MemTCheckRcvrEnDlyLimitOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - if (TechPtr->FilterCountOpt >= (UINT16)MAX_CS_PER_CHANNEL) { - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function load the result of write levelization training into RcvrEnDlyOpt, - * using it as the initial value for Receiver DQS training. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - */ -VOID -STATIC -MemTLoadInitialRcvEnDlyOptByte ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver - ) -{ - UINT8 ByteLane; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) { - TechPtr->RcvrEnDlyOpt[ByteLane] = NBPtr->ChannelPtr->WrDqsDlys[((Receiver >> 1) * TechPtr->DlyTableWidth ()) + ByteLane]; - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttecc.c deleted file mode 100644 index a85c76a635..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttecc.c +++ /dev/null @@ -1,226 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttecc.c - * - * Technology ECC byte support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_MTTECC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemTCalcDQSEccTmg ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Type, - IN OUT VOID *DlyArray - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the DQS ECC timings - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTSetDQSEccTmgs ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 Dct; - UINT8 Dimm; - UINT8 i; - - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - if (NBPtr->MCTPtr->NodeMemSize) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - ChannelPtr = NBPtr->ChannelPtr; - for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { - if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)1 << (Dimm * 2))) { - i = Dimm * TechPtr->DlyTableWidth (); - MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRcvEnDly, &ChannelPtr->RcvEnDlys[i]); - MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRdDqsDly, &ChannelPtr->RdDqsDlys[i]); - MemTCalcDQSEccTmg (TechPtr, Dimm, AccessWrDatDly, &ChannelPtr->WrDatDlys[i]); - } - } - } - } - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates the DQS ECC timings - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Dimm - Dimm number - * @param[in] Type - Type of DQS timing - * @param[in,out] *DlyArray - Pointer to the array of delays per this Dimm - * - */ - -VOID -STATIC -MemTCalcDQSEccTmg ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Dimm, - IN UINT8 Type, - IN OUT VOID *DlyArray - ) -{ - UINT8 i; - UINT8 j; - UINT8 Scale; - UINT8 EccByte; - UINT16 ByteiDly; - UINT16 BytejDly; - UINT16 EccDly; - UINT8 *WrDqsDly; - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - - NBPtr = TechPtr->NBPtr; - ChannelPtr = NBPtr->ChannelPtr; - - EccByte = TechPtr->MaxByteLanes (); - i = (UINT8) (ChannelPtr->DctEccDqsLike & 0xFF); - j = (UINT8) (ChannelPtr->DctEccDqsLike >> 8); - Scale = ChannelPtr->DctEccDqsScale; - WrDqsDly = &ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth ()]; - - if (Type == AccessRcvEnDly) { - ByteiDly = ((UINT16 *) DlyArray)[i]; - BytejDly = ((UINT16 *) DlyArray)[j]; - } else { - ByteiDly = ((UINT8 *) DlyArray)[i]; - BytejDly = ((UINT8 *) DlyArray)[j]; - } - - // - // For WrDatDly, Subtract TxDqs Delay to get - // TxDq-TxDqs Delta, which is what should be averaged. - // - if (Type == AccessWrDatDly) { - ByteiDly = ByteiDly - WrDqsDly[i]; - BytejDly = BytejDly - WrDqsDly[j]; - } - - if (BytejDly > ByteiDly) { - EccDly = ByteiDly + (UINT8) (((UINT16) (BytejDly - ByteiDly) * Scale + 0x77) / 0xFF); - // Round up --^ - } else { - EccDly = BytejDly + (UINT8) (((UINT16) (ByteiDly - BytejDly) * (0xFF - Scale) + 0x77) / 0xFF); - // Round up --^ - } - - if (Type == AccessRcvEnDly) { - ((UINT16 *) DlyArray)[EccByte] = EccDly; - } else { - ((UINT8 *) DlyArray)[EccByte] = (UINT8) EccDly; - } - - // - // For WrDatDly, Add back the TxDqs value for ECC bytelane - // - if (Type == AccessWrDatDly) { - EccDly = EccDly + WrDqsDly[EccByte]; - } - - NBPtr->SetTrainDly (NBPtr, Type, DIMM_BYTE_ACCESS (Dimm, EccByte), EccDly); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrc.c deleted file mode 100644 index 512c4b592a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrc.c +++ /dev/null @@ -1,311 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtthrc.c - * - * Phy assisted DQS receiver enable training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_MTTHRC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define TpProcMemRcvrSetSeed TpProcMemRcvrSetDelay -#define TpProcMemRcvrInitPRE TpProcMemRcvrStartSweep -#define TpProcMemRcvrBackToBackRead TpProcMemRcvrTestPattern - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemTProgramRcvrEnDly ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel, - IN UINT8 Pass - ); - -BOOLEAN -STATIC -MemTDqsTrainRcvrEnHw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern UINT16 T1minToFreq[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes first pass of Phy assisted receiver enable training - * for current node at DDR800 and below. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @pre Auto refresh and ZQCL must be disabled - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemTDqsTrainRcvrEnHwPass1 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return MemTDqsTrainRcvrEnHw (TechPtr, 1); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes second pass of Phy assisted receiver enable training - * for current node at DDR1066 and above. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @pre Auto refresh and ZQCL must be disabled - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -MemTDqsTrainRcvrEnHwPass2 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - // If current speed is higher than start-up speed, do second pass of WL - if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) { - return MemTDqsTrainRcvrEnHw (TechPtr, 2); - } - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes Phy assisted receiver enable training for current node. - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Pass - Pass of the receiver training - * - * @pre Auto refresh and ZQCL must be disabled - * - */ -BOOLEAN -STATIC -MemTDqsTrainRcvrEnHw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ) -{ - MEM_NB_BLOCK *NBPtr; - UINT32 TestAddrRJ16; - UINT8 Dct; - UINT8 ChipSel; - NBPtr = TechPtr->NBPtr; - - TechPtr->TrainingType = TRN_RCVR_ENABLE; - - AGESA_TESTPOINT (TpProcMemReceiverEnableTraining , &(NBPtr->MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart HW RxEn training\n"); - - // Set environment settings before training - MemTBeginTraining (TechPtr); - // - // Setup hardware training engine (if applicable) - // - NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - //training for each rank - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; (NBPtr->MCTPtr->Status[SbLrdimms])? ChipSel += 2: ChipSel++) { - if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) { - if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0)) { - // 1.Prepare the DIMMs for training - NBPtr->SetBitField (NBPtr, BFTrDimmSel, ChipSel >> 1); - - TechPtr->ChipSel = ChipSel; - TechPtr->Pass = Pass; - NBPtr->FamilySpecificHook[InitPerNibbleTrn] (NBPtr, NULL); - for (TechPtr->TrnNibble = NIBBLE_0; TechPtr->TrnNibble <= (NBPtr->FamilySpecificHook[TrainRxEnPerNibble] (NBPtr, &ChipSel)? NIBBLE_0 : NIBBLE_1); TechPtr->TrnNibble++) { - // 2.Prepare the phy for DQS receiver enable training. - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tTestAddr %x0000\n", TestAddrRJ16); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - - AGESA_TESTPOINT (TpProcMemRcvrSetSeed, &(NBPtr->MemPtr->StdHeader)); - NBPtr->MemNPrepareRcvrEnDlySeed (NBPtr); - - AGESA_TESTPOINT (TpProcMemRcvrInitPRE, &(NBPtr->MemPtr->StdHeader)); - // 3.BIOS initiates the phy assisted receiver enable training - NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 1); - - // 4.BIOS begins sending out of back-to-back reads to create - // a continuous stream of DQS edges on the DDR interface - AGESA_TESTPOINT (TpProcMemRcvrBackToBackRead, &(NBPtr->MemPtr->StdHeader)); - NBPtr->GenHwRcvEnReads (NBPtr, TestAddrRJ16); - - // 7.Program [DqsRcvTrEn]=0 to stop the DQS receive enable training. - NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 0); - - // 8.Get the gross and fine delay values. - // 9.Calculate the corresponding final delay values - MemTProgramRcvrEnDly (TechPtr, ChipSel, Pass); - } - } - } - } - } - // Restore environment settings after training - MemTEndTraining (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "End HW RxEn training\n\n"); - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function calculates final RcvrEnDly for each rank - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] ChipSel - Rank to be trained - * @param[in] Pass - Pass of the receiver training - * - */ -VOID -STATIC -MemTProgramRcvrEnDly ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 ChipSel, - IN UINT8 Pass - ) -{ - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - UINT8 ByteLane; - UINT16 RcvEnDly; - UINT16 CsPairRcvEnDly; - UINT16 RankRcvEnDly[9]; - NBPtr = TechPtr->NBPtr; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t PRE: "); - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8) ; ByteLane++) { - RcvEnDly = (UINT8) NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane)); - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RcvEnDly); - - RcvEnDly = RcvEnDly + TechPtr->DiffSeedGrossSeedPreGross[ByteLane]; - - // Add 1 UI to get to the midpoint of preamble - RcvEnDly += 0x20; - TechPtr->Bytelane = ByteLane; - RankRcvEnDly[ByteLane] = RcvEnDly; - if (NBPtr->FamilySpecificHook[TrainRxEnAdjustDlyPerNibble] (NBPtr, &RcvEnDly)) { - if ((ChipSel & 1) == 1) { - // For each rank pair on a dual-rank DIMM, compute the average value of the total delays saved during the - // training of each rank and program the result in D18F2x[1,0]9C_x0000_00[24:10][DqsRcvEnGrossDelay, - // DqsRcvEnFineDelay]. - CsPairRcvEnDly = ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane]; - RcvEnDly = (CsPairRcvEnDly + RcvEnDly + 1) / 2; - } - } - ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane] = RcvEnDly; - NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((ChipSel >> 1), ByteLane), RcvEnDly); - } - - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t RxEn: "); - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RankRcvEnDly[ByteLane]); - } - if (NBPtr->FamilySpecificHook[TrainRxEnGetAvgDlyPerNibble] (NBPtr, NULL)) { - if ((ChipSel & 1) == 1) { - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Avg: "); - for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane]); - } - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); - ); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c deleted file mode 100644 index 044e0bf3dd..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c +++ /dev/null @@ -1,624 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mtthrcSt.c - * - * Phy assisted DQS receiver enable seedless training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 42643 $ @e \$Date: 2010-11-24 13:51:41 -0600 (Wed, 24 Nov 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mttEdgeDetect.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE -/*---------------------------------------------------------------------------- -3 * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -VOID -STATIC -MemTRdPosRxEnSeedSetDly3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT16 RcvEnDly, - IN OUT UINT8 ByteLane - ); - -VOID -STATIC -MemTRdPosRxEnSeedCheckRxEndly3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*----------------------------------------------------------------------------- - * - * - * This function checks each bytelane for no window error. - * - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemTTrackRxEnSeedlessRdWrNoWindBLError ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 i; - SWEEP_INFO SweepData; - SweepData = *(SWEEP_INFO*)OptParam; - for (i = 0; i < ((TechPtr->NBPtr->MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) { - // - /// Skip Bytelanes that have already reached the desired result - // - if ((SweepData.ResultFound & ((UINT16)1 << i)) == 0) { - if (SweepData.TrnDelays[i] == SweepData.EndDelay) { - if ((SweepData.EndResult & ((UINT16) (1 << i))) != 0) { - TechPtr->ByteLaneError[i] = TRUE; - } else { - TechPtr->ByteLaneError[i] = FALSE; - } - } - } - } - return TRUE; -} -/*----------------------------------------------------------------------------- - * - * - * This function checks each bytelane for small window error. - * - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] OptParam - Optional parameter(Unused) - * - * @return TRUE - * ---------------------------------------------------------------------------- - */ -BOOLEAN -MemTTrackRxEnSeedlessRdWrSmallWindBLError ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT VOID *OptParam - ) -{ - TechPtr->ByteLaneError[TechPtr->Bytelane] = TRUE; - return TRUE; -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets the RxEn delay - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in,out] *RcvEnDly - Receiver Enable Delay - * @param[in,out] *ByteLane - Bytelane - * -*/ -VOID -STATIC -MemTRdPosRxEnSeedSetDly3 ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT UINT16 RcvEnDly, - IN OUT UINT8 ByteLane - ) -{ - TechPtr->NBPtr->ChannelPtr->RcvEnDlys[(TechPtr->ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane] = RcvEnDly; - TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((TechPtr->ChipSel >> 1), ByteLane), RcvEnDly); - TechPtr->NBPtr->FamilySpecificHook[ResetRxFifoPtr] (TechPtr->NBPtr, TechPtr->NBPtr); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function determines if the currert RxEn delay settings have failed - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * -*/ -VOID -STATIC -MemTRdPosRxEnSeedCheckRxEndly3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 MaxDlyDimm; - TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &MaxDlyDimm); - TechPtr->NBPtr->SetMaxLatency (TechPtr->NBPtr, TechPtr->MaxDlyForMaxRdLat); - TechPtr->DqsRdWrPosSaved = 0; - MemTTrainDQSEdgeDetect (TechPtr); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes RdDQS training and if fails adjusts the RxEn Gross results for - * each bytelane - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - All bytelanes pass - * @return FALSE - Some bytelanes fail -*/ -BOOLEAN -MemTRdPosWithRxEnDlySeeds3 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT8 ByteLane; - UINT16 PassTestRxEnDly[MAX_BYTELANES_PER_CHANNEL + 1]; - UINT16 FailTestRxEnDly[MAX_BYTELANES_PER_CHANNEL + 1]; - UINT16 FinalRxEnCycle[MAX_BYTELANES_PER_CHANNEL + 1]; - UINT16 RxOrig[MAX_BYTELANES_PER_CHANNEL]; - UINT8 i; - UINT8 j; - UINT8 NumBLWithTargetFound; - UINT8 MaxByteLanes; - INT16 RxEn; - BOOLEAN status; - BOOLEAN EsbNoDqsPosSave; - BOOLEAN OutOfRange[MAX_BYTELANES_PER_CHANNEL]; - BOOLEAN ByteLanePass[MAX_BYTELANES_PER_CHANNEL]; - BOOLEAN ByteLaneFail[MAX_BYTELANES_PER_CHANNEL]; - BOOLEAN RxEnMemClkTested[MAX_BYTELANES_PER_CHANNEL][MAX_POS_RX_EN_SEED_GROSS_RANGE]; - BOOLEAN RxEnMemClkSt[MAX_BYTELANES_PER_CHANNEL][MAX_POS_RX_EN_SEED_GROSS_RANGE]; - BOOLEAN RxEnDlyTargetFound[MAX_BYTELANES_PER_CHANNEL]; - BOOLEAN DlyWrittenToReg[MAX_BYTELANES_PER_CHANNEL]; - UINT16 RxEnDlyTargetValue[MAX_BYTELANES_PER_CHANNEL]; - UINT8 AllByteLanesOutOfRange; - UINT8 AllByteLanesSaved; - UINT8 TotalByteLanesCheckedForSaved; - UINT8 MemClkCycle; - MEM_NB_BLOCK *NBPtr; - CH_DEF_STRUCT *ChannelPtr; - NBPtr = TechPtr->NBPtr; - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - NumBLWithTargetFound = 0; - status = FALSE; - EsbNoDqsPosSave = TechPtr->NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos]; - NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_SUSPEND; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\nStart HW RxEn Seedless training\n\n"); - // 1. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][BlockRxDqsLock] = 1. - NBPtr->SetBitField (NBPtr, BFBlockRxDqsLock, 0x0100); - IDS_HDT_CONSOLE (MEM_FLOW, "\tChip Select: %02x \n", TechPtr->ChipSel); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tRxEn Orig: "); - // - // Start sweep loops for RxEn Seedless Training - // - MaxByteLanes = (TechPtr->NBPtr->MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8; //dmach - // - //Initialialize BL variables - // - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - OutOfRange[ByteLane] = FALSE; - ByteLanePass[ByteLane] = FALSE; - ByteLaneFail[ByteLane] = FALSE; - // 2. RxEnOrig = D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] result - // from 2.10.6.8.2 [Phy Assisted DQS Receiver Enable Training] - RxOrig[ByteLane] = TechPtr->RxOrig[ByteLane]; // Original RxEn Dly based on PRE results - RxEnDlyTargetFound[ByteLane] = FALSE; - RxEnDlyTargetValue[ByteLane] = 0; - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RxOrig[ByteLane]); - for (i = 0; i < MAX_POS_RX_EN_SEED_GROSS_RANGE; i++) { - RxEnMemClkTested[ByteLane][i] = FALSE; - } - } - // Start MemClk delay sweep - for (i = 0; i < MAX_POS_RX_EN_SEED_GROSS_RANGE; i++) { - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\ti: %02x\n", i); - // Start direction sweep (0, - Positive, 1 - negative) - for (j = 0; j < MAX_POS_RX_EN_SEED_GROSS_DIR; j++) { - // Edge detect may run twice to see Pass to fail transition - // It is not run if the value are already saved - // Fail test is only done if pass is found - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tj: %02x\n", j); - // Reset Bytelane Flags for next sweep - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - ByteLaneFail[ByteLane] = FALSE; - ByteLanePass[ByteLane] = FALSE; - OutOfRange[ByteLane] = FALSE; - } - if (i == 0 && j == 1) { - continue; // Since i & j are the same skip - } - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t Target BL Found: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", ((RxEnDlyTargetFound[ByteLane] == TRUE) ? 'Y' : 'N')); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t Target BL Value: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RxEnDlyTargetValue[ByteLane]); - } - ); - // - // Find the RxEn Delay for the Pass condition in the Pass to Fail transition - // "PassTestRxEnDly" - // - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t Setting PassTestRxEnDly\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t PassTestRxEnDly: "); - PassTestRxEnDly[ByteLane] = RxOrig[ByteLane]; - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - // Calculate "PassTestRxEnDly" from current "RxEnDly" - // 3. RxEnOffset = MOD(RxEnOrig + 0x10, 0x40) - RxEn = (j == 0) ? ((INT16)RxOrig[ByteLane] + 0x10 + (0x40*i)) : ((INT16)RxOrig[ByteLane] + 0x10 - (0x40*i)); - // Check if RxEnDly is in a valid range - if ((RxEn >= NBPtr->MinRxEnSeedGross) && (RxEn <= NBPtr->MaxRxEnSeedTotal)) { - PassTestRxEnDly[ByteLane] = (UINT16)RxEn; - // 4. For each DqsRcvEn value beginning from RxEnOffset incrementing by 1 MEMCLK: - // A. Program D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] with - // the current value. - MemTRdPosRxEnSeedSetDly3 (TechPtr, PassTestRxEnDly[ByteLane], ByteLane); - OutOfRange[ByteLane] = FALSE; - } else { - OutOfRange[ByteLane] = TRUE; - } - } else { - PassTestRxEnDly[ByteLane] = RxEnDlyTargetValue[ByteLane]; - } - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", PassTestRxEnDly[ByteLane]); - } - // Check if all BLs out of Range at "PassTestRxEnDly" - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t OutOfRange: "); - AllByteLanesOutOfRange = 0; - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (OutOfRange[ByteLane]) { - AllByteLanesOutOfRange++; - } - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (OutOfRange[ByteLane] == TRUE) ? 'Y' : 'N'); - } - if (AllByteLanesOutOfRange == MaxByteLanes) { - continue; // All BLs out of range, so skip - } - // Check if all BLs saved Results at "PassTestRxEnDly" - AllByteLanesSaved = 0; - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5); - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - if (!RxEnMemClkTested[ByteLane][MemClkCycle]) { - AllByteLanesSaved++; - } - } - } - // Check if "RxEnDlyValueForPassCond" passed - if (AllByteLanesSaved != 0) { - // At least one BL has not been saved, so check if "PassTestRxEnDly" passed - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t Checking if PassTestRxEnDly Passes?\n\n"); - // 4B. Perform 2.10.6.8.5 [DQS Position Training]. - // Record the result for the current DqsRcvEn setting as a pass or fail depending if a data eye is found. - MemTRdPosRxEnSeedCheckRxEndly3 (TechPtr); - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t Err Status: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (TechPtr->ByteLaneError[ByteLane] == TRUE) ? 'F' : 'P'); - } - ); - } else { - // All BLs saved, so use saved results for "PassTestRxEnDly" - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tAll BLs Saved at PassTestRxEnDly\n"); - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t Save Err Stat: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5); - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", ((RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE) ? 'F' : 'P')); - } - ); - } - // Update Saved values for "PassTestRxEnDly" - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - if (OutOfRange[ByteLane] == FALSE) { - MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5); - if (!RxEnMemClkTested[ByteLane][MemClkCycle]) { - RxEnMemClkTested[ByteLane][MemClkCycle] = TRUE; - RxEnMemClkSt[ByteLane][MemClkCycle] = TechPtr->ByteLaneError[ByteLane]; - } - } - } - } - // - // Find the RxEn Delay for the Fail condition in the Pass to Fail transition - // "FailTestRxEnDly" - // - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - DlyWrittenToReg[ByteLane] = FALSE; - } - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - FailTestRxEnDly[ByteLane] = PassTestRxEnDly[ByteLane] + 0x40; - } - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t FailTestRxEnDly: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", FailTestRxEnDly[ByteLane]); - } - ); - // Check if all BLs Saved Results at FailTestRxEnDly - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tSetting FailTestRxEnDly"); - AllByteLanesSaved = 0; - TotalByteLanesCheckedForSaved = 0; - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); - // Check if RxEnDly + 40 is valid - if ((FailTestRxEnDly[ByteLane] >= NBPtr->MinRxEnSeedGross) && (FailTestRxEnDly[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { - if (RxEnMemClkTested[ByteLane][MemClkCycle]) { - AllByteLanesSaved++; - } - OutOfRange[ByteLane] = FALSE; - } else { - OutOfRange[ByteLane] = TRUE; - } - TotalByteLanesCheckedForSaved++; - } - } - // Check if all BLs out of Range condition at FailTestRxEnDly - AllByteLanesOutOfRange = 0; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t OutOfRange: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (OutOfRange[ByteLane]) { - AllByteLanesOutOfRange++; - } - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (OutOfRange[ByteLane] == TRUE) ? 'Y' : 'N'); - } - if (AllByteLanesOutOfRange == MaxByteLanes) { - continue; // All BLs out of range, so skip - } - // Setting FailTestRxEnDly for any BL that was not saved - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t FailTestRxEnDly: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - MemClkCycle = (UINT8) (PassTestRxEnDly[ByteLane] >> 5); - // Check if New RxEnDly has Passed - if ((RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] : TechPtr->ByteLaneError[ByteLane]) == FALSE) { - if (OutOfRange[ByteLane] == FALSE) { - // BL has passed at "New RxEnDly", so check if "New RxEnDly" + 0x40 fails - MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); - if (!RxEnMemClkTested[ByteLane][MemClkCycle]) { - // Only Set Delays for ByteLanes that have not been already tested - MemTRdPosRxEnSeedSetDly3 (TechPtr, FailTestRxEnDly[ByteLane], ByteLane); - DlyWrittenToReg[ByteLane] = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'Y'); - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'N'); - } - ByteLanePass[ByteLane] = TRUE; - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'O'); - } - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'F'); - } - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'N'); - } - } - // Check if BLs that passed at PassTestRxEnDly fail at FailTestRxEnDly - if (AllByteLanesSaved != TotalByteLanesCheckedForSaved) { - // At least one BL has not been saved, so check if FailTestRxEnDly passed - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n\t\t Checking if FailTestRxEnDly Fails?\n"); - MemTRdPosRxEnSeedCheckRxEndly3 (TechPtr); - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t Err Status: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (TechPtr->ByteLaneError[ByteLane] == TRUE) ? 'F' : 'P'); - } - ); - } else { - // All BLs saved, so use saved results for FailTestRxEnDly - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tAll BLs Saved at PassTestRxEnDly\n"); - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); - IDS_HDT_CONSOLE (MEM_FLOW, "\t Save Err Stat: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE) ? 'F' : 'P'); - } - ); - } - // - // If BL failes at "FailTestRxEnDly" set FinalRxEnCycle - // - // Setting FinalRxEnCycle for any BL that Failed at FailTestRxEnDly - IDS_HDT_CONSOLE (MEM_FLOW, "\n Set FinalRxEnCycle: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); - if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; - if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { - // Since FailTestRxEnDly, we can set FinalRxEnCycle - MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); - ByteLaneFail[ByteLane] = TRUE; - OutOfRange[ByteLane] = FALSE; - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'Y'); - } else { - OutOfRange[ByteLane] = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'N'); - } - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'F'); - OutOfRange[ByteLane] = FALSE; - } - } else { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", 'Y'); - } - } - // Update Saved values for FailTestRxEnDly - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - if (OutOfRange[ByteLane] == FALSE) { - MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); - if (!RxEnMemClkTested[ByteLane][MemClkCycle] && DlyWrittenToReg[ByteLane]) { - RxEnMemClkTested[ByteLane][MemClkCycle] = TRUE; - RxEnMemClkSt[ByteLane][MemClkCycle] = TechPtr->ByteLaneError[ByteLane]; - } - } - } - } - // Check for out of Range condition - AllByteLanesOutOfRange = 0; - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t OutOfRange: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (OutOfRange[ByteLane]) { - AllByteLanesOutOfRange++; - } - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (OutOfRange[ByteLane] == TRUE) ? 'Y' : 'N'); - } - if (AllByteLanesOutOfRange == MaxByteLanes) { - continue; // All BLs out of range so skip - } - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\n FinalRxEnCycle: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", (UINT16) FinalRxEnCycle[ByteLane]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n ByteLaneFail: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (ByteLaneFail[ByteLane] == TRUE) ? 'Y' : 'N'); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n ByteLanePass: "); - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - IDS_HDT_CONSOLE (MEM_FLOW, " %c ", (ByteLanePass[ByteLane] == TRUE) ? 'Y' : 'N'); - } - ); - // - // Check for exit condition - // PassTestRxEnDly = Pass and FailTestRxEnDly[ByteLane] = Fail - // If found, use "FinalRxEnCycle" as final RxEnDly value - // - // 5. Process the array of results and determine a pass-to-fail transition. - NumBLWithTargetFound = 0; - for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { - if (RxEnDlyTargetFound[ByteLane] == FALSE) { - // Check if the current BL has found its target - if (ByteLanePass[ByteLane] == TRUE && ByteLaneFail[ByteLane] == TRUE) { - RxEnDlyTargetFound[ByteLane] = TRUE; - NumBLWithTargetFound++; - RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane]; - } else { - RxEnDlyTargetFound[ByteLane] = FALSE; - } - } else { - // BL has already failed and passed, so increment both flags - NumBLWithTargetFound++; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - // Check for exit condition - if (NumBLWithTargetFound == MaxByteLanes) { - // Exit condition found, so setting new RDQS based on RxEn-0x10 \n\n - IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Setting new RDQS based on FinalRxEnCycle \n\n"); - // 5 A. DqsRcvEnCycle = the total delay value of the pass result. - // B. Program D18F2x9C_x0000_00[2A:10]_dct[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] = - // DqsRcvEnCycle - 0x10. - NBPtr->RdDqsDlyRetrnStat = RDDQSDLY_RTN_NEEDED; - MemTRdPosRxEnSeedCheckRxEndly3 (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - status = TRUE; - break; - } else { - status = FALSE; - } - } - // Check for exit condition - if (NumBLWithTargetFound == MaxByteLanes) { - status = TRUE; - break; - } else { - status = FALSE; - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - TechPtr->NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = EsbNoDqsPosSave; - if (i == MAX_POS_RX_EN_SEED_GROSS_RANGE) { - TechPtr->NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE; - } - - // 6. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[1:0][BlockRxDqsLock] = 0. - NBPtr->SetBitField (NBPtr, BFBlockRxDqsLock, 0); - IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd HW RxEn Seedless training\n\n"); - return status; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttml.c deleted file mode 100644 index 4b16faa478..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttml.c +++ /dev/null @@ -1,259 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttml.c - * - * Technology Max Latency Training support - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_MTTML_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * This function trains Max latency for all dies - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTTrainMaxLatency ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - UINT32 TestAddrRJ16; - UINT8 Dct; - UINT8 ChipSel; - UINT8 *PatternBufPtr; - UINT8 *TestBufferPtr; - UINT8 CurrentNbPstate; - UINT16 CalcMaxLatDly; - UINT16 MaxLatDly; - UINT16 MaxLatLimit; - UINT16 Margin; - UINT16 CurTest; - UINT16 _CL_; - UINT8 TimesFail; - UINT8 TimesRetrain; - UINT16 i; - - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MCTPtr = NBPtr->MCTPtr; - MemPtr = NBPtr->MemPtr; - TechPtr->TrainingType = TRN_MAX_READ_LATENCY; - TimesRetrain = DEFAULT_TRAINING_TIMES; - IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart MaxRdLat training\n"); - // Set environment settings before training - AGESA_TESTPOINT (TpProcMemMaxRdLatencyTraining, &(MemPtr->StdHeader)); - MemTBeginTraining (TechPtr); - // - // Initialize the Training Pattern - // - if (AGESA_SUCCESS != NBPtr->TrainingPatternInit (NBPtr)) { - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); - } - TechPtr->PatternLength = (MCTPtr->Status[Sb128bitmode]) ? 6 : 3; - // - // Setup hardware training engine (if applicable) - // - NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType); - - MaxLatDly = 0; - _CL_ = TechPtr->PatternLength; - PatternBufPtr = TechPtr->PatternBufPtr; - TestBufferPtr = TechPtr->TestBufPtr; - // - // Begin max latency training - // - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - if (MCTPtr->Status[Sb128bitmode] && (Dct != 0)) { - break; - } - - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) { - TechPtr->ChipSel = ChipSel; - if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to address: %04x0000\n", TestAddrRJ16); - - // Write the test patterns - AGESA_TESTPOINT (TpProcMemMaxRdLatWritePattern, &(MemPtr->StdHeader)); - NBPtr->WritePattern (NBPtr, TestAddrRJ16, PatternBufPtr, _CL_); - - // Sweep max latency delays - NBPtr->getMaxLatParams (NBPtr, TechPtr->MaxDlyForMaxRdLat, &CalcMaxLatDly, &MaxLatLimit, &Margin); - AGESA_TESTPOINT (TpProcMemMaxRdLatStartSweep, &(MemPtr->StdHeader)); - - TimesFail = 0; - ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) - { - MaxLatDly = CalcMaxLatDly; - for (i = 0; i < (MaxLatLimit - CalcMaxLatDly); i++) { - NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", MaxLatDly); - TechPtr->ResetDCTWrPtr (TechPtr, 6); - - AGESA_TESTPOINT (TpProcMemMaxRdLatReadPattern, &(MemPtr->StdHeader)); - NBPtr->ReadPattern (NBPtr, TestBufferPtr, TestAddrRJ16, _CL_); - AGESA_TESTPOINT (TpProcMemMaxRdLatTestPattern, &(MemPtr->StdHeader)); - CurTest = NBPtr->CompareTestPattern (NBPtr, TestBufferPtr, PatternBufPtr, _CL_ * 64); - NBPtr->FlushPattern (NBPtr, TestAddrRJ16, _CL_); - - if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) { - // Reverse training decrements MaxLatDly whenever the test passes - // and uses the last passing MaxLatDly as left edge - if (CurTest == 0xFFFF) { - IDS_HDT_CONSOLE (MEM_FLOW, " P"); - if (MaxLatDly == 0) { - break; - } else { - MaxLatDly--; - } - } - } else { - // Traditional training increments MaxLatDly until the test passes - // and uses it as left edge - if (CurTest == 0xFFFF) { - IDS_HDT_CONSOLE (MEM_FLOW, " P"); - break; - } else { - MaxLatDly++; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - }// End of delay sweep - ERROR_HANDLE_RETRAIN_END ((MaxLatDly >= MaxLatLimit), TimesFail) - } - - AGESA_TESTPOINT (TpProcMemMaxRdLatSetDelay, &(MemPtr->StdHeader)); - - if (MaxLatDly >= MaxLatLimit) { - PutEventLog (AGESA_ERROR, MEM_ERROR_MAX_LAT_NO_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - NBPtr->DCTPtr->Timings.CsTrainFail |= NBPtr->DCTPtr->Timings.CsPresent; - MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct; - if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - return FALSE; - } - } else { - NBPtr->FamilySpecificHook[AddlMaxRdLatTrain] (NBPtr, &TestAddrRJ16); - - MaxLatDly = MaxLatDly + Margin; - if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) { - MaxLatDly++; // Add 1 to get back to the last passing value - } - // Set final delays - CurrentNbPstate = (UINT8) MemNGetBitFieldNb (NBPtr, BFCurNbPstate); - ASSERT (CurrentNbPstate <= 3); - NBPtr->ChannelPtr->DctMaxRdLat [CurrentNbPstate] = MaxLatDly; - NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFinal MaxRdLat: %03x\n", MaxLatDly); - - } - } - } - } - } - - // Restore environment settings after training - MemTEndTraining (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "End MaxRdLat training\n\n"); - // - // Finalize the Pattern - // - NBPtr->TrainingPatternFinalize (NBPtr); - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttoptsrc.c deleted file mode 100644 index aac8bb008d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttoptsrc.c +++ /dev/null @@ -1,428 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttoptsrc.c - * - * New Technology Software based DQS receiver enable training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_MTTOPTSRC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemTDqsTrainOptRcvrEnSw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ); - -BOOLEAN -MemTNewRevTrainingSupport ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return TRUE; -} - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes first pass of receiver enable training for all dies - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTTrainOptRcvrEnSwPass1 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return MemTDqsTrainOptRcvrEnSw (TechPtr, 1); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes receiver enable training for a specific die - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Pass - Pass of the receiver training - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -STATIC -MemTDqsTrainOptRcvrEnSw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ) -{ - _16BYTE_ALIGN UINT8 PatternBuffer[6 * 64]; - UINT8 TestBuffer[256]; - UINT8 *PatternBufPtr[6]; - UINT8 *TempPtr; - UINT32 TestAddrRJ16[4]; - UINT32 TempAddrRJ16; - UINT32 RealAddr; - UINT16 CurTest[4]; - UINT8 Dct; - UINT8 Receiver; - UINT8 i; - UINT8 TimesFail; - UINT8 TimesRetrain; - UINT16 RcvrEnDly; - UINT16 MaxRcvrEnDly; - UINT16 RcvrEnDlyLimit; - UINT16 MaxDelayCha; - BOOLEAN IsDualRank; - BOOLEAN S0En; - BOOLEAN S1En; - - - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - TechPtr->TrainingType = TRN_RCVR_ENABLE; - - - TempAddrRJ16 = 0; - TempPtr = NULL; - MaxDelayCha = 0; - TimesRetrain = DEFAULT_TRAINING_TIMES; - IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Optimized SW RxEn training\n"); - // Set environment settings before training - MemTBeginTraining (TechPtr); - - PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer; - // These two patterns used for first Test Address - MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64); - // Second Cacheline used for Dummy Read is the inverse of - // the first so that is is not mistaken for the real read - MemUFillTrainPattern (TestPattern1, PatternBufPtr[0] + 64, 64); - PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128; - // These two patterns used for second Test Address - MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64); - // Second Cacheline used for Dummy Read is the inverse of - // the first so that is is not mistaken for the real read - MemUFillTrainPattern (TestPattern0, PatternBufPtr[1] + 64, 64); - - // Fill pattern for flush after every sweep - PatternBufPtr[4] = PatternBufPtr[0] + 256; - MemUFillTrainPattern (TestPattern3, PatternBufPtr[4], 64); - - // Fill pattern for initial dummy read - PatternBufPtr[5] = PatternBufPtr[0] + 320; - MemUFillTrainPattern (TestPattern4, PatternBufPtr[5], 64); - - - // Begin receiver enable training - AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader)); - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - - // Set training bit - NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1); - - // Relax Max Latency before training - NBPtr->SetMaxLatency (NBPtr, 0xFFFF); - - if (Pass == FIRST_PASS) { - TechPtr->InitDQSPos4RcvrEn (TechPtr); - } - - // there are four receiver pairs, loosely associated with chipselects. - Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8; - for (; Receiver < 8; Receiver += 2) { - S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]); - S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]); - if (S0En) { - TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16; - } - if (S1En) { - TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16; - } - if (S0En && S1En) { - IsDualRank = TRUE; - } else { - IsDualRank = FALSE; - } - if (S0En || S1En) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Receiver); - - RcvrEnDlyLimit = 0x1FF; // @attention - limit depends on proc type - TechPtr->DqsRcvEnSaved = 0; - RcvrEnDly = RcvrEnDlyLimit; - RealAddr = 0; - - TechPtr->GetFirstPassVal = FALSE; - TechPtr->DqsRcvEnFirstPassVal = 0; - TechPtr->RevertPassVal = FALSE; - TechPtr->InitializeVariablesOpt (TechPtr); - - // Write the test patterns - AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to addresses: "); - for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { - RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); - // One cacheline of data to be tested and one of dummy data - MemUWriteCachelines (RealAddr, PatternBufPtr[i], 2); - // This is dummy data with a different pattern used for the first dummy read. - MemUWriteCachelines (RealAddr + 128, PatternBufPtr[5], 1); - IDS_HDT_CONSOLE (MEM_FLOW, " %04x0000 ", TestAddrRJ16[i]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - - // Sweep receiver enable delays - AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader)); - TimesFail = 0; - ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) - { - TechPtr->LoadInitialRcvrEnDlyOpt (TechPtr, Receiver); - while (!TechPtr->CheckRcvrEnDlyLimitOpt (TechPtr)) { - AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader)); - TechPtr->SetRcvrEnDlyOpt (TechPtr, Receiver, RcvrEnDly); - // Read and compare the first beat of data - for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { - AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader)); - RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); - // - // Issue dummy cacheline reads - // -#if 0 //KR make OPT DQS Receiver Enable training happy - MemUReadCachelines (TestBuffer + 128, RealAddr + 128, 1); - MemUReadCachelines (TestBuffer, RealAddr, 1); -#endif - MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr); - // - // Perform actual read which will be compared - // - MemUReadCachelines (TestBuffer + 64, RealAddr + 64, 1); - AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader)); - CurTest[i] = TechPtr->Compare1ClPatternOpt (TechPtr, TestBuffer + 64 , PatternBufPtr[i] + 64, i, Receiver, S1En); - // Due to speculative execution during MemUReadCachelines, we must - // flush one more cache line than we read. - MemUProcIOClFlush (TestAddrRJ16[i], 4, MemPtr); - TechPtr->ResetDCTWrPtr (TechPtr, Receiver); - - // - // Swap the test pointers such that even and odd steps alternate. - // - if ((i % 2) == 0) { - TempPtr = PatternBufPtr[i]; - PatternBufPtr[i] = PatternBufPtr[i + 1]; - - TempAddrRJ16 = TestAddrRJ16[i]; - TestAddrRJ16[i] = TestAddrRJ16[i + 1]; - } else { - PatternBufPtr[i] = TempPtr; - TestAddrRJ16[i] = TempAddrRJ16; - } - } - } // End of delay sweep - ERROR_HANDLE_RETRAIN_END (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, TRUE), TimesFail) - } - - if (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, FALSE)) { - return FALSE; - } - - TechPtr->LoadRcvrEnDlyOpt (TechPtr, Receiver); // set final delays - // - // Flush AA and 55 patterns by reading a dummy pattern to fill in FIFO - // - // Aquire a new FSBase, based on the last test address that we stored. - RealAddr = MemUSetUpperFSbase (TempAddrRJ16, MemPtr); - ASSERT (RealAddr != 0); - MemUWriteCachelines (RealAddr, PatternBufPtr[4], 1); - MemUWriteCachelines (RealAddr + 64, PatternBufPtr[4], 1); - MemUReadCachelines (TestBuffer, RealAddr, 2); - // Due to speculative execution during MemUReadCachelines, we must - // flush one more cache line than we read. - MemUProcIOClFlush (TempAddrRJ16, 3, MemPtr); - } - } // End while Receiver < 8 - - // Clear training bit when done - NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0); - - // Set Max Latency for both channels - MaxRcvrEnDly = TechPtr->GetMaxValueOpt (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly); - if (MCTPtr->GangedMode) { - if (Dct == 0) { - MaxDelayCha = MaxRcvrEnDly; - } else if (MaxRcvrEnDly > MaxDelayCha) { - NBPtr->SwitchDCT (NBPtr, 0); - NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); - } - } else { - NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); - } - TechPtr->ResetDCTWrPtr (TechPtr, 6); - } - - // Restore environment settings after training - MemTEndTraining (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "End Optimized SW RxEn training\n\n"); - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/*----------------------------------------------------------------------------- - * - * This function saves passing DqsRcvEnDly values to the stack - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Receiver - Current Chip select value - * @param[in] RcvEnDly - receiver enable delay to be saved - * @param[in] cmpResultRank0 - compare result for Rank 0 - * @param[in] cmpResultRank0 - compare result for Rank 1 - * - * @retval TRUE - All bytelanes pass - * FALSE - Some bytelanes fail - * ---------------------------------------------------------------------------- - */ - -BOOLEAN -MemTSaveRcvrEnDlyByteFilterOpt ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Receiver, - IN UINT16 RcvEnDly, - IN UINT16 CmpResultRank0, - IN UINT16 CmpResultRank1 - ) -{ - UINT8 i; - UINT8 Passed; - UINT8 Dimm; - CH_DEF_STRUCT *ChannelPtr; - - ASSERT (Receiver < MAX_CS_PER_CHANNEL); - ChannelPtr = TechPtr->NBPtr->ChannelPtr; - - Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF); - - Dimm = Receiver >> 1; - - if (TechPtr->GetFirstPassVal && (RcvEnDly - TechPtr->DqsRcvEnFirstPassVal) >= 0x30) { - for (i = 0; i < 8; i++) { - ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + i] = TechPtr->DqsRcvEnFirstPassVal + NEW_RECEIVER_FINAL_OFFSETVALUE; - } - TechPtr->DqsRcvEnSaved = 0xFF; - } - - if (Passed == 0xFF) { - if (!TechPtr->GetFirstPassVal) { - TechPtr->DqsRcvEnFirstPassVal = RcvEnDly; - TechPtr->GetFirstPassVal = TRUE; - } - return TRUE; - } else { - TechPtr->DqsRcvEnFirstPassVal = 0; - - // We have got first passing value, but later, we meet with glitch - if (TechPtr->GetFirstPassVal) { - TechPtr->DqsRcvEnFirstPassVal = 0xFF; - TechPtr->GetFirstPassVal = FALSE; - } - return FALSE; - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttsrc.c deleted file mode 100644 index 696c46eb34..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttsrc.c +++ /dev/null @@ -1,346 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mttsrc.c - * - * Technology Software based DQS receiver enable training - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Tech) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mu.h" -#include "mt.h" -#include "GeneralServices.h" -#include "merrhdl.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_TECH_MTTSRC_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -STATIC -MemTDqsTrainRcvrEnSw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes first pass of receiver enable training for all dies - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemTTrainRcvrEnSwPass1 ( - IN OUT MEM_TECH_BLOCK *TechPtr - ) -{ - return MemTDqsTrainRcvrEnSw (TechPtr, 1); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function executes receiver enable training for a specific die - * - * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK - * @param[in] Pass - Pass of the receiver training - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ -BOOLEAN -STATIC -MemTDqsTrainRcvrEnSw ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ) -{ - _16BYTE_ALIGN UINT8 PatternBuffer[3 * 64]; - UINT8 TestBuffer[120]; - UINT8 *PatternBufPtr[4]; - UINT8 *TempPtr; - UINT32 TestAddrRJ16[4]; - UINT32 TempAddrRJ16; - UINT32 RealAddr; - UINT16 CurTest[4]; - UINT8 Dct; - UINT8 Receiver; - UINT8 i; - UINT8 TimesFail; - UINT8 TimesRetrain; - UINT16 RcvrEnDly; - UINT16 MaxRcvrEnDly; - UINT16 RcvrEnDlyLimit; - UINT16 MaxDelayCha; - BOOLEAN IsDualRank; - BOOLEAN S0En; - BOOLEAN S1En; - UINT8 MaxFilterDly; - - MEM_DATA_STRUCT *MemPtr; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_NB_BLOCK *NBPtr; - - NBPtr = TechPtr->NBPtr; - MemPtr = NBPtr->MemPtr; - MCTPtr = NBPtr->MCTPtr; - TechPtr->TrainingType = TRN_RCVR_ENABLE; - - - TempAddrRJ16 = 0; - TempPtr = NULL; - MaxDelayCha = 0; - MaxFilterDly = TechPtr->MaxFilterDly; - RcvrEnDlyLimit = NBPtr->RcvrEnDlyLimit; - TimesRetrain = DEFAULT_TRAINING_TIMES; - IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader); - - IDS_HDT_CONSOLE (MEM_STATUS, "\nStart SW RxEn training\n"); - // Set environment settings before training - MemTBeginTraining (TechPtr); - - PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer; - MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64); - PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128; - MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64); - - // Begin receiver enable training - AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader)); - MaxRcvrEnDly = 0; - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - NBPtr->SwitchDCT (NBPtr, Dct); - DCTPtr = NBPtr->DCTPtr; - - // Set training bit - NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1); - - // Relax Max Latency before training - NBPtr->SetMaxLatency (NBPtr, 0xFFFF); - - if (Pass == FIRST_PASS) { - TechPtr->InitDQSPos4RcvrEn (TechPtr); - } - - // there are four receiver pairs, loosely associated with chipselects. - Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8; - for (; Receiver < 8; Receiver += 2) { - TechPtr->DqsRcvEnSaved = 0; - RcvrEnDly = RcvrEnDlyLimit; - S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]); - S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]); - if (S0En) { - TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16; - } - if (S1En) { - TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16; - } - if (S0En && S1En) { - IsDualRank = TRUE; - } else { - IsDualRank = FALSE; - } - - if (S0En || S1En) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Receiver); - - // Write the test patterns - AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader)); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to addresses: "); - for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { - RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); - MemUWriteCachelines (RealAddr, PatternBufPtr[i], 1); - IDS_HDT_CONSOLE (MEM_FLOW, " %04x0000 ", TestAddrRJ16[i]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - - // Initialize RcvrEnDly value and other DCT stored values - // MCTPtr->DqsRcvEnPass = Pass ? 0xFF : 0; - - // Sweep receiver enable delays - AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader)); - TimesFail = 0; - ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) - { - for (RcvrEnDly = 0; RcvrEnDly < RcvrEnDlyLimit; RcvrEnDly++) { - AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader)); - TechPtr->SetRcvrEnDly (TechPtr, Receiver, RcvrEnDly); - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", RcvrEnDly); - - // Read and compare the first beat of data - for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) { - AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader)); - RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr); - MemUReadCachelines (TestBuffer, RealAddr, 1); - AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader)); - CurTest[i] = TechPtr->Compare1ClPattern (TechPtr, TestBuffer, PatternBufPtr[i]); - // Due to speculative execution during MemUReadCachelines, we must - // flush one more cache line than we read. - MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr); - TechPtr->ResetDCTWrPtr (TechPtr, Receiver); - - // - // Swap the test pointers such that even and odd steps alternate. - // - if ((i % 2) == 0) { - TempPtr = PatternBufPtr[i]; - PatternBufPtr[i] = PatternBufPtr[i + 1]; - - TempAddrRJ16 = TestAddrRJ16[i]; - TestAddrRJ16[i] = TestAddrRJ16[i + 1]; - } else { - PatternBufPtr[i] = TempPtr; - TestAddrRJ16[i] = TempAddrRJ16; - } - } - - if (TechPtr->SaveRcvrEnDly (TechPtr, Receiver, RcvrEnDly, S0En ? (CurTest[0] & CurTest[1]) : 0xFFFF, S1En ? (CurTest[2] & CurTest[3]) : 0xFFFF)) { - // if all bytelanes pass - if (MaxRcvrEnDly < (RcvrEnDly - MaxFilterDly)) { - MaxRcvrEnDly = RcvrEnDly - MaxFilterDly; - } - break; - } - } // End of delay sweep - ERROR_HANDLE_RETRAIN_END ((RcvrEnDly > (RcvrEnDlyLimit - 1)), TimesFail) - } - - if (RcvrEnDly == RcvrEnDlyLimit) { - // no passing window - PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - } - - if (RcvrEnDly > (RcvrEnDlyLimit - 1)) { - // passing window too narrow, too far delayed - PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, MCTPtr); - DCTPtr->Timings.CsTrainFail |= DCTPtr->Timings.CsPresent & (UINT16) (3 << Receiver); - MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct; - if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - return FALSE; - } - } - } - - TechPtr->LoadRcvrEnDly (TechPtr, Receiver); // set final delays - } // End while Receiver < 8 - - // Clear training bit when done - NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0); - - // Set Max Latency for both channels - MaxRcvrEnDly += 0x20; // @attention - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly); - if (MCTPtr->GangedMode) { - if (Dct == 0) { - MaxDelayCha = MaxRcvrEnDly; - } else if (MaxRcvrEnDly > MaxDelayCha) { - NBPtr->SwitchDCT (NBPtr, 0); - NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); - } - } else { - NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly); - } - TechPtr->ResetDCTWrPtr (TechPtr, 6); - } - - // Restore environment settings after training - MemTEndTraining (TechPtr); - IDS_HDT_CONSOLE (MEM_FLOW, "End SW RxEn training\n\n"); - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/ma.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/ma.h deleted file mode 100644 index 17850069a3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/ma.h +++ /dev/null @@ -1,317 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * ma.h - * - * ARDK common header file - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _MA_H_ -#define _MA_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - - -#define MAX_CS_PER_CHANNEL 8 ///< Max CS per channel -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/** MARDK Structure*/ -typedef struct { - UINT16 Speed; ///< Dram speed in MHz - UINT8 Loads; ///< Number of Data Loads - UINT32 AddrTmg; ///< Address Timing value - UINT32 Odc; ///< Output Driver Compensation Value -} PSCFG_ENTRY; - -/** MARDK Structure*/ -typedef struct { - UINT16 Speed; ///< Dram speed in MHz - UINT8 Loads; ///< Number of Data Loads - UINT32 AddrTmg; ///< Address Timing value - UINT32 Odc; ///< Output Driver Compensation Value - UINT8 Dimms; ///< Number of Dimms -} ADV_PSCFG_ENTRY; - -/** MARDK Structure for RDIMMs*/ -typedef struct { - UINT16 Speed; ///< Dram speed in MHz - UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 - UINT32 AddrTmg; ///< Address Timing value - UINT16 RC2RC8; ///< RC2 and RC8 value //High byte: 1st pair value, Low byte: 2nd pair value - UINT8 Dimms; ///< Number of Dimms -} ADV_R_PSCFG_ENTRY; - -/** MARDK Structure*/ -typedef struct { - UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 - UINT32 PhyRODTCSLow; ///< Fn2_9C 180 - UINT32 PhyRODTCSHigh; ///< Fn2_9C 181 - UINT32 PhyWODTCSLow; ///< Fn2_9C 182 - UINT32 PhyWODTCSHigh; ///< Fn2_9C 183 - UINT8 Dimms; ///< Number of Dimms -} ADV_PSCFG_ODT_ENTRY; - -/** MARDK Structure for Write Levelization ODT*/ -typedef struct { - UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 - UINT8 PhyWrLvOdt[MAX_CS_PER_CHANNEL/2]; ///< WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm - UINT8 Dimms; ///< Number of Dimms -} ADV_R_PSCFG_WL_ODT_ENTRY; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -AGESA_STATUS -MemAGetPsCfgDef ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgRDr2 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgRDr3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUDr3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSDA2 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSDA3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSNi3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUNi3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSRb3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgURb3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSPh3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUPh3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUDA3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgRHy3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUHy3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgRC32_3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUC32_3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSLN3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgULN3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgSON3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUON3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgROr3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemAGetPsCfgUOr3 ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -UINT16 -MemAGetPsRankType ( - IN CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemRecNGetPsCfgDef ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -UINT16 -MemRecNGetPsRankType ( - IN CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemRecNGetPsCfgUDIMM3Nb ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemRecNGetPsCfgSODIMM3Nb ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -AGESA_STATUS -MemRecNGetPsCfgRDIMM3Nb ( - IN OUT MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN OUT CH_DEF_STRUCT *CurrentChannel - ); - -#endif /* _MA_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/memPage.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/memPage.h deleted file mode 100644 index 198fb08ad5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/memPage.h +++ /dev/null @@ -1,56 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for Memory Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * - */ -/* - ****************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************** - */ - -/** - * @page memmain Memory Component Documentation - * - * Additional documentation for the Memory component consists of - * - * - Maintenance Guides: - * - add here >>> - * - Design Guides: - * - add here >>> - * - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/merrhdl.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/merrhdl.h deleted file mode 100644 index f3d8616d36..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/merrhdl.h +++ /dev/null @@ -1,102 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mmerrhdl.h - * - * main error handling - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MMERRHDL_H_ -#define _MMERRHDL_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define EXCLUDE_ALL_DCT 0xFF -#define EXCLUDE_ALL_CHIPSEL 0xFF - -/// default times of training -#define DEFAULT_TRAINING_TIMES 1 - -/// number of us to wait in parallel training -#define PARALLEL_TRAINING_TIMEOUT 60000000 - -/// number of us to wait in PCI space access -#define PCI_ACCESS_TIMEOUT 10000000 -/// number of us to wait in special PCI space access which takes much longer than others -#define SPECIAL_PCI_ACCESS_TIMEOUT 20000000 - -/// Beginning of retrain handling, must be ended with the ending of the handling -#define ERROR_HANDLE_RETRAIN_BEGIN(counter, limit) while (counter < limit) - -/// Ending of retrain handling -#define ERROR_HANDLE_RETRAIN_END(condition, counter) \ -if (condition) { \ - counter ++; \ -} else { \ - break; \ -} - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemErrHandle ( - IN DIE_STRUCT *MCTPtr, - IN UINT8 DCT, - IN UINT16 ChipSelMask, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif /* _MMERRHDL_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mfParallelTraining.h deleted file mode 100644 index 10880b004e..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfParallelTraining.h +++ /dev/null @@ -1,112 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfParallelTraining.h - * - * Header file for the parallel training feature - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFPARALLELTRAINING_H_ -#define _MFPARALLELTRAINING_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -typedef BOOLEAN (*REMOTE_NBBLOCK_CONSTRUCTOR) ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN DIE_STRUCT *MCTPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr -); - -///< This structure defines the environment on the AP for parallel training -typedef struct _REMOTE_TRAINING_ENV { - IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Config pointer of BSP - IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info - IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling - IN REMOTE_NBBLOCK_CONSTRUCTOR NBBlockCtor; ///< NB Block constructor - IN MEM_FEAT_BLOCK_NB *FeatPtr; ///< Feature block pointer - IN UINT8 *TableBasedAlterations; ///< Point to an array of data bytes describing desired modifications to register settings - IN PSO_TABLE *PlatformMemoryConfiguration; ///< Point to platform config table - IN UINT32 HoleBase; ///< Used for Memtyping - IN UINT32 UmaSize; ///< Used for Memtyping - IN UINT16 BottomIo; ///< Used for Memtyping - IN UINT32 SysLimit; ///< Used for Memtyping - IN UINT8 BspSocket; ///< Socket number of BSP - IN UINT8 BspCore; ///< Core number of BSP - IN DIE_STRUCT DieStruct; ///< Remote copy of Die Struct -} REMOTE_TRAINING_ENV; - -///< This structure defines Die information -typedef struct _DIE_INFO { - IN OUT UINT8 Socket; ///< Socket number - IN OUT UINT8 Core; ///< Core number - IN OUT BOOLEAN Training; ///< Training Flag, 1 = Training has been started on this core -} DIE_INFO; - - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFParallelTraining ( - IN OUT REMOTE_TRAINING_ENV *EnvPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -#endif /* _MFPARALLELTRAINING_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mfStandardTraining.h deleted file mode 100644 index f342fb95d5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfStandardTraining.h +++ /dev/null @@ -1,80 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfStandardTraining.h - * - * Feature implementation of standard function which performs memory training - * from the BSP only - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFSTANDARDTRAINING_H_ -#define _MFSTANDARDTRAINING_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -BOOLEAN -MemFStandardTraining ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFSTANDARDTRAINING_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mfmemclr.h deleted file mode 100644 index 416270d62f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfmemclr.h +++ /dev/null @@ -1,82 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfmemclr.h - * - * Feature Functions For Memory Clear Operation - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - -#ifndef _MFMEMCLR_H_ -#define _MFMEMCLR_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemFMctMemClr_Init ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemFMctMemClr_Sync ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MFMEMCLR_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mfs3.h deleted file mode 100644 index 78c6ddb239..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mfs3.h +++ /dev/null @@ -1,356 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mfS3.h - * - * S3 resume memory related functions. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/S3) - * @e \$Revision: 51373 $ @e \$Date: 2011-04-21 13:10:59 -0600 (Thu, 21 Apr 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _MFS3_H_ -#define _MFS3_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define PRESELFREF 0 -#define POSTSELFREF 1 -#define DCT0 0 -#define DCT1 1 -#define DCT0_MASK 0x1 -#define DCT1_MASK 0x2 -#define DCT0_NBPSTATE_SUPPORT_MASK 0x4 -#define DCT1_NBPSTATE_SUPPORT_MASK 0x8 -#define DCT0_DDR3_MASK 0x10 -#define DCT1_DDR3_MASK 0x20 -#define NODE_WITHOUT_DIMM_MASK 0x80 -#define DCT0_ANY_DIMM_MASK 0x55 -#define DCT1_ANY_DIMM_MASK 0xAA -#define ANY_DIMM_MASK 0xFF - -#define DCT_PHY_FLAG 0 -#define DCT_EXTRA_FLAG 1 -#define SET_S3_SPECIAL_OFFSET(AccessType, Dct, Offset) ((AccessType << 11) | (Dct << 10) | Offset) - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ -/// struct for all the descriptor for pre exit self refresh and post exit self refresh -typedef struct _DESCRIPTOR_GROUP { - PCI_DEVICE_DESCRIPTOR PCIDevice[2]; ///< PCI device descriptor - CONDITIONAL_PCI_DEVICE_DESCRIPTOR CPCIDevice[2]; ///< Conditional PCI device descriptor - MSR_DEVICE_DESCRIPTOR MSRDevice[2]; ///< MSR device descriptor - CONDITIONAL_MSR_DEVICE_DESCRIPTOR CMSRDevice[2]; ///< Conditional MSR device descriptor -} DESCRIPTOR_GROUP; - -/// Northbridge block to be used in S3 resume and save. -typedef struct _S3_MEM_NB_BLOCK { - UINT8 MemS3SpecialCaseHeapSize; ///< Heap size for the special case register heap. - struct _MEM_NB_BLOCK *NBPtr; ///< Pointer to the north bridge block. - VOID (*MemS3ExitSelfRefReg) (MEM_NB_BLOCK *NBPtr, AMD_CONFIG_PARAMS *StdHeaderPtr); ///< S3 Exit self refresh register - VOID (*MemS3GetConPCIMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for PCI register setting - VOID (*MemS3GetConMSRMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for MSR register setting - UINT16 (*MemS3GetRegLstPtr) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get register list pointer for both PCI and MSR register - BOOLEAN (*MemS3Resume) (struct _S3_MEM_NB_BLOCK *S3NBPtr, UINT8 NodeID);///< Exit Self Refresh - VOID (*MemS3RestoreScrub) (MEM_NB_BLOCK *NBPtr, UINT8 NodeID);///< Restore scrubber base - AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, VOID **RegisterHeader); ///< Get register list for a device -} S3_MEM_NB_BLOCK; - -/// Header for heap space to store the special case register. -typedef struct _S3_SPECIAL_CASE_HEAP_HEADER { - UINT8 Node; ///< Node ID for the the header - UINT8 Offset; ///< Offset for the target node -} S3_SPECIAL_CASE_HEAP_HEADER; -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -AmdMemS3Resume ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemS3ResumeInitNB ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemS3Deallocate ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemFS3GetPciDeviceRegisterList ( - IN PCI_DEVICE_DESCRIPTOR *Device, - OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemFS3GetCPciDeviceRegisterList ( - IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, - OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemFS3GetMsrDeviceRegisterList ( - IN MSR_DEVICE_DESCRIPTOR *Device, - OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemFS3GetCMsrDeviceRegisterList ( - IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, - OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -MemFS3GetDeviceList ( - IN OUT DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -MemFS3Wait10ns ( - IN UINT32 Count, - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -BOOLEAN -MemNS3ResumeNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNS3ResumeClientNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ); - -BOOLEAN -MemNS3ResumeUNb ( - IN OUT S3_MEM_NB_BLOCK *S3NBPtr, - IN UINT8 NodeID - ); - -VOID -MemNS3GetConPCIMaskNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ); - -VOID -MemNS3GetConPCIMaskUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ); - -VOID -MemNS3GetCSRNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetCSRNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3GetBitFieldNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetBitFieldNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3RestoreScrubNb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Node - ); - -AGESA_STATUS -MemS3InitNB ( - IN OUT S3_MEM_NB_BLOCK **S3NBPtr, - IN OUT MEM_DATA_STRUCT **MemPtr, - IN OUT MEM_MAIN_DATA_BLOCK *mmData, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -MemNS3DisNbPsDbgNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3EnNbPsDbg1Nb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetDynModeChangeNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3DisableChannelNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetDisAutoCompUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetPreDriverCalUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -BOOLEAN -MemNS3DctCfgSelectUnb ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN VOID *Dct - ); - -VOID -MemNS3GetNBPStateDepRegUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetNBPStateDepRegUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SaveNBRegiserUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3RestoreNBRegiserUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetMemClkFreqValUnb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3ChangeMemPStateContextNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -VOID -MemNS3SetPhyClkDllFineClientNb ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN OUT VOID *Value, - IN OUT VOID *ConfigPtr - ); - -#endif //_MFS3_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mftds.h deleted file mode 100644 index 2c7af8b0fb..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mftds.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mftds.h - * - * Memory Controller - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * - **/ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * *************************************************************************** - * - */ - - -#ifndef _MFTDS_H_ -#define _MFTDS_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -VOID -MemFInitTableDrive ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 time - ); -#endif /* _MFTDS_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mm.h deleted file mode 100644 index 084c0fd3b9..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mm.h +++ /dev/null @@ -1,1307 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mm.h - * - * Common main functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 58718 $ @e \$Date: 2011-09-05 23:23:08 -0600 (Mon, 05 Sep 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _MM_H_ -#define _MM_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -#define ALLOC_SOCKET_STRUCT_HANDLE 0 -#define ALLOC_DIE_STRUCT_HANDLE 1 -#define ALLOC_DCT_STRUCT_HANDLE 2 -#define ALLOC_CHL_STRUCT_HANDLE 3 -#define ALLOC_PLATFORM_PTR_HANDLE 4 -#define ALLOC_FORM_FACTOR_HANDLE 5 -#define ALLOC_TRN_DATA_HANDLE 6 -#define ALLOC_DIMM_DATA_HANDLE 7 -#define ALLOC_PAR_TRN_HANDLE 8 -#define ALLOC_NB_REG_TABLE 9 - -#define GENERATE_MEM_HANDLE(type, x, y, z) (\ - AMD_MEM_MISC_HANDLES_START + (((type) << 18) + ((x) << 12) + ((y) << 6) + (z)) \ -) - -/// Heap handle for each supported family's NB register table -typedef enum { - NbRegTabDR, ///< Heap handle for DR NB register table - NbRegTabDA, ///< Heap handle for DA NB register table - NbRegTabC32, ///< Heap handle for C32 NB register table - NbRegTabHY, ///< Heap handle for HY NB register table - NbRegTabKR, ///< Heap handle for KR NB register table - NbRegTabLN, ///< Heap handle for LN NB register table - NbRegTabON, ///< Heap handle for ON NB register table - NbRegTabOR, ///< Heap handle for OR NB register table - NbRegTabTN, ///< Heap handle for TN NB register table - NumberOfNbRegTables ///< Number of families that have NB register tables -} NB_REG_TAB_HANDLE; - - -#define VOLT1_5_ENCODED_VAL 0 -#define VOLT1_35_ENCODED_VAL 1 -#define VOLT1_25_ENCODED_VAL 2 -#define CONVERT_VDDIO_TO_ENCODED(VddIo) (\ - (VddIo == VOLT1_5) ? VOLT1_5_ENCODED_VAL : ((VddIo == VOLT1_35) ? VOLT1_35_ENCODED_VAL : ((VddIo == VOLT1_25) ? VOLT1_25_ENCODED_VAL : 0xFF)) \ -) -#define CONVERT_ENCODED_TO_VDDIO(EncodedVal) (\ - (EncodedVal == VOLT1_5_ENCODED_VAL) ? VOLT1_5 : ((EncodedVal == VOLT1_35_ENCODED_VAL) ? VOLT1_35 : ((EncodedVal == VOLT1_25_ENCODED_VAL) ? VOLT1_25 : VOLT_UNSUPPORTED)) \ -) -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/// Bit field names used in memory initialization -typedef enum { - BFDevVendorIDReg, ///< Bit field DevVendorIDReg - BFNodeID, ///< Bit field NodeID - BFNodeCnt, ///< Bit field NodeCnt - - BFDramBaseReg0, ///< Bit field DramBaseReg0 - BFDramBaseReg1, ///< Bit field DramBaseReg1 - BFDramBaseReg2, ///< Bit field DramBaseReg2 - BFDramBaseReg3, ///< Bit field DramBaseReg3 - BFDramBaseReg4, ///< Bit field DramBaseReg4 - BFDramBaseReg5, ///< Bit field DramBaseReg5 - BFDramBaseReg6, ///< Bit field DramBaseReg6 - BFDramBaseReg7, ///< Bit field DramBaseReg7 - - BFDramLimitReg0, ///< Bit field DramLimitReg0 - BFDramLimitReg1, ///< Bit field DramLimitReg1 - BFDramLimitReg2, ///< Bit field DramLimitReg2 - BFDramLimitReg3, ///< Bit field DramLimitReg3 - BFDramLimitReg4, ///< Bit field DramLimitReg4 - BFDramLimitReg5, ///< Bit field DramLimitReg5 - BFDramLimitReg6, ///< Bit field DramLimitReg6 - BFDramLimitReg7, ///< Bit field DramLimitReg7 - - BFDramBaseHiReg0, ///< Bit field DramBaseHiReg0 - BFDramBaseHiReg1, ///< Bit field DramBaseHiReg1 - BFDramBaseHiReg2, ///< Bit field DramBaseHiReg2 - BFDramBaseHiReg3, ///< Bit field DramBaseHiReg3 - BFDramBaseHiReg4, ///< Bit field DramBaseHiReg4 - BFDramBaseHiReg5, ///< Bit field DramBaseHiReg5 - BFDramBaseHiReg6, ///< Bit field DramBaseHiReg6 - BFDramBaseHiReg7, ///< Bit field DramBaseHiReg7 - - BFDramLimitHiReg0, ///< Bit field DramLimitHiReg0 - BFDramLimitHiReg1, ///< Bit field DramLimitHiReg1 - BFDramLimitHiReg2, ///< Bit field DramLimitHiReg2 - BFDramLimitHiReg3, ///< Bit field DramLimitHiReg3 - BFDramLimitHiReg4, ///< Bit field DramLimitHiReg4 - BFDramLimitHiReg5, ///< Bit field DramLimitHiReg5 - BFDramLimitHiReg6, ///< Bit field DramLimitHiReg6 - BFDramLimitHiReg7, ///< Bit field DramLimitHiReg7 - - BFDramHoleAddrReg, ///< Bit field DramHoleAddrReg - - BFCSBaseAddr0Reg, ///< Bit field CSBaseAddr0Reg - BFCSBaseAddr1Reg, ///< Bit field CSBaseAddr1Reg - BFCSBaseAddr2Reg, ///< Bit field CSBaseAddr2Reg - BFCSBaseAddr3Reg, ///< Bit field CSBaseAddr3Reg - BFCSBaseAddr4Reg, ///< Bit field CSBaseAddr4Reg - BFCSBaseAddr5Reg, ///< Bit field CSBaseAddr5Reg - BFCSBaseAddr6Reg, ///< Bit field CSBaseAddr6Reg - BFCSBaseAddr7Reg, ///< Bit field CSBaseAddr7Reg - - BFCSMask0Reg, ///< Bit field CSMask0Reg - BFCSMask1Reg, ///< Bit field CSMask1Reg - BFCSMask2Reg, ///< Bit field CSMask2Reg - BFCSMask3Reg, ///< Bit field CSMask3Reg - - BFRankDef0, ///< Bit field RankDef 0 - BFRankDef1, ///< Bit field RankDef 1 - BFRankDef2, ///< Bit field RankDef 2 - BFRankDef3, ///< Bit field RankDef 3 - - BFDramControlReg, ///< Bit field DramControlReg - BFDramInitRegReg, ///< Bit field DramInitRegReg - BFDramBankAddrReg, ///< Bit field DramBankAddrReg - BFDramMRSReg, ///< Bit field DramMRSReg - BFDramTimingLoReg, ///< Bit field DramTimingLoReg - BFDramTimingHiReg, ///< Bit field DramTimingHiReg - BFDramConfigLoReg, ///< Bit field DramConfigLoReg - BFDramConfigHiReg, ///< Bit field DramConfigHiReg - BFDctAddlOffsetReg, ///< Bit field DctAddlOffsetReg - BFDctAddlDataReg, ///< Bit field DctAddlDataReg - BFDctAccessDone, ///< Bit field DctAccessDone - BFDctAccessError, ///< Bit field DctAccessError - BFDctExtraOffsetReg, ///< Bit field DctExtraOffsetReg - BFDctExtraDataReg, ///< Bit field DctExtraDataReg - BFDctExtraAccessDone, ///< Bit field DctExtraAccessDone - BFDramConfigMiscReg, ///< Bit field DramConfigMiscReg - BFDramCtrlMiscReg2, ///< Bit field DramCtrlMiscReg2 - BFMctCfgHiReg, ///< Bit field MctCfgHiReg - BFMctCfgLoReg, ///< Bit field MctCfgLoReg - BFExtMctCfgLoReg, ///< Bit field ExtMctCfgLoReg - BFExtMctCfgHiReg, ///< Bit field ExtMctCfgHiReg - BFDcqBwThrotWm, ///< Bit field DcqBwThrotWm - BFPrefFiveConf, ///< Bit field PrefFiveConf - BFPrefFourConf, ///< Bit field PrefFourConf - BFEnSplitDctLimits, ///< Bit field EnSplitDctLimits - BFDcqBwThrotWm1, ///< Bit field DcqBwThrotWm1 - BFDcqBwThrotWm2, ///< Bit field DcqBwThrotWm2 - - BFCSMapCKE, ///< Bit field CSMapCKE - BFTrdrdBan, ///< Bit field TrdrdBan - BFTzqcs, ///< Bit field Tzqcs - BFTzqoper, ///< Bit field Tzqoper - - BFDramHoleBase, ///< Bit field DramHoleBase - BFDramHoleOffset, ///< Bit field DramHoleOffset - BFDramMemHoistValid, ///< Bit field DramMemHoistValid - BFDramHtHoleValid, ///< Bit field BFDramHtHoleValid - BFDramHoleValid, ///< Bit field DramHoleValid - BFDramBaseAddr, ///< Bit field DramBaseAddr - BFDramIntlvSel, ///< Bit field DramIntlvSel - BFDramLimitAddr, ///< Bit field DramLimitAddr - BFDramIntlvEn, ///< Bit field DramIntlvEn - BFMemPsSel, ///< Bit field MemPsSel - BFDctCfgSel, ///< Bit field DctCfgSel - BFRcvParErr, ///< Bit field RcvParErr - - BFDctBaseReg0, ///< Bit field DctBaseReg0 - BFDctBaseReg1, ///< Bit field DctBaseReg1 - BFDctBaseReg2, ///< Bit field DctBaseReg2 - BFDctBaseReg3, ///< Bit field DctBaseReg3 - - BFDctLimitReg0, ///< Bit field DctLimitReg0 - BFDctLimitReg1, ///< Bit field DctLimitReg1 - BFDctLimitReg2, ///< Bit field DctLimitReg2 - BFDctLimitReg3, ///< Bit field DctLimitReg3 - - BFDctHighAddressOffsetReg0, ///< Bit field DctHighAddressOffsetReg0 - BFDctHighAddressOffsetReg1, ///< Bit field DctHighAddressOffsetReg1 - BFDctHighAddressOffsetReg2, ///< Bit field DctHighAddressOffsetReg2 - - BFDctTriChannelInterleaveReg0, ///< Bit field DctTriChannelInterleaveReg0 - BFDctTriChannelInterleaveReg1, ///< Bit field DctTriChannelInterleaveReg1 - BFDctTriChannelInterleaveReg2, ///< Bit field DctTriChannelInterleaveReg2 - BFDctTriChannelInterleaveReg3, ///< Bit field DctTriChannelInterleaveReg3 - BFDctTriChannelInterleaveReg4, ///< Bit field DctTriChannelInterleaveReg4 - BFDctTriChannelInterleaveReg5, ///< Bit field DctTriChannelInterleaveReg5 - BFDctTriChannelInterleaveReg6, ///< Bit field DctTriChannelInterleaveReg6 - BFDctTriChannelInterleaveReg7, ///< Bit field DctTriChannelInterleaveReg7 - - BF3DStackHeight0, ///< Bit field 3DStackHeight0 - BF3DStackHeight1, ///< Bit field 3DStackHeight1 - BF3DStackHeight2, ///< Bit field 3DStackHeight2 - BF3DStackHeight3, ///< Bit field 3DStackHeight3 - - BFIdleCycLowLimit, ///< Bit field IdleCycLowLimit - BFPendRefPayback, ///< Bit field PendRefPayback - BFProcOdtDis, ///< Bit field ProcOdtDis - - - - BFMcaNbCtlReg, ///< Bit field McaNbCtlReg - BFDramEccEn, ///< Bit field DramEccEn - BFSyncOnUcEccEn, ///< Bit field SyncOnUcEccEn - BFEccSymbolSize, ///< Bit field EccSymbolSize - BFMcaNbStatusLoReg, ///< Bit field McaNbStatusLoReg - BFMcaNbStatusHiReg, ///< Bit field McaNbStatusHiReg - BFDramScrub, ///< Bit field DramScrub - BFL2Scrub, ///< Bit field L2Scrub - BFDcacheScrub, ///< Bit field DcacheScrub - BFL3Scrub, ///< Bit field L3Scrub - BFScrubReDirEn, ///< Bit field ScrubReDirEn - BFScrubAddrLoReg, ///< Bit field ScrubAddrLoReg - BFScrubAddrHiReg, ///< Bit field ScrubAddrHiReg - BFC1ClkDivisor, ///< Bit field C1ClkDivisor - BFDisDatMsk, ///< Bit field DisDatMsk - BFNbFid, ///< Bit field NbFid - BFMTC1eEn, ///< Bit field MTC1eEn - BFL3Capable, ///< Bit field L3Capable - BFReserved00B, ///< Bit field BFReserved00B - BFEnhMemProtCap, ///< Bit field EnhMemProtCap - BFNbPsForceReq, ///< Bit field NbPsForceReq - BFNbPsCtrlDis, ///< Bit field NbPsCtrlDis - BFNbPsCap, ///< Bit field NbPsCap - - BFNonSPDHi, ///< Bit field NonSPDHi - BFRdPtrInit, ///< Bit field RdPtrInit - BFReserved001, ///< Bit field Reserved001 - BFDqsRcvEnTrain, ///< Bit field DqsRcvEnTrain - BFEarlyArbEn, ///< Bit field EarlyArbEn - BFMaxLatency, ///< Bit field either MaxRdLat or MaxAsyncLat - - BFMrsAddress, ///< Bit field MrsAddress - BFMrsBank, ///< Bit field MrsBank - BFMrsChipSel, ///< Bit field MrsChipSel - BFSendPchgAll, ///< Bit field SendPchgAll - BFSendAutoRefresh, ///< Bit field SendAutoRefresh - BFSendMrsCmd, ///< Bit field SendMrsCmd - BFDeassertMemRstX, ///< Bit field DeassertMemRstX - BFAssertCke, ///< Bit field AssertCke - BFSendZQCmd, ///< Bit field SendZQCmd - BFSendCtrlWord, ///< Bit field SendCtrlWord - BFEnDramInit, ///< Bit field EnDramInit - BFMrsLevel, ///< Bit field MrsLevel - BFMrsQoff, ///< Bit field MrsQoff - BFMrsAddressHi, ///< Bit field MrsAddress [17:13] - - BFBurstCtrl, ///< Bit field BurstCtrl - BFDrvImpCtrl, ///< Bit field DrvImpCtrl - BFDramTerm_DDR3, ///< Bit field DramTerm_DDR3 - BFDramTermDyn, ///< Bit field DramTermDyn - BFQoff, ///< Bit field Qoff - BFASR, ///< Bit field ASR - BFSRT, ///< Bit field SRT - BFTcwl, ///< Bit field Tcwl - BFPchgPDModeSel, ///< Bit field PchgPDModeSel - BFLowPowerDefault, ///< Bit field LowPowerDefault - - BFTwrDDR3, ///< Bit field TwrDDR3 - BFTcl, ///< Bit field Tcl - BFTrcd, ///< Bit field Trcd - BFTrp, ///< Bit field Trp - BFTrtp, ///< Bit field Trtp - BFTras, ///< Bit field Tras - BFTrc, ///< Bit field Trc - BFTwr, ///< Bit field Twr - BFTrrd, ///< Bit field Trrd - BFMemClkDis, ///< Bit field MemClkDis - BFDramTiming0, ///< Bit field BFDramTiming0 - BFDramTiming1, ///< Bit field BFDramTiming1 - BFDramTiming2, ///< Bit field BFDramTiming2 - BFDramTiming3, ///< Bit field BFDramTiming3 - BFDramTiming4, ///< Bit field BFDramTiming4 - BFDramTiming5, ///< Bit field BFDramTiming5 - BFDramTiming6, ///< Bit field BFDramTiming6 - BFDramTiming10, ///< Bit field BFDramTiming10 - BFDramNBP0, ///< Bit field BFDramNBP0 - - BFNonSPD, ///< Bit field NonSPD - BFTrwtWB, ///< Bit field TrwtWB - BFTrwtTO, ///< Bit field TrwtTO - BFTwtr, ///< Bit field Twtr - BFTwrrd, ///< Bit field Twrrd - BFTwrrdHi, ///< Bit field TwrrdHi - BFTwrwr, ///< Bit field Twrwr - BFTwrwrHi, ///< Bit field TwrwrHi - BFTrdrdSD, ///< Bit field TrdrdSD - BFTwrwrSD, ///< Bit field TwrwrSD - BFTwrrdSD, ///< Bit field TwrrdSD - BFTmod, ///< Bit field Tmod - BFTmrd, ///< Bit field Tmrd - BFRdOdtTrnOnDly, ///< Bit field RdOdtTrnOnDly - BFRdOdtOnDuration, ///< Bit field RdOdtOnDuration - BFWrOdtTrnOnDly, ///< Bit field WrOdtTrnOnDly - BFWrOdtOnDuration, ///< Bit field WrOdtOnDuration - BFPrtlChPDDynDly, ///< Bit field PrtlChPDDynDly - - BFAggrPDDelay, ///< Bit field AggrPDDelay - BFPchgPDEnDelay, ///< Bit field PchgPDEnDelay - - BFTrdrd, ///< Bit field Trdrd - BFTrdrdHi, ///< Bit field TrdrdHi - BFTref, ///< Bit field Tref - BFDisAutoRefresh, ///< Bit field DisAutoRefresh - BFTrfc0, ///< Bit field Trfc0 - BFTrfc1, ///< Bit field Trfc1 - BFTrfc2, ///< Bit field Trfc2 - BFTrfc3, ///< Bit field Trfc3 - - BFInitDram, ///< Bit field InitDram - BFExitSelfRef, ///< Bit field ExitSelfRef - BFDramTerm, ///< Bit field DramTerm - BFParEn, ///< Bit field ParEn - BFBurstLength32, ///< Bit field BurstLength32 - BFWidth128, ///< Bit field Width128 - BFX4Dimm, ///< Bit field X4Dimm - BFDimmEccEn, ///< Bit field DimmEccEn - BFUnBuffDimm, ///< Bit field UnBuffDimm - BFEnterSelfRef, ///< Bit field EnterSelfRef - BFDynPageCloseEn, ///< Bit field DynPageCloseEn - BFIdleCycInit, ///< Bit field IdleCycInit - BFFreqChgInProg, ///< Bit field FreqChgInProg - BFForceAutoPchg, ///< Bit field ForceAutoPchg - BFStagRefEn, ///< Bit field StagRefEn - BFPendRefPaybackS3En, ///< Bit field PendRefPaybackS3En - BFEnDispAutoPrecharge, ///< Bit field EnDispAutoPrecharge - BFDisDllShutdownSR, ///< Bit field DisDllShutdownSR - BFDisSscClkGateData, ///< Bit field DisSscClkGateData - BFDisSscClkGateCmdAddr, ///< Bit field DisSscClkGateCmdAddr - BFDisSimulRdWr, ///< Bit field DisSimulRdWr - - BFMemClkFreq, ///< Bit field MemClkFreq - BFMemClkFreqVal, ///< Bit field MemClkFreqVal - BFDdr3Mode, ///< Bit field Ddr3Mode - BFLegacyBiosMode, ///< Bit field LegacyBiosMode - BFZqcsInterval, ///< Bit field ZqcsInterval - BFRDqsEn, ///< Bit field RDqsEn - BFDisDramInterface, ///< Bit field DisDramInterface - BFPowerDownEn, ///< Bit field PowerDownEn - BFPowerDownMode, ///< Bit field PowerDownMode - BFFourRankSoDimm, ///< Bit field FourRankSoDimm - BFDcqArbBypassEn, ///< Bit field DcqArbBypassEn - BFFourRankRDimm, ///< Bit field FourRankRDimm - BFSlowAccessMode, ///< Bit field SlowAccessMode - BFBankSwizzleMode, ///< Bit field BankSwizzleMode - BFDcqBypassMax, ///< Bit field DcqBypassMax - BFFourActWindow, ///< Bit field FourActWindow - BFDphyMemPsSelEn, ///< Bit field BFDphyMemPsSelEn - - BFODTSEn, ///< Bit field ODTSEn - BFCmdThrottleMode, ///< Bit field CmdThrottleMode - BFBwCapEn, ///< Bit field BwCapEn - - BFDdr3FourSocketCh, ///< Bit field Ddr3FourSocketCh - BFSubMemclkRegDly, ///< Bit field SubMemclkRegDly - BFOdtSwizzle, ///< Bit field OdtSwizzle - BFProgOdtEn, ///< Bit field ProgOdtEn - BFCtrlWordCS, ///< Bit field CtrlWordCS - BFRefChCmdMgtDis, ///< Bit field RefChCmdMgtDis - BFFastSelfRefEntryDis, ///< Bit field FastSelfRefEntryDis - BFPrtlChPDEnhEn, ///< Bit field PrtlChPDEnhEn - BFAggrPDEn, ///< Bit field AggrPDEn - BFDataTxFifoWrDly, ///< Bit field DataTxFifoWrDly - BFWrDqDqsEarly, ///< Bit field WrDqDqsEarly - BFCSMux45, ///< Bit field CSMux45 - BFCSMux67, ///< Bit field CSMux67 - BFLrDimmMrsCtrl, ///< Bit field LrDimmMrsCtrl - BFExtendedParityEn, ///< Bit field ExtendedParityEn - BFLrDimmEnhRefEn, ///< Bit field LrDimmEnhRefEn - BFCSTimingMux67, ///< Bit field CSTimingMux67 - BFLrDimmErrOutMonEn, ///< Bit field LrDimmErrOutMonEn - - BFIntLvRgnSwapEn, ///< Bit field IntLvRgnSwapEn - BFIntLvRgnBaseAddr, ///< Bit field IntLvRgnBaseAddr - BFIntLvRgnLmtAddr, ///< Bit field IntLvRgnLmtAddr - BFIntLvRgnSize, ///< Bit field IntLvRgnSize - - BFDctSelHiRngEn, ///< Bit field DctSelHiRngEn - BFDctSelHi, ///< Bit field DctSelHi - BFDctSelIntLvEn, ///< Bit field DctSelIntLvEn - BFMemClrInit, ///< Bit field MemClrInit - BFDctGangEn, ///< Bit field DctGangEn - BFDctDatIntLv, ///< Bit field DctDatIntLv - BFDctSelIntLvAddr, ///< Bit field DctSelIntLvAddr - BFDctSelIntLvAddrHi, ///< Bit field DctSelIntLvAddrHi - BFParallelMemClrEn, ///< Bit field ParallelMemClrEn - BFDramEnabled, ///< Bit field DramEnabled - BFMemClrBusy, ///< Bit field MemClrBusy - BFMemCleared, ///< Bit field MemCleared - BFDctSelBaseAddr, ///< Bit field DctSelBaseAddr - BFDctSelBaseOffset, ///< Bit field DctSelBaseOffset - BFDctSelBankSwap, ///< Bit field DctSelBankSwap - - BFAdapPrefMissRatio, ///< Bit field AdapPrefMissRatio - BFAdapPrefPosStep, ///< Bit field AdapPrefPosStep - BFAdapPrefNegStep, ///< Bit field AdapPrefNegStep - BFCohPrefPrbLmt, ///< Bit field CohPrefPrbLmt - - BFFlushWrOnS3StpGnt, ///< Bit field FlushWrOnS3StpGnt - - BFPrefDramTrainDone, ///< Bit field PrefDramTrainDone - BFWrDramTrainMode, ///< Bit field WrDramTrainMode - BFMctPrefReqLimit, ///< Bit field MctPrefReqLimit - BFPrefDramTrainMode, ///< Bit field PrefDramTrainMode - BFDctWrLimit, ///< Bit field DctWrLimit - BFMctWrLimit, ///< Bit field MctWrLimit - BFDramTrainPdbDis, ///< Bit field DramTrainPdbDis - BFTrainLength, ///< Bit field TrainLength - BFRdTrainGo, ///< Bit field RdTrainGo - BFWrTrainGo, ///< Bit field WrTrainGo - BFWrTrainAdrPtrLo, ///< Bit field WrTrainAdrPtrLo - BFWrTrainAdrPtrHi, ///< Bit field WrTrainAdrPtrHi - BFWrTrainBufAddr, ///< Bit field WrTrainBufAddr - BFWrTrainBufDat, ///< Bit field WrTrainBufDat - BFFlushWr, ///< Bit field FlushWr - BFFlushWrOnStpGnt, ///< Bit field FlushWrOnStpGnt - BFPrefCpuDis, ///< Bit field PrefCpuDis - BFPrefIoDis, ///< Bit field PrefIoDis - BFPrefThreeConf, ///< Bit field PrefThreeConf - BFTrainCmpSts, ///< Bit field TrainCmpSts - BFTrainCmpSts2, ///< Bit field TrainCmpSts2 - BFTraceModeEn, ///< Bit field TraceModeEn - - BFAddrCmdDrvStren, ///< Bit field AddrCmdDrvStren - BFDataDrvStren, ///< Bit field DataDrvStren - BFCkeDrvStren, ///< Bit field CkeDrvStren - BFCsOdtDrvStren, ///< Bit field CsOdtDrvStren - BFClkDrvStren, ///< Bit field ClkDrvStren - BFDqsDrvStren, ///< Bit field DqsDrvStren - BFProcOdt, ///< Bit field ProcOdt - BFODCControl, ///< Bit field ODCControl - BFAddrTmgControl, ///< Bit field AddrTmgControl - BFAddrCmdFineDelay, ///< Bit field AddrCmdFineDelay - - BFWrtLvTrEn, ///< Bit field WrtLvTrEn - BFWrtLvTrMode, ///< Bit field WrtLvTrMode - BFPhyFenceTrEn, ///< Bit field PhyFenceTrEn - BFTrDimmSel, ///< Bit field TrDimmSel - BFTrNibbleSel, ///< Bit field TrNibbleSel - BFFenceTrSel, ///< Bit field FenceTrSel - BFWrLvOdt, ///< Bit field WrLvOdt - BFWrLvOdtEn, ///< Bit field WrLvOdtEn - BFDqsRcvTrEn, ///< Bit field DqsRcvTrEn - BFDisAutoComp, ///< Bit field DisAutoComp - BFWrtLvErr, ///< Bit field WrtLvErr - BFODTAssertionCtl, ///< Bit field ODTAssertionCtl - BFNibbleTrainModeEn, ///< Bit field NibbleTrainModeEn - BFRankTrainModeEn, ///< Bit field RankTrainModeEn - BFPllMult, ///< Bit field PllMult - BFPllDiv, ///< Bit field PllDiv - BFDramPhyCtlReg, ///< Bit field Dram Phy Control Register - - BFDramPhyStatusReg, ///< Bit field DramPhyStatusReg - - BFD3Cmp2PCal, ///< Bit field D3Cmp2PCal - BFD3Cmp2NCal, ///< Bit field D3Cmp2NCal - BFD3Cmp1PCal, ///< Bit field D3Cmp1PCal - BFD3Cmp1NCal, ///< Bit field D3Cmp1NCal - BFD3Cmp0PCal, ///< Bit field D3Cmp0PCal - BFD3Cmp0NCal, ///< Bit field D3Cmp0NCal - - BFPhyFence, ///< Bit field PhyFence - BFODTTri, ///< Bit field ODTTri - BFCKETri, ///< Bit field CKETri - BFChipSelTri, ///< Bit field ChipSelTri - BFPhyRODTCSLow, ///< Bit field PhyRODTCSLow - BFPhyRODTCSHigh, ///< Bit field PhyRODTCSHigh - BFPhyWODTCSLow, ///< Bit field PhyWODTCSLow - BFPhyWODTCSHigh, ///< Bit field PhyWODTCSHigh - BFUSPLLCtlAll, ///< Bit field USPLLCtlAll - BFDSPLLCtlAll, ///< Bit field DSPLLCtlAll - BFUSNibbleAlignEn, ///< Bit field USNibbleAlignEn - BFChnLinitClkEn, ///< Bit field ChnLinitClkEn - - BFTSLinkSelect, ///< Bit field TSLinkSelect - BFTS2BitLockEn, ///< Bit field TS2BitLockEn - BFTS2En, ///< Bit field TS2En - BFTS1En, ///< Bit field TS1En - BFTS0LinkStarEn, ///< Bit field TS0LinkStarEn - BFTS0En, ///< Bit field TS0En - - BFLinkTrainData, ///< Bit field LinkTrainData - - BFRstRxFifoPtrs, ///< Bit field RstRxFifoPtrs - BFRxFifoPtrInit, ///< Bit field RxFifoPtrInit - BFRstTxFifoPtrs, ///< Bit field RstTxFifoPtrs - BFTxFifoPtrInit, ///< Bit field TxFifoPtrInit - - BFLpbkCount, ///< Bit field LpbkCount - BFLpbkMap, ///< Bit field LpbkMap - BFSendLpbkMaintCmd, ///< Bit field SendLpbkMaintCmd - BFLpbkData, ///< Bit field LpbkData - - BFMbRdPtrEn, ///< Bit field MbRdPtrEn - BFLnkLpBkLat, ///< Bit field LnkLpBkLat - BFLpbkRndTripLatDone, ///< Bit field LpbkRndTripLatDone - BFLnkLatTrainEn, ///< Bit field LnkLatTrainEn - - BFDsPhyReset, ///< Bit field DsPhyReset - BFLinkReset, ///< Bit field LinkReset - - BFPllLockTime, ///< Bit field PllLockTime - BFPllRegWaitTime, ///< Bit field PllRegWaitTime - BFNclkFreqDone, ///< Bit field NclkFreqDone - BFNbPs0NclkDiv, ///< Bit field NbPs0NclkDiv - BFNbPs1NclkDiv, ///< Bit field NbPs1NclkDiv - BFNbPsCsrAccSel, ///< Bit field NbPsCsrAccSel - BFNbPsDbgEn, ///< Bit field NbPsDbgEn - BFNclkRampWithDllRelock, ///< Bit field NclkRampWithDllRelock - - BFOnLineSpareControl, ///< Bit field OnLineSpareControl - BFDdrMaxRate, ///< Bit field DdrMaxRate - - BFPhyDctCfgSelMode, ///< Bit field PhyDctCfgSelMode - BFNbPstateDis, ///< Bit field NbPstateDis - BFNbPsSel, ///< Bit field NbPsSel - BFNbPstateCtlReg, ///< Bit field NB Pstate Control register - BFSwNbPstateLoDis, ///< Bit field SwNbPstateLoDis - BFNbPstateLo, ///< Bit field NbPstateLo - BFNbPstateHi, ///< Bit field NbPstateHi - BFNbPstateMaxVal, ///< Bit field NbPstateMaxVal - BFCurNbPstate, ///< Bit field NbCurNbPstate - - BFC6Base, ///< Bit field C6Base - BFC6DramLock, ///< Bit field C6DramLock - BFCC6SaveEn, ///< Bit field CC6SaveEn - BFCoreStateSaveDestNode, ///< Bit field CoreStateSaveDestNode - - BFRxPtrInitReq, ///< Bit field RxPtrInitReq - BFAddrCmdTriEn, ///< Bit field AddrCmdTriEn - BFForceCasToSlot0, ///< Bit field ForceCasToSlot0 - BFDisCutThroughMode, ///< Bit field DisCutThroughMode - BFDbeSkidBufDis, ///< Bit field DbeSkidBufDis - BFDbeGskMemClkAlignMode, ///< Bit field DbeGskMemClkAlignMode - BFEnCpuSerRdBehindNpIoWr, ///< Bit field EnCpuSerRdBehindNpIoWr - BFDRAMPhyDLLControl, ///< Bit field DRAMPhyDLLControl - BFRxDLLWakeupTime, ///< Bit field RxDllWakeupTime - BFRxCPUpdPeriod, ///< Bit field RxCPUpdPeriod - BFRxMaxDurDllNoLock, ///< Bit field RxMaxDurDllNoLock - BFTxDLLWakeupTime, ///< Bit field TxDllWakeupTime - BFTxCPUpdPeriod, ///< Bit field TxCPUpdPeriod - BFTxMaxDurDllNoLock, ///< Bit field TxMaxDurDllNoLock - BFEnRxPadStandby, ///< Bit field EnRxPadStandby - BFMaxSkipErrTrain, ///< Bit field MaxSkipErrTrain - BFSlotSel, ///< Bit field SlotSel - BFSlot1ExtraClkEn, ///< Bit field Slot1ExtraClkEn - - BFMemTempHot, ///< Bit field MemTempHot - BFDoubleTrefRateEn, ///< Bit field DoubleTrefRateEn - - BFAcpiPwrStsCtrlHi, ///< Bit field BFAcpiPwrStsCtrlHi - BFDramSrHysEn, ///< Bit field BFDramSrHysEn - BFDramSrHys, ///< Bit field BFDramSrHys - BFMemTriStateEn, ///< Bit field BFMemTriStateEn - BFDramSrEn, ///< Bit field BFDramSrEn - - BFReserved002, ///< Bit field BFReserved002 - BFFourRankRDimm0, ///< Bit field BFFourRankRDimm0 - BFFourRankRDimm1, ///< Bit field BFFourRankRDimm1 - BFTwrwrSdSc, ///< Bit field BFTwrwrSdSc - BFTwrwrSdDc, ///< Bit field BFTwrwrSdDc - BFTwrwrDd, ///< Bit field BFTwrwrDd - BFTrdrdSdSc, ///< Bit field BFTrdrdSdSc - BFTrdrdSdDc, ///< Bit field BFTrdrdSdDc - BFTrdrdDd, ///< Bit field BFTrdrdDd - BFTstag0, ///< Bit field BFTstag0 - BFTstag1, ///< Bit field BFTstag1 - BFTstag2, ///< Bit field BFTstag2 - BFTstag3, ///< Bit field BFTstag3 - - BFDataPatGenSel, ///< Bit field DataPatGenSel - BFActPchgGenEn, ///< Bit field ActPchgGenEn - BFShmooRdDqsDly, ///< Bit field ShmooRdDqsDly - - BFCmdSendInProg, ///< Bit field CmdSendInProg - BFSendCmd, ///< Bit field SendCmd - BFTestStatus, ///< Bit field TestStatus - BFCmdTgt, ///< Bit field CmdTgt - BFCmdType, ///< Bit field CmdType - BFStopOnErr, ///< Bit field StopOnErr - BFResetAllErr, ///< Bit field ResetAllErr - BFCmdTestEnable, ///< Bit field CmdTestEnable - BFTgtChipSelectA, ///< Bit field TgtChipSelectA - BFTgtBankA, ///< Bit field TgtBankA - BFTgtAddressHiA, ///< Bit field TgtAddressHiA - BFTgtAddressA, ///< Bit field TgtAddressA - BFTgtChipSelectB, ///< Bit field TgtChipSelectB - BFTgtBankB, ///< Bit field TgtBankB - BFTgtAddressHiB, ///< Bit field TgtAddressHiB - BFTgtAddressB, ///< Bit field TgtAddressB - BFReserved008, ///< Bit field Reserved008 - BFReserved007, ///< Bit field Reserved007 - BFReserved006, ///< Bit field Reserved006 - BFCmdCount, ///< Bit field CmdCount - BFErrDqNum, ///< Bit field ErrDQNum - BFErrCnt, ///< Bit field ErrCnt - BFNibbleErrSts, ///< Bit field NibbleErrSts - BFNibbleErr180Sts, ///< Bit field NibbleErr180Sts - BFDataPrbsSeed, ///< Bit field DataPrbsSeed - BFDramDqMaskLow, ///< Bit field DramDqMaskLow - BFDramDqMaskHigh, ///< Bit field DramDqMaskHigh - BFDramEccMask, ///< Bit field DramEccMask - BFDQPatOvrEn0, ///< Bit field DQPatOvrEn0 - BFDQPatOvrEn1, ///< Bit field DQPatOvrEn1 - BFXorPatOvr, ///< Bit field XorPatOvr - BFPatOvrVal, ///< Bit field PatOvrVal - BFEccPatOvrEn, ///< Bit field EccPatOvrEn - BFSendActCmd, ///< Bit field SendActCmd - BFSendPchgCmd, ///< Bit field SendPchgCmd - BFCmdChipSelect, ///< Bit field CmdChipSelect - BFCmdBank, ///< Bit field CmdBank - BFCmdAddress, ///< Bit field CmdAddress - BFErrBeatNum, ///< Bit Field ErrBeatNum - BFErrCmdNum, ///< Bit field BFErrCmdNum - BFDQErrLow, ///< Bit field DQSErrLow - BFDQErrHigh, ///< Bit field DQSErrHigh - BFEccErr, ///< Bit field EccErr - BFFastMstateDis, ///< Bit field FastMstateDis - BFDramUserDataPattern0, ///< Bit field DramUserDataPattern0 - BFDramUserDataPattern1, ///< Bit field DramUserDataPattern1 - BFDramUserDataPattern2, ///< Bit field DramUserDataPattern2 - BFDramUserDataPattern3, ///< Bit field DramUserDataPattern3 - BFActPchgSeq, ///< Bit field ActPchgSeq - BFActPchgCmdMin, ///< Bit field ActPchgCmdMin - BFDramCommandReg4, ///< Bit field DramCommandReg4 - BFDramCommandReg5, ///< Bit field DramCommandReg5 - BFNibbleErrStsSel, ///< Bit field NibbleErrStsSel - BFErrStsDly, ///< Bit field ErrStsDly - BFErrStsDly180, ///< Bit field ErrStsDly180 - - /* Bit fields for workarounds */ - BFErr263, ///< Bit field Err263 - BFErr350, ///< Bit field Err350 - BFErr322I, ///< Bit field Err322I - BFErr322II, ///< Bit field Err322II - BFErratum468WorkaroundNotRequired, ///< Bit field Erratum468WorkaroundNotRequired - - /* Bit fields for Phy */ - BFEccDLLConf, ///< Bit field EccDLLConf - BFProcOdtAdv, ///< Bit field ProcOdtAdv - BFEccDLLPwrDnConf, ///< Bit field EccDLLPwrDnConf - BFPhyPLLLockTime, ///< Bit field PhyPLLLockTime - BFPhyDLLLockTime, ///< Bit field PhyDLLLockTime - BFSkewMemClk, ///< Bit field SkewMemClk - BFPhyDLLControl, ///< Bit field BFPhyDLLControl - BFPhy0x0D080F0C, ///< Bit field BFPhy0x0D080F0C - BFPhy0x0D080F10, ///< Bit field BFPhy0x0D080F10 - BFPhy0x0D080F11, ///< Bit field BFPhy0x0D080F11 - BFPhy0x0D088F30, ///< Bit field BFPhy0x0D088F30 - BFPhy0x0D08C030, ///< Bit field BFPhy0x0D08C030 - BFPhy0x0D082F30, ///< Bit field BFPhy0x0D082F30 - BFDiffTimingEn, ///< Bit Field DiffTimingEn - BFFence, ///< Bit Field Fence - BFDelay, ///< Bit Field Delay - BFFenceValue, ///< Bit Field FenceValue - - BFPhy0x0D040F3E, ///< Bit field BFPhy0x0D040F3E - BFPhy0x0D042F3E, ///< Bit field BFPhy0x0D042F3E - BFPhy0x0D048F3E, ///< Bit field BFPhy0x0D048F3E - BFPhy0x0D04DF3E, ///< Bit field BFPhy0x0D04DF3E - - BFPhyClkDllFine0, ///< Bit field ClkDllFineDly 0 - BFPhyClkDllFine1, ///< Bit field ClkDllFineDly 1 - - BFPhyClkConfig0, ///< Bit field ClkConfig0 - BFPhyClkConfig1, ///< Bit field ClkConfig1 - BFPhyClkConfig2, ///< Bit field ClkConfig2 - BFPhyClkConfig3, ///< Bit field ClkConfig3 - - BFPhy0x0D0F0F13, ///< Bit field BFPhy0x0D0F0F13 - BFPhy0x0D0F0F13Bit0to7, ///< Bit field BFPhy0x0D0F0F13Bit0to7 - BFPhy0x0D0F0830, ///< Bit field BFPhy0x0D0F0830 - BFPhy0x0D07812F, ///< Bit field BFPhy0x0D0F8108 - - BFDataRxVioLvl, ///< Bit field DataRxVioLvl - BFClkRxVioLvl, ///< Bit field ClkRxVioLvl - BFCmdRxVioLvl, ///< Bit field CmdRxVioLvl - BFAddrRxVioLvl, ///< Bit field AddrRxVioLvl - BFCmpVioLvl, ///< Bit field CmpVioLvl - BFCsrComparator, ///< Bit field CsrComparator - BFAlwaysEnDllClks, ///< Bit field AlwaysEnDllClks - BFPhy0x0D0FE00A, ///< Bit field Phy0x0D0FE00A - BFPllPdMode, ///< Bit fields SelCsrPllPdMode and CsrPhySrPllPdMode - - BFDataFence2, ///< Bit field DataFence2 - BFClkFence2, ///< Bit field ClkFence2 - BFCmdFence2, ///< Bit field CmdFence2 - BFAddrFence2, ///< Bit field AddrFence2 - - BFDataByteDMConf, ///< Bit field DataByteDMConf - - BFAddrCmdTri, ///< Bit field BFAddrCmdTri - BFReserved00C, ///< Bit field BFReserved00C - BFLevel, ///< Bit field Level - - BFDbeGskFifoNumerator, ///< Bit field DbeGskFifoNumerator - BFDbeGskFifoDenominator, ///< Bit field DbeGskFifoDenominator - BFDataTxFifoSchedDlyNegSlot0, ///< Bit field DataTxFifoSchedDlyNegSlot0 - BFDataTxFifoSchedDlyNegSlot1, ///< Bit field DataTxFifoSchedDlyNegSlot1 - BFDataTxFifoSchedDlySlot0, ///< Bit field DataTxFifoSchedDlySlot0 - BFDataTxFifoSchedDlySlot1, ///< Bit field DataTxFifoSchedDlySlot1 - - BFDisablePredriverCal, ///< Bit field DisablePredriverCal - BFDataByteTxPreDriverCal, ///< Bit field DataByteTxPreDriverCal - BFDataByteTxPreDriverCal2Pad1, ///< Bit field DataByteTxPreDriverCal2Pad1 - BFDataByteTxPreDriverCal2Pad2, ///< Bit field DataByteTxPreDriverCal2Pad2 - BFCmdAddr0TxPreDriverCal2Pad1, ///< Bit field CmdAddr0TxPreDriverCal2Pad1 - BFCmdAddr0TxPreDriverCal2Pad2, ///< Bit field CmdAddr0TxPreDriverCal2Pad2 - BFCmdAddr1TxPreDriverCal2Pad1, ///< Bit field CmdAddr1TxPreDriverCal2Pad1 - BFCmdAddr1TxPreDriverCal2Pad2, ///< Bit field CmdAddr1TxPreDriverCal2Pad2 - BFAddrTxPreDriverCal2Pad1, ///< Bit field AddrTxPreDriverCal2Pad1 - BFAddrTxPreDriverCal2Pad2, ///< Bit field AddrTxPreDriverCal2Pad2 - BFAddrTxPreDriverCal2Pad3, ///< Bit field AddrTxPreDriverCal2Pad3 - BFAddrTxPreDriverCal2Pad4, ///< Bit field AddrTxPreDriverCal2Pad4 - BFCmdAddr0TxPreDriverCalPad0, ///< Bit field CmdAddr0TxPreDriverCalPad0 - BFCmdAddr1TxPreDriverCalPad0, ///< Bit field CmdAddr1TxPreDriverCalPad0 - BFAddrTxPreDriverCalPad0, ///< Bit field AddrTxPreDriverCalPad0 - BFClock0TxPreDriverCalPad0, ///< Bit field Clock0TxPreDriverCalPad0 - BFClock1TxPreDriverCalPad0, ///< Bit field Clock1TxPreDriverCalPad0 - BFClock2TxPreDriverCalPad0, ///< Bit field Clock2TxPreDriverCalPad0 - BFPNOdtCal, ///< Bit field P/NOdtCal - BFPNDrvCal, ///< Bit field P/NDrvCal - BFCalVal, ///< Bit field CalVal - BFPStateToAccess, ///< Bit field PStateToAccess - BFReserved009, ///< Bit Field BFReserved009 - - BFTxp, ///< Bit field Txp - BFTxpdll, ///< Bit field Txpdll - BFDramPwrMngm1Reg, ///< Bit field DRAM Power Management 1 register - BFL3ScrbRedirDis, ///< Bit field L3ScrbRedirDis - BFDQOdt03, ///< Bit field DQ Odt 0-3 - BFDQOdt47, ///< Bit field DQ Odt 4-7 - BFTriDM, ///< Bit field TriDM - - BFTcksrx, ///< Bit field Tcksrx - BFTcksre, ///< Bit field Tcksre - BFTckesr, ///< Bit field Tckesr - BFTpd, ///< Bit field Tpd - - BFFixedErrataSkipPorFreqCap, ///< Bit field FixedErrataSkipPorFreqCap - BFPerRankTimingEn, ///< Bit field PerRankTimingEn - BFMemPhyPllPdMode, ///< Bit field MemPhyPllPdMode - BFBankSwap, ///< Bit field BankSwap - BFBwCapCmdThrottleMode, ///< Bit field BwCapCmdThrottleMode - BFRxChMntClkEn, ///< Bit field RxChMntClkEn - BFBlockRxDqsLock, ///< Bit field BlockRxDqsLock - BFRxSsbMntClkEn, ///< Bit field RxSsbMntClkEn - BFPhyPSMasterChannel, ///< Bit field PhyPSMasterChannel - - BFReserved8_0, ///< Bit field BFReserved8_0 - BFReserved8_1, ///< Bit field VrefDAC - BFReserved4_0, ///< Bit field BFReserved4_0 - BFReserved4_1, ///< Bit field BFReserved4_1 - BFReserved4_2, ///< Bit field BFReserved4_2 - BFReserved4_3, ///< Bit field BFReserved4_3 - BFReserved4_4, ///< Bit field BFReserved4_4 - BFReserved4_5, ///< Bit field BFReserved4_5 - BFReserved4_6, ///< Bit field BFReserved4_6 - BFReserved4_7, ///< Bit field BFReserved4_7 - BFReserved4_8, ///< Bit field BFReserved4_8 - BFReserved4_9, ///< Bit field BFReserved4_9 - BFReserved4_A, ///< Bit field BFReserved4_A - BFReserved4_B, ///< Bit field BFReserved4_B - BFReserved4_C, ///< Bit field BFReserved4_C - BFReserved4_D, ///< Bit field BFReserved4_D - BFReserved4_E, ///< Bit field BFReserved4_E - BFReserved4_F, ///< Bit field BFReserved4_F - BFReserved4_10, ///< Bit field BFReserved4_10 - BFReserved4_11, ///< Bit field BFReserved4_11 - BFReserved4_12, ///< Bit field BFReserved4_12 - BFReserved5_0, ///< Bit field BFReserved5_0 - BFReserved5_1, ///< Bit field BFReserved5_1 - BFReserved5_2, ///< Bit field BFReserved5_2 - BFReserved5_3, ///< Bit field BFReserved5_3 - BFReserved5_4, ///< Bit field BFReserved5_4 - BFReserved5_5, ///< Bit field BFReserved5_5 - BFReserved5_6, ///< Bit field BFReserved5_6 - BFReserved5_7, ///< Bit field BFReserved5_7 - BFReserved5_8, ///< Bit field BFReserved5_8 - BFReserved5_9, ///< Bit field BFReserved5_9 - BFReserved5_A, ///< Bit field BFReserved5_A - BFReserved5_B, ///< Bit field BFReserved5_B - BFReserved5_C, ///< Bit field BFReserved5_C - BFReserved5_D, ///< Bit field BFReserved5_D - BFReserved5_E, ///< Bit field BFReserved5_E - BFReserved5_F, ///< Bit field BFReserved5_F - BFReserved5_10, ///< Bit field BFReserved5_10 - BFReserved5_11, ///< Bit field BFReserved5_11 - BFReserved5_12, ///< Bit field BFReserved5_12 - BFReserved6_0, ///< Bit field BFReserved6_0 - BFReserved6_1, ///< Bit field BFReserved6_1 - BFReserved6_2, ///< Bit field BFReserved6_2 - BFReserved6_3, ///< Bit field BFReserved6_3 - BFReserved6_4, ///< Bit field BFReserved6_4 - BFReserved6_5, ///< Bit field BFReserved6_5 - BFReserved6_6, ///< Bit field BFReserved6_6 - BFReserved6_7, ///< Bit field BFReserved6_7 - BFReserved6_8, ///< Bit field BFReserved6_8 - BFReserved6_9, ///< Bit field BFReserved6_9 - BFReserved6_A, ///< Bit field BFReserved6_A - BFReserved6_B, ///< Bit field BFReserved6_B - BFReserved6_C, ///< Bit field BFReserved6_C - BFReserved6_D, ///< Bit field BFReserved6_D - BFReserved6_E, ///< Bit field BFReserved6_E - BFReserved6_F, ///< Bit field BFReserved6_F - BFReserved6_10, ///< Bit field BFReserved6_10 - BFReserved6_11, ///< Bit field BFReserved6_11 - BFReserved6_12, ///< Bit field BFReserved6_12 - BFReserved7_0, ///< Bit field BFReserved7_0 - BFReserved7_1, ///< Bit field BFReserved7_1 - BFReserved7_2, ///< Bit field BFReserved7_2 - BFReserved7_3, ///< Bit field BFReserved7_3 - BFReserved7_4, ///< Bit field BFReserved7_4 - BFReserved7_5, ///< Bit field BFReserved7_5 - BFReserved7_6, ///< Bit field BFReserved7_6 - BFReserved7_7, ///< Bit field BFReserved7_7 - BFReserved7_8, ///< Bit field BFReserved7_8 - BFReserved7_9, ///< Bit field BFReserved7_9 - BFReserved7_A, ///< Bit field BFReserved7_A - BFReserved7_B, ///< Bit field BFReserved7_B - BFReserved7_C, ///< Bit field BFReserved7_C - BFReserved7_D, ///< Bit field BFReserved7_D - BFReserved7_E, ///< Bit field BFReserved7_E - BFReserved7_F, ///< Bit field BFReserved7_F - BFReserved7_10, ///< Bit field BFReserved7_10 - BFReserved7_11, ///< Bit field BFReserved7_11 - BFReserved7_12, ///< Bit field BFReserved7_12 - BFDataByteDllPowerMgnByte0, ///< Bit field DataByteDllPowerManagement for Byte 0 - BFDataByteDllPowerMgnByte1, ///< Bit field DataByteDllPowerManagement for Byte 1 - BFDataByteDllPowerMgnByte2, ///< Bit field DataByteDllPowerManagement for Byte 2 - BFDataByteDllPowerMgnByte3, ///< Bit field DataByteDllPowerManagement for Byte 3 - BFDataByteDllPowerMgnByte4, ///< Bit field DataByteDllPowerManagement for Byte 4 - BFDataByteDllPowerMgnByte5, ///< Bit field DataByteDllPowerManagement for Byte 5 - BFDataByteDllPowerMgnByte6, ///< Bit field DataByteDllPowerManagement for Byte 6 - BFDataByteDllPowerMgnByte7, ///< Bit field DataByteDllPowerManagement for Byte 7 - BFDataByteDllPowerMgnByte8, ///< Bit field DataByteDllPowerManagement for Byte ECC - BFDataByteDllPowerMgnByteAll, ///< Bit field DataByteDllPowerManagement for all bytes - - BFReserved00A, ///< Bit field for BFReserved00A - BFReserved003, ///< Bit field for BFReserved003 - BFM1MemClkFreq, ///< Bit field M1MemClkFreq - BFRate, ///< Bit field Rate - BFFence2, ///< Bit field Fence2 - - BFNbVid0, ///< Bit field NbVid for NB Pstate 0 - BFNbVid0Hi, ///< Bit field 7th bit of NbVid for NB Pstate 0 - BFNbVid1, ///< Bit field NbVid for NB Pstate 1 - BFNbVid1Hi, ///< Bit field 7th bit of NbVid for NB Pstate 1 - BFNbVid2, ///< Bit field NbVid for NB Pstate 2 - BFNbVid2Hi, ///< Bit field 7th bit of NbVid for NB Pstate 2 - BFNbVid3, ///< Bit field NbVid for NB Pstate 3 - BFNbVid3Hi, ///< Bit field 7th bit of NbVid for NB Pstate 3 - - BFMemPstate0, ///< Bit field MemPstate for NB Pstate 0 - BFMemPstate1, ///< Bit field MemPstate for NB Pstate 1 - BFMemPstate2, ///< Bit field MemPstate for NB Pstate 2 - BFMemPstate3, ///< Bit field MemPstate for NB Pstate 3 - BFMemPstateDis, ///< Bit field MemPstateDis - BFMultiNodeCpu, ///< Bit field for MultiNodeCpu( MCM capability) - - BFRxBypass3rd4thStg, ///< Bit field RxBypass3rd4thStg - BFRx4thStgEn, ///< Bit field Rx4thStgEn - BFDllNoLock, ///< Bit field DllNoLock - BFEnSplitMctDatBuffers, ///< Bit field EnSplitMctDatBuffers - BFGmcTokenLimit, ///< Bit fieid GmcTokenLimit - BFMctTokenLimit, ///< Bit field MctTokenLimit - BFGmcToDctControl1, ///< Bit field GmcToDctControl1 - BFDllCSRBisaTrimDByte, ///< Bit field DllCSRBisaTrimDByte - BFDllCSRBisaTrimClk, ///< Bit field DllCSRBisaTrimClk - BFDllCSRBisaTrimCsOdt, ///< Bit field DllCSRBisaTrimCsOdt - BFDllCSRBisaTrimAByte2, ///< Bit field DllCSRBisaTrimAByte2 - BFReduceLoop, ///< Bit field ReduceLoop - BFEffArbDis, ///< Bit field EffArbDis - BFReserved005, ///< Bit field for Reserved005 register - BFDramCommand2, ///< Bit field for DramCommand2 register - BFReserved004, ///< Bit field for DramLoopbackAndTrainingControl register - - // Reserved - BFReserved01, ///< Reserved 01 - BFReserved02, ///< Reserved 02 - BFReserved03, ///< Reserved 03 - BFReserved04, ///< Reserved 04 - BFReserved05, ///< Reserved 05 - BFReserved06, ///< Reserved 06 - BFReserved07, ///< Reserved 07 - BFReserved08, ///< Reserved 08 - BFReserved09, ///< Reserved 09 - BFReserved10, ///< Reserved 10 - - BFReserved11, ///< Reserved 11 - BFReserved12, ///< Reserved 12 - BFReserved13, ///< Reserved 13 - BFReserved14, ///< Reserved 14 - BFReserved15, ///< Reserved 15 - BFReserved16, ///< Reserved 16 - BFReserved17, ///< Reserved 17 - BFReserved18, ///< Reserved 18 - BFReserved19, ///< Reserved 19 - BFReserved20, ///< Reserved 20 - BFIdsCmnMemReg, ///< Reserved for ids only, the value may dynamic change - BFDctSelBaseAddrReg, ///< Bit field DctSelBaseAddrReg - BFDctSelBaseOffsetReg, ///< Bit field DctSelBaseOffsetReg - - /* End of accessible list --- entries below this line are for private use ------------*/ - BFEndOfList, ///< End of bit field list - - // Only for Table Drive Support define. - BFRcvEnDly, ///< F2x[1,0]9C_x[2B:10] Dram DQS Receiver Enable Timing Control Registers - BFWrDatDly, ///< F2x[1, 0]9C_x[302:301, 202:201, 102:101, 02:01] DRAM Write Data Timing [High:Low] Registers - BFRdDqsDly, ///< F2x[1, 0]9C_x[306:305, 206:205, 106:105, 06:05] DRAM Read DQS Timing Control [High:Low] Registers - BFWrDqsDly, ///< F2x[1, 0]9C_x[4A:30] DRAM DQS Write Timing Control Registers - BFPhRecDly, ///< F2x[1, 0]9C_x[51:50] DRAM Phase Recovery Control Register [High:Low] Registers - BFRdDqs__Dly, ///< F2x[1, 0]9C_x0D0F_0[F,8:0]2[3:0] - /* Do not define any entries beyond this point */ - BFAbsLimit ///< Beyond this point is reserved for bit field manipulation - -} BIT_FIELD_NAME; - -/// Bit field aliases -#define BFMainPllOpFreqId BFNbFid -#define BFNbDid BFNbPs0NclkDiv -#define BFRdDramTrainMode BFPrefDramTrainMode -#define BFThrottleEn BFCmdThrottleMode -#define BFIntlvRegionEn BFIntLvRgnSwapEn -#define BFIntlvRegionBase BFIntLvRgnBaseAddr -#define BFIntlvRegionLimit BFIntLvRgnLmtAddr -#define BFRdOdtPatReg BFPhyRODTCSLow -#define BFWrOdtPatReg BFPhyWODTCSLow -#define BFLockDramCfg BFC6DramLock -#define BFRstRcvFifo BFTwr -#define BFDramCmd2Reg BFCmdBank -#define BFDramODTCtlReg BFRdOdtTrnOnDly - -/// Bit field names per DRAM CS base address register -typedef enum { - BFCSEnable = 0, ///< Chip select enable - BFSpare = 1, ///< Spare rank - BFTestFail = 2, ///< Memory test failed - BFOnDimmMirror = 3 ///< on-DIMM mirroring enable -} CS_BASE_BIT_FIELD; - -/// Flag for exclude dimm -typedef enum { - NORMAL, ///< Normal mode, exclude the dimm if there is new dimm failure - TRAINING, ///< Training mode, exclude dimms that fail during training after training is done - END_TRAINING ///< End training mode, exclude all dimms that failed during training -} DIMM_EXCLUDE_FLAG; - -#define BSP_DIE 0 -#define MAX_NODES_SUPPORTED 8 ///< Maximum number of nodes in the system. -#define MAX_CS_PER_CHANNEL 8 ///< Max CS per channel -#define MAX_CS_PER_DELAY 2 ///< Max Chip Select Controlled by a set of delays. -#define MAX_BYTELANES 8 ///< 8 byte lanes -#define MAX_DELAYS 9 ///< 8 data bytes + 1 ECC byte -#define MAX_DIMMS 4 ///< 4 DIMMs per channel - -#define VDDIO_DETERMINED 0xFF ///< VDDIO has been determined yet. Further processing is not needed. - -/// -/// MEM_SHARED_DATA -/// This structure defines the shared data area that is used by the memory -/// code to share data between different northbridge objects. Each substructure -/// in the data area defines how this data area is used by a different purpose. -/// -/// There should only be one instance of this struct created for all of the memory -/// code to use. -/// -typedef struct _MEM_SHARED_DATA { - - // System memory map data - UINT32 CurrentNodeSysBase; ///< Base[47:16] (system address) DRAM base address for current node. - /// Memory map data for each node - BOOLEAN AllECC; ///< ECC support on the system - DIMM_EXCLUDE_FLAG DimmExcludeFlag; ///< Control the exclude dimm behavior - UINT8 VoltageMap; ///< The commonly supported voltage map in the system - - UINT8 TopNode; ///< Node that has its memory mapped to TOPMEM/TOPMEM2 - BOOLEAN C6Enabled; ///< TRUE if C6 is enabled - - /// Data structure for NB register table - struct { - UINT64 FamilyId; ///< LogicalCpuid.Family - UINT32 *NBRegTable; ///< Pointer to allocated buffer for NBRegTable - } NBRegMap[MAX_NODES_SUPPORTED]; - - /// Data structure for node map - struct { - BOOLEAN IsValid; ///< TRUE if this node contains memory. - UINT32 SysBase; ///< Base[47:16] (system address) DRAM base address of this node. - UINT32 SysLimit; ///< Base[47:16] (system address) DRAM limit address of this node. - } NodeMap[MAX_NODES_SUPPORTED]; - BOOLEAN UndoHoistingAbove1TB; ///< Undo hoisting above 1TB - - /// Data structure for node interleave feature - struct { - BOOLEAN IsValid; ///< TRUE if the data in this structure is valid. - UINT8 NodeCnt; ///< Number of nodes in the system. - UINT32 NodeMemSize; ///< Total memory of this node. - UINT32 Dct0MemSize; ///< Total memory of this DCT 0. - UINT8 NodeIntlvSel; ///< Index to each node. - } NodeIntlv; -} MEM_SHARED_DATA; - -/// -/// MEM_MAIN_DATA_BLOCK -/// -typedef struct _MEM_MAIN_DATA_BLOCK { - struct _MEM_DATA_STRUCT *MemPtr; ///< Pointer to customer shared data - struct _MEM_NB_BLOCK *NBPtr; ///< Pointer to array of NB Blocks - struct _MEM_TECH_BLOCK *TechPtr; ///< Pointer to array of Tech Blocks - struct _MEM_SHARED_DATA *mmSharedPtr; ///< Pointer to shared data area. - UINT8 DieCount; ///< Total number of Dies installed -} MEM_MAIN_DATA_BLOCK; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - - -/* -node: Indicates the Node -- Value ranges from 0-7, 0xF: for all nodes -- Size - 4 Bits - -dct: Indicate the DRAM Controller -- Value is 0, 1 (0xF: apply setting to all DCTs) -- Size - 4 Bits - -dimm: This values specifies which DIMM register will be applied -- The value varies from 0 to 3, 0xF: all DIMMs -- Size - 4 Bits - -attr - Indicates if the value needs to be added, subtracted, overridden or Auto (not changed) -- 0: Do not change the current value in the register -- 1: Use the value provided in the table to override the current value in the register (the one that AGESA initially determined) -- 2: Add the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined) -- 3: Subtract the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined) -- Size - 2 Bits - -time - Indicate the timing for the register which is written. -- 0: Write register value before Dram init -- 1: Write register value before memory training -- 2: Write register value after memory training -- Size - 1 Bits - -bytelane: bytelane number -- This determines specifies which bytelane register will be applied -- Bit0 =1 - set value into Bytelane0 -- Bit1 =1 - set value into Bytelane1 -- Bit2 =1 - set value into Bytelane2 -... -... -- 0xFFFF: all bytelane -- Size - 16 Bits. - -bfIndex: Indicate the bitfield index -- Size - 16 Bits - -value - Value to be used -- This can be an offset (sub or Add) or an override value. -- Size - DWORD -*/ - -// Sample code -// NBACCESS (MTBeforeDInit, MTNodes, MTDct0, BFCSBaseAddr5Reg, MTOverride, 0x400001), -// NBACCESS (MTBeforeTrn, MTNodes, MTDct1, BFCSBaseAddr7Reg, MTOverride, 0xFFFFFFFF), -// DQSACCESS (MTAfterTrn, MTNodes, MTDcts, MTDIMM0, MTBL1+MTBL2, BFRcvEnDly, MTSubtract, 2), -// DQSACCESS (MTAfterTrn, MTNodes, MTDct1, MTDIMM1, MTBLNOECC, BFRcvEnDly, MTAdd, 1), - -#define ENDMEMTDS 0, 0, 0, 0, 0, 0, 0xFFFFFFFF, 0 - -#define NBACCESS(time, node, dct, bitfield, attr, value) \ -{ (time), \ - ((node) & 0x0F) | ((dct) << 4), \ - (((attr) & 0x07) << 4) | (VT_MSK_VALUE << 7) , \ - (UINT8)((bitfield) & 0x000000FF), \ - (UINT8)(((bitfield) >> 8) & 0x000000FF), \ - (UINT8)(((bitfield) >> 16) & 0x000000FF), \ - (UINT8)(((bitfield) >> 24) & 0x000000FF), \ - 0, 0, \ - (UINT8)((value) & 0x000000FF), \ - (UINT8)(((value) >> 8) & 0x000000FF), \ - (UINT8)(((value) >> 16) & 0x000000FF), \ - (UINT8)(((value) >> 24) & 0x000000FF), \ - 0, 0, 0 \ -} - -#define DQSACCESS(time, node, dct, dimm, bitfield, attr, b0, b1, b2, b3, b4, b5, b6, b7, b8) \ -{ (time), \ - ((node) & 0x0F) | ((dct) << 4), \ - (((dimm) & 0x0F) | ((attr) & 0x07) << 4) | (VT_ARRAY << 7) , \ - (UINT8)((bitfield) & 0x000000FF), \ - (UINT8)(((bitfield) >> 8) & 0x000000FF), \ - (UINT8)(((bitfield) >> 16) & 0x000000FF), \ - (UINT8)(((bitfield) >> 24) & 0x000000FF), \ - (b0), (b1), (b2), (b3), (b4), (b5), (b6), (b7), (b8) \ -} - -#define DQS__ACCESS(time, node, dct, dimm, bitfield, attr, l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18) \ -{ (time), \ - ((node) & 0x0F) | ((dct) << 4), \ - (((dimm) & 0x0F) | ((attr) & 0x07) << 4) | (VT_ARRAY << 7) , \ - (UINT8)((bitfield) & 0x000000FF), \ - (UINT8)(((bitfield) >> 8) & 0x000000FF), \ - (UINT8)(((bitfield) >> 16) & 0x000000FF), \ - (UINT8)(((bitfield) >> 24) & 0x000000FF), \ - (l0, (l1), (l2), (l3), (l4), (l5), (l6), (l7), (l8), (l9), (l10), (l11), (l12), (l13), (l14), (l15), (l16), (l17), (l18) \ -} -/// Type of modification supported by table driven support. -typedef enum { - MTAuto, ///< Do not change the current value in the register - MTOverride, ///< Use the value provided in the table to override the current value in the register - MTSubtract, ///< Subtract the value provided in the table as an offset to the current value in the register - MTAdd, ///< Add the value provided in the table as an offset to the current value in the reg - MTAnd, ///< And the value provided in the table as an offset to the current value in the reg - MTOr ///< Or the value provided in the table as an offset to the current value in the reg -} MTAttr; - -/// Time for table driven support to make modification. -/// NOTE please keep the order of below MT points -typedef enum { - MTBeforeInitializeMCT = 0, ///< 00 Before InitializeMCT - MTAfterAutoCycTiming, ///< 01 After Auto Cycle Timing - MTAfterPlatformSpec, ///< 02 After Platform Specific Configuration - MTBeforeDInit, ///< 03 Before Dram init - MTBeforeTrn, ///< 04 Before memory training - MTAfterMemPstate1PartialTrn, ///< 05 After partial training at starting frequency - MTAfterTrn, ///< 06 After memory training - MTAfterSwWLTrn, ///< 07 After SW Based WL Training - MTAfterHwWLTrnP1, ///< 08 After HW Based WL Training Part 1 - MTAfterHwRxEnTrnP1, ///< 09 After HW Based Receiver Enable Training Part 1 - MTAfterFreqChg, ///< 10 After each frequency change - MTAfterHwWLTrnP2, ///< 11 After HW Based WL Training Part 2 - MTAfterHwRxEnTrnP2, ///< 12 After HW Based Receiver Enable Training Part 2 - MTAfterSwRxEnTrn, ///< 13 After SW Based Receiver Enable Training - MTAfterDqsRwPosTrn, ///< 14 After DQS Read/Write Position Training - MTAfterMaxRdLatTrn, ///< 15 After Max Read Latency Training - MTAfterNbPstateChange, ///< 16 After programming NB Pstate dependent registers - MTAfterInterleave, ///< 17 After Programming Interleave registers - MTAfterSettingMemoryPstate1, ///< 18 After programming registers for memory pstate 1 - MTAfterFinalizeMCT, ///< 19 After Finalize MCT Programming - - MTValidTimePointLimit, ///< Mark the upper bound of the supported time points - MTEnd = 0xFF ///< End of enum define. -} MTTime; - -/// Node on which modification should be made by table driven support. -typedef enum { - MTNode0, ///< Node 0. - MTNode1, ///< Node 1. - MTNode2, ///< Node 2. - MTNode3, ///< Node 3. - MTNode4, ///< Node 4. - MTNode5, ///< Node 5. - MTNode6, ///< Node 6. - MTNode7, ///< Node 7. - MTNodes = 0xF ///< all nodes -} MTNode; - -/// DCT on which modification should be made by table driven support. -typedef enum { - MTDct0, ///< DCT 0. - MTDct1, ///< DCT 1. - MTDcts = 0x7, ///< all dcts -} MTDct; - -/// Dimm on which modification should be made by table driven support. -typedef enum { - MTDIMM0, ///< Dimm 0. - MTDIMM1, ///< Dimm 1. - MTDIMM2, ///< Dimm 2. - MTDIMM3, ///< Dimm 3. - MTDIMMs = 0xF, ///< all Dimms -} MTDIMM; - -/// Bytelane on which modification should be made by table driven support. -typedef enum { - MTBL0 = 0x1, ///< set the value into Bytelane0 - MTBL1 = 0x2, ///< set the value into Bytelane1 - MTBL2 = 0x4, ///< set the value into Bytelane2 - MTBL3 = 0x8, ///< set the value into Bytelane3 - MTBL4 = 0x10, ///< set the value into Bytelane4 - MTBL5 = 0x20, ///< set the value into Bytelane5 - MTBL6 = 0x40, ///< set the value into Bytelane6 - MTBL7 = 0x80, ///< set the value into Bytelane7 - MTBL8 = 0x100, ///< set the value into ECC - MTBLNOECC = 0xFF, ///< all Bytelanes except ECC - MTBLs = 0xFFFF, ///< all Bytelanes -} MTBL; - -/// Values used to indicate which type of training is being done. -typedef enum { - TRN_RCVR_ENABLE, ///< Reciever Enable Training - TRN_DQS_POSITION, ///< Read/Write DQS Position training - TRN_MAX_READ_LATENCY ///< Max read Latency training -} TRAINING_TYPE; - -/// Memory Pstate -typedef enum { - MEMORY_PSTATE0, ///< Memory Pstate 0 - MEMORY_PSTATE1, ///< Memory Pstate 1 -} MEM_PSTATE; - -/// Memory Pstate Training Stage -typedef enum { - MEMORY_PSTATE_1ST_STAGE = 0xF1, ///< Memory Pstate processing stage 1, in which full training is done at DDR667 - MEMORY_PSTATE_2ND_STAGE, ///< Memory Pstate processing stage 2, in which partial trainig will be done at DDR800 - target speed - MEMORY_PSTATE_3RD_STAGE ///< Memory Pstate processing stage 3, in which full training will be done at target frequency and MaxRdLatency training will start -} MEM_PSTATE_STAGE; - -/// RdDqsDly Retrain status -typedef enum { - RDDQSDLY_RTN_NEEDED = 0xF1, ///< RdDqsDly retrain may be needed - RDDQSDLY_RTN_SUSPEND, ///< RdDqsDly retrain is suspected - RDDQSDLY_RTN_ONGOING ///< RdDqsDly retrain condition is just detected -} RDDQSDLY_RTN_STAT; -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -AGESA_STATUS -MemAmdFinalize ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -AGESA_STATUS -MemSocketScan ( - IN OUT MEM_MAIN_DATA_BLOCK *mmPtr - ); - -VOID -SetMemError ( - IN AGESA_STATUS Errorval, - IN OUT DIE_STRUCT *MCTPtr - ); - -VOID -AmdMemInitDataStructDefRecovery ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -SetMemRecError ( - IN AGESA_STATUS Errorval, - IN OUT DIE_STRUCT *MCTPtr - ); - -AGESA_STATUS -memDefRetSuccess ( VOID ); - -VOID -AmdMemFunctionListDef ( - IN OUT VOID *pMemData - ); -#endif /* _MM_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h deleted file mode 100644 index 7b9a86e386..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h +++ /dev/null @@ -1,1743 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mn.h - * - * Common Northbridge - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 55046 $ @e \$Date: 2011-06-15 23:59:07 -0600 (Wed, 15 Jun 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _MN_H_ -#define _MN_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ -#define _4GB_RJ16 (((UINT32) 4) << (30 - 16)) -#define _1TB_RJ16 (((UINT32) 1) << (40 - 16)) -#define HT_REGION_BASE_RJ16 ((UINT32)0x00FD0000) - -#define DCT_ACCESS_WRITE (UINT32) 0x40000000 -#define MTRR_VALID 11 -#define THERMAL_OPT 31 - -#define NB_ACCESS 0 -#define DCT_PHY_ACCESS 1 -#define DCT_EXTRA 2 - -#define DCT_PHY_DIRECT 0xF1 - -#define VT_MSK_VALUE 0 -#define VT_ARRAY 1 -/*--------------------------------------------- - * TSEFO - Type Start End Function Offset - * - * 31:30 Type of access (2-bits) - * 29:29 Special (1-bit) - * 28:28 Phy Direct (1-bit) - * 27:27 Whole Register Access (1-bit) - * 26:26 Linked (1-bit) - * 25:21 Start bit (5-bits) - * 20:16 End bit (5-bits) - * 15:00 Function_Offset/Index (16-bits) - *--------------------------------------------- - */ -typedef UINT32 TSEFO; - -/** - MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex): - - @param[in] TableName - @param[in] BitFieldIndex - @param[in] a Type of access. - @param[in] b Index of register (can be in Function_Offset format). - @param[in] c Highest bit of the bit field. - @param[in] d Lowest bit of the bit field. - - @return TSEFO Access params encrypted in TSEFO format. ---*/ -#define MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex) \ -TableName[BitFieldIndex] = ( \ - (a == DCT_PHY_DIRECT) ? ( \ - (((UINT32) DCT_PHY_ACCESS) << 30) | (((UINT32) 1) << 28) | (((UINT32) b) & 0xFFFF) | (\ - ((c == 15) && (d == 0)) ? ( \ - (((UINT32) 1) << 27) | (((UINT32) b) & 0xF0000) \ - ) : ( \ - (c >= d) ? ( \ - (((UINT32) c) << 21) | (((UINT32) d) << 16) \ - ) : ( \ - (((UINT32) d) << 21) | (((UINT32) c) << 16) \ - ) \ - ) \ - ) \ - ) : ( \ - (((UINT32) a) << 30) | (((UINT32) b) & 0xFFFFFFF) | ( \ - (((UINT32) b) >> 16) ? ( \ - (((UINT32) 1) << 29) \ - ) : ( \ - (c >= d) ? ( \ - (((UINT32) c) << 21) | (((UINT32) d) << 16) \ - ) : ( \ - (((UINT32) d) << 21) | (((UINT32) c) << 16) \ - ) \ - ) \ - ) \ - ) \ -) - -/** - LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex): - This is one way link: any write to LowerBitFieldIndex would write to HigherBitFieldIndex, - but NOT the other way around. - Requirement: LowerBitFieldIndex must be declared *right* before HigherBitFieldIndex. - - @param[in] TableName - @param[in] LowerBitFieldIndex - @param[in] HigherBitFieldIndex - - @return TSEFO Access params encrypted in TSEFO format. ---*/ -#define LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex) { \ - ASSERT (LowerBitFieldIndex == (HigherBitFieldIndex - 1)) ; \ - TableName[LowerBitFieldIndex] = TableName[LowerBitFieldIndex] | (((UINT32) 1) << 26); \ -} - -// Indicate when a bitfield has multiple memory Pstate copy -#define MULTI_MPSTATE_COPY_TSEFO(TableName, BitFieldName) \ - TableName[BitFieldName] = TableName[BitFieldName] | (((UINT32) 1) << 29) - -#define TSEFO_TYPE(x) ((UINT8) (((UINT32) (x) >> 30) & 0x03)) -#define TSEFO_START(x) ((UINT8) (((UINT32) (x) >> 21) & 0x1F)) -#define TSEFO_END(x) ((UINT8) (((UINT32) (x) >> 16) & 0x1F)) -#define TSEFO_OFFSET(x) ((UINT32) (x) & 0xFFFF) -#define TSEFO_LINKED(x) ((UINT8) (((UINT32) (x) >> 26) & 0x01)) -#define TSEFO_DIRECT_EN(x) ((UINT8) (((UINT32) (x) >> 28) & 0x01)) -#define TSEFO_WHOLE_REG_ACCESS(x) ((UINT8) (((UINT32) (x) >> 27) & 0x01)) -#define _FN(x, y) (((UINT32) (x) << 12) + (UINT32) (y)) -#define TSEFO_MULTI_MPSTATE_COPY(x) ((UINT8) (((UINT32) (x) >> 29) & 1)) -#define _NOT_USED_ 0 - -/* */ -#define B0_DLY 0 -#define B1_DLY 1 -#define B2_DLY 2 -#define B3_DLY 3 -#define B4_DLY 4 -#define B5_DLY 5 -#define B6_DLY 6 -#define B7_DLY 7 -#define ECC_DLY 8 - -#define DDR2_TRAIN_FLOW 0 -#define DDR3_TRAIN_FLOW 1 - -// -// Minimum Data Eye width in consecutive 32nds of a UI of -// valid data -// -#define MIN_RD_DATAEYE_WIDTH_NB 4 -#define MIN_WR_DATAEYE_WIDTH_NB 4 - -// -// RELIABLE READ/WRITE MODE DEFINITIONS -// -#define PRECHARGE_ALL_BANKS 0xFF ///< Use to specify PrechargeAll Command to Precharge Cmd Function -#define CMD_TGT_A 0x00 ///< Issue Commands to Command Target A -#define CMD_TGT_AB 0x01 ///< Issue Commands to Command Targets A and B -#define CMD_TYPE_READ 0x00 ///< Read Command -#define CMD_TYPE_WRITE 0x01 ///< Write Command -#define CMD_TYPE_WR_RD 0x02 ///< Alternating Write and Read Commands -#define CPG_BANK_ADDRESS_A 0x0 ///< Dimm Bank address used in Reliable RD/RW mode training -#define CPG_BANK_ADDRESS_B 0x1 ///< Dimm Bank address used in Reliable RD/RW mode training -#define CPG_ROW_ADDRESS_A 0x0 ///< Dimm Row address used in Reliable RD/RW mode training -#define CPG_ROW_ADDRESS_B 0x0 ///< Dimm Row address used in Reliable RD/RW mode training -#define CPG_COL_ADDRESS_A 0x0 ///< Dimm Column address used in Reliable RD/RW mode training -#define CPG_COL_ADDRESS_B 0x0 ///< Dimm Column address used in Reliable RD/RW mode training -#define CPG_COMPARE_MASK_LOW 0x00000000 ///< Dram DQMask[31:0] used to mask comparison on reads. 1=ignore -#define CPG_COMPARE_MASK_HI 0x00000000 ///< Dram DQMask[63:32] used to mask comparison on reads. 1=ignore -#define CPG_COMPARE_MASK_ECC 0x00 ///< Dram EccMask used to mask comparison on reads. 1=ignore -#define PRBS_SEED_32 0x062221 ///< Data PRBS Seed -#define PRBS_SEED_64 0x066665 ///< Data PRBS Seed -#define PRBS_SEED_128 0x026666 ///< Data PRBS Seed -#define PRBS_SEED_256 0x044443 ///< Data PRBS Seed - - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/// Structure for Reliable Read/Write Mode Data -/// These are values that may need to be referenced by the low level functions -/// during training and are initialized at the begining of a particular type of training. -typedef struct _RRW_SETTINGS { - UINT8 CmdTgt; ///< Value to program into CmdTgt - UINT8 TgtBankAddressA; ///< Target A Bank address - UINT32 TgtRowAddressA; ///< Target A Row address - UINT32 TgtColAddressA; ///< Target A Column address - UINT8 TgtBankAddressB; ///< Target B Bank address - UINT32 TgtRowAddressB; ///< Target B Row address - UINT32 TgtColAddressB; ///< Target B Column address - UINT32 CompareMaskLow; ///< Compare Mask Bits 31:0 - UINT32 CompareMaskHigh; ///< Compare Mask Bits 63:32 - UINT8 CompareMaskEcc; ///< Compare Mask Ecc - UINT32 DataPrbsSeed; ///< PRBS Seed value -} RRW_SETTINGS; - -/// DQS training related delays -typedef enum { - AccessRcvEnDly, ///< Receiver enable delay - AccessWrDatDly, ///< Write data delay - AccessRdDqsDly, ///< Read DQS delay - AccessWrDqsDly, ///< Write DQS delay - AccessPhRecDly, ///< Phase recovery delay - AccessRdDqs__Dly ///< Read DQS delay -} TRN_DLY_TYPE; - -/// Training patterns for position training -typedef enum { - POS_PATTERN_72B, ///< 72 bit pattern - POS_PATTERN_256B, ///< 256 bit pattern -} POS_TRN_PATTERN_TYPE; - -/// ODT mode -typedef enum { - MISSION_MODE, ///< ODT during mission mode - WRITE_LEVELING_MODE ///< ODT during write leveling -} ODT_MODE; - -/* - * DRBN - Dimm-Rank-Byte-Nibble - * 31:12 Reserved - * 11:09 Dimm (3-bits) - * 08 Rank (1-bit) - * 07:05 Reserved - * 04:01 Byte (4-bits) - * 00 Nibble (1-bit) - */ -typedef UINT32 DRBN; -#define MAKE_DRBN(dimm, rank, byte, nibble) ((((UINT32) (dimm)) << 9) | (((UINT32) (rank)) << 8) | \ -(((UINT32) (byte)) << 1) | ((UINT32) (nibble)) ) -#define DIMM_BYTE_ACCESS(dimm, byte) ((((UINT32) (dimm)) << 9) | (((UINT32) (byte)) << 1)) -#define CS_NBBL_ACCESS(cs, nibble) ((((UINT32) (cs)) << 8) | ((UINT32) (nibble))) -#define DIMM_NBBL_ACCESS(dimm, nibble) ((((UINT32) (dimm)) << 9) | ((UINT32) (nibble))) -#define DRBN_DIMM(x) ((UINT8) (((UINT32) (x) >> 9) & 0x07)) -#define DRBN_RANK(x) ((UINT8) (((UINT32) (x) >> 8) & 0x01)) -#define DRBN_BYTE(x) ((UINT8) (((UINT32) (x) >> 1) & 0x0F)) -#define DRBN_NBBL(x) ((UINT8) (((UINT32) (x)) & 0x01)) -#define DRBN_DIMM_NBBL(x) ((UINT8) (((UINT32) (x)) & 0x1F)) - -/* Dimm Type mask */ -#define DT_X4 0x01 -#define DT_X8 0x02 -#define DT_X16 0x04 -#define DT_SR 0x10 -#define DT_DR 0x20 -#define DT_QR 0x40 - -#define DT_ANY_X4 0x71 -#define DT_ANY_X8 0x72 -#define DT_ANY_X16 0x74 -#define DT_ANY_SR 0x17 -#define DT_ANY_DR 0x27 -#define DT_ANY_QR 0x47 -#define DT_ANY_SR_DR (DT_ANY_SR | DT_ANY_DR) -#define DT_ANY (DT_ANY_SR | DT_ANY_DR | DT_ANY_QR) - -/// Delay Scaling Info Struct - Describes number of delay increments per UI of a delay type -/// -typedef struct _TRN_DLY_PARMS { - UINT8 Min; ///< Minimum Value - UINT8 Max; ///< Maximum Value - UINT8 Mask; ///< Mask to be applied (i.e. 0xFF if adjustable by one, 0xFE if adjustable by 2, etc.) -} TRN_DLY_PARMS; - -/// Structure for certain data saving needed for DCT. -typedef struct { - UINT8 RcvEnDlyCounts[8]; ///< DQS Receiver Enable Delay counts - UINT32 PhRecReg[3]; ///< 3 Phase recovery control registers - BOOLEAN Is__x4; ///< Check if training is enabled and x4 DIMMs are installed -} MEM_DCT_CACHE; - -/// Structure for table driven support. -typedef struct _MEM_TBL_ALIAS { - UINT8 time; ///< Modification time. - UINT8 node:4; ///< Node on which to make modification. - UINT8 dct:4; ///< DCT on which to make modification. - UINT8 dimm:4; ///< Dimm on which to make modification. - UINT8 attr:3; ///< Attribute of modification. - UINT8 vtype:1; ///< Flag indicating value type. - UINT32 bfindex; ///< Bit field index that need to be modified. - union { ///< Union is defined to easy select between single and multiple bytelane cases. - struct { ///< Sub-struct used for one bytelane value. - UINT16 bytelane:16; ///< Bytelane on which to make modification. - UINT32 value; ///< Modified value. - UINT8 reserved[3]; ///< Reserved for this purpose - } s; ///< single value to one or multiple bytelanes - UINT8 bytelanevalue[9]; ///< Array to specify individual bytelane values - } data; -} MEM_TABLE_ALIAS; - -/// Structure for Platform Specific Block. -typedef struct _MEM_PS_BLOCK { - UINT8 DramTerm; ///< Dram Term - UINT8 QR_DramTerm; ///< Dram Term for QR - UINT8 DynamicDramTerm; ///< Dynamic Dram Term - UINT8 NumOfReg[MAX_DIMMS_PER_CHANNEL]; ///< Number of registers on each RDIMM (From SPD) - UINT8 MR0WR; ///< MR0WR - UINT8 MR0CL31; ///< MR0[CL][3:1] - UINT8 MR0CL0; ///< MR0CL[0] - UINT8 RttNom[8]; ///< RttNom value for maximum 8 chipsels per channel - UINT8 RttWr[8]; ///< RttWr value for maximum 8 chipsels per channel - UINT8 F0RC8; ///< F0RC8 - UINT8 F1RC0; ///< F1RC0 - UINT8 F1RC1; ///< F1RC1 - UINT8 F1RC2; ///< F1RC2 - UINT8 RC10OpSpd; ///< RC10[OperatingSpeed] - UINT8 LrdimmRowAddrBits[MAX_DIMMS_PER_CHANNEL]; ///< Effective Row address bits used by LRDIMMS - UINT16 SpeedLimit[VOLT1_25_ENCODED_VAL + 1]; ///< SpeedLimit of individual VDDIO - UINT8 WLSeedVal; ///< Seed value of WL training extracted from PSC table - UINT16 HWRxENSeedVal; ///< Seed value of HW RxEn training extracted from PSC table - - /* PUBLIC functions */ - BOOLEAN (*MemPDoPs) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets Form factor info. - VOID (*MemPGetPORFreqLimit) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets the speed limit of a dimm population. - BOOLEAN (*MemPGetPass1Seeds) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets pass1 seeds of WL and RxEn training. -} MEM_PS_BLOCK; - -/// Structure parameters needed in frequency change of client NB. -typedef struct _MEM_FREQ_CHANGE_PARAM { - UINT16 PllLockTimeDefault; ///< Default PllLockTime - UINT8 RdPtrInit667orHigher; ///< RdPtrInit for frequency 667MHz and higher - UINT8 RdPtrInitLower667; ///< RdPtrInit for frequency lower than 667MHz - UINT8 NclkPeriodMul2x; ///< Multiplier for NclkPeriod in parial sum calculation x 2 - UINT8 MemClkPeriodMul2x; ///< Multiplier for MemClkPeriod in parial sum calculation x 2 - UINT8 SyncTimeMul4x; ///< Multiplier for SyncTime - UINT16 TDataProp800orHigher; ///< TDataProp for frequency 800MHz or higher - UINT16 TDataPropLower800; ///< TDataProp for frequency lower than 800MHz -} MEM_FREQ_CHANGE_PARAM; - -/// List for NB items that are supported -typedef enum { - SetSpareEn, ///< Sets spare enable - CheckSpareEn, ///< Spare enabled - SetDllShutDown, ///< Sets DllShutDown - CheckEccDLLPwrDnConfig, ///< Checks to determine if EccDLLPwrDnConf needs to be adjusted - DimmBasedOnSpeed, ///< Checks to determine if Dimm number needs to be adjusted based on speed - CheckMaxDramRate, ///< Checks to determine the maximum rate - Check1GAlign, ///< Checks to determine if 1 GB alignment is supported - DramModeBeforeDimmPres, ///< Check to determine if DRAM mode needs to be set before dimm presence - DramModeAfterDimmPres, ///< Check to determine if DRAM mode needs to be set after dimm presence - CheckClearOnDimmMirror, ///< Check to determine if we need to clear on DIMM mirror - CheckDisDllShutdownSR, ///< Check to determine if DisDllShutdown needs to be set - CheckMemClkCSPresent, ///< Check to determine if chipselect needs to be set based on disabled memclocks - CheckChangeAvgValue, ///< Check to determine if we need to change average value - CheckMaxRdDqsDlyPtr, ///< Check to determine change Max Rd Dqs Delay - CheckPhyFenceTraining, ///< Check to determine if we need to Phy Fence training - CheckGetMCTSysAddr, ///< Check to determine if we need to GetMCTSysAddr - CheckSendAllMRCmds, ///< Check to determine if we need to SendAllMRCmds - CheckFindPSOverideWithSocket, ///< Check to determine if we need to Find PSOveride With Socket - CheckFindPSDct, ///< Check to determine if we need to Find PSOveride With DCT - CheckODTControls, ///< Check to determine if we need to set ODT controls - CheckDummyCLRead, ///< Check to determine if an extra dummy read is required - CheckDllStdBy, ///< Check to determine if setting DLL stand by is required - CheckSlewWithMarginImprv, ///< Check to determine if setting of Slew With MarginImprv is required - CheckSlewWithoutMarginImprv, ///< Check to determine if setting of Slew Without MarginImprv is required - CheckDllSpeedUp, ///< Check to determine if setting of Dll SpeedUp is required - CheckDllRegDis, ///< Check to determine if setting of DLL Regulator Disable is required - FenceTrnBeforeDramInit, ///< Check to determine if fence training has been done before Dram init - WLSeedAdjust, ///< Check to determine if WL seed needs to be adjusted - UnifiedNbFence, ///< Check to determine if Phy fence is of Unified NB - AdjustTwr, ///< Check to determine if Twr needs to be adjusted - ChannelPDMode, ///< Check to determine if channel power down mode is the only that is supported - ForceEnMemHoleRemapping, ///< Check to determine if we need to force enabling memory hole remapping - AdjustTrdrdSD, ///< Check to determine if we need to adjust TrdrdSD - ReverseMaxRdLatTrain, ///< Check to determine if reverse (pass to fail) algorithm is supported for MaxRdLat training - SkipErrTrain, ///< Check to determine if skip error training is supported - DramSrHys, ///< Check to determine if DRAM SR hysteresis is supported - PchgPDMode, ///< Check to determine if Precharge powerdown mode is supported - EccByteTraining, ///< Check to determine if DRAM ECC Byte training - CheckDrvImpCtrl, ///< Check to determine if we need to set DrvImpCtrl - CheckDramTerm, ///< Check to determine if we need to set DramTerm - CheckDramTermDyn, ///< Check to determine if we need to set DramTermDyn - CheckQoff, ///< Check to determine if we need to set Qoff - CheckSetSameDctODTsEn, ///< Check to defermine if we need to set "ODTsEn" the same on each DCT - WLNegativeDelay, ///< Check to determine if the NB can tolerate a negtive WL delay value - SchedDlySlot1Extra, ///< Check to determine if DataTxSchedDly Slot1 equation in slowMode to subtract an extra MEMCLK - TwoStageDramInit, ///< Check to determine if we need to seperate Draminit into 2 stages. The first one processes info on all nodes. The second one does Dram Init. - ExtraPclkInMaxRdLat, ///< Check to determine if an extra PCLK is needed for MaxRdLat - CsrPhyPllPdEn, ///< Check to determine if CSR Phy PLL Powerdown is enabled or not - AdjustTrc, ///< Check to determine if we need to adjust Trc - ProgramCsrComparator, ///< Check to determine if we need to program CsrComparator with the same value as D18F2x09C_x0D0F_0[7:0]1F[RxVioLvl] - EnProcOdtAdvForUDIMM, ///< Check to determine if we need to always enable ProcOdtAdv for UDIMM - SetTDqsForx8DimmOnly, ///< Only set MR1[TDQS] for x8 DIMMs when x4 and x8 DIMMs are both present on a channel - WlRttNomFor1of3Cfg, ///< Set Rtt_Nom = Rtt_Wr in one of three DIMMs per channel configurations - PerformanceOnly, ///< Only support performance policy, does not support battery life policy - AdjustTrp, ///< Check to determin if Trp needs to be adjusted - DllStaggerEn, ///< Check to determin if Dll Stagger should be turned on - - EnumSize ///< Size of list -} NB_SUPPORTED; - -/// List for family specific functions that are supported -typedef enum { - BeforePhyFenceTraining, ///< Family specific tasks before Phy Fence Training - BeforeMemClkFreqVal, ///< hook before setting MemClkFreqVal bit - AfterMemClkFreqVal, ///< Override PllMult and PllDiv - OverridePllMult, ///< Override PllMult - OverridePllDiv, ///< Override PllDiv - BeforeMemClr, ///< Before MemClr - SendMrsCmdsPerCs, ///< Send MRS commands per CS - SetupHwTrainingEngine, ///< Setup Hardware training engine for specific training type - OverrideRcvEnSeed, ///< Override seed for hardware based RcvEn training - AddlMaxRdLatTrain, ///< Perform additional MaxRdLat training if needed - ForceAutoComp, ///< Force Auto Comp - DetectMemPllError, ///< Detect MemPll Divide by 3 bug - ReEnablePhyComp, ///< Re-Enable Phy Compensation after RcvEn Training - ExtractWLODT, ///< Extract WL ODT value thr given ODT pattern - DCTSelectSwitch, ///< Select DCT when we switch DCT - ScrubberErratum, ///< Erratum for setting scrubber rate - MR0_PPD, ///< Override MR0[PPD] - GetDdrMaxRate, ///< Interpret DdrMaxRate with Familiy-specific encoding - ExitPhyAssistedTraining, ///< Perform family specific tasks when exiting phy assisted training - AfterSaveRestore, ///< Action after save/restore execution - OverrideDataTxFifoWrDly, ///< Override DataTxFifoWrDly based on training result of WrDatDly - OverrideRcvEnSeedPassN, ///< Override seed for hardware based RcvEn training where N greater than 0 - AfterMemClkFreqChg, ///< Reprogram DIMMs' buffers after MEMCLK frequency change - AdjustTxpdll, ///< Adjust Txpdll value to encoded register value - CalcWrDqDqsEarly, ///< Calculate WrDqDqsEarly - TrainWlPerNibble, ///< Train Write Leveling per nibble - TrainWlPerNibbleAdjustWLDly, ///< Train WL per nibble and adjust the WL delay - TrainWlPerNibbleSeed, ///< Save the seed for WL nibble based training - TrainRxEnPerNibble, ///< Train Rx Enable Training per nibble - TrainRxEnAdjustDlyPerNibble, ///< Train Rx Enable Training nibble and adjust the RxEn delay - TrainRxEnGetAvgDlyPerNibble, ///< Display Rx Enable Training average nibble value for each BL - InitPerNibbleTrn, ///< Initiates Per Nibble Training. - BeforeSetCsTri, ///< Modify CS tri-state bit map. - ForceRdDqsPhaseB, ///< Force RdDqsDly to phase B - SetDqsODT, ///< Set DQS ODT - DisLowPwrDrvStr, ///< Hook to skip setting LowPowerDriveStrengthEn - AdjustRdDqsDlyOffset, ///< Adjust the bit offset of the RdDqsDly Bit Bitfield before writing and after reading - ResetRxFifoPtr, ///< Reset RxFifo pointer during Read DQS training - EnableParityAfterMemRst, ///< Enable DRAM Address Parity after memory reset. - FinalizeVDDIO, ///< Finalize VDDIO - TrainingNibbleZero, ///< Check for see Nibble zero is being trained (individually or with x8 training) - ProgOdtControl, ///< Calculate RdOdtTrnOnDly and RdOdtOnDuration - SetSkewMemClk, ///< Set SkewMemClk - OverrideWLSeed, ///< Override WL seed - ForcePhyToM0, ///< Force Phy to M0 - AdjustCSIntLvLowAddr, ///< Adjust CS interleaving low address - Adjust2DVrefStepSize, ///< Adjusts the step size for Vref during RdDqs training - Adjust__RdDqsStepSize, ///< Adjusts the step size for RdDqs during RdDqs training - ReleaseNbPstate, ///< Release NB P-state - InitializeRxEnSeedlessTraining, ///< Initializes RxEn Seedless Training - TrackRxEnSeedlessRdWrNoWindBLError, ///< Track Bytelane Errors resulting from No window for RxEn Seedless Training - TrackRxEnSeedlessRdWrSmallWindBLError, ///< Track Bytelane Errors resulting from Small window for RxEn Seedless Training - InitialzeRxEnSeedlessByteLaneError, ///< Initializes ByteLaneError to False for RxEn Seedless Training - InitExtMMIOAddr, ///< Initializes extended MMIO address space - MemPstateStageChange, ///< handle training when multiple memory pstate is supported - ProgramFence2RxDll, ///< program RxDll in a different register - RdDqsDlyRestartChk, ///< Check to see if we need to restart RdDqsDly - BeforeWrDatTrn, ///< Check to see if special handling is needed before WrDatDly Training - ForceLvDimmVoltage, ///< Force LVDIMM voltage to 1.5V - BfAfExcludeDimm, ///< Workaround before and after excluding dimms - AdjustWrDqsBeforeSeedScaling, ///< For some family, negative WL is compensated and WrDqs needs to be adjusted before seed scaling - OverridePrevPassRcvEnDly, ///< Check to determine if we need override PrevPassRcvEnDly - AdjustRdPtrInit, ///< Adjust RdPtrInit value according to certain conditions - Adjust2DPhaseMaskBasedOnEcc, ///< Adjusts the Phase Mask Based on ECC - FixupSysAddr, ///< Adjust physical address before identifying DIMM. - RegAccessFence, ///< Make sure previous phy registers writes are done - - NumberOfHooks ///< Size of list -} FAMILY_SPECIFIC_FUNC_INDEX; - -///< Entry for SPD Timing -typedef struct { - BIT_FIELD_NAME BitField; ///< Bit field name of the timing - UINT8 Min; ///< Minimum value for timing - UINT8 Max; ///< Maximum value for timing - UINT8 Bias; ///< Bias from actual value - UINT8 Ratio_x2; ///< Actual value will be multiplied by (Ratio_x2/2) -} CTENTRY; - -/// Structure for northbridge block. -typedef struct _MEM_NB_BLOCK { - MEM_DATA_STRUCT *MemPtr; ///< Point to MEM_DATA_STRUCT. - MEM_PARAMETER_STRUCT *RefPtr; ///< Point to MEM_PARAMETER_STRUCT. - DIE_STRUCT *MCTPtr; ///< point to current Node's MCT struct - DCT_STRUCT *DCTPtr; ///< point to current Node's DCT struct - DCT_STRUCT *AllDCTPtr; ///< point to all Node's DCT structs - CH_DEF_STRUCT *ChannelPtr; ///< point to current channel data - SPD_DEF_STRUCT *SPDPtr; ///< Point to SPD data for current DCT. - struct _MEM_TECH_BLOCK *TechPtr; ///< point to technology block. - struct _MEM_FEAT_BLOCK_NB *FeatPtr; ///< point to NB Specific feature block. - struct _MEM_SHARED_DATA *SharedPtr; ///< Pointer to Memory scratchpad area - struct _MEM_NB_BLOCK *AdjacentDieNBPtr; ///< Pointer to Adjacent Die In same socket - BOOLEAN DieEnabled[MAX_NODES_SUPPORTED];///< Indicates the Dies that are enabled - SPD_DEF_STRUCT *AllNodeSPDPtr; ///< Point to SPD data for the system. - DIE_STRUCT *AllNodeMCTPtr; ///< point to all Node's MCT structs - UINT8 DimmToBeUsed; ///< Dimm to be used in recovery mode. - MEM_PS_BLOCK *PsPtr; ///< point to platform specific block - MEM_PS_BLOCK *PSBlock; ///< point to the first platform specific block on this node. - MEM_FREQ_CHANGE_PARAM *FreqChangeParam; ///< pointer to parameter of frequency change. - - PCI_ADDR PciAddr; ///< PCI address for this node - TSEFO *NBRegTable; ///< contains all bit field definitions - - UINT8 Node; ///< current node. - UINT8 Dct; ///< current DCT. - UINT8 Channel; ///< current channel. - UINT8 DctCount; ///< number of DCTs on the current NB. - UINT8 ChannelCount; ///< number of channels per DCT of the current NB. - UINT8 NodeCount; ///< number of Nodes supported - BOOLEAN Ganged; ///< mode for current MCT controller. - POS_TRN_PATTERN_TYPE PosTrnPattern; ///< specifies the pattern that should be used for position training. - BOOLEAN MemCleared; ///< memory clear flag. - UINT32 CPGInit; ///< continuous pattern generation flag. - UINT16 StartupSpeed; ///< startup speed for DDR3. - UINT16 RcvrEnDlyLimit; ///< maximum value that RcvrEnDly field can take. - UINT32 McaNbCtlReg; ///< reserve MCA reports. - UINT32 VarMtrrHiMsk; ///< variable MTRR mask for upper 32 bits. - UINT32 CsRegMsk; ///< mask for CS base register - UINT32 NBClkFreq; ///< Current NB Clock frequency - UINT8 DefDctSelIntLvAddr; ///< Default DctSelIntLvAddr - UINT8 TrainingSequenceIndex; ///< Index into the Training Sequence - RRW_SETTINGS RrwSettings; /// - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/// Test patterns for DQS training -typedef enum { - TestPattern0, ///< Test pattern used in first pass of receiver enable training - TestPattern1, ///< Test pattern used in first pass of receiver enable training - TestPattern2, ///< Test pattern used in second pass of receiver enable training - TestPatternJD1B, ///< 72-bit test pattern used in position training (ganged mode) - TestPatternJD1A, ///< 72-bit test pattern used in position training - TestPatternJD256B, ///< 256-bit test pattern used in position training (ganged mode) - TestPatternJD256A, ///< 256-bit test pattern used in position training - TestPatternML, ///< Test pattern used in first pass of max latency training - TestPattern3, ///< Test pattern used in first pass of receiver enable training - TestPattern4 ///< Test pattern used in first pass of receiver enable training -} TRAIN_PATTERN; - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -VOID -MemUWriteCachelines ( - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -MemUReadCachelines ( - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -MemUDummyCLRead ( - IN UINT32 Address - ); - -VOID -MemUFlushPattern ( - IN UINT32 Address, - IN UINT16 ClCount - ); - - -VOID -MemUFillTrainPattern ( - IN TRAIN_PATTERN Pattern, - IN UINT8 Buffer[], - IN UINT16 Size - ); - -UINT32 -MemUSetUpperFSbase ( - IN UINT32 Address, - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -MemUSetTargetWTIO ( - IN UINT32 Address, - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -MemUResetTargetWTIO ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -MemUProcIOClFlush ( - IN UINT32 Address, - IN UINT16 ClCount, - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -MemUWait10ns ( - IN UINT32 Count, - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -MemUGetWrLvNblErr ( - IN OUT UINT16 *ErrBitmap, - IN UINT32 TestAddr, - IN UINT16 ClCount - ); - -VOID -AlignPointerTo16Byte ( - IN OUT UINT8 **BufferPtrPtr - ); - -VOID * -FindPSOverrideEntry ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN PSO_ENTRY EntryType, - IN UINT8 SocketID, - IN UINT8 ChannelID, - IN UINT8 DimmID, - IN CPU_LOGICAL_ID *LogicalIdPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GetMaxDimmsPerChannel ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID - ); - -UINT8 -GetMaxChannelsPerSocket ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GetMaxCSPerChannel ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID - ); - -UINT8 -GetSpdSocketIndex ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -GetSpdChannelIndex ( - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 SocketID, - IN UINT8 ChannelID, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -GetVarMtrrHiMsk ( - IN CPU_LOGICAL_ID *LogicalIdPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -MemUMFenceInstr ( - VOID - ); - -UINT32 -MemUnsToMemClk ( - IN MEMORY_BUS_SPEED Speed, - IN UINT32 NumberOfns - ); -#endif /* _MU_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/Makefile.inc deleted file mode 100644 index 26207664d7..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += htInitRecovery.c -libagesa-y += htInitReset.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitRecovery.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitRecovery.c deleted file mode 100644 index 2fdce7b26d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitRecovery.c +++ /dev/null @@ -1,168 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Init the Socket and Node maps for Recovery mode. - * - * Create the Socket and Node maps just like normal boot, - * except that they only indicate the BSC is present. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -#include "AGESA.h" -#include "Ids.h" -#include "Topology.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE - -AGESA_STATUS -AmdHtInitRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Get new Socket and Node Maps. - * - * Put the Socket Die Table and the Node Table in heap with known handles. - * - * @param[out] SocketDieToNodeMap The Socket, Module to Node info map - * @param[out] NodeToSocketDieMap The Node to Socket, Module map. - * @param[in] StdHeader Header for library and services. - */ -VOID -STATIC -NewNodeAndSocketTablesRecovery ( - OUT SOCKET_DIE_TO_NODE_MAP *SocketDieToNodeMap, - OUT NODE_TO_SOCKET_DIE_MAP *NodeToSocketDieMap, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 j; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - // Allocate heap for the table - AllocHeapParams.RequestedBufferSize = (((MAX_SOCKETS) * (MAX_DIES)) * sizeof (SOCKET_DIE_TO_NODE_ITEM)); - AllocHeapParams.BufferHandle = SOCKET_DIE_MAP_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - // HeapAllocateBuffer must set BufferPtr to valid or NULL. - *SocketDieToNodeMap = (SOCKET_DIE_TO_NODE_MAP)AllocHeapParams.BufferPtr; - ASSERT (SocketDieToNodeMap != NULL); - // Initialize shared data structures - for (i = 0; i < MAX_SOCKETS; i++) { - for (j = 0; j < MAX_DIES; j++) { - (**SocketDieToNodeMap)[i][j].Node = HT_LIST_TERMINAL; - (**SocketDieToNodeMap)[i][j].LowCore = HT_LIST_TERMINAL; - (**SocketDieToNodeMap)[i][j].HighCore = HT_LIST_TERMINAL; - } - } - } - // Allocate heap for the table - AllocHeapParams.RequestedBufferSize = (MAX_NODES * sizeof (NODE_TO_SOCKET_DIE_ITEM)); - AllocHeapParams.BufferHandle = NODE_ID_MAP_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - // HeapAllocateBuffer must set BufferPtr to valid or NULL. - *NodeToSocketDieMap = (NODE_TO_SOCKET_DIE_MAP)AllocHeapParams.BufferPtr; - ASSERT (NodeToSocketDieMap != NULL); - // Initialize shared data structures - for (i = 0; i < MAX_NODES; i++) { - (**NodeToSocketDieMap)[i].Socket = HT_LIST_TERMINAL; - (**NodeToSocketDieMap)[i].Die = HT_LIST_TERMINAL; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize the Node and Socket maps for an AP Core. - * - * In each core's local heap, create a Node to Socket map and a Socket/Module to Node map. - * The mapping is filled in by reading the AP Mailboxes from PCI config on each node. - * - * @param[in] StdHeader global state, input data - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -AmdHtInitRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_MAILBOXES NodeApMailBox; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - SOCKET_DIE_TO_NODE_MAP SocketDieToNodeMap = NULL; - NODE_TO_SOCKET_DIE_MAP NodeToSocketDieMap = NULL; - - NodeApMailBox.ApMailInfo.Info = 0; - NodeApMailBox.ApMailExtInfo.Info = 0; - - // Allocate heap for caching the mailboxes - AllocHeapParams.RequestedBufferSize = sizeof (AP_MAILBOXES); - AllocHeapParams.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE; - AllocHeapParams.Persist = HEAP_SYSTEM_MEM; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - *(AP_MAILBOXES *)AllocHeapParams.BufferPtr = NodeApMailBox; - } - - NewNodeAndSocketTablesRecovery (&SocketDieToNodeMap, &NodeToSocketDieMap, StdHeader); - // HeapAllocateBuffer must set BufferPtr to valid or NULL, so the checks below are ok. - - // There is no option to not have socket - node maps, if they aren't allocated that is a fatal bug. - ASSERT (SocketDieToNodeMap != NULL); - ASSERT (NodeToSocketDieMap != NULL); - - (*SocketDieToNodeMap)[0][0].Node = 0; - (*SocketDieToNodeMap)[0][0].LowCore = 0; - (*SocketDieToNodeMap)[0][0].HighCore = 0; - - // We lie about being Socket 0 and Module 0 always, it isn't necessarily true. - (*NodeToSocketDieMap)[0].Socket = (UINT8)0; - (*NodeToSocketDieMap)[0].Die = (UINT8)0; - - return AGESA_SUCCESS; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitReset.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitReset.c deleted file mode 100644 index 9e8b4efdb1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/HT/htInitReset.c +++ /dev/null @@ -1,332 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Recovery HT, a Hypertransport init for Boot Blocks. For normal - * boots, run Recovery HT first in boot block, then run full HT init - * in the system BIOS. Recovery HT moves the devices on the chain with - * the southbridge to their assigned device IDS, so that all their PCI - * Config space is accessible. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Recovery HyperTransport - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "AdvancedApi.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_RECOVERY_HT_HTINITRESET_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define MAX_NODES 1 -#define MAX_LINKS 8 - -extern CONST AMD_HT_RESET_INTERFACE HtOptionResetDefaults; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/** - * Our global state data structure. - * - * Keep track of inputs and outputs, and keep any working state. - */ -typedef struct { - AMD_HT_RESET_INTERFACE *HtBlock; ///< The interface - AGESA_STATUS Status; ///< Remember the highest severity status event - VOID *ConfigHandle; ///< Config Pointer, opaque handle for passing to lib -} HTR_STATE_DATA; - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*************************************************************************** - *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** - ***************************************************************************/ - -/*----------------------------------------------------------------------------------------*/ -/** - * Enable Routing Tables. - * - * Turns routing tables on for a node zero. - * - * @param[in] State Our State - */ - -VOID -STATIC -HtrEnableRoutingTables ( - IN HTR_STATE_DATA *State - ) -{ - PCI_ADDR Reg; - UINT32 Temp; - Temp = 0; - Reg.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0x6C); - LibAmdPciWriteBits (Reg, 0, 0, &Temp, State->ConfigHandle); -} - -/*************************************************************************** - *** Non-coherent init code *** - *** Algorithms *** - ***************************************************************************/ -/*----------------------------------------------------------------------------------------*/ -/** - * Process the SouthBridge Link. - * - * Process a non-coherent link, and setting the device ID for all devices found. - * - * @param[in] State Our State, Inputs - */ -VOID -STATIC -HtrProcessLink ( - IN HTR_STATE_DATA *State - ) -{ - UINT32 CurrentBUID; - UINT32 Temp; - UINT32 UnitIDcnt; - PCI_ADDR CurrentPtr; - UINT8 Depth; - BUID_SWAP_LIST *SwapPtr; - PCI_ADDR Link1ControlRegister; - BOOLEAN IsCaveDevice; - - // No PCI init to run, everything has to be on Bus zero. This makes fewer - // northbridge dependencies. - // - // Assign BUIDs so that config space for all devices is visible. - // - if (State->HtBlock->ManualBuidSwapList != NULL) { - // Manual non-coherent BUID assignment - // Assign BUID's per manual override - // - SwapPtr = &(State->HtBlock->ManualBuidSwapList->SwapList); - Depth = 0; - while (SwapPtr->Swaps[Depth].FromId != 0xFF) { - CurrentPtr.AddressValue = MAKE_SBDFO (0, 0, SwapPtr->Swaps[Depth].FromId, 0, 0); - - do { - LibAmdPciFindNextCap (&CurrentPtr, State->ConfigHandle); - ASSERT (CurrentPtr.AddressValue != ILLEGAL_SBDFO); - LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle); - } while ((Temp & (UINT32)0xE00000FF) != (UINT32)0x00000008); // HyperTransport Slave Capability - - CurrentBUID = SwapPtr->Swaps[Depth].ToId; - // Set the device's BUID - LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBUID, State->ConfigHandle); - Depth++; - } - } else { - // Automatic non-coherent device detection - Depth = 0; - CurrentBUID = 1; - for (;;) { - CurrentPtr.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); - - LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle); - if (Temp == (UINT32)0xFFFFFFFF) { - // No device found at currentPtr - break; - } - - // HyperTransport Slave Capability - do { - LibAmdPciFindNextCap (&CurrentPtr, State->ConfigHandle); - if (CurrentPtr.AddressValue == ILLEGAL_SBDFO) { - // There is a device at currentPtr, but it isn't an HT device. - return; - } - LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle); - } while ((Temp & (UINT32)0xE00000FF) != (UINT32)0x00000008); // HyperTransport Slave Capability - - // Get the device's Unit ID Count. - LibAmdPciReadBits (CurrentPtr, 25, 21, &UnitIDcnt, State->ConfigHandle); - if ((UnitIDcnt + CurrentBUID) > 24) { - // An error handler for the case where we run out of BUID's on a chain - State->Status = AGESA_ERROR; - ASSERT (FALSE); - return; - } - // While we are still certain we are accessing this device, remember if it is a cave device. - // This is found by reading EOC from the Link 1 Control Register. - Link1ControlRegister = CurrentPtr; - Link1ControlRegister.Address.Register += 8; - LibAmdPciReadBits (Link1ControlRegister, 6, 6, &Temp, State->ConfigHandle); - IsCaveDevice = ((Temp == 0) ? FALSE : TRUE); - - // Set the device's BUID - IDS_HDT_CONSOLE (HT_TRACE, "Device found at depth=%d.\n", Depth); - LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBUID, State->ConfigHandle); - - CurrentPtr.Address.Device = CurrentBUID; - // Get the device's BUID - LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle); - if (Temp != CurrentBUID) { - if ((Depth == 0) && IsCaveDevice) { - // If the chain only consists of a single cave device, that device may have retained zero - // for it's BUID. - CurrentPtr.Address.Device = 0; - LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle); - if (Temp == 0) { - // Per HyperTransport specification, devices not accepting BUID reassignment hardwire BUID to zero. - Depth++; - // Success! - IDS_HDT_CONSOLE (HT_TRACE, "Compliant Cave at BUID=0.\n"); - break; - } else if (Temp == CurrentBUID) { - // and then, there are the other kind of devices .... - // Restore the writable BUID field (which contains the value we just wrote) to zero. - Temp = 0; - LibAmdPciWriteBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle); - Depth++; - // Success! - IDS_HDT_CONSOLE (HT_TRACE, "Cave left at BUID=0.\n"); - break; - } - } - // An error handler for this critical error - State->Status = AGESA_ERROR; - ASSERT (FALSE); - return; - } - - IDS_HDT_CONSOLE (HT_TRACE, "Compliant Device assigned at BUID=%d.\n", CurrentBUID); - Depth++; - CurrentBUID += UnitIDcnt; - } - // Provide information on automatic device results - State->HtBlock->Depth = Depth; - } -} - -/*************************************************************************** - *** HT Reset Initialize *** - ***************************************************************************/ - -/** - * A constructor for the HyperTransport input structure. - * - * Sets inputs to valid, basic level, defaults. - * - * @param[in] StdHeader Config handle - * @param[in,out] AmdHtResetInterface HT Interface structure to initialize. - * - * @retval AGESA_SUCCESS Constructors are not allowed to fail -*/ -AGESA_STATUS -AmdHtResetConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ) -{ - AmdHtResetInterface->ManualBuidSwapList = HtOptionResetDefaults.ManualBuidSwapList; - return AGESA_SUCCESS; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize HT for Reset, Boot Blocks. - * - * This is the top level external interface for Hypertransport Reset Initialization. - * Create our initial internal state and initialize the non-coherent chain to the - * southbridge. This interface must be executed by both normal and recovery boot paths. - * - * @param[in] StdHeader Interface structure - * @param[in] AmdHtResetInterface our interface and inputs - * - * @retval AGESA_SUCCESS Successful init - * @retval AGESA_ERROR Device Error, BUID max exceed error. - * - */ -AGESA_STATUS -AmdHtInitReset ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ) -{ - HTR_STATE_DATA State; - AGESA_STATUS IgnoredStatus; - - State.Status = AGESA_SUCCESS; - if (IsBsp (StdHeader, &IgnoredStatus)) { - State.ConfigHandle = (AMD_CONFIG_PARAMS *)StdHeader; - State.HtBlock = AmdHtResetInterface; - HtrEnableRoutingTables (&State); - - HtrProcessLink (&State); - } - return State.Status; -} diff --git a/src/vendorcode/amd/agesa/f15/errno.h b/src/vendorcode/amd/agesa/f15/errno.h deleted file mode 100644 index 2d90c8dfe9..0000000000 --- a/src/vendorcode/amd/agesa/f15/errno.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -// this dummy errno.h prevents an agesa build failure when the gcc -// cross compiler target is i386-elf. In this case, mm_malloc.h -// includes errno.h, but the gcc cross compiler does not supply it. - -extern int errno; -#define EINVAL 1 diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc deleted file mode 100644 index b5f8fddcbf..0000000000 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ /dev/null @@ -1,1618 +0,0 @@ -/* - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/****************************************************************************** -* AMD Generic Encapsulated Software Architecture -* -* $Workfile:: GccCar.inc $Revision:: 32932 $ -* -* Description: GccCar.inc - AGESA cache-as-RAM setup Include File for GCC complier -* -******************************************************************************/ - -.altmacro - -BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ -BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ -CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ -CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ -CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ - -#ifdef __x86_64__ -CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */ -#else -CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ -#endif - -APIC_BASE_ADDRESS = 0x0000001B - APIC_BSC = 8 /* Boot Strap Core */ - -AMD_MTRR_VARIABLE_BASE0 = 0x0200 -AMD_MTRR_VARIABLE_BASE6 = 0x020C -AMD_MTRR_VARIABLE_MASK7 = 0x020F -AMD_MTRR_FIX64k_00000 = 0x0250 -AMD_MTRR_FIX16k_80000 = 0x0258 -AMD_MTRR_FIX16k_A0000 = 0x0259 -AMD_MTRR_FIX4k_C0000 = 0x0268 -AMD_MTRR_FIX4k_C8000 = 0x0269 -AMD_MTRR_FIX4k_D0000 = 0x026A -AMD_MTRR_FIX4k_D8000 = 0x026B -AMD_MTRR_FIX4k_E0000 = 0x026C -AMD_MTRR_FIX4k_E8000 = 0x026D -AMD_MTRR_FIX4k_F0000 = 0x026E -AMD_MTRR_FIX4k_F8000 = 0x026F - -/* Reproduced from AGESA.h */ -AMD_AP_MTRR_FIX64k_00000 = 0x00000250 -AMD_AP_MTRR_FIX16k_80000 = 0x00000258 -AMD_AP_MTRR_FIX16k_A0000 = 0x00000259 -AMD_AP_MTRR_FIX4k_C0000 = 0x00000268 -AMD_AP_MTRR_FIX4k_C8000 = 0x00000269 -AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A -AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B -AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C -AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D -AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E -AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F -CPU_LIST_TERMINAL = 0xFFFFFFFF - -AMD_MTRR_DEFTYPE = 0x02FF - WB_DRAM_TYPE = 0x1E /* MemType - memory type */ - MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ - MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ - -HWCR = 0x0C0010015 /* Hardware Configuration */ - INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ - -IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ - /* uses 16h - 19h */ -TOP_MEM = 0x0C001001A /* Top of Memory */ -TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ - -LS_CFG = 0x0C0011020 /* Load-Store Configuration */ - DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ - DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ - -IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ - IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ - DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ - DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ - -DC_CFG = 0x0C0011022 /* Data Cache Configuration */ - DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ - DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ - DIS_HW_PF = 13 /* Hardware prefetches bit */ - -DE_CFG = 0x0C0011029 /* Decode Configuration */ - CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ - -BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ -CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ - F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ - IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ - -CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ - COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ - - -CR0_PE = 0 # Protection Enable -CR0_NW = 29 # Not Write-through -CR0_CD = 30 # Cache Disable -CR0_PG = 31 # Paging Enable - -/* CPUID Functions */ - -CPUID_MODEL = 1 -AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ - -NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ - INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ - -MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ - CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ - SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ - MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ - MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ - MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ - MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ - -PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ - PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ - PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ - CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ - CONFIG_EVENT_H = 4 /* Increment count by number of event */ - /* occured in clock cycle */ - EVENT_ENABLE = 22 /* Enable the event */ -PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ - -# Local use flags, in upper most byte if ESI -FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized -FLAG_STACK_REENTRY = 25 # Signals that the environment has made a re-entry (2nd) call to set up the stack -FLAG_IS_PRIMARY = 26 # Signals that this core is the primary within the comoute unit - -CR0_MASK = ((1 << CR0_CD) | (1 << CR0_NW)) -MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) - -/**************************************************************************** - * - * CPU MACROS - PUBLIC - * - ****************************************************************************/ -.macro _WRMSR - .byte 0x0f, 0x30 -.endm - -.macro _RDMSR - .byte 0x0F, 0x32 -.endm - -.macro AMD_CPUID arg0 - .ifb \arg0 - mov $0x1, %eax - .byte 0x0F, 0x0A2 /* Execute instruction */ - bswap %eax - xchg %ah, %al /* Ext model in al now */ - rol $0x08, %eax /* Ext model in ah, model in al */ - and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */ - .else - mov \arg0, %eax - .byte 0x0F, 0x0A2 - .endif -.endm - -/**************************************************************************** -* -* AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless -* -* Set any family specific controls needed to enable the use of -* cache as general storage before main memory is available. -* -* Inputs: -* none -* Outputs: -* none - ****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK - - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 -.endm - -/**************************************************************************** -* -* AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless -* -* Return any family specific controls to their 'standard' -* settings for using cache with main memory. -* -* Inputs: -* none -* Outputs: -* none - ****************************************************************************/ -.macro AMD_DISABLE_STACK_FAMILY_HOOK - - AMD_DISABLE_STACK_FAMILY_HOOK_F10 - AMD_DISABLE_STACK_FAMILY_HOOK_F12 - AMD_DISABLE_STACK_FAMILY_HOOK_F14 - AMD_DISABLE_STACK_FAMILY_HOOK_F15 - -.endm - -/**************************************************************************** -* -* GET_NODE_ID_CORE_ID Macro - Stackless -* -* Read family specific values to determine the node and core -* numbers for the core executing this code. -* -* Inputs: -* none -* Outputs: -* SI[7:0] = Core# (0..N, relative to node) -* SI[15:8]= Node# (0..N) -* SI[23:16]= reserved -* SI[24]= flag: 1=Family Unrecognized -* SI[25]= flag: 1=Interface re-entry call -* SI[26]= flag: 1=Core is primary of compute unit -* SI[31:27]= reserved, =0 -****************************************************************************/ -.macro GET_NODE_ID_CORE_ID - LOCAL node_core_exit - - mov $-1, %si - GET_NODE_ID_CORE_ID_F10 - GET_NODE_ID_CORE_ID_F12 - GET_NODE_ID_CORE_ID_F14 - GET_NODE_ID_CORE_ID_F15 - /* - * Check for unrecognized Family - */ - cmp $-1, %si # Has family (node/core) already been discovered? - jnz node_core_exit # Br if yes - - mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue - - mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B - _RDMSR - bt $APIC_BSC, %eax # Is this the BSC? - jc node_core_exit # Br if yes - hlt # Kill APs -node_core_exit: - -.endm - -/**************************************************************************** -## Family 10h MACROS -##*************************************************************************** -#--------------------------------------------------- -# -# AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -# -# Set any family specific controls needed to enable the use of -# cache as general storage before main memory is available. -# -# Inputs: -# ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -# Outputs: -# none -# -# Family 10h requirements (BKDG section 2.3.3): -# * Paging disabled -# * MSRC001_0015[INVDWBINVD]=0 -# * MSRC001_1021[DIS_IND]=1 -# * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -# * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -# * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -# * MSRC001_1022[DIS_HW_PF]=1 -# * MSRC001_102A[IcDisSpecTlbWr]=1 -# * MSRC001_102A[ClLinesToNbDis]=1 -# * No INVD or WBINVD, no exceptions, page faults or interrupts -****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 - LOCAL fam10_enable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x01, %al # Is this family 10h? - jnz fam10_enable_stack_hook_exit # Br if no - - mov $DC_CFG, %ecx # MSR:C001_1022 - _RDMSR - bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DTLB reloads bit - bts $DIS_CLR_WBTOL2_SMC_HIT, %eax # Turn on Disable the self modifying code check buffer bit - bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit - _WRMSR - - dec %cx # MSR:C001_1021 - _RDMSR - bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative TLB reloads bit - bts $DIS_IND, %eax # Turn on Disable indirect branch predictor - _WRMSR - - mov $BU_CFG2, %ecx # MSR C001_102A - _RDMSR - bts $F10_CL_LINES_TO_NB_DIS, %eax # Allow BIOS ROM to be cached in the IC - bts $(IC_DIS_SPEC_TLB_WR-32), %edx #Disable speculative writes to the ITLB - _WRMSR - - mov $HWCR, %ecx # MSR C001_0015 - _RDMSR - bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set - jc fam10_skipClearingBit4 - btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion - _WRMSR - -fam10_skipClearingBit4: - mov %esi, %eax # load core# - or %al, %al # If (BSP) - jne fam10_enable_stack_hook_exit - mov $PERF_COUNTER3, %ecx # Select performance counter three - # to count number of CAR evictions - xor %eax, %eax # Initialize the lower part of the counter to zero - xor %edx, %edx # Initializa the upper part of the counter to zero - _WRMSR # Save it - mov $PERF_CONTROL3, %ecx # Select the event control three - _RDMSR # Get the current setting - and $PERF_CONTROL3_RESERVE_L, %eax # Preserve the reserved bits - or $CONFIG_EVENT_L, %eax # Set the lower part of event register to - # select CAR Corruption occurred by any cores - and $PERF_CONTROL3_RESERVE_H, %dx # Preserve the reserved bits - or $CONFIG_EVENT_H, %dx # Set the upper part of event register - _WRMSR # Save it - bts $EVENT_ENABLE, %eax # Enable it - _WRMSR # Save it - -fam10_enable_stack_hook_exit: -.endm - -/**************************************************************************** -* -* AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -* -* Return any family specific controls to their 'standard' -* settings for using cache with main memory. -* -* Inputs: -* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -* Outputs: -* none -* -* Family 10h requirements: -* * INVD or WBINVD -* * MSRC001_0015[INVD_WBINVD]=1 -* * MSRC001_1021[DIS_IND]=0 -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -* * MSRC001_1022[DIS_HW_PF]=0 -* * MSRC001_102A[IcDisSpecTlbWr]=0 -* * MSRC001_102A[ClLinesToNbDis]=0 -*****************************************************************************/ - -.macro AMD_DISABLE_STACK_FAMILY_HOOK_F10 - LOCAL fam10_disable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x01, %al # Is this family 10h? - jnz fam10_disable_stack_hook_exit # Br if no - - mov $DC_CFG, %ecx # MSR:C001_1022 - _RDMSR - btr $DC_DIS_SPEC_TLB_RLD, %eax # Enable speculative TLB reloads - btr $DIS_CLR_WBTOL2_SMC_HIT, %eax # Allow self modifying code check buffer - btr $DIS_HW_PF, %eax # Allow hardware prefetches - _WRMSR - - dec %cx # MSR:C001_1021 - _RDMSR - btr $DIS_IND, %eax # Turn on indirect branch predictor - btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads - _WRMSR - - mov $BU_CFG2, %ecx # MSR:C001_102A - _RDMSR -/* - * BTS error if SBIOS `allows WP code to be cached', but copying - * ramstage/payloads from ROM to RAM will be very slow if disable it here. - * - * TODO: disable `allows WP code to be cached' after the ROM to RAM copying. - */ -// btr $F10_CL_LINES_TO_NB_DIS, %eax # Return L3 to normal mode - btr $(IC_DIS_SPEC_TLB_WR-32), %edx #Re-enable speculative writes to the ITLB - _WRMSR - - #-------------------------------------------------------------------------- - # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - mov $HWCR, %ecx # MSR:0000_0015 - _RDMSR - mov %ax, %bx # Save INVD -> WBINVD bit - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion for the invd instruction. - _WRMSR - invd # Clear the cache tag RAMs - mov %bx, %ax # Restore INVD -> WBINVD bit - _WRMSR - - #-------------------------------------------------------------------------- - # End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - mov $PERF_CONTROL3, %ecx # Select the event control three - _RDMSR # Retrieve the current value - btc $EVENT_ENABLE, %eax # Is event enable, complement it as well - jnc fam10_disable_stack_hook_exit # No - cmp $CONFIG_EVENT_L, %ax # Is the lower part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit # No - cmp $CONFIG_EVENT_H, %dl # Is the upper part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit # No - _WRMSR # Disable the event - -fam10_disable_stack_hook_exit: -.endm - -/**************************************************************************** -* -* GET_NODE_ID_CORE_ID_F10 Macro - Stackless -* -* Read family specific values to determine the node and core -* numbers for the core executing this code. -* -* Inputs: -* none -* Outputs: -* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -*****************************************************************************/ -.macro GET_NODE_ID_CORE_ID_F10 - - LOCAL node_core_f10_exit - LOCAL node_core_f10_AP - - cmp $-1, %si # Has node/core already been discovered? - jnz node_core_f10_exit # Br if yes - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x01, %al # Is this family 10h? - jnz node_core_f10_exit # Br if no - - xor %esi, %esi # Assume BSC, clear flags - mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B - _RDMSR - bt $APIC_BSC, %eax # Is this the BSC? - jnc node_core_f10_AP # Br if no - - # This is the BSP. - # Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register - mov $0x0CF8, %dx - out %eax, %dx - add $4, %dx - in %dx, %eax - btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0 - out %eax, %dx - jmp 1f # - -node_core_f10_AP: - # - # This is an AP. Routing tables have been enabled by the HT Init process. - # Also, the MailBox register was set by the BSP during early init - # The Mailbox register content is formatted as follows: - # UINT32 Node:4# // The node id of Core's node. - # UINT32 Socket:4# // The socket of this Core's node. - # UINT32 Module:2# // The internal module number for Core's node. - # UINT32 ModuleType:2# // Single Module = 0, Multi-module = 1. - # UINT32 :20# // Reserved - # - mov $0x0C0000408, %ecx # Read the family 10h mailbox - _RDMSR # MC4_MISC1[63:32] - mov %dx, %si # SI = raw mailbox contents (will extract node# from this) - shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId] - mov %bx, %di # DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID $AMD_CPUID_APIC # - shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core# - inc %cl # CL = Number of enabled cores in the socket - mov %cx, %bx - - mov $NB_CFG, %ecx # MSR:C001_001F - _RDMSR # EDX has InitApicIdCpuIdLo bit - - mov %bh, %cl # CL = APIC ID size - mov $1, %al # Convert APIC ID size to an AND mask - shl %cl, %al # AL = 2^APIC ID size - dec %al # AL = mask for relative core number - xor %ah, %ah # AX = mask for relative core number - bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1? - #.if (!carry?) # Br if yes - jc 0f - mov $8, %ch # Calculate core number shift count - sub %cl, %ch # CH = core shift count - mov %ch, %cl - shr %cl, %di # Right justify core number - #.endif - 0: - and %ax, %di # DI = socket-relative core number - - mov %si, %cx # CX = raw mailbox value - shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and $3, %cl # Isolate ModuleType - xor %bh, %bh # BX = Number of enabled cores in the socket - shr %cl, %bx # BX = Number of enabled cores per node - xor %dx, %dx # Clear upper word for div - mov %di, %ax # AX = socket-relative core number - div %bx # DX = node-relative core number - movzx %si, %eax # prepare return value, [23:16]=shared Core# (=0, not shared) - and $0x000F, %ax # AX = node number - shl $8, %ax # [15:8]=node# - mov %dl, %al # [7:0]=core# (relative to node) - mov %eax, %esi # ESI = return value -1: - bts $FLAG_IS_PRIMARY, %esi # all Family 10h cores are primary -node_core_f10_exit: -.endm - - -/***************************************************************************** -** Family 12h MACROS -*****************************************************************************/ -/***************************************************************************** -* -* AMD_ENABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -* -* Set any family specific controls needed to enable the use of -* cache as general storage before main memory is available. -* -* Inputs: -* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -* Outputs: -* none -* -* Family 12h requirements (BKDG section 2.3.3): -* The following requirements must be satisfied prior to using the cache as general storage: -* * Paging must be disabled. -* * MSRC001_0015[INVD_WBINVD]=0 -* * MSRC001_1020[DIS_SS]=1 -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -* * MSRC001_1022[DIS_HW_PF]=1 -* * MSRC001_1029[ClflushSerialize]=1 -* * No INVD or WBINVD, no exceptions, page faults or interrupts -*****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F12 - LOCAL fam12_enable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x03, %al # Is this family 12h? - jnz fam12_enable_stack_hook_exit # Br if no - - mov $DC_CFG, %ecx # MSR:C001_1022 - _RDMSR - bts $DC_DIS_SPEC_TLB_RLD, %eax # Disable speculative DC-TLB reloads - bts $DIS_CLR_WBTOL2_SMC_HIT, %eax # Disable self modifying code check buffer - bts $DIS_HW_PF, %eax # Disable hardware prefetches - _WRMSR - - dec %cx #IC_CFG # MSR:C001_1021 - _RDMSR - bts $IC_DIS_SPEC_TLB_RLD, %eax # Disable speculative IC-TLB reloads - _WRMSR - - dec %cx #LS_CFG # MSR:C001_1020 - _RDMSR - bts $DIS_SS, %eax # Disabled Streaming store functionality - _WRMSR - - mov $HWCR, %ecx # MSR C001_0015 - _RDMSR - bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set - jc fam12_skipClearingBit4 - btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion - _WRMSR - -fam12_skipClearingBit4: - mov $DE_CFG, %ecx # MSR:C001_1029 - _RDMSR - bts $CL_FLUSH_SERIALIZE, %eax # Serialize all CL Flush actions - _WRMSR - -fam12_enable_stack_hook_exit: -.endm - -/***************************************************************************** -* -* AMD_DISABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -* -* Return any family specific controls to their 'standard' -* settings for using cache with main memory. -* -* Inputs: -* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -* Outputs: -* none -* -* Family 12h requirements: -* * INVD or WBINVD -* * MSRC001_0015[INVD_WBINVD]=1 -* * MSRC001_1020[DIS_SS]=0 -* * MSRC001_1021[IC_DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DC_DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -* * MSRC001_1022[DIS_HW_PF]=0 -* * MSRC001_1029[ClflushSerialize]=0 -*****************************************************************************/ -.macro AMD_DISABLE_STACK_FAMILY_HOOK_F12 - LOCAL fam12_disable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x03, %al # Is this family 12h? - jnz fam12_disable_stack_hook_exit # Br if no - - mov $DC_CFG, %ecx # MSR:C001_1022 - _RDMSR - btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative DC-TLB reloads - btr $DIS_CLR_WBTOL2_SMC_HIT, %eax # Enable self modifying code check buffer - btr $DIS_HW_PF, %eax # Enable Hardware prefetches - _WRMSR - - dec %cx #IC_CFG # MSR:C001_1021 - _RDMSR - btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative IC-TLB reloads - _WRMSR - - dec %cx #LS_CFG # MSR:C001_1020 - _RDMSR - btr $DIS_SS, %eax # Turn on Streaming store functionality - _WRMSR - - mov $DE_CFG, %ecx # MSR:C001_1029 - _RDMSR - btr $CL_FLUSH_SERIALIZE, %eax - _WRMSR - - #-------------------------------------------------------------------------- - # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - mov $HWCR, %ecx # MSR:0000_0015h - _RDMSR - mov %ax, %bx # Save INVD -> WBINVD bit - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion - _WRMSR - invd # Clear the cache tag RAMs - mov %bx, %ax # Restore INVD -> WBINVD bit - _WRMSR - - #-------------------------------------------------------------------------- - # End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - -fam12_disable_stack_hook_exit: -.endm - -/***************************************************************************** -* -* GET_NODE_ID_CORE_ID_F12 Macro - Stackless -* -* Read family specific values to determine the node and core -* numbers for the core executing this code. -* -* Inputs: -* none -* Outputs: -* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -*****************************************************************************/ -.macro GET_NODE_ID_CORE_ID_F12 - - LOCAL node_core_f12_exit - - cmp $-1, %si # Has node/core already been discovered? - jnz node_core_f12_exit # Br if yes - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x03, %al # Is this family 12h? - jnz node_core_f12_exit # Br if no - - shr $24, %ebx # CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID - bts $FLAG_IS_PRIMARY, %ebx # all family 12h cores are primary - mov %ebx, %esi # ESI = Node#=0, core number -node_core_f12_exit: -.endm - -/***************************************************************************** -** Family 14h MACROS -*****************************************************************************/ -/***************************************************************************** -* -* AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -* -* Set any family specific controls needed to enable the use of -* cache as general storage before main memory is available. -* -* Inputs: -* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -* Outputs: -* none -* -* Family 14h requirements (BKDG section 2.3.3): -* * Paging must be disabled. -* * MSRC001_0015[INVD_WBINVD]=0. -* * MSRC001_1020[DisStreamSt]=1. -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads. -* * MSRC001_1022[DIS_HW_PF]=1. -* * No INVD or WBINVD, no exceptions, page faults or interrupts -*****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F14 - LOCAL fam14_enable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x05, %al # Is this family 14h? - jnz fam14_enable_stack_hook_exit # Br if no - - mov $DC_CFG, %ecx # MSR:C001_1022 - _RDMSR - bts $DIS_HW_PF, %eax # Disable hardware prefetches - _WRMSR - - dec %cx #IC_CFG # MSR:C001_1021 - _RDMSR - bts $IC_DIS_SPEC_TLB_RLD, %eax # Disable speculative TLB reloads - _WRMSR - - dec %cx #LS_CFG # MSR:C001_1020 - _RDMSR - bts $DIS_STREAM_ST, %eax # Disabled Streaming store functionality - _WRMSR - - mov $HWCR, %ecx # MSR C001_0015 - _RDMSR - bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set - jc fam14_skipClearingBit4 - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion - _WRMSR -fam14_skipClearingBit4: # Keeping this label - -fam14_enable_stack_hook_exit: -.endm - -/***************************************************************************** -* -* AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -* -* Return any family specific controls to their 'standard' -* settings for using cache with main memory. -* -* Inputs: -* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -* Outputs: -* none -* -* Family 14h requirements: -* * INVD or WBINVD -* * MSRC001_0015[INVD_WBINVD]=1. -* * MSRC001_1020[DisStreamSt]=0. -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0. -* * MSRC001_1022[DIS_HW_PF]=0. -*****************************************************************************/ -.macro AMD_DISABLE_STACK_FAMILY_HOOK_F14 - LOCAL fam14_disable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x05, %al # Is this family 14h? - jnz fam14_disable_stack_hook_exit # Br if no - - mov $LS_CFG, %ecx # MSR:C001_1020 - _RDMSR - btr $DIS_STREAM_ST, %eax # Turn on Streaming store functionality - _WRMSR - - inc %cx #IC_CFG # MSR:C001_1021 - _RDMSR - btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative DC-TLB reloads - _WRMSR - - inc %cx #DC_CFG # MSR:C001_1022 - _RDMSR - btr $DIS_HW_PF, %eax # Turn on hardware prefetches - _WRMSR - - #-------------------------------------------------------------------------- - # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - mov $HWCR, %ecx # MSR:C001_0015h - _RDMSR - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion - _WRMSR - invd # Clear the cache tag RAMs - bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD - _WRMSR - - #-------------------------------------------------------------------------- - # End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - -fam14_disable_stack_hook_exit: -.endm - -/***************************************************************************** -* -* GET_NODE_ID_CORE_ID_F14 Macro - Stackless -* -* Read family specific values to determine the node and core -* numbers for the core executing this code. -* -* Inputs: -* none -* Outputs: -* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -*****************************************************************************/ -.macro GET_NODE_ID_CORE_ID_F14 - - LOCAL node_core_f14_exit - - cmp $-1, %si # Has node/core already been discovered? - jnz node_core_f14_exit # Br if yes - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x05, %al # Is this family 14h? - jnz node_core_f14_exit # Br if no - - xor %esi, %esi # Node must be 0 - bts $FLAG_IS_PRIMARY, %esi # all family 14h cores are primary - mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B - _RDMSR - bt $APIC_BSC, %eax # Is this the BSC? - jc node_core_f14_exit # Br if yes - inc %si # Set core to 1 -node_core_f14_exit: -.endm - - - -/***************************************************************************** -** Family 15h MACROS -*****************************************************************************/ -/***************************************************************************** -* -* AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -* -* Set any family specific controls needed to enable the use of -* cache as general storage before main memory is available. -* -* Inputs: -* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -* Outputs: -* none -* -* Family 15h requirements (BKDG #42301 section 2.3.3): -* * Paging must be disabled. -* * MSRC001_0015[INVD_WBINVD]=0 -* * MSRC001_1020[DisSS]=1 -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -* * MSRC001_1022[DisHwPf]=1 -* * No INVD or WBINVD, no exceptions, page faults or interrupts -*****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F15 - LOCAL fam15_enable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $0x06, %al # Is this family 15h? - jnz fam15_enable_stack_hook_exit # Br if no - - bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set - jc fam15_skipClearingBit4 - mov $HWCR, %ecx # MSR C001_0015 - _RDMSR - btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion - _WRMSR - -fam15_skipClearingBit4: - mov $LS_CFG, %ecx # MSR:C001_1020 - _RDMSR - bts $DIS_SS, %eax # Turn on Streaming store functionality disabled bit - _WRMSR - - inc %ecx #IC_CFG # MSR:C001_1021 - _RDMSR - bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative IC-TLB reloads bit - _WRMSR - - inc %ecx #DC_CFG # MSR:C001_1022 - _RDMSR - bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DC-TLB reloads bit - bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit - _WRMSR - - mov $CU_CFG3, %ecx # MSR:C001_102B - _RDMSR - btr $(COMBINE_CR0_CD - 32), %edx # Clear CombineCr0Cd bit - _WRMSR - -fam15_enable_stack_hook_exit: -.endm - - -/***************************************************************************** -* -* AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -* -* Return any family specific controls to their 'standard' -* settings for using cache with main memory. -* -* Inputs: -* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -* Outputs: -* none -* -* Family 15h requirements: -* * INVD or WBINVD -* * MSRC001_0015[INVD_WBINVD]=1 -* * MSRC001_1020[DisSS]=0 -* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -* * MSRC001_1022[DIS_HW_PF]=0 -*****************************************************************************/ -.macro AMD_DISABLE_STACK_FAMILY_HOOK_F15 - LOCAL fam15_disable_stack_hook_exit - - AMD_CPUID $CPUID_MODEL - mov %eax, %ebx # Save revision info to EBX - shr $20, %eax # AL = cpu extended family - cmp $0x06, %al # Is this family 15h? - jnz fam15_disable_stack_hook_exit # Br if no - - mov $LS_CFG, %ecx # MSR:C001_1020 - #.if (ebx != 00600F00h) ; Is this rev A0? - cmp $0x00600F00, %ebx - jz 0f - _RDMSR - btr $DIS_SS, %eax # Turn on Streaming store functionality - _WRMSR - #.endif - 0: # End workaround for errata 495 and 496 - - inc %ecx #IC_CFG # MSR:C001_1021 - _RDMSR - btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads - _WRMSR - - inc %ecx #DC_CFG # MSR:C001_1022 - _RDMSR - btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads - #.if (ebx != 00600F00h) # Is this rev A0? - cmp $0x00600F00, %ebx - jz 0f - btr $DIS_HW_PF, %eax # Turn on hardware prefetches - #.endif # End workaround for erratum 498 - 0: - _WRMSR - #-------------------------------------------------------------------------- - # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - bt $FLAG_IS_PRIMARY, %esi - #.if (carry?) # Only clear cache from primary core - jnc 0f - mov $HWCR, %ecx # MSR:C001_0015h - _RDMSR - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion - _WRMSR - invd # Clear the cache tag RAMs - bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD - _WRMSR - #.endif # end - 0: - - #-------------------------------------------------------------------------- - # End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - #-------------------------------------------------------------------------- - - mov $CU_CFG3, %ecx # MSR:C001_102B - _RDMSR - bts $(COMBINE_CR0_CD - 32), %edx # Set CombineCr0Cd bit - _WRMSR - -fam15_disable_stack_hook_exit: -.endm - - -/***************************************************************************** -* -* GET_NODE_ID_CORE_ID_F15 Macro - Stackless -* -* Read family specific values to determine the node and core -* numbers for the core executing this code. -* -* Inputs: -* none -* Outputs: -* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -*****************************************************************************/ -.macro GET_NODE_ID_CORE_ID_F15 - - LOCAL node_core_f15_exit - LOCAL node_core_f15_AP - LOCAL node_core_f15_shared - - cmp $-1, %si # Has node/core already been discovered? - jnz node_core_f15_exit # Br if yes - - AMD_CPUID $CPUID_MODEL - shr $20, %eax # AL = cpu extended family - cmp $06, %al # Is this family 15h? - jnz node_core_f15_exit # Br if no - - xor %esi, %esi # Assume BSC, clear local flags - mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B - _RDMSR - bt $APIC_BSC, %eax # Is this the BSC? - jnc node_core_f15_AP # Br if no - - # This is the BSP. - # Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register - mov $0x0CF8, %dx - out %eax, %dx - add $4, %dx - in %dx, %eax - btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0 - out %eax, %dx - jmp node_core_f15_shared # - -node_core_f15_AP: - # - # This is an AP. Routing tables have been enabled by the HT Init process. - # Also, the MailBox register was set by the BSP during early init - # The Mailbox register content is formatted as follows: - # UINT32 Node:4; // The node id of Core's node. - # UINT32 Socket:4; // The socket of this Core's node. - # UINT32 Module:2; // The internal module number for Core's node. - # UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1. - # UINT32 :20; // Reserved - # - mov $0x0C0000408, %ecx # Read the family 15h mailbox - _RDMSR # MC4_MISC1[63:32] - mov %dx, %si # SI = raw mailbox contents (will extract node# from this) - shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId] - mov %bx, %di # DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID $AMD_CPUID_APIC # - shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core# - inc %cl # CL = Number of enabled cores in the socket - mov %cx, %bx - - mov $NB_CFG, %ecx - _RDMSR # EDX has InitApicIdCpuIdLo bit - - mov %bh, %cl # CL = APIC ID size - mov $1, %al # Convert APIC ID size to an AND mask - shl %cl, %al # AL = 2^APIC ID size - dec %al # AL = mask for relative core number - xor %ah, %ah # AX = mask for relative core number - bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1? - #.if (!carry?) # Br if yes - jc 0f - mov $8, %ch # Calculate core number shift count - sub %cl, %ch # CH = core shift count - mov %ch, %cl - shr %cl, %di # Right justify core number - #.endif - 0: - and %ax, %di # DI = socket-relative core number - - mov %si, %cx # CX = raw mailbox value - shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and $3, %cl # Isolate ModuleType - xor %bh, %bh # BX = Number of enabled cores in the socket - shr %cl, %bx # BX = Number of enabled cores per node - xor %dx, %dx # Clear upper word for div - mov %di, %ax # AX = socket-relative core number - div %bx # DX = node-relative core number - movzx %si, %eax # Prepare return value - and $0x000F, %ax # AX = node number - shl $8,%ax # [15:8]=node# - mov %dl, %al # [7:0]=core# (relative to node) - mov %eax, %esi # ESI = node-relative core number - - # - # determine if this core shares MTRRs - # -node_core_f15_shared: - mov $0x8000C580, %eax # Compute Unit Status - mov %si, %bx - shl $3, %bh # Move node# to PCI Dev# field - add %bh, %ah # Adjust for node number - mov $0x0CF8, %dx - out %eax, %dx - add $4, %dx - in %dx, %eax # [3:0]=Enabled# [19:16]=DualCore - - # BL is MyCore# - mov $0x06, %cx # Use CH as 'first of pair' core# - #.while (cl > 0) - jmp 0f - 8: - bt $0, %eax # Is pair enabled? - #.if (carry?) # - jnc 1f - mov $0x01, %bh # flag core as primary - bt $16, %eax # Is there a 2nd in the pair? - #.if (carry?) # - jnc 4f - #.break .if (ch == bl) # Does 1st match MyCore#? - cmp %bl, %ch - je 9f - inc %ch - xor %bh, %bh # flag core as NOT primary - #.break .if (ch == bl) # Does 2nd match MyCore#? - cmp %bl, %ch - je 9f - jmp 2f - #.else # No 2nd core - 4: - #.break .if (ch == bl) # Does 1st match MyCore#? - cmp %bl, %ch - je 9f - #.endif - 2: - inc %ch - #.endif - 1: - shr $1, %eax - dec %cl - #.endw - 0: - #.if (cl == 0) - cmp $0x0, %cl - ja 8b - 9: - or %cl, %cl - jne 1f - #Error - core# didn't match Compute Unit Status content - bts $FLAG_UNKNOWN_FAMILY, %esi - bts $FLAG_IS_PRIMARY, %esi # Set Is_Primary for unknowns - #.endif - 1: - #.if (bh != 0) # Check state of primary for the matched core - or %bh, %bh - je 2f - bts $FLAG_IS_PRIMARY, %esi # Set shared flag into return value - #.endif - 2: - -node_core_f15_exit: - -.endm - -/***************************************************************************** -* AMD_ENABLE_STACK: Setup a stack -* -* In: -* No inputs -* -* Out: -* SS:ESP - Our new private stack location -* -* EAX = AGESA_STATUS -* -* ECX = Stack size in bytes -* -* Requirements: -* * This routine presently is limited to a max of 64 processor cores -* Destroyed: -* EBX, EDX, EDI, ESI, EBP, DS, ES -* -* Description: -* Fixed MTRR address allocation to cores: -* The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K. -* There is a max of 1 BSP, 7 core0s and 56 other cores. -* Although each core has it's own cache storage, they share the address space. Each core must -* be assigned a private and unique address space for its stack. To support legacy systems, -* the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved -* for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.) -* -* 80000h 40000h 00000h -* +----------+----------+----------+----------+----------+----------+----------+----------+ -* 64K | | | | | | | | | 64K ea -* ea +----------+----------+----------+----------+----------+----------+----------+----------+ -* | MTRR 0000_0250 MTRRfix64K_00000 | -* +----------+----------+----------+----------+----------+----------+----------+----------+ -* | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node -* |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core -* +----------+----------+----------+----------+----------+----------+----------+----------+ -* -* C0000h B0000h A0000h 90000h 80000h -* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -*16K | | | | | | | | | | | | | | | | | -* ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -* | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 | -* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -* | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node -* | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core -* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -* -* E0000h D0000h C0000h -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea -* ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 | -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<| -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* -* 100000h F0000h E0000h -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 | -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -* | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | -* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -*****************************************************************************/ -.macro AMD_ENABLE_STACK - -# These are local labels. Declared so linker doesn't cause 'redefined label' errors - LOCAL SetupStack - LOCAL Real16bMode - LOCAL Protected32Mode - LOCAL ClearTheStack - -# Note that SS:ESP will be default stack. Note that this stack -# routine will not be used after memory has been initialized. Because -# of its limited lifetime, it will not conflict with typical PCI devices. - - # get node id and core id of current executing core - GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node) - # Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established - - # determine if stack is already enabled. We are using the DefType MSR for this determination. - # It is =0 after reset; CAR setup sets it to enable the MTRRs - mov %cr0, %eax - test $CR0_MASK, %eax # Is cache disabled? (CD & NW bits) - jnz SetupStack # Jump if yes - mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF - _RDMSR - test $MSR_MASK, %eax # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN) - jz SetupStack # Jump if no - or $FLAG_STACK_REENTRY, %esi # Bit25, indicate stack has already been initialized - -SetupStack: - # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM - mov %esi, %ebx # Get my Node/Core info - xor %bl, %bl - shl $3, %bh # Isolate my node#, match alignment for PCI Dev# - mov $0x8000C144, %eax # D18F1x44:DRAM Base/Limit# N is Base, N+4 is Limit - add %bh, %ah - mov %eax, %ebx # Save PCI address for Base/Limit pair - - mov $0x0CF8, %dx - out %eax, %dx - add $4, %dx - xor %eax, %eax # Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB) - out %eax, %dx # DRAM Limit = node0, no interleave - - mov %ebx, %eax - sub $4, %eax # Now point to the Base register - mov $0x0CF8, %dx - out %eax, %dx - add $4, %dx - mov $0x00000003, %eax # Set the read and write enable bits - out %eax, %dx # DRAM Base = 0x0000, R/W - - AMD_ENABLE_STACK_FAMILY_HOOK - - # Init CPU MSRs for our init routines - mov $MTRR_SYS_CFG, %ecx # SYS_CFG - _RDMSR - bts $MTRR_FIX_DRAM_MOD_EN, %eax # Turn on modification enable bit - _WRMSR - - mov %esi, %eax - bt $FLAG_STACK_REENTRY, %eax # Is this a 2nd entry? - #.if (!carry?) # On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP - jc 0f - bt $FLAG_IS_PRIMARY, %eax # Is this core the primary in a compute unit? - #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset - # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores - # Clear all variable and Fixed MTRRs for non-shared cores - jnc 0f - mov $AMD_MTRR_VARIABLE_BASE0, %ecx - xor %eax, %eax - xor %edx, %edx - #.while (cl != 10h) # Variable MTRRphysBase[n] and MTRRphysMask[n] - jmp 1f - 2: - _WRMSR - inc %cl - #.endw - 1: - cmp $0x10, %cl - jne 2b - mov $AMD_MTRR_FIX64k_00000, %cx # MSR:0000_0250 - _WRMSR - mov $AMD_MTRR_FIX16k_80000, %cx # MSR:0000_0258 - _WRMSR - mov $AMD_MTRR_FIX16k_A0000, %cx # MSR:0000_0259 - _WRMSR - mov $AMD_MTRR_FIX4k_C0000, %cx # Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000 - #.while (cl != 70h) - jmp 3f - 4: - _WRMSR - inc %cl - #.endw - 3: - cmp $0x70, %cl - jne 4b - # Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init. - # - not strictly needed since the FixedMTRRs take presedence. - mov $(16 * 1024 * 1024), %eax - mov $TOP_MEM, %ecx # MSR:C001_001A - _WRMSR - #.endif # End Is_Primary - #.endif # End Stack_ReEntry - 0: - # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores - xor %eax, %eax - xor %edx, %edx - mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019 - #.while (cl != 1Ah) - jmp 1f - 2: - _WRMSR - inc %cl - #.endw - 1: - cmp $0x1A, %cl - jne 2b - mov $TOP_MEM2, %ecx # MSR:C001_001D - _WRMSR - - # setup MTRRs for stacks - # A speculative read can be generated by a speculative fetch mis-aligned in a code zone - # or due to a data zone being interpreted as code. When a speculative read occurs outside a - # controlled region (intentionally used by software), it could cause an unwanted cache eviction. - # To prevent speculative reads from causing an eviction, the unused cache ranges are set - # to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs. - # Note: some core stack regions will share an MTRR since the control granularity is much - # larger than the allocated stack zone. The allocation algorithm must account for this 'extra' - # space covered by the MTRR when parseling out cache space for the various uses. In some cases - # this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c - # - # Outcome of this block is that: (Note the MTRR map at the top of the file) - # ebp - start address of stack block - # ebx - [31:16] - MTRR MSR address - # - [15:8] - slot# in MTRR register - # - [7:0] - block size in #4K blocks - # review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node) - # - - mov %si, %ax # Load node, core - #.if (al == 0) # Is a core 0? - or %al, %al - jne 1f - #.if (ah == 0) # Is Node 0? (BSP) - or %ah, %ah - jne 2f - # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx - mov $BSP_STACK_BASE_ADDR, %ebp - jmp 0f - #.else # node 1 to 7, core0 - 2: - # Is a Core0 of secondary node, assign 16K stacks - mov $AMD_MTRR_FIX16k_80000, %bx - shl $16, %ebx # - mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE >> 12), %bl - mov %ah, %al # Base = (Node# * Size)# - mul %bl # - movzx %ax, %eax # - shl $12, %eax # Expand back to full byte count (* 4K) - add $CORE0_STACK_BASE_ADDR, %eax - mov %eax, %ebp - #.endif - jmp 0f - #.else #core 1 thru core 7 - 1: - # Is core 1-7 of any node, assign 4K stacks - mov $8, %al # CoreIndex = ( (Node# * 8) ... - mul %ah # - mov %si, %bx # - add %bl, %al # ... + Core#)# - - mov $AMD_MTRR_FIX64k_00000, %bx - shl $16, %ebx # - mov %al, %bh # Slot# = (CoreIndex / 16) + 4# - shr $4, %bh # - add $4, %bh # - mov $(CORE1_STACK_SIZE >> 12), %bl - - mul %bl # Base = ( (CoreIndex * Size) ... - movzx %ax, %eax # - shl $12, %eax # Expand back to full byte count (* 4K) - add $CORE1_STACK_BASE_ADDR, %eax # ... + Base_Addr)# - mov %eax, %ebp - #.endif - 0: - - # Now set the MTRR. Add this to already existing settings (don't clear any MTRR) - mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot - mov %bh, %cl # ShiftCount = ((slot# ... - and $0x03, %cl # ... % 4) ... - shl $0x03, %cl # ... * 8)# - shl %cl, %edi # Cache type is now in correct position - ror $16, %ebx # Get the MTRR address - movzx %bx, %ecx # - rol $16, %ebx # Put slot# & size back in BX - _RDMSR # Read-modify-write the MSR - #.if (bh < 4) # Is value in lower or upper half of MSR? - cmp $4, %bh - jae 1f - or %edi, %eax # - jmp 0f - #.else - 1: # - or %edi, %edx # - #.endif # - 0: - _WRMSR # - - # Enable MTRR defaults as UC type - mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF - _RDMSR # Read-modify-write the MSR - bts $MTRR_DEF_TYPE_EN, %eax # MtrrDefTypeEn - bts $MTRR_DEF_TYPE_FIX_EN, %eax # MtrrDefTypeFixEn - _WRMSR - - # Close the modification window on the Fixed MTRRs - mov $MTRR_SYS_CFG, %ecx # MSR:0C001_0010 - _RDMSR - bts $MTRR_FIX_DRAM_EN, %eax # MtrrFixDramEn - bts $MTRR_VAR_DRAM_EN, %eax # variable MTRR enable bit - btr $MTRR_FIX_DRAM_MOD_EN, %eax # Turn off modification enable bit - _WRMSR - - # Enable caching in CR0 - mov %cr0, %eax # Enable WT/WB cache - btr $CR0_PG, %eax # Make sure paging is disabled - btr $CR0_CD, %eax # Clear CR0 NW and CD - btr $CR0_NW, %eax - mov %eax, %cr0 - - # Use the Stack Base & size to calculate SS and ESP values - # review: - # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - # ebp - start address of stack block - # ebx - [31:16] - MTRR MSR address - # - [15:8] - slot# in MTRR register - # - [7:0] - block size in #4K blocks - # - mov %ebp, %esp # Initialize the stack pointer - mov %esp, %edi # Copy the stack start to edi - movzx %bl, %bx - movzx %bx, %ebx # Clear upper ebx, don't need MSR addr anymore - shl $12, %ebx # Make size full byte count (* 4K) - add %ebx, %esp # Set the Stack Pointer as full linear address - sub $4, %esp - # - # review: - # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - # edi - 32b start address of stack block - # ebx - size of stack block - # esp - 32b linear stack pointer - # - - # Determine mode for SS base; - mov %cr0, %ecx # Check for 32-bit protect mode - bt $CR0_PE, %ecx # - #.if (!carry?) # PE=0 means real mode - jc Protected32Mode - mov %cs, %cx # PE=1 - cmp $0x0D000, %cx # Check for CS - jb Protected32Mode # If CS < D000, it is a selector instead of a segment - # alter SS:ESP for 16b Real Mode: -Real16bMode: - mov %edi, %eax - shr $4, %eax # Create a Real Mode segment for ss, ds, es - mov %ax, %ss - mov %ax, %ds - mov %ax, %es - shl $4, %eax - sub %eax, %edi # Adjust the clearing pointer for Seg:Offset mode - mov %ebx, %esp # Make SP an offset from SS - sub $4, %esp # - # .endif # endif - # #else - # Default is to use Protected 32b Mode - #.endif - ; -Protected32Mode: - # - # Clear The Stack - # Now that we have set the location and the MTRRs, initialize the cache by - # reading then writing to zero all of the stack area. - # review: - # ss - Stack base - # esp - stack pointer - # ebx - size of stack block - # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - # edi - address of start of stack block - # - -ClearTheStack: # Stack base is in SS, stack pointer is in ESP - shr $2, %ebx # ebx = stack block size in dwords - mov %bx, %cx # - # Check our flags - Don't clear an existing stack - #.if ( !(esi & 0FF000000h)) # Check our flags - test $(1 << FLAG_STACK_REENTRY), %esi - jne 1f - cld - mov %edi, %esi - rep lodsl (%esi) # Pre-load the range - xor %eax, %eax - mov %bx, %cx - mov %edi, %esi # Preserve base for push on stack - rep stosl (%edi) # Clear the range - movl $0x0ABCDDCBA, (%esp) # Put marker in top stack dword - shl $2, %ebx # Put stack size and base - push %ebx # in top of stack - push %esi - - mov %ebx, %ecx # Return size of stack in bytes - xor %eax, %eax # eax = 0 : no error return code - jmp 0f - #.else - 1: - movzx %cx, %ecx - shl $2, %ecx # Return size of stack in bytes - mov %esi, %eax - shr $24, %eax # Keep the flags as part of the error report - or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up) - #.endif - 0: -.endm - -/***************************************************************************** -* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine -* should only be executed on the BSP -* -* In: -* none -* -* Out: -* none -* -* Preserved: -* ESP -* Destroyed: -* EAX, EBX, ECX, EDX, EDI, ESI -*****************************************************************************/ -.macro AMD_DISABLE_STACK - - # get node/core/flags of current executing core - GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) - - # Turn on modification enable bit - mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010 - _RDMSR - bts $MTRR_FIX_DRAM_MOD_EN, %eax # Enable modifications - _WRMSR - - # Set lower 640K MTRRs for Write-Back memory caching - mov $AMD_MTRR_FIX64k_00000, %ecx - mov $0x1E1E1E1E, %eax - mov %eax, %edx - _WRMSR # 0 - 512K = WB Mem - mov $AMD_MTRR_FIX16k_80000, %ecx - _WRMSR # 512K - 640K = WB Mem - - # Turn off modification enable bit - mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010 - _RDMSR - btr $MTRR_FIX_DRAM_MOD_EN, %eax # Disable modification - _WRMSR - - AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations - -.endm diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.c b/src/vendorcode/amd/cimx/sb700/ACPILIB.c deleted file mode 100644 index ebeb828ea9..0000000000 --- a/src/vendorcode/amd/cimx/sb700/ACPILIB.c +++ /dev/null @@ -1,120 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - -/*++ - -Routine Description: - - Locate ACPI table - -Arguments: - - Signature - table signature - -Returns: - - pointer to ACPI table - ---*/ -void* ACPI_LocateTable( - UINT32 Signature -) -{ - UINT32 i; - UINT32 *RsdPtr = (UINT32 *)0xe0000; - UINT32 *Rsdt = NULL; - DESCRIPTION_HEADER *CurrentTable; - do{ -// if (*RsdPtr == ' DSR' && *(RsdPtr+1) == ' RTP'){ - if ((*RsdPtr == Int32FromChar ('R', 'S', 'D', ' ')) && (*(RsdPtr+1) == Int32FromChar ('R', 'T', 'P', ' '))){ - Rsdt = (UINT32 *)(uintptr_t)((RSDP *)RsdPtr)->RsdtAddress; - break; - } - RsdPtr+=4; - }while (RsdPtr <= (UINT32*)0xffff0); - if(Rsdt != NULL && ACPI_GetTableChecksum(Rsdt)==0){ - for (i = 0;i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof(DESCRIPTION_HEADER))/4;i++){ - CurrentTable = (DESCRIPTION_HEADER*)(uintptr_t)*(UINT32*)((UINT8*)Rsdt + sizeof(DESCRIPTION_HEADER) + i*4); - if (CurrentTable->Signature == Signature) return CurrentTable; - } - } - return NULL; -} - -/*++ - -Routine Description: - - Update table checksum - -Arguments: - - TablePtr - table pointer - -Returns: - - none - ---*/ -void ACPI_SetTableChecksum( - void* TablePtr -) -{ - UINT8 Checksum = 0; - ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0; - Checksum = ACPI_GetTableChecksum(TablePtr); - ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0x100 - Checksum; -} - -/*++ - -Routine Description: - - Get table checksum - -Arguments: - - TablePtr - table pointer - -Returns: - - none - ---*/ -UINT8 ACPI_GetTableChecksum( - void* TablePtr -) -{ - return GetByteSum(TablePtr,((DESCRIPTION_HEADER*)TablePtr)->Length); -} - diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.h b/src/vendorcode/amd/cimx/sb700/ACPILIB.h deleted file mode 100644 index 5f2734fafd..0000000000 --- a/src/vendorcode/amd/cimx/sb700/ACPILIB.h +++ /dev/null @@ -1,61 +0,0 @@ -/*;******************************************************************************** -; -; Copyright (C) 2012 Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;*********************************************************************************/ - -#ifndef _AMD_ACPILIB_H_ -#define _AMD_ACPILIB_H_ - -typedef struct _RSDP{ - UINT64 Signature; - UINT8 Checksum; - UINT8 OEMID[6]; - UINT8 Revision; - UINT32 RsdtAddress; - UINT32 Length; - UINT64 XsdtAddress; - UINT8 ExtendedChecksum; - UINT8 Reserved[3]; -}RSDP; - -typedef struct _DESCRIPTION_HEADER{ - UINT32 Signature; - UINT32 Length; - UINT8 Revision; - UINT8 Checksum; - UINT8 OEMID[6]; - UINT8 OEMTableID[8]; - UINT32 OEMRevision; - UINT32 CreatorID; - UINT32 CreatorRevision; -}DESCRIPTION_HEADER; - -void* ACPI_LocateTable(UINT32 Signature); -void ACPI_SetTableChecksum(void* TablePtr); -UINT8 ACPI_GetTableChecksum(void* TablePtr); - -#endif //ifndef _AMD_ACPILIB_H_ diff --git a/src/vendorcode/amd/cimx/sb700/AMDLIB.c b/src/vendorcode/amd/cimx/sb700/AMDLIB.c deleted file mode 100644 index b9fea1a41c..0000000000 --- a/src/vendorcode/amd/cimx/sb700/AMDLIB.c +++ /dev/null @@ -1,434 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - - -#include "Platform.h" - -VOID -ReadIO ( - IN UINT16 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - OpFlag = OpFlag & 0x7f; - switch ( OpFlag ) { - case AccWidthUint8: - *(UINT8*)Value = ReadIo8 (Address); - break; - case AccWidthUint16: - *(UINT16*)Value = ReadIo16 (Address); - break; - case AccWidthUint32: - *(UINT32*)Value = ReadIo32 (Address); - break; - default: - break; - } -} - -VOID -WriteIO ( - IN UINT16 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - OpFlag = OpFlag & 0x7f; - switch ( OpFlag ) { - case AccWidthUint8: - WriteIo8 (Address, *(UINT8*)Value); - break; - case AccWidthUint16: - WriteIo16 (Address, *(UINT16*)Value); - break; - case AccWidthUint32: - WriteIo32 (Address, *(UINT32*)Value); - break; - default: - break; - } -} - -VOID -RWIO ( - IN UINT16 Address, - IN UINT8 OpFlag, - IN UINT32 Mask, - IN UINT32 Data - ) -{ - UINT32 Result; - ReadIO (Address, OpFlag, &Result); - Result = (Result & Mask) | Data; - WriteIO (Address, OpFlag, &Result); -} - - -VOID -ReadPCI ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - OpFlag = OpFlag & 0x7f; - - if ( (UINT16)Address < 0xff ) { - //Normal Config Access - UINT32 AddrCf8; - AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC); - WriteIO (0xCf8, AccWidthUint32, &AddrCf8); - ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); - } -} - -VOID -WritePCI ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - OpFlag = OpFlag & 0x7f; - if ( (UINT16)Address < 0xff ) { - //Normal Config Access - UINT32 AddrCf8; - AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC); - WriteIO (0xCf8, AccWidthUint32, &AddrCf8); - WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); - } -} - -VOID -RWPCI ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN UINT32 Mask, - IN UINT32 Data - ) -{ - UINT32 Result; - Result = 0; - OpFlag = OpFlag & 0x7f; - ReadPCI (Address, OpFlag, &Result); - Result = (Result & Mask) | Data; - WritePCI (Address, OpFlag, &Result); -} - -void -ReadIndexPCI32 ( -UINT32 PciAddress, -UINT32 IndexAddress, -void* Value -) -{ - WritePCI(PciAddress,AccWidthUint32,&IndexAddress); - ReadPCI(PciAddress+4,AccWidthUint32,Value); -} - -void -WriteIndexPCI32 ( -UINT32 PciAddress, -UINT32 IndexAddress, -UINT8 OpFlag, -void* Value -) -{ - - WritePCI(PciAddress,AccWidthUint32 | (OpFlag & 0x80),&IndexAddress); - WritePCI(PciAddress+4,AccWidthUint32 | (OpFlag & 0x80) ,Value); -} - -void -RWIndexPCI32 ( -UINT32 PciAddress, -UINT32 IndexAddress, -UINT8 OpFlag, -UINT32 Mask, -UINT32 Data -) -{ - UINT32 Result; - ReadIndexPCI32(PciAddress,IndexAddress,&Result); - Result = (Result & Mask)| Data; - WriteIndexPCI32(PciAddress,IndexAddress,(OpFlag & 0x80),&Result); - -} - -void -ReadMEM ( -UINTN Address, -UINT8 OpFlag, -void* Value -) -{ - OpFlag = OpFlag & 0x7f; - switch (OpFlag){ - case AccWidthUint8 : *((UINT8*)Value)=*((UINT8*)Address);break; - case AccWidthUint16: *((UINT16*)Value)=*((UINT16*)Address);break; - case AccWidthUint32: *((UINT32*)Value)=*((UINT32*)Address);break; - } -} - -void -WriteMEM ( -UINTN Address, -UINT8 OpFlag, -void* Value -) -{ - OpFlag = OpFlag & 0x7f; - switch (OpFlag){ - case AccWidthUint8 : *((UINT8*)Address)=*((UINT8*)Value);break; - case AccWidthUint16: *((UINT16*)Address)=*((UINT16*)Value);break; - case AccWidthUint32: *((UINT32*)Address)=*((UINT32*)Value);break; - } -} - -void -RWMEM ( -UINTN Address, -UINT8 OpFlag, -UINT32 Mask, -UINT32 Data -) -{ - UINT32 Result; - ReadMEM(Address,OpFlag,&Result); - Result = (Result & Mask)| Data; - WriteMEM(Address,OpFlag,&Result); -} - - -void -RWMSR( -UINT32 Address, -UINT64 Mask, -UINT64 Value -) -{ - MsrWrite(Address,(MsrRead(Address)& Mask)|Value); -} - -UINT32 -IsFamily10() -{ - CPUID_DATA Cpuid; - CpuidRead(0x1,(CPUID_DATA *)&Cpuid); - - return Cpuid.REG_EAX & 0xff00000; -} - - -UINT8 GetNumberOfCpuCores(void) -{ - UINT8 Result=1; - Result=ReadNumberOfCpuCores(); - return Result; -} - - -void -Stall( -UINT32 uSec -) -{ - UINT16 timerAddr; - UINT32 startTime, elapsedTime; - ReadPMIO(SB_PMIO_REG24, AccWidthUint16, &timerAddr); - - if (timerAddr ==0){ - uSec = uSec/2; - while (uSec!=0){ - ReadIO(0x80,AccWidthUint8,(UINT8 *)(&startTime)); - uSec--; - } - } - else{ - ReadIO(timerAddr, AccWidthUint32,&startTime); - while (1){ - ReadIO(timerAddr, AccWidthUint32,&elapsedTime); - if (elapsedTime < startTime) - elapsedTime = elapsedTime+0xFFFFFFFF-startTime; - else - elapsedTime = elapsedTime-startTime; - if ((elapsedTime*28/100)>uSec) - break; - } - } -} - - -void -Reset( -) -{ - RWIO(0xcf9,AccWidthUint8,0x0,0x06); -} - - -CIM_STATUS -RWSMBUSBlock( -UINT8 Controller, -UINT8 Address, -UINT8 Offset, -UINT8 BufferSize, -UINT8* BufferPrt -) -{ - UINT16 SmbusPort; - UINT8 i; - UINT8 Status; - ReadPCI(PCI_ADDRESS(0,0x14,0,Controller?0x58:0x10),AccWidthUint16,&SmbusPort); - SmbusPort &= 0xfffe; - RWIO(SmbusPort + 0,AccWidthUint8,0x0,0xff); - RWIO(SmbusPort + 4,AccWidthUint8,0x0,Address); - RWIO(SmbusPort + 3,AccWidthUint8,0x0,Offset); - RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x14); - RWIO(SmbusPort + 5,AccWidthUint8,0x0,BufferSize); - if(!(Address & 0x1)){ - for (i = 0 ;i < BufferSize;i++){ - WriteIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]); - } - } - RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x54); - do{ - ReadIO(SmbusPort + 0,AccWidthUint8,&Status); - if (Status & 0x1C) return CIM_ERROR; - if (Status & 0x02) break; - }while(!(Status & 0x1)); - - do{ - ReadIO(SmbusPort + 0,AccWidthUint8,&Status); - }while(Status & 0x1); - - if(Address & 0x1){ - for (i = 0 ;i < BufferSize;i++){ - ReadIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]); - } - } - return CIM_SUCCESS; -} - - - -void outPort80(UINT32 pcode) -{ - WriteIO(0x80, AccWidthUint8, &pcode); - return; -} - - -UINT8 -GetByteSum( - void* pData, - UINT32 Length -) -{ - UINT32 i; - UINT8 Checksum = 0; - for (i = 0;i < Length;i++){ - Checksum += *((UINT8*)pData+i); - } - return Checksum; -} - - -UINT32 -readAlink( - UINT32 Index -){ - UINT32 Data; - WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); - ReadIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data); - //Clear Index - Index=0; - WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); - return Data; -} - - -void -writeAlink( - UINT32 Index, - UINT32 Data -){ - WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); - WriteIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data); - //Clear Index - Index=0; - WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); - -} - - -/** - * - * IsServer - Determine if southbridge type is SP5100 (server) or SB7x0 (non-server) - * - * A SP5100 is determined when both following two items are true: - * 1) Revision >= A14; - * 2) A server north bridge chipset is detected; - * - * A list of server north bridge chipset: - * - * Family DeviceID - * ---------------------- - * SR5690 0x5A10 - * SR5670 0x5A12 - * SR5650 0x5A13 - * - */ -UINT8 -IsServer (void){ - UINT16 DevID; - - if (getRevisionID () < SB700_A14) { - return 0; - } - ReadPCI ((NB_BDF << 16) + 2, AccWidthUint16, &DevID); - return ((DevID == 0x5a10) || (DevID == 0x5a12) || (DevID == 0x5a13))? 1: 0; -} - -/** - * - * IsLS2Mode - Determine if LS2 mode is enabled or not in northbridge. - * - */ -UINT8 -IsLs2Mode (void) -{ - UINT32 HT3LinkTraining0; - - ReadPCI ((NB_BDF << 16) + 0xAC, AccWidthUint32, &HT3LinkTraining0); - return ( HT3LinkTraining0 & 0x100 )? 1: 0; -} diff --git a/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c b/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c deleted file mode 100644 index bf4f06aad5..0000000000 --- a/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c +++ /dev/null @@ -1,276 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - - -void -ReadPMIO ( -UINT8 Address, -UINT8 OpFlag, -void* Value -) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - if (OpFlag == 0x02) OpFlag = 0x03; - for (i=0;i<=OpFlag;i++){ - WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 - Address++; - ReadIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7 - } -} - - -void -WritePMIO ( -UINT8 Address, -UINT8 OpFlag, -void* Value -) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - if (OpFlag == 0x02) OpFlag = 0x03; - for (i=0;i<=OpFlag;i++){ - WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 - Address++; - WriteIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7 - } -} - - -void -RWPMIO ( -UINT8 Address, -UINT8 OpFlag, -UINT32 AndMask, -UINT32 OrMask -) -{ - UINT32 Result; - - OpFlag = OpFlag & 0x7f; - ReadPMIO(Address,OpFlag,&Result); - Result = (Result & AndMask)| OrMask; - WritePMIO(Address,OpFlag,&Result); -} - - -void -ReadPMIO2 ( -UINT8 Address, -UINT8 OpFlag, -void* Value -) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - if (OpFlag == 0x02) OpFlag = 0x03; - for (i=0;i<=OpFlag;i++){ - WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 - Address++; - ReadIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1 - } -} - - -void -WritePMIO2 ( -UINT8 Address, -UINT8 OpFlag, -void* Value -) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - if (OpFlag == 0x02) OpFlag = 0x03; - for (i=0;i<=OpFlag;i++){ - WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 - Address++; - WriteIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1 - } -} - - -void -RWPMIO2 ( -UINT8 Address, -UINT8 OpFlag, -UINT32 AndMask, -UINT32 OrMask -) -{ - UINT32 Result; - - OpFlag = OpFlag & 0x7f; - ReadPMIO2(Address,OpFlag,&Result); - Result = (Result & AndMask)| OrMask; - WritePMIO2(Address,OpFlag,&Result); -} - - -void -EnterEcConfig() -{ - UINT16 dwEcIndexPort; - - ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); - dwEcIndexPort &= ~(UINT16)(BIT0); - RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0x5A); -} - -void -ExitEcConfig() -{ - UINT16 dwEcIndexPort; - - ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); - dwEcIndexPort &= ~(UINT16)(BIT0); - RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0xA5); -} - - -void -ReadEC8 ( -UINT8 Address, -UINT8* Value -) -{ - UINT16 dwEcIndexPort; - - ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); - dwEcIndexPort &= ~(UINT16)(BIT0); - WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 - ReadIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7 -} - - -void -WriteEC8 ( -UINT8 Address, -UINT8* Value -) -{ - UINT16 dwEcIndexPort; - - ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); - dwEcIndexPort &= ~(UINT16)(BIT0); - WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 - WriteIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7 -} - - -void -RWEC8 ( -UINT8 Address, -UINT8 AndMask, -UINT8 OrMask -) -{ - UINT8 Result; - ReadEC8(Address,&Result); - Result = (Result & AndMask)| OrMask; - WriteEC8(Address, &Result); -} - - -void -programPciByteTable ( -REG8MASK* pPciByteTable, -UINT16 dwTableSize -) -{ - UINT8 i, dbBusNo, dbDevFnNo; - UINT32 ddBDFR; - - dbBusNo = pPciByteTable->bRegIndex; - dbDevFnNo = pPciByteTable->bANDMask; - pPciByteTable++; - for (i = 1; i < dwTableSize; i++){ - if ( (pPciByteTable->bRegIndex==0xFF) && (pPciByteTable->bANDMask==0xFF) && (pPciByteTable->bORMask==0xFF) ){ - pPciByteTable++; - dbBusNo = pPciByteTable->bRegIndex; - dbDevFnNo = pPciByteTable->bANDMask; - } - else{ - ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ; - TRACE((DMSG_SB_TRACE, "PFA=%X AND=%X, OR=%X\n", ddBDFR, pPciByteTable->bANDMask, pPciByteTable->bORMask)); - RWPCI(ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask); - pPciByteTable++; - } - } -} - - -void -programPmioByteTable ( -REG8MASK* pPmioByteTable, -UINT16 dwTableSize -) -{ - UINT8 i; - for (i = 0; i < dwTableSize; i++){ - TRACE((DMSG_SB_TRACE, "PMIO Reg = %X AndMask = %X OrMask = %X\n",pPmioByteTable->bRegIndex,pPmioByteTable->bANDMask, pPmioByteTable->bORMask)); - RWPMIO(pPmioByteTable->bRegIndex, AccWidthUint8 , pPmioByteTable->bANDMask, pPmioByteTable->bORMask); - pPmioByteTable++; - } -} - - -UINT8 -getClockMode ( -void -) -{ - UINT8 dbTemp=0; - - RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); - ReadPMIO(SB_PMIO_REGB0, AccWidthUint8, &dbTemp); - return(dbTemp&BIT4); -} - - -UINT16 -readStrapStatus ( -void -) -{ - UINT16 dwTemp=0; - - RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); - ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTemp); - return(dwTemp); -} diff --git a/src/vendorcode/amd/cimx/sb700/AZALIA.c b/src/vendorcode/amd/cimx/sb700/AZALIA.c deleted file mode 100644 index 8659c1dd8b..0000000000 --- a/src/vendorcode/amd/cimx/sb700/AZALIA.c +++ /dev/null @@ -1,304 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - - -#include "Platform.h" - -void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum); -void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0); - -//Pin Config for ALC880, ALC882 and ALC883: -CODECENTRY AzaliaCodecAlc882Table[] = { - {0x14, 0x01014010}, - {0x15, 0x01011012}, - {0x16, 0x01016011}, - {0x17, 0x01012014}, - {0x18, 0x01A19030}, - {0x19, 0x411111F0}, - {0x1a, 0x01813080}, - {0x1b, 0x411111F0}, - {0x1C, 0x411111F0}, - {0x1d, 0x411111F0}, - {0x1e, 0x01441150}, - {0x1f, 0x01C46160}, - {0xff, 0xffffffff} -}; - - -//Pin Config for ALC262 -CODECENTRY AzaliaCodecAlc262Table[] = { - {0x14, 0x01014010}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, -// {0x17, 0x01012014}, - {0x18, 0x01A19830}, - {0x19, 0x02A19C40}, - {0x1a, 0x01813031}, - {0x1b, 0x02014C20}, - {0x1c, 0x411111F0}, - {0x1d, 0x411111F0}, - {0x1e, 0x0144111E}, - {0x1f, 0x01C46150}, - {0xff, 0xffffffff} -}; - -//Pin Config for ALC0861: -CODECENTRY AzaliaCodecAlc861Table[] = { - {0x01, 0x8086C601}, - {0x0B, 0x01014110}, - {0x0C, 0x01813140}, - {0x0D, 0x01A19941}, - {0x0E, 0x411111F0}, - {0x0F, 0x02214420}, - {0x10, 0x02A1994E}, - {0x11, 0x99330142}, - {0x12, 0x01451130}, - {0x1F, 0x411111F0}, - {0x20, 0x411111F0}, - {0x23, 0x411111F0}, - {0xff, 0xffffffff} -}; - -//Pin Config for ADI1984: -CODECENTRY AzaliaCodecAd1984Table[] = { - {0x11, 0x0221401F}, - {0x12, 0x90170110}, - {0x13, 0x511301F0}, - {0x14, 0x02A15020}, - {0x15, 0x50A301F0}, - {0x16, 0x593301F0}, - {0x17, 0x55A601F0}, - {0x18, 0x55A601F0}, - {0x1A, 0x91F311F0}, - {0x1B, 0x014511A0}, - {0x1C, 0x599301F0}, - {0xff, 0xffffffff} -}; - - -CODECENTRY FrontPanelAzaliaCodecTableList[] = { - {0x19, 0x02A19040}, - {0x1b, 0x02214020}, - {0xff, 0xffffffff} -}; - - -CODECTBLLIST azaliaCodecTableList[] = { - {0x010ec0880, &AzaliaCodecAlc882Table[0]}, - {0x010ec0882, &AzaliaCodecAlc882Table[0]}, - {0x010ec0883, &AzaliaCodecAlc882Table[0]}, - {0x010ec0885, &AzaliaCodecAlc882Table[0]}, - {0x010ec0262, &AzaliaCodecAlc262Table[0]}, - {0x010ec0861, &AzaliaCodecAlc861Table[0]}, - {0x011d41984, &AzaliaCodecAd1984Table[0]}, - {(UINT32)0x0FFFFFFFF, (CODECENTRY*)0xFFFFFFFF} -}; - - -/*------------------------------------------------------------------------------- -; Procedure: azaliaInitAfterPciEnum -; -; Description: This routine detects Azalia and, if present, initializes Azalia -; This routine is called from atiSbAfterPciInit -; -; -; Exit: None -; -; Modified: None -; -;----------------------------------------------------------------------------- -*/ -void azaliaInitAfterPciEnum (AMDSBCFG* pConfig){ - UINT8 i, dbEnableAzalia=0, dbPinRouting, dbChannelNum=0, dbTempVariable = 0; - UINT16 dwTempVariable = 0; - UINT32 ddBAR0, ddTempVariable = 0; - - if (pConfig->AzaliaController == 1) return; - - if (pConfig->AzaliaController != 1){ - RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT1, BIT1); - ReadPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); - - if (ddBAR0 != 0){ //Keep the flag as disabled if BAR is 0 or all "F"s. - if (ddBAR0 != 0xFFFFFFFF){ - ddBAR0 &= ~(0x03FFF); - dbEnableAzalia = 1; - TRACE((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n")); - } - } - } - - if (dbEnableAzalia){ //if Azalia is enabled - //Get SDIN Configuration - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF8, AccWidthUint32 | S3_SAVE, 0, ddTempVariable); - ddTempVariable |= (pConfig->AzaliaSdin3 << 6); - ddTempVariable |= (pConfig->AzaliaSdin2 << 4); - ddTempVariable |= (pConfig->AzaliaSdin1 << 2); - ddTempVariable |= pConfig->AzaliaSdin0; - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, (ddTempVariable & 0xFF)); - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0); - - i=11; - do{ - ReadMEM( ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - dbTempVariable |= BIT0; - WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - Stall(1000); - ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - i--; - } while ( (!(dbTempVariable & BIT0)) && (i > 0) ); - - if (i==0){ - TRACE((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n")); - return; - } - - Stall(1000); - ReadMEM( ddBAR0+SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable); - if (dwTempVariable & 0x0F){ - TRACE((DMSG_SB_TRACE, "CIMxSB - Atleast One Azalia CODEC found \n")); - //atleast one azalia codec found - ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8, &dbPinRouting); - do{ - if ( ( !(dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) - configureAzaliaPinCmd(pConfig, ddBAR0, dbChannelNum); - dbPinRouting >>= 2; - dbChannelNum++; - } while (dbChannelNum != 4); - } - else{ - TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n")); - //No Azalia codec found - if (pConfig->AzaliaController != 2) - dbEnableAzalia = 0; //set flag to disable Azalia - } - } - - if (dbEnableAzalia){ - //redo clear reset - do{ - dwTempVariable = 0; - WriteMEM( ddBAR0+SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable); - ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - dbTempVariable &= ~(UINT8)(BIT0); - WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - } while (dbTempVariable & BIT0); - - if (pConfig->AzaliaSnoop == 1) - RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); - } - else{ - //disable Azalia controller - RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0); - RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0); - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55); - } -} - - -void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum){ - UINT32 ddTempVariable, ddChannelNum; - CODECTBLLIST* ptempAzaliaOemCodecTablePtr; - CODECENTRY* tempAzaliaCodecEntryPtr; - - if ((pConfig->AzaliaPinCfg) != 1) - return; - - ddChannelNum = dbChannelNum << 28; - ddTempVariable = 0xF0000; - ddTempVariable |= ddChannelNum; - WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable); - Stall(60); - ReadMEM(ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable); - - if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) ) - ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR(&azaliaCodecTableList[0]); - else - ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->pAzaliaOemCodecTablePtr; - - TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %x \n", (UINT32)ptempAzaliaOemCodecTablePtr)); - - while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){ - if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable) - break; - else - ++ptempAzaliaOemCodecTablePtr; - } - - if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){ - TRACE((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n")); - tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr; - TRACE((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %x \n", (UINT32)tempAzaliaCodecEntryPtr)); - - if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) ) - tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(tempAzaliaCodecEntryPtr); - - configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); - if (pConfig->AzaliaFrontPanel != 1){ - if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ){ - if ( ((pConfig->pAzaliaOemFpCodecTableptr) == NULL) || ((pConfig->pAzaliaOemFpCodecTableptr) == 0xFFFFFFFF)) - tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(&FrontPanelAzaliaCodecTableList[0]); - else - tempAzaliaCodecEntryPtr = (CODECENTRY*)(uintptr_t) pConfig->pAzaliaOemFpCodecTableptr; - configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); - } - } - } -} - - -void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0){ - UINT8 dbtemp1,dbtemp2, i; - UINT32 ddtemp=0,ddtemp2=0; - - while ((tempAzaliaCodecEntryPtr->Nid) != 0xFF){ - dbtemp1=0x20; - if ((tempAzaliaCodecEntryPtr->Nid) == 0x1) - dbtemp1=0x24; - ddtemp = tempAzaliaCodecEntryPtr->Nid; - ddtemp &= 0xff; - ddtemp <<= 20; - ddtemp |= ddChannelNum; - ddtemp |= (0x700 << 8); - for(i=4; i>0; i--){ - do{ - ReadMEM(ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2); - } while (ddtemp2 & BIT0); - dbtemp2 = ( (tempAzaliaCodecEntryPtr->Byte40) >> ((4-i) * 8 ) ) & 0xff; - ddtemp = (ddtemp & 0xFFFF0000)+ ((dbtemp1 - i) << 8) + dbtemp2; - WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp); - Stall(60); - } - ++tempAzaliaCodecEntryPtr; - } -} - diff --git a/src/vendorcode/amd/cimx/sb700/DEBUG.c b/src/vendorcode/amd/cimx/sb700/DEBUG.c deleted file mode 100644 index f40682eac9..0000000000 --- a/src/vendorcode/amd/cimx/sb700/DEBUG.c +++ /dev/null @@ -1,169 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - -#define COM_BASE_ADDRESS 0x3f8 -#define DIVISOR 115200 -#define LF 0x0a -#define CR 0x0d - - -#ifdef CIM_DEBUG - #ifndef CIM_DEBUG_LEVEL - #define CIM_DEBUG_LEVEL 0xf -#endif - -void -TraceCode( UINT32 Level, UINT32 Code){ - - if (!(Level & CIM_DEBUG_LEVEL)){ - return; - } -#if CIM_DEBUG & 1 - if (Code != 0xFF){ - WriteIO(0x80,AccWidthUint8,&Code); - } -#endif - -} - - -void -TraceDebug( UINT32 Level, CHAR8 *Format, ...){ - CHAR8 temp[16]; - va_list ArgList; - - if (!(Level & CIM_DEBUG_LEVEL)){ - return; - } - -#if CIM_DEBUG & 2 - ArgList = va_start(ArgList,Format); - Format= (CHAR8*) FIXUP_PTR(Format); - while (1){ - if (*Format == 0) break; - if (*Format == '%'){ - int Radix = 0; - if(*(Format+1)=='s'||*(Format+1)=='S'){ - SendStringPort((CHAR8*) FIXUP_PTR(va_arg(ArgList,CHAR8*))); - Format+=2; - continue; - } - - if(*(Format+1)=='d'||*(Format+1)=='D'){ - Radix = 10; - } - if(*(Format+1)=='x'||*(Format+1)=='X'){ - Radix = 16; - } - if (Radix){ - ItoA(va_arg(ArgList,int),Radix,temp); - SendStringPort(temp); - Format+=2; - continue; - } - } - SendBytePort(*Format); - if(*(Format)==0x0a) SendBytePort(0x0d); - Format++; - } - va_end(ArgList); -#endif -} - - -void -ItoA( UINT32 Value, int Radix, char* pstr) -{ - char* tsptr = pstr; - char* rsptr = pstr; - char ch1,ch2; - unsigned int Reminder; -//Create String - do{ - Reminder = Value%Radix; - Value = Value/Radix; - if (Reminder<0xa) *tsptr=Reminder+'0'; - else *tsptr=Reminder-0xa+'a'; - tsptr++; - } while(Value); -//Reverse String - *tsptr = 0; - tsptr--; - while(tsptr>rsptr){ - ch1 = *tsptr; - ch2 = *rsptr; - *rsptr = ch1; - *tsptr = ch2; - tsptr--; - rsptr++; - } -} - -void -InitSerialOut(){ - UINT8 Data; - UINT16 Divisor; - Data = 0x87; - WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data); - Divisor = 115200 / DIVISOR; - Data = Divisor & 0xFF; - WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data); - Data = Divisor >> 8; - WriteIO(COM_BASE_ADDRESS + 0x01,AccWidthUint8, &Data); - Data = 0x07; - WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data); -} - - -void -SendStringPort(char* pstr){ - - while (*pstr!=0){ - SendBytePort(*pstr); - pstr++; - } -} - -void -SendBytePort(UINT8 Data) -{ - int Count = 80; - UINT8 Status; - do { - ReadIO((COM_BASE_ADDRESS + 0x05),AccWidthUint8, &Status); - if(Status == 0xff) break; - // Loop port is ready - } while ( (Status & 0x20) == 0 && (--Count) != 0); - WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data); -} -#endif diff --git a/src/vendorcode/amd/cimx/sb700/DISPATCHER.c b/src/vendorcode/amd/cimx/sb700/DISPATCHER.c deleted file mode 100644 index 920539d571..0000000000 --- a/src/vendorcode/amd/cimx/sb700/DISPATCHER.c +++ /dev/null @@ -1,154 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - -void DispatcherEntry(void *pConfig){ - -//#if CIM_DEBUG -// InitSerialOut(); -//#endif - - TRACE((DMSG_SB_TRACE, "CIM - SB700 Entry\n")); - - saveConfigPointer(pConfig); - - if (((STDCFG*)pConfig)->Func == SB_POWERON_INIT) - sbPowerOnInit((AMDSBCFG*)pConfig); - - if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_INIT) - sbBeforePciInit((AMDSBCFG*)pConfig); - if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_INIT) - sbAfterPciInit((AMDSBCFG*)pConfig); - if (((STDCFG*)pConfig)->Func == SB_LATE_POST_INIT) - sbLatePost((AMDSBCFG*)pConfig); - if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT) - sbBeforePciRestoreInit((AMDSBCFG*)pConfig); - if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT) - sbAfterPciRestoreInit((AMDSBCFG*)pConfig); - if (((STDCFG*)pConfig)->Func == SB_SMM_SERVICE) - { - // sbSmmService((AMDSBCFG*)pConfig); - } - if (((STDCFG*)pConfig)->Func == SB_SMM_ACPION) - sbSmmAcpiOn((AMDSBCFG*)pConfig); - - TRACE((DMSG_SB_TRACE, "CIMx - SB Exit\n")); -} - -UINT32 GetPciebase(){ - AMDSBCFG* Result; - Result = getConfigPointer(); - return Result->StdHeader.pPcieBase; -} - - -void saveConfigPointer(AMDSBCFG* pConfig){ - UINT8 dbReg, i; - UINT32 ddValue; - - ddValue = ((UINTN) pConfig); - dbReg = SB_ECMOS_REG08; - - for (i=0; i<=3; i++){ - WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg); - WriteIO(SB_IOMAP_REG73, AccWidthUint8, (UINT8 *)&ddValue); - ddValue >>= 8; - dbReg++; - } -} - - -AMDSBCFG* getConfigPointer(){ - UINT8 dbReg, dbValue, i; - UINTN ddValue=0; - - dbReg = SB_ECMOS_REG08; - for (i=0; i<=3; i++){ - WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg); - ReadIO(SB_IOMAP_REG73, AccWidthUint8, &dbValue); - ddValue |= (dbValue<<(i*8)); - dbReg++; - } - return( (AMDSBCFG*) ddValue); -} - -/** - * AmdSbDispatcher - Dispatch Southbridge function - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -AGESA_STATUS -AmdSbDispatcher ( - IN VOID *pConfig - ) -{ - AGESA_STATUS Status = AGESA_SUCCESS; - - saveConfigPointer (pConfig); - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) { - sbPowerOnInit ((AMDSBCFG*) pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) { - sbBeforePciInit ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) { - sbAfterPciInit ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) { - sbLatePost ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) { - sbBeforePciRestoreInit ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) { - sbAfterPciRestoreInit ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) { - sbSmmService ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) { - sbSmmAcpiOn ((AMDSBCFG*)pConfig); - } - - return Status; -} diff --git a/src/vendorcode/amd/cimx/sb700/EC.c b/src/vendorcode/amd/cimx/sb700/EC.c deleted file mode 100644 index 3ad15e1146..0000000000 --- a/src/vendorcode/amd/cimx/sb700/EC.c +++ /dev/null @@ -1,132 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - -#ifndef NO_EC_SUPPORT - -REG8MASK sb710PorInitPciTable[] = { - // SMBUS Device(Bus 0, Dev 20, Func 0) - {0x00, SMBUS_BUS_DEV_FUN, 0}, - {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible. - {SB_SMBUS_REG38, (UINT8)~(BIT7+BIT5+BIT4+BIT3+BIT2+BIT1), 0x0D}, - {SB_SMBUS_REG38+1, ~(UINT8)(BIT2+BIT1), BIT3 }, - {SB_SMBUS_REGE1, 0xFF, BIT1}, - {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible. - {0xFF, 0xFF, 0xFF}, - - // LPC Device(Bus 0, Dev 20, Func 3) - {0x00, LPC_BUS_DEV_FUN, 0}, - {SB_LPC_REGB8+3, ~(UINT8)(BIT1), BIT7+BIT2}, - {0xFF, 0xFF, 0xFF}, -}; - -REG8MASK sb710PorPmioInitTbl[]={ - // index andmask ormask - {SB_PMIO_REGD7, 0xFF, BIT5}, - {SB_PMIO_REGBB, 0xFF, BIT5}, -}; - - -void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG* pConfig){ - UINT8 dbVar0, i=0; - - if (!(isEcPresent())) - return; //return if EC is not enabled - - for(i=0;i<0xFF;i++){ - ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG40, AccWidthUint8 | S3_SAVE, &dbVar0); - if ( dbVar0 & BIT7 ) break; //break if EC is ready - Stall(500); //wait for EC to become ready - } - - if (getRevisionID() >= SB700_A14){ - programPciByteTable( (REG8MASK*)FIXUP_PTR(&sb710PorInitPciTable[0]), sizeof(sb710PorInitPciTable)/sizeof(REG8MASK) ); - programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sb710PorPmioInitTbl[0]), (sizeof(sb710PorPmioInitTbl)/sizeof(REG8MASK)) ); - } - - RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA), AccWidthUint8 | S3_SAVE, 0xFF, BIT2); //Enable SPI Prefetch in EC - - //Enable config mode - EnterEcConfig(); - - //Do settings for mailbox - logical device 0x09 - RWEC8(0x07, 0x00, 0x09); //switch to device 9 (Mailbox) - RWEC8(0x60, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr >> 8)); //set MSB of Mailbox port - RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr & 0xFF)); //set LSB of Mailbox port - RWEC8(0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1 - - if (pBuildOptPtr->EcKbd == CIMX_OPTION_ENABLED){ - RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3), AccWidthUint8 | S3_SAVE, 0xFF, BIT7+BIT3); - //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC - RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT3+BIT2+BIT1+BIT0); - //Disable LPC Decoding of port 60/64 - RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 0); - //Enable logical device 0x07 (Keyboard controller) - RWEC8(0x07, 0x00, 0x07); - RWEC8(0x30, 0x00, 0x01); - } - - if (pBuildOptPtr->EcChannel0 == CIMX_OPTION_ENABLED){ - //Logical device 0x08 - RWEC8(0x07, 0x00, 0x08); - RWEC8(0x60, 0x00, 0x00); - RWEC8(0x61, 0x00, 0x62); - RWEC8(0x30, 0x00, 0x01); //;Enable Device 8 - } - //Logical device 0x05 - RWEC8(0x07, 0x00, 0x05); //Select logical device 05, IR controller - RWEC8(0x60, 0x00, pBuildOptPtr->EcLdn5MailBoxAddr >> 8); - RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn5MailBoxAddr & 0xFF)); - RWEC8(0x70, 0xF0, (pBuildOptPtr->EcLdn5Irq)); //Set IRQ to 05h - RWEC8(0x30, 0x00, 0x01); //Enable logical device 5, IR controller - - RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT4); //Enable EC(IMC) to generate SMI to BIOS - ExitEcConfig(); -} - - -void ecInitBeforePciEnum(AMDSBCFG* pConfig){ - if (!(isEcPresent())) - return; //return if EC is not enabled -} - - -void ecInitLatePost(AMDSBCFG* pConfig){ - if (!(isEcPresent()) ) - return; //return if EC is not enabled - //Enable config mode - EnterEcConfig(); //Enable config mode - //for future use - ExitEcConfig(); -} - -#endif diff --git a/src/vendorcode/amd/cimx/sb700/FLASH.c b/src/vendorcode/amd/cimx/sb700/FLASH.c deleted file mode 100644 index 0d842453cc..0000000000 --- a/src/vendorcode/amd/cimx/sb700/FLASH.c +++ /dev/null @@ -1,58 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - -void fcInitBeforePciEnum(AMDSBCFG* pConfig){ - - TRACE((DMSG_SB_TRACE, "Entering PreInit Flash \n")); - RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT1, 00); - - //Enable IDE and disable flash - //Enable IDE and disable flash - RWPMIO(SB_PMIO_REG59, AccWidthUint8, ~(UINT32)(BIT1+BIT0), 0); - RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT3), BIT0); //Configure GPIO3 as IDE_RST# and release RST - if (pConfig->IdeController){ - //Disabling IDE controller - RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0); - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); - } - else{ - //Enable IDE controller - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0); - } - - //RPR 8.2 Enable IDE Data bus DD7 Pull down Resistor if IDE is enabled and FC is disabled - RWPMIO2(SB_PMIO2_REGE5, AccWidthUint8, 0xFF, BIT2); - //Slowdown the clock to FC if FC is not enabled, this is a power savings feature - RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT4), BIT4); - RWPMIO(SB_PMIO_REGBC, AccWidthUint8, 0xC0, 0); -} diff --git a/src/vendorcode/amd/cimx/sb700/LEGACY.c b/src/vendorcode/amd/cimx/sb700/LEGACY.c deleted file mode 100644 index c904d595d2..0000000000 --- a/src/vendorcode/amd/cimx/sb700/LEGACY.c +++ /dev/null @@ -1,38 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - -UINT32 GetFixUp(){ - STDCFG* Result; - Result = (STDCFG*) getConfigPointer(); - return Result->pImageBase; -} diff --git a/src/vendorcode/amd/cimx/sb700/Makefile.inc b/src/vendorcode/amd/cimx/sb700/Makefile.inc deleted file mode 100644 index b96fbb8b1a..0000000000 --- a/src/vendorcode/amd/cimx/sb700/Makefile.inc +++ /dev/null @@ -1,67 +0,0 @@ -#***************************************************************************** -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of Advanced Micro Devices, Inc. nor the names of -# its contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -#***************************************************************************** - -CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/cimx/sb700 -CPPFLAGS_x86_32 += -I$(src)/vendorcode/amd/cimx/sb700 - -CPPFLAGS_x86_64 += -I$(src)/southbridge/amd/cimx/sb700 -CPPFLAGS_x86_64 += -I$(src)/vendorcode/amd/cimx/sb700 - -romstage-y += ACPILIB.c -romstage-y += AMDLIB.c -romstage-y += AMDSBLIB.c -romstage-y += AZALIA.c -romstage-y += DEBUG.c -romstage-y += DISPATCHER.c -romstage-y += EC.c -romstage-y += FLASH.c -romstage-y += SATA.c -romstage-y += SBCMN.c -romstage-y += SBCMNLIB.c -romstage-y += SBMAIN.c -romstage-y += SBPort.c -romstage-y += SMM.c -romstage-y += USB.c - -ramstage-y += ACPILIB.c -ramstage-y += AMDLIB.c -ramstage-y += AMDSBLIB.c -ramstage-y += AZALIA.c -ramstage-y += DEBUG.c -ramstage-y += DISPATCHER.c -ramstage-y += EC.c -ramstage-y += FLASH.c -ramstage-y += SATA.c -ramstage-y += SBCMN.c -ramstage-y += SBCMNLIB.c -ramstage-y += SBMAIN.c -ramstage-y += SBPort.c -ramstage-y += SMM.c -ramstage-y += USB.c -ramstage-y += LEGACY.c diff --git a/src/vendorcode/amd/cimx/sb700/OEM.h b/src/vendorcode/amd/cimx/sb700/OEM.h deleted file mode 100644 index 51a829694d..0000000000 --- a/src/vendorcode/amd/cimx/sb700/OEM.h +++ /dev/null @@ -1,91 +0,0 @@ -/*;******************************************************************************** -; -; Copyright (C) 2012 Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;*********************************************************************************/ -#ifndef _AMD_SB_CIMx_OEM_H_ -#define _AMD_SB_CIMx_OEM_H_ - -#ifndef BIOS_SIZE - #define BIOS_SIZE 0x04 //04 - 1MB -#endif -#ifndef LEGACY_FREE - #define LEGACY_FREE 0x00 -#endif - -/** - * PCIEX_BASE_ADDRESS - Define PCIE base address - * - * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 - */ -#ifdef MOVE_PCIEBAR_TO_F0000000 - #define PCIEX_BASE_ADDRESS 0xF7000000 -#else - #define PCIEX_BASE_ADDRESS 0xE0000000 -#endif - - -#define SMBUS0_BASE_ADDRESS 0xB00 -#define SMBUS1_BASE_ADDRESS 0xB20 -#define SIO_PME_BASE_ADDRESS 0xE00 -#define SPI_BASE_ADDRESS 0xFEC10000 - -#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address -#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address - -#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; -#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; -#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; -#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; -#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; -#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; -#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; - -#define EC_LDN5_MAILBOX_ADDRESS 0x550 -#define EC_LDN5_IRQ 0x05 -#define EC_LDN9_MAILBOX_ADDRESS 0x3E - -#define SATA_IDE_MODE_SSID 0x43901002 -#define SATA_RAID_MODE_SSID 0x43921002 -#define SATA_RAID5_MODE_SSID 0x43931002 -#define SATA_AHCI_SSID 0x43911002 -#define OHCI0_SSID 0x43971002 -#define OHCI1_SSID 0x43981002 -#define EHCI0_SSID 0x43961002 -#define OHCI2_SSID 0x43971002 -#define OHCI3_SSID 0x43981002 -#define EHCI1_SSID 0x43961002 -#define OHCI4_SSID 0x43991002 - -#define SMBUS_SSID 0x43851002 -#define IDE_SSID 0x439C1002 -#define AZALIA_SSID 0x43831002 -#define LPC_SSID 0x439D1002 -#define P2P_SSID 0x43841002 - -#define RESERVED_VALUE 0x00 - -#endif //ifndef _AMD_SB_CIMx_OEM_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SATA.c b/src/vendorcode/amd/cimx/sb700/SATA.c deleted file mode 100644 index d5032397fe..0000000000 --- a/src/vendorcode/amd/cimx/sb700/SATA.c +++ /dev/null @@ -1,453 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - -//Table for class code of SATA Controller in different modes -UINT32 sataIfCodeTable[] = { - 0x01018f00, //sata class ID of IDE - 0x01040000, //sata class ID of RAID - 0x01060100, //sata class ID of AHCI - 0x01018a00, //sata class ID of Legacy IDE - 0x01018f00, //sata class ID of IDE to AHCI mode - 0x01060100, //sata class ID of AMD-AHCI mode - 0x01018f00 //sata class ID of IDE to AMD-AHCI mode -}; - -//Table for device id of SATA Controller in different modes -UINT16 sataDeviceIDTable[] = { - 0x4390, //sata device ID of IDE - 0x4392, //sata device ID of RAID - 0x4391, //sata class ID of AHCI - 0x4390, //sata device ID of Legacy IDE - 0x4390, //sata device ID of IDE->AHCI mode - 0x4394, //sata device ID for AMD-AHCI mode - 0x4390 //sata device ID of IDE->AMDAHCI mode -}; - - -void sataInitBeforePciEnum(AMDSBCFG* pConfig){ - UINT32 ddValue, *tempptr; - UINT16 *pDeviceIdptr, dwDeviceId; - UINT8 dbValue, dbOrMask, dbAndMask; - - - dbAndMask=0; - dbOrMask=0; - // Enable/Disable Combined mode & do primary/secondary selections, enable/disable - if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) dbAndMask= BIT3; //Clear BIT3 - if (pConfig->SataIdeCombMdPriSecOpt == 1) dbOrMask = BIT4; //Set BIT4 - if (pConfig->SataSmbus == 0) dbOrMask = BIT1; - - RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(dbAndMask), dbOrMask); - - if (pConfig->SataController == 0){ - // SATA Controller Disabled & set Power Saving mode to disabled - RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT1); - return; - } - - restrictSataCapabilities(pConfig); - - // Get the appropriate class code from the table and write it to PCI register 08h-0Bh - // Set the appropriate SATA class based on the input parameters - dbValue=pConfig->SataClass; - tempptr= (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]); - ddValue=tempptr[dbValue]; - - // BIT0: Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h, bit 0 - // BIT4:disable fast boot - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT4+BIT0); - - // Write the class code to SATA PCI register 08h-0Bh - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue); - - if (pConfig->SataClass == LEGACY_IDE_MODE) //SATA = Legacy IDE - //Set PATA controller to native mode - RWPCI(((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); - - //Change the appropriate device id - if (pConfig->SataClass == AMD_AHCI_MODE) { - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xff, BIT0); - } - pDeviceIdptr= (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]); - - ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId); - if ( !((dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) && (pConfig->SataClass == RAID_MODE)) ){ - //if not (SB750 & RAID mode), then program the device id - dwDeviceId=pDeviceIdptr[dbValue]; - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId); - } - - if (pConfig->AcpiS1Supported) - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA PM & MSI capability - else - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG60+1), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA MSI capability - - if (getRevisionID() >= SB700_A13){ - //Enable test/enhancement mode for A13 - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+3), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 00); - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT24+BIT21), 0xBF80); - } - - if (getRevisionID() >= SB700_A14){ - //Fix for TT SB01352 - LED Stays On When ODD Attached To Slave Port In IDE Mode - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint8 | S3_SAVE, 0xFF, BIT6); - } - - // Disable write access to PCI header - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); - - // RPR 6.5 SATA PHY Programming Sequence - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint16 | S3_SAVE, 0x00, 0x2C00); - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG88, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG8C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG90, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG9C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA0, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA4, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA8, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); - - CallBackToOEM(SATA_PHY_PROGRAMMING, NULL, pConfig); -} - -void sataInitAfterPciEnum(AMDSBCFG* pConfig){ - UINT32 ddAndMask=0, ddOrMask=0, ddBar5=0; - UINT8 dbVar, dbPortNum; - - if (pConfig->SataController == 0) return; //return if SATA controller is disabled. - - //Enable write access to pci header, pm capabilities - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0); - - //Disable AHCI enhancement function (RPR 7.2) - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0xFF, BIT7); - - restrictSataCapabilities(pConfig); - - ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); - - if ( (ddBar5 == 0) || (ddBar5 == -1) ) { - //assign temporary BAR5 - if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1)) - ddBar5 = 0xFEC01000; - else - ddBar5=pConfig->TempMMIO; - - WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); - } - - ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); - RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable - - ddBar5 &= 0xFFFFFC00; //Clear Bits 9:0 - if (!pConfig->SataPortMultCap) - ddAndMask |= BIT12; - if (!pConfig->SataAggrLinkPmCap) - ddAndMask |= BIT11; - if (pConfig->SataSscPscCap) - ddOrMask |= BIT1; - - RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask); - - - //Clear HPCP and ESP by default - RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFC0FC0, 0); - - if (pConfig->SataHpcpButNonESP !=0) { - RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFFFFC0, pConfig->SataHpcpButNonESP); - } - - // SATA ESP port setting - // These config bits are set for SATA driver to identify which ports are external SATA ports and need to - // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will - // not enable power management(HIPM & DIPM) for these ports. - if (pConfig->SataEspPort !=0) { - RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT20); - RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0); - RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT17+BIT16+BIT15+BIT14+BIT13+BIT12),(pConfig->SataEspPort << 12)); - } - - if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) ) - RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50+2), AccWidthUint8, ~(UINT32)(BIT3+BIT2+BIT1), BIT2+BIT1); //set MSI to 8 messages - - if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) && ((pConfig->SataIdeCombinedMode) == CIMX_OPTION_DISABLED) ){ - RWMEM((ddBar5 + SB_SATA_BAR5_REG00),AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), BIT2+BIT0); - RWMEM((ddBar5 + SB_SATA_BAR5_REG0C),AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); - } - - for (dbPortNum=0;dbPortNum<=5;dbPortNum++){ - if (pConfig->SataPortMode & (1 << dbPortNum)){ - //downgrade to GEN1 - RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10); - RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01); - Stall(1000); - RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00); - } - } - - //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround. - if ( !(pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) && ((pConfig->SataClass) != AMD_AHCI_MODE) ) ) - sataDriveDetection(pConfig, ddBar5); - - if ( (pConfig->SataPhyWorkaround==1) || ( (pConfig->SataPhyWorkaround==0) && (getRevisionID() < SB700_A13)) ) - sataPhyWorkaround(pConfig, ddBar5); - - // Set the handshake bit for IDE driver to detect the disabled IDE channel correctly. - // Set IDE PCI Config 0x63 [3] if primary channel disabled, [4] if secondary channel disabled. - if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) - RWPCI( ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG63), AccWidthUint8 , 0xF9, (0x02 << (pConfig->SataIdeCombMdPriSecOpt)) ); - - WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); - - //Disable write access to pci header, pm capabilities - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); -} - - -void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){ - UINT32 ddVar0; - UINT8 dbPortNum, dbVar0; - UINT32 dwIoBase, dwVar0; - - TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n")); - TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5)); - - if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ){ - for (dbPortNum=0;dbPortNum<4;dbPortNum++){ - ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0); - if ( ( ddVar0 & 0x0F ) == 0x03){ - if ( dbPortNum & BIT0) - //this port belongs to secondary channel - ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase); - else - //this port belongs to primary channel - ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase); - - //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them - if (pConfig->SataClass == LEGACY_IDE_MODE) - dwIoBase = ( (0x170) | ( (~((dbPortNum & BIT0) << 7)) & 0x80 ) ); - - if ( dbPortNum & BIT1) - //this port is slave - dbVar0=0xB0; - else - //this port is master - dbVar0=0xA0; - dwIoBase &= 0xFFF8; - WriteIO(dwIoBase+6, AccWidthUint8, &dbVar0); - - //Wait in loop for 30s for the drive to become ready - for (dwVar0=0;dwVar0<3000;dwVar0++){ - ReadIO(dwIoBase+7, AccWidthUint8, &dbVar0); - if ( (dbVar0 & 0x88) == 0) - break; - Stall(10000); - } - } //end of if ( ( ddVar0 & 0x0F ) == 0x03) - } //for (dbPortNum=0;dbPortNum<4;dbPortNum++) - } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ) -} - - -//This patch is to workaround the SATA PHY logic hardware issue in the SB700. -//Internally this workaround is called as 7NewA -void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5){ - - UINT8 dbPortNum, dbVar0; - - if (pConfig->Gen1DeviceShutdownDuringPhyWrknd == 0x01){ - for (dbPortNum=0;dbPortNum<=5;dbPortNum++){ - ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint8, &dbVar0); - if ( (dbVar0 & 0xF0) == 0x10){ - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, 0xFF, (01 << dbPortNum)); - } - - } - } - - RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), BIT4+BIT3);//set PMIO_D0[4:3] = 11b // this is to tell SATA PHY to use the internal 100MHz clock - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint8 | S3_SAVE, 0x00, 0x40);// set SATA PCI_CFG 0x86[7:0] = 0x40 //after the reset is done, perform this to turn on the diff clock path into SATA PHY - Stall(2000);// Wait for 2ms - RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), 00);//13. set PMIO_D0[4:3] = 00b - Stall(20000);// Wait 20ms - forceOOB(ddBar5);// Force OOB - - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, ~(0x03F), 00); -} - - -void forceOOB(UINT32 ddBar5){ - UINT8 dbPortNum; - for (dbPortNum=0;dbPortNum<=5;dbPortNum++) - RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01); - Stall(2000); - for (dbPortNum=0;dbPortNum<=5;dbPortNum++) - RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00); - Stall(2000);// Wait for 2ms -} - -/*++ - -Routine Description: - - SATA Late Configuration - - if the mode is selected as IDE->AHCI - { 1. Set class ID to AHCI - 2. Enable AHCI interrupt - } - -Arguments: - - pConfig - SBconfiguration - -Returns: - - void - ---*/ -void sataInitLatePost(AMDSBCFG* pConfig){ - UINT32 ddBar5; - UINT8 dbVar; - - //Return immediately is sata controller is not enabled - if (pConfig->SataController == 0) return; - - restrictSataCapabilities(pConfig); - - //Get BAR5 value - ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); - - //Assign temporary BAR if is not already assigned - if ( (ddBar5 == 0) || (ddBar5 == -1) ){ - //assign temporary BAR5 - if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1)) - ddBar5 = 0xFEC01000; - else - ddBar5=pConfig->TempMMIO; - WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); - } - - ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); - //Enable memory and io access - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03); - //Enable write access to pci header, pm capabilities - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); - - shutdownUnconnectedSataPortClock(pConfig, ddBar5); - - if ( (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){ - //program the AHCI class code - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100); - //Set interrupt enable bit - RWMEM((ddBar5 + 0x04),AccWidthUint8,~(UINT32)0,BIT1); - //program the correct device id for AHCI mode - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391); - - if (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) - //program the correct device id for AMD-AHCI mode - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xFF, BIT0); - } - - //Disable write access to pci header and pm capabilities - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); - //Clear error status - RWMEM((ddBar5 + SB_SATA_BAR5_REG130),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); - RWMEM((ddBar5 + SB_SATA_BAR5_REG1B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); - RWMEM((ddBar5 + SB_SATA_BAR5_REG230),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); - RWMEM((ddBar5 + SB_SATA_BAR5_REG2B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); - //Restore memory and io access bits - WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar ); -} - - -void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5){ - UINT8 dbPortNum, dbPortSataStatus, NumOfPorts=0; - UINT8 UnusedPortBitMap; - UINT8 SataType; - UINT8 ClockOffEnabled ; - - UnusedPortBitMap = 0; - - // First scan for all unused SATA ports - for (dbPortNum = 5; dbPortNum <= 5; dbPortNum--) { - ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus); - if ((!(dbPortSataStatus & 0x01)) && (!((pConfig->SataEspPort) & (1 << dbPortNum)))) { - UnusedPortBitMap |= (1 << dbPortNum); - } - } - - // Decide if we need to shutdown the clock for all unused ports - SataType = pConfig->SataClass; - ClockOffEnabled = (pConfig->SataClkAutoOff && ((SataType == NATIVE_IDE_MODE) || (SataType == LEGACY_IDE_MODE) || \ - (SataType == IDE_TO_AHCI_MODE) || (SataType == IDE_TO_AMD_AHCI_MODE))) || \ - (pConfig->SataClkAutoOffAhciMode && ((SataType == AHCI_MODE) || (SataType == AMD_AHCI_MODE))); - - if (ClockOffEnabled) { - //Shutdown the clock for the port and do the necessary port reporting changes. - TRACE((DMSG_SB_TRACE, "Shutting down clock for SATA ports %X \n", UnusedPortBitMap)); - RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, UnusedPortBitMap); - RWMEM(ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~UnusedPortBitMap, 00); - } - - // If all ports are in disabled state, report at least one - ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus); - if ( (dbPortSataStatus & 0x3F) == 0) { - dbPortSataStatus = 1; - RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(0x3F), dbPortSataStatus); - } - - // Decide if we need to hide unused ports from being seen by OS (this saves OS startup time) - if (pConfig->SataHideUnusedPort && ClockOffEnabled) { - dbPortSataStatus &= ~UnusedPortBitMap; // Mask off unused ports - for (dbPortNum = 0; dbPortNum <= 6; dbPortNum++) { - if (dbPortSataStatus & (1 << dbPortNum)) - NumOfPorts++; - } - if (NumOfPorts == 0 ) { - NumOfPorts = 0x01; - } - RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1); - } -} - - -void restrictSataCapabilities(AMDSBCFG* pConfig){ - //Restrict capabilities - if ( ((getSbCapability(Sb_Raid0_1_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \ - ((getSbCapability(Sb_Raid5_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \ - ((getSbCapability(Sb_Ahci_Capability)== 0x02) && ((pConfig->SataClass == AHCI_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE)))){ - pConfig->SataClass = NATIVE_IDE_MODE; - } -} diff --git a/src/vendorcode/amd/cimx/sb700/SB700.h b/src/vendorcode/amd/cimx/sb700/SB700.h deleted file mode 100644 index f9e71e8945..0000000000 --- a/src/vendorcode/amd/cimx/sb700/SB700.h +++ /dev/null @@ -1,1028 +0,0 @@ -/*;******************************************************************************** -; -; Copyright (C) 2012 Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;*********************************************************************************/ - -#ifndef _AMD_SB700_H_ -#define _AMD_SB700_H_ - -#pragma pack(push,1) - -#define CIMx_Version 0x0660 -#define RC_Information 0x00 -#define Additional_Changes_Indicator 0x00 - -#define SB_POWERON_INIT 0x001 -#define OUTDEBUG_PORT 0x002 -#define SB_BEFORE_PCI_INIT 0x010 -#define SB_AFTER_PCI_INIT 0x020 -#define SB_LATE_POST_INIT 0x030 -#define SB_BEFORE_PCI_RESTORE_INIT 0x040 -#define SB_AFTER_PCI_RESTORE_INIT 0x050 -#define SB_SMM_SERVICE 0x060 -#define SB_SMM_ACPION 0x061 - -#ifndef OEM_CALLBACK_BASE - #define OEM_CALLBACK_BASE 0x100 -#endif - -//0x00 - 0x0F callback functions are reserved for bootblock -#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10 -#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20 - -#define CFG_ADDR_PORT 0xCF8 -#define CFG_DATA_PORT 0xCFC -#define ATI_AZALIA_ExtBlk_Addr 0x0F8 -#define ATI_AZALIA_ExtBlk_DATA 0x0FC - -#define ALINK_ACCESS_INDEX 0x0CD8 -#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4 - -/*------------------------------------------------------------------ -; I/O Base Address - Should be set by host BIOS -;------------------------------------------------------------------ */ -#define DELAY_PORT 0x0E0 - -/*------------------------------------------------------------------ -; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display -;------------------------------------------------------------------ */ -#define SB7XX_DEVICE_ID 0x4385 - -#define SB700_A11 0x39 -#define SB700_A12 0x3A -#define SB700_A13 0x3B -#define SB700_A14 0x3C -#define SB700_A15 0x3D - -#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0) -#define FC_BUS_DEV_FUN ((0x11 << 3) + 1) -#define USB1_OHCI0_BUS_DEV_FUN ((0x12 << 3) + 0) -#define USB1_OHCI1_BUS_DEV_FUN ((0x12 << 3) + 1) -#define USB2_OHCI0_BUS_DEV_FUN ((0x13 << 3) + 0) -#define USB2_OHCI1_BUS_DEV_FUN ((0x13 << 3) + 1) -#define USB3_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) -#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) -#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) - -#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0) -#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1) -#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2) -#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3) -#define SBP2P_BUS_DEV_FUN ((0x14 << 3) + 4) -#define NB_BDF ((0 << 3) + 0) -#define HT_LINK_BUS_DEV_FUN ((0x18 << 3) + 0) -#define DCT1_BUS_DEV_FUN ((0x18 << 3) + 2) -#define DCT2_BUS_DEV_FUN ((0x19 << 3) + 2) -#define DCT3_BUS_DEV_FUN ((0x1A << 3) + 2) -#define DCT4_BUS_DEV_FUN ((0x1B << 3) + 2) - - -//Sata Controller Mode -#define NATIVE_IDE_MODE 0 -#define RAID_MODE 1 -#define AHCI_MODE 2 -#define LEGACY_IDE_MODE 3 -#define IDE_TO_AHCI_MODE 4 -#define AMD_AHCI_MODE 5 -#define IDE_TO_AMD_AHCI_MODE 6 - -//Sata Port Configuration -#define SIX_PORTS 0 -#define FOUR_PORTS 1 - -#define SB750_SATA_DEFAULT_DEVICE_ID 0x4393 - -#define SB_AX_INDXC_REG30 0x30 -#define SB_AX_DATAC_REG34 0x34 -#define SB_AX_INDXP_REG38 0x38 -#define SB_AX_DATAP_REG3C 0x3C - -#define AX_INDXC 0 -#define AX_INDXP 1 -#define AXCFG 2 -#define ABCFG 3 - -#define SB_AB_REG02 0x02 -#define SB_AB_REG04 0x04 -#define SB_AB_REG40 0x40 // -#define SB_AB_REG54 0x54 //;miscCtr54 -#define SB_AB_REG58 0x58 //;RAB Control - RW - 32 bits - [RegAddr:58] -#define SB_AB_REG60 0x60 //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:60] -#define SB_AB_REG64 0x64 //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64] -#define SB_AB_REG6C 0x6C //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:6C] -#define SB_AB_REG80 0x80 //;DMA Prefetch Control Port 1 - RW - 32 bits - [RegAddr:80] -#define SB_AB_REG88 0x88 //;DMA Prefetch Control Port 2 - RW - 32 bits - [RegAddr:88] -#define SB_AB_REG8C 0x8C //;AB Enhancement - RW - 16 bits - [RegAddr:88] -#define SB_AB_REG90 0x90 //;BIF Control - RW - 32 bits - [RegAddr:90] -#define SB_AB_REG94 0x94 //;MSI Control - RW - 32 bits -#define SB_AB_REG98 0x98 //;BIF Control 1 - RW - 32 bits -#define SB_AB_REG9C 0x9C //; -#define SB_AB_REG10050 BIT16+0x50 -#define SB_AB_REG10054 BIT16+0x54 //;AL_Arb_Ctl, AL_Clk_Ctl -#define SB_AB_REG10060 BIT16+0x60 //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:10060] -#define SB_AB_REG10064 BIT16+0x64 //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64] -#define SB_AB_REG10090 BIT16+0x90 //; -#define SB_AB_REG1009C BIT16+0x9C //; - - -#define SB_PMIO_REG00 0x000 // MiscControl -#define SB_PMIO_REG01 0x001 // MiscStatus -#define SB_PMIO_REG02 0x002 // SmiWakeUpEventEnable1 -#define SB_PMIO_REG03 0x003 // SmiWakeUpEventEnable2 -#define SB_PMIO_REG04 0x004 // SmiWakeUpEventEnable3 -#define SB_PMIO_REG05 0x005 // SmiWakeUpEventStatus1 -#define SB_PMIO_REG06 0x006 // SmiWakeUpEventStatus2 -#define SB_PMIO_REG07 0x007 // SmiWakeUpEventStatus3 -#define SB_PMIO_REG08 0x008 // InactiveTmrEventEnable1 -#define SB_PMIO_REG09 0x009 // InactiveTmrEventEnable2 -#define SB_PMIO_REG0A 0x00A // InactiveTmrEventEnable3 -#define SB_PMIO_REG0B 0x00B // PmTmr1InitValue -#define SB_PMIO_REG0C 0x00C // PmTmr1CurValue -#define SB_PMIO_REG0D 0x00D // PwrLedExtEvent -#define SB_PMIO_REG0E 0x00E // AcpiControl -#define SB_PMIO_REG0F 0x00F // AcpiStatus -#define SB_PMIO_REG10 0x010 // AcpiEn -#define SB_PMIO_REG11 0x011 // S1AgpStpEn -#define SB_PMIO_REG12 0x012 // PmTmr2InitValue -#define SB_PMIO_REG13 0x013 // PmTmr2CurValue -#define SB_PMIO_REG14 0x014 // Programlo0RangeLo -#define SB_PMIO_REG15 0x015 // ProgramIo0Rangei -#define SB_PMIO_REG16 0x016 // ProgramIo1RangeLo -#define SB_PMIO_REG17 0x017 // ProgramIo1Rangei -#define SB_PMIO_REG18 0x018 // ProgramIo2RangeLo -#define SB_PMIO_REG19 0x019 // ProgramIo2Rangei -#define SB_PMIO_REG1A 0x01A // ProgramIo3RangeLo -#define SB_PMIO_REG1B 0x01B // ProgramIo3Rangei -#define SB_PMIO_REG1C 0x01C // ProgramIoEnable -#define SB_PMIO_REG1D 0x01D // IOMonitorStatus -#define SB_PMIO_REG1E 0x01E // InactiveTmrEventEnable4 -#define SB_PMIO_REG20 0x020 // AcpiPm1EvtBlkLo -#define SB_PMIO_REG21 0x021 // AcpiPm1EvtBlki -#define SB_PMIO_REG22 0x022 // AcpiPm1CntBlkLo -#define SB_PMIO_REG23 0x023 // AcpiPm1CntBlki -#define SB_PMIO_REG24 0x024 // AcpiPmTmrBlkLo -#define SB_PMIO_REG25 0x025 // AcpiPmTmrBlki -#define SB_PMIO_REG26 0x026 // CpuControlLo -#define SB_PMIO_REG27 0x027 // CpuControli -#define SB_PMIO_REG28 0x028 // AcpiGpe0BlkLo -#define SB_PMIO_REG29 0x029 // AcpiGpe0Blki -#define SB_PMIO_REG2A 0x02A // AcpiSmiCmdLo -#define SB_PMIO_REG2B 0x02B // AcpiSmiCmdi -#define SB_PMIO_REG2C 0x02C // AcpiPmaCntBlkLo -#define SB_PMIO_REG2D 0x02D // AcpiPmaCntBlki -#define SB_PMIO_REG2E 0x02E // AcpiSsCntBlkLo -#define SB_PMIO_REG2F 0x02F // AcpiSsCntBlki -#define SB_PMIO_REG30 0x030 // GEvtConfig0 -#define SB_PMIO_REG31 0x031 // GEvtConfig1 -#define SB_PMIO_REG32 0x032 // GPMConfig0 -#define SB_PMIO_REG33 0x033 // GPMConfig1 -#define SB_PMIO_REG34 0x034 // GPMConfig2 -#define SB_PMIO_REG35 0x035 // GPMConfig3 -#define SB_PMIO_REG36 0x036 // GEvtLevelConfig -#define SB_PMIO_REG37 0x037 // GPMLevelConfig0 -#define SB_PMIO_REG38 0x038 // GPMLevelConfig1 -#define SB_PMIO_REG39 0x039 // GEvtStatus -#define SB_PMIO_REG3A 0x03A // PMEStatus0 -#define SB_PMIO_REG3B 0x03B // PMEStatus1 -#define SB_PMIO_REG3C 0x03C // OtersConfig -#define SB_PMIO_REG3E 0x03E // VRT_T1 -#define SB_PMIO_REG3F 0x03F // VRT_T2 -#define SB_PMIO_REG40 0x040 // Fan0DutyCycle -#define SB_PMIO_REG41 0x041 // Fan0Control -#define SB_PMIO_REG42 0x042 // Fan1DutyCycle -#define SB_PMIO_REG43 0x043 // Reserved for internal use -#define SB_PMIO_REG50 0x050 // PM_Enable -#define SB_PMIO_REG51 0x051 // TPRESET1 -#define SB_PMIO_REG52 0x052 // TPRESET2 -#define SB_PMIO_REG53 0x053 // TESTENABLE -#define SB_PMIO_REG54 0x054 // PWRBTTN_CLR -#define SB_PMIO_REG55 0x055 // SoftPciRst -#define SB_PMIO_REG56 0x056 // Reserved -#define SB_PMIO_REG59 0x059 // Ac97Mask -#define SB_PMIO_REG60 0x060 // Options_0 -#define SB_PMIO_REG61 0x061 // Options_1 -#define SB_PMIO_REG62 0x062 // Sadow_SCI -#define SB_PMIO_REG63 0x063 // SwitcVoltageTime -#define SB_PMIO_REG64 0x064 // SwitchGI_Time -#define SB_PMIO_REG65 0x065 // UsbPMControl -#define SB_PMIO_REG66 0x066 // MiscEnable66 -#define SB_PMIO_REG67 0x067 // MiscEnable67 -#define SB_PMIO_REG68 0x068 // MiscEnable68 -#define SB_PMIO_REG69 0x069 // WatcDogTimerControl -#define SB_PMIO_REG6C 0x06C // WatcDogTimerBase0 -#define SB_PMIO_REG6D 0x06D // WatcDogTimerBase1 -#define SB_PMIO_REG6E 0x06E // WatcDogTimerBase2 -#define SB_PMIO_REG6F 0x06F // WatcDogTimerBase3 -#define SB_PMIO_REG70 0x070 // S_LdtStartTime -#define SB_PMIO_REG71 0x071 // FidVidOption -#define SB_PMIO_REG72 0x072 // Spare4 -#define SB_PMIO_REG73 0x073 // Spare5 -#define SB_PMIO_REG74 0x074 // PwrFailSadow -#define SB_PMIO_REG75 0x075 // Tpreset1b -#define SB_PMIO_REG76 0x076 // S0S3ToS5Enable0 -#define SB_PMIO_REG77 0x077 // S0S3ToS5Enable1 -#define SB_PMIO_REG78 0x078 // S0S3ToS5Enable2 -#define SB_PMIO_REG79 0x079 // S0S3ToS5Enable3 -#define SB_PMIO_REG7A 0x07A // NoStatusControl0 -#define SB_PMIO_REG7B 0x07B // NoStatusControl1 -#define SB_PMIO_REG7C 0x07C // MiscEnable7C -#define SB_PMIO_REG80 0x080 // SMAF0 -#define SB_PMIO_REG81 0x081 // SMAF1 -#define SB_PMIO_REG82 0x082 // SMAF2 -#define SB_PMIO_REG83 0x083 // SMAF3 -#define SB_PMIO_REG84 0x084 // WakePinCntl -#define SB_PMIO_REG85 0x085 // CF9Rst -#define SB_PMIO_REG86 0x086 // ThermTrotCntl -#define SB_PMIO_REG87 0x087 // LdtStpCmd -#define SB_PMIO_REG88 0x088 // LdtStartTime -#define SB_PMIO_REG89 0x089 // AgpStartTime -#define SB_PMIO_REG8A 0x08A // LdtAgpTimeCntl -#define SB_PMIO_REG8B 0x08B // StutterTime -#define SB_PMIO_REG8C 0x08C // StpClkDlyTime -#define SB_PMIO_REG8D 0x08D // AbPmeCntl -#define SB_PMIO_REG8E 0x08E // FakeAsr -#define SB_PMIO_REG8F 0x08F // FakeAsrEn -#define SB_PMIO_REG90 0x090 // GEVENTOUT -#define SB_PMIO_REG91 0x091 // GEVENTEnable -#define SB_PMIO_REG92 0x092 // GEVENTIN -#define SB_PMIO_REG95 0x095 // GPM98EN -#define SB_PMIO_REG9A 0x09A // EnanceControl -#define SB_PMIO_REG9E 0x09E // EnanceControl -#define SB_PMIO_REG9F 0x09F // EnanceControl -#define SB_PMIO_REGA0 0x0A0 // Programlo4RangeLo -#define SB_PMIO_REGA1 0x0A1 // ProgramIo4Rangei -#define SB_PMIO_REGA2 0x0A2 // Programlo5RangeLo -#define SB_PMIO_REGA3 0x0A3 // ProgramIo5Rangei -#define SB_PMIO_REGA4 0x0A4 // Programlo6RangeLo -#define SB_PMIO_REGA5 0x0A5 // ProgramIo6Rangei -#define SB_PMIO_REGA6 0x0A6 // Programlo7RangeLo -#define SB_PMIO_REGA7 0x0A7 // ProgramIo7Rangei -#define SB_PMIO_REGA8 0x0A8 // PIO7654Enable -#define SB_PMIO_REGA9 0x0A9 // PIO7654Status -#define SB_PMIO_REGB0 0x0B0 -#define SB_PMIO_REGB1 0x0B1 -#define SB_PMIO_REGB2 0x0B2 // MiscControl3 -#define SB_PMIO_REGB4 0x0B4 // HPET BAR -#define SB_PMIO_REGB6 0x0B6 -#define SB_PMIO_REGB7 0x0B7 -#define SB_PMIO_REGBB 0x0BB // IMC_ACPI_Enable -#define SB_PMIO_REGBC 0x0BC // -#define SB_PMIO_REGBD 0x0BD // -#define SB_PMIO_REGC9 0x0C9 // MultiK8Control -#define SB_PMIO_REGCA 0x0CA // -#define SB_PMIO_REGCB 0x0CB // -#define SB_PMIO_REGCC 0x0CC // -#define SB_PMIO_REGCD 0x0CD // -#define SB_PMIO_REGD0 0x0D0 // -#define SB_PMIO_REGD2 0x0D2 // -#define SB_PMIO_REGD4 0x0D4 // -#define SB_PMIO_REGD7 0x0D7 // - - -#define SB_RTC_REG00 0x00 // Seconds - RW -#define SB_RTC_REG01 0x01 // Seconds Alarm - RW -#define SB_RTC_REG02 0x02 // Minutes - RW -#define SB_RTC_REG03 0x03 // Minutes Alarm - RW -#define SB_RTC_REG04 0x04 // ours - RW -#define SB_RTC_REG05 0x05 // ours Alarm- RW -#define SB_RTC_REG06 0x06 // Day of Week - RW -#define SB_RTC_REG07 0x07 // Date of Mont - RW -#define SB_RTC_REG08 0x08 // Mont - RW -#define SB_RTC_REG09 0x09 // Year - RW -#define SB_RTC_REG0A 0x0A // Register A - RW -#define SB_RTC_REG0B 0x0B // Register B - RW -#define SB_RTC_REG0C 0x0C // Register C - R -#define SB_RTC_REG0D 0x0D // DateAlarm - RW -#define SB_RTC_REG32 0x32 // AltCentury - RW -#define SB_RTC_REG48 0x48 // Century - RW -#define SB_RTC_REG50 0x50 // Extended RAM Address Port - RW -#define SB_RTC_REG53 0x53 // Extended RAM Data Port - RW -#define SB_RTC_REG7E 0x7E // RTC Time Clear - RW -#define SB_RTC_REG7F 0x7F // RTC RAM Enable - RW - -#define B_ECMOS_REG00 0x00 // scratc-reg - //;BIT0=0 AsicDebug is enabled - //;BIT1=0 SLT S3 runs -#define SB_ECMOS_REG01 0x01 -#define SB_ECMOS_REG02 0x02 -#define SB_ECMOS_REG03 0x03 -#define SB_ECMOS_REG04 0x04 -#define SB_ECMOS_REG05 0x05 -#define SB_ECMOS_REG06 0x06 -#define SB_ECMOS_REG07 0x07 -#define SB_ECMOS_REG08 0x08 // save 32BIT Pysical address of Config structure -#define SB_ECMOS_REG09 0x09 -#define SB_ECMOS_REG0A 0x0A -#define SB_ECMOS_REG0B 0x0B - -#define SB_ECMOS_REG0C 0x0C //;save MODULE_ID -#define SB_ECMOS_REG0D 0x0D //;Reserve for NB - -#define SB_IOMAP_REG00 0x000 // Dma_C 0 -#define SB_IOMAP_REG02 0x002 // Dma_C 1 -#define SB_IOMAP_REG04 0x004 // Dma_C 2 -#define SB_IOMAP_REG06 0x006 // Dma_C 3 -#define SB_IOMAP_REG08 0x008 // Dma_Status -#define SB_IOMAP_REG09 0x009 // Dma_WriteRest -#define SB_IOMAP_REG0A 0x00A // Dma_WriteMask -#define SB_IOMAP_REG0B 0x00B // Dma_WriteMode -#define SB_IOMAP_REG0C 0x00C // Dma_Clear -#define SB_IOMAP_REG0D 0x00D // Dma_MasterClr -#define SB_IOMAP_REG0E 0x00E // Dma_ClrMask -#define SB_IOMAP_REG0F 0x00F // Dma_AllMask -#define SB_IOMAP_REG20 0x020 // IntrCntrlReg1 -#define SB_IOMAP_REG21 0x021 // IntrCntrlReg2 -#define SB_IOMAP_REG40 0x040 // TimerC0 -#define SB_IOMAP_REG41 0x041 // TimerC1 -#define SB_IOMAP_REG42 0x042 // TimerC2 -#define SB_IOMAP_REG43 0x043 // Tmr1CntrlWord -#define SB_IOMAP_REG61 0x061 // Nmi_Status -#define SB_IOMAP_REG70 0x070 // Nmi_Enable -#define SB_IOMAP_REG71 0x071 // RtcDataPort -#define SB_IOMAP_REG72 0x072 // AlternatRtcAddrPort -#define SB_IOMAP_REG73 0x073 // AlternatRtcDataPort -#define SB_IOMAP_REG80 0x080 // Dma_Page_Reserved0 -#define SB_IOMAP_REG81 0x081 // Dma_PageC2 -#define SB_IOMAP_REG82 0x082 // Dma_PageC3 -#define SB_IOMAP_REG83 0x083 // Dma_PageC1 -#define SB_IOMAP_REG84 0x084 // Dma_Page_Reserved1 -#define SB_IOMAP_REG85 0x085 // Dma_Page_Reserved2 -#define SB_IOMAP_REG86 0x086 // Dma_Page_Reserved3 -#define SB_IOMAP_REG87 0x087 // Dma_PageC0 -#define SB_IOMAP_REG88 0x088 // Dma_Page_Reserved4 -#define SB_IOMAP_REG89 0x089 // Dma_PageC6 -#define SB_IOMAP_REG8A 0x08A // Dma_PageC7 -#define SB_IOMAP_REG8B 0x08B // Dma_PageC5 -#define SB_IOMAP_REG8C 0x08C // Dma_Page_Reserved5 -#define SB_IOMAP_REG8D 0x08D // Dma_Page_Reserved6 -#define SB_IOMAP_REG8E 0x08E // Dma_Page_Reserved7 -#define SB_IOMAP_REG8F 0x08F // Dma_Refres -#define SB_IOMAP_REG92 0x092 // FastInit -#define SB_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1 -#define SB_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2 -#define SB_IOMAP_REGC0 0x0C0 // Dma2_C4Addr -#define SB_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt -#define SB_IOMAP_REGC4 0x0C4 // Dma2_C5Addr -#define SB_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt -#define SB_IOMAP_REGC8 0x0C8 // Dma2_C6Addr -#define SB_IOMAP_REGCA 0x0CA // Dma2_C6Cnt -#define SB_IOMAP_REGCC 0x0CC // Dma2_C7Addr -#define SB_IOMAP_REGCE 0x0CE // Dma2_C7Cnt -#define SB_IOMAP_REGD0 0x0D0 // Dma_Status -#define SB_IOMAP_REGD2 0x0D2 // Dma_WriteRest -#define SB_IOMAP_REGD4 0x0D4 // Dma_WriteMask -#define SB_IOMAP_REGD6 0x0D6 // Dma_WriteMode -#define SB_IOMAP_REGD8 0x0D8 // Dma_Clear -#define SB_IOMAP_REGDA 0x0DA // Dma_Clear -#define SB_IOMAP_REGDC 0x0DC // Dma_ClrMask -#define SB_IOMAP_REGDE 0x0DE // Dma_ClrMask -#define SB_IOMAP_REGF0 0x0F0 // NCP_Error -#define SB_IOMAP_REG40B 0x040B // DMA1_Extend -#define SB_IOMAP_REG4D0 0x04D0 // IntrEdgeControl -#define SB_IOMAP_REG4D6 0x04D6 // DMA2_Extend -#define SB_IOMAP_REGC00 0x0C00 // Pci_Intr_Index -#define SB_IOMAP_REGC01 0x0C01 // Pci_Intr_Data -#define SB_IOMAP_REGC14 0x0C14 // Pci_Error -#define SB_IOMAP_REGC50 0x0C50 // CMIndex -#define SB_IOMAP_REGC51 0x0C51 // CMData -#define SB_IOMAP_REGC52 0x0C52 // GpmPort -#define SB_IOMAP_REGC6F 0x0C6F // Isa_Misc -#define SB_IOMAP_REGCD0 0x0CD0 // PMio2_Index -#define SB_IOMAP_REGCD1 0x0CD1 // PMio2_Data -#define SB_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index -#define SB_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data -#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index -#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data -#define SB_IOMAP_REGCF9 0x0CF9 // CF9Rst reg - - -#define SB_CM_REG02 0x002 // TempStatus (via SB_IOMAP_REGC50) -#define SB_CM_REG03 0x003 // TempInterrupt (via SB_IOMAP_REGC50) - -#define SB_SATA_REG00 0x000 // Vendor ID - R- 16 bits -#define SB_SATA_REG02 0x002 // Device ID - RW -16 bits -#define SB_SATA_REG04 0x004 // PCI Command - RW - 16 bits -#define SB_SATA_REG06 0x006 // PCI Status - RW - 16 bits -#define SB_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08 -#define SB_SATA_REG0C 0x00C // Cace Line Size - R/W - 8bits -#define SB_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits -#define SB_SATA_REG0E 0x00E // eader Type - R - 8 bits -#define SB_SATA_REG0F 0x00F // BIST - R - 8 bits -#define SB_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits -#define SB_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits -#define SB_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits -#define SB_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits -#define SB_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits -#define SB_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits -#define SB_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits -#define SB_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits -#define SB_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits -#define SB_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits -#define SB_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits -#define SB_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits -#define SB_SATA_REG3E 0x03E // Min Grant - R - 8 bits -#define SB_SATA_REG3F 0x03F // Max Latency - R - 8 bits -#define SB_SATA_REG40 0x040 // Configuration - RW - 32 bits -#define SB_SATA_REG44 0x044 // Software Data Register - RW - 32 bits -#define SB_SATA_REG48 0x048 -#define SB_SATA_REG50 0x050 // Message Capability - R - 16 bits -#define SB_SATA_REG52 0x052 // Message Control - R/W - 16 bits -#define SB_SATA_REG54 0x054 // Message Address - R/W - 32 bits -#define SB_SATA_REG58 0x058 // Message Data - R/W - 16 bits -#define SB_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits -#define SB_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits -#define SB_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits -#define SB_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits -#define SB_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits -#define SB_SATA_REG68 0x068 // MSI Program Weigt - R/W - 8 bits -#define SB_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits -#define SB_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits -#define SB_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits -#define SB_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits -#define SB_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits -#define SB_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits -#define SB_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits -#define SB_SATA_REG86 0x086 // PY Global Control -#define SB_SATA_REG87 0x087 -#define SB_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune(0:23) -#define SB_SATA_REG8A 0x08A -#define SB_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune(0:23) -#define SB_SATA_REG8E 0x08E -#define SB_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune(0:23) -#define SB_SATA_REG92 0x092 -#define SB_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune(0:23) -#define SB_SATA_REG96 0x096 -#define SB_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits -#define SB_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits -#define SB_SATA_REGA0 0x0A0 // -#define SB_SATA_REGA4 0x0A4 // -#define SB_SATA_REGA5 0x0A5 //; -#define SB_SATA_REGA8 0x0A8 // -#define SB_SATA_REGAD 0x0AD //; -#define SB_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits -#define SB_SATA_REGB5 0x0B5 //; -#define SB_SATA_REGBD 0x0BD //; -#define SB_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits -#define SB_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits - -#define SB_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits -#define SB_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits -#define SB_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits -#define SB_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits -#define SB_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits -#define SB_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits -#define SB_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits -#define SB_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits -#define SB_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits -#define SB_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits -#define SB_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits -#define SB_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits -#define SB_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits -#define SB_SATA_BAR5_REG8C 0x08C // IDE0 Read Aead Data - RW - 32 bits -#define SB_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits -#define SB_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits -#define SB_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits -#define SB_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits -#define SB_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits -#define SB_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits -#define SB_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits -#define SB_SATA_BAR5_REGCC 0x0CC // Read/Write Aead Data - RW - 32 bits -#define SB_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits -#define SB_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits -#define SB_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits -#define SB_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits -#define SB_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REGF8 0x0F8 // PORT Configuration -#define SB_SATA_BAR5_REGFC 0x0FC - -#define SB_SATA_BAR5_REG100 0x0100 //;Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180 -#define SB_SATA_BAR5_REG104 0x0104 //;Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel -#define SB_SATA_BAR5_REG108 0x0108 //;Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel -#define SB_SATA_BAR5_REG10C 0x010C //;Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel -#define SB_SATA_BAR5_REG110 0x0110 // Port-N Interrupt Status -#define SB_SATA_BAR5_REG144 0x0144 //;Serial ATA PY Configuration - RW - 32 bits -#define SB_SATA_BAR5_REG148 0x0148 //;SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)] -#define SB_SATA_BAR5_REG14C 0x014C //;SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)] -#define SB_SATA_BAR5_REG120 0x0120 // Port Task Fike Data -#define SB_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status -#define SB_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control - -#define SB_SATA_BAR5_REG130 0x0130 -#define SB_SATA_BAR5_REG1B0 0x01B0 -#define SB_SATA_BAR5_REG230 0x0230 -#define SB_SATA_BAR5_REG2B0 0x02B0 - -#define SB_FC_REG00 0x00 // Device/Vendor ID - R -#define SB_FC_REG04 0x04 // Command - RW -#define SB_FC_REG10 0x10 // BAR - -#define SB_FC_MMIO_REG70 0x070 -#define SB_FC_MMIO_REG200 0x200 - -#define SB_OHCI_REG00 0x00 // Device/Vendor ID - R -#define SB_OHCI_REG04 0x04 // Command - RW -#define SB_OHCI_REG06 0x06 // Status - R -#define SB_OHCI_REG08 0x08 // Revision ID/Class Code - R -#define SB_OHCI_REG0C 0x0C // Miscellaneous - RW -#define SB_OHCI_REG10 0x10 // Bar_OCI - RW -#define SB_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW -#define SB_OHCI_REG34 0x34 // Capability Pointer - R -#define SB_OHCI_REG3C 0x3C // Interrupt Line - RW -#define SB_OHCI_REG3D 0x3D // Interrupt Line - RW - -#define SB_OHCI_REG40 0x40 // Config Timers - RW -#define SB_OHCI_REG4C 0x4C // MSI Weigt - RW -#define SB_OHCI_REG50 0x50 // ATI Misc Control - RW -#define SB_OHCI_REG51 0x51 -#define SB_OHCI_REG58 0x58 // Over Current Control - RW -#define SB_OHCI_REG5C 0x5C // Over Current Control - RW -#define SB_OHCI_REG60 0x60 // Serial Bus Release Number - R -#define SB_OHCI_REG68 0x68 // Over Current Enable - RW -#define SB_OHCI_REGD0 0x0D0 // MSI Control - RW -#define SB_OHCI_REGD4 0x0D4 // MSI Address - RW -#define SB_OHCI_REGD8 0x0D8 // MSI Data - RW -#define SB_OHCI_BAR_REG00 0x00 // cRevision - R -#define SB_OHCI_BAR_REG04 0x04 // cControl -#define SB_OHCI_BAR_REG08 0x08 // cCommandStatus -#define SB_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW -#define SB_OHCI_BAR_REG10 0x10 // cInterruptEnable -#define SB_OHCI_BAR_REG14 0x14 // cInterruptDisable -#define SB_OHCI_BAR_REG18 0x18 // HcCCA -#define SB_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED -#define SB_OHCI_BAR_REG20 0x20 // HcControleadED -#define SB_OHCI_BAR_REG24 0x24 // cControlCurrentED RW -#define SB_OHCI_BAR_REG28 0x28 // HcBulkeadED -#define SB_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW -#define SB_OHCI_BAR_REG30 0x30 // HcDoneead -#define SB_OHCI_BAR_REG34 0x34 // cFmInterval -#define SB_OHCI_BAR_REG38 0x38 // cFmRemaining -#define SB_OHCI_BAR_REG3C 0x3C // cFmNumber -#define SB_OHCI_BAR_REG40 0x40 // cPeriodicStart -#define SB_OHCI_BAR_REG44 0x44 // HcLSThresold -#define SB_OHCI_BAR_REG48 0x48 // HcRDescriptorA -#define SB_OHCI_BAR_REG4C 0x4C // HcRDescriptorB -#define SB_OHCI_BAR_REG50 0x50 // HcRStatus -#define SB_OHCI_BAR_REG160 0x160 - -#define SB_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R -#define SB_EHCI_REG04 0x04 // Command - RW -#define SB_EHCI_REG06 0x06 // Status - R -#define SB_EHCI_REG08 0x08 // Revision ID/Class Code - R -#define SB_EHCI_REG0C 0x0C // Miscellaneous - RW -#define SB_EHCI_REG10 0x10 // BAR - RW -#define SB_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW -#define SB_EHCI_REG34 0x34 // Capability Pointer - R -#define SB_EHCI_REG3C 0x3C // Interrupt Line - RW -#define SB_EHCI_REG3D 0x3D // Interrupt Line - RW -#define SB_EHCI_REG40 0x40 // Config Timers - RW -#define SB_EHCI_REG4C 0x4C // MSI Weigt - RW -#define SB_EHCI_REG50 0x50 // ATI Misc Control - RW -#define SB_EHCI_REG54 0x54 // ATI Misc Control - RW -#define SB_EHCI_REG58 0x58 // Over Current Control - R -#define SB_EHCI_REG60 0x60 // SBRN - R -#define SB_EHCI_REG61 0x61 // FLADJ - RW -#define SB_EHCI_REG62 0x62 // PORTWAKECAP - RW -#define SB_EHCI_REGD0 0x0D0 // MSI Control - RW -#define SB_EHCI_REGD4 0x0D4 // MSI Address - RW -#define SB_EHCI_REGD8 0x0D8 // MSI Data - RW -#define SB_EHCI_REGDC 0x0DC // PME Control - RW -#define SB_EHCI_REGE0 0x0E0 // PME Data / Status - RW -#define SB_EHCI_BAR_REG00 0x00 // CAPLENGT - R -#define SB_EHCI_BAR_REG02 0x002 // CIVERSION- R -#define SB_EHCI_BAR_REG04 0x004 // CSPARAMS - R -#define SB_EHCI_BAR_REG08 0x008 // CCPARAMS - R -#define SB_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R -#define SB_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits -#define SB_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits -#define SB_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits -#define SB_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits -#define SB_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits -#define SB_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits -#define SB_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits -#define SB_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits -#define SB_EHCI_BAR_REG64 0x064 // PORTSC(1-N_PORTS) -RW - 32 bits -#define SB_EHCI_BAR_REG84 0x084 // Packet Buffer Thresold Values - RW - 32 bits -#define SB_EHCI_BAR_REG88 0x088 // Packet Buffer Dept Value - RW - 32 bits -#define SB_EHCI_BAR_REG94 0x094 // UTMI Control and Status - RW - 32 bits -#define SB_EHCI_BAR_REG98 0x098 // Bist Control - RW - 32 bits -#define SB_EHCI_BAR_REG9C 0x09C // ATI EOR Control - RW - 32 bits -#define SB_EHCI_BAR_REGA4 0x0A4 // USB IN/OUT FIFO Thresold Setting -#define SB_EHCI_BAR_REGBC 0x0BC // ECI misc Setting -#define SB_EHCI_BAR_REGC0 0x0C0 // USB PHY Auto Calibration Setting - -#define SB_SMBUS_REG00 0x000 //;VendorID - R -#define SB_SMBUS_REG02 0x002 //;DeviceID - R -#define SB_SMBUS_REG04 0x004 // Command- RW -#define SB_SMBUS_REG05 0x005 // Command- RW -#define SB_SMBUS_REG06 0x006 // STATUS- RW -#define SB_SMBUS_REG08 0x008 // Revision ID/Class Code- R -#define SB_SMBUS_REG0A 0x00A //; -#define SB_SMBUS_REG0B 0x00B //; -#define SB_SMBUS_REG0C 0x00C // Cace Line Size- R -#define SB_SMBUS_REG0D 0x00D // Latency Timer- R -#define SB_SMBUS_REG0E 0x00E // eader Type- R -#define SB_SMBUS_REG0F 0x00F // BIST- R -#define SB_SMBUS_REG10 0x010 // Base Address 0- R -#define SB_SMBUS_REG11 0x011 //; -#define SB_SMBUS_REG12 0x012 //; -#define SB_SMBUS_REG13 0x013 //; -#define SB_SMBUS_REG14 0x014 // Base Address 1- R -#define SB_SMBUS_REG18 0x018 // Base Address 2- R -#define SB_SMBUS_REG1C 0x01C // Base Address 3- R -#define SB_SMBUS_REG20 0x020 // Base Address 4- R -#define SB_SMBUS_REG24 0x024 // Base Address 5- R -#define SB_SMBUS_REG28 0x028 // Cardbus CIS Pointer- R -#define SB_SMBUS_REG2C 0x02C // Subsystem Vendor ID- W -#define SB_SMBUS_REG2E 0x02E // Subsystem ID- W -#define SB_SMBUS_REG30 0x030 // Expansion ROM Base Address - R -#define SB_SMBUS_REG34 0x034 // Capability Pointer - R -#define SB_SMBUS_REG38 0x038 -#define SB_SMBUS_REG3C 0x03C // Interrupt Line - R -#define SB_SMBUS_REG3D 0x03D // Interrupt Pin - R -#define SB_SMBUS_REG3E 0x03E // Min_Gnt - R -#define SB_SMBUS_REG3F 0x03F // Max_Lat - R -#define SB_SMBUS_REG40 0x040 // PCI Control- RW -#define SB_SMBUS_REG41 0x041 // MiscFunction- RW -#define SB_SMBUS_REG42 0x042 // DmaLimit- RW -#define SB_SMBUS_REG43 0x043 // DmaEnanceEnable RW -#define SB_SMBUS_REG48 0x048 // ISA Address Decode Control Register #1- RW -#define SB_SMBUS_REG49 0x049 // ISA Address Decode Control Register #2- RW -#define SB_SMBUS_REG4A 0x04A // Scratc Pad- RW -#define SB_SMBUS_REG50 0x050 // PciGpioOutControl- RW -#define SB_SMBUS_REG54 0x054 // PciGpioConfig- RW -#define SB_SMBUS_REG58 0x058 // ASFSMBusIoBase -#define SB_SMBUS_REG59 0x059 //; -#define SB_SMBUS_REG5C 0x05C // Smart Power Control1 -#define SB_SMBUS_REG60 0x060 // MiscEnable- RW -#define SB_SMBUS_REG64 0x064 // Features Enable- RW -#define SB_SMBUS_REG68 0x068 // UsbEnable - RW -#define SB_SMBUS_REG6C 0x06C // TestMode- RW -#define SB_SMBUS_REG70 0x070 // RunTimeTest- R -#define SB_SMBUS_REG74 0x074 // IoApic_Conf- RW -#define SB_SMBUS_REG78 0x078 // IoAddrEnable - R/W -#define SB_SMBUS_REG79 0x079 //; -#define SB_SMBUS_REG7C 0x07C // RTC Control ;VSJ-2005-06-16 -#define SB_SMBUS_REG80 0x080 // GPIO_Out_Cntrl - RW -#define SB_SMBUS_REG81 0x081 // GPIO_Status - R -#define SB_SMBUS_REG90 0x090 // Smbus Base Address - R -#define SB_SMBUS_REG94 0x094 // Reserved - R -#define SB_SMBUS_REG98 0x098 // -#define SB_SMBUS_REGA0 0x0A0 // MoreGPIOIn +C R -#define SB_SMBUS_REGA4 0x0A4 // MoreGPIOIn +C R -#define SB_SMBUS_REGA8 0x0A8 // GPIOControl +C RW -#define SB_SMBUS_REGAC 0x0AC // MiscUsbEt - RW -#define SB_SMBUS_REGAD 0x0AD // MiscSata -#define SB_SMBUS_REGAE 0x0AE -#define SB_SMBUS_REGAF 0x0AF // SataIntMap - RW -#define SB_SMBUS_REGB0 0x0B0 // MSI Mapping Capability - R -#define SB_SMBUS_REGB4 0x0B4 //HPET BASE Address -#define SB_SMBUS_REGBC 0x0BC // PciIntGpio - RW -#define SB_SMBUS_REGBE 0x0BE // UsbIntMap - RW -#define SB_SMBUS_REGC0 0x0C0 // IokHiDrvSt - RW -#define SB_SMBUS_REGD0 0x0D0 // -#define SB_SMBUS_REGD2 0x0D2 // I2CbusConfig - RW -#define SB_SMBUS_REGD3 0x0D3 // I2CCommand - RW -#define SB_SMBUS_REGD4 0x0D4 // I2CSadow1- RW -#define SB_SMBUS_REGD5 0x0D5 // I2Csadow2- RW -#define SB_SMBUS_REGD6 0x0D6 // I2CBusRevision - RW -#define SB_SMBUS_REGE0 0x0E0 // MSI_Weigt -#define SB_SMBUS_REGE1 0x0E1 // MSI_Weigt -#define SB_SMBUS_REGF0 0x0F0 // AB_REG_BAR - RW -#define SB_SMBUS_REGF1 0x0F1 -#define SB_SMBUS_REGF4 0x0F4 // WakeIoAddr- RW -#define SB_SMBUS_REGF8 0x0F8 // ExtendedAddrPort- RW -#define SB_SMBUS_REGFC 0x0FC // ExtendedDataPort- RW - - -#define SB_IDE_REG00 0x00 // Vendor ID -#define SB_IDE_REG02 0x02 // Device ID -#define SB_IDE_REG04 0x04 // Command -#define SB_IDE_REG06 0x06 // Status -#define SB_IDE_REG08 0x08 // Revision ID/Class Code -#define SB_IDE_REG09 0x09 // Class Code -#define SB_IDE_REG0A 0x0A -#define SB_IDE_REG0C 0x0C // Cace Link Size -#define SB_IDE_REG0D 0x0D // Master Latency Timer -#define SB_IDE_REG0E 0x0E // eader Type -#define SB_IDE_REG0F 0x0F // BIST Mode Type -#define SB_IDE_REG10 0x10 // Base Address 0 -#define SB_IDE_REG14 0x14 // Base Address 1 -#define SB_IDE_REG18 0x18 // Base Address 2 -#define SB_IDE_REG1C 0x1C // Base Address 3 -#define SB_IDE_REG20 0x20 // Bus Master Interface Base Address -#define SB_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID -#define SB_IDE_REG34 0x34 // MSI Capabilities Pointer -#define SB_IDE_REG3C 0x3C // Interrupt Line -#define SB_IDE_REG3D 0x3D // Interrupt Pin -#define SB_IDE_REG3E 0x3E // Min_gnt -#define SB_IDE_REG3F 0x3F // Max_latency -#define SB_IDE_REG40 0x40 // IDE PIO Timing -#define SB_IDE_REG44 0x44 // IDE Legacy DMA (Multi-words DMA) Timing Modes -#define SB_IDE_REG48 0x48 // IDE PIO Control -#define SB_IDE_REG4A 0x4A // IDE PIO Mode -#define SB_IDE_REG4C 0x4C // IDE Status -#define SB_IDE_REG54 0x54 // IDE Ultra DMAControl -#define SB_IDE_REG55 0x55 // IDE Ultra DMA Status -#define SB_IDE_REG56 0x56 // IDE Ultra DMA Mode -#define SB_IDE_REG60 0x60 // IDE PCI Retry Timing Counter -#define SB_IDE_REG61 0x61 // PCI Error Control -#define SB_IDE_REG62 0x62 // IDE Internal Control -#define SB_IDE_REG63 0x63 // IDE Internal Control -#define SB_IDE_REG64 0x64 // IDE PLL Control -#define SB_IDE_REG68 0x68 // IDE MSI Programmable Weigt -#define SB_IDE_REG6C 0x6C // IDE Dynamic Clocking -#define SB_IDE_REG70 0x70 // IDE MSI Control -#define SB_IDE_REG74 0x74 // IDE MSI Address Register -#define SB_IDE_REG78 0x78 // IDE MSI Data Register - - -#define SB_AZ_REG00 0x00 // Vendor ID - R -#define SB_AZ_REG02 0x02 // Device ID - R/W -#define SB_AZ_REG04 0x04 // PCI Command -#define SB_AZ_REG06 0x06 // PCI Status - R/W -#define SB_AZ_REG08 0x08 // Revision ID -#define SB_AZ_REG09 0x09 // Programming Interface -#define SB_AZ_REG0A 0x0A // Sub Class Code -#define SB_AZ_REG0B 0x0B // Base Class Code -#define SB_AZ_REG0C 0x0C // Cace Line Size - R/W -#define SB_AZ_REG0D 0x0D // Latency Timer -#define SB_AZ_REG0E 0x0E // eader Type -#define SB_AZ_REG0F 0x0F // BIST -#define SB_AZ_REG10 0x10 // Lower Base Address Register -#define SB_AZ_REG14 0x14 // Upper Base Address Register -#define SB_AZ_REG2C 0x2C // Subsystem Vendor ID -#define SB_AZ_REG2D 0x2D // Subsystem ID -#define SB_AZ_REG34 0x34 // Capabilities Pointer -#define SB_AZ_REG3C 0x3C // Interrupt Line -#define SB_AZ_REG3D 0x3D // Interrupt Pin -#define SB_AZ_REG3E 0x3E // Minimum Grant -#define SB_AZ_REG3F 0x3F // Maximum Latency -#define SB_AZ_REG40 0x40 // Misc Control 1 -#define SB_AZ_REG42 0x42 // Misc Control 2 Register -#define SB_AZ_REG43 0x43 // Misc Control 3 Register -#define SB_AZ_REG44 0x44 // Interrupt Pin Control Register -#define SB_AZ_REG46 0x46 // Debug Control Register -#define SB_AZ_REG4C 0x4C -#define SB_AZ_REG50 0x50 // Power Management Capability ID -#define SB_AZ_REG52 0x52 // Power Management Capabilities -#define SB_AZ_REG54 0x54 // Power Management Control/Status -#define SB_AZ_REG60 0x60 // MSI Capability ID -#define SB_AZ_REG62 0x62 // MSI Message Control -#define SB_AZ_REG64 0x64 // MSI Message Lower Address -#define SB_AZ_REG68 0x68 // MSI Message Upper Address -#define SB_AZ_REG6C 0x6C // MSI Message Data - -#define SB_AZ_BAR_REG00 0x00 // Global Capabilities - R -#define SB_AZ_BAR_REG02 0x02 // Minor Version - R -#define SB_AZ_BAR_REG03 0x03 // Major Version - R -#define SB_AZ_BAR_REG04 0x04 // Output Payload Capability - R -#define SB_AZ_BAR_REG06 0x06 // Input Payload Capability - R -#define SB_AZ_BAR_REG08 0x08 // Global Control - R/W -#define SB_AZ_BAR_REG0C 0x0C // Wake Enable - R/W -#define SB_AZ_BAR_REG0E 0x0E // State Cange Status - R/W -#define SB_AZ_BAR_REG10 0x10 // Global Status - R/W -#define SB_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R -#define SB_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R -#define SB_AZ_BAR_REG20 0x20 // Interrupt Control - R/W -#define SB_AZ_BAR_REG24 0x24 // Interrupt Status - R/W -#define SB_AZ_BAR_REG30 0x30 // Wall Clock Counter - R -#define SB_AZ_BAR_REG38 0x38 // Stream Syncronization - R/W -#define SB_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W -#define SB_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW -#define SB_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W -#define SB_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W -#define SB_AZ_BAR_REG4C 0x4C // CORB Control - R/W -#define SB_AZ_BAR_REG4D 0x4D // CORB Status - R/W -#define SB_AZ_BAR_REG4E 0x4E // CORB Size - R/W -#define SB_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW -#define SB_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW -#define SB_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW -#define SB_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W -#define SB_AZ_BAR_REG5C 0x5C // RIRB Control - R/W -#define SB_AZ_BAR_REG5D 0x5D // RIRB Status - R/W -#define SB_AZ_BAR_REG5E 0x5E // RIRB Size - R/W -#define SB_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W -#define SB_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W -#define SB_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W -#define SB_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W -#define SB_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W -#define SB_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R - - -#define SB_LPC_REG00 0x00 // VID- R -#define SB_LPC_REG02 0x02 // DID- R -#define SB_LPC_REG04 0x04 // CMD- RW -#define SB_LPC_REG06 0x06 // STATUS- RW -#define SB_LPC_REG08 0x08 // Revision ID/Class Code - R -#define SB_LPC_REG0C 0x0C // Cace Line Size - R -#define SB_LPC_REG0D 0x0D // Latency Timer - R -#define SB_LPC_REG0E 0x0E // eader Type - R -#define SB_LPC_REG0F 0x0F // BIST- R -#define SB_LPC_REG10 0x10 // Base Address Reg 0- RW* -#define SB_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro -#define SB_LPC_REG34 0x34 // Capabilities Pointer - Ro -#define SB_LPC_REG40 0x40 // PCI Control - RW -#define SB_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW -#define SB_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW -#define SB_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW -#define SB_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW -#define SB_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW -#define SB_LPC_REG49 0x49 // LPC Sync Timeout Count - RW -#define SB_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW -#define SB_LPC_REG4C 0x4C // Memory Range Register - RW -#define SB_LPC_REG50 0x50 // Rom Protect 0 - RW -#define SB_LPC_REG54 0x54 // Rom Protect 1 - RW -#define SB_LPC_REG58 0x58 // Rom Protect 2 - RW -#define SB_LPC_REG5C 0x5C // Rom Protect 3 - RW -#define SB_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles - -#define SB_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles - -#define SB_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW -#define SB_LPC_REG65 0x65 -#define SB_LPC_REG66 0x66 -#define SB_LPC_REG67 0x67 -#define SB_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW -#define SB_LPC_REG69 0x69 -#define SB_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW -#define SB_LPC_REG6B 0x6B -#define SB_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW -#define SB_LPC_REG6D 0x6D -#define SB_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW -#define SB_LPC_REG6F 0x6F -#define SB_LPC_REG70 0x70 // Firmware ub Select - RW* -#define SB_LPC_REG71 0x71 -#define SB_LPC_REG72 0x72 -#define SB_LPC_REG73 0x73 -#define SB_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R -#define SB_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R -#define SB_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R -#define SB_LPC_REG9C 0x9C -#define SB_LPC_REG80 0x80 // MSI Capability Register- R -#define SB_LPC_REG8C 0x8C -#define SB_LPC_REGA0 0x0A0 // SPI base address -#define SB_LPC_REGA1 0x0A1 // SPI base address -#define SB_LPC_REGA2 0x0A2 // SPI base address -#define SB_LPC_REGA3 0x0A3 // SPI base address -#define SB_LPC_REGA4 0x0A4 -#define SB_LPC_REGB8 0x0B8 -#define SB_LPC_REGBA 0x0BA // EcControl -#define SB_LPC_REGBB 0x0BB // HostControl - - -#define SB_P2P_REG00 0x00 // VID - R -#define SB_P2P_REG02 0x02 // DID - R -#define SB_P2P_REG04 0x04 // CMD- RW -#define SB_P2P_REG06 0x06 // STATUS- RW -#define SB_P2P_REG08 0x08 // Revision ID/Class Code- R -#define SB_P2P_REG0C 0x0C // CSIZE- RW -#define SB_P2P_REG0D 0x0D // LTIMER- RW -#define SB_P2P_REG0E 0x0E // TYPE- R -#define SB_P2P_REG18 0x18 // PBN- RW -#define SB_P2P_REG19 0x19 // SBN- RW -#define SB_P2P_REG1A 0x1A // SUBBN- RW -#define SB_P2P_REG1B 0x1B // SLTIMER- RW -#define SB_P2P_REG1C 0x1C // IOBASE- RW -#define SB_P2P_REG1D 0x1D // IOLMT- RW -#define SB_P2P_REG1E 0x1E // SSTATUS- RW -#define SB_P2P_REG20 0x20 // MBASE- RW -#define SB_P2P_REG21 0x21 -#define SB_P2P_REG22 0x22 // MLMT- RW -#define SB_P2P_REG23 0x23 -#define SB_P2P_REG24 0x24 // PMBASE- RW -#define SB_P2P_REG25 0x25 -#define SB_P2P_REG26 0x26 // PMLMT- RW -#define SB_P2P_REG27 0x27 -#define SB_P2P_REG30 0x30 // IOBU16- RW -#define SB_P2P_REG32 0x32 // IOLU16- RW -#define SB_P2P_REG34 0x34 // ECP_PTR- R -#define SB_P2P_REG3C 0x3C // INTLN- RW -#define SB_P2P_REG3D 0x3D // INTPN- R -#define SB_P2P_REG3E 0x3E // BCTRL- RW -#define SB_P2P_REG40 0x40 // CPCTRL- R/W -#define SB_P2P_REG41 0x41 // DCTRL- RW -#define SB_P2P_REG42 0x42 // CLKCTRL- R/W -#define SB_P2P_REG43 0x43 // ARCTRL- RW -#define SB_P2P_REG44 0x44 // SMLT_PERF- RW -#define SB_P2P_REG46 0x46 // PMLT_PERF- RW -#define SB_P2P_REG48 0x48 // PCDMA- RW -#define SB_P2P_REG49 0x49 // Additional Priority- Bits RW -#define SB_P2P_REG4A 0x4A // PCICLK Enable- Bits RW -#define SB_P2P_REG4B 0x4B // Misc Control RW -#define SB_P2P_REG4C 0x4C // AutoClockRun control RW -#define SB_P2P_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop -#define SB_P2P_REG54 0x54 // MSI Mapping Capability -#define SB_P2P_REG58 0x58 // Signature Register of Microsoft Rework -#define SB_P2P_REG64 0x64 // Misc Control Register -#define SB_P2P_REG65 0x65 // Misc Control Register - -#define SB_PMIO2_REG00 0x00 -#define SB_PMIO2_REG01 0x01 -#define SB_PMIO2_REG31 0x31 -#define SB_PMIO2_REG32 0x32 -#define SB_PMIO2_REG33 0x33 -#define SB_PMIO2_REG34 0x34 -#define SB_PMIO2_REG35 0x35 -#define SB_PMIO2_REG36 0x36 -#define SB_PMIO2_REG37 0x37 -#define SB_PMIO2_REG38 0x38 -#define SB_PMIO2_REG39 0x39 -#define SB_PMIO2_REG3A 0x3A -#define SB_PMIO2_REG3B 0x3B -#define SB_PMIO2_REG3C 0x3C -#define SB_PMIO2_REG3D 0x3D -#define SB_PMIO2_REG3E 0x3E -#define SB_PMIO2_REG3F 0x3F -#define SB_PMIO2_REG40 0x40 -#define SB_PMIO2_REG41 0x41 -#define SB_PMIO2_REG42 0x42 -#define SB_PMIO2_REG43 0x43 -#define SB_PMIO2_REG44 0x44 -#define SB_PMIO2_REG45 0x45 -#define SB_PMIO2_REG46 0x46 -#define SB_PMIO2_REG47 0x47 -#define SB_PMIO2_REG48 0x48 -#define SB_PMIO2_REG49 0x49 -#define SB_PMIO2_REG54 0x54 -#define SB_PMIO2_REG58 0x58 -#define SB_PMIO2_REG59 0x59 -#define SB_PMIO2_REG5A 0x5A -#define SB_PMIO2_REG5B 0x5B -#define SB_PMIO2_REG5C 0x5C -#define SB_PMIO2_REG70 0x70 -#define SB_PMIO2_REGE5 0xE5 - -#define SB_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register - - -//Bus 0 Device 0x18 Function 0 HyperTransfer -//Link Frequency/Revision Register 0x88/0xA8/0xC8/0xE8 - 32 bits. -#define HT_LINK_REG89 0x89 -#define HT_LINK_REGA9 0xA9 -#define HT_LINK_REGC9 0xC9 -#define HT_LINK_REGE9 0xE9 - -//Link Type Register 0x98/0xB8/0xD8/0xF8 - 32 bits. -#define HT_LINK_REG98 0x98 -#define HT_LINK_REGB8 0xB8 -#define HT_LINK_REGD8 0xD8 -#define HT_LINK_REGF8 0xF8 - -//Link Frequency Extension Register 0x9C/0xBC/0xDC/0xFC - 32 bits. -#define HT_LINK_REG9C 0x9C -#define HT_LINK_REGBC 0xBC -#define HT_LINK_REGDC 0xDC -#define HT_LINK_REGFC 0xFC - -//DRAM CS Base Address Register D18F2x40/x48/x50/x58 -#define DCT_REG40 0x40 -#define DCT_REG48 0x48 -#define DCT_REG50 0x50 -#define DCT_REG58 0x58 - -//DRAM Configuration Low Register D18F2x90/x91/x92/x93 -#define DCT_REG90 0x90 -#define DCT_REG91 0x91 -#define DCT_REG92 0x92 -#define DCT_REG93 0x93 - -#pragma pack(pop) - -#endif //#ifndef _AMD_SB700_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBCMN.c b/src/vendorcode/amd/cimx/sb700/SBCMN.c deleted file mode 100644 index ca2ec782c6..0000000000 --- a/src/vendorcode/amd/cimx/sb700/SBCMN.c +++ /dev/null @@ -1,572 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - - -REG8MASK sbEarlyPostByteInitTable[]={ - // SMBUS Device(Bus 0, Dev 20, Func 0) - {0x00, SMBUS_BUS_DEV_FUN, 0}, - {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make BAR registers of smbus visible. - {SB_SMBUS_REG24, 0X00, (CIMx_Version & 0xFF)}, //Program the version information - {SB_SMBUS_REG24+1, 0x00, (CIMx_Version >> 8)}, - {SB_SMBUS_REG24+2, 0x00, RC_Information}, - {SB_SMBUS_REG24+3, 0x00, Additional_Changes_Indicator}, - {SB_SMBUS_REG43, ~(UINT8)BIT3, BIT3}, //Make BAR registers of smbus invisible. - {SB_SMBUS_REGAE, ~(UINT8)(BIT6 + BIT5), BIT6 + BIT5}, //Disable Timer IRQ enhancement for proper operation of the 8254 timer. - // [6] - IoApicPicArbEn, set 1 to enable arbiter between APIC and PIC interrupts - {SB_SMBUS_REGAD, ~(UINT8)(BIT0+BIT1+BIT2+BIT4), BIT0+BIT3}, // Initialize SATA to default values, SATA Enabled, - // Combined mode enabled, SATA as primary, power saving enable - {SB_SMBUS_REGAF, 0xE3, 6 << 2}, // Set SATA Interrupt to INTG# - {SB_SMBUS_REG68, BIT3, 0 }, // First disable all usb controllers and then enable then according to setup selection - {0xFF, 0xFF, 0xFF}, - - // IDE Device(Bus 0, Dev 20, Func 1) - {0x00, IDE_BUS_DEV_FUN, 0}, - {SB_IDE_REG62+1, ~(UINT8)BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0 - // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1 - {0xFF, 0xFF, 0xFF}, - - // Azalia Device(Bus 0, Dev 20, Func 2) - {0x00, AZALIA_BUS_DEV_FUN, 0}, - {SB_AZ_REG4C, ~(UINT8)BIT0, BIT0}, - {0xFF, 0xFF, 0xFF}, - - // LPC Device(Bus 0, Dev 20, Func 3) - {0x00, LPC_BUS_DEV_FUN, 0}, - - {SB_LPC_REG40, ~(UINT8)BIT2, BIT2}, // Enabling LPC DMA Function 0x40[2] - {SB_LPC_REG78, ~(UINT8)BIT1, 00}, // Disables MSI capability - {0xFF, 0xFF, 0xFF}, - - // P2P Bridge(Bus 0, Dev 20, Func 4) - {0x00, SBP2P_BUS_DEV_FUN, 0}, - - {SB_P2P_REG64+1, 0xFF, BIT7+BIT6}, //Adjusting CLKRUN#, PCIB_PCI_Config 0x64[15]=01 - //Enabling arbiter fix, PCIB_PCI_Config 0x64[14]=01 - {SB_P2P_REG64+2, 0xFF, BIT4}, //Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20] - - {SB_P2P_REG0D, 0x00, 0x40}, //Setting Latency Timers to 0x40, Enables the PCIB to retain ownership - {SB_P2P_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted. - - {0xFF, 0xFF, 0xFF}, - - // SATA Device(Bus 0, Dev 17, Func 0) - {0x00, SATA_BUS_DEV_FUN, 0}, - {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post - {SB_SATA_REG40+3, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x40 [29] = 1 - {SB_SATA_REG48+2, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x48 [24] = 1, [21] = 1 - {SB_SATA_REG48+3, 0xff, BIT0}, - {SB_SATA_REG44 + 2, 0, 0x10}, // Program watchdog timer with 16 retries before timer time-out. - {0xFF, 0xFF, 0xFF}, -}; - - -REG8MASK sbEarlyPostPmioInitTbl[]={ - // index andmask ormask - {SB_PMIO_REG55, ~(UINT8)(BIT3+BIT4+BIT5), BIT5+BIT3}, //BIT3(PcieNative)=1b, BIT4(Pcie_Wak_Mask)=0b, BIT5(Pcie_WAK_Sci)=1b - {SB_PMIO_REG01, 0xff, BIT1}, - {SB_PMIO_REG0E, 0xff, BIT2 + BIT3}, - {SB_PMIO_REG10, 0x3E, (BIT6+BIT5+BIT3+BIT1)}, // RTC_En_En + TMR_En_En + GLB_EN_EN and clear EOS_EN + PciExpWakeDisEn - {SB_PMIO_REG61, 0xFF, 0x40}, // USB Device Support to Wakeup System from S3/S4 state, USB PME & PCI Act from NB - {SB_PMIO_REG59, 0xFC, 0x00 }, // Clear the flash controller bits BIT1:0 - {SB_PMIO_REG01, 0xFF, 0x97 }, // Clear all the status - {SB_PMIO_REG05, 0xFF, 0xFF }, - {SB_PMIO_REG06, 0xFF, 0xFF }, - {SB_PMIO_REG07, 0xFF, 0xFF }, - {SB_PMIO_REG0F, 0xFF, 0x1F }, - {SB_PMIO_REG1D, 0xFF, 0xFF }, - {SB_PMIO_REG39, 0xFF, 0xFF }, - {SB_PMIO_REG7C, ~(UINT8)(BIT5+BIT3+BIT2), BIT3+BIT2}, //Turn on BLink LED - {SB_PMIO_REG67, 0xFF, 0x06}, // C State enable, must be set in order to exercise C state - {SB_PMIO_REG68, 0x38, 0x84}, - {SB_PMIO_REG8D, 0xFF, 0x01}, // Set PM_Reg_0x8D[0] to enable PmeTurnOff/PmeMsgAck handshake to fix PCIE LAN S3/S4 wake failure - {SB_PMIO_REG84, 0xFD, BIT3+BIT0}, - {SB_PMIO_REG53, 0xFF, BIT7+BIT6}, //ACPI System Clock setting, PMIO Reg 0x53[6]=1. Our reference clock - //is either 25 or 100Mhz and so the default acpi clock is actually - //running at 12.5Mhz and so the system time will run slow. We have - //generated another internal clock which runs at 14.318Mhz which is the - //correct frequency. We should set this bit to turn on this feature PMIO_REG53[6]=1 - //PCI Clock Period, PM_IO 0x53 [7] = 1. By setting this, PCI clock period - //increase to 30.8 ns. - {SB_PMIO_REG95, ~(UINT8)(BIT2+BIT1+BIT0), BIT2+BIT1}, //USB Advanced Sleep Control, Enables USB EHCI controller - //to sleep for 6 uframes in stead of the standard 10us to - //improve power saving. - {SB_PMIO_REGD7, 0xFF, BIT6+BIT1}, - -}; - - -// commonInitEarlyBoot - set /SMBUS/ACPI/IDE/LPC/PCIB. This settings should be done during S3 resume also -void commonInitEarlyBoot(AMDSBCFG* pConfig) { - UINT16 dwTempVar; - CPUID_DATA CpuId; - CPUID_DATA CpuId_Brand; - UINT8 dbValue; - UINT32 ddValue; - UINT8 Family, Model, Stepping; - - TRACE((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n")); - CpuidRead (0x01, &CpuId); - CpuidRead (0x80000001, &CpuId_Brand); //BrandID - - //Early post initialization of pci config space - programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbEarlyPostByteInitTable[0]), sizeof(sbEarlyPostByteInitTable)/sizeof(REG8MASK) ); - - // RPR 5.5 Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST. - RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4); - - - #if 0 //KZ [083011]-It's used wrong BIOS SIZE for coreboot. - //For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before - //changing it. - ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar); - if ( (dwTempVar == 0x08) || (dwTempVar == 0x00)) - RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint8 | S3_SAVE, 0, 0x0E);// Change the 1Mb below ROM decoding range to 0xE0000 to 0xFFFFF - #endif - - if (pConfig->AzaliaController == 1) - RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0); - else - RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); - - //Disable or Enable PCI Clks based on input - RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG42, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT5+BIT4+BIT3+BIT2), ((pConfig->PciClks) & 0x0F) << 2 ); - RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4A, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), ((pConfig->PciClks) >> 4) | ((pConfig->PciClk5) << 1) ); - ReadPMIO(SB_PMIO_REG2C, AccWidthUint16, &dwTempVar); // Read Arbiter address, Arbiter address is in PMIO 2Ch - RWIO(dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter - - abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers - // Set LDTSTP# duration to 10us for HydraD CPU model 8, 9 or A; or when HT link is 200MHz; or Family15 Orochi CPU C32/G34 package - ddValue = CpuId.REG_EAX & 0x00FF00F0; - dbValue = 1; - - if((CpuId.REG_EAX & 0x00F00F00) == 0x00600F00) { - if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) { - //Orochi processor G34/C32, set to 10us - dbValue = 10; - } - else { - // Orochi processor AM3, set to 5us - dbValue = 5; - } - } - - if ((pConfig->AnyHT200MhzLink) || (ddValue == 0x100080) || (ddValue == 0x100090) || (ddValue == 0x1000A0)) { - //any kind of CPU run HT at 200Mhz , or HydraD CPU model 8, 9 or A, set to 10us - dbValue = 10; - } - - - RWPMIO(SB_PMIO_REG8B, AccWidthUint8 | S3_SAVE, 0x00, dbValue); - - // Enable/Disable watchdog timer - RWPMIO(SB_PMIO_REG69, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, (UINT8)(!pConfig->WatchDogTimerEnable)); - - // Per SB700/SP5100 RPR 2.5 - // - // Enable C1e stutter timer for any system with chip revision >= A14 - // Set SMBUS:0x5c[22:16] = 16 -- Set amount of idle time to 16ms - // - - if (getRevisionID() >= SB700_A14) { - dwTempVar = 0x0010; - - // Set PMIO:0xcb[5] = 1 -- AutoStutterTimerEn, set 1 to enable - // Set PMIO:0xcb[6] = 1 -- AutoStutterTimeSel, 1=1ms timer tick increment; 0=2us increment - RWPMIO(SB_PMIO_REGCB, AccWidthUint8 | S3_SAVE, 0xff, BIT6 + BIT5); - - Family = (UINT8)((CpuId.REG_EAX & 0x00ff0000)>> 16); - Model = (UINT8)((CpuId.REG_EAX & 0x000000f0)>> 4); - Stepping = (UINT8) (CpuId.REG_EAX & 0x0000000f); - - // For Server system (SP5100) with CPU type = Family 10h with LS2 mode enabled: - // Model=6 && Stepping=2 || Model=(4I5|6) && Stepping >=3 || Model=(8|9) && Stepping >= 1 || Model Ah - // Set SMBUS:0x5c[22:16] = 20 -- Set amount of idle time to 20ms - if (IsLs2Mode() && (Family == 0x10)) { - switch( Model ){ - case 0x4: - case 0x5: - if( Stepping >= 3 ) dwTempVar = 0x14; - break; - case 0x6: - if( Stepping >= 2 ) dwTempVar = 0x14; - break; - case 0x8: - if( Stepping >= 1 ) dwTempVar = 0x14; - break; - case 0x9: - if( Stepping >= 1 ) dwTempVar = 0x14; - break; - case 0xA: - dwTempVar = 0x14; - break; - } - } - // Set SMBUS:0x5c[7] = 1 -- CheckC3, set 1 to check for C3 state - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG5C, AccWidthUint32 | S3_SAVE, ~(0x7F << 16), (dwTempVar << 16) + BIT7); - } - - //Message-Triggered C1E is not supported in Family 10h G34r1 HY-D0 (0x00100F90) and Family 10h C32 HY-D0 (0x00100F80) processor. - ddValue = CpuId.REG_EAX; - if ((getRevisionID() == SB700_A15) && (pConfig->MTC1e == CIMX_OPTION_ENABLED) && (ddValue != 0x00100F90) && (ddValue != 0x00100F80)) { - // - // MTC1e: For A15 (server only) - The settings here borrow the existing legacy ACPI BM_STS and BM_RLD bits as a - // mechanism to break out from C1e under a non-OS controlled C3 state. Under this scheme, the logic will automatically - // clear the BM_STS bit whenever it enters C1e state. Whenever BM_REQ#/IDLE_EXIT# is detected, it will cause the - // BM_STS bit to be set and therefore causing the C state logic to exit. - // - // Set BMReqEnable (SMBUS:0x64[5]=1) to enable the pin as BM_REQ#/IDLE_EXIT# to the C state logic - // Set CheckOwnReq (SMBUS:0x64[4]=0) to force IDLE_EXIT# to set BM_STS and wake from C3 - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, 0xEF, BIT5); - - // Set PCI_Active_enable (PMIO:0x61[2]=1), the secondary enable bit for SB to monitor BM_REQ#/IDLE_EXIT# - RWPMIO(SB_PMIO_REG61, AccWidthUint8 | S3_SAVE, 0xff, BIT2); - - // Set auto_bm_rld (PMIO:0x9a[4]=1) so that assertion on BM_REQ#/IDLE_EXIT# pin will cause C state logic to break out from C1e - // Set auto_clr_bm_sts (PMIO:0x9a[5]=1) will cause the C state logic to automatically clear the BM_STS bit whenever it sees a C1e entry - RWPMIO(SB_PMIO_REG9A, AccWidthUint8 | S3_SAVE, 0xff, BIT5 + BIT4); - - - // MTC1e: The logic basically counts the number of HALT_ENTER messages. When it has received the number of HALT_ENTER - // messages equal to NumOfCpu (PMIO:0xc9[3:0]), it will generate an internal C1e command to the C state logic. - // The count increments when it sees HALT_ENTER message after it has generated the C1e command, and it treats the - // HALT_EXIT message as a break event. - // - // Set ServerCEn - RWPMIO(SB_PMIO_REGBB, AccWidthUint8 | S3_SAVE, 0xFF, BIT7); - - // Enable counting HALT - // PMIO:0xc9[4] = CountHaltMsgEn - // PMIO:0xc9[3:0] = NumOfCpu, set to 1 since CPU logic will coordinate among cores and only generate one HALT message - RWPMIO(SB_PMIO_REGC9, AccWidthUint8 | S3_SAVE, 0xE0, BIT4 + 1); - } - - c3PopupSetting(pConfig); - - TRACE((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n")); -} - - -void commonInitEarlyPost(AMDSBCFG* pConfig){ - //early post initialization of pmio space - programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbEarlyPostPmioInitTbl[0]), (sizeof(sbEarlyPostPmioInitTbl)/sizeof(REG8MASK)) ); - CallBackToOEM(PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig); -} - - -// AB-Link Configuration Table -ABTBLENTRY abTblEntry600[]={ - // Enabling Downstream Posted Transactions to Pass Non-Posted Transactions for the K8 Platform ABCFG 0x10090[8] = 1 - // ABCFG 0x10090 [16] = 1, ensures the SMI# message to be sent before the IO command is completed. The ordering of - // SMI# and IO is important for the IO trap to work properly. - {ABCFG,SB_AB_REG10090 ,BIT16+BIT8 ,BIT16+BIT8 }, - // Enabling UpStream DMA Access AXCFG: 0x04[2]=1 - {AXCFG,SB_AB_REG04 ,BIT2 ,BIT2 }, - // Setting B-Link Prefetch Mode ABCFG 0x80 [17] = 1 ABCFG 0x80 [18] = 1 - {ABCFG,SB_AB_REG80 ,BIT17+BIT18 ,BIT17+BIT18 }, - // Disable B-Link client's credit variable in downstream arbitration equation (for All Revisions) - // ABCFG 0x9C[0] = 1 Disable credit variable in downstream arbitration equation - // Enabling Additional Address Bits Checking in Downstream Register Programming - // ABCFG 0x9C[1] = 1 - {ABCFG,SB_AB_REG9C ,BIT8+BIT1+BIT0 ,BIT8+BIT1+BIT0 }, - // Enabling IDE/PCIB Prefetch for Performance Enhancement - // IDE prefetch ABCFG 0x10060 [17] = 1 ABCFG 0x10064 [17] = 1 - // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1 - {ABCFG,SB_AB_REG10060 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable - {ABCFG,SB_AB_REG10064 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable - // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1 - // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20] - {ABCFG,SB_AB_REG94 ,BIT20 ,BIT20+0x00FEE }, - // Programming cycle delay for AB and BIF clock gating - // Enabling AB and BIF Clock Gating - // Enabling AB Int_Arbiter Enhancement - // Enabling Requester ID - {ABCFG,SB_AB_REG10054, 0x00FFFFFF , 0x010407FF }, - {ABCFG,SB_AB_REG98 , 0xFFFF00FF , 0x00014700 }, // Enable the requestor ID for upstream traffic ABCFG 0x98[16]=1 -// {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x01040000 }, - {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x00040000 }, - - {ABCFG,0,0,-1}, // This dummy entry is to clear ab index - {-1, -1, -1, -1 }, -}; - - -// AB-Link Configuration Table -ABTBLENTRY abTblForA15[]={ - - //SMI Reordering fix - {ABCFG, SB_AB_REG90 ,BIT21 , BIT21 }, - {ABCFG, SB_AB_REG9C ,BIT15+BIT9+BIT5 ,BIT15+BIT9+BIT5}, - - //Posted pass NP Downstream feature - {AX_INDXC, SB_AB_REG02, BIT9 ,BIT9 }, - {ABCFG, SB_AB_REG9C, BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6 , BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6}, - {ABCFG, SB_AB_REG1009C, BIT5+BIT4 , BIT5+BIT4}, - - //Posted pass NP upstream feature - {ABCFG, SB_AB_REG58, BIT15+BIT14+BIT13+BIT12+BIT11, BIT15+BIT14+BIT13+BIT11}, - - //64 bit Non-posted memory write support - {AX_INDXC, SB_AB_REG02, BIT10 ,BIT10 }, - - {ABCFG, SB_AB_REG10090, BIT12+BIT11+BIT10+BIT9 , BIT12+BIT11+BIT10+BIT9}, - - {ABCFG,0,0,-1}, // This dummy entry is to clear ab index - {-1, -1, -1, -1 }, -}; - - -// abLinkInitBeforePciEnum - Set ABCFG registers -void abLinkInitBeforePciEnum(AMDSBCFG* pConfig){ - ABTBLENTRY *pAbTblPtr; - - // disable PMIO decoding when AB is set - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, 0); - - pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblEntry600[0]); - abcfgTbl(pAbTblPtr); - - if (getRevisionID() > SB700_A11){ - //Enable OHCI Prefetch - writeAlink( (SB_AB_REG80 | (ABCFG << 30)), (readAlink((SB_AB_REG80 | (ABCFG << 30)))) | BIT0); - //Register bit to maintain correct ordering of SMI and IO write completion - writeAlink( (SB_AB_REG8C | (ABCFG << 30)), (readAlink((SB_AB_REG8C | (ABCFG << 30)))) | BIT8); - } - - if (getRevisionID() >= SB700_A14){ - //Enable fix for TT SB01345 - writeAlink( (SB_AB_REG90 | (ABCFG << 30)), (readAlink((SB_AB_REG90 | (ABCFG << 30)))) | BIT17); - //Disable IO Write and SMI ordering enhancement - writeAlink( (SB_AB_REG9C | (ABCFG << 30)), (readAlink((SB_AB_REG9C | (ABCFG << 30)))) & (0xFFFFFEFF)); - } - - if (getRevisionID() >= SB700_A15) { - pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblForA15[0]); - abcfgTbl(pAbTblPtr); - } - - - // enable pmio decoding after ab is configured - // or BYTE PTR es:[ebp+SMBUS_BUS_DEV_FUN shl 12 + SB_SMBUS_REG64], BIT2 - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2); -} - - -void abcfgTbl(ABTBLENTRY* pABTbl){ - UINT32 ddValue; - - while ((pABTbl->regType) != 0xFF){ - TRACE((DMSG_SB_TRACE, "RegType: %X, RegNumber:%X, AndMask=%X, OrMask=%X \n",pABTbl->regType , pABTbl->regIndex, pABTbl->regMask, pABTbl->regData)); - if (pABTbl->regType > AX_INDXP){ - ddValue = pABTbl->regIndex | (pABTbl->regType << 30); - writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData); - } - else{ - ddValue = 0x30 | (pABTbl->regType << 30); - writeAlink(ddValue, pABTbl->regIndex); - ddValue = 0x34 | (pABTbl->regType << 30); - writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData); - } - ++pABTbl; - } - - //Clear ALink Access Index - ddValue = 0; - WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue); - TRACE((DMSG_SB_TRACE, "Exiting abcfgTbl\n")); -} - - -// programSubSystemIDs - Config Subsystem ID for all SB devices. -void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions){ - UINT32 ddTempVar; - UINT16 dwDeviceId; - - RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci0Ssid); - RWPCI((USB1_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci1Ssid); - RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci2Ssid); - RWPCI((USB2_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci3Ssid); - RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci4Ssid); - - RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci0Ssid); - RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci1Ssid); - - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->SmbusSsid); - RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->IdeSsid); - RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->LpcSsid); - RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->AzaliaSsid); - - ddTempVar = pStaticOptions->SataIDESsid; - if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass)== IDE_TO_AHCI_MODE) ) - ddTempVar = pStaticOptions->SataAHCISsid; - - ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId); - if ((pConfig->SataClass) == RAID_MODE){ - ddTempVar = pStaticOptions->SataRAIDSsid; - if (dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) - ddTempVar = pStaticOptions->SataRAID5Ssid; - } - - if ( ((pConfig->SataClass) == AMD_AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AMD_AHCI_MODE) ) { - ddTempVar = pStaticOptions->SataAHCISsid; - } - RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar); -} - -void commonInitLateBoot(AMDSBCFG* pConfig){ - UINT8 dbValue; - UINT32 ddVar; - - // We need to do the following setting in late post also because some bios core pci enumeration changes these values - // programmed during early post. - // RPR 4.5 Master Latency Timer - // Master Latency Timer PCIB_PCI_config 0x0D/0x1B = 0x40 - // Enables the PCIB to retain ownership of the bus on the - // Primary side and on the Secondary side when GNT# is deasserted. - //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG0D], 40h - //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG1B], 40h - dbValue = 0x40; - WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG0D, AccWidthUint8, &dbValue); - WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG1B, AccWidthUint8, &dbValue); - - //SB P2P AutoClock control settings. - ddVar = (pConfig->PcibAutoClkCtrlLow) | (pConfig->PcibAutoClkCtrlLow); - WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4C, AccWidthUint32, &ddVar); - ddVar = (pConfig->PcibClkStopOverride); - RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6)); - - if (pConfig->MobilePowerSavings){ - //If RTC clock is not driven to any chip, it should be shut-off. If system uses external RTC, then SB needs to - //drive out RTC clk to external RTC chip. If system uses internal RTC, then this clk can be shut off. - RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, (pConfig->ExternalRTCClock)<<4); - if (!getClockMode()){ - if (!(pConfig->UsbIntClock) ){ - //If the external clock is used, the second PLL should be shut down - RWPMIO(SB_PMIO_REGD0, AccWidthUint8, 0xFF, BIT0); - // If external clock mode is used, the 25Mhz oscillator buffer can be turned-off by setting PMIO 0xD4[7]=1 - RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT7); - //Disable unused clocks - RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x7E); - } - } - writeAlink(0x30, SB_AB_REG40); - writeAlink(0x34, ((readAlink(0x34)) & 0xFFFF0000) | 0x008A); - - } - else{ - //Don't shutoff RTC clock - RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, 0); - //Dont disable second PLL - RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); - //Enable the 25Mhz oscillator - RWPMIO(SB_PMIO_REGD4, AccWidthUint8, ~(UINT32)BIT7, 0); - RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x00); - } -} - - -void -hpetInit (AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions) -{ - DESCRIPTION_HEADER* pHpetTable; - - if (pConfig->HpetTimer == 1) { - UINT8 dbTemp; - - RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT7); - // Program the HPET BAR address - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGB4, AccWidthUint32 | S3_SAVE, 0, pStaticOptions->HpetBase); - - // Enable HPET MMIO decoding: SMBUS:0x43[4] = 1 - // Enable HPET MSI support only when HpetMsiDis == 0 - dbTemp = (pConfig->HpetMsiDis)? BIT4 : BIT7 + BIT6 + BIT5 + BIT4; - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, dbTemp); - // Program HPET default clock period - if (getRevisionID() >= SB700_A13) { - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG34, AccWidthUint32 | S3_SAVE, 0x00, 0x429B17E); - } - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); - // Enable High Precision Event Timer (also called Multimedia Timer) interrupt - RWPCI((SMBUS_BUS_DEV_FUN << 16) + (SB_SMBUS_REG64+1), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2); - } - else { - if (!(pConfig->S3Resume)) { -// pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable('TEPH'); - pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable(Int32FromChar ('T', 'E', 'P', 'H')); - if (pHpetTable != NULL) { -// pHpetTable->Signature = 'HPET'; - pHpetTable->Signature = Int32FromChar ('T', 'E', 'P', 'H'); - } - } - } -} - - -void c3PopupSetting(AMDSBCFG* pConfig){ - UINT8 dbTemp; - CPUID_DATA CpuId; - - CpuidRead (0x01, &CpuId); - //RPR 2.3 C-State and VID/FID Change - dbTemp = GetNumberOfCpuCores(); - if (dbTemp > 1){ - //PM_IO 0x9A[5]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated. - //PM_IO 0x9A[4]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD - //PM_IO 0x9A[2]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert - //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time. - RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT5+BIT4+BIT2); - } - - //SB700 needs to changed for RD790 support - //PM_IO 0x8F [4] = 0 for system with RS690 - //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link. - //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle. - //PM_IO 0x8F[5]=1, Ignore BM_STS_SET message from NB - RWPMIO(SB_PMIO_REG8F, AccWidthUint8, ~(UINT32)(BIT5+BIT4), BIT5); - - //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that - //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also - //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT - //link is disconnected. - //Increase LDTSTOP Deassertion time for SP5100 to 20us, SB700 remains the same - dbTemp = (IsServer())? 0x14 : 0x10; - RWPMIO(SB_PMIO_REG88, AccWidthUint8, 0x00, dbTemp); - - //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The - //delay will allow USB DMA to go on in a continous manner - RWPMIO(SB_PMIO_REG89, AccWidthUint8, 0x00, 0x10); - - //Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time - RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xFF, BIT7); - -} - diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c deleted file mode 100644 index 130dbc4235..0000000000 --- a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c +++ /dev/null @@ -1,108 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - -UINT8 isEcPresent(){ - UINT8 dbFlag; - UINT16 dwVar0; - - //Read the EC configuration register base address from LPCCfg_A4[15:1] - //Write 0x5A to the EC config index register to unlock the access - //Write 0x20 to the EC config index register to select the device ID register - //Read the value of device ID register from the EC config data register - //If the value read is 0xB7, then EC is enabled. - //Write 0xA5 to re-lock the EC config index register if EC is enabled. - - ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwVar0); - dwVar0 &= 0xFFFE; - RWIO(dwVar0, AccWidthUint8, 0, 0x5A); - RWIO(dwVar0, AccWidthUint8, 0, 0x20); - ReadIO(dwVar0+1, AccWidthUint8, &dbFlag); - RWIO(dwVar0, AccWidthUint8, 0, 0xA5); - - return ( dbFlag == 0xB7); -} - -void -getSbInformation ( -SB_INFORMATION *sbInfo){ - UINT16 dwDevId; - UINT8 dbRev; - - ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16 | S3_SAVE, &dwDevId); - ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08, AccWidthUint8 | S3_SAVE, &dbRev); - sbInfo->sbModelMask = SB_MODEL_UNKNOWN; - if ( (dwDevId == SB7XX_DEVICE_ID) && (dbRev <= SB_Rev_Sb7xx_A14) ){ - sbInfo->sbModelMask |= SB_MODEL_SB700; - sbInfo->sbModelMask |= SB_MODEL_SR5690; - sbInfo->sbRev = dbRev; - ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, &dbRev); - if (dbRev & 01) - sbInfo->sbModelMask |= SB_MODEL_SB750; - if (isEcPresent()) - sbInfo->sbModelMask |= SB_MODEL_SB710; - return; - } -} - - -SB_CAPABILITY_SETTING -getSbCapability ( -SB_CAPABILITY_ITEM sbCapabilityItem -) -{ - SB_CAPABILITY_SETTING sbCapSetting=SB_UNKNOWN; - UINT32 ddTemp0; - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00); - ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); - - if (sbCapabilityItem < Sb_Unknown_Capability) - sbCapSetting = ((ddTemp0 >> (sbCapabilityItem << 1) ) & 0x03); - - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); - return sbCapSetting; -} - - -void -setSbCapability ( -SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting -) -{ - UINT32 ddTemp0; - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00); - ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); - if ( (sbCapabilityItem < Sb_Unknown_Capability) & (sbCapSetting < Sb_Cap_Setting_Unknown) ) - ddTemp0 = (ddTemp0 & ~(0x03 << (sbCapabilityItem << 1))) | ( (sbCapSetting & 0x03) << (sbCapabilityItem << 1)); - WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); -} diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h deleted file mode 100644 index e737bc971e..0000000000 --- a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h +++ /dev/null @@ -1,89 +0,0 @@ -/*;******************************************************************************** -; -; Copyright (C) 2012 Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;*********************************************************************************/ - -#ifndef _AMD_SBLIB_H_ -#define _AMD_SBLIB_H_ - -//SB7xx Family -#define SB7xx_DEVICE_ID 0x4385 -#define SB700 0x00 -#define SB750 0x01 -#define SB710 0x02 - -//SB800 Family -#define SB800 0x10 - -#define SB_UNKNOWN 0xFF - -//SB700 Revision IDs -#define SB700_A11 0x39 -#define SB700_A12 0x3A -#define SB700_A13 0x3B -#define SB700_A14 0x3C - -#define SB_Rev_Sb7xx_A11 0x39 -#define SB_Rev_Sb7xx_A12 0x3A -#define SB_Rev_Sb7xx_A13 0x3B -#define SB_Rev_Sb7xx_A14 0x3C - - -typedef enum { - Sb_Raid0_1_Capability, /// - Sb_Raid5_Capability, /// - Sb_Ahci_Capability, /// - Sb_Unknown_Capability -} SB_CAPABILITY_ITEM; - - -typedef enum { - Sb_Cap_Setting_Auto, - Sb_Cap_Setting_Enabled, - Sb_Cap_Setting_Disabled, - Sb_Cap_Setting_Unknown -} SB_CAPABILITY_SETTING; - - -#define SB_MODEL_SB700 BIT0 -#define SB_MODEL_SB750 BIT1 -#define SB_MODEL_SB710 BIT2 -#define SB_MODEL_SR5690 BIT3 -#define SB_MODEL_UNKNOWN BIT31 - -typedef struct -{ - UINT32 sbModelMask; - UINT8 sbRev; -}SB_INFORMATION; - - -void getSbInformation (SB_INFORMATION *sbInfo); -SB_CAPABILITY_SETTING getSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem); -void setSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting); - -#endif //#ifndef _AMD_SBLIB_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBDEF.h b/src/vendorcode/amd/cimx/sb700/SBDEF.h deleted file mode 100644 index 5ffd34e7da..0000000000 --- a/src/vendorcode/amd/cimx/sb700/SBDEF.h +++ /dev/null @@ -1,164 +0,0 @@ -/*;******************************************************************************** -; -; Copyright (C) 2012 Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;*********************************************************************************/ - -#ifndef _AMD_SBDEF_H_ -#define _AMD_SBDEF_H_ - -//AMD Library Routines - -UINT64 -MsrRead ( - IN UINT32 MsrAddress - ); - -VOID -MsrWrite ( - IN UINT32 MsrAddress, - IN UINT64 Value - ); - -void ReadIO(UINT16 Address, UINT8 OpFlag, void *Value); -void WriteIO(UINT16 Address, UINT8 OpFlag, void *Value); -void ReadPCI(UINT32 Address, UINT8 OpFlag, void *Value); -void WritePCI(UINT32 Address,UINT8 OpFlag, void *Value); -void RWPCI(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data); -void ReadIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,void* Value); -void WriteIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,void* Value); -void RWIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,UINT32 Mask,UINT32 Data); -void RWIO (UINT16 Address, UINT8 OpFlag, UINT32 Mask, UINT32 Data); -void ReadMEM(UINTN Address,UINT8 OpFlag, void* Value); -void WriteMEM(UINTN Address,UINT8 OpFlag, void* Value); -void RWMEM(UINTN Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data); -UINT32 IsFamily10(void); -UINT64 ReadMSR(UINT32 Address); -void WriteMSR(UINT32 Address,UINT64 Value); -void RWMSR(UINT32 Address, UINT64 Mask, UINT64 Value); -void Stall(UINT32 uSec); -void Reset(void); -CIM_STATUS RWSMBUSBlock(UINT8 Controller, UINT8 Address, UINT8 Offset, UINT8 BufferSize, UINT8* BufferPrt); -void InitSerialOut(void); -void ReadPMIO(UINT8 Address, UINT8 OpFlag, void* Value); -void WritePMIO(UINT8 Address, UINT8 OpFlag, void* Value); -void RWPMIO(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask); -void ReadPMIO2(UINT8 Address, UINT8 OpFlag, void* Value); -void WritePMIO2(UINT8 Address, UINT8 OpFlag, void* Value); -void RWPMIO2(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask); -void outPort80(UINT32 pcode); -UINT8 GetNumberOfCpuCores(void); -UINT8 ReadNumberOfCpuCores(void); -UINT8 GetByteSum(void* pData, UINT32 Length); -UINT32 readAlink(UINT32 Index); -void writeAlink(UINT32 Index,UINT32 Data); - -//---------------------------------------------------------------------------------------------- -//---------------------------------------------------------------------------------------------- -void azaliaInitAfterPciEnum (AMDSBCFG* pConfig); - -void SendBytePort(UINT8 Data); -void SendStringPort(char* pstr); -void ItoA(UINT32 Value,int Radix,char* pstr); -AMDSBCFG* getConfigPointer(void); -void saveConfigPointer(AMDSBCFG* pConfig); - - -UINT32 GetFixUp(void); - -void sataInitAfterPciEnum(AMDSBCFG* pConfig); -void sataInitBeforePciEnum(AMDSBCFG* pConfig); -void sataInitLatePost(AMDSBCFG* pConfig); -void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5); -void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5); -void forceOOB(UINT32 ddBar5); -void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5); -void restrictSataCapabilities(AMDSBCFG* pConfig); - - -void commonInitEarlyBoot(AMDSBCFG* pConfig); -void commonInitEarlyPost(AMDSBCFG* pConfig); -void setRevisionID(void); -UINT8 getRevisionID(void); -UINT8 IsServer (void); -UINT8 IsLs2Mode (void); -void abLinkInitBeforePciEnum(AMDSBCFG* pConfig); -void abcfgTbl(ABTBLENTRY* pABTbl); -void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions); -void commonInitLateBoot(AMDSBCFG* pConfig); -void hpetInit(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions); -void c3PopupSetting(AMDSBCFG* pConfig); - -void sbBeforePciInit (AMDSBCFG* pConfig); -void sbAfterPciInit(AMDSBCFG* pConfig); -void sbLatePost(AMDSBCFG* pConfig); -void sbBeforePciRestoreInit(AMDSBCFG* pConfig); -void sbAfterPciRestoreInit(AMDSBCFG* pConfig); -void sbSmmAcpiOn(AMDSBCFG* pConfig); -UINT32 GetPciebase(void); -UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig); -void sbSmmService(AMDSBCFG* pConfig); -void softwareSMIservice(void); - -void sbPowerOnInit (AMDSBCFG *pConfig); -void programPciByteTable(REG8MASK* pPciByteTable, UINT16 dwTableSize); -void programPmioByteTable(REG8MASK* pPmioByteTable, UINT16 dwTableSize); -UINT8 getClockMode(void); -UINT16 readStrapStatus (void); - -void usbInitBeforePciEnum(AMDSBCFG* pConfig); -void usbInitAfterPciInit(AMDSBCFG* pConfig); -void usbInitMidPost(AMDSBCFG* pConfig); -void programOhciMmioForEmulation(void); - -void fcInitBeforePciEnum(AMDSBCFG* pConfig); - -unsigned char ReadIo8 (IN unsigned short Address); -unsigned short ReadIo16 (IN unsigned short Address); -unsigned int ReadIo32 (IN unsigned short Address); -void WriteIo8 (IN unsigned short Address, IN unsigned char Data); -void WriteIo16 (IN unsigned short Address, IN unsigned short Data); -void WriteIo32 (IN unsigned short Address, IN unsigned int Data); -unsigned long long ReadTSC (void); -void CpuidRead (IN unsigned int Func, IN OUT CPUID_DATA* Data); - -#ifndef NO_EC_SUPPORT -void EnterEcConfig(void); -void ExitEcConfig(void); -void ReadEC8(UINT8 Address, UINT8* Value); -void WriteEC8(UINT8 Address, UINT8* Value); -void RWEC8(UINT8 Address, UINT8 AndMask, UINT8 OrMask); -void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG *pConfig); -void ecInitBeforePciEnum(AMDSBCFG* pConfig); -void ecInitLatePost(AMDSBCFG* pConfig); -#endif -UINT8 isEcPresent(void); - -void DispatcherEntry(void *pConfig); -AGESA_STATUS AmdSbDispatcher(void *pConfig); -void AMDFamily15CpuLdtStopReq(void); - -#endif //#ifndef _AMD_SBDEF_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBMAIN.c b/src/vendorcode/amd/cimx/sb700/SBMAIN.c deleted file mode 100644 index 45f08df7de..0000000000 --- a/src/vendorcode/amd/cimx/sb700/SBMAIN.c +++ /dev/null @@ -1,285 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - -BUILDPARAM DfltStaticOptions={ - BIOS_SIZE, // BIOS Size - LEGACY_FREE, // Legacy Free Option - 0x00, // Dummy space holder - - 0x00, // ECKbd disable/enable - 0x00, // EcChannel0 disable/enable - 0x00, // Dummy space holder1 - - SMBUS0_BASE_ADDRESS, // Smbus Base Address; - SMBUS1_BASE_ADDRESS, // Smbus Base Address; - SIO_PME_BASE_ADDRESS, // SIO PME Base Address - WATCHDOG_TIMER_BASE_ADDRESS, // Watchdog Timer Base Address - SPI_BASE_ADDRESS, - - PM1_EVT_BLK_ADDRESS, // AcpiPm1EvtBlkAddr; - PM1_CNT_BLK_ADDRESS, // AcpiPm1CntBlkAddr; - PM1_TMR_BLK_ADDRESS, // AcpiPmTmrBlkAddr; - CPU_CNT_BLK_ADDRESS, // CpuControlBlkAddr; - GPE0_BLK_ADDRESS, // AcpiGpe0BlkAddr; - SMI_CMD_PORT, // SmiCmdPortAddr; - ACPI_PMA_CNT_BLK_ADDRESS, // AcpiPmaCntBlkAddr; - - EC_LDN5_MAILBOX_ADDRESS, - EC_LDN5_IRQ, - EC_LDN9_MAILBOX_ADDRESS, // EC LDN9 Mailbox address - RESERVED_VALUE, - RESERVED_VALUE, - RESERVED_VALUE, - RESERVED_VALUE, - - HPET_BASE_ADDRESS, // HPET Base address - - SATA_IDE_MODE_SSID, - SATA_RAID_MODE_SSID, - SATA_RAID5_MODE_SSID, - SATA_AHCI_SSID, - - OHCI0_SSID, - OHCI1_SSID, - EHCI0_SSID, - OHCI2_SSID, - OHCI3_SSID, - EHCI1_SSID, - OHCI4_SSID, - SMBUS_SSID, - IDE_SSID, - AZALIA_SSID, - LPC_SSID, - P2P_SSID, -}; - - -/********************************************************************************* -* -* Routine Description: Config SB Before PCI INIT -* -* Arguments: -* -* pConfig - SBconfiguration -* -* Returns: -* -* void -* -**********************************************************************************/ -void sbBeforePciInit (AMDSBCFG* pConfig){ - BUILDPARAM *pStaticOptions; - - pStaticOptions = &pConfig->BuildParameters; - TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n")); - commonInitEarlyBoot(pConfig); - commonInitEarlyPost(pConfig); -#ifndef NO_EC_SUPPORT - ecInitBeforePciEnum(pConfig); -#endif - usbInitBeforePciEnum(pConfig); // USB POST TIME Only - fcInitBeforePciEnum(pConfig); // Preinit flash controller - sataInitBeforePciEnum(pConfig); // Init SATA class code and PHY - programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID - - TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n")); -} - - -/********************************************************************************* -* -* Routine Description: Config SB After PCI INIT -* -* Arguments: -* -* pConfig - SBconfiguration -* -* Returns: void -* -* Reference: atiSbAfterPciInit -* -**********************************************************************************/ -void sbAfterPciInit(AMDSBCFG* pConfig){ - BUILDPARAM *pStaticOptions; - - TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n")); - - pStaticOptions = &pConfig->BuildParameters; - usbInitMidPost(pConfig); //usb initialization which is required only during post - usbInitAfterPciInit(pConfig); // Init USB MMIO - sataInitAfterPciEnum(pConfig); // SATA port enumeration - azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio - - TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n")); -} - - -/********************************************************************************* -* -* Routine Description: Config SB during late POST -* -* Arguments: -* -* pConfig - SBconfiguration -* -* Returns: void -* -* Reference: atiSbLatePost -* -**********************************************************************************/ -void sbLatePost(AMDSBCFG* pConfig){ - UINT16 dwVar; - BUILDPARAM *pStaticOptions; - pStaticOptions = &pConfig->BuildParameters; - TRACE((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n")); - ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16, &dwVar); - if (dwVar != SB7XX_DEVICE_ID){ - // Display message that the SB is wrong and stop the system - TRACE((DMSG_SB_TRACE, "Current system does not have SB700 chipset. Stopping\n")); - for(;;); - } - commonInitLateBoot(pConfig); - sataInitLatePost(pConfig); - hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit -#ifndef NO_EC_SUPPORT - ecInitLatePost(pConfig); -#endif -} - -/********************************************************************************* -* -* Routine Description: Config SB before ACPI S3 resume PCI config device restore -* -* Arguments: -* -* pConfig - SBconfiguration -* -* Returns: void -* -* Reference: AtiSbBfPciRestore -* -**********************************************************************************/ -void sbBeforePciRestoreInit(AMDSBCFG* pConfig){ - BUILDPARAM *pStaticOptions; - - TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n")); - - pConfig->S3Resume = 1; - - pStaticOptions = &pConfig->BuildParameters; - commonInitEarlyBoot(pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB - abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers - usbInitBeforePciEnum(pConfig); // USB POST TIME Only - fcInitBeforePciEnum(pConfig); // Preinit flash controller - sataInitBeforePciEnum(pConfig); - programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID -} - - -/********************************************************************************* -* -* Routine Description: Config SB after ACPI S3 resume PCI config device restore -* -* Arguments: -* -* pConfig - SBconfiguration -* -* Returns: void -* -* Reference: AtiSbAfPciRestore -* -**********************************************************************************/ -void sbAfterPciRestoreInit(AMDSBCFG* pConfig){ - BUILDPARAM *pStaticOptions; - - pConfig->S3Resume = 1; - - pStaticOptions = &pConfig->BuildParameters; - TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n")); - - commonInitLateBoot(pConfig); - sataInitAfterPciEnum(pConfig); - azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio - hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit - sataInitLatePost(pConfig); - sbSmmAcpiOn(pConfig); -} - - -/*++ - -Routine Description: - - SB config hook during ACPI_ON - -Arguments: - - pConfig - SBconfiguration - -Returns: - - void - ---*/ - -void sbSmmAcpiOn(AMDSBCFG* pConfig){ - UINT32 ddBar5; - UINT8 dbPort; - - //RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0); - if (getRevisionID() >= SB700_A13) - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); //Enable Legacy DMA prefetch enhancement - - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0); - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8| S3_SAVE, ~(UINT32)BIT7, 0); - programOhciMmioForEmulation(); - - // For IDE_TO_AHCI_MODE and IDE_TO_AMD_AHCI_MODE, clear Interrupt Status register for all ports - ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); - if ((pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){ - for (dbPort = 0; dbPort <= 5; dbPort++) { - RWMEM(ddBar5 + SB_SATA_BAR5_REG110 + dbPort * 0x80, AccWidthUint32, 0x00, 0xFFFFFFFF); - } - } -} - - -UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig){ - UINT32 Result=0; - TRACE((DMSG_SB_TRACE,"OEM Call Back Func [%x] Data [%x]\n",Func,Data)); - if (pConfig->StdHeader.pCallBack==NULL) - return Result; - Result = (*(pConfig->StdHeader.pCallBack))(Func,Data,pConfig); - TRACE((DMSG_SB_TRACE,"SB Hook Status [%x]\n",Result)); - return Result; -} diff --git a/src/vendorcode/amd/cimx/sb700/SBPort.c b/src/vendorcode/amd/cimx/sb700/SBPort.c deleted file mode 100644 index d1484812b9..0000000000 --- a/src/vendorcode/amd/cimx/sb700/SBPort.c +++ /dev/null @@ -1,441 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - -REG8MASK sbPorInitPciTable[] = { - // SMBUS Device(Bus 0, Dev 20, Func 0) - {0x00, SMBUS_BUS_DEV_FUN, 0}, - {SB_SMBUS_REGD0+2, 0x00, 0x01}, - {SB_SMBUS_REG40, 0x00, 0x44}, - {SB_SMBUS_REG40+1, 0xFF, 0xE9}, //Set smbus pci config 0x40[14]=1, This bit is used for internal bus flow control. - {SB_SMBUS_REG64, 0x00, 0xBF}, //SB_SMBUS_REG64[13]=1, delays back to back interrupts to the CPU - {SB_SMBUS_REG64+1, 0x00, 0x78}, - {SB_SMBUS_REG64+2, ~(UINT8)BIT6, 0x9E}, - {SB_SMBUS_REG64+3, 0x0F, 0x02}, - {SB_SMBUS_REG68+1, 0x00, 0x90}, - {SB_SMBUS_REG6C, 0x00, 0x20}, - {SB_SMBUS_REG78, 0x00, 0xFF}, - {SB_SMBUS_REG04, 0x00, 0x07}, - {SB_SMBUS_REG04+1, 0x00, 0x04}, - {SB_SMBUS_REGE1, 0x00, 0x99}, //RPR recommended setting, Sections "SMBUS Pci Config" & "IMC Access Control" - {SB_SMBUS_REGAC, ~(UINT8)BIT4, BIT1}, - {SB_SMBUS_REG60+2, ~(UINT8)(BIT1+BIT0) , 0x24}, // Disabling Legacy USB Fast SMI# Smbus_PCI_config 0x62 [5] = 1. Legacy USB - // can request SMI# to be sent out early before IO completion. - // Some applications may have problems with this feature. The BIOS should set this bit - // to 1 to disable the feature. Enabling Legacy Interrupt Smbus_PCI_Config 0x62[2]=1. - {0xFF, 0xFF, 0xFF}, - - // LPC Device(Bus 0, Dev 20, Func 3) - {0x00, LPC_BUS_DEV_FUN, 0}, - {SB_LPC_REG40, 0x00, 0x04}, - {SB_LPC_REG48, 0x00, 0x07}, - {SB_LPC_REG4A, 0x00, 0x20}, // Port Enable for IO Port 80h. - {SB_LPC_REG78, ~(UINT8)BIT0, 0x00}, - {SB_LPC_REG7C, 0x00, 0x05}, - {SB_LPC_REGB8+3, ~(UINT8)BIT0, BIT7+BIT6+BIT5+BIT3+BIT0}, //RPR recommended setting,Section "IO / Mem Decoding" & "SPI bus" - {0xFF, 0xFF, 0xFF}, - - // P2P Bridge(Bus 0, Dev 20, Func 4) - {0x00, SBP2P_BUS_DEV_FUN, 0}, - {SB_P2P_REG40, 0x00, 0x26}, // Enabling PCI-bridge subtractive decoding & PCI Bus 64-byte DMA Read Access - {SB_P2P_REG4B, 0xFF, BIT6+BIT7+BIT4}, - {SB_P2P_REG1C, 0x00, 0x11}, - {SB_P2P_REG1D, 0x00, 0x11}, - {SB_P2P_REG04, 0x00, 0x21}, - {SB_P2P_REG50, 0x02, 0x01}, // PCI Bridge upstream dual address window - {0xFF, 0xFF, 0xFF}, -}; - - -REG8MASK sbA13PorInitPciTable[] = { - // SMBUS Device(Bus 0, Dev 20, Func 0) - {0x00, SMBUS_BUS_DEV_FUN, 0}, - {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible. - {SB_SMBUS_REG38, (UINT8)~BIT7, 00}, - {SB_SMBUS_REGAC+1, ~(UINT8)BIT5, 0}, //Enable SATA test/enhancement mode - {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible. - {0xFF, 0xFF, 0xFF}, -}; - - -REG8MASK sbA14PorInitPciTable[] = { - // LPC Device(Bus 0, Dev 20, Func 3) - {0x00, LPC_BUS_DEV_FUN, 0}, - {SB_LPC_REG8C+2, ~(UINT8)BIT1, 00}, - {0xFF, 0xFF, 0xFF}, -}; - -REG8MASK sbPorPmioInitTbl[] = { - // index andmask ormask - {SB_PMIO_REG67, 0xFF, 0x02}, - {SB_PMIO_REG37, 0xFF, 0x04}, // Configure pciepme as rising edge - {SB_PMIO_REG50, 0x00, 0xE0}, // Enable CPU_STP (except S5) & PCI_STP - {SB_PMIO_REG60, 0xFF, 0x20}, // Enable Speaker - {SB_PMIO_REG65, (UINT8)~(BIT4+BIT7), 0x00},// Clear PM_IO 0x65[4] UsbResetByPciRstEnable to avoid S3 reset to reset USB - {SB_PMIO_REG55, ~(UINT8)BIT6, 0x07}, // Select CIR wake event to ACPI.GEVENT[23] & Clear BIT6 SoftPciRst for safety - {SB_PMIO_REG66, 0xFF, BIT5}, // Configure keyboard reset to generate pci reset - {SB_PMIO_REGB2, 0xFF, BIT7}, - {SB_PMIO_REG0E, 0xFF, BIT3}, // Enable ACPI IO decoding - {SB_PMIO_REGD7, 0xF6, 0x80}, - {SB_PMIO_REG7C, 0xFF, BIT4}, // enable RTC AltCentury register - - {SB_PMIO_REG75, 0xC0, 0x05}, // PME_TURN_OFF_MSG during ASF shutdown - {SB_PMIO_REG52, 0xC0, 0x08}, - - {SB_PMIO_REG8B, 0x00, 0x10}, - {SB_PMIO_REG69, 0xF9, 0x01 << 1}, // [Updated RPR] Set default WDT resolution to 10ms -}; - -REG8MASK sbA13PorPmioInitTbl[]={ - // index andmask ormask - {SB_PMIO_REGD7, 0xFF, BIT5+BIT0}, //Fixes for TT SB00068 & SB01054 (BIT5 & BIT0 correspondingly) - {SB_PMIO_REGBB, (UINT8)~BIT7, BIT6+BIT5}, //Fixes for TT SB00866 & SB00696 (BIT6 & BIT5 correspondingly) - // Always clear [7] to begin with SP5100 C1e disabled - -// {SB_PMIO_REG65, 0xFF, BIT7}, -// {SB_PMIO_REG75, 0xC0, 0x01}, // PME_TURN_OFF_MSG during ASF shutdown -// {SB_PMIO_REG52, 0xC0, 0x02}, - -}; - - -void sbPowerOnInit (AMDSBCFG *pConfig){ - UINT8 dbVar0, dbVar1, dbValue; - UINT16 dwTempVar; - BUILDPARAM *pBuildOptPtr; - - TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n")); - - setRevisionID(); - ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwTempVar); - if (dwTempVar == SB750_SATA_DEFAULT_DEVICE_ID) - RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, 0xFF, 0x01); - - // Set A-Link bridge access address. This address is set at device 14h, function 0, - // register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundry. - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF0, AccWidthUint32, 00, ALINK_ACCESS_INDEX); - - writeAlink(0x80000004, 0x04); // RPR 3.3 Enabling upstream DMA Access - writeAlink(0x30, 0x10); //AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform. - writeAlink(0x34, readAlink(0x34) | BIT9); - - if (!(pConfig->ResetCpuOnSyncFlood)){ - //Enable reset on sync flood - writeAlink( (UINT32)( ((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30)), - (UINT32)( readAlink((((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30))) | ((UINT32)BIT2) )); - } - - pBuildOptPtr = &(pConfig->BuildParameters); - - WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG90, AccWidthUint32 | S3_SAVE, &(pBuildOptPtr->Smbus0BaseAddress) ); - - dwTempVar = pBuildOptPtr->Smbus1BaseAddress & (UINT16)~BIT0; - if( dwTempVar != 0 ){ - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG58, AccWidthUint16 | S3_SAVE, 00, (dwTempVar|BIT0)); - // Disable ASF Slave controller on SB700 rev A15. - if (getRevisionID() == SB700_A15) { - RWIO((dwTempVar+0x0D), AccWidthUint8, (UINT8)~BIT6, BIT6); - } - } - - WritePCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pBuildOptPtr->SioPmeBaseAddress)); - RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F,(pBuildOptPtr->SpiRomBaseAddress)); - - WritePMIO(SB_PMIO_REG20, AccWidthUint16, &(pBuildOptPtr->AcpiPm1EvtBlkAddr)); - WritePMIO(SB_PMIO_REG22, AccWidthUint16, &(pBuildOptPtr->AcpiPm1CntBlkAddr)); - WritePMIO(SB_PMIO_REG24, AccWidthUint16, &(pBuildOptPtr->AcpiPmTmrBlkAddr)); - WritePMIO(SB_PMIO_REG26, AccWidthUint16, &(pBuildOptPtr->CpuControlBlkAddr)); - WritePMIO(SB_PMIO_REG28, AccWidthUint16, &(pBuildOptPtr->AcpiGpe0BlkAddr)); - WritePMIO(SB_PMIO_REG2A, AccWidthUint16, &(pBuildOptPtr->SmiCmdPortAddr)); - WritePMIO(SB_PMIO_REG2C, AccWidthUint16, &(pBuildOptPtr->AcpiPmaCntBlkAddr)); - RWPMIO(SB_PMIO_REG2E, AccWidthUint16, 0x00,(pBuildOptPtr->SmiCmdPortAddr)+8); - WritePMIO(SB_PMIO_REG6C, AccWidthUint32, &(pBuildOptPtr->WatchDogTimerBase)); - - //Program power on pci init table - programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbPorInitPciTable[0]), sizeof(sbPorInitPciTable)/sizeof(REG8MASK) ); - //Program power on pmio init table - programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbPorPmioInitTbl[0]), (sizeof(sbPorPmioInitTbl)/sizeof(REG8MASK)) ); - - dbValue = 0x00; - ReadIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue); - dbValue &= 0xF3; - WriteIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue); - - dbValue = 0x0A; - WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue); - ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); - dbValue &= 0xEF; - WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); - - - if (getRevisionID() >= SB700_A13){ - programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA13PorInitPciTable[0]), sizeof(sbA13PorInitPciTable)/sizeof(REG8MASK) ); - programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbA13PorPmioInitTbl[0]), (sizeof(sbA13PorPmioInitTbl)/sizeof(REG8MASK)) ); - } - - if ((getRevisionID() >= SB700_A14) ) - programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA14PorInitPciTable[0]), sizeof(sbA14PorInitPciTable)/sizeof(REG8MASK) ); - - if ( (getRevisionID() >= SB700_A14) && ( (pConfig->TimerClockSource == 1) || (pConfig->TimerClockSource == 2) )){ - ReadPMIO(SB_PMIO_REGD4, AccWidthUint8, &dbVar1); - if (!(dbVar1 & BIT6)){ - RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT6); - pConfig->RebootRequired=1; - } - } - - if (getRevisionID() > SB700_A11) { - if (pConfig->PciClk5 == 1) - RWPMIO(SB_PMIO_REG41, AccWidthUint8, ~(UINT32)BIT1, BIT1); // Enabled PCICLK5 for A12 - } - - dbVar0 = (pBuildOptPtr->BiosSize + 1) & 7; - if (dbVar0 > 4) { - dbVar0 = 0; - } - //KZ [061811]-It's used wrong BIOS SIZE for coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0); - - if (pConfig->Spi33Mhz) - //spi reg0c[13:12] to 01h to run spi 33Mhz in system bios - RWMEM((pBuildOptPtr->SpiRomBaseAddress)+SB_SPI_MMIO_REG0C,AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT13+BIT12), BIT12); - - //SB internal spread spectrum settings. A reboot is required if the spread spectrum settings have to be changed - //from the existing value. - ReadPMIO(SB_PMIO_REG42, AccWidthUint8, &dbVar0); - if (pConfig->SpreadSpectrum != (dbVar0 >> 7) ) - pConfig->RebootRequired = 1; - if (pConfig->SpreadSpectrum) - RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, BIT7); - else - RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, 0); - - if ( !(pConfig->S3Resume) ){ - //To detect whether internal clock chip is used, do the following procedure - //set PMIO_B2[7]=1, then read PMIO_B0[4]; if it is 1, we are strapped to CLKGEN mode. - //if it is 0, we are using clock chip on board. - RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); - - //Do the following programming only for SB700-A11. - //1. Set PMIO_B2 [7]=1 and read B0 and B1 and save those values. - //2. Set PMIO_B2 [7]=0 - //3. Write the saved values from step 1, back to B0 and B1. - //4. Set PMIO_B2 [6]=1. - ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar); - if (getRevisionID() == SB700_A11){ - RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT7, 00); - WritePMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar); - RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT6); - } - - if (!(dwTempVar & BIT4)){ - RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); //Enable PLL2 - - //we are in external clock chip on the board - if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){ - //Configure usb clock to come from internal PLL - RWPMIO(SB_PMIO_REGD2, AccWidthUint8, 0xFF, BIT3); //Enable 48Mhz clock from PLL2 - RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2 - } - else{ - //Configure usb clock to come from external clock - RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2 - RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 00); //Disable 48Mhz clock from PLL2 - } - } - else{ - //we are using internal clock chip on this board - if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){ - //Configure usb clock to come from internal PLL - RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 0); //Enable 48Mhz clock from PLL2 - RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2 - } - else{ - //Configure usb clock to come from external clock - RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2 - RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, BIT3); //Disable 48Mhz clock from PLL2 - } - } - - ReadPMIO(SB_PMIO_REG43, AccWidthUint8, &dbVar0); - RWPMIO(SB_PMIO_REG43, AccWidthUint8, ~(UINT32)(BIT6+BIT5+BIT0), (pConfig->UsbIntClock << 5)); - //Check whether our usb clock settings changed compared to previous boot, if yes then we need to reboot. - if ( (dbVar0 & BIT0) || ( (pConfig->UsbIntClock) != ((dbVar0 & (BIT6+BIT5)) >> 5)) ) pConfig->RebootRequired = 1; - } - - if (pBuildOptPtr->LegacyFree) //if LEGACY FREE system - RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000); - else - RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5); - - if ( (getRevisionID() == SB700_A14) || (getRevisionID() == SB700_A13)){ - RWPMIO(SB_PMIO_REG65, AccWidthUint8, 0xFF, BIT7); - RWPMIO(SB_PMIO_REG75, AccWidthUint8, 0xC0, BIT0); - RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xC0, BIT1); - } - - if (getRevisionID() >= SB700_A15) { - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0); - //Enable unconditional shutdown fix in A15 - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG38+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT4); - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG06+1, AccWidthUint8 | S3_SAVE, 0xFF, 0xD0); - } - - // [Updated RPR] Set ImcHostSmArbEn(SMBUS:0xE1[5]) only when IMC is enabled - if (isEcPresent()) { - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGE1, AccWidthUint8 | S3_SAVE, 0xFF, BIT5); - } - - //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement - // to program VID/FID LDTSTP# duration selection register - AMDFamily15CpuLdtStopReq(); - -#ifndef NO_EC_SUPPORT - ecPowerOnInit(pBuildOptPtr, pConfig); -#endif -} - - -void setRevisionID(void){ - UINT8 dbVar0, dbVar1; - - ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); - ReadPMIO(SB_PMIO_REG53, AccWidthUint8, &dbVar1); - if ( (dbVar0 == 0x39) && (dbVar1 & BIT6) && !(dbVar1 & BIT7)){ - RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, BIT0); - RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, 00, SB700_A12); - RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, 00); - } - ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); -} - - -UINT8 getRevisionID(void){ - UINT8 dbVar0; - - ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); - return dbVar0; -} - - -void AMDFamily15CpuLdtStopReq(void) { - CPUID_DATA CpuId; - CPUID_DATA CpuId_Brand; - UINT8 dbVar0, dbVar1, dbVar2; - - //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement - //to program VID/FID LDTSTP# duration selection register - //If any of the following system configuration properties are true LDTSTP# assertion time required by the processor is 10us: - // 1. Any link in the system operating at a Gen 1 Frequency. - // 2. Also for server platform (G34/C32) set PM_REG8A[6:4]=100b (16us) - - CpuidRead (0x01, &CpuId); - CpuidRead (0x80000001, &CpuId_Brand); //BrandID, to read socket type - if ((CpuId.REG_EAX & 0xFFFFFF00) == 0x00600F00) { - - //Program to Gen 3 default value - 001b - RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x10); //set [6:4]=001b - - //Any link in the system operating at a Gen 1 Frequency. - //Check Link 0 - Link connected regsister - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG98), AccWidthUint8, &dbVar2); - dbVar2 = dbVar2 & 0x01; - - if(dbVar2 == 0x01) { - //Check Link 0 - Link Frequency Freq[4:0] - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG89), AccWidthUint8, &dbVar0); - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG9C), AccWidthUint8, &dbVar1); - dbVar0 = dbVar0 & 0x0F; //Freq[3:0] - dbVar1 = dbVar1 & 0x01; //Freq[4] - dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] - //Value 6 or less indicate Gen1 - if(dbVar0 <= 0x6) { - RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b - } - } - - //Check Link 1 - Link connected regsister - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGB8), AccWidthUint8, &dbVar2); - dbVar2 = dbVar2 & 0x01; - if(dbVar2 == 0x01) { - //Check Link 1 - Link Frequency Freq[4:0] - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGA9), AccWidthUint8, &dbVar0); - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGBC), AccWidthUint8, &dbVar1); - dbVar0 = dbVar0 & 0x0F; //Freq[3:0] - dbVar1 = dbVar1 & 0x01; //Freq[4] - dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] - //Value 6 or less indicate Gen1 - if(dbVar0 <= 0x6) { - RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b - } - } - - //Check Link 2 - Link connected regsister - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGD8), AccWidthUint8, &dbVar2); - dbVar2 = dbVar2 & 0x01; - if(dbVar2 == 0x01) { - //Check Link 2 - Link Frequency Freq[4:0] - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGC9), AccWidthUint8, &dbVar0); - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGDC), AccWidthUint8, &dbVar1); - dbVar0 = dbVar0 & 0x0F; //Freq[3:0] - dbVar1 = dbVar1 & 0x01; //Freq[4] - dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] - //Value 6 or less indicate Gen1 - if(dbVar0 <= 0x6) { - RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b - } - } - - //Check Link 3 - Link connected regsister - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGF8), AccWidthUint8, &dbVar2); - dbVar2 = dbVar2 & 0x01; - if(dbVar2 == 0x01) { - //Check Link 3 - Link Frequency Freq[4:0] - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGE9), AccWidthUint8, &dbVar0); - ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGFC), AccWidthUint8, &dbVar1); - dbVar0 = dbVar0 & 0x0F; //Freq[3:0] - dbVar1 = dbVar1 & 0x01; //Freq[4] - dbVar0 = ((dbVar1 << 4) | dbVar0); //Freq[4:0] - //Value 6 or less indicate Gen1 - if(dbVar0 <= 0x6) { - RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b - } - } - - // Server platform (G34/C32) set PM_REG8A[6:4]=100b (16us) - if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) { - RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b - } - } - -} - diff --git a/src/vendorcode/amd/cimx/sb700/SBTYPE.h b/src/vendorcode/amd/cimx/sb700/SBTYPE.h deleted file mode 100644 index 3dc571f0f7..0000000000 --- a/src/vendorcode/amd/cimx/sb700/SBTYPE.h +++ /dev/null @@ -1,249 +0,0 @@ -/*;******************************************************************************** -; -; Copyright (C) 2012 Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;*********************************************************************************/ - -#ifndef _AMD_SBTYPE_H_ -#define _AMD_SBTYPE_H_ - -#pragma pack(push,1) - -typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig); -typedef void (*SMM_SERVICE_ROUTINE) (void); - -typedef struct _STDCFG{ - UINT32 pImageBase; - UINT32 pPcieBase; - UINT8 Func; - CIM_HOOK_ENTRY pCallBack; - UINT32 pB2ImageBase; -}STDCFG; //Size of stdcfg is 17 bytes - -typedef struct _BUILDPARAM -{ - UINT16 BiosSize:3; //0-1MB, 1-2MB, 2-4MB, 3-8MB, 7-512KB, all other values reserved - UINT16 LegacyFree:1; - UINT16 Dummy0:12; - - UINT16 EcKbd:1; - UINT16 EcChannel0:1; - UINT16 Dummy1:14; - - UINT32 Smbus0BaseAddress; - UINT16 Smbus1BaseAddress; - UINT32 SioPmeBaseAddress; - UINT32 WatchDogTimerBase; - UINT32 SpiRomBaseAddress; - - UINT16 AcpiPm1EvtBlkAddr; - UINT16 AcpiPm1CntBlkAddr; - UINT16 AcpiPmTmrBlkAddr; - UINT16 CpuControlBlkAddr; - UINT16 AcpiGpe0BlkAddr; - UINT16 SmiCmdPortAddr; - UINT16 AcpiPmaCntBlkAddr; - - UINT16 EcLdn5MailBoxAddr; - UINT8 EcLdn5Irq; - UINT16 EcLdn9MailBoxAddr; - UINT32 ReservedDword0; - UINT32 ReservedDword1; - UINT32 ReservedDword2; - UINT32 ReservedDword3; - - UINT32 HpetBase; //HPET Base address - - UINT32 SataIDESsid; - UINT32 SataRAIDSsid; - UINT32 SataRAID5Ssid; - UINT32 SataAHCISsid; - - UINT32 Ohci0Ssid; - UINT32 Ohci1Ssid; - UINT32 Ehci0Ssid; - UINT32 Ohci2Ssid; - UINT32 Ohci3Ssid; - UINT32 Ehci1Ssid; - UINT32 Ohci4Ssid; - UINT32 SmbusSsid; - UINT32 IdeSsid; - UINT32 AzaliaSsid; - UINT32 LpcSsid; - UINT32 P2PSsid; -}BUILDPARAM; - -typedef struct _CODECENTRY{ - UINT8 Nid; - UINT32 Byte40; -}CODECENTRY; - -typedef struct _CODECTBLLIST{ - UINT32 CodecID; - CODECENTRY* CodecTablePtr; -}CODECTBLLIST; - -typedef struct _AMDSBCFG -{ - STDCFG StdHeader; //offset 0:16 - 17 bytes - //UINT32 MsgXchgBiosCimx; //offset 17:20 - 4 bytes - UINT32 S3Resume:1; - UINT32 RebootRequired:1; - UINT32 Spi33Mhz:1; - UINT32 SpreadSpectrum:1; - UINT32 UsbIntClock:1; //0:Use external clock, 1:Use internal clock - UINT32 PciClk5:1; //0:disable, 1:enable - UINT32 TimerClockSource:2; //0:100Mhz PCIE Reference clock (same as SB700-A12, - //1: 14Mhz using 25M_48M_66M_OSC pin, 2: Auto (100Mhz for SB700-A12, 14Mhz - //using 25M_48m_66m_0SC pin for SB700-A14, SB710, SP5100 - UINT32 ResetCpuOnSyncFlood:1; //0:Reset CPU on Sync Flood, 1:Do not reset CPU on sync flood - UINT32 MsgXchgBiosCimxDummyBB:23; - - /** BuildParameters - The STATIC platform information for CIMx Module. */ - BUILDPARAM BuildParameters; - - //SATA Configuration - UINT32 SataController :1; //0, 0:disable 1:enable* //offset 25:28 - 4 bytes - UINT32 SataClass :3; //1, 0:IDE* 1:RAID 2:AHCI 3:Legacy IDE 4:IDE->AHCI 5:AMD_AHCI, 6:IDE->AMD_AHCI - UINT32 SataSmbus :1; //4, 0:disable 1:enable* - UINT32 SataAggrLinkPmCap:1; //5, 0:OFF 1:ON - UINT32 SataPortMultCap :1; //6, 0:OFF 1:ON - UINT32 SataReserved :2; //8:7, Reserved - UINT32 SataClkAutoOff :1; //9, AutoClockOff for IDE modes 0:Disabled, 1:Enabled - UINT32 SataIdeCombinedMode :1; //10, SataIDECombinedMode 0:Disabled, 1:Enabled - UINT32 SataIdeCombMdPriSecOpt:1; //11, Combined Mode, SATA as primary or secondary 0:primary 1:secondary - UINT32 SataReserved1 :6; //17:12, Not used currently - UINT32 SataEspPort :6; //23:18 SATA port is external accessiable on a signal only connector (eSATA:) - UINT32 SataClkAutoOffAhciMode:1; //24: Sata Auto clock off for AHCI mode - UINT32 SataHpcpButNonESP:6; //25:30 Hotplug capable but not e-sata port - UINT32 SataHideUnusedPort:1; //31, 0:Disabled 1:Enabled - - //Flash Configuration //offset 29:30 - 2 bytes - UINT16 FlashController :1; //0, 0:disable FC & enable IDE 1:enable FC & disable IDE - UINT16 FlashControllerMode:1; //1, 0:Flash behind SATA 1:Flash as standalone - UINT16 FlashHcCrc:1; //2, - UINT16 FlashErrorMode:1; //3 - UINT16 FlashNumOfBankMode:1; //4 - UINT16 FlashDummy:11; //5:15 - - //USB Configuration //offset 31:32 - 2 bytes - UINT16 Usb1Ohci0 :1; //0, 0:disable 1:enable* Bus 0 Dev 18 Func0 - UINT16 Usb1Ohci1 :1; //1, 0:disable 1:enable* Bus 0 Dev 18 Func1 - UINT16 Usb1Ehci :1; //2, 0:disable 1:enable* Bus 0 Dev 18 Func2 - UINT16 Usb2Ohci0 :1; //3, 0:disable 1:enable* Bus 0 Dev 19 Func0 - UINT16 Usb2Ohci1 :1; //4, 0:disable 1:enable* Bus 0 Dev 19 Func1 - UINT16 Usb2Ehci :1; //5, 0:disable 1:enable* Bus 0 Dev 19 Func2 - UINT16 Usb3Ohci :1; //6, 0:disable 1:enable* Bus 0 Dev 20 Func5 - UINT16 UsbOhciLegacyEmulation:1; //7, 0:Enabled, 1:Disabled - UINT16 UsbDummy :8; //8:15 - - //Azalia Configuration //offset 33:36 - 4 bytes - UINT32 AzaliaController:2; //0, 0:AUTO, 1:disable, 2:enable - UINT32 AzaliaPinCfg :1; //2, 0:disable, 1:enable - UINT32 AzaliaFrontPanel:2; //3, 0:AUTO, 1:disable, 2:enable - UINT32 FrontPanelDetected:1; //5, 0:Not detected, 1:detected - UINT32 AzaliaSdin0 :2; //6 - UINT32 AzaliaSdin1 :2; //8 - UINT32 AzaliaSdin2 :2; //10 - UINT32 AzaliaSdin3 :2; //12 - UINT32 AzaliaDummy :18; //14:31 - - CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 37:40 - 4 bytes - UINT32 pAzaliaOemFpCodecTableptr; //offset 41:44 - 4 bytes - - //Miscellaneous Configuration //offset 45:48 - 4 bytes - UINT32 MiscReserved0:1; //0 - UINT32 HpetTimer:1; //1, 0:disable 1:enable - UINT32 PciClks:5; //2:6, 0:disable, 1:enable - UINT32 MiscReserved1:3; //9:7, Reserved - UINT32 IdeController:1; //10, 0:Enable, 1:Disabled - UINT32 MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform - UINT32 ExternalRTCClock:1; //12, 0:Don't Shut Off, 1:Shut Off, external RTC clock - UINT32 AcpiS1Supported:1; //13, 0:S1 not supported, 1:S1 supported - UINT32 AnyHT200MhzLink:1; //14, 0:No HT 200Mhz Link in platform, 1; There is 200MHz HT Link in platform - UINT32 WatchDogTimerEnable:1; //15, [0]: WDT disabled; 1: WDT enabled - UINT32 MTC1e:1; //16, Message Triggered C1e - 0:Disabled*, 1:Enabled - UINT32 HpetMsiDis:1; //17, HPET MSI - 0:Enable HPET MSI, 1:Disable - UINT32 EhciDataCacheDis:1; //18, 0:Date Cache Enabled, 1:Date Cache Disabled /** EHCI Async Data Cache Disable */ - UINT32 MiscDummy:13; - - UINT32 AsmAslInfoExchange0; //offset 49:52 - 4 bytes - UINT32 AsmAslInfoExchange1; //offset 53:56 - - //DebugOptions_1 //offset 57:60 - UINT32 FlashPinConfig :1; //0, 0:desktop mode 1:mobile mode - UINT32 UsbPhyPowerDown :1; //1 - UINT32 PcibClkStopOverride :10; //11:2 - UINT32 Debug1Reserved0:4; //15:11 - UINT32 AzaliaSnoop:1; //16 0:Disable, 1:Enable - UINT32 SataSscPscCap:1; //17, 0:Enable SSC/PSC capability, 1:Disable SSC/PSC capability - UINT32 SataPortMode:6; //23:18, 0: AUTO, 1:Force SATA port(6/5/4/3/2/1) to GEN1 - UINT32 SataPhyWorkaround:2; //25:24, 0:AUTO, 1:Enable, 2:Disable - UINT32 Gen1DeviceShutdownDuringPhyWrknd:2; //27:26, 0:AUTO, 1:YES, 2:NO - UINT32 OhciIsoOutPrefetchDis:1; //28, 0:Enable OHCI ISO OUT prefetch, 1:Disable - UINT32 Debug1Dummy:3; // - - //DebugOptions_2 - UINT32 PcibAutoClkCtrlLow:16; - UINT32 PcibAutoClkCtrlHigh:16; - - //TempMMIO - UINT32 TempMMIO:32; - -}AMDSBCFG; - -typedef struct _SMMSERVICESTRUC -{ - UINT8 enableRegNum; - UINT8 enableBit; - UINT8 statusRegNum; - UINT8 statusBit; - CHAR8 *debugMessage; - SMM_SERVICE_ROUTINE serviceRoutine; -}SMMSERVICESTRUC; - -typedef struct _ABTblEntry -{ - UINT8 regType; - UINT32 regIndex; - UINT32 regMask; - UINT32 regData; -}ABTBLENTRY; - -#define PCI_ADDRESS(bus,dev,func,reg) \ -(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) - -typedef UINT32 CIM_STATUS; -#define CIM_SUCCESS 0x00000000 -#define CIM_ERROR 0x80000000 -#define CIM_UNSUPPORTED 0x80000001 - -#pragma pack(pop) - -#define CIMX_OPTION_DISABLED 0 -#define CIMX_OPTION_ENABLED 1 - -#endif // _AMD_SBTYPE_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SMM.c b/src/vendorcode/amd/cimx/sb700/SMM.c deleted file mode 100644 index 0d752fb13a..0000000000 --- a/src/vendorcode/amd/cimx/sb700/SMM.c +++ /dev/null @@ -1,91 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - -SMMSERVICESTRUC smmItemsTable[]={ - {SB_PMIO_REG0E, BIT2, SB_PMIO_REG0F, BIT2, (CHAR8 *)"Software SMI through SMI CMD port \n ", softwareSMIservice}, - {SB_PMIO_REG00, BIT4, SB_PMIO_REG01, BIT4, (CHAR8 *)"Software initiated SMI \n ", NULL}, - {SB_PMIO_REG02, 0xFF, SB_PMIO_REG05, 0xFF, (CHAR8 *)"SMI on IRQ15-8 \n ", NULL}, - {SB_PMIO_REG03, 0xFF, SB_PMIO_REG06, 0xFF, (CHAR8 *)"SMI on IRQ7-0 \n ", NULL}, - {SB_PMIO_REG04, 0xFF, SB_PMIO_REG07, 0xFF, (CHAR8 *)"SMI on legacy devices activity(Serial, FDD etc) \n ", NULL}, - {SB_PMIO_REG1C, 0xFF, SB_PMIO_REG1D, 0xFF, (CHAR8 *)"SMI on PIO 0123 \n ", NULL}, - {SB_PMIO_REGA8, 0x0F, SB_PMIO_REGA9, 0xFF, (CHAR8 *)"SMI on PIO 4567 \n ", NULL}, -}; - - -/*++ - -Routine Description: - - SB SMI service - -Arguments: - - pConfig - SBconfiguration - -Returns: - - void - ---*/ - -void sbSmmService(AMDSBCFG* pConfig){ - UINT8 i, dbEnableValue, dbStatusValue; - SMMSERVICESTRUC *pSmmItems; - SMM_SERVICE_ROUTINE serviceRoutine; - - pSmmItems = (SMMSERVICESTRUC *)FIXUP_PTR(&smmItemsTable[0]); - TRACE((DMSG_SB_TRACE, "CIMx - Entering SMM services \n")); - for (i = 1; i <= (sizeof(smmItemsTable)/sizeof(SMMSERVICESTRUC)); i++){ - dbEnableValue = pSmmItems->enableRegNum; - ReadPMIO(pSmmItems->enableRegNum, AccWidthUint8, &dbEnableValue); - ReadPMIO(pSmmItems->statusRegNum, AccWidthUint8, &dbStatusValue); - if ( (dbEnableValue & (pSmmItems->enableBit)) && (dbStatusValue & (pSmmItems->statusBit)) ){ - TRACE((DMSG_SB_TRACE, "\n \nSmi source is: %s \n", pSmmItems->debugMessage)); - TRACE((DMSG_SB_TRACE, "Enable Reg:%d Value:%d\n", pSmmItems->enableRegNum, dbEnableValue)); - TRACE((DMSG_SB_TRACE, "Status Reg:%d Value:%d\n\n", pSmmItems->statusRegNum, dbStatusValue)); - if ( (pSmmItems->serviceRoutine)!= NULL){ - serviceRoutine = (void *)FIXUP_PTR(pSmmItems->serviceRoutine); - serviceRoutine(); - } - } - } - TRACE((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n")); -} - - -void softwareSMIservice(void){ - UINT16 dwSmiCmdPort, dwVar; - ReadPMIO(SB_PMIO_REG2A, AccWidthUint16, &dwSmiCmdPort); - ReadIO(dwSmiCmdPort, AccWidthUint16, &dwVar); - TRACE((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar)); -} diff --git a/src/vendorcode/amd/cimx/sb700/USB.c b/src/vendorcode/amd/cimx/sb700/USB.c deleted file mode 100644 index 9c5e7b3be4..0000000000 --- a/src/vendorcode/amd/cimx/sb700/USB.c +++ /dev/null @@ -1,187 +0,0 @@ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - -#include "Platform.h" - - -void usbInitBeforePciEnum(AMDSBCFG* pConfig){ - UINT8 dbVar=0; - - TRACE((DMSG_SB_TRACE, "Entering PreInit Usb \n")); - if (pConfig->Usb1Ohci0){ - dbVar = (pConfig->Usb1Ehci << 2); - dbVar |= ((pConfig->Usb1Ohci0) << 0); - dbVar |= ((pConfig->Usb1Ohci1) << 1); - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT0+BIT1+BIT2), dbVar ); - } - if (pConfig->Usb2Ohci0){ - dbVar = (pConfig->Usb2Ehci << 6) ; - dbVar |= ((pConfig->Usb2Ohci0) << 4); - dbVar |= ((pConfig->Usb2Ohci1) << 5); - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT6+BIT4+BIT5), dbVar ); - } - if (pConfig->Usb3Ohci) - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT7), ((pConfig->Usb3Ohci) << 7) ); - - RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+1, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT4), BIT4); -} - - -void usbInitAfterPciInit(AMDSBCFG* pConfig){ - UINT32 ddBarAddress, ddVar; - - ReadPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address - if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){ - //Enable Memory access - RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); - //USB Common PHY CAL & Control Register setting - ddVar = 0x00020F00; - WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar); - //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD - //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 - RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040); - //RPR - EHCI dynamic clock gating feature - //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled. - // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1 - RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11); - } - - ReadPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address - if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){ - //Enable Memory access - RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); - //USB Common PHY CAL & Control Register setting - ddVar = 0x00020F00; - WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar); - //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD - //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 - RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040); - //RPR - EHCI dynamic clock gating feature - //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled. - // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1 - RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11); - } - - if (pConfig->UsbPhyPowerDown) - RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT0); - else - RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); - - // Disable the MSI capability of USB host controllers - RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); - RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); - RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); - - //RPR recommended setting "EHCI Advance Asynchronous Enhancement DISABLE" - //Set EHCI_pci_configx50[28]='1' to disable the advance async enhancement feature to avoid the bug found in Linux. - //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support - //RPR recommended setting "EHCI Async Park Mode" - //Set EHCI_pci_configx50[23]='1' to disable "EHCI Async Park Mode support" - // RPR recommended setting "EHCI Advance PHY Power Savings" - // Set EHCI_pci_configx50[31]='1' if SB700 A12 & above - // Fix for EHCI controller driver yellow sign issue under device manager - // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1 - RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6); - RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6); - - //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices - //OHCI 0_PCI_Config 0x50[16] = 1 - RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); - RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); - RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); - - if (getRevisionID() >= SB700_A14){ - RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3); - RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3); - - RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17); - RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17); - RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25); - } - - if (getRevisionID() >= SB700_A15) { - //USB PID Error checking - RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1); - RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1); - } - - // RPR 6.25 - Optionally disable OHCI isochronous out prefetch - if (pConfig->OhciIsoOutPrefetchDis) { - RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); - RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); - RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); - } - - if ( pConfig->EhciDataCacheDis ) { - // Disable Async Data Cache, EHCI_pci_configx50[26]='1' - RWPCI ((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26); - RWPCI ((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26); - } -} - - -void usbInitMidPost(AMDSBCFG* pConfig){ - if (pConfig->UsbOhciLegacyEmulation == 0){ - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); - RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT7); - } - else{ - programOhciMmioForEmulation(); - } -} - - -void programOhciMmioForEmulation(void){ - UINT32 ddBarAddress; - - ReadPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address - ddBarAddress &= 0xFFFFF000; - if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ - //Enable Memory access - RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); - RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); - } - - ReadPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address - ddBarAddress &= 0xFFFFF000; - if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ - //Enable Memory access - RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); - RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); - } - - ReadPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address - if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ - //Enable Memory access - RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); - RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); - } -} diff --git a/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h b/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h deleted file mode 100644 index e8f6b38a77..0000000000 --- a/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h +++ /dev/null @@ -1,196 +0,0 @@ -/*;******************************************************************************** -; -; Copyright (C) 2012 Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;*********************************************************************************/ - -#ifndef _AMD_AMDLIB_H_ -#define _AMD_AMDLIB_H_ - -typedef CHAR8 *va_list; -#ifndef _INTSIZEOF - #define _INTSIZEOF(n)( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) ) -#endif - -// Also support coding convention rules for var arg macros -#ifndef va_start -#define va_start(ap,v) ( ap = (va_list)&(v) + _INTSIZEOF(v) ) -#endif -#define va_arg(ap,t) ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) ) -#define va_end(ap) ( ap = (va_list)0 ) - -#ifndef CIMx_DEBUG - #define CIMx_DEBUG 0 -#endif - - -#pragma pack(push,1) - -#define IMAGE_ALIGN 32*1024 -#define NUM_IMAGE_LOCATION 32 - -//Entry Point Call -typedef void (*CIM_IMAGE_ENTRY)(void* pConfig); - -//Hook Call - -typedef struct _Reg8Mask -{ - UINT8 bRegIndex; - UINT8 bANDMask; - UINT8 bORMask; -}REG8MASK; - - -typedef struct _CIMFILEHEADER{ - UINT32 AtiLogo; - UINT32 EntryPoint; - UINT32 ModuleLogo; - UINT32 ImageSize; - UINT16 Version; - UINT8 CheckSum; - UINT8 Reserved1; - UINT32 Reserved2; -}CIMFILEHEADER; - -typedef struct _CPUID_DATA{ - UINT32 REG_EAX; - UINT32 REG_EBX; - UINT32 REG_ECX; - UINT32 REG_EDX; -}CPUID_DATA; - -#ifndef BIT0 - #define BIT0 (1 << 0) -#endif -#ifndef BIT1 - #define BIT1 (1 << 1) -#endif -#ifndef BIT2 - #define BIT2 (1 << 2) -#endif -#ifndef BIT3 - #define BIT3 (1 << 3) -#endif -#ifndef BIT4 - #define BIT4 (1 << 4) -#endif -#ifndef BIT5 - #define BIT5 (1 << 5) -#endif -#ifndef BIT6 - #define BIT6 (1 << 6) -#endif -#ifndef BIT7 - #define BIT7 (1 << 7) -#endif -#ifndef BIT8 - #define BIT8 (1 << 8) -#endif -#ifndef BIT9 - #define BIT9 (1 << 9) -#endif -#ifndef BIT10 - #define BIT10 (1 << 10) -#endif -#ifndef BIT11 - #define BIT11 (1 << 11) -#endif -#ifndef BIT12 - #define BIT12 (1 << 12) -#endif -#ifndef BIT13 - #define BIT13 (1 << 13) -#endif -#ifndef BIT14 - #define BIT14 (1 << 14) -#endif -#ifndef BIT15 - #define BIT15 (1 << 15) -#endif -#ifndef BIT16 - #define BIT16 (1 << 16) -#endif -#ifndef BIT17 - #define BIT17 (1 << 17) -#endif -#ifndef BIT18 - #define BIT18 (1 << 18) -#endif -#ifndef BIT19 - #define BIT19 (1 << 19) -#endif -#ifndef BIT20 - #define BIT20 (1 << 20) -#endif -#ifndef BIT21 - #define BIT21 (1 << 21) -#endif -#ifndef BIT22 - #define BIT22 (1 << 22) -#endif -#ifndef BIT23 - #define BIT23 (1 << 23) -#endif -#ifndef BIT24 - #define BIT24 (1 << 24) -#endif -#ifndef BIT25 - #define BIT25 (1 << 25) -#endif -#ifndef BIT26 - #define BIT26 (1 << 26) -#endif -#ifndef BIT27 - #define BIT27 (1 << 27) -#endif -#ifndef BIT28 - #define BIT28 (1 << 28) -#endif -#ifndef BIT29 - #define BIT29 (1 << 29) -#endif -#ifndef BIT30 - #define BIT30 (1 << 30) -#endif -#ifndef BIT31 - #define BIT31 (1 << 31) -#endif - -#define PCI_ADDRESS(bus,dev,func,reg) \ -(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) - -#pragma pack(pop) - -typedef enum { - AccWidthUint8 = 0, - AccWidthUint16, - AccWidthUint32, -} ACC_WIDTH; - -#define S3_SAVE 0x80 - -#endif //#ifndef _AMD_AMDLIB_H_ -- cgit v1.2.3