From 0f5b8ba53de143c2e0ddbb475a32b12fd2e43290 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Tue, 8 Mar 2022 16:17:29 +0530 Subject: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP In order to enable the UFS controller (PCI device 12.7), the PCI specification says that the device at function 0 in the same slot must also be enabled, which is the ISH. Therefore, this CL enables both the UFS controller and ISH. TEST=Boot to kernel and check lspci output 00:12.0 Serial controller: Intel Corporation Device 54fc 00:12.7 Mass storage controller [0109]: Intel Corporation Device 54ff Signed-off-by: Meera Ravindranath Signed-off-by: Rizwan Qureshi Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62662 Reviewed-by: Lean Sheng Tan Reviewed-by: Kangheui Won Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/devicetree_n.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index 57a37016fe..40dba8b931 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -270,6 +270,8 @@ chip soc/intel/alderlake device ref gspi0 on end device ref p2sb on end device ref emmc on end + device ref ish on end + device ref ufs on end device ref hda on chip drivers/intel/soundwire device generic 0 on -- cgit v1.2.3