From 0dfda74408097be2c04f9999011b8fa3f43fc7cf Mon Sep 17 00:00:00 2001
From: Aamir Bohra <aamir.bohra@intel.com>
Date: Mon, 17 Dec 2018 20:35:36 +0530
Subject: mb/google/hatch: Add SoC and EC asl files in DSDT

This implementation adds below code:

1. Add SOC ACPI code in dsdt.asl
   -> platform.asl
   -> globalnvs.asl
   -> cpu.asl
   -> northbridge.asl
   -> southbridge.asl
   -> sleepstate.asl

2. Add chromeos.asl in dsdt.asl

3. Add EC ACPI code in dsdt.asl
   -> superio.asl
   -> ec.asl

4. Remove config for WAK/PTS ACPI method as chromeec
   doesn't implement those.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
---
 src/mainboard/google/hatch/Kconfig                 |  1 -
 src/mainboard/google/hatch/dsdt.asl                | 36 ++++++++++++++++++++++
 .../variants/baseboard/include/baseboard/gpio.h    |  3 ++
 3 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index ef060f5c3a..b6dec1381e 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -12,7 +12,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
 	select MAINBOARD_HAS_SPI_TPM_CR50
 	select MAINBOARD_HAS_TPM2
 	select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
-	select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
 	select SOC_INTEL_COFFEELAKE
 	select SYSTEM_TYPE_LAPTOP
 
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index cb83509a93..93f7fc00b0 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -14,6 +14,9 @@
  */
 
 #include <arch/acpi.h>
+#include <variant/ec.h>
+#include <variant/gpio.h>
+
 DefinitionBlock(
 	"dsdt.aml",
 	"DSDT",
@@ -23,4 +26,37 @@ DefinitionBlock(
 	0x20110725	/* OEM revision */
 )
 {
+	/* Some generic macros */
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <soc/intel/cannonlake/acpi/globalnvs.asl>
+
+	/* CPU */
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/cannonlake/acpi/northbridge.asl>
+			#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		}
+	}
+
+#if IS_ENABLED(CONFIG_CHROMEOS)
+	/* Chrome OS specific */
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+#endif
+
+	/* Chipset specific sleep states */
+	#include <soc/intel/cannonlake/acpi/sleepstates.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
 }
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
index 921d77a419..0cdec4629e 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
@@ -32,4 +32,7 @@
 /* EC wake pin is LAN_WAKE# */
 #define GPE_EC_WAKE		GPE0_LAN_WAK
 
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI		GPE0_ESPI
+
 #endif /* BASEBOARD_GPIO_H */
-- 
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