From 0d28b978e51b5c4c7b3a5a9fc8b20f1fd06690c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 21 Nov 2022 12:43:04 +0100 Subject: intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register difference. Based on Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 Signed-off-by: Michał Żygowski Change-Id: I11241836ecc9066d323977b030686567c87ed256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69870 Tested-by: build bot (Jenkins) Reviewed-by: Sean Rhodes Reviewed-by: Krystian Hebel --- src/soc/intel/common/block/smm/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index 2d960d6b47..4944ade5db 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -44,3 +44,12 @@ config HECI_DISABLE_USING_SMM help HECI disable using SMM. Select this option to make HECI disable using SMM mode, independent of dedicated UPD to perform HECI disable. + +config PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B + bool + depends on SOC_INTEL_COMMON_BLOCK_SMM + default n + help + Intel Core processors select the periodic SMI rate via GEN_PMCON_A. + On Intel Atom processors the register is different and they use + GEN_PMCON_B/GEN_PMCON2 with different address. -- cgit v1.2.3