From 0c707d4dbc0753b5e40559b8940c6cb2afd80e4d Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 8 Jul 2020 16:54:40 -0700 Subject: soc/amd/picasso: Add PCI driver for data fabric devices Data fabric devices are PCI devices which support PCI configuration space but do not require any MMIO/IO resources. This change adds a PCI driver for the data fabric devices which only provides device operations for adding node to SSDT and returning the ACPI name for the device. Signed-off-by: Furquan Shaikh Change-Id: I3da9287db5febf1a1d7eb1dfbed9f1348f80a588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43314 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/picasso/Makefile.inc | 2 +- src/soc/amd/picasso/data_fabric.c | 169 +++++++++++++++++++++++++++++++++ src/soc/amd/picasso/data_fabric_util.c | 117 ----------------------- 3 files changed, 170 insertions(+), 118 deletions(-) create mode 100644 src/soc/amd/picasso/data_fabric.c delete mode 100644 src/soc/amd/picasso/data_fabric_util.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b6c0ddb915..d19402f79d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -52,7 +52,7 @@ verstage_x86-y += reset.c ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c -ramstage-y += data_fabric_util.c +ramstage-y += data_fabric.c ramstage-y += root_complex.c ramstage-y += mca.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c new file mode 100644 index 0000000000..23cb94c837 --- /dev/null +++ b/src/soc/amd/picasso/data_fabric.c @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void disable_mmio_reg(int reg) +{ + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), + IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), 0); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), 0); +} + +static bool is_mmio_reg_disabled(int reg) +{ + uint32_t val = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg)); + return !(val & ((MMIO_WE | MMIO_RE))); +} + +static int find_unused_mmio_reg(void) +{ + unsigned int i; + + for (i = 0; i < NUM_NB_MMIO_REGS; i++) { + if (is_mmio_reg_disabled(i)) + return i; + } + return -1; +} + +void data_fabric_set_mmio_np(void) +{ + /* + * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. + * + * AGESA has already programmed the NB MMIO routing, however nothing + * is yet marked as non-posted. + * + * If there exists an overlapping routing base/limit pair, trim its + * base or limit to avoid the new NP region. If any pair exists + * completely within HPET-LAPIC range, remove it. If any pair surrounds + * HPET-LAPIC, it must be split into two regions. + * + * TODO(b/156296146): Remove the settings from AGESA and allow coreboot + * to own everything. If not practical, consider erasing all settings + * and have coreboot reprogram them. At that time, make the source + * below more flexible. + * * Note that the code relies on the granularity of the HPET and + * LAPIC addresses being sufficiently large that the shifted limits + * +/-1 are always equivalent to the non-shifted values +/-1. + */ + + unsigned int i; + int reg; + uint32_t base, limit, ctrl; + const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; + const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT; + + for (i = 0; i < NUM_NB_MMIO_REGS; i++) { + /* Adjust all registers that overlap */ + ctrl = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(i)); + if (!(ctrl & (MMIO_WE | MMIO_RE))) + continue; /* not enabled */ + + base = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(i)); + limit = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i)); + + if (base > np_top || limit < np_bot) + continue; /* no overlap at all */ + + if (base >= np_bot && limit <= np_top) { + disable_mmio_reg(i); /* 100% within, so remove */ + continue; + } + + if (base < np_bot && limit > np_top) { + /* Split the configured region */ + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i), np_bot - 1); + reg = find_unused_mmio_reg(); + if (reg < 0) { + /* Although a pair could be freed later, this condition is + * very unusual and deserves analysis. Flag an error and + * leave the topmost part unconfigured. */ + printk(BIOS_ERR, + "Error: Not enough NB MMIO routing registers\n"); + continue; + } + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), np_top + 1); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), limit); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), ctrl); + continue; + } + + /* If still here, adjust only the base or limit */ + if (base <= np_bot) + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i), np_bot - 1); + else + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(i), np_top + 1); + } + + reg = find_unused_mmio_reg(); + if (reg < 0) { + printk(BIOS_ERR, "Error: cannot configure region as NP\n"); + return; + } + + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), np_bot); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), np_top); + pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), + (IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT) | MMIO_NP | MMIO_WE + | MMIO_RE); +} + +static const char *data_fabric_acpi_name(const struct device *dev) +{ + switch (dev->device) { + case PCI_DEVICE_ID_AMD_FAM17H_DF0: + return "DFD0"; + case PCI_DEVICE_ID_AMD_FAM17H_DF1: + return "DFD1"; + case PCI_DEVICE_ID_AMD_FAM17H_DF2: + return "DFD2"; + case PCI_DEVICE_ID_AMD_FAM17H_DF3: + return "DFD3"; + case PCI_DEVICE_ID_AMD_FAM17H_DF4: + return "DFD4"; + case PCI_DEVICE_ID_AMD_FAM17H_DF5: + return "DFD5"; + case PCI_DEVICE_ID_AMD_FAM17H_DF6: + return "DFD6"; + default: + printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); + } + + return NULL; +} + +static struct device_operations data_fabric_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = data_fabric_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_DF0, + PCI_DEVICE_ID_AMD_FAM17H_DF1, + PCI_DEVICE_ID_AMD_FAM17H_DF2, + PCI_DEVICE_ID_AMD_FAM17H_DF3, + PCI_DEVICE_ID_AMD_FAM17H_DF4, + PCI_DEVICE_ID_AMD_FAM17H_DF5, + PCI_DEVICE_ID_AMD_FAM17H_DF6, + 0 +}; + +static const struct pci_driver data_fabric_driver __pci_driver = { + .ops = &data_fabric_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, +}; diff --git a/src/soc/amd/picasso/data_fabric_util.c b/src/soc/amd/picasso/data_fabric_util.c deleted file mode 100644 index a375b84477..0000000000 --- a/src/soc/amd/picasso/data_fabric_util.c +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -static void disable_mmio_reg(int reg) -{ - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), - IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT); - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), 0); - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), 0); -} - -static bool is_mmio_reg_disabled(int reg) -{ - uint32_t val = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg)); - return !(val & ((MMIO_WE | MMIO_RE))); -} - -static int find_unused_mmio_reg(void) -{ - unsigned int i; - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - if (is_mmio_reg_disabled(i)) - return i; - } - return -1; -} - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit, ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT; - - for (i = 0; i < NUM_NB_MMIO_REGS; i++) { - /* Adjust all registers that overlap */ - ctrl = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(i)); - if (!(ctrl & (MMIO_WE | MMIO_RE))) - continue; /* not enabled */ - - base = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(i)); - limit = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i), np_bot - 1); - reg = find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, - "Error: Not enough NB MMIO routing registers\n"); - continue; - } - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), np_top + 1); - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), limit); - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), ctrl); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(i), np_bot - 1); - else - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(i), np_top + 1); - } - - reg = find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "Error: cannot configure region as NP\n"); - return; - } - - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_BASE(reg), np_bot); - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), np_top); - pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT) | MMIO_NP | MMIO_WE - | MMIO_RE); -} -- cgit v1.2.3