From 0c557cd983e021b1675fb1688784652d4815f0ba Mon Sep 17 00:00:00 2001 From: Katherine Hsieh Date: Fri, 13 Apr 2018 06:24:51 +0000 Subject: Revert "mb/google/reef/sand: Override USB2 phy settings" This reverts commit aef0d6b0a7ec867ee29acf9e1c695be27626f239. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: I2eb1d5ddb05ca6bbf6512edf48e3e0d8396ce6a7 Signed-off-by: Katherine Hsieh Reviewed-on: https://review.coreboot.org/25651 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Reviewed-by: Martin Roth --- src/mainboard/google/reef/variants/sand/devicetree.cb | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index e53af885e0..16889bb8c9 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -112,22 +112,6 @@ chip soc/intel/apollolake # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" - # Override USB2 PER PORT register (PORT 1) - register "usb2eye[1]" = "{ - .Usb20PerPortPeTxiSet = 4, - .Usb20PerPortTxiSet = 4, - .Usb20IUsbTxEmphasisEn = 1, - .Usb20PerPortTxPeHalf = 0, - }" - - # Override USB2 PER PORT register (PORT 4) - register "usb2eye[4]" = "{ - .Usb20PerPortPeTxiSet = 7, - .Usb20PerPortTxiSet = 7, - .Usb20IUsbTxEmphasisEn = 1, - .Usb20PerPortTxPeHalf = 0, - }" - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF -- cgit v1.2.3