From 0bca050f2cbff36f9d7c55eddafc34e6b495a767 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 21 Sep 2019 16:21:47 +0300 Subject: device/cardbus: Fix use of PCI_CB_BRIDGE_CONTROL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Read-modify-write needs to access the same register. Numerically both used defines are 0x3e, while register implementations are not identical but only similar. Change-Id: I9348b855320f86868e2d3ef76d3b8d7a4ab7fae0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35518 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner --- src/device/cardbus_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index 4b24c54df7..826d785fd4 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -161,7 +161,7 @@ void cardbus_enable_resources(struct device *dev) /* Error check */ ctrl |= (PCI_CB_BRIDGE_CTL_PARITY | PCI_CB_BRIDGE_CTL_SERR); printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); - pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); + pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctrl); pci_dev_enable_resources(dev); } -- cgit v1.2.3