From 06f4f65d241d1908c5d72cd0455351194ce52ca7 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Tue, 8 Aug 2023 13:56:37 +0100 Subject: soc/intel/alderlake: Make C1e configurable Make it possible to enable C1e from the devicetree by adding `c1e_enable`. C1e was disabled by ea2a38be323173075db3b13729a4006ea1fef72d for all RPL SOCs to reduce noise. This will ensure that boards that disabled it based on CPUID are unchanged. Signed-off-by: Sean Rhodes Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/chip.h | 3 +++ src/soc/intel/alderlake/fsp_params.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index b1e90fa774..2f94db65df 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -736,6 +736,9 @@ struct soc_intel_alderlake_config { */ bool disable_package_c_state_demotion; + /* Enable Enhanced C States */ + bool enable_c1e; + /* i915 struct for GMA backlight control */ struct i915_gpu_controller_info gfx; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 4ceda50fb4..5edfbcc781 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1070,7 +1070,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; if (cpu_id == CPUID_RAPTORLAKE_J0 || cpu_id == CPUID_RAPTORLAKE_Q0) - s_cfg->C1e = 0; + s_cfg->C1e = config->enable_c1e; else s_cfg->C1e = 1; #if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) -- cgit v1.2.3