From 05e740fc40e409dcf8d592f4bbeaf87dc92140c5 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 31 Mar 2012 12:52:21 +0200 Subject: Replace cache control magic numbers with symbols Instead of opaque numbers like (1<<29), use symbols like CR0_NoWriteThrough. Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5 Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/amd/agesa/cache_as_ram.inc | 3 ++- src/cpu/amd/car/cache_as_ram.inc | 3 ++- src/cpu/amd/car/disable_cache_as_ram.c | 4 +++- src/cpu/intel/car/cache_as_ram.inc | 7 ++++--- src/cpu/intel/car/cache_as_ram_ht.inc | 17 +++++++++-------- src/cpu/intel/model_106cx/cache_as_ram.inc | 15 ++++++++------- src/cpu/intel/model_206ax/cache_as_ram.inc | 15 ++++++++------- src/cpu/intel/model_6ex/cache_as_ram.inc | 15 ++++++++------- src/cpu/intel/model_6fx/cache_as_ram.inc | 15 ++++++++------- src/cpu/via/car/cache_as_ram.inc | 9 +++++---- src/include/cpu/x86/cache.h | 6 ++++++ 11 files changed, 63 insertions(+), 46 deletions(-) diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 2124bf3be8..389f7ec5f8 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -28,6 +28,7 @@ */ #include "gcccar.inc" +#include /* * XMM map: @@ -88,7 +89,7 @@ disable_cache_as_ram: /* Disable cache */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 invd diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 4625da1ca0..18a19fc030 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -19,6 +19,7 @@ */ #include +#include #include #define CacheSize CONFIG_DCACHE_RAM_SIZE @@ -320,7 +321,7 @@ wbcache_post_fam10_setup: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 jmp_if_k8(fam10_end_part1) diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 0f91154824..a48a39c6ab 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -21,12 +21,14 @@ * be warned, this file will be used other cores and core 0 / node 0 */ +#include + static inline __attribute__((always_inline)) void disable_cache_as_ram(void) { msr_t msr; /* disable cache */ - write_cr0(read_cr0() | (1 << 30)); + write_cr0(read_cr0() | CR0_CacheDisable); msr.lo = 0; msr.hi = 0; diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 7742a68225..6e642f68f9 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -23,6 +23,7 @@ #include #include +#include #include #include @@ -254,7 +255,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -328,7 +329,7 @@ lout: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Clear sth. */ @@ -353,7 +354,7 @@ lout: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Clear boot_complete flag. */ diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index ca107c4c56..4e0f391d33 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -22,6 +22,7 @@ #include #include +#include #include #include @@ -188,7 +189,7 @@ ap_init: /* Do not disable cache (so BSP can enable it). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 post_code(0x28) @@ -271,7 +272,7 @@ no_msr_11e: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -284,7 +285,7 @@ no_msr_11e: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x2d) @@ -310,7 +311,7 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 post_code(0x2e) @@ -338,7 +339,7 @@ no_msr_11e: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x34) @@ -357,14 +358,14 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x37) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -393,7 +394,7 @@ no_msr_11e: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index caf5d03299..e74e24c0bd 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -20,6 +20,7 @@ #include #include +#include #include #define CPU_MAXPHYADDR 32 @@ -84,7 +85,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +123,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +151,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +182,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -207,7 +208,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index c4d3701c48..7d402e4d4e 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -20,6 +20,7 @@ #include #include +#include #include #include @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -126,7 +127,7 @@ clear_mtrrs: post_code(0x26) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Enable cache for our code in Flash because we do XIP here */ @@ -162,7 +163,7 @@ clear_mtrrs: post_code(0x28) /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer below MRC variable space. */ @@ -195,7 +196,7 @@ before_romstage: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -235,14 +236,14 @@ before_romstage: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -275,7 +276,7 @@ before_romstage: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 08f5b1138d..92337c8158 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -20,6 +20,7 @@ #include #include +#include #include #define CPU_MAXPHYADDR 36 @@ -84,7 +85,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +123,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +151,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +182,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -217,7 +218,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 25d8de28a1..61feb1d8b5 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -20,6 +20,7 @@ #include #include +#include #include #define CPU_MAXPHYADDR 36 @@ -91,7 +92,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -105,7 +106,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -129,7 +130,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -157,7 +158,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -188,14 +189,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -214,7 +215,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 90e6d2b88f..bfad5285dd 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -27,6 +27,7 @@ #include #include +#include #include #define CacheSize CONFIG_DCACHE_RAM_SIZE @@ -39,7 +40,7 @@ CacheAsRam: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 invd @@ -139,7 +140,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -219,7 +220,7 @@ testok: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Set the default memory type and enable variable MTRRs. */ @@ -259,7 +260,7 @@ testok: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 invd diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index c2de073a52..a448228776 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -20,6 +20,11 @@ #ifndef CPU_X86_CACHE #define CPU_X86_CACHE +#define CR0_CacheDisable (1 << 30) +#define CR0_NoWriteThrough (1 << 29) + +#if !defined(__ASSEMBLER__) + /* * Need two versions because ROMCC chokes on certain clobbers: * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: @@ -107,4 +112,5 @@ static inline __attribute__((always_inline)) void disable_cache(void) void x86_enable_cache(void); #endif +#endif /* !__ASSEMBLER__ */ #endif /* CPU_X86_CACHE */ -- cgit v1.2.3