From 04ea73ee78bceb680a2565777c4c7774c2ad1a8e Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 7 Nov 2018 12:58:28 +0100 Subject: siemens/mc_apl3: Set Full Reset Bit into Reset Control Register This mainboard provides customer hardware reset button. A feature of this button is that it holds the APL in reset state as long as the reset button is pressed. After releasing the reset button the APL should restart again without the need for a power cycle. When Bit 3 in Reset Control Register (I/O port CF9h) is set to 1 and then the reset button is pressed the PCH will drive SLP_S3 active (low). Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/29530 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index f41fe732f3..3a87a4f5c5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -62,6 +63,13 @@ void variant_mainboard_final(void) cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); } + + /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). + * When Bit 3 is set to 1 and then the reset button is pressed the PCH + * will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard + * to generate the right reset timing. + */ + outb(FULL_RST, RST_CNT); } static void wait_for_legacy_dev(void *unused) -- cgit v1.2.3