From 0423a2bd1a710c21c741a909abead82956d8cbd6 Mon Sep 17 00:00:00 2001 From: Tristan Shieh Date: Tue, 12 Jun 2018 15:04:43 +0800 Subject: mediatek: Share mtcmos code among similar SOCs Refactor mtcmos code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Ibfd0a90f6eba3ed2e74a3fd54279c7645aa41774 Signed-off-by: Tristan Shieh Reviewed-on: https://review.coreboot.org/27028 Tested-by: build bot (Jenkins) Reviewed-by: Paul Kocialkowski Reviewed-by: Hung-Te Lin Reviewed-by: Julius Werner --- src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 6 +-- src/soc/mediatek/mt8173/include/soc/mtcmos.h | 7 +-- src/soc/mediatek/mt8173/include/soc/spm.h | 13 ++++-- src/soc/mediatek/mt8173/mtcmos.c | 68 +++++++++++++++++----------- 4 files changed, 59 insertions(+), 35 deletions(-) diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index e471b4f312..cb6cc2c2e3 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -381,15 +381,15 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params) } /* mempll new power-on */ - write32(&mt8173_spm->poweron_config_set, 0x1 << 0 | + write32(&mtk_spm->poweron_config_set, 0x1 << 0 | SPM_PROJECT_CODE << 16); /* request mempll reset/pdn mode */ - setbits_le32(&mt8173_spm->power_on_val0, 0x1 << 27); + setbits_le32(&mtk_spm->power_on_val0, 0x1 << 27); udelay(2); /* unrequest mempll reset/pdn mode and wait settle */ - clrbits_le32(&mt8173_spm->power_on_val0, 0x1 << 27); + clrbits_le32(&mtk_spm->power_on_val0, 0x1 << 27); udelay(31); /* PLL ready */ diff --git a/src/soc/mediatek/mt8173/include/soc/mtcmos.h b/src/soc/mediatek/mt8173/include/soc/mtcmos.h index a2b4f6554c..5460e1fde0 100644 --- a/src/soc/mediatek/mt8173/include/soc/mtcmos.h +++ b/src/soc/mediatek/mt8173/include/soc/mtcmos.h @@ -13,9 +13,10 @@ * GNU General Public License for more details. */ -#ifndef __SOC_MEDIATEK_MT8173_MTCMOS_H__ -#define __SOC_MEDIATEK_MT8173_MTCMOS_H__ +#ifndef __SOC_MEDIATEK_COMMON_MTCMOS_H__ +#define __SOC_MEDIATEK_COMMON_MTCMOS_H__ void mtcmos_audio_power_on(void); void mtcmos_display_power_on(void); -#endif /* __SOC_MEDIATEK_MT8173_MTCMOS_H__ */ + +#endif /* __SOC_MEDIATEK_COMMON_MTCMOS_H__ */ diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h index 77516fc1f0..133c8a30f8 100644 --- a/src/soc/mediatek/mt8173/include/soc/spm.h +++ b/src/soc/mediatek/mt8173/include/soc/spm.h @@ -23,7 +23,14 @@ enum { SPM_PROJECT_CODE = 0xb16 }; -struct mt8173_spm_regs { +enum { + DISP_SRAM_PDN_MASK = 0xf << 8, + DISP_SRAM_ACK_MASK = 0x1 << 12, + AUDIO_SRAM_PDN_MASK = 0xf << 8, + AUDIO_SRAM_ACK_MASK = 0xf << 12, +}; + +struct mtk_spm_regs { u32 poweron_config_set; u32 reserved1[3]; u32 power_on_val0; /* 0x010 */ @@ -152,8 +159,8 @@ struct mt8173_spm_regs { u32 sleep_ca15_wfi_en[4]; }; -check_member(mt8173_spm_regs, sleep_ca15_wfi_en[3], 0xf1c); +check_member(mtk_spm_regs, sleep_ca15_wfi_en[3], 0xf1c); -static struct mt8173_spm_regs *const mt8173_spm = (void *)SPM_BASE; +static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; #endif /* __SOC_MEDIATEK_MT8173_SPM_H__ */ diff --git a/src/soc/mediatek/mt8173/mtcmos.c b/src/soc/mediatek/mt8173/mtcmos.c index cdd31f4bc1..00e37edb9b 100644 --- a/src/soc/mediatek/mt8173/mtcmos.c +++ b/src/soc/mediatek/mt8173/mtcmos.c @@ -13,10 +13,19 @@ * GNU General Public License for more details. */ +#include + #include #include #include +struct power_domain_data { + void *pwr_con; + u32 pwr_sta_mask; + u32 sram_pdn_mask; + u32 sram_ack_mask; +}; + enum { SRAM_ISOINT_B = 1U << 6, SRAM_CKISO = 1U << 5, @@ -28,44 +37,51 @@ enum { }; enum { - SRAM_PDN = 0xf << 8, - DIS_SRAM_ACK = 0x1 << 12, - AUD_SRAM_ACK = 0xf << 12, -}; - -enum { - DIS_PWR_STA_MASK = 0x1 << 3, - AUD_PWR_STA_MASK = 0x1 << 24, + DISP_PWR_STA_MASK = 0x1 << 3, + AUDIO_PWR_STA_MASK = 0x1 << 24, }; -static void mtcmos_power_on(u32 *pwr_con, u32 pwr_sta_mask) +static void mtcmos_power_on(const struct power_domain_data *pd) { - write32(&mt8173_spm->poweron_config_set, + write32(&mtk_spm->poweron_config_set, (SPM_PROJECT_CODE << 16) | (1U << 0)); - setbits_le32(pwr_con, PWR_ON); - setbits_le32(pwr_con, PWR_ON_2ND); + setbits_le32(pd->pwr_con, PWR_ON); + setbits_le32(pd->pwr_con, PWR_ON_2ND); - while (!(read32(&mt8173_spm->pwr_status) & pwr_sta_mask) || - !(read32(&mt8173_spm->pwr_status_2nd) & pwr_sta_mask)) + while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) || + !(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask)) continue; - clrbits_le32(pwr_con, PWR_CLK_DIS); - clrbits_le32(pwr_con, PWR_ISO); - setbits_le32(pwr_con, PWR_RST_B); - clrbits_le32(pwr_con, SRAM_PDN); -} + clrbits_le32(pd->pwr_con, PWR_CLK_DIS); + clrbits_le32(pd->pwr_con, PWR_ISO); + setbits_le32(pd->pwr_con, PWR_RST_B); + clrbits_le32(pd->pwr_con, pd->sram_pdn_mask); -void mtcmos_audio_power_on(void) -{ - mtcmos_power_on(&mt8173_spm->audio_pwr_con, AUD_PWR_STA_MASK); - while (read32(&mt8173_spm->audio_pwr_con) & AUD_SRAM_ACK) + while (read32(pd->pwr_con) & pd->sram_ack_mask) continue; } void mtcmos_display_power_on(void) { - mtcmos_power_on(&mt8173_spm->dis_pwr_con, DIS_PWR_STA_MASK); - while (read32(&mt8173_spm->dis_pwr_con) & DIS_SRAM_ACK) - continue; + static const struct power_domain_data disp = { + .pwr_con = &mtk_spm->dis_pwr_con, + .pwr_sta_mask = DISP_PWR_STA_MASK, + .sram_pdn_mask = DISP_SRAM_PDN_MASK, + .sram_ack_mask = DISP_SRAM_ACK_MASK, + }; + + mtcmos_power_on(&disp); +} + +void mtcmos_audio_power_on(void) +{ + static const struct power_domain_data audio = { + .pwr_con = &mtk_spm->audio_pwr_con, + .pwr_sta_mask = AUDIO_PWR_STA_MASK, + .sram_pdn_mask = AUDIO_SRAM_PDN_MASK, + .sram_ack_mask = AUDIO_SRAM_ACK_MASK, + }; + + mtcmos_power_on(&audio); } -- cgit v1.2.3