From 0024678d17586aa294684e2b27acf5c04b22fb08 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 25 May 2022 14:51:50 +0200 Subject: cpu/intel/model_fxx: Select SSE2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Starting from Intel Pentium 4, cpus featured SSE2. This will be used in the follow-up patches to determine whether to use mfence as this instruction was introduced with the SSE2 feature set. Change-Id: I8ce37d855cf84a9fb9fe9e18d77b0c19be261407 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/64666 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas Reviewed-by: Kyösti Mälkki --- src/cpu/intel/model_f2x/Kconfig | 1 + src/cpu/intel/model_f3x/Kconfig | 1 + src/cpu/intel/model_f4x/Kconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 672cf75517..eb11a3338d 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_F2X select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG select CPU_INTEL_COMMON + select SSE2 diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index b0a9f7ce64..ca76929dc5 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -3,3 +3,4 @@ config CPU_INTEL_MODEL_F3X select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON + select SSE2 diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 550a978e85..a77a14c72f 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_F4X bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS + select SSE2 -- cgit v1.2.3