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2005-07-06cleaning cvs leftoversarch import user (historical)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-02-08larger default sizeStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-17Make building with different libpci versions easier. The defines might go intoStefan Reinauer
official libpci for 2.2 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-11use Paulo's reduced versionLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-11*** empty log message ***Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-04adapt to freebios v2. still doesnt handle comments correctly.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-10mptable toolRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-08added -E option for chip erase, remove duplicated codeLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-08add retry to write_byte_program_jedec(), 99% success rateLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-07enable LPC decoding for 1 MB more addresss, for supporting SST49LF00xA/BLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-07SST49LF00[2,3,4] should useLi-Ta Lo
the same driver as 49LF008 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-28fixes to make adl855pc compile.Ronald G. Minnich
fixes to emulator. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-22- Add the cpu path support. Oops I failed to commit this earlierEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-20added missing cpu and cpu_bus supportGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-15- Don't force spew level debug messages on the kherpiEric Biederman
- optimize_link_read_pointers compiles now on the solo so don't disable it. - Start sorting out the confusion between and object and an initobject on the ppc ports - Major bugfix release of romcc to support to remove preprocessor deficiencies. The line and column numbers are computed are now correct. But watch out the error messages sometimes report the location of the next token so things are still a little skewed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-11mpspec.h: Tweak the write_smp_table macro so that it is safe if passed a ↵Eric Biederman
complex expression. crt0.S.lb: Modified so that it is safe to include console.inc console.c: Added print_debug_ and frieds which are non inline variants of the normal console functions div64.h: Only include limits.h if ULONG_MAX is not defined and define ULONG_MAX on ppc socket_754/Config.lb Conditionally set config chip.h socket_940.c We don't need and #if CONFIG_CHIP_NAME we won't be linked in if there are no references. slot_2/chip.h: The operations struct need to be spelled cpu_intelt_slot_2_ops slot_2/slot2.c: The same spelling fix socket_mPGA603/chip.h: again socket_mPGA603/socket_mPGA603_400Mhz.c: and again socket_mPGA604_533Mhz/Config.lb: Conditionally defing CONFIG_CHIP_NAME socket_mPGA604_800Mhz/chip.h: Another spelling fix socket_mPGA604_800Mhz.c and again via/model_centaur/model_centaur_init.c: It's not an intel CPU so don't worry about Intel microcode uptdates earlymtrr.c: Remove work around for older versions of romcc pci_ids.h: More ids. malloc.c: We don't need string.h any longer uart8250.c: Be consistent when delcaring functions static inline arima/hdama/mptable.c: Cleanup to be a little more consistent amdk8/coherent_ht.c: - Talk about nodes not cpus (In preparation for dual cores) - Remove clear_temp_row (as it is no longer needed) - Demoted the failure messages to spew. - Modified to gracefully handle failure (It should work now if cpus are removed) - Handle the non-SMP case in verify_mp_capabilities - Add clear_dead_routes which replaces clear_temp_row and does more - Reorganize setup_coherent_ht_domain to cleanly handle failure. - incoherent_ht.c: Clean up the indenation a little. i8259.c: remove blank lines at the start of the file. keyboard.c: Make pc_keyboard_init static ramtest.c: Add a print out limiter, and cleanup the printout a little. amd8111/Config.lb: Mention amd8111_smbus.c amd8111_usb.c: Call the structure usb_ops not smbus_ops. NSC/pc97307/chip.h: Fix spelling issue pc97307/superio.c: Use &ops no &pnp_ops. w83627hf/suerio.c: ditto w83627thf/suerio.c: ditto buildrom.c: Use braces around the body of a for loop. It's more maintainable. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-09- Clean up the CPP output a little bitEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-09- Fix silly thinkos in that caused parsing problems in romcc.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-09- Fix minor glitch in romcc where it would not return from a header fileEric Biederman
if it had a preprocessor directive on the last line. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-08- Romcc preprocessor bug fixes, (The code size went down about 350 lines.. :)Eric Biederman
- Preprocessor constant expression evaluation is no long a special case so unsigned long values can not be used. - Undefined macros are not converted to 0. But a big warning is printed. - Garbage at the of an #include directive is now done in tokens instead of in characters. This allows comments after an #include directive. - Repaired a previously unnoticed regression in constant expression evaluation. Logical expressions can now be evaluated again. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05add compiler from crosstool, tooStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- First pass at getting the powerpc ports to compileEric Biederman
The static device tree is not built properly at all yet, but at least we get through it. FIXME (What is the proper way to handle add in boards?) - Add generic div64 support and ppc div64 support - Fix abuild so it properly generates the CC line when cross compiling. - Add one more possible ppc cross compiler target git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05remove nasty workaround, include echo in function again :)Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05add debug functionStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05...Stefan Reinauer
add option so it's possible to ignore broken builds git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- Add another possible powerpc cross compiler prefixEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- More fixes...Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- Ensure every copy of Options.lb uses:Eric Biederman
CROSS_COMPILE CC HOSTCC OBJCOPY git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- Ensure the all target is the first commands in the makefile....Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- Put the rule for the Makefile at the bottom of the makefile!Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- In the makefile header get the name of the Makefile correctEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- Massage the code to generate the top level Makefile so theEric Biederman
generated Makefile has correct dependencies and is somewhat complete. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05stepan goes to bed now.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05- some steps towards cross compileStefan Reinauer
- add option to force rebuilds even if they were previously ok - add option to build on target only - play around git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04- Update abuild.sh so it will rebuild successfull buildsEric Biederman
- Move pci_set_method out of hardwaremain.c - Re-add debugging name field but only include the CONFIG_CHIP_NAME is enabled. All instances are now wrapped in CHIP_NAME - Many minor cleanups so most ports build. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30- To reduce confuse rename the parts of linuxbios bios that run fromEric Biederman
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload... - Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86 - ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB. - Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work. - Start using romcc's built in preprocessor (This will simplify header compiler checks) - Add helper functions for examining all of the resources - Remove debug strings from chip.h - Add llshell to src/arch/i386/llshell (Sometime later I can try it...) - Add the ability to catch exceptions on x86 - Add gdb_stub support to x86 - Removed old cpu options - Added an option so we can detect movnti support - Remove some duplicate definitions from pci_ids.h - Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic - Minor romcc bug fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21show error logfileStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- Bump the LinuxBIOS major versionEric Biederman
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-20Tyan update to work with new CPU ConfigYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19initial checkin of automatic linuxbios image build test scriptStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-18- FIXED resources are also ASSIGNED resourcesEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-18- Set the parent's link properly in the bus fieldEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- Bump MAX_LINKS to 4 I have actually found an i2c bridge that needs thisEric Biederman
- Fix the hdama Config.lb to not longer use the link keywords oops, and instead to have it nest everything properly. - Update config.g to not support the link keyword - update config.g to not support northbridge/southbridge/cpu/pmc noise words we can just use chip now. - Remove old link handling from the code - Detect and handle duplicate paths so we generate one device with multiple links git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- HDAMA boots!Eric Biederman
- Set the bootstrap processor flag in the mptable. - Implement 64bit support in our print statements - Fix the reporting of how many cpus we are waiting to stop. It is the 1 less than the actual number of cpus running. - Actually enable cpu_initialization. - Fix firstsiblingdevice in config.g - Add IORESOURCE_FIXED to all of the resources set by config.g - Fix the apic_cluster rule to add an apic_cluster path not an apic path. - Add a div64.h to assist in the 64bit printf. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- First stab at running linuxbios without the old static device tree.Eric Biederman
Things are close but not quite there yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- Fix config.g and the hdama config so everthing builds again.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-15add back stuff from beforeRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-15fixes for apic, i2cRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-15closerRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-15this now works right.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14more or less more or less brokenRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14more breakage, thanks to RonRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- Add chip and a few other bug fixesEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06epia-m supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-30support for sst firmware hubRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-28use hex print in id1, id2Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-28add support for ICH4. more i955pm stuff.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-07code reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-07seperate code generationLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-08added testbios for V2Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-29- Small bug fixes to romcc. The deep problems with not inlining functions ↵Eric Biederman
remain git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03remove brain-dead verify codeGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-29- Don't confuse return statements with conditional branchesEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-28- Upgrade to romcc version 0.63Eric Biederman
This includes more test cases Lots of small bug fixes A built in C preprocessor Initial support for not inlining everything __attribute__((noinline)) works Better command line options and help Constants arrays can be read at compile time Asm statements that are not volatile will now be removed when their outputs go unused Loads and stores that are not volatile will be removed when their values go unused The number of FIXMES in the code is finally starting to go down. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-24minor reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-29chaged chip_device_path::enable to chip_device_path::enabled,Li-Ta Lo
again, I am the only one who can't speak English. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-14seperate checksum and code generating code.Li-Ta Lo
use mmap instead of file io git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-13removed unused assignirq.c and aute generated irq_tables.cLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-13back out incorrect commit on config.gLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-13porting getpir to freebios2Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-13add missing return at 205Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-27data tye consistenceLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-27removed false alarm of erase/write, use verify '-v' if you are not sure ↵Li-Ta Lo
about the integrity git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-23These changes tighten up rules for exporting options.Greg Watson
1. Exportable options ('export used') used to be exported if referred to in a 'uses' statement. These options will now only be exported if the option is set, or the default value is changed. 2. Options marked as 'export always' with no default value ('default none') used to generate defines with no values 'export k8:='. This behavior has changed so that the option will ONLY be exported if it has a value assigned using 'set' or 'default'. Otherwise it is an error. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-22fixed minor typoLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-22more jedec standard consolidatation.Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-20rmove unused #define and function declaretionLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-20I have no idea what i was trying to show off when I used the while loop ratherLi-Ta Lo
than for loop. Please forgive me, I was too young 4 years ago. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-20consolidate more jedec standard codeLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-19remove duplicated codeLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-18Added support for SST49LF0xxA parts.David W. Hendricks
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-18Added support for more SST 49lf0xxA partsDavid W. Hendricks
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-18forgot a semicolonLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-18removed unused code in pm49fl004, remove experimental delay in sst49lf040Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-18fixed stupid i++ evalution order bugLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-18fixed 32bit v.s. 64bit long int arithematicsLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-17removed spd_dump.c, it has nothing to do with flashing flash parts.Li-Ta Lo
use standard product ID exit method for w49f002u move udelay stuff into its own file git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-17move utility functions into new source filesLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-17Added support for SST49LF040David W. Hendricks
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-11- Moved hlt() to it's own header.Eric Biederman
- Reworked pnp superio device support. Now complete superio support is less than 100 lines. - Added support for hard coding resource assignments in Config.lb - Minor bug fixes to romcc - Initial support for catching the x86 processor BIST error codes. I've only seen this trigger once in production during a very suspcious reset but... - added raminit_test to test the code paths in raminit.c for the Opteron - Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED so we can tell what we have really done. - Added generic AGP/IOMMU setting code to x86 - Added an implementation of memmove and removed reserved identifiers from memcpy - Added minimal support for booting on pre b3 stepping K8 cores - Moved the checksum on amd8111 boards because our default location was on top of extended RTC registers - On the Hdama added support for enabling i2c hub so we can get at the temperature sensors. Not that i2c bus was implemented well enough to make that useful. - Redid the Opteron port so we should only need one reset and most of memory initialization is done in cpu_fixup. This is much, much faster. - Attempted to make the VGA IO region assigment work. The code seems to work now... - Redid the error handling in amdk8/raminit.c to distinguish between a bad value and a smbus error, and moved memory clearing out to cpufixup. - Removed CONFIG_KEYBOARD as it was useless. See pc87360/superio.c for how to setup a legacy keyboard properly. - Reworked the register values for standard hardware, moving the defintions from chip.h into the headers of the initialization routines. This is much saner and is actually implemented. - Made the hdama port an under clockers BIOS. I debuged so many interesting problems. - On amd8111_lpc added setup of architectural/legacy hardware - Enabled PCI error reporting as much as possible. - Enhanded build_opt_tbl to generate a header of the cmos option locations so that romcc compiled code can query the cmos options. - In romcc gracefully handle function names that degenerate into function pointers - Bumped the version to 1.1.6 as we are getting closer to 2.0 TODO finish optimizing the HT links of non dual boards TODO make all Opteron board work again TODO convert all superio devices to use the new helpers TODO convert the via/epia to freebios2 conventions TODO cpu fixup/setup by cpu type git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-07config.gGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-02-13fix makefileRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-02-10now we support 8111 and these parts.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1375 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-02-04- Update to the latest config.gEric Biederman
- Everything except if statements should work correctly git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-05- Lower DEBUG_CONSISTENCY to 1 2 is only really useful when debuggingEric Biederman
the register allocator. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-05New option behavior:Greg Watson
1. Options can only be set with 'option' statement in the target configuration file. Options can be set as many times as needed. 2 Option DEFAULT values can be changed (or set) in any configuration file. Changing a default value will display a warning message. 3. A default value is changed with the statement 'default <op> = <val>'. 4. Setting an option overrides the default value. 5. The 'mainboard' and 'arch' statements now set options implicitly. No 'uses' statement is required. The idea is that parts will define default values for options that they need/use. Option overrides are only done in the target file. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-05fix volatileRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-25due to popular demand, added flash_and_burn to the freebios2 tree.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-22- Update romcc to version 0.37Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-14- Fix the link check so it actually checks for the appropriate maximum linkEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 09:59:25 +0000