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This fixes most of the simpler shellcheck errors in shellcheck 0.4.6.
There are still a few warnings left that weren't simple to fix or
would have required more testing before I was confident in them.
Change-Id: I79ab3614cc1d69d3dfe1e0374e930313f2011cbf
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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- Add the Do-not-assume-glibc-glob-internals patch to fix segfaults.
- Update glob_interface_v2 patch to the patch directly from the
make git repository instead of translating it. This gives better
attributution to the original author.
Change-Id: Ibc936fc00925a4ca2170a6f5dca7c2b8d8d62f02
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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- Exclude build flags that generate warnings when scanbuild is running
- Add the SCANBUILD_ARGS variable to abuild so we can pass in arguments
to scanbuild.
- Set the default scanbuild argument to -k (--keep-going) so that even
if an error occurs it continues with the scan. This is similar to what
we do with coverity runs.
Change-Id: I82e7c13d7fd7432b43c17a31834ec82fca158a07
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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- Create a new target, docker-jenkins-attach, to access the running
jenkins server
- Update docker-shell target to set term & size.
Change-Id: Ifa67afb62d4a216281ebece405e9b26fd4d14622
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27494
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Without the second set of braces it fails (due to -Werror) with
"suggest braces around initialization of subobject"
Change-Id: I63cb01dd26412599551ee921c3215a4aa69f4e17
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27551
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We don't block commits for failing checkpatch in gerrit, and we
shouldn't block them here. This allows checkpatch to still run, so
users can see the issues, but won't prevent the commit.
Adds a delay if checkpatch fails so that the issues can be seen.
Change-Id: Ibd4e8bb74e0b02825dcdf16e233a061c4bb43f50
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/27534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Some types of payload segment headers do not use all fields.
If these unused fields are not initialized to 0, they can
cause problems in other software which consumes payloads.
For example, PAYLOAD_SEGMENT_ENTRY does not use the compression
field. If it happens to be a non-existent compression type,
the 'cbfstool extract' command fails.
BUG=https://ticket.coreboot.org/issues/170
TEST=cbfstool tianocore.cbfs create -s 2097152 -m x86
cbfstool tianocore.cbfs add-payload -f UEFIPAYLOAD.fd -n payload -c lzma -v
xxd tianocore.cbfs | head # visually inspect compression field for 0
Change-Id: I359ed117ab4154438bac7172aebf608f7a022552
Signed-off-by: kitching@google.com
Reviewed-on: https://review.coreboot.org/27540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The linux trampoline was modifying the existing GDT
to add the 0x10 and 0x18 descriptors for Linux.
This will not work when the existing GDT is in ROM.
Change the code to set up a new GDT in what we know to be
RAM.
Tested by booting a linux payload. The main reason this works
is that Linux almost immediately loads its own GDT and then
segment registers. This GDT is a very temporary bridge.
Note that none of this change used to be necessary; the coreboot
GDT was originally compatible with Linux (ca 2000);
then Linux changed.
Change-Id: I13990052fbfd6a500adab8a2db8f7aead1d24fa6
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Even though we were setting V=1 in the build, this wasn't getting passed
to abuild, so the builds there didn't have additional debug information.
That made it difficult to debug issues on the builder. This sets the
verbose flag for abuild if V=1 is set.
Change-Id: Id9ec50add9693a6c36ffdb5c78d148d0fc012549
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Because earlier versions of debian set /dev as a standard tmpfs
filesystem, that was a simple place to build. Now, this has been
changed and /dev isn't a standard tmpfs that will grow to 50% of
memory. It's a fixed, very small size, and can no longer even be
resized.
Because of this, create a new directory to build in and add it to
/etc/fstab. Mount it when the container is started.
As long as we're at it, make the other build directories (ccache
and slave-root/workspace) tmpfs as well. The builders we're using now
have plenty of memory, so don't write any of the files to disk.
Update the Makefile to get rid of all references to ccache directory.
Change-Id: I21fd2c4395d7ffb9428172f035991338658cd907
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In case multiple FMAP regions are specified, print the FMAP name.
Useful if VBOOT is enabled and multiple CBFS are printed.
Change-Id: Id6f29ebeda8a9bde6dfe39362e0f2a5e33c86b26
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26862
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert Cavium's BDK devicetree blob to a static C file.
The resulting file must be included in mainboard folder to provide
board specific configuration values to BDK functions.
Example call:
python devicetree_convert.py --in sff8104.dtb --out bdk_devicetree.c
Change-Id: I76a5588aefe4f680228eca46a0e4dba7e695931c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26228
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Update stable directories
- Remove duplicated directories
There are currently 220 files that still need to have headers added or
be excluded from the lint-000-license-headers test.
Change-Id: I40046a2fb7359262b130f6813eda1f2c30916b46
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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In Windows Cygwin enviroment, compiler reports
redefinition error at cbfstool/ifwitool.c
on _packed and __aligned.
Skip new defines when vales are already defined.
Change-Id: I3af3c6b8fc57eee345afcef2f871b897138f78ce
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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commit c1072f2 [cbfstool: Update FIT entries in the second bootblock]
incorrectly changed the value of type_checksum_valid for microcode
entries from FIT_TYPE_MICROCODE to 0, breaking microcode loading on
Skylake/FSP1.1 devices (and others?). Correct this by reverting to the
previous value.
Test: build/boot google/chell, observe FspTempRamInit no longer fails,
device boots as expected.
Change-Id: Ib2a90137c7d4acf6ecd9f06cb6f856bd7e783676
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27266
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also update patches as necessary.
Change-Id: I1e8074954d5d7a4eff590abb7439e9be7d3762aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/25997
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Copied from the GNU make repository
author Paul Smith <psmith@gnu.org>
commit 48c8a116
configure.ac: Support GLIBC glob interface version 2
Change-Id: Id70a2b98dad6349ee56985d8dd6d4f0d87b470e6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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With -D, the newly built toolchain isn't installed into $prefix/...
but into $DESTDIR/$prefix/... while being built for $prefix alone.
This is useful for distributions, but it breaks down when the build
host already has the toolchain installed in $prefix without proper
build isolation (cf. gentoo):
In such cases libgcc etc are built using the new compiler (as gcc's
build system is smart enough to state the path explicitly), but that
compiler then uses its regular algorithm to determine the path to as,
ld, ...
That makes it use the tools from $prefix, which might differ in formats
(assembly, certain object file flags, ...): nds32le-elf in particular
has rather unstable formats still, and so new compilers can't work
with old binutils.
The approach to deal with this is to take an unused path that's
specified by gcc's build system ($out/gcc/$arch/$version) and symlink
it to the new toolchain - these explicitly given directories take
precedence over the default search path, and so the new binutils
are used.
Change-Id: Ia9a262e73f56cd486a2ae07422b598c205a03aed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27241
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Once a second bootblock has been added using topswap (-j)
option, Update the entries in second FIT using -j option with
update-fit command.
Additionally add a -q option which allows to insert the address of
a FMAP region (which should hold a microcode) as the first entry in
the second FIT.
BUG=None
BRANCH=None
TEST= Create ROM images with -j options and update FIT using -q option.
example:
./build/util/cbfstool/cbfstool coreboot.tmp create \
-M build/fmap.fmap -r COREBOOT,FW_MAIN_A,FW_MAIN_B,RW_LEGACY
build/util/cbfstool/cbfstool coreboot.tmp add \
-f build/cbfs/fallback/bootblock.bin -n bootblock -t \
bootblock -b -49152 -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add-master-header -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add -f build/cpu_microcode_blob.bin \
-n cpu_microcode_blob.bin -t microcode -r COREBOOT -a 16
build/util/cbfstool/cbfstool coreboot.tmp. update-fit \
-n cpu_microcode_blob.bin -x 4 -j 0x10000 -q FW_MAIN_A
Also try the failure scenarion by providing invalid topswap size.
Change-Id: I9a417031c279038903cdf1761a791f2da0fe8644
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/26836
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add an option '-j' which takes the size of topswap boundary.
This option serves both as a bool and a size for creating
a second bootblock to be used with topswap feature in Intel CPUs.
'-j' is also used in conjunction with add-master-header to
update the location of cbfs master header in the second bootblock.
BUG=None
BRANHC=None
TEST=add bootblock entry to the image with -j option specifying different
topswap sizes and also use the -j option for add-master-header.
Change-Id: I3e455dc8b7f54e55f2229491695cf4218d9cfef8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22537
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are many boards in coreboot which support multiple
variants. When abuild is used to compile a single target, it builds
all its variants. If a target has 5 variants, then abuild takes nearly
10x the time to compile all variants of the target. This change adds
an option -b/--board-variant to enable abuild to compile only a single
variant of the target.
TEST=Verified:
1. abuild builds all variants of the target if -b option is not
provided.
2. abuild builds a single variant if -b option is provided.
3. abuild prints appropriate error message if invalid variant name is
provided.
Change-Id: I3781568c6409c5ec2610a8386a21d86037428e7f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27215
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"ops" field was used in device structure only to add
default_dev_ops_root for root device. It was always set to NULL for
all other devices. This change gets rid of ops field from struct
device and instead hardcodes default_dev_ops_root in pass1 for root
device.
BUG=b:80081934
TEST=Verified that static.c generated with and without this change is
exactly the same.
Change-Id: I0848788610c2ed27274daf4920de3068a9784d4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27209
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support to allow variants to override the devices and
properties in base device tree by providing an override device
tree. It works as follows:
1. Both base and override device trees are parsed from provided input
files.
2. Walk through the trees in lockstep fashion using depth-first
traversal checking if a node in override tree has a matching node in
base tree.
- If matching node is found, then update the properties of base node
using the override node. Continue walking the children of the nodes.
- If matching node is not found, then copy the entire override
subtree of the node under the current base parent. In addition to
that, chip instance pointers of the nodes in override tree need to be
updated if they were pointing to the override parents chip instance.
Since chip always expects a device to be present, it leads to a
side-effect that overriding chip registers requires that a device is
always provided for the chip in the override tree as well.
BUG=b:80081934
Change-Id: I6604e4f8abe3fc48240e942fea32da96031e1e46
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27206
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change allows sconfig utility to accept an extra optional
parameter to specify override device tree that can be used to override
the properties or add new devices in addition to that provided by base
device tree. This is helpful for variants that share most of the
devicetree but have to override certain registers or add some devices
which might not be applicable to base devicetree.
In order to support the override devicetree, following changes are
made in this CL:
1. override_root_dev and override_root_bus are provided.
2. main() function is updated to accept an optional argument.
3. If override device file is provided, then parse_devicetree is
called for override_devtree as well.
This change in itself does not provide the override feature. It is
only a small step towards the final goal. The override devicetree
parsed by sconfig is currently unused.
BUG=b:80081934
Change-Id: I477e038c8922ae1a9ed5d8bf22a5f927a19a69c7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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From checkpatch output, look for keywords starting with 'ERROR:' &
'WARNING:' .
Also check for keywork ': FILE:' instead of the same without the
colon (:).
BUG=None
BRANCH=None
TEST=Check if patch https://review.coreboot.org/#/c/coreboot/+/22537/21
is processed & json output is generated properly.
Change-Id: Ib690ab34a1ffabc4f83642634fd34beea16a64dc
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/27170
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Recent patches in coreboot have fixed the freeze issues related to the
use of me_cleaner on Nehalem.
However, at least on the Lenovo X201, with me_cleaner some PCIe devices
(like the SATA and USB controllers) disappear. In particular, setting
the AltMeDisable bit ("-S" or "-s" flag) makes them disappear
completely, while unsetting it makes them disappear only during cold
boots.
This kind of behaviour was already observed by Youness Alaoui on the
Purism Librem laptops ([1]), and it seems related to some required
board-specific PCIe configuration in the ME's MFS partition.
For this reason, on the Lenovo X201, "-w EFFS" has been added to the
me_cleaner arguments, which whitelists the MFS-equivalent partition for
ME generation 2. This fixes all the issues, and the PCIe devices work as
expected.
[1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/
Change-Id: Ie77a80d2cb4945cf1c984bdb0fb1cc2f18e82ebc
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/27178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Some older CPUs have a fixed size of 2048 bytes for microcode total size.
Change-Id: Ia50c087af41b0df14b607ce3c3b4eabc602e8738
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27090
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds missing PCI IDs to allow tool to dump the
C220 PCH (8 series) southbridge.
Intel Document 328904 is the datasheet for this PCH.
Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Signed-off-by: Quan Tran <qeed.quan@gmail.com>
Reviewed-on: https://review.coreboot.org/27168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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* Add LinuxBoot support
* Add u-root mode
* Download kernel and u-root from upstream sources.
* Add customization options
* Clean kernel only if directory exists
Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23071
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The endian conversion function be32toh() is defined in
src/include/endian.h, however this file is not used for cbfstool
compilation. Currently the one provided by the host is used and if the
host does not provide this endian.h file, the build will fail.
However, we do have endian conversion functions in commonlib/endian.h
which is available for cbfstool compilation.
Switch from be32toh() to read_be32() in order to avoid relying on a
host provided include file.
We use functions from commonlib/endian.h already in cbfstool.
Change-Id: I106274cf9c69e1849f848920d96a61188f895b36
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/27116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In order to support booting a GNU/Linux payload on non x86, the FIT format
should be used, as it is the defacto standard on ARM.
Due to greater complexity of FIT it is not converted to simple ELF format.
Add support for autodecting FIT payloads and add them as new CBFS_TYPE 'fit'.
The payload is included as is, with no special header.
The code can determine the type at runtime using the CBFS_TYPE field.
Support for parsing FIT payloads in coreboot is added in a follow on
commit.
Compression of FIT payloads is not supported, as the FIT sections might be
compressed itself.
Starting at this point a CBFS payload/ can be either of type FIT or SELF.
Tested on Cavium SoC.
Change-Id: Ic5fc30cd5419eb76c4eb50cca3449caea60270de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use of device_t is deprecated.
Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Move generators for the board status report and the kconfig options
report into a common directory and wrap them in a docker container.
Also rework to emit HTML not wiki syntax.
Change-Id: If42e1dd312c5fa4e32f519865e3b551bc471bc72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of checking each directory in series, kick off the checks
in parallel and then wait for them to finish. Failures print out with
file information, so mixing output isn't a problem. This reduces
the time it takes to run on lumberingbuilder by 60%.
This could probably be sped up even more by splitting up src/mainboard
into smaller sections.
This method does skip a few control files at the top level - .gitignore,
.checkpatch.conf, gnat.adc, etc. These could be added to the list of
files to check, but I didn't think it was needed.
Change-Id: I171977e713a9956cf4142cfc0a199e10040abb35
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In preparation to allow devicetree overrides, it will be necessary to
use the same parsing functions to prepare two separate parse
trees. This change does the following things:
1. Updates root device and bus names to add base_ prefix.
2. Adds a function parse_devicetree that sets the root_parent and
linenum before calling yyparse().
3. Updates all uses of root_dev to refer to the next base_root_dev.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built using
abuild is the same with and without this change.
Change-Id: I403a90c1ebf07ac66115ddfe137daf0980dc1a18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instead of checking each directory in series, kick off all the checks
in parallel and then wait for them to finish. Failures print out with
file information, so mixing output isn't a problem. This reduces
the time it takes to run on lumberingbuilder from 31 seconds to 6.
Change-Id: I1252a68a723370389d399f3d1a2aff3fad64c365
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Copy the script `scripts/config` from Linux (commit 427fbe89 (Merge
branch 'next' of
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux)) into the
newly created directory `scripts`. Here is the original commit message
from 2009.
> commit 8e54701ea85b0ab0971637825a628f5aa2b678a4
> Author: Andi Kleen <andi@firstfloor.org>
> Date: Sat Jan 3 03:21:41 2009 +0100
>
> kconfig: add script to manipulate .config files on the command line
>
> I often change single options in .config files. Instead of using
> an editor or one of the frontends it's convenient to do this from
> the command line. It's also useful to do from automated build scripts
> when building different variants from a base config file.
>
> I extracted most of the CONFIG manipulation code from one of my
> build scripts into a new shell script scripts/config
>
> The script is not integrated with the normal Kconfig machinery
> and doesn't do any checking against Kconfig files, but just manipulates
> that text format. This is always done at make time anyways.
>
> I believe this script would be a useful standard addition for scripts/*
>
> Sample usage:
>
> ./scripts/config --disable smp
> Disable SMP in .config file
>
> ./scripts/config --file otherdir/.config --module e1000e
> Enable E1000E as module in otherdir/.config
>
> ./scripts/config --state smp
> y
> Check state of config option CONFIG_SMP
>
> After merging into git please make scripts/config executable
>
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Change-Id: Ie32a4459398df8694956dd644f38692017a26388
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/26243
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib417f435011f0331a1b0228734874ef0a62fb587
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This also removes a "chapters mode" that we never used.
Change-Id: Ib301e2f4db0b9678081fa987a5dcc7108bb103a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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SoCs from Skylake on have many settings as so called private con-
figuration registers (PCRs). These are organized as 256 ports with
a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's
BAR to access them.
Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19593
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Most things still need to be filled in, but this will allow us to build
boards which use this SOC.
BUG=b:80501386
BRANCH=none
TEST=timer and uart work fine
Change-Id: Ie81fa56ffce85188e1f9e979f9b0e64b764c2627
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26659
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I75fa4577055f25dde0a8b1044c005bba72cabd92
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I1a0db60b527c2f7ffe77743c0d75b78a7c8bc4cc
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26877
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change gets rid of rescnt member in struct device since it is
redundant. "res" member can be used to determine if resource list is
present or not.
BUG=b:80081934
TEST=Verified that static.c generated with and without this CL is
exactly the same for all boards built using abuild.
Change-Id: I73a2361686ad1130716a7d29576f2d02b9ed33c1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change re-factors the device structure in parse tree to be able
to support multidev devices just like non-multidev devices.
With this change, every device has a bus under it which is the parent
of all devices that fall on the bus. If there are duplicate entries in
the devicetree, then there will be multiple buses under the device and
each bus will have its own set of children.
The tree starts out with a root device which has a root bus under
it. This is a special device which is created statically and its
parent is its own root bus. When parsing the device tree file, devices
get added under the root bus as children.
Since this change re-organizes the way devicetree is represented, it
gets rid of latestchild and next_sibling pointers from struct
device. Also, the tree traversal to generate static.c is changed to
breadth-first walk instead of using the next_sibling.
BUG=b:80081934
TEST=Verified using abuild that all boards compile successfully.
Change-Id: Ic8c8a73a247e8e992ab6b1b2cc3131e06fa2e5a1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change updates queue handling routines to be more generic so that
it can be used by more than just chip queue. Additionally, it provides
functions to dequeue element from head and peek head of a queue which
will be used in a follow-up commit.
BUG=b:80081934
TEST=Verified that abuild compiles successfully for all boards.
Change-Id: Ibd2de85b48c5d4e2790bf974ea3bb1bd387f66ee
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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During compilation sconfig/main.c gives an error regarding number of
arguments passed in fprintf.
BUG=none
BRANCH=none
TEST=check if compilation warning has been fixed
Change-Id: Ia769cc606a1e3f7e1188cd82235442493d37f664
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26972
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change gets rid of unused 3rd parameter chips to the function
walk_device_tree.
BUG=b:80081934
TEST=Verified that abuild compiles successfully for all boards.
Change-Id: I255ff030562073b16310fc22a0981808bf2c062f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Required to get a current version string onto doc.coreboot.org
Change-Id: Iac54c4be2d4e783b7bf9ed529a431e72c67abab7
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/26896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Make the directory name match the name of the subdomain.
Change-Id: I2dcf2385e6d953b7fe02caef72413149a332ec24
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/26887
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We don't need the .deb files in the image forever
Change-Id: I67a56faf8f9466e5162f7662708a5abb2971d2f9
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/26895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Sphinx >= 1.6 can't use recommonmark. debian/stable is ancient enough to
have an older version.
Change-Id: I287deab9168ab6124b05d0c6d6e8cdbd7fdc2eec
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/26699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Check that filenames have only alphanumeric characters plus underscore,
dash, and period.
Change-Id: I7bf0be15d588aa1a5ece628b56e871662d6af44b
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Now that chips and devices are treated differently and the device tree
actually contains only devices, next and nextdev are exactly the same
for all devices in the tree. This change gets rid of nextdev pointer
and updates all uses of nextdev to next.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built by abuild
is same with and without this change.
Change-Id: Ie50b3d769a78fe0beddba2e5551441b43cb212a2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Now that chips and devices are treated differently in sconfig, this
change gets rid of struct header and add_header function which were
responsible for maintaining list of headers that need to be added to
static.c.
Instead, struct chip is re-factored into struct chip and
struct chip_instance, where chip is a list of unique chips required by
the mainboard whereas chip_instance is an instance of the chip. One
chip can have multiple instances dependending upon the devices in the
system. Also, struct device is updated to hold a pointer to chip
instance instead of the chip structure. This unique list of chips is
then used to add appropriate headers to static.c
BUG=b:80081934
TEST=Verified using abuild that all boards compile successfully.
Change-Id: I6fccdf7c361b4f55a831195adcda9b21932755aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a helper function s_alloc (sconfig alloc) that allocates memory
using calloc to get 0 initialized memory and checks to ensure it is
not NULL.
BUG=b:80081934
Change-Id: I56a70cf4865c50ed238226ace86e867bb1ec53db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The only reason bus pointer existed in device structure in sconfig was
to allow a node to point to the parent which could be a chip and bus
which is the true parent in device tree hierarchy. Now that chip is no
longer a device, there is no need for separate bus and parent
pointers. This change gets rid of the redundant bus pointer in struct
device in sconfig.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built by abuild
is same with and without this change.
Change-Id: I21f8fe1545a9ed53d66d6d4462df4a5d63023844
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change removes call to add_header from parsing functions and
moves it to a local function within main.c. It also adds a new
function emit_headers that is responsible for creating the linked list
for chip headers and emitting those to static.c
BUG=b:80081934
TEST=Verified that static.c for all files compiled using abuild is the
same with and without this change.
Change-Id: I24d526e81323115d3cc927242a4b9e49414afbe0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change adds a new structure "struct chip" to identify elements of
type chip rather than re-using the structure for device. Until now
chip was treated as a device while generating the parse tree and then
device tree postprocessing skipped over all the chip entries in
children and sibling pointers of device nodes.
With this change, the device tree will only contain struct device in
the parsed tree. It helps by avoiding unnecessary pointers to chip
structure as children or next_sibling and then skipping those elements
in post processing. Every device can then hold a pointer to its chip.
When generating static.c, chip structure is emitted before device
structure to ensure that the device structure has chip within its
scope. Externally, the only visible change in static.c should be the
order in which chip/device elements are emitted i.e. previously all
chips under a particular device were emitted to static.c and then the
devices using those chips. Now, all chips are emitted before all the
devices in static.c
BUG=b:80081934
TEST=Verified that abuild is successful for all boards. Also, verified
that static.c generated for eve, kahlee, scarlet, asrock imb_a180 is
unchanged from before in node definitions.
Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The generated file .dependencies shall be removed on invocation of
'make clean' as the clean target aims to delete all generated files.
Change-Id: I4ec291fe84136bbdf1c2563cc10195846652a36d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/26600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Run `git status` to let the user spot what is going on.
Change-Id: I154d964354872f922cd22b05a5d2231ca2504f25
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22016
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie79cfb92cfb8b8f628aa4b12bba946b0479fc466
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I122acaf9129afaa7b3ae8fd50d8717138809132e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Tested on Pentium 4, CPUID = 0F65 board: NEC 945G-M4.
Change-Id: I27c4bb0aed3259aa332581384077e000c9fb4b4c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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CPUID F6x will not support all MSRs on intel_pentium4_later.
Removed from pentium4_later and added as Pentium D.
Change-Id: Ic6ac0593607b6f87fe921ac52738dad5ee3457dc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I6c14f3aad59749896816bb8789788fc513e7176f
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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- Add some directories and files to the ignore list
- Add the LGPL as a recognized header. It's used in some files that
were pulled into coreboot from other sources.
Change-Id: I53423205f1cbf142a294ee5d24e885741a44dfcd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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It now looks like this:
Check that files have license headers (lint-stable-000-license-headers): success
Check for superfluous whitespace in the tree (lint-stable-003-whitespace): success
Check that C labels begin at start-of-line (lint-stable-004-style-labels): success
Change-Id: I9d1f6adebae5b68a51e89c2833f8713f0ffcb616
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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It's a white list (configured through $(top)/.clang-format-scope) with
the expectation that the list will grow over time.
Once everything is covered, we can turn off the white-listing and keep
everything enforced.
To not drive people crazy, only check the files their commit touched.
Change-Id: I52c7ea73fd36aaa46c0bfce928158e1cd6304540
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Instead of requiring the user to enter their root password to set the
created files to their user, create a new user inside the docker
container with the correct UID & GID and build with that.
Change-Id: Ibbeff00211e8cf653f48204d285e06bca39b5fd2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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These files are supposed to contain trailing whitespace due to the patch
format. Also use the exclusion list in the pre-commit hook.
Change-Id: I8816c05ea703964a332915a0675096836957b242
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26695
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Users can have non-default configurations as to how git diff et al are
presenting file names in diffs (default: a/ and b/ prefixes). checkpatch
expects that and trims the first element, so enforce that configuration
for the diff that's sent into it.
Change-Id: I099795119456a73c900b31ce191c2d9e898a5c7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
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We didn't bail out if configuring or building of GCC failed but run
`make install` and later steps instead. This resulted in very confusing
logs that concealed the actual error.
Change-Id: Ia064e0bfd96f0cbad391da3bb19e4dc304d988ff
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26496
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows one to compile intelmetool with support for older ME
versions by setting the OLDARC preprocessor definition.
For example, compiling with OLDARC enabled avoids the "ME: GET FW
VERSION message failed:" error on the Lenovo X201i (ME version 6.0).
Change-Id: I5eb0da7663e795f790e2723bb334447380724b56
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/26450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Because the tegra124 & tegra201 lp0 builds weren't junit tests, the
builds weren't actually picked up by jenkins, so any failures were
not previously reported.
Change-Id: Ie443ca713912d01ccf6921ce49f846d7297163ef
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26422
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4cb70c2aa466ac71dc8fcd25a7c1824696f32909
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/26449
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I967f67a19a96cac8b7e0e98356e87d7d0610d4b2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch adds a new "rawcompress" command to cbfs-compression-tool,
that works exactly the same as "compress" except that it doesn't add the
custom 8-byte header to the file. This can be useful if you need to
compress something into a format that coreboot's decompression routines
can work with, but it's not supposed to go into CBFS.
Change-Id: I18a97a35bb0b0f71f3226f97114936dc81d379eb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch adds two minor improvements to the way cbfs-compression-tool
parses the compression algorithm type that is passed through the -t
option of the 'compress' subcommand. These improvements are intended
to prevent accidents and unexpected behavior when using the
cbfs-compression-tool, in particular in automated contexts such as a
Makefile rule.
In the first part of this patch, a return statement is inserted after
the 'if (algo->name == NULL)' check of the compress() function. This
causes the function to exit immediately and subsequently abort the
program when the algorithm type was not detected correctly. Previously,
execution would continue with the 'algo' pointer pointing to the zeroed
out stopper entry of the types_cbfs_compression[] array. The ultimate
effect of this would be to pass 0 as 'algo->type' to the
compression_function() function, which happens to be the same
enumeration value as is used for CBFS_COMPRESS_NONE, leading to a valid
compression function result that matches the behavior of no compression.
Thus, if a script calling cbfs-compression-tool compress contained a
typo in the -t parameter, it would continue running with an unintended
compression result rather than immediately exiting cleanly.
In the second part of this patch, the strcmp() function is replaced with
strcasecmp() when comparing 'algo->name' with the 'algoname' parameter
that was passed to the compress() function. strcasecmp() uses an
identical function signature as strcmp() and is thus suitable as a
drop-in replacement, but it differs in behavior: rather than only
returning a result of 0 when the two NULL-terminated input strings are
character by character identical, the strcasecmp() function applies a
weaker concept of identity where characters of the latin alphabet
(hexadecimal ranges 0x41 through 0x5a and 0x61 through 0x7a) are also
considered identical to other characters that differ from them only in
their case. This causes the -t parameter of cbfs-compression-tool
compress to also accept lowercase spellings of the available compression
algorithms, such as "lz4" instead of "LZ4" and "lzma" instead of "LZMA".
As an unintended but harmless side-effect, mixed-case spellings such as
"lZ4" or "LZmA" will also be recognized as valid compression algorithms.
(Note that since the character "4" (hexadecimal 0x34) of the "LZ4"
compression type name is not part of the above-mentioned ranges of latin
alphabet characters, no new substitutions become valid for that part of
the "LZ4" string with this patch.)
Change-Id: I375dbaeefaa0d4b0c5be81bf7668f8f330f1cf61
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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- Remove archive utilities no longer needed by EM100 build
- Remove duplicate libgmp-dev entry
- Add graphviz needed for doxygen builds
Tested building to verify dependencies:
coreboot(what-jenkins-does), em100, chromeec, flashrom, SeaBIOS, TINT,
memtest86+, tianocore, doxygen, ipxe, FILO, GRUB, libpayload,
depthcharge
Tested ROM in QEMU
Change-Id: Idb5cf43807706b3298ee08f6707f495d3a79abb6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26393
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Up to this point, junit.xml has only been used to build tools, as abuild
has handled the coreboot builds. To add additional tests not covered
by abuild, we need junit.xml to work with bare directories.
This also requires updating the build directory (BLD_DIR) for existing
builds using the junit.xml target.
Change-Id: If6e27e02e25e20f48e5a9372373de6058ca378dd
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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compare_timestamp_entries will fail for entries that are different by
at least 2^32 since entry_stamp is 64-bit and the return for compare
is 32-bit. This change fixes compare_timestamps by actually comparing
the entries to return 1, -1 or 0 instead of doing math on them.
TEST=Verified that "cbmem -t" sorts entries correctly on previously
failing entries.
Change-Id: I67c3c4d1761715ecbf259935fabb22ce37c3966e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It seems this was never used and the usage doesn't mention it either.
Change-Id: I9240c0ed5453beff6ae46fae3748c68a0da30477
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26324
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We have two payload options in abuild:
"None" or a pointer to an elf file.
This disables all other options in abuild, and makes disabling the other
options common to both valid options.
Change-Id: Icbd6fde4343ac1cff05778131f9e54370baf4224
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This reverts commit 717ba748366cda19b7532897a5b8d59fc2cd25d9.
This breaks seabios and a few other payloads. This is not
ready for use.
Change-Id: I48ebe2e2628c11e935357b900d01953882cd20dd
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Currently, adding a payload to CBFS using the build system, the warning
below is shown.
W: Unknown type 'payload' ignored
Update payload type from "simple elf" to "simple_elf" and rename the
word "payload" to "simple_elf" in all Makefiles.
Fixes: 4f5bed52 (cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF)
Change-Id: Iccf6cc889b7ddd0c6ae04bda194fe5f9c00e495d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26240
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I67c4f579f898a709dde3fab6bab1474a721da770
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18258
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Icc3973dfc7217ca649fb4151ccdea5461a550bb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Registers IA32_MCi_xx are defined as architectural MSRs
since "P6 Family Processors" and should have model-agnostic
indexing.
Note that in IA32 architecture manual, names of these MSRs are
similarly swapped in the table of Intel Core Microarchitecture.
I take this is an error in the documentation only, and it got
copy-pasted across different CPU family files in the utility.
Change-Id: I227102875b5c3d6ac144ed23a3085f3c37dabd4a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26269
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I46cd986f4914b214156da49db37ecfa749386ce8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Not everything non-intel is AMD.
Change-Id: I06d6fbaa0b4f2c9e61d9b3b4aeeb349a91aa090e
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18255
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the timestamp entries are added out of order, the duration
calculation will be wrong.
AGESA collects timestamp data through all the stages. Then in AmdInitPost
it asks for a buffer to write TP_Perf_STRUCT into. agesawrapper will then
take the data and call timestamp_add on each entry. This results in
the entries being out of order.
TEST=Built firmware for grunt that manually added entries and then ran
cbmem -t/-T to verify the entries were in the correct order.
Change-Id: I6946a844b71d714141b3372e4c43807cfe3528ad
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26168
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The VIA CPUs allow setting the CPUID vendor, which is best read as
a character string.
Change-Id: I67f77ca75f7d77e47b3ba09bad904df5805e373a
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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VIA c3 & C7 use the the family of 0x6 and model 10, but are not quite
Pentium III.
Change-Id: I85e9853b42cfd20db46db0bd244620d6813bc826
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18256
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This commit adds support for describing USB ports in devicetree.cb.
It allows a USB port location to be described in the tree with
configuration information, and ACPI code to be generated that
provides this information to the OS.
A new scan_usb_bus() is added that will scan bridges for devices so
a tree of ports and hubs can be created.
The device address is computed with a 'port type' and a 'port id'
which is flexible for SOC to handle depending on their specific USB
setup and allows USB2 and USB3 ports to be described separately.
For example a board may have devices on two ports, one with a USB2
device and one with a USB3 device, both of which are connected to an
xHCI controller with a root hub:
xHCI
|
RootHub
| |
USB2[0] USB3[2]
device pci 14.0 on
chip drivers/usb/acpi
register "name" = ""Root Hub""
device usb 0.0 on
chip drivers/usb/acpi
register "name" = ""USB 2.0 Port 0""
device usb 2.0 on end
end
chip drivers/usb/acpi
register "name" = ""USB 3.0 Port 2""
device usb 3.2 on end
end
end
end
end
Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I84f612db058d83936ddd5a6baa32c993e5b0f594
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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gcc 8.1 insists.
Change-Id: I8cb00fafdfff7679e38f357c6e8968da656c351d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/25995
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make sure that SiFive-related code is counted under RISC-V in the
release notes.
Change-Id: I3a74bb25ea66c98bc194adafd8267afeb42d7993
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25987
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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