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2023-01-27amdfwtool: Update and extend PSP header format descriptionZheng Bao
The comment in the header amdfwtool.c was written long time ago and is needed to get updated. Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-25amdfwtool: Remove comment "fallthrough"Zheng Bao
Fix the comment as "checkpatch" says. Change-Id: Ifa5d7de037aa7024779f3aa4a5d2f5033eed264a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71648 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-22amdfwtool: Change the variable name to body_locationZheng Bao
The dir_location and efs_location have the same meaning. Now the dir means body. Change-Id: I02d4dc848f189449b6f0a1eea5cd6b8020a7d101 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-22amdfwtool: Add instance = 0 for bios imageZheng Bao
For future BIOS image entry whose instance = 1. Change-Id: Iaa40872b270cf9ff289794c8c51c4d8b448d862d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-22amdfwtool: Add missing code for checking new family phoenix & glindaZheng Bao
Change-Id: Ib82f6c03b93d277f3f7f27ce57c1a41fdc103575 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22amdfwtool: Add entry types required to support glinda & phoenix SOCZheng Bao
Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-12soc/amd: Change Morgana codename to PhoenixMartin Roth
Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24util/amdfwtool: Write EFS and AMDFW body in separate filesKarthikeyan Ramasubramanian
Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12amdfwtool: Add definition of instance for PSP entryZheng Bao
Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12util/amdfwtool/amdfwtool: Don't rewrite macrosElyes Haouas
Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-11util/amdfwtool: Add more instances some types in BDTArthur Heymans
Some hardware uses more instances. Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11util/amdfwtool: Add new typesArthur Heymans
These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-26util/amdfwtool: Add build rules for amdfwreadKarthikeyan Ramasubramanian
Add build rules to build amdfwread tool. Also mark this as a dependency either while building tools or amdfw.rom. BUG=None TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: List AMDFW RO binary entriesKarthikeyan Ramasubramanian
Add support to walk through PSP L1, PSP L2, BIOS L1, BIOS L2 directories and list the entries present in them. Accommodate both recovery A/B layout and normal layout. This is required to identify the location and size of each entries in the finally built amdfw.rom. This in turn can be used to perform any platform specific verification on the relevant components. BUG=None TEST=Build and list the contents of AMDFW binary. /usr/bin/amdfwread --ro-list /build/skyrim/firmware/image-skyrim.bin Table: FW Offset Size PSPL1: Dir 0x00d97000 +-->PSPL1: 0x48 0x00d98000 0x00001000 +-->PSPL2: Dir 0x00c30000 +-->PSPL2: 0x00 0x00c31000 0x00000440 +-->PSPL2: 0x01 0x00c31500 0x00007580 +-->PSPL2: 0x02 0x00c38b00 0x00019470 +-->PSPL2: 0x08 0x00c52000 0x0001f560 +-->PSPL2: 0x09 0x00c71600 0x00000440 +-->PSPL2: 0x0b 0x430000041(Soft-fuse) +-->PSPL2: 0x0c 0x00c71b00 0x00023100 +-->PSPL2: 0x12 0x00c94c00 0x00015890 +-->PSPL2: 0x13 0x00caa500 0x000021c0 +-->PSPL2: 0x20 0x00cac700 0x00000640 +-->PSPL2: 0x21 0x00cace00 0x00000030 +-->PSPL2: 0x22 0x00cad000 0x00001000 +-->PSPL2: 0x24 0x00cae000 0x00003b60 +-->PSPL2: 0x28 0x00cb1c00 0x00022890 +-->PSPL2: 0x2d 0x00cd4500 0x00003100 +-->PSPL2: 0x30 0x00cd7600 0x0006b550 +-->PSPL2: 0x3a 0x00d42c00 0x000006d0 +-->PSPL2: 0x3c 0x00d43300 0x000018c0 +-->PSPL2: 0x44 0x00d44c00 0x00006610 +-->PSPL2: 0x45 0x00d4b300 0x00001c70 +-->PSPL2: 0x50 0x00d4d000 0x00001a00 +-->PSPL2: 0x51 0x00d4ea00 0x00001020 +-->PSPL2: 0x52 0x00d4fb00 0x00010180 +-->PSPL2: 0x55 0x00d5fd00 0x00000600 +-->PSPL2: 0x5a 0x00d60300 0x00000570 +-->PSPL2: 0x5c 0x00d60900 0x00000b20 +-->PSPL2: 0x71 0x00d61500 0x00024710 +-->PSPL2: 0x73 0x00d85d00 0x00010640 +-->PSPL2: 0x8d 0x00d96400 0x00000030 +-->PSPL2: 0x49 0x00d99000 0x00001000 +-->BIOSL2: Dir 0x00d99000 +-->BIOSL2: 0x60 0x00d9a000 0x00009924 +-->BIOSL2: 0x68 0x00da4000 0x00009924 +-->BIOSL2: 0x61 0x2001000(DRAM-Address) +-->BIOSL2: 0x62 0x00dada00 0x00010000 +-->BIOSL2: 0x63 0x00000000 0x0001e000 +-->BIOSL2: 0x64 0x00db4200 0x00006310 +-->BIOSL2: 0x65 0x00dba600 0x000004e0 +-->BIOSL2: 0x64 0x00dbab00 0x00006180 +-->BIOSL2: 0x65 0x00dc0d00 0x00000250 +-->BIOSL2: 0x6b 0x201f000(DRAM-Address) +-->PSPL1: 0x4a 0x00d98000 0x00001000 Change-Id: Ia1b8f1a2b9bc7dc6925a305cdff1442aaff182cd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66761 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: Handle recovery A/B layoutKarthikeyan Ramasubramanian
Upcoming AMD SoCs use recovery A/B layout. Update amdfwread tool to handle it. Also add a generic read_header function to read different header types. BUG=None TEST=Run amdfwread tool against both Skyrim and Guybrush BIOS images to dump the Softfuse entry. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66554 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit maskKarthikeyan Ramasubramanian
Optional arguments that involve printing information from the firmware image is mapped to bit fields with bit 31 set. But instead of just setting bit 31, bits 27 - 31 are set. Fix AMDFW_OPT* bit mask. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0d88669bace45f3332c5e56527516b2f38295a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66573 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: Update relative_offset functionKarthikeyan Ramasubramanian
* AMD_ADDR_PHYSICAL refers to physical address in the memory map * AMD_ADDR_REL_BIOS is relative to the start of the BIOS image * AMD_ADDR_REL_TAB is relative to the start of concerned PSP or BIOS tables Update the relative_offset implementation accordingly. Though AMD_ADDR_REL_SLOT is defined it is not used. Removing that to simplify the relative_offset implementation so that it can be used for both PSP and BIOS firmware tables. Hence update the relative_offset function signature as well. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-21util/amdfwutil: Fix adding microcode binariesArthur Heymans
Change-Id: I726df4ff97688f4c48961e6e61672cef6c3b7aff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-11util/amdfwread: Fix cookie error messageArthur Heymans
Change-Id: I580675fcbf8c5058ade371c6b9edb7b7070a78a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-11util/amdfwutil: Order enum and use hex consistentlyArthur Heymans
This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-10-10util/amdfwtool: Add Mendocino to usageFred Reitberger
Add missing Mendocino soc to usage print. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I8b995fccc23dcca87d45cc13fbb1ebbc1f0e2add Reviewed-on: https://review.coreboot.org/c/coreboot/+/68226 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10util/amdfwtool: Add preliminary code for morgana & glinda SOCsMartin Roth
This allows amdfwtool to recognize the names for the upcoming morgana and glinda SoCs. It does not yet do anything for those SoCs, but this allows the morgana SoC to build. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I766ce4a5863c55cbc4bef074ac5219b498c48c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68193 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02util/amdfwtool: Generate hashes for signed AMDFW componentsKangheui Won
Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02util/amdfwtool: Add options to separate signed firmwaresKangheui Won
Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02util/amdfwtool: Include the header with __packed definitionKarthikeyan Ramasubramanian
Checkpatch script recommends to use __packed instead of __attribute__((packed)). Currently the build rule for amdfwtool does not include the required header file with __packed definition. Update the compiler flag to include the required header file. BUG=None TEST=Build amdfwtool. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I448cbad533608dd5c2bd4f2d827fcc5db5dee5cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67384 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30util/amdfwtool/data_parse: fix PMU subprogram/instance ID handlingFelix Held
The parsing of the PMU binary subprogram and instance numbers only worked correctly for the cases where the ID in the name in the fw.cfg file was between 0 and 9, but returned wrong results if it was between a and f. Switch to using strtol with a base of 16 instead of subtracting the char '0' from the char in the filename in find_register_fw_filename_bios_dir to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic5fd41daf9f26d11c1f86375387c1d7beac04124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-22util/amdfwtool: Add support for PSP NVRAM base addr and sizeRitul Guru
Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04util/amdfwtool/amdfwread: Fix incorrect option indexKarthikeyan Ramasubramanian
index I/O argument to getopt_long is not the index to argv. Instead it is an index into the optlong array corresponding to the parsed option. Also getopt() uses a global variable optind to track the index of the next argument to be processed. Use the optindex variable as an index to extract the filename from argv. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Change-Id: I33c74a0c8e12c5af76954524cf7294b7541d286b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66553 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29amdfwtool: Fix indentationZheng Bao
Change-Id: I4c57c9bade318d54315f9692cd37edb694e33aa9 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58320 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26util/amdfwtool: Add changes to reserve BIOS SIGRitul Guru
changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-12amdfwtool/amdfwtool.h: Allow 16 additional PSP entries to be supportedAltamshali Hirani
Consolidate MAX_BIOS_ENTRIES and MAX_PSP_ENTRIES definitions into one file Signed-off-by: Altamshali Hirani <al.hirani@amd.corp-partner.google.com> Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62911 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11util/amdfwtool: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used. Update amdfwtool for consistency with the correct naming convention. BUG=b:239072117 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I673a9b99d207603b605756fc7d277c54c5d0f311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66467 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-09util/amdfwtool: Fix ISH_B directory offsetKarthikeyan Ramasubramanian
On boards which use both PSP recovery A/B layout as well as VBOOT A/B layout, ISH_B directory entry is pointing directly to PSP Level2 directory. This is not correct and either ISH_B should be marked as not present or it should point to the ISH_A directory itself which in turn point to PSP L2 directory. Fix it by choosing the latter option. BUG=None TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0a7a56e98de3f85669ff8ec2fcd1687aa33576a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-01util/amdfwtool: Support PSP whitelist file on recovery A/B layoutKarthikeyan Ramasubramanian
This is required to enable PSP verstage on SoCs with recovery A/B layout. BUG=b:217414563 TEST=Ensure that the concerned type 0x3a PSP entry is present in PSP L2 directory. Build and boot to OS in Skyrim with both PSP and x86 verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5fae2b5dbcc95a99af3df9f59bb8516280ec1281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-26util/amdfwtool: Update the location of PSP verstage and signing keyKarthikeyan Ramasubramanian
On SoCs which use A/B recovery layout, PSP verstage and signing keys are expected to be present only in PSP L2 directory. Update amdfwtool to include the PSP verstage and signing key only in PSP L2 directory. BUG=b:239519603, b:238938623 TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ieeb415be800b7ccf10d6983eb0b567e0a5eaa955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-30util/amdfwtool: Initalize all variables before useFred Reitberger
Not all of the fields of the amd_cb_config structure were properly initialized. Rather than initialize each field individually, initialize the entire structure to 0. TEST: Boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia343f01bce3956d66d01ce485b43963193c9df31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-05-13util/amdfwtool: Add amdfwread utilityRobert Zieba
Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-05-05util/amdfwtool: Add IKEK key for Trusted ApplicationKarthikeyan Ramasubramanian
This binary file is required for use by Trusted Applications that execute in PSP. BUG=b:229947314 TEST=Build and boot to OS in Skyrim. Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-25amdfwtool: Use command line option use-combo to decide if use comboZheng Bao
The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-25amdfwtool: Change the name of macros for 'BHD'Zheng Bao
Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-14util/amdfwtool: Maintain one copy of PSP Level2 entriesKarthikeyan Ramasubramanian
AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-13amdfwtool: Add a flag to record the second gen instead of romsigZheng Bao
This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-05amdfwtool: Add a macro to set explicitly second gen for old SOCsZheng Bao
It is more reasonable than getting the value from memset. For the reserved bits, keep them as they were for old SOCs. Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-03util/amdfwtool/data_parse: fix SPL table handling regressionFelix Held
Use the SPL table binary from the config file if no override is specified via the spl-table command line argument. This fixes a regression caused by commit 6c5ec8e31ccbe3d9bbf201c956fc3b54703a9767 (amdfwtool: Add options to support mainboard specific SPL table). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I93419a878b41b1dfcbf58d930740aaae553120f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30util/amdfwtool: use ISH support for Sabrina SoCFelix Held
The PSP in the Sabrina SoC uses the image slot header to find the second level PSP directory table, so it needs the ISH to be generated. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9e6308854147c9f6f72d722215c833ee86ee4f94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63186 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30util/amdfwtool: add Sabrina SoC typeFelix Held
Add PLATFORM_SABRINA to the enum of supported platforms and integrate it into the existing code. Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe52b44395619f697686bd900a522562abbe7646 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30util/amdfwtool: select A/B recovery when ISH is usedFelix Held
In newer AMD SoCs, the image slot header is used in the AMD A/B recovery scheme, so set recovery_ab to true when need_ish is true. Also move the block of code before the process_config call, since that call will already use the recovery_ab field of the cb_config struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I65903765514f215bf5cc9b949d0b95aff781eb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63184 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30util/amdfwtool: use table-relative addressing in ISH caseFelix Held
When the image slot header (ISH) is used, the addresses in the PSP and BIOS directory tables need to be relative to the beginning of the table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia61f7c8313d5a1af95c68b9177a53a2f5443552a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-29amdfwtool: Clear the whole byte of EFS_GENZheng Bao
Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-27amdfwtool: Add ISH header support for A/B recovery layoutZheng Bao
Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-27util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW typesFelix Held
Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware table entries, so add those as a preparation for Sabrina support. Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-23amdfwtool: Change the some FW's level for A/B recoveryZheng Bao
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to level 2 only for A/B recovery for Sabrina, which is going to be the long term and A/B recovery layout only. So the amdfwtool should be changed for Sabrina. The old levels of these 3 FWs are for Cezanne, which doesn't use AB recovery now. Just set the specific field levels in generic Cezanne folder for demo. Leave the fw.cfg in Guybrush unchanged. Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-21amdfwtool: Check the length of matching string before accessingZheng Bao
If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character is got or access violation happens. Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-09amdfwtool: Clear struct match before regular expression matchingZheng Bao
If it is not cleared and the number of strings is fewer than last iteration, the match[3] will keep the last value, which actually should be empty. Add assert to make sure the level is a legal value. BUG=b:222038278 Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-24amdfwtool: Check the real length of PMU stringZheng Bao
The length should be checked before the PMU_STR_INS_INDEX(th) character is accessed, otherwise it is going to an access violation. Change-Id: I8b59eb34e1cb01fd6e2571fcebc28ef2084b6ec4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21amdfwtool: Add entries for PMUI & PMUD with instance 2Zheng Bao
Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-21amdfwtool: Add support for AMD's BIOS A/B recovery featureZheng Bao
The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUDZheng Bao
Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-12amdfwtool: Add options to support mainboard specific SPL tableZheng Bao
For the generic board which uses Cezanne, we use the generic SPL table. For the Guybrush Chromebook, we need to use a customized SPL file. BUG=b:216096562 Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-07amdfwtool: Add SPL supportZheng Bao
SPL: Security Patch Level The data in SPL is used for FW anti-rollback, preventing rollback of platform level firmware to older version that are deemed vulnerable from a security point of view. BUG=b:216096562 Change-Id: I4665f2372ccd599ab835c8784da08cde5558a795 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-16amdfwtool: Upgrade "relative address" to four address modesZheng Bao
Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-14amdfwtool: Use relative address for EFS gen2Zheng Bao
The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. The field additional_info in table header can tell if the absolute or relative address is used. Chips like Cezanne can run in both cases, so no problem comes up so far. The related change in psp_verstage has been uploaded. https://review.coreboot.org/c/coreboot/+/58316 The relative mode is the mode 1 of four address modes. The absolute mode is the mode 0. Later we will implement mode 2. Not sure if mode 3 is needed. It needs to be simple to work with psp_verstage change to make SOC Cezanne work quickly. This patch is defacto a subset of https://review.coreboot.org/c/coreboot/+/59308 which implements the framework of address mode and covers mode 0,1,2. Some hardcode value like 29 can be removed in 59308. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-18amdfwtool: Call the set_efs_table for StoneyridgeZheng Bao
Related to https://review.coreboot.org/c/coreboot/+/58555 commit-id: 35b7e0a2d82ac In 58555, we added the SOC ID for Stoneyridge in amdfwtool command line. But it raised building error because it then called "set_efs_table" without setting SPI mode. So we skipped calling that. But in set_efs_table, it has case for Stoneyridge. The boards also need to have this setting. So we remove the skipping and give the proper SPI mode in mainboard Kconfig. Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18amdfwtool: Set flag comboable as bool typeZheng Bao
Fix the CL: https://review.coreboot.org/c/coreboot/+/58942 The type comboable was int but set as true. Change-Id: Id2c43378735c089a27a5aa683b55a0f7ec3677de Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18amdfwtool: Add a union for combo and psp directoryZheng Bao
For combo layout, this is for combo header. For non-combo layout, this is for PSP directory. Change-Id: Ie7b5aec6b511ad61972908d1d22a13aeb7dd73a9 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15amdfwtool: Set soc name for StoneyridgeZheng Bao
For the stoneyridge, soc_name is not set in Makefile, so set_efs_table is not called. Keep it unchanged. Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-11amdfwtool: Pack out-of-bounds check into a function and moveZheng Bao
Need to check the FWs number limit several times. So pack the duplicated steps into a function. And do it before access the new entry. Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05amdfwtool: Change the flag value to type boolZheng Bao
Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05amdfwtool: Fix the parameter point to NULL instead of integerZheng Bao
Change-Id: Iaeeec7a7e2de7847bfcefa5b7ff3f259f86533d4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05amdfwtool: Change the definition of level to a bitwise formZheng Bao
Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-29amdfwtool: Add PSP ID for combo and ISH header for A/B recoveryZheng Bao
Nobody calls the function until combo or A/B is added, so suppress the warning for now. Test=Majolica (Cezanne) Change-Id: I3082b850fb3fd2d7ae83a1c4dfd89eb7e1bd0f97 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-19util/amdfwtool: rename PSP related embedded_firmware struct elementsFelix Held
The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-09-23amdfwtool: Add an optional column of levelZheng Bao
The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-17amdfwtool: Detect the flag multilevel to decide the actual valueZheng Bao
To save the space for FW, some of the FWs are going to be defined as LVL2 entries. To be compatible to "flattened" layout, we still drop the LVL2 entry to level1 if there is only one level. Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-15amdfwtool: Add new SOC mendocinoZheng Bao
Change-Id: I54492600dd954a5585ce3b1d842d264a4a50907a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-31amdfwtool: Add flag for multi FW level to the struct amd_cb_configZheng Bao
This change can make the code be more flexible. And later we will use amd_cb_config to transfer parameters. Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31amdfwtool: Copy string in a safer wayZheng Bao
The issue is reported by Coverity. Using strcpy or strcat copying string without checking length may cause overflow. BUG=b:188769921 Reported-by: Coverity (CID:1438964) Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14Revert "amdfwtool: Use relative address for EFS gen2"Kangheui Won
This reverts commit 0fc87e31e0b9ad15dd199fe96189a2ade6abf240. Reason for revert: Breaks psp_verstage in guybrush BUG=b:182477057 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da Reviewed-on: https://review.coreboot.org/c/coreboot/+/56131 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08amdfwtool: Fix the NULL pointer in parametersZheng Bao
Change-Id: Ia2c65013d48fc1ad88d3caf6ef59824745c992de Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55550 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08amdfwtool: Use relative address for EFS gen2Zheng Bao
The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. Chips like Cezanne can run in both cases, so no problem comes up so far. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-14amdfwtool: Null check the pointers before using themZheng Bao
BUG=b:188769922 Reported-by: Coverity (CID:1438963) Change-Id: Ia520e33c9e4065236478665fb0ef047fa47c9b81 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54999 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-09amdfwtool: Add missing license headerZheng Bao
Change-Id: Id466e733d421602cfe0403ead95e417f0bb37eb4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-09amdfwtool: Move EFS related definitions to header fileZheng Bao
EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07amdfwtool: Print the entry type when dumping the firmwaresZheng Bao
Change-Id: I07bf10e16a42a2b2ab784ee6ac4a4465b7412da6 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07amdfwtool: Set the region_type as 0 for entry "BIOS level 2"Zheng Bao
This region_type is actually not used. But we need to set it explicitly as a known value. We can refer "PSP spec #55758" or the link below: https://doc.coreboot.org/soc/amd/psp_integration.html Change-Id: I8b914f9f02beecce707aba86248826cd9208e6c0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-18amdfwtool:cezanne: use correct bootloader binary for whitelist supportNikolai Vyssotski
PSP whitelist bootloader (PSPBTLDR_WL_FILE) should be copied to type 0x73 entry and not type 0x01 (stage1 bootloader). We will also need to change WHL BL filename (Type0x01->Type0x73) in a separate CL. BUG=b:181135622 Change-Id: I71539a2065546547edc8a2621474cd1388b6434b Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-18amdfwtool: Remove the misleading option charactersZheng Bao
Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-30amdfwtool: Cleanup the message of helpZheng Bao
1. Wrap the long lines. 2. Align the message. 3. Add new SOC name, Cezanne. 4. Fix the cases. Change-Id: Id537d7c9b77641289274c1b2b6f606e2be37ac6b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-16util/amdfwtool: Clean up MakefileMartin Roth
- Add method to disable warnings as errors - Add help target - Add phony targets to .PHONY BUG=None TEST=make all; make help; make all WERROR="" Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Icd0cfd3e2579c9016ebb616e371d1076a5a171b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16util/amdfwtool: Enable warnings as errorsMartin Roth
BUG=None TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7746430c24dd052c435561236454b456bc597517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16util/amdfwtool: Fix all warningsMartin Roth
Fixes these warnings: warning: alignment 1 of 'struct _psp_directory_table' is less than 16 [-Wpacked-not-aligned] warning: alignment 1 of 'struct _psp_combo_directory' is less than 16 [-Wpacked-not-aligned] In function 'find_register_fw_filename_bios_dir': warning: implicit conversion from 'enum _amd_fw_type' to 'amd_bios_type' {aka 'enum _amd_bios_type'} [-Wenum-conversion] BUG=None TEST=Build and verify binaries are identical. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I761d9893ac6737b42af96c4b2a57c5a4fc61ab05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-03amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)Zheng Bao
Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-28util/amdfwtool: Add "all" target to MakefilePatrick Georgi
The test-tools make target requires it. Change-Id: I20819f8d587e6b3a472cdc32751e9edf505d5ba6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-08util/amdfwtool,post: add missing distclean targetFelix Held
Without this target some spurious errors occurred when running make distclean at the top level of coreboot. Change-Id: I3d3061b386fc5b4a043cfc7ff8fd3c0da33c0e83 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49227 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-31util/amdfwtool: portability fixes for FreeBSDIdwer Vollering
Add the stdint.h header, and drop the GLIBC section from amdfwtool.h to build this tool on FreeBSD as well as Linux. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I295fd308b0f5e2902931f02c9455823a614976de Reviewed-on: https://review.coreboot.org/c/coreboot/+/48977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21amdfwtool: Add support of cezanne and renoirZheng Bao
Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11amdfwtool: Register APCB and APCB_BK respectivelyZheng Bao
We took the assumption the APCB(0x60) and APCB_BK(0x68) are the same file. For picasso, they are. For later programe, they are not. Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-11util/amdfwtool: Fix EFS generation polarityMarshall Dawson
The DWORD used to indicate the Embedded Firmware Structure's generation uses 1 to indicate a first-gen structure, e.g. a SPI device's erased value of 0xffffffff. A 0 in bit 0 is how Client PSPs will interpret the structure as designed for second-gen. This change and the original addition should have no effects on any current products as none interpret offset 0x24. BUG=b:158755102 TEST=inspect EFS in coreboot.rom Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: If391f356a1811ed04acdfe9ab9de2e146f6ef5fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-21util/amdfwtool: add missing zero-initialization for local variableFelix Held
Change-Id: Ib156b16b874f74f58bd816071db3a7acf33c5aaf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47817 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-17amdfwtool: Move the MP2CFG checking to category of BIOS dataZheng Bao
Change-Id: Iaaf9c96dd0ed8c31bb50350d37646ca08a1bbff0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>