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2013-02-28Drop CONFIG_WRITE_HIGH_TABLESStefan Reinauer
It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-27Fix microcode selection codeStefan Reinauer
The ARM CPUs we know of don't have CPU microcode updates, so don't show the selection in Kconfig. Also simplify (and fix) the microcode selection in the Makefile that would try to include microcode even though none is available. Change-Id: I502d9b48d4449c1a759b5e90478ad37eef866406 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2540 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-27Google/snow: update the GPIO emulation.Ronald G. Minnich
Add two more GPIOs (total 6) as needed by the Google Snow laptop. These are faking out settings for now. This code is tested and working. Change-Id: I2077ffb8b85958eefdf54e19763d57cc1178ce89 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2538 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2013-02-27Persimmon: remove HDMI Audio, PCI device 00:01.1 from devicetree.cbJens Rottmann
Commit 8487229b (Persimmon doesn't have HDMI so the GNB HD Audio should be disabled.) turned off the device in AGESA. Now remove it from devicetree.cb, too. This prevents the following boot message: PCI: Left over static devices: PCI: 00:01.1 PCI: Check your devicetree.cb. Also clarify the line's comment a bit for the Fam14 boards which still retain this device (to counter the loss of information ;-). Change-Id: Ib671ed2e0d04bdef2869e8d70208d6e55cdea3fd Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2537 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-27selfboot: Report correct entry point address in debug message.Hung-Te Lin
Entry point in payload segment header is a 64 bit integer (ntohll). The debug message is currently reading that as a 32 bit integer (which will produce 00000000 for most platforms). Change-Id: I931072bbb82c099ce7fae04f15c8a35afa02e510 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2535 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-02-27smm: Update rev 0x30101 SMM revision save stateAaron Durbin
According to both Haswell and the SandyBridge/Ivybridge BWGs the save state area actually starts at 0x7c00 offset from 0x8000. Update the em64t101_smm_state_save_area_t structure and introduce a define for the offset. Note: I have no idea what eptp is. It's just listed in the haswell BWG. The offsets should not be changed. Change-Id: I38d1d1469e30628a83f10b188ab2fe53d5a50e5a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2515 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-27Mainboard SMI S state handler was using the wrong definesMarc Jones
The PCH register bit definition for sleep type is a little confusing. For example, 7 is S5. To make this simpler for the mainbaord developer, the mainboard smi sleep hander is called as mainboard_sleep(slp_typ-2). A couple mainboard SMI handlers were using the PCH define for slp_ty, so S3 code would be run for S5 and S5 code would never be run. Change-Id: Iaecf96bfd48cf00153600cd119760364fbdfc29e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/2514 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-27IOAPIC: Divide setup_ioapic() in two parts.Kyösti Mälkki
Currently some southbridge codes implement the set_ioapic_id() part locally and do not implement the load_vectors() part at all. This change allows clean-up of those southbridges without introducing changed behaviour. Change-Id: Ic5e860b9b669ecd1e9ddac4bbb92d80bdb9c2fca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/300 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-26Unify setting 82801a/b/c/d IOAPIC IDKyösti Mälkki
Remove obscure local copy of writing the ioapic registers. Change-Id: I133e710639ff57c6a0ac925e30efce2ebc43b856 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2532 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-26AMD Inagua: buildOpts.c: Adapt whitespace to coding stylePaul Menzel
Mainly replace spaces by tabs and format comments correctly. Commit »Inagua: Indent and wihtespace cleanup« (f03360f3) [1] was unfortunately incomplete and also used spaces instead of tabs in some cases. Hopefully fix this once and for all to have a template for the other boards. [1] http://review.coreboot.org/547 Change-Id: If15c797581dfefe2a57cd6f26e5bdac4cdd014dd Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2526 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-26AGESA: skip s3_resume.h if CONFIG_HAVE_ACPI_RESUME is disabledJens Rottmann
Commit »AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'« (22ec9f9a) [1] introduced a check throwing an error if S3_DATA_SIZE isn't big enough. However without CONFIG_HAVE_ACPI_RESUME the variable S3_DATA_SIZE isn't defined at all and compilation will fail if s3_resume.h is included. This patch makes it again possible turn off HAVE_ACPI_RESUME relatively easily in Parmer/Thatcher/Persimmon's Kconfig if you don't care about S3 and don't want flash writes on every boot. [1] http://review.coreboot.org/2383 Change-Id: I999e4b7634bf172d8380fd14cba6f7f03468fee3 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/2528 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-02-26AMD Fam14 boards: reduce unnecessary differences, 2nd attemptJens Rottmann
This patch reduces unnecessary differences between AMD Inagua, Persimmon, Union Station, South Station and Asrock E350M1. It's only cosmetical, but makes them a little bit easier to compare. This is the remainder of the original http://review.coreboot.org/2464, parts of which somehow got lost in a flurry of refactoring and splitting patches. Change-Id: I034228be9edaaa4122506763d7bb4158f8e0ec53 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2529 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-26Revert "AMD S3: Program the flash in a bigger data packet"Dave Frodin
This reverts commit ca6e1f6c04c96c435bdbf30a1b88cab0e5be330b. The packet size changes ends up corrupting the flash when booting Persimmon. I did figure out that the maximum number of bytes that can be sent is actually 8 bytes according to the sb800 spec. There must be additional problems beyond that since setting the packet size to 8 still causes problems. Change-Id: Ieb24247cf79e95bb0e548c83601dfddffbf6be59 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/2509 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2013-02-25AMD Southbridge: Add RTC init to lpc_initMike Loptien
Adding RTC init code to the Southbridge initialization code in 'lpc_init'. This initializes the RTC so that the Date Alarm register is set to a valid value (0x00) at startup. By setting the Date Alarm register to 0x00, it does not get evaluated along with the seconds, minutes, and hours when running 'fwts s3'. Information about fwts (Firmware Test Suite) can be found here: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same edit made to the CIMX SB800 titled 'AMD/Persimmon: Add RTC init to CIMX SB800' with commit ID: c4d3d which can be viewed here: http://review.coreboot.org/#/c/2488/ Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2510 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-25Supermicro H8SCM & H8QGI: Fix printk warningsMartin Roth
Changes: - Fix printk warnings for these two platforms by getting rid of the l length specifier and casting to unsigned int. This gets rid of a bunch of warnings like this one: agesawrapper.c:279, GNU Compiler 4 (gcc), Priority: Normal format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'UINT32' [-Wformat] Notes: - This is the same change that was done for Tyan s8226 in change: ddff32eb - http://review.coreboot.org/#/c/2451/ Tyan S8226: Fix printk warnings - I have not tested this change on either of these platforms, I have just compiled it. Change-Id: I46b4c13fde7473cd2a084c7c7cb5c893f1731b02 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2502 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25AMD Southstation: Fix final warningMartin Roth
Changes: - Add #include of delay.h in mainboard.c to pick up declaration of mdelay function. Notes: - This fixes this warning: mainboard.c:69, GNU Compiler 4 (gcc), Priority: Normal implicit declaration of function 'mdelay' [-Wimplicit-function-declaration] Change-Id: I72f333cd87215a7fc1e62d1d7ee4b2395444b03e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2501 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25AMD Fam14 boards: Set P_BLK length to 6 for all processorsPaul Menzel
Currently on for example on AMD Persimmon and ASRock E350M1 Linux complains, that the PBLK length is invalid [1]. ACPI: Invalid PBLK length [0] Consequently, frequency scaling might not work correctly, though for these two boards it seems to work according to PowerTOP. Indeed, according to the ACPI specification [2], setting PBlockLength to 0 is only allowed if there is no PBlockAddress. Otherwise it has to be set to 6. 18.5.93 Processor (Declare Processor) […] PBlockAddress provides the system I/O address for the processors register block. Each processor can supply a different such address. PBlockLength is the length of the processor register block, in bytes and is either 0 (for no P_BLK) or 6. With one exception, all processors are required to have the same PBlockLength. The exception is that the boot processor can have a non-zero PBlockLength when all other processors have a zero PBlockLength. It is valid for every processor to have a PBlockLength of 0. And that is exactly what Linux is checking in `drivers/acpi/processor_driver.c` [3]. static int acpi_processor_get_info(struct acpi_device *device) { […] /* * On some boxes several processors use the same processor bus id. * But they are located in different scope. For example: * \_SB.SCK0.CPU0 * \_SB.SCK1.CPU0 * Rename the processor device bus id. And the new bus id will be * generated as the following format: * CPU+CPU ID. */ sprintf(acpi_device_bid(device), "CPU%X", pr->id); ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id, pr->acpi_id)); if (!object.processor.pblk_address) ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No PBLK (NULL address)\n")); else if (object.processor.pblk_length != 6) printk(KERN_ERR PREFIX "Invalid PBLK length [%d]\n", object.processor.pblk_length); else { pr->throttling.address = object.processor.pblk_address; pr->throttling.duty_offset = acpi_gbl_FADT.duty_offset; pr->throttling.duty_width = acpi_gbl_FADT.duty_width; pr->pblk = object.processor.pblk_address; /* * We don't care about error returns - we just try to mark * these reserved so that nobody else is confused into thinking * that this region might be unused.. * * (In particular, allocating the IO range for Cardbus) */ request_region(pr->throttling.address, 6, "ACPI CPU throttle"); } […] } This issue has proliferated to all AMD based boards so fix it for all of them by setting P_BLK length to 6. The DSDT of for example AMD Parmer and AMD Thatcher also set it to 6 everywhere so this solution is taken instead of setting the P_BLK system I/O base to 0 for all but the first processor which is how it is done for earlier AMD based boards. As note having to set this manually should not be needed and this should be autogenerated as done for most of the Intel boards and the AMD K8 based boards (`src/cpu/amd/model_fxx/powernow_acpi.c`). [1] http://www.coreboot.org/pipermail/coreboot/2013-January/073636.html [2] http://acpi.info/DOWNLOADS/ACPIspec40a.pdf [3] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/acpi/processor_driver.c;h=e83311bf1ebdaaaea1adbf2de1351cca907d3465;hb=5da1f88b8b727dc3a66c52d4513e871be6d43d19#l351 Tested-by: Paul Menzel <paulepanter@users.sourceforge.net> • ASRock E350M1: Tested-by: Paul Menzel <paulepanter@users.sourceforge.net> • AMD Persimmon: Tested-by: Martin Roth <martin.roth@se-eng.com> Change-Id: Ie79fe4812532d124cc81747c75a4f3d88d00531c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2189 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-25Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) doesJens Rottmann
USB ports 0-4 are handled by PCI devices 12.0 (OHCI) and 12.2 (EHCI). 12.1 simply does not exist, so remove it from devicetree.cb. While at it make the comment more detailed. Likewise for all USB ports. USB device 14.6 is the Broadcom GbE MAC integrated in the Hudson-E1. Add it to devicetree.cb. It's used on Inagua (on), but not on Persimmon (off). Change-Id: Idea27b3390fa4470f2592e79fdd633d5a218b97b Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2463 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-25AMD boards: ACPI DSDT: Use COREBOOT for the OEM Table ID fieldPaul Menzel
The DSDT header contains the fields OEMID and OEM Table ID. See for example ACPI specification 4.0a [1] 5.2.11.1 Differentiated System Description Table (DSDT) on page 135. There Table 5-16 contains the descriptions. Field Byte Length Byte Offset Description =================================================== OEMID 6 10 OEM ID OEM Table ID 8 16 The manufacture model ID. Currently in coreboot there is no common method what to put in these fields. Mostly Intel based boards populate it with "CORE " ore "COREv4" and AMD based boards populate it with the board vendor and model number, abbreviated appropriately to fit into these fields. On most boards the proprietary vendor BIOS seems to leave these fields – displayed with `sudo dmidecode` under System Information – blank To Be Filled By O.E.M. and fill out the Base Board Information with the board vendor and model name. In [2] Jens Rottmann argues that the this is really just the table ID used for naming it and that »99% of the DSDT code is not board specific«. Both approaches seem to have their advantages, but using the second one, developers often seem to forget to update them (for example AMD Thather). The current situation is at least not optimal. and therefore at least unify the string in the OEM Table ID. If unifying the OEM ID is also a good idea this should be done too. If later on it should be decided that the board vendor and model should be used again, this should be somehow derived from Kconfig. The following command was used for the change [3]. $ git grep -l '\/\* TABLE ID \*\/' | xargs sed -i '/TABLE ID/s/"\([^"]*\)"/"COREBOOT"/' This patch is split out from [2]. [1] http://www.acpi.info/spec40a.htm [2] http://review.coreboot.org/#/c/2464/ [3] http://stackoverflow.com/questions/5207838/sed-regex-matching-text-between-to-double-quotes-when-a-certain-text-appears-i Change-Id: Iec98c615ce37f928abc1b500eff5aa865d772cb2 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2472 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25google/snow: enable GPIO entries and CHROMEOS in buildingRonald G. Minnich
These were not separable or it would have been two CLs. Enable CHROMEOS configure option on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. Add a chromeos.c file for snow, needed to build. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. We are getting further into the process of actually booting a real kernel. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2467 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25QEMU x86: northbridge.c: Name enabling device function to `northbridge_enable`Paul Menzel
Similar to the discussion on the coreboot list [1] Am Freitag, den 22.02.2013, 02:17 +0100 schrieb Peter Stuge: […] > Function names should try to be descriptive. "enable_dev" is not very > descriptive. I like "mainboard_enable" because it makes output such > as > > printk("%s: foo", __func__); > > useful. rename the function for the northbridge to `northbridge_enable`. [1] http://www.coreboot.org/pipermail/coreboot/2013-February/074549.html Change-Id: I262311ec511e394550330214621b8c37780c1d4e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2496 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25Persimmon: Fix warning, enable warnings as errorsMartin Roth
- Fix redefinition warning for SB_GPIO_REG50 introduced in commit fa8702cf - http://review.coreboot.org/#/c/2446/ Persimmon: adapt PCIe reset code copied from Inagua to actually match Persimmon The warning being fixed is: SB800.h:1491, GNU Compiler 4 (gcc), Priority: Normal "SB_GPIO_REG50" redefined [enabled by default] - Enable warnings as errors so no more warnings will be accidentally committed. Change-Id: Ib443b2bd2067f0b7d5f93f79170899a0f8f61060 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2494 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25mainboard.c: Name enable_dev function uniformly `mainboard_enable`Paul Menzel
To reduce the differences between these file name the enabling device function in the directory `src/mainboard` uniformly `mainboard_enable` [1]. Thanks to the awesome help of gnomon and BlastHardcheese in the IRC channel #sed on <irc.freenode.net>. gnomon came up with the following command to do the actual work. $ cd src/mainboard $ for f in */*/mainboard.c ; \ > do src="$(awk '/\.enable_dev = /{v=$NF; sub(/,$/,"",v); print v}' "$f")" ; \ > [[ -z $src ]] && continue ; \ > printf '%s\n' "g/${src}/s/${src}\([,(]\)/mainboard_enable\1/p" w | ed -s "$f" ; \ > done `src/mainboard/digitallogic/msm586seg/mainboard.c` and `src/mainboard/technologic/ts5300/mainboard.c` had to be adapted manually as no comma was used separating the struct members. And with the following statement, gnomon is even more likable! My pleasure entirely. Good luck with coreboot; I'm a big fan of the project. [1] http://www.coreboot.org/pipermail/coreboot/2013-February/074548.html Change-Id: Ife9cd0c2d9cc1ed14afc6d40063450553f06a6c6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2493 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25Technologic TS5300: mainboard.c: Move { to next linePaul Menzel
This is coreboot’s coding style. Change-Id: I7441f2c1927a49a3b7171112b7798dae6b56cfb5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2492 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Bernhard Urban <lewurm@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25ARMv7: Simplify div64Stefan Reinauer
We don't need the overly complex optimized version, since we're only doing this in very few non-critical places. Also, add the div* files to the bootblock, they're needed if we do printk. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I83bd766d4b03b488326ade1c13b7c364a7119e7b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2508 Tested-by: build bot (Jenkins)
2013-02-24Siemens SITEMP G1P1: mainboard.c: Rename `init` to `mainboard_init`Paul Menzel
This is the common way to name that function, so unify that. Change-Id: I8a01051bd304039662894b89eed53ce14dde98b6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2491 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-24AMD f14 vendorcode: Fix warningMartin Roth
Add brackets around initializer in #define for PCIE_DDI_DATA_INITIALIZER to fix the warning: PlatformGnbPcie.c:89, GNU Compiler 4 (gcc), Priority: Normal missing braces around initializer [-Wmissing-braces] This warning happens for Inagua and South Station Change-Id: I7d8f742dd8335b704b0493aa6e9eaebc3cc50b1e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2495 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-23Add support for Google's Chromebook PixelStefan Reinauer
Ladies and gentlemen, I'm very happy to announce coreboot support for the latest and greatest Google Chromebook: The Chromebook Pixel. See the link below for more information on the Chromebook Pixel, and its exciting specs: http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel The device is running coreboot and open source firmware on the EC (see ChromeEC commit for more information on that exciting topic) Change-Id: I03d00cf391bbb1a32f330793fe9058493e088571 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2482 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-23AMD based boards: platform_cfg.h: Replace `_*BOARDNAME*_CFG_H_` with ↵Jens Rottmann
`_PLATFORM_CFG_H_` Reduce unnecessary differences between AMD based boards only using the file `platform_cfg.h` for configuration making them a little bit easier to compare. Inagua & co. mention the board name in several places which are really not that board specific. Sometimes people even forget to change it: Union Station’s platform_cfg.h starts with "#ifndef _PERSIMMON_CFG_H_". Funny. Change that to "_PLATFORM_CFG_H_" everywhere. The following command was used. $ find . -name platform_cfg.h | xargs sed -i '/_CFG_H_/s/_.*_/_PLATFORM_CFG_H_/' More boards seem to use that kind of naming (`git grep _CFG_H_`) but it is not certain that this will not break anything as for example the board AMD Dinar also has header files for configuration stuff for the north- and southbridge. $ git grep _CFG_H_ […] src/mainboard/amd/dinar/platform_cfg.h:#ifndef _PLATFORM_CFG_H_ src/mainboard/amd/dinar/platform_cfg.h:#define _PLATFORM_CFG_H_ src/mainboard/amd/dinar/platform_cfg.h:#endif //_PLATFORM_CFG_H_ src/mainboard/amd/dinar/rd890_cfg.h:#ifndef _RD890_CFG_H_ src/mainboard/amd/dinar/rd890_cfg.h:#define _RD890_CFG_H_ src/mainboard/amd/dinar/rd890_cfg.h:#endif //_RD890_CFG_H_ src/mainboard/amd/dinar/sb700_cfg.h:#ifndef _SB700_CFG_H_ src/mainboard/amd/dinar/sb700_cfg.h:#define _SB700_CFG_H_ src/mainboard/amd/dinar/sb700_cfg.h:#endif //_SB700_CFG_H […] Change-Id: Ida15fa6a7adfc770240ac30e795946000dae3f16 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2464 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-23AMD/Persimmon: Add RTC init to CIMX SB800Mike Loptien
Adding RTC init code to the Southbridge initialization code in 'late.c'. This initializes the RTC so that the Date Alarm register is set to a valid value (0x00) at startup. By setting the Date Alarm register to 0x00, it does not get evaluated along with the seconds, minutes, and hours when running 'fwts s3'. Information about fwts (Firmware Test Suite) can be found here: https://wiki.ubuntu.com/Kernel/Reference/fwts This was tested on a Persimmon but will apply to other mainboards as well. Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2488 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-22Add support for Google ChromeECStefan Reinauer
Google ChromeEC is an EC with completely open source firmware. See https://gerrit.chromium.org/gerrit/gitweb?p=chromiumos/platform/ec.git;a=summary for the EC firmware source code (aka more information about the ChromeEC) This patch adds support for the ChromeEC on coreboot's side. Great thanks to the ChromeEC team for this amazing work. It's another important milestone towards a free and open firmware stack on modern hardware. Change-Id: Iace78af9d291791d2f5f80ccca1587b418738cec Signed-off-by: Stefan Reinauer <reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/2481 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-22*/acpi_tables.c: Use ALIGN macroPatrick Georgi
At the request of Paul Menzel, I reran an old classic of a coccinelle script: @@ expression E; @@ -(E + 7) & -8 +ALIGN(E, 8) @@ expression E; @@ -(E + 15) & -16 +ALIGN(E, 16) Change-Id: I01da31b241585e361380f75aacf3deddb13d11c3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-22libcbfs: Fix legacy CBFS API, typosHung-Te Lin
Pulling CBFS fix from libpayload: http://review.coreboot.org/#/c/2455/2 get_cbfs_header expects CBFS_HEADER_INVALID_ADDRESS (0xffffffff) instead of NULL when something is wrong. Also, fix typo. Change-Id: I7f393f7c24f74a3358f7339a3095b0d845bdc02d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2457 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-21AMD Fam14 boards: Unify `acpi_table.c` by mainly using Inagua’s onePaul Menzel
There were just whitespace differences and three boards did not contain printk(BIOS_DEBUG, "alib\n"); dump_mem(ssdt, ((void *)alib) + alib->length); which is enclosed `#if DUMP_ACPI_TABLES == 1` to dump the ACPI tables. Basically the whitespace in the license header in Inagua’s file was fixed and then the file copied over to the other directories. Change-Id: I23f73acad427b5ec14cf51651af67240871f7488 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2470 Tested-by: build bot (Jenkins) Reviewed-by: Alvaro G. <andor@pierdelacabeza.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-21AMD boards: Fix typo `@brief` in commentPaul Menzel
The following command was used to correct the typo. $ git grep -l @breif | xargs sed -i 's/@breif/@brief/' Change-Id: If0b579279de3c41571b9cda643836f5748a752a2 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2473 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-21Persimmon: platform_cfg.h: Declare codec arrays as `static const`Jens Rottmann
From ISO C99 standard: »The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature.« Found at <http://www.approxion.com/?p=41>. Change-Id: Iee7878affb2a5d157a94763083689d75e8218b2f Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2474 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-21Persimmon: dimmSpd.c: Use spaces for alignment of if-predicatePaul Menzel
The relational operators in the if-predicate are aligned in all `dimmSpd.c` files so revert part of the change in commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303@gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 to remove the incorrectly introduced tabs and to unify that. It might contradict the current coding style but it is even used in the latest code as seen in the following file. src/northbridge/amd/agesa/family15tn/dimmSpd.c Change-Id: Ib611267f99090d0830bdc2319527389f193ea1eb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2471 Reviewed-by: Alvaro G. <andor@pierdelacabeza.com> Tested-by: build bot (Jenkins)
2013-02-21Persimmon: Indent commentPaul Menzel
This was overlooked in the following commit. commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303@gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 Change-Id: If6bf4836b46077614a04c1e106c241a4f97da166 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2468 Tested-by: build bot (Jenkins) Reviewed-by: Alvaro G. <andor@pierdelacabeza.com>
2013-02-21AMD Fam14 boards: dimmSpd.c: Set `iobase` to `SMBUS0_BASE_ADDRESS` instead ↵Jens Rottmann
of `0xB00` For AMD Inagua, the following two commits commit 01f7ab93359ae0fee5784d35effbcbe0b596df18 Author: Kerry Sheh <shekairui@gmail.com> Date: Thu Jan 19 13:18:36 2012 +0800 Inagua: Synchronize AMD/inagua mainboard. Reviewed-on: http://review.coreboot.org/542 and commit d91c9b7e3cb9fdaeb9399a21907996130f3120bb Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 10:59:55 2011 -0600 AMD Inagua platform updates Reviewed-on: http://review.coreboot.org/136 replaced the constant `iobase` is set to by the define `SMBUS0_BASE_ADDRESS` from `OEM.h`. Do the same for AMD Persimmon, South Station, Union station and ASRock E350M1. Change-Id: If095cd9d9b28b118b4072c7c9d345bf620b774c9 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2453 Tested-by: build bot (Jenkins)
2013-02-21AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'Zheng Bao
Currently the size of the volatile storage for S3 reserved in the image is hardcoded to 32768 bytes. Make that configurable by introducing the Kconfig 'S3_DATA_SIZE'. As the storage space is needed for storing non-volatile, volatile and MTRR data, add a check if the size is big enough. Change-Id: I9152797cf0045c8da48109a9d760e417717686db Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2383 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-21ARMV7: create a correct LB_SERIAL table entryRonald G. Minnich
If CONFIG_CONSOLE_SERIAL is set, and we can call the standard function and get a non-zero uart address, then we create an lb table entry. The code was mostly right, just needed a tweak. Change-Id: I5b36c7b4e580a23319b7ba92cc8ad61592b1757a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2466 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-20Whitespace: Replace tab character in license text with two spacesPaul Menzel
For whatever reason tabs got inserted in the license header text. Remove one occurrence of that with the following command [1]. $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,' [1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2460 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-20Persimmon: Replace tab with space in address in license headerPaul Menzel
The following commit was too eager replacing spaces with tabs. commit 36abff1dc8e74beafa47ad83de17416681970916 Author: Marc Jones <marcj303@gmail.com> Date: Mon Nov 7 23:26:14 2011 -0700 Cleanup Persimmon mainboard whitespace. Reviewed-on: http://review.coreboot.org/427 Fix that with the following command. $ git grep -l 'Floor, Boston, MA'$'\t''02110-1301 USA' | xargs sed -i 's/Boston, MA[ ]*02110-1301 USA/Boston, MA 02110-1301 USA/' Change-Id: Ia118a8c19d94ce1f1048280a0f1d49d447cfa2a7 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2461 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-20armv7: Don't let users set ram parameters that are fixed in hardware.Ronald G. Minnich
The SDRAM base is fixed in hardware. It makes no sense to make it configurable. The TEXT start is a magic number that should also be fixed, not settable. Change-Id: Ie44cc5c8da1dc38fc00eb602c4a295b045ca5364 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2465 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-20ARMV7: minor tweaks to inter-stage calling and payload handling.Ronald G. Minnich
Payloads, by design, can return. There's lots of mechanism in the payload code to support it, and the chooser payload relies on it. Hence, we should not mark the function call in exit_stage as noreturn. Not all ARM have unified caches, and it's not always easy to tell what to do. So we are very paranoid. Before we call between stages, we should carefully flush the dcache to memory and invalidate the icache. This may be more than is necessary on all architectures but it doesn't really hurt for the most part. So compile cache management code into all stages, and call the flush dcache/invalidate icache from all stages. Change-Id: Ib9cc625c4dfd2d7d4b3c69a74686cc655a9d6484 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2462 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-19Tyan S8226: Fix incompatible pointer warningMartin Roth
Fix warning: mptable.c:52, GNU Compiler 4 (gcc), Priority: Normal passing argument 3 of 'mptable_write_buses' from incompatible pointer type [enabled by default] mptable_write_buses is expecting a pointer to an int, so I changed the U8 isa_bus to an int to match. A U8 doesn't make sense if the value could be greater than 255 - certainly unlikely, but possible since the value of isa_bus gets set to the maximum PCI bus number + 1. Change-Id: I7ea416f48285922d6cf341382109993fd3f6405c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2450 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19Tyan S8226: Fix integer truncated warningMartin Roth
Fix Warning: sb700_cfg.c:129, GNU Compiler 4 (gcc), Priority: Normal large integer implicitly truncated to unsigned type [-Woverflow] The issue here was that an 8 bit value was being placed into a 2-bit bitfield. $ more src/vendorcode/amd/cimx/sb700/SBTYPE.h […] UINT32 AzaliaSdin0 :2; //6 UINT32 AzaliaSdin1 :2; //8 UINT32 AzaliaSdin2 :2; //10 UINT32 AzaliaSdin3 :2; //12 $ more src/mainboard/tyan/s8226/sb700_cfg.h […] * SDIN0 is define at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin * SDIN1 is define at BIT2 & BIT3 * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN #define AZALIA_SDIN_PIN 0x2A #endif […] $ more src/mainboard/tyan/s8226/sb700_cfg.c […] sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; […] The 8 bit value 0x2A (binary 00 10 10 10), was being used incorrectly – I believe the original intent of this value was to enable the SDIN pins 0, 1, & 2. Because it was getting truncated as it was put into AzaliaSdin0, this wasn't happening and only SDIN0 was being enabled. I am leaving only SDIN0 enabled at this point to as not change the actual behavior on the platform. Change-Id: Icaeb956926309dbfb5af25a36ccb842877e17a34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2452 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-19Tyan S8226: Fix printk warningsMartin Roth
Fix 84 warnings all like this one: agesawrapper.c:289, GNU Compiler 4 (gcc), Priority: Normal format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'UINT32' [-Wformat] Fixed by getting rid of the l length specifier and casting to unsigned int. Change-Id: Ic143c1034f760fa5efb2220aa33861e399ddd708 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2451 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-19Inagua+children: fix simple copy & paste error in code to reset PCIe slotsJens Rottmann
Looking at AssertSlotReset, the comments and all other case's it's obvious this is a simple copy & paste error where someone just forgot to change one occurrance of the GPIO nr. Also the AMD Inagua schematics show that GPIO02 is what they really meant. Also forward the fix to boards copied from Inagua (AMD South Station, Union Station, Asrock E350M1). Change-Id: I6b9a3d473245fa27604b2f148a730290277a88ed Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2445 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-19exynos5250: add uartmem_getbaseaddr() in uart driverDavid Hendricks
Change-Id: I76545ad3fca3cc0997050253be77ea83b5d74cb2 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2423 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-19move uartmem_getbaseaddr() to generic uart headerDavid Hendricks
This moves uartmem_getbaseaddr() from an 8250-specific header to the generic uart header. This is to accomodate non-8250 memory-mapped UARTs. Change-Id: Id25e7dab12b33bdd928f2aa4611d720aa79f3dee Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-19armv7/snow: add CPU and RAM resources via allocatorDavid Hendricks
This adds necessary device operations to add CPU and RAM resources. Change-Id: Ief8f66627ef37f4fa786bfc3f7899529d3e5b037 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2419 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-19snow: add cpu_cluster and domain resources via devicetree.cbDavid Hendricks
This patch will cause the resource allocator to actually set aside the memory resources using methods in the previous patch. The coreboot table output will include "RAM" entries (there were none before): coreboot memory table: 0. 0000000040400000-00000000bff001ff: RAM 1. 00000000bff00200-00000000bff00fff: CONFIGURATION TABLES 2. 00000000bff01000-00000000bfffffff: RAM Change-Id: I5cd76e93fc232fdae1754253efb4e9269b3a20c0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2420 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-19build system: Retire REQUIRES_BLOBPatrick Georgi
REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory, builds failed when all files were configured to point to other sources. This change modifies the blob mechanism so that cbfs-files can be tagged as "required" with some specification what is missing. If the configured files can't be found (wrong path, missing file), the build system returns a list of descriptions, then aborts. Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2418 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19AMD S3: Change S3_VOLATILE_POS to S3_DATA_POSZheng Bao
S3_DATA_POS defines address where the whole S3 data is stored. Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2438 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19RTC: Use the correct index when setting the default monthDave Frodin
Change-Id: I947a8b7ccd6141f164d1e63f7b8f524efa6c00f2 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/2442 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-19armv7: init stack to 0xdeadbeef to detect stack overflowsDavid Hendricks
This adds a simple loop which initializes the stack to 0xdeadbeef which is used by checkstack(). Change-Id: I8aecf7bfb1067de68c4080c1fcb7eefa28fd04a7 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2421 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-18Persimmon: drop useless DDR3 voltage code copied from InaguaJens Rottmann
Inagua can use GPIOs 178,179 to switch VMEM to 1.5, 1.35 or 1.25 V, which it does according to data read from the SO-DIMM's SPD EEPROM. On Persimmon (according to DB-FT1 rev. D schematics) both GPIOs are unconnected, there is no way to change the 1.5 V DDR3 voltage (save unsoldering a resistor). The whole code copied over from Inagua is useless. Removed the code, instead a comment hints at Inagua, for people who do designs based on Persimmon but do have a way to change VMEM. The line ...->DDR3Voltage = VOLT1_5; is supposed to make the AGESA DDR3 code select the RAM timings for the actually supplied voltage instead of the hoped-for but unavailable lower voltage. I have no idea how to test this, but in any case it can't hurt. Change-Id: Id098e09418b665645814a6ee2d41a3bff72238ba Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2448 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-18Persimmon: disable APU PCIe port 3Jens Rottmann
According to DB-FT1 rev. D schematics the APU PCIe lane 3 is unconnected. Reflect this fact in the mainboard code. Change-Id: Ic98f4a63ef971628df7fbf97f56b80ebe7cb8517 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2447 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-18Persimmon: adapt PCIe reset code copied from Inagua to actually match PersimmonJens Rottmann
Comparing Persimmon and Inagua schematics and Coreboot code show the PCIe reset code has been blindly copied even though it doesn't suit the Persimmon at all. The Inagua can employ GPIOs 21, 25, 02 to manually reset devices on APU PCIe lanes 0/1, 2, 3 respectively. (Appearently the motivation for this is to revive buggy PCIe gen1 devices which got confused by PCIe gen2 signal training.) However the Persimmon not only doesn't support this, it even needs these 3 pins for the PCI interface! Instead it uses GPIO50 to reset devices on lanes 0-2 all at once. Lane 3 is unconnected anyway. This patch adapts the Persimmon mainboard code according to the DB-FT1 rev. D schematics. Change-Id: I05a657d9bf8cc59acc4f5174eb20375165c860c7 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2446 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-18Kconfig: string option doesn't work properly inside choice sectionJens Rottmann
At least not in menuconfig. Move it after the endchoice. Change-Id: I87d2f70e7c1fbe539cd78cb602a39335b2886d8d Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2443 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-18AMD S3: Program the flash in a bigger data packetZheng Bao
According to spi.c in src/southbridge/amd/agesa/hudson readwrite = (bytesin + readoffby1) << 4 | bytesout; We can see that Hudson limits the SPI programming data packet size as 15. We used to write data to SPI in dword mode. It didn't take full advantage of the data packet size. We need to leverage that to speed up programming time. Change-Id: I615e3c8e754e58702247bc26cfffbedaf5827ea8 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2306 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-18AMD S3: Fix typo vol*a*tile in southbridge KconfigZheng Bao
Change non-volitile to non-volatile. Change-Id: Idfc7db3b3dcf078f0f3134fc62679bed439a4fd2 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2437 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-18AMD Family12h: Fix warningsMartin Roth
Add needed prototypes to .h files. Remove unused variables and fix types in printk statements. Add #IFNDEFs around #DEFINEs to keep them from being defined twice. Fix a whole bunch of casts. Fix undefined pre-increment behaviour in a couple of macros. These now match the macros in the F14 tree. Change a value of 0xFF that was getting truncated when being assigned to a 4-bit bitfield to a value of 0x0f. This was tested with the torpedo build. This fixes roughly 132 of the 561 warnings in the coreboot build so I'm not going to list them all. Here is a sample of the warnings fixed: In file included from src/cpu/amd/agesa/family12/model_12_init.c:35:0: src/include/cpu/amd/amdfam12.h:52:5: warning: redundant redeclaration of 'get_initial_apicid' [-Wredundant-decls] In file included from src/cpu/amd/agesa/family12/model_12_init.c:34:0: src/include/cpu/amd/multicore.h:48:5: note: previous declaration of 'get_initial_apicid' was here src/northbridge/amd/agesa/family12/northbridge.c:50:10: warning: no previous prototype for 'get_node_pci' [-Wmissing-prototypes] src/northbridge/amd/agesa/family12/northbridge.c: In function 'get_hw_mem_hole_info': src/northbridge/amd/agesa/family12/northbridge.c:302:13: warning: unused variable 'i' [-Wunused-variable] src/northbridge/amd/agesa/family12/northbridge.c: In function 'domain_set_resources': src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat] src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat] src/northbridge/amd/agesa/family12/northbridge.c:716:1: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat] In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0, from src/northbridge/amd/agesa/family12/northbridge.c:38: src/vendorcode/amd/agesa/f12/AGESA.h:1282:0: warning: "TOP_MEM" redefined [enabled by default] In file included from src/northbridge/amd/agesa/family12/northbridge.c:34:0: src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0, from src/northbridge/amd/agesa/family12/northbridge.c:38: src/vendorcode/amd/agesa/f12/AGESA.h:1283:0: warning: "TOP_MEM2" redefined [enabled by default] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetNumberOfComplexes': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:99:19: warning: operation on 'ComplexList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfPcieEnginesList': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:126:20: warning: operation on 'PciePortList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfDdiEnginesList': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:153:19: warning: operation on 'DdiLinkList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetComplexDescriptorOfSocket': src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:225:17: warning: operation on 'ComplexList' may be undefined [-Wsequence-point] src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c:246:1: warning: no previous prototype for 'PcieFmForceDccRecalibrationCallback' [-Wmissing-prototypes] In file included from src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c:58:0: src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h:120:5: warning: large integer implicitly truncated to unsigned type [-Woverflow] And fixed a boatload of these types of warning: src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress': src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:687:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:694:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:701:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:702:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:705:23: warning: assignment makes integer from pointer without a cast [enabled by default] src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:709:21: warning: assignment makes integer from pointer without a cast [enabled by default] Change-Id: I97fa0b8edb453eb582e4402c66482ae9f0a8f764 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2348 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-18AMD S3: Include the s3_resume.h only when S3 is enabled.Zheng Bao
Change-Id: I9a6c4f61e5dda6665f92c8526bb26a458ee2b739 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2384 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-16exynos5250: clean out some stale IRAM-related config variablesDavid Hendricks
This cleans out some obsolete Kconfig variables pertaining to IRAM usage. Change-Id: Ie53f5f7204eadc3a3dddc739d2b4b6237242b198 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2417 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-16armv7/exynos5250: fix usage of _stack and _estackDavid Hendricks
This patch fixes up the usage of stack pointer and regions. The current approach only works by coincidence, so this fixes a few things at once to get it into a working state and allow us to use checkstack() again: - Add a STACK_SIZE Kconfig variable. Earlier on it was evaluated to 0. - Assign _stack and _estack using CPU-specific Kconfig variables since it may reside elsewhere in memory (not necessarily DRAM). - Make the existing IRAM stack variables more useful in this context. Change-Id: I4ca5b5680c9ea7e26b1b2b6b3890e028188b51c2 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2416 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-15ARMv7: Drop u-boot type remainsStefan Reinauer
Just a mechanical cleanup. Change-Id: I0815625e629ab0b7ae6c948144085f1bd8cabfb5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2408 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-15Exynos5250: Drop unused file ehci-s5p.hStefan Reinauer
Change-Id: I39014377af718766ef86c149e2d2da3d97eaa728 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2407 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-15OT200: add CMOS supportChristian Gmeiner
nvramtool works as expected. root@CHGM-DEV-OT200:~# /home/vis/nvramtool -a baud_rate = 19200 debug_level = Emergency Change-Id: Ia25dc5b4f0ed3a2dd7cc67b7d3174db3a6eff70e Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/2382 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-02-15Exynos: Drop dead code in cpu.hStefan Reinauer
Change-Id: Ibb5fa27a0d45ddd8f57e8e8c28961d204e2ef1e3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2409 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-15ARMv7: straighten out reset codeStefan Reinauer
We don't need three different implementations. Change-Id: Ie7b5fa90794676ea38838454a33e8e9188428eb7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2406 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-15Exynos5: Drop S5P directory and merge filesStefan Reinauer
s5p-common mostly contained duplicate files, drop the whole directory and merge the few pieces that we are using into exynos5-common. Change-Id: I5f18e8a6d2379d719ab6bbbf817fe15bda70d17f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2405 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-15ARMv7: Drop sr32, and wait_on_valueStefan Reinauer
They're unused. Also drop some unused defines in system.h Change-Id: Ia5afc3a676a4a94787041430f05d08f333033c73 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2404 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-02-15ARMv7: Fix include file names in memset & memcpyStefan Reinauer
We don't have asm/ Change-Id: I7f80f47e9d7f457b7a5a64603c59b14d3b536a8c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2403 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-15ARMv7: Drop more unused filesStefan Reinauer
Change-Id: I0dd83f96d2a9598e9677d1b0b114229de6724287 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2401 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-15Drop include/arch-generic/div64.hStefan Reinauer
It's unused. Change-Id: Id67ca754ff7ad148ff1ecd4f1e5c986a4e7585a8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2400 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-15Exynos: Drop unused include filesStefan Reinauer
Change-Id: Ib533938446a289167725f5beda77c2ee5236e8a5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2395 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-02-14ARMv7: drop multiboot supportStefan Reinauer
Multiboot is an x86 only thing. Drop support on ARM. Change-Id: I13fafa464a794206d5450b4a1f23a187967a8338 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2392 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14Exynos: Drop duplicate copy of watchdog.hStefan Reinauer
Change-Id: I4c9bfa9eb7708420dc42c16bc152d761d2bdfee3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2391 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14ARMv7: Drop SKIP_LOWLEVEL_INITStefan Reinauer
It's not used. Change-Id: I713d60209815f0aad93f5d4d3afef9f825db427e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2393 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-02-14Exynos5250: Drop SHA implementationStefan Reinauer
We don't need SHA in coreboot. Change-Id: I1985d5e2c74fac39ff9dcdba4c23bb34fa857ec7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2390 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-02-14Chromebooks: mainboard.c: Do not spell Chromebook in CamelCasePaul Menzel
»Chromebook« is the official spelling [1]. So correct that with the following command. $ git grep -l ChromeBook | xargs sed -i s,ChromeBook,Chromebook, The incorrect spelling was only used for the chip name. [1] http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html#hp-pav Change-Id: I9c19f399a3e3d36bd644ec375822daa384a14961 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2370 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-14Google Butterfly: thermal.h: Align macro contentPaul Menzel
Change-Id: I3729f9bf66fcd72fa8870bb56a9c253a7368c774 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2371 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14armv7: don't write a forward entry in coreboot tablesDavid Hendricks
We don't seem to need it, and it currently confuses the payload. (credit to Gabe Black for this, I'm just uploading it) Change-Id: I4e3a60eceb9b24e3bc8e50db431c1a731d1cdbae Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/2385 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14snow: Set up MMU after DRAM is workingDavid Hendricks
This was omitted earlier while we were debugging DRAM code (0a5bc7f). It was likely broken due to inconsistent units earlier on. Now that things are cleaned up and working, let's add it back in. Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2379 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14snow: remove superfluous printk's from romstage mainDavid Hendricks
These were left over from earlier debugging and are no longer needed. They don't indicate any status or useful info (other than which line of code has been executed). Error messages are available in case something needs attention. Change-Id: Ie09fac29c42908cb8924169e56d8927fb76f02da Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2386 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-13armv7/exynos: remove some stale files leftover from initial importDavid Hendricks
This removes some files leftover from the initial port. Some are leftover from U-Boot and some were leftover from the skeleton code derived from x86. There's a bit more that we'll get in another sweep. Change-Id: I325793ecb902b3b9430dcf531714ce025d201de6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2380 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-13armv7: use start and size parameters in mmu_setup()David Hendricks
mmu_setup() was originally written in U-Boot to utilize board-specific global data. Since we're trying to avoid that, we added start and size parameters so that board-specific info can be passed in via mainboard code. Let's start using it that way. Change-Id: I7d7de0e42bd918c9f9f0c177acaf56c110bf8353 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2378 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-12armv7: stages.c: Fix grammar: s,The is to,This is to,Paul Menzel
The comment introduced in commit 50c0a50ac6a3fa54ed1286e8b76f933701b6d053 Author: David Hendricks <dhendrix@chromium.org> Date: Thu Jan 31 17:05:50 2013 -0800 armv7: unify stage hand-off routines Reviewed-on: http://review.coreboot.org/2254 contained a typo, which is corrected now. Change-Id: I87f7cfa82fcd12b6961d3329e634b4c201cc047e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2372 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-12Google Butterfly: acpi/thermal.asl: Fix typo »The*re* is no …«Paul Menzel
The commit introducing support for the Google Butterfly Chromebook commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2 Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon Feb 11 11:11:36 2013 -0800 Add support for "Butterfly" Chromebook Reviewed-on: http://review.coreboot.org/2359 contains the typo, which is corrected now. Change-Id: I932f4cd248cac71c3ede39a7da97162e791827cb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2373 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-12Google Butterfly: gpio.h: Correct whitespace errorsPaul Menzel
Correct some whitespace inconsistencies introduced in the following commit. commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2 Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon Feb 11 11:11:36 2013 -0800 Add support for "Butterfly" Chromebook Reviewed-on: http://review.coreboot.org/2359 Change-Id: Ifeda7eb29ddf855cdfea41ddbd685441ede55756 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2374 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-12Google Parrot/Butterfly: fadt.c: Align macros correctlyPaul Menzel
The commits adding support for the Google Parrot Chromebook commit a7198b34ccf120df2a9e5b9f104812e96916ad08 Author: Stefan Reinauer <reinauer@chromium.org> Date: Tue Dec 11 16:00:47 2012 -0800 Add support for Google Parrot Chromebook Reviewed-on: http://review.coreboot.org/2026 and the Google Butterfly Chromebook commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2 Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon Feb 11 11:11:36 2013 -0800 Add support for "Butterfly" Chromebook Reviewed-on: http://review.coreboot.org/2359 had macros in `fadt.c` which were not aligned correctly and did not adhere to the coding style which uses just one space after `#define`. Fix this and use tabs instead of spaces everywhere. Change-Id: I1422c57a3bdc2faa29d2a6e2064e4d3aeed0f1cb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2375 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-12fix an error message in checkstack()David Hendricks
The order of some printk arguments were reversed. Change-Id: I5e8f70b79050b92ebe8cfa5aae94b6cd1a5fd547 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2364 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-12armv7: jump to ELF image using stage_exit()David Hendricks
This is just to get us to the payload. TODO: Do we want to implement any of the stuff from the x86 version, such as copying coreboot to a new location? Change-Id: Ia0544f111d7a1189ebd92d0ba3e11448eabd6252 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2363 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-02-12armv7: Add emulation/qemu-armv7 board.Hung-Te Lin
To simplify testing ARM implementation, we need a QEMU configuration for ARM. The qemu-armv7 provides serial output, CBFS simulation, and full boot path (bootblock, romstage, ramstage) to verify the boot loader functionality. To run with QEMU: export QEMU_AUDIO_DRV=none qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom Verified to boot until ramstage loaded successfully by QEMU v1.0.50. Change-Id: I1f23ffaf408199811a0756236821c7e0f2a85004 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2354 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-11spi-generic.h: Adapt include guardPatrick Georgi
Rename _SPI_H_ to _SPI_GENERIC_H_ to match recent file rename. Change-Id: I8b75e2e0a515fb540587630163ad289d0a6a0b22 Reported-by: Peter Stuge <peter@stuge.se> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2360 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-11Add support for "Butterfly" ChromebookStefan Reinauer
We're happy to announce coreboot support for the "Butterfly" Chromebook, a.k.a HP Pavilion Chromebook. More information at: http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html This commit also includes support for the ENE KB3940Q embedded controller running on Quanta's firmware. Change-Id: I194f847a94005218ec04eeba091c3257ac459510 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2359 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
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