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2024-10-28soc/mediatek/mt8196: Enable PCIe supportJianjun Wang
Enable PCIe support for mt8196. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I9c0aaa1c6da8c247b319e7ed2317dd871e276461 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84698 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28mb/google/rauru: Add mainboard_needs_pcie_initJianjun Wang
Add a trivial mainboard_needs_pcie_init implementation that always return true. For now, the storage types of rauru SKUs are still unknown. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I6b4f08e15f62da18aa37226075894f2827a9e7ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/84697 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28soc/mediatek/mt8196: Add PCIe driver and early init supportJianjun Wang
Add PCIe driver for MT8196 platform. According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. To ensure the 100ms delay requirement is met and to save delay time in the ramstage, add an early init data region to store the elapsed time since assertion. This will speed up the boot time by 100ms. PCIe port 1 and port 2 share the same PCIe resources, but PCIe port 2 is not used. Therefore, in mtk_pcie_pre_init(), make sure PCIe port 2 is reset to prevent interference with PCIe port 1. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I826a96822e88972bcd4966b6681797a646adf3d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-28soc/mediatek/common: Move PCIe definition to the common directoryJarried Lin
To reduce duplicate pcie.h in other SOC folder, mocw pcie.h to mediatek/common folder TEST=Build pass BUG=b:317009620 Change-Id: I8e29ed4027433700652b07b3461eeb8546d45c9b Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-27soc/intel/skylake/Makefile: Remove dead codeFelix Singer
This code is never reached since the hardware uses different SoCs. Besides, mainboard specific code should not be added to SoC code. Change-Id: Id82d5d0b829442c35c093974c06a029259838a9a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-10-26soc/intel/cmn/fast_spi: Improve debug message for SPI flash windowsSubrata Banik
This commit improves the debug messages when initializing SPI flash windows by adding the window type (Fixed Decode or Extended Decode) to the log output. This makes it easier to understand which window is being initialized and can help with debugging issues related to SPI flash access. w/o this patch: [INFO ] MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] MMAP window: SPI flash base=0x900000, Host base=0xf9900000, Size=0x700000 w/ this patch: [INFO ] Fixed Decode Window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] Extended Decode Window: SPI flash base=0x900000, Host base=0xf9900000, Size=0x700000 Change-Id: I904f70f42fa70ea06e6f49bd44631a8491463207 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-26mb/google/fatcat: Drop LOCK_CONFIG for GPP_D15 in early GPIO configSubrata Banik
Ideally lock configuration is not applicable for early GPIO configuration (like bootblock/romstage) and is only required for GPIO PAD configuration by later statge (like ramstage). The GPP_D15 pin was previously configured with LOCK_CONFIG in the early bootblock GPIO configuration. This is not necessary and prevents later boot stages from configuring this GPIO. Change-Id: Ie0e648b750d7579def39ed95eab862dc3245499c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com>
2024-10-25mb/google/brox/lotso: Enable BT audio offload configWentao Qin
Enable BT audio offload of WIFI_CNVI_WIFI6E or unprovisioned based on fw_config. BUG=b:373510270 TEST=Build and boot to Lotso. Verify the config from serial logs. w/o this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 0 ``` w/ this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 1 ``` Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Change-Id: I36f8c3fb24166c86d5fc4099fa9cde8cdecb9d49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84768 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-10-24soc/intel/common: Add PCIe device IDs for Snow RidgeYuchi Chen
This patch adds SPI and some accelerator device IDs for SNR platform. IDs are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0. Change-Id: I7bd135d788816e4c3c42ac937450cf8cdcea00bc Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84782 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-24mb/google/fatcat: add GPIO pad configure based on fw_configJeremy Compostella
BUG=b:348678529 TEST=on Google Fatcat board. Set the proper CBI fw_config bit(s) and check that the corresponding GPIO PADs are configured as expected value accordingly. Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d54 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamirbohra@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-24mb/google/fatcat: Ensure RW_SECTION_B starts at 16MB boundarySubrata Banik
This patch updates the flash map layout to guarantee that the RW_SECTION_B section starts at a 16MB boundary. TEST=Successfully builds google/fatcat. Change-Id: I74ea21a8a4107d438bc03a0da182ea7e991e74bc Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-24mb/google/brya/var/nova: Disable Thunderbolt deviceKenneth Chan
Nova doesn't support thunderbolt, so disable the TBT setting. Enabling TBT also causes the system to fail to enter S3/S5 state. S5 fail log: 24-10-21 20:23:34.610 Port 80 writes: 24-10-21 20:23:34.610 9a02 9a32 9a14 9c15 9c18 9c19 9c20 9c22 9c25 9c28 9c3f 9c43 9c44 9c4f 9c23 9a50 9a5f 9a33 9b40 9b41 24-10-21 20:23:34.620 9b42 9b47 9c80 9c81 9c82 9c83 9a61 9a63 9a03 9a04 9a05 9a06 9a07 9a0f 9a65 9a64 9c6a 9c71 9c7f 99 24-10-21 20:23:34.626 a0 a1 72 24 25 24 25 55 24 25 55 55 73 74 75 75 75 75 75 75 24-10-21 20:23:34.633 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 24-10-21 20:23:34.639 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 24-10-21 20:23:34.643 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 76 77 79 9c 24-10-21 20:23:34.649 93 7a fe 7b f8 aa ab 96 <--new powerinfo 24-10-21 20:23:59.424 powerinfo 24-10-21 20:23:59.424 power state 4 = S0, in 0x00ff The correct power state for S5 is G3, not S0. BUG=b:374213121 TEST=emerge-constitution coreboot chromeos-bootimage. Booting to OS and verify S3/S5 by EC log. Change-Id: I2bae8ae396f001dbef3322e361f9563792e1a1ef Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84838 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-24mb/google/nissa/var/glassway: Add touch screen ELAN9004 supportDaniel Peng
1. 2nd touch panel: INX N140HCN-EA1 C5 2. Set TOUCHSCREEN_ELAN9004 to value "3" BUG=b:374899470 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. Confirm command evtest and touchscreen function is workable. Change-Id: Ic25bd46c7cb7948e920de4fd44edb87f20cf01c4 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84834 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-24mb/google/nissa/var/glassway: Support Samsung K3LKBKB0BM-MGCPDaniel Peng
Add the new memory support: Samsung K3LKBKB0BM-MGCP BUG=b:374880584 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/glassway/memory/ \ src/mainboard/google/brya/variants/glassway/memory/\ mem_parts_used.txt" Change-Id: I47d9fd64fa841a2cf60930c5e319a9130019b0a5 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84831 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-23device/dram/ddr3: Use boolean for spd_dimm_is_registered_ddr3()Elyes Haouas
Change-Id: I8c9d66777b69b35f4df147c141fe94694f57be31 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83902 Reviewed-by: coreboot org <coreboot.org@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23device/dram/ddr2: Use boolean for spd_dimm_is_registered_ddr2()Elyes Haouas
Change-Id: I475f0c7582148e9b9f86b542f753a6654e9f9135 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: coreboot org <coreboot.org@gmail.com>
2024-10-23soc/intel/broadwell; Use boolean for pch_is_wpt_xxElyes Haouas
Use boolean for pch_is_wpt() and pch_is_wpt_ulx(). Change-Id: Ifd1a46ebdbe08df6cc21ada100b94930b02cd7de Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: coreboot org <coreboot.org@gmail.com>
2024-10-23mb/erying: Add Erying Polestar G613 Pro (TGL-H)Alicja Michalska
Erying is a Chinese manufacturer selling desktop motherboards with laptop SoCs and custom shim to mount desktop coolers. Working: - Serial port (IT8613E 0x3f8) - All rear USB ports (3.0, 2.0) - Both HDMI ports - Realtek GbE NIC - Internal audio (ALC897/ TGL-H HDMI) - Environment Controller (SuperIO fan control) - All SATA ports - All PCI-E/M.2 ports - M.2 NGFF WiFi - PCI-E Resizable BAR (ReBAR) - VT-x WIP/Broken: - PCI-E ASPM (also broken on vendor's FW, clocks are messed up) - S3/s0ix (also broken on stock, setting 3VSB register didn't help - system goes to sleep, but RAM loses power) - DisplayPort on I/O panel (seemingly a simple fix) - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) - Automatic fan control (IT8613E can't read CPU_TIN at the moment) Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as vendor hasn't enabled any protections on SPI chip. TEST=Flash coreboot build onto the motherboard, install following PCI-E cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi. Power the system up and boot into Windows 10 to check ACPI sanity, then reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk benchmark, compilation at the same time to check system's stability. Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-23device/pciexp: Add hot-plug capable helper functionPatrick Rudolph
Add and use a new helper function to determine if a device is 1) a PCIe device 2) it's mark hot-plug capable Change-Id: I61cc013844024b43808cd2f054310cb6676ba69e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-10-23soc/intel/xeon_sp: Report PCIe integrated end points under DRHDJincheng Li
In case of a PCH-less platform, no DRHD_INCLUDE_PCI_ALL flags are used, all PCIe integrated end points should be explicitly listed under the DRHD they are affiliated to. Otherwise, the device MSI setting could fail. TESTED = Build and boot on intel/beechnutcity CRB In CentOS Stream (5.14.0-479.el9.x86_64) 9 5.14.0-479.el9.x86_64, without the changes, below failure logs will occur, [ 6.908347] ------------[ cut here ]------------ [ 6.908353] WARNING: CPU: 0 PID: 8 at drivers/pci/msi/msi.h:121 pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908374] Modules linked in: [ 6.908379] CPU: 0 PID: 8 Comm: kworker/0:0 Not tainted 5.14.0-479.el9.x86_64 #1 [ 6.908385] Hardware name: Intel Beechnut City CRB/Beechnut City CRB, BIOS c1e9362c93be-dirty 09/25/2024 [ 6.908389] Workqueue: events work_for_cpu_fn [ 6.908401] RIP: 0010:pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908411] Code: 90 90 90 0f 1f 44 00 00 48 8b 87 00 03 00 00 89 f2 48 85 c0 74 14 f6 40 28 01 74 0e 48 81 c7 c8 00 00 00 31 f6 e9 19 de ac ff <0f> 0b b8 ed ff ff ff c3 cc cc cc cc 66 66 2e 0f 1f 84 00 00 00 00 [ 6.908417] RSP: 0000:ffffac47c0137c80 EFLAGS: 00010246 [ 6.908423] RAX: 0000000000000000 RBX: ffff9a0a874e2000 RCX: 000000000000009c [ 6.908428] RDX: 0000000000000001 RSI: 0000000000000001 RDI: ffff9a0a874e2000 [ 6.908433] RBP: 0000000000000000 R08: 0000000000000004 R09: 0000000000000001 [ 6.908437] R10: ffff9a0a8adcb258 R11: 0000000000000000 R12: 0000000000000001 [ 6.908440] R13: 0000000000000001 R14: ffff9a0a8738be00 R15: ffff9a0a874e20c8 [ 6.908443] FS: 0000000000000000(0000) GS:ffff9a0ded000000(0000) knlGS:0000000000000000 [ 6.908448] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 6.908451] CR2: ffff9a11fffff000 CR3: 00000003cd410001 CR4: 0000000000770ef0 [ 6.908455] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 6.908457] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7: 0000000000000400 [ 6.908460] PKRU: 55555554 [ 6.908462] Call Trace: [ 6.908465] <TASK> [ 6.908470] ? show_trace_log_lvl+0x1c4/0x2df [ 6.908484] ? show_trace_log_lvl+0x1c4/0x2df [ 6.908492] ? msi_capability_init+0x193/0x280 [ 6.908501] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908509] ? __warn+0x7e/0xd0 [ 6.908519] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908527] ? report_bug+0x100/0x140 [ 6.908537] ? handle_bug+0x3c/0x70 [ 6.908545] ? exc_invalid_op+0x14/0x70 [ 6.908551] ? asm_exc_invalid_op+0x16/0x20 [ 6.908561] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908569] msi_capability_init+0x193/0x280 [ 6.908577] __pci_enable_msi_range+0x1a3/0x230 [ 6.908586] pci_alloc_irq_vectors_affinity+0xc3/0x110 [ 6.908594] pcie_port_enable_irq_vec+0x3f/0x250 [ 6.908604] ? __pci_set_master+0x31/0xd0 [ 6.908614] pcie_portdrv_probe+0xdf/0x300 [ 6.908620] local_pci_probe+0x4c/0xa0 [ 6.908627] work_for_cpu_fn+0x13/0x20 [ 6.908635] process_one_work+0x194/0x380 [ 6.908643] worker_thread+0x2fe/0x410 [ 6.908649] ? __pfx_worker_thread+0x10/0x10 [ 6.908655] kthread+0xdd/0x100 [ 6.908665] ? __pfx_kthread+0x10/0x10 [ 6.908673] ret_from_fork+0x29/0x50 [ 6.908686] </TASK> [ 6.908688] ---[ end trace 0000000000000000 ]--- Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84315 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23util/cbfstool: Add Intel platform boot policy supportGang Chen
Intel platform boot policy setting blob is linked into FIT table as an FIT4 entry. It is required for server executing CBnT and/or PFR without a PCH. Please refer to chapter 4.6 of the document in below link: https://www.intel.com/content/dam/www/public/us/en/documents/ guides/fit-bios-specification.pdf Tool usage: ./util/cbfstool/ifittool -f <binary> -a -n <cbfs name> -t 4 \ -r COREBOOT -s <max table size> Change-Id: I0f9fc61341430b1a35a44d50b108dcfaf31cd11c Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84305 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/intel/xeon_sp/ibl: Remove unused logicsJincheng Li
Change-Id: I79b08630753b3aceb94becc8b9d682a3d3ca8310 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84308 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-23soc/intel/xeon_sp/ibl: Update registers for reach bootableShuo Liu
Change-Id: Id2a2946b7fdfd7fd245835afe6abc9a3f7e1a508 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-23soc/intel/xeon_sp: Add Kconfig SUPPORT_SIMICS_SIMULATIONShuo Liu
Xeon-SP simics doesn't provide simulation of writable PAM-F (Programmable Attribute Map) segment and hence coreboot needs to enable SHADOW_ROM_TABLE_TO_EBDA to write system table pointers to EBDA (Extended BIOS Data Area). Change-Id: I216204987ad646a5d1655323d2725cfd3415a2d7 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-23mb/ocp/deltalake: Clean codePatrick Rudolph
Use dev_find_all_devices_on_stack() to find the PCI device on a given stack. That way open coded duplicated code can be dropped and there's no need to call socket0_get_ubox_busno(), which allows to drop socket0_get_ubox_busno(). In addition it adds PCI multi segment support. Change-Id: Ib0ed177ae22112a9f2ed32199409d91cb5851ede Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84790 Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/mediatek/common: Add more definitions for SPMIYidi Lin
The newly added enums and struct members will be used by MT8196. BUG=none TEST=emerge-corsola coreboot; emerge-geralt coreboot Change-Id: I32e758cc4244114073606c418a69e0467cdf1039 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84773 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/mediatek/common: Maintain common pmif data in pmif_init.cYidi Lin
MT8196 has different pmif_spmi_arb and pmif_spi_arb configurations. Move the common pmif data to a separate file in order to reuse common/pmif.c as much as possible. BUG=none TEST=emerge-corsola coreboot; emerge-geralt coreboot Change-Id: I24643ce58a57b9cc3c5220bc06a85b141b366eee Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-10-23soc/mediatek/common: Config CAL_TOL_RATE and CAL_MAX_VAL in SoC folderYidi Lin
MT8196 has differenet configurations from other platforms. Make CAL_TOL_RATE and CAL_MAX_VAL as per SoC configuration in order to reuse common/pmif_clk.c BUG=none TEST=emerge-corsola coreboot; emerge-geralt coreboot Change-Id: Iefc8180e1719d9796df7457b619a8792ceb762b2 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84771 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/intel/pantherlake: Update PlatformDebugOption to Trace ReadyJamie Ryu
This enables SOC_INTEL_DEBUG_CONSENT to set PlatformDebugOption to Trace Ready to have the safe configurations for Panther Lake ES SoC. This safe configuration will be removed once the feature is fully verified and safe to be set to the default value. BUG=b:373915085 TEST=Build fatcat and check the platform boots without an issue. Change-Id: I1eaabcb2e2aaff16ee4e64d1c7709b229de18459 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84823 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-23include/device: Add missing includePatrick Rudolph
Fix the following error when including device/pciexp.h src/include/device/pciexp.h: In function 'pciexp_is_downstream_port': src/include/device/pciexp.h:42:24: error: 'PCI_EXP_TYPE_ROOT_PORT' undeclared (first use in this function) 42 | return type == PCI_EXP_TYPE_ROOT_PORT || by including pci_def.h. Change-Id: Idfd36301a5e766bbe97c93afef88c97507a4c4dc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84791 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-22drivers/usb/acpi: Account for the lack of a reset gpioSean Rhodes
Adjust the DSM to return 0x00 (unsupported) when no reset gpio is passed to the driver. Leave the _RST method to comply with the ACPI specification but omit the BTRT method as it won't do anything. Change-Id: I9f8e98fb4f5a22b2f7617b131a3d71cf90f5bc80 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-22soc/intel/alderlake_n: Fix display flicker issue when using internal FIVRSimon Yang
If project set configure_ext_fivr = 0 will cause PchFivrVccstIccMaxControl do not set correctly. BUG=b:361831628 TEST=Verified on Teliks360 that affected DUTs. Change-Id: I816de9c0c507aad3b73ab29e9f72048704f4662d Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84812 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-10-21soc/intel: Use NEM+ effective way size for for ADL, MTL and PTLJeremy Compostella
Alder Lake, Meteor Lake and Panther Lake use the effective way size when setting up the Enhanced No-Eviction Mode (cf. `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE'). BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83947 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-21soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+Jeremy Compostella
On Alder Lake, Meteor Lake and Panther Lake platforms the way size to consider for NEM+ computation is the effective way size. On Alder Lake, the External Design Specification #627270 "3.5.2 No-Eviction Mode (NEM) Sizes" provides a way to compute the effective way size by reading the number of CBO. Unfortunately, reading the number of CBO is not possible on Meteor Lake and Panther Lake. Therefore, we instead compute the effective way size as the biggest of power of two of the way size which works across all three platforms. The Kconfig `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE' is introduced to control this behavior. The issue addressed by this commit can be observed with the following experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to 0x400000 (4 MB). The number of ways that used to be computed is round(0x400000 / 0x180000) = round(2.66) = 3. 3 ways were mapped to cover the 0x400000 NEM+ region. When the bootblock code accesses memory between 3 MB and 4 MB, the core would raise a page fault exception. The right computation is: 0x400000 / eff_way_size(0x180000) = 4. 4 ways needs to be mapped to cover the entire 0x400000 NEM+ region. BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-21mb/google/fatcat: Disable C1 state auto-demotion for ES SoCJamie Ryu
This disables C1 state auto-demotion to run the coreboot with Panther Lake ES SoC without an issue. This configuration will be remove later once the related features are fully verified. BUG=b:373915085 TEST=Build fatcat and check the platform boots without an issue. Change-Id: I384dba2918cfd04deb90284513c204fa8c21094b Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84767 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-21mb/google/brox/jubilant: Modify WWAN Rolling RW101R-GL power sequenceRen Kuo
There is no ACPI power resource for LTE module Rolling RW101R-GL, therefore implement the power sequence of power-on, power-off, and reset timing from GPIO init, bootstate init callbacks, and smihandler function. BUG=b:368450447 BRANCH=None TEST= Build firmware and verify on jubilant with LTE:RW101R-GL. Measure the power on, power off, and reset timing. Run warm boot, cold boot and suspend/resume to make sure WWAN devcie is workable. Change-Id: I4a205e3db777c7c225d31b6cc802883fd7167089 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-10-21mb/google/brox/jubilant: Update CPU power limitsRen Kuo
Update jubilant CPU PL4 from 9 watt to 14 watt for critical battery boot. The maximum peak power is set at 14 watt which is 45W multiplied by 32% efficiency. Overriding power limits for AC power without battery: PL1 (15000, 18000) PL2 (41000, 41000) PL4 (14) BUG=b:364441688 BRANCH=None TEST=Able to successfully boot on jubilant SKU1 and SKU2 with AC only. Test on AC 65W and 45W w/o battery, and check PL4 values from log. Change-Id: Id1e58797206a61d241f48b057b304e05c9c323d9 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84784 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-21mb/google/dedede/var/drawcia: Add Realtek WLAN card supportRobert Chen
Add wifi PCIe hosts M.2 E-key WLAN to fulfill drawman_jsl_schematic_20200528. BUG=None BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: If414ff1941d2d70c5f0444ac58b228ed5c95303a Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-10-21drivers/spi/spi_flash_internal: add missing types.h includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7c5477bbc248a21e21f3a640bdb81304a1bce38c Reviewed-on: https://review.coreboot.org/c/coreboot/+/84788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-10-19mb/google/rauru: Add new board variant NaviLeo Chou
Add a new Rauru follower 'Navi'. BUG=b:341210522 TEST=emerge-cherry coreboot Change-Id: Ia2a6c1c09b3cedc0ef7f51ec93fdabf2c07c8885 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84694 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-19mb/google/rauru: Add NAU8318 supportAmanda Huang
NAU8318 supports beep function via GPIO control. Configure the GPIO pins and pass them to the payload. BUG=b:343143718 TEST=Verify beep function through CLI in depthcharge successfully. We can test with: firmware-shell: badusbbeep firmware-shell: devbeep Change-Id: I79277bc1947dab517dea5aba583c5b4e0ac81bc4 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84693 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-19mb/google/rauru: Configure the fingerprint pinsYidi Lin
There is no powering-on control in the fingerprint kernel driver. The fingerprint team of ChromeOS suggests powering-on FP MCU in the FW. Follow trogdor to pull down FP_RST_1V8_S3_L, AP_FP_FW_UP_STRAP, EN_PWR_FP and pull up EN_PWR_FP in ramstage for power rail to be stable. BUG=b:340401582 TEST=measure waveform and the fingerprint works on ChromeOS Change-Id: I05600d90fdf922faeb778a36d8a08f68c1bb4125 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84692 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-19mb/google/rauru: Pass XHCI_INIT_DONE to the payloadYidi Lin
Configure GPIO EINT28 (XHCI_INIT_DONE) as output, so that payloads (for example depthcharge) can assert it to notify EC to enable USB VBUS. BUG=b:317009620 TEST=emerge-rauru coreboot Change-Id: I5950974435b56997626886b16d371cd8e6472e3c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84691 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-18soc/xeon_sp: Initially add N-1 IBL codesShuo Liu
N-1 IBL (Integrated Boot Logic) codes are initially forked from EBG (Emmitsburg PCH) codes (src/soc/intel/xeon_sp/ebg). N-1 IBL codes are a set of stub codes to fulfill build sanity check for GNR SoC and CRB codes before the formal codes are published. Change-Id: I6bd5a2ed973ff91750c5ed1f9a57d30e41d8b97e Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-17mb/google/nissa/var/glassway: Add convertible and clamshell WIFI SAR ↵Daniel Peng
FW_CONFIG ids Based on Gallida360 design, we add two new options for WIFI_SAR_ID: - WIFI_SAR_ID_INTEL_CONVERTIBLE 2 - WIFI_SAR_ID_INTEL_CLAMSHELL 3 BUG=b:372354703 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I1b58c4f572d4dbcb269d38485664ddc51e378e5e Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84779 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-17mb/google/fatcat: Create francka variantIan Feng
Create the francka variant of the fatcat reference board. BUG=b:370666276 TEST=util/abuild/abuild -p none -t google/fatcat -x -a make sure the build includes GOOGLE_FRANCKA Change-Id: I372f445f7007d0d33020545a8febbce27c260e41 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84769 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-17mb/google/fatcat: add pre-mem configuration based on fw_configCliff Huang
Add the GPIO pad configuration to be performed before memory is set up along with the relevant devices definition. This patch includes: - FW config for pre-mem GPIO PAD configuration - Add overridetree changes used by pre-mem FW config BUG=b:348678529 TEST=Boot on Google Fatcat board. Note this cannot be tested by itself directly. Test with CL:84408, set the proper CBI fw_config bit(s) and check that the corresponding GPIO PADs are configured as expected value accordingly. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iac1f637c21a9818512b224dc4cbe4a75dbc516ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/84718 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-16mb/google/brya: Create telith variantKun Liu
Create the telith variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0) BUG=372506691 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TELITH Change-Id: I4971b9691d3dd293ca640795967c36472afef9c9 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84759 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-10-16mb/arm/rdn2: Add support for Arm Neoverse N2Naresh Solanki
Add support for Arm Neoverse N2 Reference design. Based on Arm Neoverse N2 reference design Revision: Release D TEST=Build Arm Neoverse N2 & make sure there is no error. Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-10-16mb/ibm/sbp1: Add SMBIOS slotsPatrick Rudolph
Add the BMC and all PCIe slots that the board implements. There are 32 RSSDs and 2 M.2 slots. Change-Id: Id7d72990d6997d1e8b9ce75477ce3dc571c99839 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-16smbios: Add slot typesPatrick Rudolph
Add slot types found in SMBIOS spec 3.8.0. Change-Id: I705529efcbf2add420fb6f4a720ec33444d46efa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-16soc/intel/xeon_sp: Allow Memory POR independent of RMTNaresh Solanki
TEST=Build & boot in IBM SBP1 system. Verified the settings are effective in FSP logs. Change-Id: I4341ead89a2683f64c834a6981ba316fcfef4f9a Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84741 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-16drivers/mipi: Update brightness for IVO_T109NW41 panelYang Wu
The current panel brightness is only 360 nits. Adjust the power and gamma to optimize the panel brightness. The brightness after adjustment is 390 nits. BUG=b:320892589 TEST=boot ciri with IVO_T109NW41 panel and see firmware screen BRANCH=geralt Change-Id: I760c37bf915bb40ad2efa7c947034cb168938f2a Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84758 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-10-16device/azalia: Clear busy bit after failed verb commandNico Huber
The spec tells us to clear the busy bit manually after a timeout. Do that and wait immediately, to detect further issues early. Also fix some related comments and prints: Failures shouldn't be debug messa- ges. And we are talking to the PIO interface of the controller, not the codec. So this was never about the codec being ready. Change-Id: I4b737f8259157c01bfcd9e6631cc15d39c653d06 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83592 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-16mb/google/brya/var/glassway: Add Stylus FunctionDaniel Peng
1. Add STYLUS fw_config setting. 2. Enable stylus device settings. 3. Disable the stylus GPIO pins based on fw_config. BUG=b:364798563 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot 2. Confirm command evtest for stylus PRP0001:00 and workable. Change-Id: Ifa8555eed1c31e9342a50a735fc618106f26d41a Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84713 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-10-14drivers/usb/acpi: Remove Tile Activation Method in Intel Bluetooth driverSean Rhodes
Linux has never supported this feature, and according to our FAE, the Windows driver dropped support for it in 2022 so remove it. Change-Id: I4f0b6108bb5db657490a8b9395bb99378fc63c4d Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-14drivers/usb/acpi: Add support for RTD3 for Intel BluetoothSean Rhodes
Add support for RTD3 for Intel Bluetooth. This is done by controlling the enable GPIO (GPP_VGPIO_0 for most SOCs) that exists on all wireless cards since Jefferson Peak. The exception is GalePeak2, which uses VSEC and this driver doesn't support that. Change-Id: Ibea97ab0ae0a9f1eb6aaca43d831bb4ce7bdc02e Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-14soc/intel/*: Add debug prints for misaligned FSP and driver settingsSean Rhodes
Print a warning when the FSP UPD for CNVi Audio Offload is enabled without the corresponding USB ACPI driver being enabled. Throw an error when the USB ACPI driver is enabled without the corresponding UPD being enabled. Change-Id: I449c43998dd379dc68a33db47a2fe51cfe5cda2f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-10-14drivers/usb/acpi: Add AOLD Method for Intel BluetoothSean Rhodes
Add AOLD Method, which returns an integer based on whether Audio Offload is enabled. Leave the existing control of Audio Offload in `soc/soc_chip.h`. Add `cnvi_bt_audio_offload` in the USB ACPI `chip.h` to control the aforementioned return value. The value in `soc/soc_chip.h` and `chip.h` should match. Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84134 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-14i945: Use nullptr instead of NULLElyes Haouas
nullptr was introduced in C11 spec and gcc 4.7. https://en.cppreference.com/w/cpp/language/nullptr https://stackoverflow.com/questions/16256586/how-to-enable-c11-on-later-versions-of-gcc coreboot switched to GCC 4.7.2 on October 25, 2021, prior to coreboot v4.1. https://review.coreboot.org/c/coreboot/+/1609 GCC-13 implemented nullptr constant: https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3042.htm So use it insted of NULL macro. Change-Id: I7d47e692a33d739345a81f589d4329a31beeb8c5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83860 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-14drivers/pc80/tpm: Remove flag TPM_RDRESP_NEED_DELAYBill XIE
After CB:76315, TPM_RDRESP_NEED_DELAY, whose historical mission has ended, could be removed. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I51e046fb738d2ff7a23225739de62a1a7780bc1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/84717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2024-10-14drivers/pc80/tpm: Fix tis_readresponse()Kyösti Mälkki
TPM_RDRESP_NEED_DELAY was introduced in 2018 in CB:25322 after observing errors with SLB9635 by Infineon. It has been confirmed also SLB9670 and SLB9672 require a fix or delay here. Presumably, prior to CB:4388 SLB9635 did not have this problem, as this particular TPM shipped with samsung/lumpy Chromebook since 2011. In CB:4388 the code changed from polling the status register (+burst_count) using a 32bit read to separated 8bit reads. So far, experiments on samsung/lumpy and SLB9635 indicate that it would be sufficient to add a single tpm_read_status() call to see TIS_STS_DATA_AVAILABLE as set at the time of evaluating the loop exit condition. Change-Id: If5c3e93c7946ebf8226f7bba47b38253f6920c61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Co-authored-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-14mb/google/nissa/var/sundance: Change touch panel and wwan gpio settingRoger Wang
In order to fit the specification, change gpio setting for touch panel and wwan. Change items: 1. wwan : Add WWAN_RST_L to 0. And we want WWAN_EN to pull high more early than WWAN_RST_L, so add WWAN_EN to 1 in romstage stage. 2. touch panel : First we add EN_PP3300_TCHSCR and USI_RST_L to 0 to init status. And we want EN_PP3300_TCHSCR to pull high more early than USI_RST_L so delete USI_RST_L pull high in romstage. BUG=b:357764679 Test=emerge-nissa coreboot Change-Id: I0a07ea8e2bf3d165dcebd89c4c564f157d9d4846 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84668 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-13mb/google/brox/var/lotso: Reduce gspi speed from 10 MHz to 9 MHzKun Liu
Reduce gspi speed from 10 MHz to 9 MHz, because Raptor Lake Refresh platform GSPI supports max frequency 9 MHz. BUG=b:342932183 TEST=emerge-brox coreboot Change-Id: If5b7885d95cfe21ec71cc37e6d72419935b0844f Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84708 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-12mb/google/brox/lotso: Enable devices on unprovisioned fw_configWentao Qin
Setting devices to unprovisioned allows us to perform functional testing without having to rewrite the fw config during the SMT phase of factory production. BUG=None TEST=Build lotso firmware and boot to OS when fw_config is unprovisioned and ensure all devices are enable. Change-Id: I3b8285ce335ee0f3595d184eb0921f697bdbd0c2 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84714 Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-10-11soc/intel/xeon_sp: Revise IIO domain ACPI name encodingShuo Liu
GNR/SRF supports up to 18 logical IIO stacks. Revise IIO domain ACPI name encoding in below form to support GNR/SRF, prefix (16 bit) | socket (3-bit) | stack (5-bit) Change-Id: I6f4c3c22980f2797dd47c8e0d684e0a3175030b7 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-11soc/amd/common/block/psp/Kconfig: drop some 'default n'Felix Held
Since the Kconfig default for boolean options is already 'n', there's no need to add that default to the option. Still kept the 'default n' for the 3 options that result in fuses inside the SoC to be burnt (PERFORM_RPMC_PROVISIONING, PERFORM_SPL_FUSING and PSP_PLATFORM_SECURE_BOOT) to point out the fact that that's not selected by default more clearly. Change-Id: I55971f1f130d8ec23d4572a215008d9465e1520a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-10-11soc/amd/common/psp_smi_flash: add RPMC command-specific data structuresFelix Held
Add the data structures used for the command buffers for the PSP SMI commands to increment and request the state of the monotonic counters in the SPI flash. These data structures are specific to the PSP SMI mailbox interface and not the data structures from the RPMC specification. The AGESA code was used as a reference. Change-Id: I8bc8ff4cf9b7ebd0e034f040dde2db8385bb8f79 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/alderlake: Fix PEG0 IRQ routingSean Rhodes
PEG0 should be set to PCI_INT_D, not PCI_INT_A. This fixes: pcieport 0000:00:06.0: can't derive routing for PCI INT D pcieport 0000:00:06.0: PCI INT D: not connected PEG1 should also be PCI_INT_B. Tested on `starbook_adl` with Ubuntu 24.04 by running SSD benchmark with GNOME disks and suspend. Change-Id: I0f37bb9ac8572d7335084a20fceca6977a491498 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84619 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11mb/starlabs/*: Rework the performance profilesSean Rhodes
Rather than hardcoded values, simply change these to -25% of the defaults for Power Saving, and +25% for Performance. Change-Id: I16aeb4d5dc25a3f240a775509276c9d3189e9699 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84661 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11mb/starlabs/*: Adjust the scope of PTTSean Rhodes
The Windows driver only checks PCI0, so move the window accordingly so that it can be used. Tested on `starlite_adl` by booting Windows 11 installation medium. Prior to this patch, it would flag that the security requirements were not met - it now happily installs. Change-Id: I5d0d062502af99104690f9a9affec09f42b5bc71 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84663 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-11mb/starlabs/byte_adl: Configure GPP_E14 as EDP_HPDSean Rhodes
This pin is used by the DisplayPort connector for Hot Plug. Change-Id: I3c63e2e3e168a915daee81afd6a9084a3f01b986 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84662 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11mb/starlabs/*: Set PL4 to 1.0C of the batterySean Rhodes
Override the PL4 to the maximum power the battery can provide without a charger connected to prevent drawing too much power. Change-Id: I2945e1ed0f33ab6692631e327c1457980b353c06 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84660 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11mb/starlabs/starlite_adl: Correct the SOC definition in devtreeSean Rhodes
The wrong definition was used, so the code had no effect. The ID for the processor used is `b06e0`. Change-Id: I36e13074a77b93871c1d86664e35a33afe39a402 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84659 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11mb/starlabs/*: Enhance USB configuration and commentsSean Rhodes
Some boards use hubs for devices, so correct the ACPI configuration for these ports. Also, add more information to the comments for the ports. Change-Id: I8472130aba8e777557cf68280fa0058dbeb77df9 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2024-10-11mb/starlabs/*: Add PLD Groups to USB ACPI configurationSean Rhodes
Change-Id: I6fb228bab06b050ac1a51de46ffe5c0d3d80adfb Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2024-10-11mb/starlabs/starlite_adl: Make I2C speed configurableSean Rhodes
Make the I2C speed user configurable from CMOS. Both the touchscreen and accelerometer support running at 100MHz or 400MHz. They perform better at 400MHz but use more power - this patch lets the user choose. Change-Id: Ia1b08d7ec6212418bb95d0a52077f01c930f8830 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2024-10-11mb/starlabs/starlite_adl: Alphabetize and group FSP UPDsSean Rhodes
Change-Id: Ibe47f242ce12fc4906baeee89393a34a56eaca76 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83881 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11soc/intel/cnvi: Add CNIP MethodSean Rhodes
This method is used to provision the CNVi, and ensure that it is in the correct state. Intel document #559910 details this. Change-Id: Id8a36a09c7beaf3ba8b29d3276bd9dc59420dab5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83713 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11soc/intel/cnvi: Add CFLR MethodSean Rhodes
This method is used to limit frequencies on CNVi. Intel document #559910 details this. Change-Id: Idc4c35e71076fd31786212995472bb8d58c961de Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add power related methodsSean Rhodes
Only the _PRR method is used here, however, _PS0, _PS3 and _DSW must exist to avoid a BSOD on Windows. Change-Id: Ib4a1a8a76ce74b991a3e8686e9594c2c2b145a39 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvw: Add GPEH MethodSean Rhodes
Add a general purpose handle to allow CNVi to be notified of state changes. Intel document #559910 details this. Change-Id: I36c98c525c99fb2b7b5ebd8b0e392e6626e97290 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83710 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11soc/intel/cnvi: Add PRR method for CNVi ResetSean Rhodes
Add a _PRR method that the OS can use to reset the wireless. This is only used for integrated solutions and depends on the CNMT Mutex that's created with `drivers/usb/acpi`. Whilst new ACPI is added, the behavior of existing boards won't be changed unless they configure the accompanying Bluetooth device. Intel document #559910 details this. Change-Id: I25e8462780badcad88b13052a6eb282c83af5def Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add _S0W to ensure CNVi isn't put into D3 ColdSean Rhodes
All CNVi modules, integrated or dedicated only support D3 Hot so add _S0W to limit the sleep state. Intel document #559910 details this. Change-Id: I1541cebc022adc927a9cd883500320e9ef82359f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add CWAR FieldsSean Rhodes
These fields are used to monitor events on CNVi. Intel document #559910 details this. Change-Id: I3c1efc039e929ad1eeb8a0dd7c176e370e502e0c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83709 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add CNVW OpRegionSean Rhodes
The CNVi driver is relatively basic in coreboot and most noticeably, recent Linux kernels flag that lack of a _PRR method, which is used to reset WiFi and Bluetooth. This patch series adds methods recommended by Intel in document #559910. This patch defines an OpRegion for CNVi, for both integrated and dedicated solutions. Change-Id: Idd2ff93fb65c40f656804d96966e1881202ccb56 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-11soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetreeSean Rhodes
Hook up CNVi Bluetooth UPDs to the devicetree. Set CnviBtCore to `true` so the current behaviour is not changed. Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84596 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/*: Disable c6dramSean Rhodes
None of these boards support or use S0ix so c6dram isn't needed, so disable it. Change-Id: I8124899a1f7ce20442f28919f7315ee7e52355e5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84632 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/byte_adl/mk_ii: Correct USB Port Names to Type-ASean Rhodes
There is only 1 Type-C port, the rest are Type-A. Tested on Linux by verified the correct names are shown in dmesg. Change-Id: Iaf5a29f3d25f299658116fa61ae488775e2b70a2 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84642 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/starlite_adl: Adjust the configuration for USB 2 Port 2Sean Rhodes
Port 2 is a hub, used for the internal keyboard and the card reader. Adjust this to a hub. Change-Id: I3a9b9e6803934291b46fb502ff1b3b088c047703 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2024-10-10mb/starlabs/starlite_adl: Add PLD groups to USB ACPI configurationSean Rhodes
Change-Id: I8ea01c21ec03c11e9599684dbe51d103c07c172a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84640 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/starlite_adl: Reconfigure the touchscreenSean Rhodes
The existing GPIO configuration was IRQ heavy; tweak this to reduce the number of interrupts. Change-Id: I6d23bea5ec12e86a3606186edb29636540283fa3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84639 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/starlite_adl: Adjust the PROCHOT GPIOSean Rhodes
A debug configuration was left in the patch when it was uploaded, remove this. Change-Id: I3ab8137d3841dfa200750a97969af5dca477d7e2 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2024-10-10mb/starlabs/starlite_adl: Configure Wireless GPIOs laterSean Rhodes
The wireless GPIOs don't need to be configured in the bootblock, so set them up in ramstage. Change-Id: Iab399884edde29891e66ffc097cf6f3dff71c351 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84637 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/starbook: Add options to disable USB devicesSean Rhodes
Add options to disable the card reader and fingerprint reader. Change-Id: Iee985aa2db3da5c2d393b8dc2dc722e990c43272 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84631 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10include/spi_flash: add RPMC field length definesFelix Held
The first table from the chapter 4.1 'OP1/OP2 Command Definition: No Address Phase' of the JEDEC standard JESD260 (Replay Protected Monotonic Counter (RPMC) for Serial Flash Devices) in the version from April 2021 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0050aea6cdc537122bae63fddb417dd9f6b75a02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84703 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-09soc/amd/common/psp: add and call PSP SMI SPI RPMC function stubsFelix Held
In the case where the x86 owns the SPI controller and the RPMC feature is used, the PSP will send an SMI to the x86 side for it to send the RPMC increment monotonic counter and RPMC request monotonic counter commands to the SPI flash and return the result to the PSP. Add stubs as handlers for those two PSP SMI commands. Change-Id: If6091d2b0002f817922cac4cba373f0f981b646e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84702 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ana Cabral
2024-10-09drivers/spi: add Numonyx and Micron names to STMicro caseFelix Held
STMicro first moved their SPI NOR flash business to Numonyx which was a joint venture with Intel which later got sold to Micron, so add a comment to the VENDOR_ID_STMICRO JEDEC manufacturer ID define and mention all 3 companies that have sold SPI NOR flash chips using this manufacturer ID to the Kconfig help text of SPI_FLASH_STMICRO. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7886396d8f0a9766f568a221c0b5ade02489060b Reviewed-on: https://review.coreboot.org/c/coreboot/+/84018 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-10-09drivers/ocp/ewl: Remove space after a castElyes Haouas
Change-Id: I50ee0adc2f70ad593815783078145cc4b494f70c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77732 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-09mb/google/brya/var/glassway: Add WFC FunctionDaniel_Peng
1.Add WFC fw_config setting. 2.Used USB2 Port7 for WFC. BUG=b:365184481 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ie5dcf5ed8f72a4bdf4c2c7fc63bf94dc7b869eef Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84685 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 21:44:12 +0000