summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2016-11-15google/link/i915.c: Fix build error when native gfx init enabledIru Cai
- Move members of struct edid to struct edid_mode - Change `u32 pmmio` to `u8 *pmmio` in i915_lightup_sandy Change-Id: Id64daf5eae1d4d8265105067b2e6ae55786a5638 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/17332 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-15nb/gm45: Refactor IGD vram decodingArthur Heymans
This is more consistent with other Intel GMCH code. Change-Id: I7bfaa79b9031e2dcc5879a607cadacbdd22ebde7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17405 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-14google/chromeec: Add elog events for recovery mode switchesFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified eventlog on reef 0 | 2016-11-12 19:49:25 | Log area cleared | 4088 1 | 2016-11-12 19:49:25 | Kernel Event | Clean Shutdown 2 | 2016-11-12 19:49:25 | ACPI Enter | S5 3 | 2016-11-12 19:49:39 | System boot | 365 4 | 2016-11-12 19:49:39 | EC Event | Power Button 5 | 2016-11-12 19:49:45 | Chrome OS Recovery Mode | Recovery Button Pressed 6 | 2016-11-12 19:49:45 | Chrome OS Developer Mode 7 | 2016-11-12 19:49:45 | EC Event | Keyboard Recovery 8 | 2016-11-12 19:49:45 | Memory Cache Update | Recovery | Success 9 | 2016-11-12 19:50:46 | System boot | 366 10 | 2016-11-12 19:50:46 | EC Event | Power Button 11 | 2016-11-12 19:50:52 | Chrome OS Recovery Mode | Recovery Button Pressed 12 | 2016-11-12 19:50:52 | Chrome OS Developer Mode 13 | 2016-11-12 19:50:52 | EC Event | Keyboard Recovery Forced Hardware Reinit 14 | 2016-11-12 19:50:52 | Memory Cache Update | Recovery | Success 15 | 2016-11-12 19:51:24 | Power Button 16 | 2016-11-12 19:51:24 | ACPI Enter | S5 17 | 2016-11-12 19:51:27 | System boot | 367 18 | 2016-11-12 19:51:27 | EC Event | Power Button 19 | 2016-11-12 19:51:32 | Wake Source | Power Button | 0 20 | 2016-11-12 19:51:32 | ACPI Wake | S5 21 | 2016-11-12 19:51:32 | Chrome OS Developer Mode 22 | 2016-11-12 19:51:32 | Memory Cache Update | Normal | Success Change-Id: I45dda210cf9d4e5a75404792fcee15b2010787a7 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17394 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14vboot: Add new function for logging recovery mode switchesFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully Change-Id: I87cd675ea45a8b05a178cf64119bf5f9d8d218ca Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17408 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14elog: Update event log IDs for EC eventsFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully Change-Id: Idf2d377bf4709ea25616adfbde55f39798c0cd39 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17393 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14commonlib: Add new cbmem id for EC_HOSTEVENTFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully. Change-Id: Ife167bff484ef552bd6cd2e61fdc8291ad6a8acf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17392 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14lib/tpm2: do not create all NVRAM spaces with the same set of attributesVadim Bendebury
The TPM spaces created by the RO need to have different attributes depending on the space's use. The firmware rollback counter and MRC hash spaces are created by the RO code and need to be protected at the highest level: it should be impossible to delete or modify the space once the RO exits, and it is how it is done before this patch. The rest of the spaces should be possible to modify or recreate even after the RO exits. Let's use different set of NVRAM space attributes to achieve that, and set the 'pcr0 unchanged' policy only for the firmware counter and MRC cache spaces. The definitions of the attributes can be found in "Trusted Platform Module Library Part 2: Structures", Revision 01.16, section "13.2 TPMA_NV (NV Index Attributes)." CQ-DEPEND=CL:410127 BRANCH=none BUG=chrome-os-partner:59651 TEST=verified that the reef system boots fine in both normal and recovery modes; using tpmc confirmed that firmware, kernel and MRC cache NVRAM spaces are readable in both and writeable only in recovery mode. Change-Id: I1a1d2459f56ec929c9a92b39175888b8d1bcda55 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/17388 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Pronin <apronin@chromium.org>
2016-11-14soc/intel/apollolake: Increase HEAP_SIZESathyanarayana Nujella
Adding both 2-ch & 4-ch DMIC blob causes the below error: memalign(boundary=8, size=3048): failed: Tried to round up free_mem_ptr 7abc48b0 to 7abc5498 but free_mem_end_ptr is 7abc4d70 Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr) Increased heap size fixes the above issue. BUG=chrome-os-partner:56918 BRANCH=none TEST=Compiles successfully for reef Change-Id: Ic910f169f7ef4bb746cb273e276428713a884227 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17157 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14soc/intel/apollolake: Add support for DMIC 4ch & 1chSathyanarayana Nujella
Add NHLT support for DMIC Quad & Mono channel capture BUG=chrome-os-partner:56918 BRANCH=none Change-Id: If630ed53bb2cf00ccc441eb062b2e8c650d3cf01 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17156 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14soc/nvidia/tegra210: Remove CONSOLE_SERIAL_TEGRA210_UART_CHOICESMartin Roth
The Kconfig symbol CONSOLE_SERIAL_TEGRA210_UART_CHOICES was attached to a choice, and isn't used anywhere. Remove it as unnecessary. Change-Id: I4efd2e43ac34b266db0d40d1bc8c123bd377b3a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17391 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-11-14intel/apollolake: Enable turboShaunak Saha
This patch adds punit initialization code after FspMemoryInit so that turbo can be initialized after that. BUG=chrome-os-partner:58158 BRANCH=None Change-Id: I4939da47da82b9a728cf1b5cf6d5ec54b4f5b31d Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/17203 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14soc/rockchip: split edp_enable() functionLin Huang
To avoid garbage display in firmware on warm reset, we need to enable eDP display in depthcharge instead when the framebuffer is cleared. Therefore limit edp_enable() in coreboot to just configure eDP, and leave enabling the display to depthcharge. CQ-DEPEND=CL:402071 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, and display work Change-Id: I9d937ead33ebba58e33e02fd73b80d6e11bb69aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38b0d18c3fae37dfccb18fe809f763b98703167c Original-Change-Id: Ibbc283a5892b98f4922f02fd67465fe2e1d01b71 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/402095 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17207 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-14google/chell : update DPTF policy settingsSumeet Pawnikar
Fine tuned DPTF policy values for chell device as below, 1. Increase Passive temperature value to 52 degree Celsius for TSR2. 2. Remove charger effect for TSR2. 3. Increase Minimum PowerLimit1 to 3W. 4. Reduce Maximum PowerLimit1 to 6W. BUG=chrome-os-partner:54718 BRANCH=None. TEST=Built for chell device. Change-Id: I46f69e3cd527ea3d28bdd7daa29d91f76770c277 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17376 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14skylake: Update the thermal time window for throttling actionSumeet Pawnikar
This patch reduces the thermal time window to 100 milliseconds for fast throttling action at prochot. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built for skylake platform and verified the thermal time window value. Change-Id: If79d213cb8e19277ffdb882267d2f8672df93446 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17384 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14drivers/pc80/tpm: Select TPM device name based on Kconfig optionSubrata Banik
Device ID remains same for SLB9670 Infineon TPM 1.1 and TPM 2.0 chip. Hence select based on TPM2 Kconfig option. BUG=none BRANCH=none TEST=Build and boot SKL RVP with SPI TPM 2.0 module Change-Id: I57e63f2f2899d25ed6b797930fd8bf1d1cdc1b1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17374 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14intel/kblrvp: Enable TPMNaresh G Solanki
Add choice to build without TPM, TPM 1.2 support or TPM 2.0 support. Additionally configure lpc clock pad used with LPC TPM & update devicetree.cb. Change-Id: I1c24fdefa6e73637b3037ecf118559abe5fde300 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17367 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-14riscv: add a variable to control trap managementRonald G. Minnich
This variable can be set in a debugger (e.g. Spike) to finely control which traps go to coreboot and which go to the supervisor. Change-Id: I292264c15f002c41cf8d278354d8f4c0efbd0895 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17404 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-13riscv: change payload() to pass the config string pointer as arg0Ronald G. Minnich
The riscv 1.9 standard defines a textual config string to be passed to kernels and hypervisors. Change the payload function to pass this string in a0. Change-Id: I3be7f1712accf2d726704e4c970f22749d3c3f36 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17254 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-12riscv: start to use the configstring functionsRonald G. Minnich
These functions will allow us to remove hardcodes, as long as we can verify the qemu and lowrisc targets implement the configstring correctly. Hence, for the most part, we'll start with mainboard changes first. Define a new config variable, CONFIG_RISCV_CONFIGSTRING, which has a default value that works on all existing systems but which can be changed as needed for a new SOC or mainboard. Change-Id: I7dd3f553d3e61f1c49752fb04402b134fdfdf979 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17256 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-12riscv: bring in the configstring parsing functions from UCBRonald G. Minnich
I've tested this with commits to come later. This is from the lowrisc bbl distribution, 87588c4, with fixes so it builds. Change-Id: I87893638872259c94d6972e1971578b633155e7e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17255 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-11-12drivers/intel/fsp2_0: track end of firmware notificationsAaron Durbin
The end of firmware notification is currently not being tracked so it's hard to get good data on how long it takes. Update the code to provide timestamp data as well as post codes. BUG=chrome-os-partner:56656 Change-Id: I74c1043f2e72d9d85b23a99b8253ac465f62a7f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17373 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-11-12soc/intel/apollolake: cache the MMIO BIOS regionAaron Durbin
If the boot media is memory mapped temporarily mark it as write protect MTRR type so that memory-mapped accesses are faster. Depthcharge payload loading was sped up by 75ms using this. BUG=chrome-os-partner:56656,chrome-os-partner:59682 Change-Id: Iba87a51a05559d81b8e00fa4f6824dacf7a661f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17372 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-12cpu/x86/mtrr: allow temporary MTRR range during corebootAaron Durbin
Certain platforms have a poorly performing SPI prefetcher so even if accessing MMIO BIOS once the fetch time can be impacted. Payload loading is one example where it can be impacted. Therefore, add the ability for a platform to reconfigure the currently running CPU's variable MTRR settings for the duration of coreboot's execution. The function mtrr_use_temp_range() is added which uses the previous MTRR solution as a basis along with a new range and type to use. A new solution is calculated with the updated settings and the original solution is put back prior to exiting coreboot into the OS or payload. Using this patch on apollolake reduced depthcharge payload loading by 75 ms. BUG=chrome-os-partner:56656,chrome-os-partner:59682 Change-Id: If87ee6f88e0ab0a463eafa35f89a5f7a7ad0fb85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17371 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-12soc/intel/common/lpss_i2c: configure buses by rise/fall timesAaron Durbin
The default register count calculations are leading to higher frequencies than expected. Provide an alternative method for calculating the register counts by utilizing the rise and fall times of the bus. If the rise time is supplied the rise/fall time values are used, but the register overrides take precedence over the rise/fall time calculation. This allows platforms to choose whichever method works the best. BUG=chrome-os-partner:58889 Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17350 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-11lib/tlcl: Ensure tlcl library is initialized only onceFurquan Shaikh
Since tlcl library is used other than just vboot driver, ensure that the library is initialized only once per stage. BUG=chrome-os-partner:59355 BRANCH=None TEST=Verified in recovery mode on reef, tlcl library is initialized only once in romstage. Change-Id: I6245fe9ed34f5c174341b7eea8db456b45113287 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17364 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11samsung/stumpy: fix power LED operationMatt DeVillier
commit 80EF7B7 [IT8772F: Clean up it8772f includes and add a LED API] broke power LED operation when it incorrectly transferred values from the old function (it8772f_gpio_setup) to the new one ( it8772f_gpio_led). Restore the correct values so power LED illuminates when powered on. Change-Id: I99a38351bb52063fafa7436e6397a8da7fc1e952 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17266 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-11mainboard/google/snappy: Configure PERST pinWisley Chen
Configure GPIO 122 as PERST. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: If2528632fe65c3ed1af19b2ce6f99e8be0cd1ad9 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17356 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11kblrvp: Add support for Hynix memoryNaresh G Solanki
Add support for hynix memory variant of RVP3. Change-Id: Ic1f8630b36eb131b70c5e3b620957d9602da11ee Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17339 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11mainboard/intel/kblrvp: Add support to read board ID from ECAamir Bohra
Add a function to identify an Intel RVP board by querying EC Change-Id: I21337000827639fb8f22c5ee9bc5d86f1ebe1e74 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/17283 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11src/vboot: mark factory_initialze_tpm() as staticVadim Bendebury
This function is not used anywhere else in the code. BRANCH=none BUG=none TEST=reef and kevin boards (using tpm1.2 and tpm2.0 respectively) build successfully. Change-Id: Ifcc345ae9c22b25fdcfc2e547e70766021d27e32 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/17387 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-11intel cache-as-ram: Unify stack setupKyösti Mälkki
No need to have %ebx reserved here. Change-Id: I9fe9292ddc610079b876019a71c69af5b1bcf2a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17357 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11intel post-car: Separate files for setup_stack_and_mtrrs()Kyösti Mälkki
Have a common romstage.c file to prepare CAR stack guards. MTRR setup around cbmem_top() is somewhat northbridge specific, place stubs under northbridge for platrform that will move to RELOCATABLE_RAMSTAGE. Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15762 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11intel/sandybridge: Use common ACPI S3 recoveryKyösti Mälkki
Fix regression, S3 resume not working on sandy/ivy after commit 9d6f365 ACPI S3: Remove HIGH_MEMORY_SAVE where possible There is some 20ms delay with ACPI S3 wakeup time due to MTRR setup being done after the backup copy. Moving to RELOCATABLE_RAMSTAGE fixes this delay by removing need of this backup entirely. Change-Id: Ib72ff914f5dfef8611f5f6cf9687495779013b02 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15248 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11google/snappy: update timing of sdmode togglingWisley Chen
Maxim98357a speaker amp requires BCLK & SFRM to be active and stable before it is unmuted. If there is a BLCK and no SFRM, it results in a pop sound. sdmode_delay property already exists which facilitates this configuration. This patch updates "sdmode_delay" to avoid pop sound. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ic9095ae6812ba822c760229e69f5b27c6c244cdf Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17361 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11mainboard/google/snappy: Set PL1 override to 12000mWWisley Chen
Snappy is using APL SoC SKU's with 6W TDP max. As Reef, the energy calculation is wrong with the current VR solution. Experiments show that SoC TDP max (6W) can be reached when RAPL PL1 is set to 12W. Therefore, we've inserted 12W override after reading the fused value (6W) so that the system can reach the right performance level. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Idd702077cd05e2b43823542cb804b2d4b42f7116 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17362 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11soc/intel/common/lpss_i2c: simplify API and use common config structureAaron Durbin
The apollolake and skylake had duplicate stanzas of code for initializing the i2c buses. Additionally, they also had very similar structures for providing settings for the i2c speed control. Introduce a new struct lpss_i2c_bus_config and utilize it in both apollolake and skylake thereby removing the need for SoC-specific structres. The new structure is used for initializing a bus fully as the lpss i2c API is simplified in that lpss_i2c_init() is only required to be called. The struct lpss_i2c_bus_config structure is passed in for both initializing and filling in the SSDT information. The formerly exposed functions are made static to reduce the external API exposure. BUG=chrome-os-partner:58889 Change-Id: Ib4fa8a7a4de052da75c778a7658741a5a8e0e6b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17348 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-11soc/intel/skylake: move i2c voltage config to own variableAaron Durbin
In preparation of merging the lpss i2c config structures on apollolake and skylake move the i2c voltage variable to its own field. It makes refactoring things easier, and then there's no reason for a separate SoC specific i2c config structure. BUG=chrome-os-partner:58889 Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17347 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-10mainboard/google/reef: Add digitizer device to devicetreeFurquan Shaikh
BUG=chrome-os-partner:56246 BRANCH=None TEST=Verified kernel is able to talk to the device. Even without the digitizer, no issues observed with the kernel. Change-Id: I894a5f4cd8f6a51e641a2c8f7b1f682ab76712ae Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17343 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-10mainboard/google/reef: Tune digitizer I2C frequency to 400kHzFurquan Shaikh
This brings the I2C frequency down to 400kHz which is spec for fast I2C. BUG=chrome-os-partner:56246 BRANCH=None TEST=Verified frequency in kernel. Change-Id: Ib83c57eec8644903cb9c4b2ab50c94038eb690c1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17342 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10drivers/i2c/wacom: Make the driver more genericFurquan Shaikh
Wacom I2C driver can be used by devices other than touchscreen. e.g. digitizer. So there is no need to name the driver with touchscreen specific attributes. Only a separate descriptor name is required that needs to be set by mainboard correctly. BUG=chrome-os-partner:56246 BRANCH=None TEST=Compiles successfully. Change-Id: I0d32a4adae477373b3f4c5f3abbe188860701194 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17341 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10intel/kblrvp: Program I/O expanderNaresh G Solanki
Program I/O expander connected on I2C bus 4 Change-Id: I1a431f50e7b06446399a7d7cb9490615818147e7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17338 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10drivers/intel/fsp2_0: Add support for recovery MRC hash space in TPMFurquan Shaikh
This space is read/updated only in recovery mode. 1. During read phase, verify if the hash of MRC data read from RECOVERY_MRC_CACHE matches the hash stored in TPM. 2. During update phase, calculate hash of training data returned by MRC and save it in TPM. BUG=chrome-os-partner:59355 BRANCH=None TEST=Verified MRC data hash comparison and update operation on reef. Change-Id: Ifcbbf1bd22033767625ec55b659e05fa7a7afc16 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17274 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10vboot: Add support for recovery hash space in TPMFurquan Shaikh
1. Add a new index for recovery hash space in TPM - 0x100b 2. Add helper functions to read/write/lock recovery hash space in TPM 3. Add Kconfig option that can be selected by mainboards that want to define this space. 4. Lock this new space while jumping from RO to RW. BUG=chrome-os-partner:59355 BRANCH=None TEST=Verified use of recovery hash space on reef. Change-Id: I1cacd54f0a896d0f2af32d4b7c9ae581a918f9bb Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17273 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10mainboard/thomson/ip1000: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/thomson/ip1000. Change-Id: Id7b979d2539d4a80609a60464527939c4d449822 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17308 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/supermicro/h8qme_fam10: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/supermicro/h8qme_fam10. Change-Id: Ia03c205ce498eadf8a34749a6a21fb2d0b29c840 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17306 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/supermicro/h8qgi: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/supermicro/h8qgi. Change-Id: I6cf123272283edbf89e854e4aa1a15a2d566133e Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17305 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/roda/rk9: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/roda/rk9. Change-Id: I56fec2a2814ee4b91b11f71dbdca1271792cd0e5 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17302 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/roda/rk886ex: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/roda/rk886ex. Change-Id: I2e88adc444dbbde7a4344829d7bd5a6c9e1f7531 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17301 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/rca/rm4100: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/rcs/rm4100. Change-Id: I8b242eefe796cd93337177fc694ea42c57c53f08 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17300 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/google/pyro: Set PL1 override to 12000mWKevin Chiu
Pyro is using APL SoC SKU's with 6W TDP max. As Reef, the energy calculation is wrong with the current VR solution. Experiments show that SoC TDP max (6W) can be reached when RAPL PL1 is set to 12W. Therefore, we've inserted 12W override after reading the fused value (6W) so that the system can reach the right performance level. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17335 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10google/pyro: Tune i2c frequency to 400 KhzKevin Chiu
tune i2c devices clk for pyro: I2C0: audio da7219 I2C2: TPM H1 I2C3: wacom touchscreen I2C4: elan touchpad BUG=chrome-os-partner:58881 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: If3c92ed260277c27a94d2fcf7883e9441519e40e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10google/pyro: update timing of sdmode togglingKevin Chiu
Maxim98357a speaker amp requires BCLK & SFRM to be active and stable before it is unmuted. If there is a BLCK and no SFRM, it results in a pop sound. sdmode_delay property already exists which facilitates this configuration. This patch updates "sdmode_delay" to avoid pop sound. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: I5aee41957c9de7a05f962d3ede74efc6998a78fc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10mainboard/google/pyro: Configure PERST pinKevin Chiu
Configure GPIO 122 as PERST. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: Id760251a1b037feb62ec43199a145e407b074769 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10mainboard/kontron/ktqm77: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/kontron/ktqm77. Change-Id: I47763d1e2bfeee6366ce24b20d874adf7c6f65be Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17299 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-10antirollback: Sync TPM space indices with vboot libraryFurquan Shaikh
BUG=chrome-os-partner:59355 BRANCH=None TEST=Compiles successfully for reef. Change-Id: I27f2e10556214598d479e4a84e8949465e7da7d6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10TPM: Add TPM driver files to romstageFurquan Shaikh
This driver is required for reading and updating TPM space for recovery MRC data hash in romstage. BUG=chrome-os-partner:59355 BRANCH=None TEST=Compiles successfully for reef. Change-Id: I8edb7af13285a7a192e3d55fc6a11cfe12654bf9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17270 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-10mainboard/google/reef: Add support for RECOVERY_MRC_CACHEFurquan Shaikh
1. Add RECOVERY_MRC_CACHE region to reef FMAP. 2. Implement helper function for getting event for recovery mode with memory retraining. 3. Select HAS_RECOVERY_MRC_CACHE. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified recovery mode behavior with and without memory training request on reef. Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17243 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10mrc: Add support for separate training cache in recovery modeFurquan Shaikh
1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or RECOVERY_MRC_CACHE based on the boot mode. - If normal mode boot, use RW_MRC_CACHE, if available. - If recovery mode boot: - Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is requested explicity with retrain memory request. - Use RECOVERY_MRC_CACHE otherwise. 2. Protect RW and RECOVERY mrc caches in recovery and non-recovery boot modes. Check if both are present under one unified region and protect that region as a whole. Else try protecting individual regions. 3. Update training data in appropriate cache: - Use RW_MRC_CACHE if normal mode. - Use RECOVERY_MRC_CACHE if present in recovery mode. Else use RW_MRC_CACHE. 4. Add proper debug logs to indicate which training data cache is used at any point. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that correct cache is used in both normal and recovery mode on reef. Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17242 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10vboot: Add support for recovery mode with forced memory retrainingFurquan Shaikh
1. Add new function vboot_recovery_mode_memory_retrain that indicates if recovery mode requires memory retraining to be performed. 2. Add helper function get_recovery_mode_retrain_switch to read memory retrain switch. This is provided as weak function which should be implemented by mainboard just like {get,clear}_recovery_mode_switch. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified behavior of recovery mode with forced memory retraining on reef Change-Id: I46c10fbf25bc100d9f562c36da3ac646c9dae7d1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17241 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10southbridge/amd: Remove debug echo when building PIMartin Roth
If this information is needed, use make V=1. That will print the actual command, not a command that needs to be updated with every addition if it's going to stay in sync. Change-Id: I64d33d93c7fad3359d8ef78657bdb86d1fb4d4a1 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17328 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10southbridge/amd: update for amdfwtool size on command lineMartin Roth
amdfwtool was getting the ROM size as a #define when it was built. It has been updated to pass it in as a command line parameter, so now it can be built just once for abuild as a shared tool. Update the calls to amdfwtool to pass the ROM size. All platforms using amdfwtool had the output verified using a binary compare. This reverts commit 0529236ed22f1a28d29f2054674004c4f7a056e7 (Makefile.inc: Don't share amdfwtool between platforms) Change-Id: I188b34e08249f2d00bd48957ced750b21f1ec348 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17327 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10Revert "vboot: Add vboot library to romstage"Furquan Shaikh
This reverts commit 21fdd8d0b2206be85dd920e94fb9657a22ab5226. I meant to abandon the original change and clicked submit instead. Change-Id: I1db29b62c5c071113d308583f094f77285c9ba1e Reviewed-on: https://review.coreboot.org/17346 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10vboot: Add vboot library to romstageFurquan Shaikh
This library is needed for calculating sha-256 of recovery mrc data in romstage. BUG=chrome-os-partner:59355 BRANCH=None TEST=Compiles succesfully for reef. Change-Id: Ie257208c7b3ad07d00e4eb777debf19c42a2fc0c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17271 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10google/chromeec: Sync ec_commands.h host events with ec codebaseFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully for reef Change-Id: Ibfa5681e16a97e342633104d2aae1fb0402939b8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17240 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-11-10mainboard/kontron/986lcd-m: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/kontron/986lcd-m. Change-Id: Ib47a4bb3580cb72ee51fb06c6faa6d2d1bd3a80c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17298 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09southbridge/intel/i82801dx: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside southbridge/intel/i82801dx. Change-Id: I32888930d3742432a73dfc0a32c6586186e6757c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17297 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/jetway/j7f2: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/jetway/j7f2. Change-Id: I37f59f74ac22fbf6e036cdb0515301e8dec400fb Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17296 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/iei/pm-lx2-800-r10: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/iei/pm-lx2-800-r10. Change-Id: I60e5b84141aa4998427c3ecaadf8fce1654b8210 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17295 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/ibase/mb899: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/ibase/mb899. Change-Id: Id5b460090db58e91b2c210d8633a69114a9c7f6b Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17294 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/getac/p470: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/getac/p470. Change-Id: Ifb81976ed7068f9d51edb0d297cd4a12265c51ec Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17293 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09soc/intel/skylake: fix memory access beyond array boundsRizwan Qureshi
chip.h has a config array PcieRpClkReqNumber which corresponds to a FSP UPD parameter, the size is currently set to 20. However the size of PcieRpClkReqNumber UPD in FSP2.0 is 24, so memcpy (config buffer to UPD buffer) in chip_fsp20.c will read beyond the bounds of config array. Hence set the size of PcieRpClkReqNumber array based on the FSP in use. Found-by: Coverity Scan #1365385, #1365386 Change-Id: I937f68ef33f218cd7f9ba5cf3baaec162bca3fc8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/17292 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09amd/cpu: Add details to chip namesMarshall Dawson
Newer AMD families have multiple models within them, each often requiring unique support. The chip_name files were starting to have a lot of duplication. Specify the model in the name, as well as the family. Change-Id: I236b260e2a565e212c486347c4a633eadcdf0042 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17187 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09nb/amd/amdmct/mct: Remove commented codeElyes HAOUAS
Change-Id: Id0c62cebfceaf083f1bb39514b06b32c55128b85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17172 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/roda: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I4ce2705a8a07d0388bbdb459b63b59fc10a3aa39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16929 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09nb/intel/i945/early_init.c: Add DDR2-667 detection for 945GCElyes HAOUAS
945G-M4 returns : "unknown max. RAM clock (2)", however, it supports up to DDR2-667MHz. i945/raminit.c sdram_capabilities_max_supported_memory_frequency() function returns 667 for case 2. Change-Id: I3d54c88af897a71db757d00288f3968ed2c19151 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17191 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-09cpu/intel: Add MSR to support enabling turbo frequencyShaunak Saha
This patch adds definition FREQ_LIMIT_RATIO MSR. FREQ_LIMIT_RATIO register allows to determine the ratio limits to be used to limit frequency. BUG=chrome-os-partner:58158 BRANCH=None Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/17211 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09AMD binaryPI: Delay ACPI S3 backup until ramstage loaderKyösti Mälkki
Change-Id: I482cf93fe5dfab95817c87c32aad33df2e0a6439 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09AGESA: Delay ACPI S3 backup until ramstage loaderKyösti Mälkki
Change-Id: I59773161f22c1ec6a52050245f9ad3e6cc74a934 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15470 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09ACPI S3: Remove HIGH_MEMORY_SAVE where possibleKyösti Mälkki
Add implementation to use actual requirements of ramstage size for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB. Only the required amount of low memory is backed up when ACPI_TINY_LOWMEM_BACKUP is selected for the platform. Enable this option for AGESA and binaryPI, other platforms (without RELOCATABLE_RAMSTAGE) currently keep their romstage ramstack in low memory for s3 resume path. Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-11-09mainboard/google/reef: use common google smbios mainboard versionAaron Durbin
BUG=chromium:663243 Change-Id: Ic78a6aac11a8e842911245c59e8ced7ed2c4e27a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17291 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-09vendorcode/google: add common smbios mainboard version supportAaron Durbin
Provide an option to deliver the mainboard smbios version in the form of 'rev%d' based on the board_id() value. BUG=chromium:663243 Change-Id: If0a34935f570612da6e0c950fd7e8f0d92b6984f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17290 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-09string.h: only guard snprintf() with __ROMCC__Aaron Durbin
There's no need to keep the snprintf() declaration hidden for early stages. romcc is the entity that has issues. Therefore, be explicit about when to guard snprintf(). BUG=chromium:663243 Change-Id: Ib4d0879e52c3f73c6ca61ab75f672f0003fca71f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17289 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-09google/pyro: Update WACOM touchscreen ACPI _HIDJanice Li
WACOM request to add a new identifier `WCOMNTN2`, and use that for the board Pyro with all LCD combinations. BRANCH=master BUG=chrome-os-partner:58093 TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage Signed-off-by: Janice Li <janice.li@quantatw.com> Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307 Reviewed-on: https://review.coreboot.org/17257 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-09ec/acpi: Include ec.c unconditionally in romstageNico Huber
Dependencies on EC code should be specified at board level and not here. We can include the file unconditionally in romstage and let the linker decide if it's needed. Change-Id: Ie2d1970ac1dd175a9d42651573a88cd866f19cb9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17123 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09Move select UDELAY_LAPIC from nb/gm45/Kconfig to cpu/model_1067x/KconfigArthur Heymans
Change-Id: I51cf4f35bf2ea95c8c19ab885e6308535314b0af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17153 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09nb/intel/gm45: Use LAPIC udelay instead of custom versionArthur Heymans
This change may slow down the raminit by maximum 200usec, but reuses the lapic udelay definition. Change-Id: I60a68f8a7911b257c0eecda96f7c5bf302bb51ed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17152 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08mb/lenovo/t400: use socket mPGA478MN instead of BGA945Arthur Heymans
The T400 features a socket P (mPGA478MN) and could potentially support model_6fx CPUs. Change-Id: I24f3356aa213c29011953daed31f46404e7a4d9d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17155 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08cpu/intel/socket_mPGA478MN: Add socket PArthur Heymans
This mobile CPU socket supports model_6fx and model_1067x. Change-Id: Iecd6aae22831de7c3810545f0cb0be9738f96a2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17154 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-11-08mb/gigabyte/ga-945gcm-s2l: add mainboardArthur Heymans
Startpoint was Intel d945gclf, which has same chipset and Gigabyte ga-g41m-es2l which has same Superio. What works and is tested: * PCI slot; * PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card; * onboard VGA output (only textmode implemented) with native graphic init; * 533, 800, 1067MHz FSB CPU (1333MHz is unsupported by the chipset); * serial output during and after boot. What does not work: * resume from suspend (does not work for d945gclf either). Quirks: * The Realtek ethernet card requires a reset which currently also hardcodes a MAC adress. This board was only tested with the SeaBIOS payload due to flash size constraints (512KB) and with GNU/Linux. Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17033 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08soc/intel/apollolake: Provide chipset value for ifdtoolAndrey Petrov
Change-Id: I99454a9fca3b677a389bcaf7693ff4e18415c9ad Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17259 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-08southbridge/intel: Set chipset in ifdtool invocationsAndrey Petrov
Since IFD format is floating, ifdtool needs to be parameterized with a chipset it is dealing with. Add -p <chipset> argument to ifdtool invocations if chipset provides it. Change-Id: I4fd1783b5d994617912aedcf17adc2a98c97227b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17258 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08nb/x4x/raminit.c: Improve crossclock table cosmeticsArthur Heymans
Change-Id: I3f692c55fdff99aa9eb41eaaea79a41ac93be590 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17170 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08vboot: Wrap line in comment longer than 80 charactersNaresh G Solanki
Fix comment greater than 80 columns. Change-Id: Ie0be96868e8a99f79781c6bafc8991a955f37ffa Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17265 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-08intel/kblrvp: Update mainboard configurationNaresh G Solanki
Update devicetree.cb as per RVP3 mainboard. * Enable & configure PCIE ports, * Enable & configure USB ports, * Enable SSIC for WWAN, * Disable unused I2C ports, * Disable deep S5, * Disable HDA, * Update VR config, Updated gpio.h to disable pull down for SoC power button. Change-Id: I235a1d44dabef16ded2aaad13aef36ca57f37c8e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17247 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-08intel/e7501: Remove unused northbridge codeKyösti Mälkki
No boards left in the tree for this northbridge. Change-Id: Id45da11b9d78cbd6bd50acb5a3c6c3c270f9020e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17281 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-08intel post-car: Split legacy socketsKyösti Mälkki
Move old sockets to use romstage_legacy.c, these are ones using intel/car/cache_as_ram.inc. These will not be converted to RELOCATABLE_RAMSTAGE as boards are candidates for getting dropped from the tree anyways. Change-Id: I2616b4edee53446f1875711291e9dfed2911e2fb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-08quick_ram_check: Remove reference to RAMBASEKyösti Mälkki
Change-Id: Ieb8f11690fb0e9b287d866be56010bb9adefd21d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15239 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-08intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZEKyösti Mälkki
Not referenced in code. Change-Id: Iea91f4418eb122fb647ec0f4f42cb786e8eadf23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17268 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07mainboard/intel/kblrvp: Remove unused code in dptf.aslNaresh G Solanki
Remove unused code from dptf.asl Change-Id: Icaa675fd1052367457d6e50d51d567e7db02fd42 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17249 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07mainboard/intel/kblrvp: Configure usb over current pin & cdclockNaresh G Solanki
Configure overcurrent pins for various usb ports. Configure CdClock to 3. Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17251 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 11:00:10 +0000