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2021-01-25mb/libretrend/Kconfig: Remove duplicated stringElyes HAOUAS
Change-Id: Iab19538e1f5a74b714cb2a34855d9717315b9018 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-01-25mb/51nb/Kconfig: Remove duplicated stringElyes HAOUAS
Change-Id: Ib184dbfef05608bbf18d49fee5cbc9dd12ed6751 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49883 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25src/lib/: Remove "this file is part of" lineElyes HAOUAS
Change-Id: I9031dad52581e77aa56014b1fede884f2cdeb6de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49882 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroringMichael Niewöhner
Drop the old, redundant code for mirroring LPC registers to DMI and make use of the new common code. Select the new Kconfig option for LPC DMI mirroring by the option SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig directly. APL, even though it's younger than SPT, does not need mirroring. Test: Set LGMR address by calling `lpc_open_mmio_window` and check that both the PCI cfg and DMI LGMR register get written correctly. Tested successfully on clevo/cml-u. Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-25soc/intel/lpc_lib: mirror LPC registers to DMI when requiredMichael Niewöhner
Starting with SPT, LPC registers IOD, IOE, LGIR* and LGMR need to be mirrored to their corresponding DMI registers. Add the required writes to DMI registers, where the PCI config registers get written. This is already done in soc code for IOD, IOE and LGIR* by mirroring the registers later, during PCH init. Also the code mostly matches accross the platforms. This common implementation will avoid delayed mirroring of the registers and also deduplicate the code. This change also adds a new Kconfig that will be selected by platforms requiring mirroring of LPC IO/MMIO registers to their corresponding DMI registers. For making use of this common code, the redundant soc code needs to be dropped and the newly introduced Kconfig option has to be selected. This is done in the follow-up change. Change-Id: I39f3bf4c486a1bbc112b2b453381de6da4bbac4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-25mb/google/dedede/var/boten: Add custom SAR values for BotenKevin Chang
Add Boten customized SAR table. BUG=b:175931508 BRANCH=dedede TEST=build and test no Boten Change-Id: I3b00f56c8b890979cbf2155c97a3a064d8b0ba1a Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-25mb/google/dedede/var/magolor: Enable EC keyboard backlightTim Chen
BUG=b:177288782 TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I98f741da4a22494883939c4efe7960c66e71c6a7 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-25drivers/intel/fsp2_0/header_display.c: Correct component_attribute checkBenjamin Doron
According to FSP_INFO_HEADER structure in FSP EAS v2.0-v2.2, BIT1 indicates an "official" build. Change-Id: I94df6050a1ad756bbeff60cda0ebac76ae5f8249 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25mb/google/dedede/var/sasuke: Enable bluetooth deviceSeunghwan Kim
"usb2_ports[7]" for internal bluetooth device was configured as 'USB2_PORT_EMPTY' mistakenly in previous patch, so we need to enable it again. BUG=None BRANCH=firmware-dedede-13606.B TEST=Built and verified BT device existence with lsusb Change-Id: Id2900152e23bbc2f454d064dc86a9e45e934ea0f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25trogdor: Explicitly initialize display pins in bootblockJulius Werner
This patch adds explicit initializations for the remaining named display (power) control GPIOs to the bootblock GPIO init code. These pins are usually mapped to pins that are already configured to pull-downs on power-on reset so this wasn't really required, but we have already moved them around so often that you never know when EEs might one day move them to a pin with a different power-on reset configuration, so it's better to be explicit. In one particular case, GPIO(67) (used by CoachZ rev1+ but not by anything else for the EN_PP3300_DX_EDP pin) is not actually a pull-down on boot, even though that is claimed by the datasheet. This is likely due to the fact that it can serve as the SPI_HOLD pin for the boot flash QSPI bus, so even though our board's boot flash doesn't really use that pin, it seems that the boot ROM still configures it as such. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I533baa962d2dfc87cfa510f442ed2e8912e0e5b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: mturney mturney <mturney@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2021-01-25arm64/armv8: Set ARCH_ARMV8_EXTENSION depend on ARCH_ARM64Elyes HAOUAS
This will remove "ARCH_ARMV8_EXTENSION=0" from ".config" when unneeded. Change-Id: Idd4ad67fb4a3efdb0864803f87c6b5f508fb4364 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-25soc/intel/xeon_sp/cpx: Fix loading MCU on APsArthur Heymans
Commit 393992f (cpu/mp_init: Fix microcode lock) fixed the semantics of parallel loading microcode updates. So now '*parallel = 1' really means loading MCU in parallel, which seems to fail inconsistently on around 10% of the APs. Change-Id: I755dd302abbb58537d840852e8e290bea282a674 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49671 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd/common/acpi: Add _UID for PNP0C02 devicesRaul E Rangel
When MAINBOARD_HAS_SPEAKER is false, the SPKR gets _HID PNP0C02. This conflicts with the LDRC device. PNP0C02 is also used other places in the picasso code base, so I chose a random _UID for each device. The _UIDs are unique in the code base so it's easy to search for duplicates. BUG=b:175146875 TEST=Boot trembyle to linux Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I01be41515e011293e90a6b42b8e34de8ec3ffc18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25mb/google/zork: Fix duplicate i2c_tunnel uidRaul E Rangel
This conflicts with the MSTH i2c_tunnel. BUG=b:175146875 BRANCH=zork TEST=Boot trembyle and inspect ACPI tables. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iac04c7dc361d427f5ebb99644aa70bd0c7dbb918 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25soc/amd/picasso/acpi: Add UID for PCI INT devicesRaul E Rangel
If a _HID/_CID are not unique, we need to add a _UID field to differentiate the objects. BUG=b:175146875 BRANCH=zork TEST=Boot linux, dump ACPI table and verify UIDs are unique Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icd2ccede2b6c2e332157e2eeca89fba14a46b360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25mb/google/volteer/eldrid: Use #define symbols for usb2_ports configTim Wawrzynczak
It's easier to understand what these symbolic names mean rather than using the constants; the static.c will will end up (indirectly) including `soc/usb.h` therefore the macros are in scope here. Change-Id: I5ef977a05a2522e177f32c99bfab74f9288ae869 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-25mb/google/zork: update USB 2.0 controller Lane Parameter for gumbozKevin Chiu
From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1) the most effective corrections for the depressed eye are tx_rise_tune=0x0 tx_pre_emp_amp_tune=0x3 tx_fsls_tune = 0x3 BUG=b:173476380 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass USB 2.0 SI eye diagram verification Change-Id: Ib31c5d55e30b958d3e552e8d0b4a160947444636 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-25mb/google/zork: update USB 2.0 controller Lane Parameter for dirinbozKevin Chiu
From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1) the most effective corrections for the depressed eye are: tx_rise_tune=0x0 tx_pre_emp_amp_tune=0x3 tx_fsls_tune = 0x3 BUG=b:165209698 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass USB 2.0 SI eye diagram verification Change-Id: I80afd6bf1257b9a72d0d7651b48d243ebaf5de2f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-01-25mb/google/kahlee: Deduplicate now-equivalent mainboard.cAngel Pons
The only difference is an additional include that is no longer needed. Change-Id: I0053d03aa4d05f5c0fa833d8634419b6667e38a7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49832 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25bayhub bh720: Configure VIH tuning via devicetreeAngel Pons
There's no need to repeat the same code on every board. Change-Id: I2e19decfe8609fa644e609673a56ee5109bafefa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49831 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driverFurquan Shaikh
This change uses the newly added meminit block driver and updates TGL SoC and mainboard code accordingly. TEST=Verified that UPDs are configured correctly with and without this change. Change-Id: I6d58cd6568b7bbe03c4e3011b2301209893e85a9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-25soc/intel/common: Add support for populating meminit dataFurquan Shaikh
This change adds support for a common block memory driver that can be used for performing the required operations to read SPD data for different memory channel DIMMs. This data can then be used by the SoC code to populate different memory related UPDs. Most recent Intel platforms follow a similar pattern for configuring FSP-M UPDs for initializing memory. These platforms use one of the following topologies: 1. Memory down 2. DIMM modules 3. Mixed Thus, SPD data is either obtained from CBFS (for memory down topology) or from on-module EEPROM (for DIMM modules). This SPD data read from CBFS or EEPROM is then passed into FSP-M using SPD UPDs for different channels/DIMMs as per the memory organization. Similarly, DQ/DQS configuration is accepted from mainboard and passed into FSP-M using UPDs as per the FSP-M/MRC organization of memory channels. Different memory technologies on a platform support physical channels of different widths. Since the data bus width is fixed for a platform, the number of physical channels is determined by data bus width / physical channel width. The number of physical channels are different depending upon the size of physical channel supported by the memory technology. FSP-M for a platform uses the same set of UPDs for different memory technologies and aims at providing maximum flexibility. Thus, the platform code needs to format mainboard inputs for DQ, DQS and SPD into the UPDs appropriately as per the memory technology used by the board. Example: DDR4 on TGL supports 2 physical channels each 64-bit wide. However, FSP-M UPDs assume channels 16-bit wide. Thus, FSP-M provides 16 UPDs for SPDs (considering 2 DIMMs per channel and 8 channels with each channel 16-bit wide). Hence, for DDR4, only the SPD UPDs for MRC channel 0 and 4 are supposed to be used. This common driver allows the SoC to define the attributes of the platform: 1. DIMMS_PER_CHANNEL: Maximum DIMMs that are supported per channel by any memory technology on the platform 2. DATA_BUS_WIDTH: Width of the data bus. 3. MRC_CHANNEL_WIDTH: Width of the channel as used by the MRC to define UPDs. In addition to this, the SoC can define different attributes of each memory technology supported by the platform using `struct soc_mem_cfg`: 1. Number of physical channels 2. Physical channel to MRC channel mapping 3. Masks for memory down topologies Using the above information about different memory technologies supported by the platform and the mainboard configuration for SPD, the common block memory driver reads SPD data and provides pointers to this data for each dimm within each channel back to the SoC code. SoC code can then use this information to configure FSP-M UPDs accordingly. In addition to that, the common block driver also returns information about how the channels are populated so that the SoC code can use this information to expose DQ/DQS information in FSP-M UPDs. This driver aims at minimizing the effort required for supporting different memory technologies on any new Intel SoC by reducing per-SoC effort to a table of configurations rather than having to implement similar logic for each SoC. BUG=b:172978729 Change-Id: I256747f0ffc49fb326cd8bc54a6a7b493af139c0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49040 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/intel/tigerlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGDBora Guvendik
Make IGD disable when mainboard user selects SOC_INTEL_DISABLE_IGD. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib297b339ce15ccb9212da32b27022610bc8aa2b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-25mb/asus/p5ql-em/Kconfig: Drop 'select ARCH_X86'Elyes HAOUAS
ARCH_X86 is already selected. Change-Id: I2be69e0b7a1889794121ed94380e543ac420218b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methodsAngel Pons
Creating named objects within a method is highly inefficient. So, pass a reference to the OperationRegion field that needs to be updated instead. Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-24cpu/intel/model_2065x: Drop configurable TDP copy-pastaAngel Pons
Configurable TDP is only supported by Ivy Bridge onwards. Change-Id: I8a742ab6d9d22b325ed725df4f749955efb3028f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24cpu/intel/model_2065x: Drop unused c-state codeAngel Pons
None of the mainboards have the magic SpeedStep device, so the C-state generation function bails out without doing anything. Moreover, this code is broken and was copied from Sandy Bridge. Thus, drop it. Change-Id: I580157ee33c599af5fc48b06eeb39cb32c9831ec Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24soc/intel/broadwell: Drop enable check from LPD0/LPD3Angel Pons
When SerialIO devices are disabled, their _STA method evaluates to 0, which means the device is not present. It is expected that OSPM would not attempt to change the power state of a device that is not present. Lynxpoint does not have these checks, thus remove them from Broadwell. Also remove the now-unused Arg1 parameter to avoid warnings from IASL. Change-Id: Ic5e999ac1171ce49db66bec45c58d8aa5711ec53 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/google/poppy: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are identical. Change-Id: I4f8b77b3f196ca51346bb7932a40875c4dd5d2a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24ec/google/wilco: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ie5c88f8acee16ff77f9707d7ed56436bf0d521b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24ec/compal: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I934f9d1664f657597f15daed2d2d0c41cd124d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24ec/acpi: Convert 'ec.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ifd85d2eabbda4e25406f20391489c0e7ad314348 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/razer: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl are same. Change-Id: I9c7cbc4ee874657a7381b1b220872c4ebecd0821 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46085 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24mb/packardbell: Convert to ASL 2.0 syntaxElyes HAOUAS
Built for packardbell/ms2290 provides same build/dsdt.dsl file. Change-Id: I5f1dbb2595c3ee8cb35bb8a6431288f4a96ce978 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lippert: Convert to ASL 2.0 syntaxElyes HAOUAS
Built provides same dsdt.dsl file for lippert/frontrunner-af Change-Id: I61d8af98e2003547e332f463b23c1e1cf79f7f00 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/x230: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I18667ae74454e0db83fb40d8f130909510ddc379 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/x1_carbon_gen1: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I9764d90e713f35d54056fbafae3e3ada18bea1eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/x131e: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I3bee00030f03577b0449202233f7e76f7de96339 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/t530: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I95eab372b3c6b6df5231f0d232e878576bab5290 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/t520: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ice7cfc263c339ba9ec3705c1cee44a6d69f2e4d3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/t440p: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I91e25fe62080582b925fa1f1a88512f318ab9415 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/t430s: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I2825dff6b68da9b1e2bb13f03a4251af02438b66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/t430: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Id4a724193c4c120373a3e696ebd1fb7155fd8531 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/t420s: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I6e928c23165abad623ee3c2a26e090b029d55572 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/l520: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I9d0e4982888823bb62a174a603a126676e68e308 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/g505s: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I56f844706ba6bde3e57a6a81ff1d8e16863913f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/t420: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I3890f75e3c27a689e9d57b4708514160e1550fdb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/t410: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I5859c64b0ccd1dfdce040b2c3bbdd9192617ffbe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/x60: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are identical. Change-Id: I305561625d973093645236c77ef13a96ab780f94 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/x220: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I4c5c67d70e004eeece61e66d427d6f9df9cab4ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/x201: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I3b553e1b68ee8f236fcab311a076001b94a47975 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46204 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24mb/lenovo/x200: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are identical. Change-Id: I0767afcb0ffdd6f9a8d83209955d42d9e89325e9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/biostar/am1ml: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'dsdt.dsl' files are identical. Change-Id: Ifdd5008bcb9c7e41e637a30f70316c7926f927b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24soc/intel/quark/gpio_i2c.c: Use __func__Elyes HAOUAS
Change-Id: Id84a88933d32f60dd8d864d9a10d84a2b3c365ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24soc/intel/denverton_ns/pmc.c: Use __func__Elyes HAOUAS
Change-Id: I06134e48b2d33c178883fc2047bcfbad417c6d02 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24soc/intel/denverton_ns/npk.c: Use __func__Elyes HAOUAS
Change-Id: Ib0f425d74bc219ef518394526b51f2756eb95d61 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-01-24soc/intel/denverton_ns/lpc.c: Use __func__Elyes HAOUAS
Change-Id: Ic83a6a5db3b3d8a08c92064f8039d1bac825ffc3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mainboard/lenovo/s230u/smihandler.c: Use __func__Elyes HAOUAS
Change-Id: If46ef5ffbd3de82d793a095b011e5740b776ff14 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mainboard/intel/strago/ec.c: Use __func__Elyes HAOUAS
Change-Id: Ifa30e9d2a71eae9a438e84367fd8b4f8bd920983 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mainboard/intel/emeraldlake2/ec.c: Use __func__Elyes HAOUAS
Change-Id: I75f534245d37f401357b611efc5c190e8a872d02 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24ec/acpi/ec.c: Use __func__Elyes HAOUAS
Change-Id: I4823b84d851d7d1f0f48be44ab28e7365b553b6f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24drivers/intel/gma/opregion.c: Use __func__Elyes HAOUAS
Change-Id: Ia45825ade0c9d24d5b87882e21bfc6df82a693e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24drivers/elog/elog.c: Use __func__Elyes HAOUAS
Change-Id: I024a0c2d7c53634c58d5d80522933ecad554d7c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24device/pci_rom.c: Use __func__Elyes HAOUAS
Change-Id: I24c40d511eeaa5073acd2b47b20b4ec2f85bb69e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/t400: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I4e6d5048ca9e949a70f3619f05b74870c1f1fe30 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24mb/lenovo/s230u: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are identical. Change-Id: I8843d418bd9c34a4f079444bc6ce8ecd4559e36d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24ec/purism/librem/acpi/ec.asl: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ic773f8404c24fc886e8420a5f4b3e00b2d752ba2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24soc/samsung/exynos5250/dp-reg.c: Use __func__Elyes HAOUAS
Change-Id: I572ee7faaa4453d32852eea2b83b0b27c549abf2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-01-24arch/x86: Use wildcard for mb/smihandler.cKyösti Mälkki
Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24ACPI: Clean up GNVS initialisationKyösti Mälkki
With the common <soc/nvs.h> approach platform does not need to implement the common accessors or sizeof() function. Change-Id: I1050a252f765c763c1ae2d1610cbfb0d973ba026 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-24soc/amd/cezanne/Kconfig: select missing SSE2 optionFelix Held
This will set the corresponding enable bit in CR4 in bootblock_crt0.S Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I648a83fbcb71456bf1e5b11c491e7cadc8e0e281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24soc/amd/cezanne/Kconfig: select X86_AMD_FIXED_MTRRSFelix Held
This option will make the ramstage MTRR core set the additional bits in the fixed MTRRs that need to be set on AMD CPUs to enable caching. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94bca61acfc6e38a6d808eb5020537b4e8596178 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24soc/amd/cezanne: add basic romstageFelix Held
This currently only initializes the console, calls into the FSP driver that then calls into FSP-M and then jumps to ramstage after the FSP-M returns. Right now, this mainly unblocks the FSP-M development. Change-Id: I9f3cdaac573e365bb4d59364d44727677f53e91b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24soc,vendorcode/amd/cezanne: add basic FSP integrationFelix Held
This is a trimmed-down version of the Cezanne FSP integration code, so for example the UPD definitions are empty, which will be addressed later. Since coreboot just leaves the UPD values at their default, this is not a problem during the initial platform bring-up. Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24soc/amd/picasso: Remove some empty stringsZheng Bao
Change-Id: If1ff88010f8bf941ec6a76019c4b6a4cb9b31093 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-24soc/amd/cezanne: Add PSP integration for cezanneZheng Bao
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48528 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24soc/intel/xeon_sp/cpx: Account for 'rc' heap managerArthur Heymans
The xeon_sp/cpx has a second 'rc' heap inside FSP-M that is statically allocated at the start of CAR. This breaks FSP 2.0 specification. This can be worked around in the linker scripts to make sure coreboot and FSP-M don't fight over the same memory. Tested - on ocp/deltalake: boot and the "Smashed stack detected in romstage!" message at the end of romstage is gone. - qemu/i440fx: BUILD_TIMELESS=1 results in the same binary. Change-Id: I6d02b8a46a2a8ef00f34d8f257595d43f5d3d590 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-01-24arch/x86/car.ld: Account for FSP-T reserved areaArthur Heymans
Tested - on ocp/deltalake: boots (with FSP-T). - qemu/i440fx: BUILD_TIMELESS=1 results in the same binary. Change-Id: I7e364ab039b65766eb95538db6b3507bbfbfb487 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-24soc/intel/lpc_lib: drop dead codeMichael Niewöhner
Change-Id: I7cf5f97c3229fe6a72d70a36e8cff49ff3cf611b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-24soc/intel/icl: drop wrong, unused codeMichael Niewöhner
The ids used in function `soc_get_pch_series()` are not valid for Icelake. Since it's not even used, instead of fixing it, drop it. Change-Id: I4a1ee4b84f11ea314cb666ce4506ff90168da0ca Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49875 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24soc/intel/cnl: use Kconfig to determine PCH typeMichael Niewöhner
We already know the PCH type at build time, so there is no need to do runtime detection. Thus, use Kconfig and drop `get_pch_series()`. Change-Id: I470871af5f5954e91a8135fddf4a2297a514d740 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49874 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24soc/intel/broadwell: Align raminit with HaswellAngel Pons
Rename and split functions to match what Haswell does. Change-Id: I4f3e997dd934bdf7717a70603d9413eae93cf181 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24soc/intel/broadwell: Drop `struct romstage_params`Angel Pons
It is no longer necessary. Change-Id: Ib37c9de83badc6339dca6916aec8c34a43797652 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24broadwell: Flatten `mainboard_pre_raminit`Angel Pons
All Broadwell boards only use the `mainboard_pre_raminit` function to call `mainboard_fill_pei_data` and optionally `mainboard_fill_spd_data`. Move the declaration and weak definition of `mainboard_fill_spd_data` to platform code, replace the call to `mainboard_pre_raminit` in romstage.c with calls to `mainboard_fill_pei_data` and `mainboard_fill_spd_data`, and delete all other instances of `mainboard_pre_raminit` for Broadwell. Finally, delete now-empty romstage.c and spd.h files from mainboards. Change-Id: I3334b20bd7138bb753b996a137ff106e87c6e8a5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24broadwell: Clean up `mainboard_post_raminit`Angel Pons
Make it optional and change its signature. Change-Id: I4b5f3fb08e8954514ebf39e72c95aa62d66856d7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24soc/intel/broadwell/chip.h: Drop unused fieldsAngel Pons
Broadwell boards now use the CPU code for Haswell. Therefore, these devicetree options are no longer used anywhere and can be removed. Change-Id: Ib0d1b6eecc11a70d1a2614669353a8040c860535 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24soc/intel/broadwell: Select CPU_INTEL_HASWELLAngel Pons
This allows us to drop many now-redundant Kconfig options. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. The default configuration file also remains identical, as expected. Change-Id: I20b0200550508679bf2533342ce918b221dcf81e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24soc/intel/broadwell: Move romstage.c to HaswellAngel Pons
Broadwell no longer has CPU code. Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46951 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24soc/intel/broadwell: Drop now-unused CPU codeAngel Pons
All boards now use Haswell's CPU code, which also supports Broadwell. Change-Id: Ia0b8f7bf64334dd965baad0a30a7bb0ed81c4cac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46950 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24soc/intel/broadwell: Use Haswell CPU headersAngel Pons
Now that the boards use Haswell's CPU code, Broadwell can be updated. Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46949 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24mb/google/auron: Use Haswell CPU codeAngel Pons
The VR config and S0ix options are now specified for the CPU chip. Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46945 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24mb/google/jecht: Use Haswell CPU codeAngel Pons
Change-Id: I6c106b152bb2824e000232d23c2991898b2c4475 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46946 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24mb/intel/wtm2: Use Haswell CPU codeAngel Pons
Change-Id: I478576afa3b390cf5480298aafe6e049b5e90bff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46947 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24mb/purism/librem_bdw: Use Haswell CPU codeAngel Pons
Change-Id: I736bff90305952d279a10dfe90a2ee3a533220b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46948 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24soc/intel/broadwell: Allow to use Haswell CPU code insteadAngel Pons
This allows individual boards to be adapted to use Haswell CPU code. Also rename the CPU_SPECIFIC_OPTIONS symbol to avoid any collisions. Change-Id: I65e878dacf0a0d53fd8d4defce6684f4ceb92588 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46944 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24soc/intel/broadwell: Select INTEL_LYNXPOINT_LPAngel Pons
This allows the correct Haswell and Lynxpoint code to be used. Change-Id: Icbfc5bb11b1ea755a143fa340a3971376f4e5e91 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46958 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24cpu/intel/haswell: Add Broadwell CPUIDs and microcodeAngel Pons
Broadwell can now use the Haswell CPU driver. Change-Id: I36138cab72b1e3ad0ff7f6434996f5ce00de9d0d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46942 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24cpu/intel/haswell: Set C9/C10 vccminAngel Pons
Backport commit ab7586fa26 (broadwell: Set C9/C10 vccmin) to Haswell. Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46922 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24cpu/intel/haswell: Add fast ramp voltage for BroadwellAngel Pons
Backport commit 55228ba4b4 (broadwell: Changes from 2.2.0 ref code) to Haswell, to eventually migrate Broadwell to use the same Haswell code. Change-Id: I03d9ff16bcaab9091bd723ce933aa3f2d71e29b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46921 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24lib/edid_fill_fb: Relax bits_per_pixel constraintRaul E Rangel
The Picasso VBIOS is not setting the reserved_mask_size correctly. This change relaxes the constraint to allow bpp_mask <= bits_per_pixel. This is how the code previously used to work before CB:39002. BUG=b:177094598, b:177422379 TEST=boot zork and see depthcharge working Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2e67532fa949fbd673269d8d7f1c0d8af6124ac9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 13:35:26 +0000