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2022-05-24mb/google/brask/variants/moli: add fw_config for usb retimerRaihow Shi
add USBC0_RETIMER into 2, 3 bits for usb retimer. BUG=b:232486478 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Idaf2e53387476d344d2c838a6e762f5a4c582989 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-24device: Add log_resource()Kyösti Mälkki
This will replace LOG_{MEM/IO}_RESOURCE macros once the new resource constructors are available. Change-Id: I21b030dc42dcb8e462b29f49499be5fd31ea38f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24soc/intel/cmn/fast-spi: Add BIOS MMIO window as reserved regionWerner Zeh
Add the boot flash MMIO window to the resources to report this region as reserved to the OS. This is done to stay consistent with the reserved memory ranges by coreboot and make the OS aware of them. As x86 systems preserves the upper 16 MiB below 4G for BIOS flash decoding use the complete window for reporting independent of the actually used SPI flash size. This will block the preserved MMIO window. Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24mb/google/brya/var/kinox: Update the DPTF parametersDtrain Hsu
Follow the Thermal_paramters_list-0520.xlsx to modify DPTF baseline PL1 values. 1. Modify baseline PL1 min_power from 15000 to 12000. 2. Modify baseline PL1 max_power from 17000 to 25000. BUG=b:231380286 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ibd3098ee6bbf964cffddfcc9a4600cb7d81162d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64595 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Ricky Chang <rickytlchang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/google/brya/variants/nivviks: Add DPTF passive and critical policies for ↵Vidya Gopalakrishnan
Nivviks Add DPTF passive and critical policies for ADL-N Nivviks design. Temperature threshold for triggering Passive Policy is set to 75C and Critical Policy is set to 85C respectively for TSR0/1. BUG=b:224884901 BRANCH=None TEST=Build FW and test on Nivviks board. Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Change-Id: I5c9b9e8c2489c7da501ca136e2aa6fbc764bf400 Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64466 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/google/brya/baseboard/nissa: Enable DPTF for Nissa variantsVidya Gopalakrishnan
BUG=b:224884901 BRANCH=None TEST=Build FW and test on Nivviks board Change-Id: I3f5e8dd3d2ff517e27b0b08a0173f094bc6043bd Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-24mb/intel/ehlcrb: Adjust TSN GBE settings in devicetreeLean Sheng Tan
Set PCH TSN link speed to 1 Gbps and enable MultiVC for all TSN ports. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8d43c3ba8f02645c8ad2993f76e610d838b0151a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-24security/tpm/crtm: Use bootblock from FMAP on non x86 platformsWerner Zeh
All non x86 platforms use bootblock in FMAP (see Makefile.inc). Add a build time check for that so that all the other possibilities (CBFS or other places for the bootblock) are dropped at build time. Change-Id: Ic18336a0b79b5d319c2cdfecb7e1eeb89d241206 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24security/tpm/crtm.c: Fix !CONFIG_BOOTBLOCK_IN_CBFS measuringArthur Heymans
On some platforms the bootblock is not placed in cbfs, but embedded inside another binary that loads in into DRAM/SRAM. e8217b11f1 (Kconfig: Add an option to skip adding a cbfs bootblock on x86) removed adding a cbfs file containing the bootblock in that case. Change-Id: Id47ecedbc8713ebd5d9814f1c4faf43c52780447 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/google/brya: Create kuldax variantDavid Wu
Create the kuldax variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:233380254 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KULDAX Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I95c04768bbed8657d2858bcd66fc041f56910b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-24mb/google/brya/var/volmar: Add wifi sar tableRen Kuo
1. Add wifi sar table for volmar 2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG BUG=b:233319626 TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I09069bbc3a41b66ec9a88cfede46acc067209b01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2022-05-24mainboard/google/corsola: Fix incorrect timestamps in the eventlogYidi Lin
Timestamp '2000-00-00 00:00:00' is considered as the invalid format. Enable RTC to fix incorrect timestamp format in the eventlog. BUG=b:232035991 TEST=check the timestamp field in /var/log/eventlog.txt Change-Id: I8d9822075377734ef4a609ddeee79385fe7af0f0 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2022-05-24soc/intel/alderlake: Drop unused `PCH_DEV_SLOT_LPC` macroSubrata Banik
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the Alder Lake SoC PCI device list. BUG=none TEST=Able to build and boot taeko, google board. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib2ae40fcc4499de34534f27f03b4c359c37409e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-23soc/intel/apollolake: Enable SSDT for fast SPI controllerWerner Zeh
Since the fast SPI controller is hidden on Apollo Lake the OS cannot probe it and is therefore unaware of the reserved resources assigned in coreboot. Select 'FAST_SPI_GENERATE_SSDT' to enable SSDT creation to report the reserved resources to the OS. Change-Id: I23e77a0a01141dc4f299988d19509e6df555a654 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-23cpu/x86/smm: Remove heapArthur Heymans
Currently no smihandler uses heap. coreboot's heap manager also is quite limited in what it will free (only the latest alloc). This makes it a bad idea to use it inside the smihandler, as depending on the alloc usage the heap might actually be full at some point, breaking the smihandler. This also reduces the ramstage by 448 bytes on google/vilboz. Change-Id: I70cd822be17c1efe13c94a9dbd2e1038808b9c56 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-23mb/siemens/mc_ehl: Disable RAPLUwe Poeche
Disable RAPL for all mainboards based on mc_ehl for stable real time mode of CPUs. Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR register are cleared. Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-23soc/intel/elkhartlake/systemagent: Disable RAPL based on KconfigUwe Poeche
This patch provides the possibility for EHL based boards to disable RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch. On Elkhart Lake the way via setting relevant MSR bits does not work. Therefore the way via MCHBAR is choosen. Test: Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1. Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-22mb/google/guybrush: Remove TODO for ESPI functionsJon Murphy
The feature request was moved to Skyrim in the interest of time and effort. The bug was updated to reflect this, and the comment should be removed from the monkey island code base BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Id4ca43692aa56b6dba2f7acc1f924b30c1e966ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/64558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-22mb/google/guybrush: Remove unused sleep GPIO tableJon Murphy
On Guybrush, there wasn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function calls/overhead. BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic51ee4845d663acf34f050f7b3abf57a7c247c88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-21mb/gogle/skyrim/devicetree: enable display HDA deviceFelix Held
The HD audio controller of the GPU on bus A device 0 function 1 wasn't enabled, so it didn't get resources assigned. Enable it to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib9a4129ce594c5dd59f70e855fef5f2c04ebb9c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64554 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21mb/gogle/skyrim/devicetree: enable audio coprocessor deviceFelix Held
The ACP device on bus A device 0 function 5 wasn't enabled, so it didn't get resources assigned. Enable the ACP device to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc9376314213e9d624756519f703d508411cb1bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/64553 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21mb/gogle/skyrim/devicetree: enable crypto deviceFelix Held
The crypro device on bus A device 0 function 2 wasn't enabled, so it didn't get resources assigned resulting in this the Linux kernel error: [ 38.582036] pci 0000:04:00.2: attach allowed to drvr ccp [internal device] [ 38.582064] ccp 0000:04:00.2: enabling device (0000 -> 0002) [ 38.582175] ccp 0000:04:00.2: ioremap failed [ 38.582178] ccp 0000:04:00.2: initialization failed [ 38.582181] ccp: probe of 0000:04:00.2 failed with error -12 Enable the crypto device to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia812df6e59f3767dcbaa908fa620b62619590f85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64552 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edgeMario Scheithauer
There are three external Marvell PHY 88E1512 on this mainboard. The PHY IRQ comes with a falling edge but the EHL MAC side needs a rising edge signal. For that reason, we need an inversion of the IRQ polarity. Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-21soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarityMario Scheithauer
EHL MAC side expects a rising edge signal for an IRQ. Based on the mainboard wiring it could be necessary to change the interrupt polarity. This patch provides the functionality to invert a falling edge signal that comes from an external PHY. The inverting can be activated via devicetree parameter. Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-21mb/google/nissa: Change pen garage wake to EV_ACT_ANYEric Lai
Follow google stylus spec. The Stylus-Present GPIO MUST be a wake pin that interrupts the system in active operation when the stylus is removed or inserted. BUG=b:233159811 TEST=EC wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Icf609c647e19914684a93c89022f2cd4888a67ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/64538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-21soc/intel/apollolake: Hook up Sata Hot Plug to device treeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I37d31598e87e5b625ded3186980e3aba7dcf6440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-21soc/intel/apollolake: Hook up Legacy 8254 TimerSean Rhodes
Hook Timer8254ClkSetting to `legacy_8254_timer` cmos option. If that isn't set, fallback to the `USE_LEGACY_8254_TIMER` Kconfig option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f91cc2c8f48e9da47399059386092314b631b08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-21mb/google/brya/var/craask: Generate SPD ID for supported memory partTyler Wang
Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. H9JCNNNBK3MLYR-N6E BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ibb111cddc00a0d066ef9792d974a6e4ad263cc99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-21mb/starlabs/lite/glk: Correct indendation in devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I780e2765059ad7473fe5f33c50dd0d8a561151fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-21src/soc/intel/cmn/fast-spi: Add SSDT extension to fast SPI driverWerner Zeh
If the SPI controller is hidden from the OS (which is default on Apollo Lake) then OS has no chance to probe the device and therefore can not be aware of the resources this PCI device occupies. If the OS needs to move some resources for a reason it can happen that the new allocated window will be shadowed by the hidden PCI device resource and hence causing a conflict. As a result this MMIO window will be inaccessible from the OS which will cause issues in applications. For instance on Apollo Lake this causes flashrom to stop working. This patch adds a SSDT extension for the PCI device if it is hidden from the OS and reports the occupied resource via ACPI to the OS. For the cases where the device is hidden later at coreboot runtime and therefore is not marked as hidden in the PCI device itself a Kconfig switch called 'FAST_SPI_GENERATE_SSDT' is introduced. It defaults to 'no' and can be set from SOC code to override it. Since there is no defined ACPI ID for the fast SPI controller available now, the generic one (PNP0C02) is used. Test: Boot mc_apl4 and make sure flashrom works again. Change-Id: Ia16dfe6e001188aad26418afe0f04c53ecfd56f1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-21mb/google/nissa/var/craask: Disable pen garage and WFC based on fw_configTyler Wang
BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ib5770f02a6d524417be6723f7f70aa80d9452f62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-21mb/google/nissa/var/craask: Switch LTE-related GPIOs settings based on fw_configTyler Wang
If the LTE USB DB is connected, enable LTE-related settings. Otherwise, disable LTE-related settings. BUG=b:229938024, b:229048361, b:229040345 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I37719cee48370a04534067aa64a3aa77e453948a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20mb/google/brya/var/crota: Enable SaGvTerry Chen
Enable SaGv support for crota BUG=b:229600878 TEST=FW_NAME=crota emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ibc06ef19e9fbbc91ef650a4ac060ce2b7c5c25d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-20mb/google/dedede/beadrix: Update FW_CONFIG probe for daughter board LTETeddy Shih
To make sure daughter board LTE existing, we update probe to DB ports value of FW_CONFIG field, (https://partnerissuetracker.corp.google.com/issues/226910787#comment11) as well as, refer to Google Henry and Ivan comments (https://partnerissuetracker.corp.google.com/issues/226910787#comment14) BRANCH=dedede BUG=b:226910787 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I9ab4412b614ec665fbafc998756b805591982b65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-20mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for NereidV Sowmya
This patch configures external V1p05/Vnn/VnnSx rails for Nereid to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I1df4ea10798354f41fe9cce0f8c478930517207c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for NivviksV Sowmya
This patch configures external V1p05/Vnn/VnnSx rails for Nivviks to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: If8da0dfe3059087526f74042be3c8b7e4a7ece82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20mb/intel/adlrvp: Configure the external V1p05/Vnn/VnnSx railsV Sowmya
This patch configures external V1p05/Vnn/VnnSx rails for adlrvp-n to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I06298eb1aec07eae34420c5736e912c707fefbc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20mb/google/brya: Disable PCH USB2 phy power gating for primusCasper Chang
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for primus board. Please refer Intel doc#723158 for more information. BUG=b:221461379 TEST=Verify the build for primus board Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I4d7d52bdeafe8b1b55822b5c8d040c94ce1f3878 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-20mb/google/brya/acpi: Add support for NBCI _DSM subfunctionTim Wawrzynczak
The Nvidia GPU supports another function named NBCI (NoteBook Common Interface), which has some subfunctions which are required for the Nvidia kernel driver to consume. The specification for this function comes from the Nvidia GN20 Software Design Guide. BUG=b:214581763 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I19eb9417923d297a084d6f5329682e91cd506a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-20mb/google/brya/var/agah: Select INCLUDE_NVIDIA_GPU_ASLTim Wawrzynczak
The agah variant will include an Nvidia GN20 series GPU, therefore select the INCLUDE_NVIDIA_GPU_ASL Kconfig to include the respective ASL code into the DSDT. BUG=b:214581763 TEST=build patch train Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icc718d01506ccb4dd42841239e96926f4ddaa9c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-20mb/google/brya: Add PEG and initial Nvidia dGPU ASL supportTim Wawrzynczak
Some brya variants will use a GN20 series Nvidia GPU, which requires quite a bit of ACPI support code to be written for it. This patch lands a decent bit of the initial code for it on the brya platform, including: 1) PEG RTD3 methods 2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods) 3) NVOP _DSM method There will be more support to come later, this is all written to specifications from the Nvidia Software Design Guide for GN20. BUG=b:214581763 TEST=build patch train Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-20lib/Makefile.inc: Add cbfs header pointer on !BOOTBLOCK_IN_CBFSArthur Heymans
On some x86 targets it the bootblock is loaded via a different mechanism, like via the AMD PSP or Intel IFWI. Some payloads need that pointer so add it to cbfs. Note that on Intel APL this file is not used, which is why the bootblock still needs to contain the pointer in the ARCH_X86 part. It is not worth it to add logic to specifically deal with APL as this is a legacy feature anyway. For AMD non-car platform this fixes cbfs access in SeaBIOS. Change-Id: If46e80e3eed5cc3f59964ac58e507f927fc563c4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-20soc/intel/ehl: Use defines for Ethernet controller IDsMario Scheithauer
Use defines for a better reading of the code. Change-Id: I8e696240d649c0ea2341b8f04b62eebffebc1d57 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64519 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-20mb/siemens/mc_ehl2: Quick fix for PSE TSN phy interface typeLean Sheng Tan
Based on quick fix on this commit 7b0fe59be (soc/intel/ehl: Fix logical bug for PseTsnGbePhyInterfaceType), disable PSE TSN SGMII as the original intention is to set the PSE TSN phy interface as RGMII. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Id2e05b19f156621a945110791038bc0d19a0aad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-20soc/intel/ehl: Fix logical bug for PseTsnGbePhyInterfaceTypeLean Sheng Tan
By right if PseTsnGbeSgmiiEnable is disable, PseTsnGbePhyInterfaceType should use RGMII setting. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: If593a5534716a9e93f99cb155fb5e86e12b1df17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-20mb/google/skyrim: Expose SKU and board ID to Chrome OSAmanda Huang
Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to provide common routine for reading skudid and boardid from Chrome EC. BUG=b:229052726 TEST=emerge-skyrim coreboot chromeos-bootimage Check the corresponding directory gets mounted to /run/chromeos-config/v1 Change-Id: I6aff02d29d44e95cd9b9e9485593c81f0d4a4b0e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-20mb/google/brya/variants/crota: Configure audio codec IRQ typeTerry Chen
The audio codec used by crota has a level-sensitive interrupt, therefore configure the GPIO pad as level-sensitive. BUG=b:230418589 TEST=emerge-brya coreboot and verified pass Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I588c21e44b9bb17cd5a48bf5f22465ec328496e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-20mb/google/skyrim/var/skyrim: Add better descriptors for USB endpointsJon Murphy
Fix descriptors for USB ports to align with their function and placement with respect to the schematics. BUG=N/A TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If57bebf9bffd4616c437ec655b64cab3298ac08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-20vc/amd/fsp/sabrina: Update PSP header to set the SOC FW IDJon Murphy
Update the PSP header to set the SOC FW ID to 0x0149 for this platform BUG=b:217414563 TEST=Build and verify header is set correctly Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic604ec96560c2d4d89c48c4a27528c5cfe4ca7e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-20CBMEM: Change declarations for initialization hooksKyösti Mälkki
There are efforts to have bootflows that do not follow a traditional bootblock-romstage-postcar-ramstage model. As part of that CBMEM initialisation hooks will need to move from romstage to bootblock. The interface towards platforms and drivers will change to use one of CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called in the first stage with CBMEM available. Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-20soc/mediatek: Fill coreboot table with PCIe infoJianjun Wang
In order to pass PCIe base address to payloads, implement pcie_fill_lb() to fill coreboot table with PCIe info. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-19mb/google/brya/var/kinox: Remove stop pin declaration for LANDtrain Hsu
Remove the stop pin declaration for LAN. Confirmed with LAN vendor, 8111K do not need to implement stop pin. It caused S0ix fail. BUG=b:232327947 TEST=Build and suspend_stress_test -c 5 pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I9bdaa28cd879c1ea7de2de8afb25761df39bcfc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-19coreboot_tables: Add PCIe info to coreboot tableJianjun Wang
Add 'lb_fill_pcie' function to pass PCIe information from coreboot to libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the __weak function. ARM platform usually does not have common address for PCIe to access the configuration space of devices. Therefore, new API is added to pass the base address of PCIe controller for payloads to access PCIe devices. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2022-05-19arch/x86/car.ld: Add a Kconfig param to flag AGESA brokennessArthur Heymans
AGESA has a lot of code in the .data section (initialized data). However there is no such section in CAR stages as the code runs in XIP mode and CAR is too small to contain the data section. When the linker can not match code to a section it will just append it, which is why AGESA worked at all. Follow-up patches will attempt to fix AGESA and set Kconfig parameter to 'n'. After all AGESA sources have been fixed, this can be removed. Change-Id: I311ee17e3c0bd283692194fcee63af4449583d74 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-05-19mb/google/nissa: Rework LTE GPIO configurationReka Norman
Currently, the LTE pins are enabled in gpio.c, then disabled in fw_config.c if LTE is not present. However, since there's a short delay between mainboard_init() and fw_config_handle(), this means that when LTE is not present GPP_H19 (SOC_I2C_SUB_INT_ODL, used for the SAR sensor) will be floating for a short period of time. Rework the GPIO config so that the LTE pins are disabled in the baseboard, then enabled in fw_config.c for variants using LTE. However, this doesn't work for WWAN_EN and WWAN_RST_L since they need to be enabled in bootblock. So these are instead enabled in the variant gpio.c, then disabled in fw_config.c if LTE is not present. BUG=None TEST=LTE still works on nivviks Change-Id: I9d8cbdff5a0dc9bdee87ee0971bc170409d925a2 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-19mb/google/dedede/beadrix: Update PCIe and SATA pins for Realtek RTL8822CE ↵Teddy Shih
suspend To make sure Realtek RTL8822CE suspend stress test smoothly, we remove 1c.7 as wireless LAN (WLAN) connects the signal PCIE_4 and it will map to 1c.7. refer to Intel Simon comment (https://partnerissuetracker.corp.google.com/issues/230386474#comment12), as well as, remove redundant 17.0 and 1c.6 that both are described by baseboard/devicetree.cb BRANCH=dedede BUG=b:230386474 TEST=on beadrix, verified by Realtek RTL8822CE can run suspend stress test properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ib418eed57f07afaa6b397b42a057808eab142f7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-05-19soc/intel/common/block/smbus: Deduplicate some codeAngel Pons
Reuse existing SMBus code from southbridge/intel/common/smbus_ops.h. Change-Id: Iea4f6886bb49590f7f96abbfbe631ac9d4dda902 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64432 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-19drivers/intel/fsp2_0: Avoid hardcoding `log_level` for FSP debug handlerSubrata Banik
This patch fixes a potential corner case scenario where the value of CONFIG_DEFAULT_CONSOLE_LOGLEVEL is less than `BIOS_SPEW` hence, coreboot is unable to redirect FSP serial messages over UART. Rather than passing hard coded `BIOS_SPEW` for the FSP debug handler, this patch now calls get_log_level() function to pass the supported log level while printing FSP serial msg. BUG=b:225544587 TEST=Able to build and boot taeko. Also, able to see FSP debug log with CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8a18101f5c3004252205387bde28590c72e05b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64460 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-18mb/google/brya/var/crota: Add reset and enable delay time for rtd3-coldTerry Chen
This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. We checked power on sequence requires enable pin prior to reset pin delay of 50ms and add delay of 20ms to meet the sequence on various eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:231291431 TEST=USE="project_crota" emerge-brya coreboot chromeos-bootimage Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Id9bed46e801602f3f327753053ec6a1ceb0656e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-18soc/intel/elkhartlake: Skip FSP Notify APIsLean Sheng Tan
Follow this commit 95986169f (soc/intel/alderlake: Skip FSP Notify APIs) to skip FSP Notify APIs. Elkhart Lake SoC deselects Kconfigs as below: - USE_FSP_NOTIFY_PHASE_READY_TO_BOOT - USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE to skip FSP notify APIs (Ready to boot and End of Firmware) and make use of native coreboot driver to perform SoC recommended operations prior booting to payload/OS. When deselecting these Kconfigs, cse_final_ready_to_boot() and cse_final_end_of_firmware() in the common cse driver will be used instead as required operations to perform prior to booting to OS. Check out this CL for further info: commit 90e318bba (soc/intel/common/cse: Add `finalize` operation for CSE) Additionally, create a helper function `heci_finalize()` to keep HECI related operations separated for easy guarding again config. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I477c204233f83bc96fd5cd39346bff15ed942dc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-18soc/intel/ehl/tsn_gbe.c: Reduce `void *` castsAngel Pons
Remove two redundant `void *` casts in `clrsetbits32()` calls. In addition, preemptively retype the `io_mem_base` variable in order to avoid having to add casts in future commits. Change-Id: Iae9c8189a6f8cd29181c52c2241789c6d392d77b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-18soc/intel/alderlake: Add support enable external V1P05/Vnn railsV Sowmya
This patch adds the support to enable the external V1P05/Vnn rails in S0 state via devicetree. BUG=b:223102016 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I555e5607af15a5f5d83ef74321b1b71f17cca289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-18soc/intel/alderlake: Update the VccIn Aux Imon IccMaxV Sowmya
This patch updates the VccIn Aux Imon IccMax for ADL-N to SOC SKU specific value of 27A. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified that VccIn Aux Imon IccMax value is set to 27mA. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: If09cd1112fac9b30ff04c45aa5a6062c2513c715 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-18soc/intel/alderlake: Configure the SKU specific parameters for VR domainsV Sowmya
This patch configures the SKU specific power delivery parameters for the VR domains for ADL-N. +--------------+-------+-------+-------+-------+-----------+--------+ | SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 081 | IA | 4.7 | 4.7 | 53 | 22 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 22 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 081(7W) | IA | 5.0 | 5.0 | 37 | 14 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 14 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | + Pentium +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 12 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | + Celeron +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 26 | 12 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 021(6W) | IA | 5.0 | 5.0 | 27 | 10 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 23 | 10 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ Kit: 646929 - ADL N Platform Design Guide -> Power_Map_Rev1p0 BUG=b:223102016 TEST=Boot and verify the UPD values are configured properly for ADL-N SKU's. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I3d6ae20323d3e859f52228822d4cbad143921a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-18mb/google/nissa: Change EC wake interrupt to IRQEric Lai
EC wake event doesn't work. Nissa has a separate EC wake pin. SCI only is not handled by EC, so we need to set dual route to wake the system. BUG=b:229142661 TEST=EC wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ide1f4a2494bb0a64b11ab4c5135fc43d2a635f74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-18intel/common/block: Provide RAPL and min clock ratio switches in commonUwe Poeche
There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-18arch/x86: Make sure bootblock gets buildtestedArthur Heymans
Now that the bootblock isn't added to cbfs anymore, on some targets it's only conditionally build. One example would be Intel APL where it only gets build when stitched into an IFWI. This is always done when compiling for real targets but not by the CI builder. This adds a dummy target to make sure the bootblock always gets buildtested. Change-Id: I60601e01a2c370b5c21493b71d51f495bb42f41d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-17amd/agesa/heapmanager.c: Avoid pragma pack on the rest of the fileArthur Heymans
AGESA.h has a '#pragma pack' nested somewhere. The pack pragma packs all structs which is not what is expected in the structs inside the headers included below AGESA.h. Change-Id: Ia70f68ea0ece7c097a37517206d75b71d695561f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-17mainboard/**/devicetree.cb: Fix typoAngel Pons
repalcement ---> replacement Change-Id: I486170e89f75fa7c01c7322bb8db783fd4f61931 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64404 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17soc/intel/elkhartlake/chip.h: Drop unused membersAngel Pons
Remove devicetree options that aren't used anywhere in the code. Change-Id: I7eace61079e14423325332d277fdda4f986fd133 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64403 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17soc/intel/elkhartlake: Enable SMBus depending on dev stateAngel Pons
Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's state in the devicetree. This avoids having to manually make sure the SMBus PCI device and the `SmbusEnable` setting are in sync. Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17lib/Makefile.inc: Correct filename to master_header_pointer.cReka Norman
Builds are failing sporadically with: src/lib/master_header_pointer.c:5:10: fatal error: fmap_config.h: No such file or directory 5 | #include <fmap_config.h> | ^~~~~~~~~~~~~~~ Correct the filename in the Makefile from header_pointer.c to master_header_pointer.c so that there's a dependency from master_header_pointer.c to fmap_config.h. Change-Id: I41bcb2a21fdbc48f09d5b6be3e211ca56607d849 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64431 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17mb/google/brya/var/mithrax: update overridetree and KconfigJohn Su
1. Update override devicetree based on schematics. 2. Update Kconfig based on schematics. BUG=b:229191897 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ia28ae16f609fda6d90558e69b2d41139dbe533fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-17mb/google/brya/var/mithrax: Generate RAM ID and SPD fileJohn Su
Add the support RAM parts for mithrax. Here is the ram part number list: DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) K4UBE3D4AA-MGCR 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 2 (0010) MT53E1G32D2NP-046 WT:B 1 (0001) BUG=b:229191897 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I2d19721a44f0176365a81da30d2f49b68a14df7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-17mb/google/brya/var/mithrax: update gpio settingsJohn Su
Configure GPIOs according to schematics BUG=b:229191897 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I31a1e02b2fa3d2075efbf488cd611b6c5a88500f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-17soc/amd/block/psp/psp_gen2: move SPL fusing earlier to BS_PAYLOAD_LOADFelix Held
The psp_notify_boot_done call is done at the entry of BS_PAYLOAD_BOOT, so it's not guaranteed that the psp_set_spl_fuse call is done before the psp_notify_boot_done call. Moving the psp_set_spl_fuse call makes sure that it's done before the psp_notify_boot_done call. This also brings the psp_set_spl_fuse call in line with the enable_secure_boot call that sends the PSB fusing command to the PSP. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id76b462608c3d788cd90e73a64d18c8e8b89dbfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-17soc/intel/skylake: Hook up FSP hyper-threading setting to option APIFelix Singer
Hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the mainboard kontron/bsl6, since it is obsolete now. Change-Id: I1023d1b94acb63f30455c56b394b68059deaaa16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-17mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridgeMario Scheithauer
On this mainboard there are legacy PCI devices connected behind a PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This patch disables the unused PCI clock outputs on the XIO2001 bridge. Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17arch/x86/ebda.c: Move setting up ebda to a BS hookArthur Heymans
device.c should not hold arch specific code. Change-Id: I9dfdb905a83916c0e9d298e1c38da89f6bc5e038 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-17mb/google/brya/var/kinox: Set memory SMBus addresses to 0x52, 0x50Dtrain Hsu
Follow the Kinox_schematic_R01_20220418.pdf to set memory SMBus addresses to 0x52, 0x50. BUG=b:231398371 TEST=Build and boot to OS with either 1 or 2 DIMM slots populated. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I32bb4f62a6b8a485ac757a60f5d16adb69109e2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-17mb/google/nissa: add RO_GSCVD section to WP_ROKangheui Won
This area is used for storing AP RO verification information. BRANCH=none BUG=b:227801913 TEST=build and boot nivviks Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: If5c03aca56e659d61c31613b284a55d0eba0d843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16rules.h: Use more consistent namingArthur Heymans
Use 'ENV' consistently and drop the redundant 'STAGE' in the naming. Change-Id: I51f2a7e70eefad12aa214e92f23e5fd2edf46698 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16soc/amd/cezanne/fsp_m_params: fix modification of constantFred Reitberger
mcfg->usb_phy is a pointer to a struct usb_phy_config. The config is constant. Changing a constant is undefined behavior, so create a local static instance of usb_phy_config that can be modified safely. Change-Id: If9b76b869a5b0581f979432ce57cc40f1c253880 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-16soc/amd/cezanne/fsp_m_params: add defines for FSP USB struct versionFelix Held
Add and use defines instead of magic values in fsp_m_params.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0e33eb0af5310ab4610ea8951688464c4960260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64126 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16soc/amd/cezanne/fsp_m_params: don't hard-code USB PHY config table sizeFelix Held
Use sizeof instead of having a hard-coded struct length. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85dc2fce11d9a670b2037d8a6a694177cfaa2177 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16mb/siemens/mc_ehl2: Enable TSN GbE driverMario Scheithauer
This variant uses all three EHL Ethernet GbE-TSN Controller so enable the TSN GbE driver in order to set the needed MAC addresses. The required function to retrieve a valid MAC address was already implement in the common mainboard.c for mc_ehl. TEST: - Boot mc_ehl2 into Linux and check MAC addr via 'ip a' Change-Id: Ia052c44feb606f9e1d31d047f2acc67e3226a895 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16soc/intel/elkhartlake: Provide ability to update TSN GbE MAC addressesMario Scheithauer
This patch provides the functionality to change the TSN GbE MAC addresses. Prerequisite for this is a mainboard specific function that returns a matching MAC address. A test was performed with the next patch in the series, which enables the TSN GbE driver for mc_ehl2 mainboard. Change-Id: I2303a64cfd09fa02734ca9452d26591af2a76221 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16mb/siemens/mc_ehl2: Set PCH TSN link speed to 1 Gbps in devicetreeMario Scheithauer
TSN runs in SGMII mode on this mainboard. This requires setting the link speed to 1 Gbps. Change-Id: I9f1da971b4de5671d6d38be6dbc50edbbe20d157 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16mb/siemens/mc_ehl2: Adjust PSE TSN settings in devicetreeMario Scheithauer
This mainboard uses all three internal Ethernet GbE-TSN controllers. Two of them are initialized by the Programmable Services Engine (PSE). This patch enables the Serial Gigabit Media Independent Interface (SGMII) mode for GbE PSE0 and GbE PSE1. By setting PCH PSE DMA pins to host owned, the IO is under control of the IA processor cores through system software. TEST: - Boot mc_ehl2 into Linux and check inet addr via 'ip a' Change-Id: I74e660548b2c44d5dbdb6023d5a36cfdd7e96f43 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16soc/intel/elkhartlake: Implement TSN GbE driverMario Scheithauer
To be able to make EHL Ethernet GbE-TSN Controller configurable, a driver is required. Functionality comes in following patches. Change-Id: I7522914c56b74486bb088280d2686acf7027d1d3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16mb/google/brask/variants/moli: remove DB_OPT from overridetreeRaihow Shi
Both option-HDMI and option-DP use the same setting of vbt, and ABSENT is just physically remove option board from motherboard, so it just need one vbt, and it don't need the fw_config to decide which vbt will be return. BUG=b:231769131 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I1f8cdcbc05ed3bc689d29261e4fd4d700326dce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/brask/variants/moli: return the default VBTRaihow Shi
Both option-HDMI and option-DP use the same setting of vbt, and ABSENT is physically remove option board from motherboard, so set default vbt has option-DP setting and only return it. BUG=b:231769131 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I440143dabcf04c103f2a4420a7e4afb8ec12ec1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16drivers/wifi/generic: Add new device IDBora Guvendik
New device id 0x51f1 is added. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I695309d529a117bad68fc89a7f136e69cecb95d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-16src/driver/intel/mipi_camera: Update ACPI entry to provide silicon infoBora Guvendik
CPUID_RAPTORLAKE_P_J0 is ES. Add it to generate is_es = 1 in ACPI Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib8d57f7fb0b3d15bc4bcdeae47bfbdde17e13118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-16soc/intel: Add Raptor Lake device IDsBora Guvendik
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
2022-05-16superio/nuvoton/nct6687d: Add early support for NCT6687DMichał Żygowski
Based on the public datasheet of NCT6686 which should be similar to NCT6687D. TEST=Enable serial for debugging on MSI PRO Z690-A WIFI DDR4 and see coreboot console on the debug port Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0e8744b5958af196de3de63de31852029d81436e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16soc/intel/common: Implement IOC driverWonkyu Kim
Starting with Meteor Lake SoC, the PCR/DMI interface to program GPMR is replaced with IOC (I/O Cache), hence, this patch implements IOC driver to support that migration. Reference: 643504 MTL FAS section 7.5.2 TEST=Build and boot to OS for TGL RVP and MTL PSS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63198 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16acpi, arch/x86/smp/mpspec,soc/amd/common: Move MP_IRQ_ flags into acpi.hRaul E Rangel
The MP_IRQ flags can be used in the MP table and the ACPI MADT table. Move them into acpi.h to avoid pulling in the full mpspec.h which is only available on x86. BUG=b:218874489, b:160595155 TEST=Build Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f1091b7629a6446fa399720b0270556a926401a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63845 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16soc/intel/cmn/spi: Separate fast SPI device from generic SPI driverWerner Zeh
The fast SPI controller (usually handling the boot NOR flash) is a different controller type than the generic SPI controllers as it provides access to the boot flash and usually is not used for generic SPI slave connections. Though there is common code for the fast SPI controller it currently do not uses the PCI driver structure. This patch adds the PCI driver envelope to the fast SPI driver and moves Apollo Lake as the first platform to this driver. Change-Id: I31bf39ec1c622db887dec9ca8623a7f282402849 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16soc/amd/common/block/psp: Add platform secure boot supportRitul Guru
Add Platform Secure Boot (PSB) enablement via the PSP if it is not already enabled. Upon receiving psb command, PSP will program PSB fuses as long as BIOS signing key token is valid. Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is only available with NDA customers. Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>