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2013-03-30ASRock E350M1: PlatformGnbPcie.c: Do not return anything for void return typePaul Menzel
When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/PlatformGnbPcie.romstage.o CC mainboard/asrock/e350m1/agesawrapper.romstage.o CC mainboard/asrock/e350m1/buildOpts.romstage.o src/mainboard/asrock/e350m1/PlatformGnbPcie.c: In function 'OemCustomizeInitEarly': src/mainboard/asrock/e350m1/PlatformGnbPcie.c:131:5: warning: 'return' with a value, in function returning void [enabled by default] […] The function signature is (the return type might not be part of this though [1]), VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) so do not return anything. All other AMD Family 14 boards already have the correct code. For example following commit fixed this for AMD Persimmon. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 [1] http://cboard.cprogramming.com/cplusplus-programming/117286-what-exactly-function-signature.html Change-Id: Ie60246bd9bb8452efd096e6838d8610f6364a6aa Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2954 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-30armv7: change some unsigned ints to uint32_tDavid Hendricks
Use register-sized types in case the inline assembler doesn't do so automatically. Change-Id: I3202ba972ef2548323fe557f45dc4b0b1cf6c818 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2983 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-29armv7: remove loop from dcache_mmu_disable()David Hendricks
dcache_mmu_disable() no longer needs to have its own iterative loop to select each cache level of cache since dcache_clean_invalidate_all() does that now. Change-Id: I5ca273f98943981b943c1c1622f4574d7133fb50 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2967 Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-29snow: explicitly configure L2 cacheDavid Hendricks
This adds a call to explicitly configure L2 cache (though defaults should be set correctly). Change-Id: I120e29c986918c2904a0332e46fcf9f1c5380d85 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2950 Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-29exynos5250: Add function for configuring L2 cacheDavid Hendricks
This adds a new function to configure L2 cache for the exynos5250 and deprecates the old function. Change-Id: I9562f3301aa1e2911dae3856ab57bb6beec2e224 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2949 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-29AMD CIMx SB800: Update Kconfig help texts to new SATA mode defaultPaul Menzel
In the following commit commit ee5c111755ac4acc6dfb6e10a4e271211e149a39 Author: Paul Menzel <paulepanter@users.sourceforge.net> Date: Tue Mar 12 12:41:40 2013 +0100 AMD CIMx SB800: Enable AHCI mode for SATA controller by default Reviewed-on: http://review.coreboot.org/2661 I forgot to update the help texts to the new SATA mode default. Do so now. Additionally note that help texts for `choice` do not seem to be shown. Change-Id: I17f401633a2136efca2b21a621482e0724ff9f04 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2936 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29armv7: update sync barrier usage in dcache_op_set_way()David Hendricks
This moves the dsb() before the loop to sync any outstanding memory accesses, and adds an isb() after the loop to ensure all outstanding instructions are completed. Change-Id: I1a11b39f104ae780370cfd2db3badcf4e91dc017 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2929 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29wtm2: auto-select CACHE_ROMAaron Durbin
The WTM2 board has a fairly static configuration. As such it's been tested to properly handle CACHE_ROM given the number of MTRRs the boards' CPUs supports. Change-Id: Ic67cd1eebce580003dc6b6655cac2b2a92dd1b5f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2964 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29AMD Inagua: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errorsPaul Menzel
Now that the AMD Inagua builds without any warnigs, remove the config option `WARNINGS_ARE_ERRORS` set to no by default from the file `Kconfig` so warnings are treated as errors to prevent code from being added in the future introducing warnings. Change-Id: I0b58bd74b06dc54d180b16d6a207354b5fea0d0f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2953 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29AMD Inagua: broadcom.c: Add missing prototype for `broadcom_init()`Paul Menzel
Building the AMD Inagua board, the following warning is thrown. CC mainboard/amd/inagua/get_bus_conf.ramstage.o src/mainboard/amd/inagua/broadcom.c:319:6: warning: no previous prototype for 'broadcom_init' [-Wmissing-prototypes] This warning was introduced by commit 3926b4c5. commit 3926b4c520e74da9dc22e3d136a8a178483e0d25 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Fri Mar 1 19:41:41 2013 +0100 AMD Inagua: add GEC firmware, document Broadcom BCM57xx Selfboot Patch format Reviewed-on: http://review.coreboot.org/2831 Adding the prototype to `broadcom.c` and removing it from `mainboard.c` fixes the warning. Change-Id: I1da0c4e972e129047dd8230d573f1c43fd71eb20 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2952 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29google boards: auto-select CACHE_ROMAaron Durbin
Automatically select CACHE_ROM for all Google boards. Tested by generating a config for the link board. CACHE_ROM was selected and was unable to unselect it using 'make oldconfig'. Change-Id: I8e34207e3929a020bb0280657f95ba7a000ad024 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2963 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29x86: mtrr: optimize hole carving above 4GiBAaron Durbin
There is an optimization that can take place when hole carving in ranges above 4GiB. If the range is the last range then there is no need to carve UC holes out from the larger WB range. This optimization also has the same assumption of choosing WB as the default MTRR type: the OS needs to properly handle accessing realloacted MMIO resources with PAT so that the MTRR type can be overidden. Below are results using a combination of options. The board this was tested on has 10 variable MTRRs at its disposal. It has 4GiB of RAM. IO hole config #1: hole starts at 0xad800000 No CACHE_ROM and no WRCOMB resources (takes 4 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x0000000100000000 size 0x52800000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 4/6. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0 No CACHE_ROM and 1 WRCOMB resource (takes 6 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 6/7. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0 CACHE_ROM and no WRCOMB resources (takes 7 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000ff800000 size 0x52000000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 11/7. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6 MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6 MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 5 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 6 base 0x0000000100000000 mask 0x0000007f00000000 type 6 CACHE_ROM and 1 WRCOMB resource (takes 8 MTRRs): Previously this combination was impossible without the optimization. MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 12/8. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6 MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6 MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 5 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 6 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 7 base 0x0000000100000000 mask 0x0000007f00000000 type 6 IO hole config #1: hole starts at 0x80000000 No CACHE_ROM and no WRCOMB resources (takes 1 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x0000000100000000 size 0x80000000 type 0 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 1/2. MTRR: WB selected as default type. MTRR: 0 base 0x0000000080000000 mask 0x0000007f80000000 type 0 No CACHE_ROM and 1 WRCOMB resource (takes 3 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 4/3. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6 CACHE_ROM and no WRCOMB resources (takes 3 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000ff800000 size 0x7f800000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 9/3. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6 CACHE_ROM and 1 WRCOMB resource (takes 4 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 10/4. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 2 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 3 base 0x0000000100000000 mask 0x0000007f00000000 type 6 Change-Id: Ia3195af686c3f0603b21f713cfb2d9075eb02806 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2959 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29x86: mtrr: add hole punching supportAaron Durbin
Some ranges would use less variable MTRRs if an UC area can be carved off the top of larger WB range. Implement this approach by doing 3 passes over each region in the addres space: 1. UC default type. Cover non-UC and non-WB regions with respectie type. Punch UC hole at upper end of larger WB regions with WB type. 2. UC default type. Cover non-UC regions with respective type. 3. WB default type. Cover non-WB regions with respective type. The hole at upper end of a region uses the same min alignment of 64MiB. Below are results using a combination of options. The board this was tested on has 10 variable MTRRs at its disposal. It has 4GiB of RAM. IO hole config #1: hole starts at 0xad800000 No CACHE_ROM or WRCOMB resources (takes 4 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x0000000100000000 size 0x52800000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 4/9. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0 No CACHE_ROM. 1 WRCOMB resource (takes 6 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 6/10. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0 CACHE_ROM and no WRCOMB resources (taks 10 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000ff800000 size 0x52000000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 MTRR: default type WB/UC MTRR counts: 11/10. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6 MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6 MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 5 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 6 base 0x0000000100000000 mask 0x0000007fc0000000 type 6 MTRR: 7 base 0x0000000140000000 mask 0x0000007ff0000000 type 6 Taking a reserved OS MTRR. MTRR: 8 base 0x000000014f600000 mask 0x0000007fffe00000 type 0 Taking a reserved OS MTRR. MTRR: 9 base 0x000000014f800000 mask 0x0000007fff800000 type 0 A combination of CACHE_ROM and WRCOMB just won't work. IO hole config #2: hole starts at 0x80000000: No CACHE_ROM or WRCOMB resources (takes 1 MTRR): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x0000000100000000 size 0x80000000 type 0 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 1/5. MTRR: WB selected as default type. MTRR: 0 base 0x0000000080000000 mask 0x0000007f80000000 type 0 No CACHE_ROM. 1 WRCOMB resource (takes 4 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 4/6. MTRR: WB selected as default type. MTRR: 0 base 0x0000000080000000 mask 0x0000007fc0000000 type 0 MTRR: 1 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0 MTRR: 2 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 3 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0 CACHE_ROM and no WRCOMB resources (takes 6 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000ff800000 size 0x7f800000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 9/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 2 base 0x0000000100000000 mask 0x0000007f80000000 type 6 MTRR: 3 base 0x000000017ce00000 mask 0x0000007fffe00000 type 0 MTRR: 4 base 0x000000017d000000 mask 0x0000007fff000000 type 0 MTRR: 5 base 0x000000017e000000 mask 0x0000007ffe000000 type 0 CACHE_ROM and 1 WRCOMB resource (takes 7 MTRRs): MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0 0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: default type WB/UC MTRR counts: 10/7. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 2 base 0x00000000ff800000 mask 0x0000007fff800000 type 0 MTRR: 3 base 0x0000000100000000 mask 0x0000007f80000000 type 6 MTRR: 4 base 0x000000017ce00000 mask 0x0000007fffe00000 type 0 MTRR: 5 base 0x000000017d000000 mask 0x0000007fff000000 type 0 MTRR: 6 base 0x000000017e000000 mask 0x0000007ffe000000 type 0 Change-Id: Iceb9b64991accf558caae2e7b0205951e9bcde44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2925 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29memrange: add 2 new range_entry routinesAaron Durbin
Two convenience functions are added to operate on a range_entry: - range_entry_update_tag() - update the entry's tag - memranges_next_entry() - get the next entry after the one provide These functions will be used by a follow on patch to the MTRR code to allow hole punching in WB region when the default MTRR type is UC. Change-Id: I3c2be19c8ea1bbbdf7736c867e4a2aa82df2d611 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2924 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29chromeos: remove CACHE_ROM automatic selectionAaron Durbin
It's not appropriate for the chromeos Kconfig to automatically select CACHE_ROM. The reason is that enabling CACHE_ROM is dependent on the board and chipset atrributes. Change-Id: I47429f1cceefd40226c4b943215d627a3c869c7b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2921 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29x86: add rom cache variable MTRR index to tablesAaron Durbin
Downstream payloads may need to take advantage of caching the ROM for performance reasons. Add the ability to communicate the variable range MTRR index to use to perform the caching enablement. An example usage implementation would be to obtain the variable MTRR index that covers the ROM from the coreboot tables. Then one would disable caching and change the MTRR type from uncacheable to write-protect and enable caching. The opposite sequence is required to tearn down the caching. Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29sandybridge: add option to mark graphics memory write-combining.Aaron Durbin
The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Add an option to enable write-combining for the graphics memory. Change-Id: I7d37fd78906262aabef92c2b4f4cab0e3f7e4f6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29haswell: add option to mark graphics memory write-combining.Aaron Durbin
The graphics memory can be accessed in a faster manner by setting it to write-combing mode. Add an option to enable write-combining for the graphics memory. Change-Id: I797fcd9f0dfb074f9e45476773acbfe614eb4b0a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2893 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29x86: mtrr: add CONFIG_CACHE_ROM supportAaron Durbin
The CONFIG_CACHE_ROM support in the MTRR code allocates an MTRR specifically for setting up write-protect cachine of the ROM. It is assumed that CONFIG_ROM_SIZE is the size of the ROM and the whole area should be cached just under 4GiB. If enabled, the MTRR code will allocate but not enable rom caching. It is up to the callers of the MTRR code to explicitly enable (and disable afterwards) through the use of 2 new functions: - x86_mtrr_enable_rom_caching() - x86_mtrr_disable_rom_caching() Additionally, the CACHE_ROM option is exposed to the config menu so that it is not just selected by the chipset or board. The reasoning is that through a multitude of options CACHE_ROM may not be appropriate for enabling. Change-Id: I4483df850f442bdcef969ffeaf7608ed70b88085 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29mtrr: honor IORESOURCE_WRCOMBAaron Durbin
All resources that set the IORESOURCE_WRCOMB attribute which are also marked as IORESOURCE_PREFETCH will have a MTRR set up that is of the write-combining cacheable type. The only resources on x86 that can be set to write-combining are prefetchable ones. Change-Id: Iba7452cff3677e07d7e263b79982a49c93be9c54 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2892 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29lib: add memrange infrastructureAaron Durbin
The memrange infrastructure allows for keeping track of the machine's physical address space. Each memory_range entry in a memory_ranges structure can be tagged with an arbitrary value. It supports merging and deleting ranges as well as filling in holes in the address space with a particular tag. The memrange infrastructure will serve as a shared implementation for address tracking by the MTRR and coreboot mem table code. Change-Id: Id5bea9d2a419114fca55c59af0fdca063551110e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2888 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29stdlib: add ALIGN_UP and ALIGN_DOWN macrosAaron Durbin
There wasn't an equivalent to align down so add ALIGN_DOWN. For symmetry provide an ALIGN_UP macro as well. Change-Id: I7033109311eeb15c8c69c649878785378790feb9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2951 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29resources: introduce IORESOURCE_WRCOMBAaron Durbin
Certain MMIO resources can be set to a write-combining cacheable mode to increase performance. Typical resources that use this would be graphics memory. Change-Id: Icd96c720f86f7e2f19a6461bb23cb323124eb68e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2891 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29resources: remove IORESOURCE_[UMA_FB|IGNORE_MTRR]Aaron Durbin
The IORESOURCE_UMA_FB and IORESOURCE_IGNORE_MTRR attributes on a resource provided hints to the MTRR algorithm. The IORESOURCE_UMA_FB directed the MTRR algorithm to setup a uncacheable space for the resource. The IORESOURCE_IGNORE_MTRR directed the MTRR algorithm to ignore this resource as it was used reserving RAM space. Now that the optimizing MTRR algorithm is in place there isn't a need for these flags. All IORESOURCE_IGNORE_MTRR users are handled by the MTRR code merging resources of the same cacheable type. The users of the IORESOURCE_UMA_FB will find that the default MTRR type calculation means there isn't a need for this flag any more. Change-Id: I4f62192edd9a700cb80fa7569caf49538f9b83b7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29x86: add new mtrr implementationAaron Durbin
The old MTRR code had issues using too many variable MTRRs depending on the physical address space layout dictated by the device resources. This new implementation calculates the default MTRR type by comparing the number of variable MTRRs used for each type. This avoids the need for IORESOURE_UMA_FB because in many of those situations setting the default type to WB frees up the variable MTTRs to set that space to UC. Additionally, it removes the need for IORESOURCE_IGNORE_MTRR becuase the new mtrr uses the memrange library which does merging of resources. Lastly, the sandybridge gma has its speedup optimization removed for the graphics memory by writing a pre-determined MTRR index. That will be fixed in an upcoming patch once write-combining support is added to the resources. Slight differences from previous MTRR code: - The number of reserved OS MTRRs is not a hard limit. It's now advisory as PAT can be used by the OS to setup the regions to the caching policy desired. - The memory types are calculated once by the first CPU to run the code. After that all other CPUs use that value. - CONFIG_CACHE_ROM support was dropped. It will be added back in its own change. A pathological case that was previously fixed by changing vendor code to adjust the IO hole location looked like the following: MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6 0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6 As noted by the output below it's impossible to accomodate those ranges even with 10 variable MTRRS. However, because the code can select WB as the default MTRR type it can be done in 6 MTRRs: MTRR: default type WB/UC MTRR counts: 6/14. MTRR: WB selected as default type. MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0 MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0 MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0 Change-Id: Idfcc78d9afef9d44c769a676716aae3ff2bd79de Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2889 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29coreboot table: use memrange libraryAaron Durbin
Use the memrange library for keeping track of the address space region types. The memrange library is built to do just that for both the MTRR code and the coreboot memtable code. Change-Id: Iee2a7c37a3f4cf388db87ce40b580f274384ff3c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2917 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29armv7: set cache level explicitly for dcache/unified cache caseDavid Hendricks
This adds a missing CSSELR write in the case of a dcache or unified cache being invalidated by armv7_invalidate_caches(), ensuring that all levels of dcache/unified cache are invalidated as expected when the function is called. Change-Id: Ie90184bf8a8181afa3afe0786897455b30b7f022 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2947 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-03-29armv7: invalidate TLB after changing translation table entriesDavid Hendricks
This adds a call to tlb_invalidate_all() after configuring a range of memory. Change-Id: I558402e7e54b6bf9e0b013f153d9b84c0873a6cf Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2946 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-03-29armv7: iterate thru all levels when doing dcache opsDavid Hendricks
This makes dcache maintenance functions operate on all levels of cache instead of just the current one. Change-Id: I2708fc7ba6da6740dbdfd733d937e7c943012d62 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2945 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-03-29armv7: add functions for reading/writing L2CTLRDavid Hendricks
This adds simple accessor functions for reading/writing L2CTLR. Change-Id: I2768d00d5bb2c43e84741ccead81e529dac9254d Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2948 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29armv7: use stdint.h in cache and MMU filesDavid Hendricks
This makes it easier to copy + paste code into libpayload since libpayload since both coreboot and libpayload have stdint.h and it defines the types needed. Change-Id: Ifa55f04a9bdddd17bc1a2679321a6744c75f25a8 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2944 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29armv7: added paranoia for cache libraryDavid Hendricks
This adds some paranoia to cache manipulation routines: - "memory" is added to the clobber list for functions which clean and/or invalidate dcache or TLB entries. - Remove unneeded clobber list for read_sctlr() Change-Id: Iaa82ef78bfdad4119f097c3b6db8219f29f832bc Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2928 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-28armv7: clean+invalidate all cache levels when disabling MMUDavid Hendricks
This iterates thru all cache levels and cleans + invalidates all data and unified caches before disabling dcache and MMU. Change-Id: I8a671b4c90d7b88b8d0a95947bfa17f912cebaa2 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2930 Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-28armv7: cosmetic changes to dcache_op_mva()David Hendricks
This is just a cosmetic change to dcache_op_mva() to (hopefully) make it a easier to follow and more difficult to screw up. Change-Id: Ia348b2d58f2f2bf5c3cafabcfba06bc411937dba Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2927 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-28armv7: fix a bad variable assignmentDavid Hendricks
'<' was used when '<<' is needed. Oops! Change-Id: I8451f76888e86219df16b50739cd2c8db80dcb14 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2941 Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-28armv7: pass incremented value to dccimvacDavid Hendricks
This passes the correct value into dccimvac. Change-Id: I6098440ea48a9b6429380d5913fce6d36e3afb41 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2926 Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
2013-03-27exynos5250: assign RAM resources in cpu_init()David Hendricks
This moves the ram resource allocation into cpu_init() so that we no longer rely on declaring a domain in devicetree.cb (which is kind of weird for this platform). This does not cause any actual changes to the coreboot memory table, and paves the way for further updates to Snow's devicetree. Change-Id: I141277f59b5d48288f409257bf556a1cfa7a8463 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2923 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-26armv7: fixes for dcache_op_by_mva()David Hendricks
This fixes a couple issues with dcache_op_by_mva(): - Add missing data and instruction sync barriers. - Removes unneded -1 from loop terminating condition. Change-Id: I098388614397c1e53079c017d56b1cf3ef273676 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2913 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-26ARMv7: Drop ROMSTAGE_BASE from Makefile.incStefan Reinauer
It's not used (instead ARM puts it in Kconfig) Change-Id: Ia22a7ac756bec4cb6fee00a4d946a020ea6290aa Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2916 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-03-26Revert "coreboot table: use memrange library"Aaron Durbin
This reverts commit 56075eaefcd7ef51464206166b24a0a47a59147f Change-Id: I8a37ce1f5ce36e4a120941ec264140abc9447ff5 Reviewed-on: http://review.coreboot.org/2915 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-26x86: dynamic cbmem: fix acpi reservationsAaron Durbin
If a configuration was not using RELOCTABLE_RAMSTAGE, but it was using HAVE_ACPI_RESUME then the ACPI memory was not being marked as reserved to the OS. The reason is that memory is marked as reserved during write_coreboot_table(). These reservations were being added to cbmem after the call to write_coreboot_table(). In the non-dynamic cbmem case this sequence is fine because cbmem area is a fixed size and is already reserved. For the dynamic cbmem case that no longer holds by the nature of the dynamic cbmem. Change-Id: I9aa44205205bfef75a9e7d9f02cf5c93d7c457b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-26coreboot table: use memrange libraryAaron Durbin
Use the memrange library for keeping track of the address space region types. The memrange library is built to do just that for both the MTRR code and the coreboot memtable code. Change-Id: Ic667df444586c2b5b5f2ee531370bb790d683a42 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2896 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-26Revert "samsung/exynos5: add resource functions for the display port"David Hendricks
This reverts commit 9427ca151e44644238b1b52138894195a9f5175f Looks like we were a bit too anxious to see this one get in. The devicetree.cb change seems to have broken things. coreboot memory table: 0. 0000000050000000-000000005000ffff: RESERVED 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES 2. 0000014004000000-00000140044007ff: RESERVED Before this patch: coreboot memory table: 0. 0000000040000000-00000000bfefffff: RAM 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES Change-Id: I618e4f1976265d56cfd6a61d0c5736c55a0f3cec Reviewed-on: http://review.coreboot.org/2914 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-26ARMv7: Drop XIP relocation code for romstageStefan Reinauer
It was never used, because we pushed romstage_null into the CBFS instead of romstage_xip. It's not surprising this worked, but it was a crude hack. Get rid of all the intermediate objects that are not needed. This could probably be further simplified to use the default cbfs mechanism in our build system instead of having a specific rule for romstage, but that's for another day. Change-Id: I492ca2015ec81e13499fcd8dd331371f46a31c78 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2912 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-26samsung/exynos5: add resource functions for the display portRonald G. Minnich
This does NOT turn on the graphics. The device tree has been changed enough so that, at the very least, the correct functions are called at the correct time, with the correct paramaters. We decided to yank the I2C entries as they did not obvious function and might not even have been correct. Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. We realized that the display code should be part of the cpu -- that's how the hardware works! Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2615 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-26armv7: add new dcache and MMU setup functionsDavid Hendricks
This adds new MMU setup code. Most notably, this version uses cbmem_add() to determine the translation table base address, which in turn is necessary to ensure payloads which wipe memory can tell which regions to wipe out. TODOs: - Finish cleaning up references to old cache/MMU stuff - Add L2 setup (from exynos_cache.c) - Set up ranges dynamically rather than in ramstage's main(). Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2877 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-25AMD Inagua: add GEC firmware, document Broadcom BCM57xx Selfboot Patch formatJens Rottmann
The Broadcom BCM5785 GbE MAC integrated in the AMD Hudson-E1 requires a secret sauce firmware blob to work. As Broadcom wasn't willing to send us any documentation (or a firmware adapted to our Micrel PHY) I had to figure out everything by myself in many weeks of hard detective work. In the end we had to settle for a different solution, the modified firmware I devised for the Micrel KSZ9021 PHY on our early FrontRunner-AF prototypes is no longer needed for the production version. However the information contained here might be very useful for others who'd like to use a competing PHY instead of Broadcom's 50610, so it should not get lost. And of course the unmodified, but now in large parts documented Selfboot Patch is needed to get Ethernet on AMD Inagua. The code introduced here should make the Hudson's internal MAC usable without having to add the proprietary firmware blob. - At least in theory. Unfortunately we've been unable to actually test this patch on Inagua, therefore the broadcom_init() call in mainboard.c was left commented out. If you have the hardware and can confirm it works please enable it. The fun thing is: as Broadcom refused to do any business with us at all, or send us any documentation, we never had to sign an NDA with them. This leaves me free to publish everything I have found out. :-) Change-Id: I94868250591862b376049c76bd21cb7e85f82569 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2831 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-23dynamic cbmem: fix memconsole and timestampsAaron Durbin
There are assumptions that COLLECT_TIMESTAMPS and CONSOLE_CBMEM rely on EARLY_CBMEM_INIT. This isn't true in the face of DYNAMIC_CBMEM as it provides the same properties as EARLY_CBMEM_INIT. Therefore, allow one to select COLLECT_TIMESTAMPS and CONSOLE_CBMEM when DYNAMIC_CBMEM is selected. Lastly, don't hard code the cbmem implementation when COLLECT_TIMESTAMPS is selected. Change-Id: I053ebb385ad54a90a202da9d70b9d87ecc963656 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23resources: introduce reserved_ram_resource()Aaron Durbin
mmio_resource() was previously being used for reserving RAM from the OS by using IORESOURCE_IGNORE_MTRR atrribute. Instead, be more explicit for those uses with reserved_ram_resource(). bad_ram_resource() now calls reserved_ram_resource(). Those resources are marked as cacheable but reserved. The sandybridge and haswell code were relying on the implementation fo the MTRR algorithm's interaction for reserved regions. Instead be explicit about what ranges are MMIO reserved and what are RAM reserved. Change-Id: I1e47026970fb37c0305e4d49a12c98b0cdd1abe5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2886 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23x86: mark .textfirst as allocatable and executableAaron Durbin
When the linking of ramstage was changed to use an intermeidate object with all ramstage objects in it the .textfirst section was introduced to keep the entry point at 0. However, the section was not marked allocatable or executable. Nor was it marked as @progbits. That didn't cause an issue on its own since .textfirst was directly called out in the linker script. However, the rmodule infrastructure relies on all the relocation entries being included in the rmodule. Without the proper section attributes the .rel.textfirst section entries were not being included in the final ramstage rmodule. Change-Id: I54e7055a19bee6c86e269eba047d9a560702afde Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23relocatable ramstage: fix linkingAaron Durbin
The ramstage is now linked using an intermediate object that is created from the complete list of ramstage object files. The rmodule code was developed when ramstage was linked using an archive file. Because of the fact that the rmodule headers are not referenced from any other object the link could start by specifying the rmodule header object for ramstage. That, however, is not the case as all ramstage objects are included in the intermediate linked object. Therefore, the ramstage_module_header.ramstage.o object file needs to be removed from the object list for the ramstage rmodule. Change-Id: I6a79b6f8dd1dbfe40fdc7753297243c3c9b45fae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2884 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23vboot module: fix compilation issuesAaron Durbin
There were 3 things stopping the vboot module from being compiled: 1. The vboot_reference code removed in the firmware/arch/$(ARCH)/include directory. This caused romcc to fail because romcc fails if -I<dir> points to non-existent directory. 2. The rmodule API does not have the no-clearing-of-bss variant of the load function. 3. cbfs API changes. Change-Id: I1e1296c71c5831d56fc9acfaa578c84a948b4ced Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23x86: expose console_tx_flush in romstageAaron Durbin
The vboot module relied on being able to flush the console after it called vtxprintf() from its log wrapper function. Expose the console_tx_flush() function in romstage so the vboot module can ensure messages are flushed. Change-Id: I578053df4b88c2068bd9cc90eea5573069a0a4e8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2882 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23rmodule: align ld script with latest x86 ld scriptAaron Durbin
The x86 linker script added a .textfirst section. In order to properly link ramstage as a relocatable module the .textfirst section needs to be included. Also, the support for code coverage was added by including the constructor section and symbols. Coverage has not been tested as I suspect it might not work in a relocatable environment without some tweaking. However, the section and symbols are there if needed. Change-Id: Ie1f6d987d6eb657ed4aa3a8918b2449dafaf9463 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23cbfs: fix relocation ramstage compiler errorsAaron Durbin
There were some cbfs calls that did not get transitioned to the new cbfs API. Fix the callsites to conform to the actual cbfs, thus fixing the copilation errors. Change-Id: Ia9fe2c4efa32de50982e21bd01457ac218808bd3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22Unify setting i82801e LPCKyösti Mälkki
Make it more similar to i82801d LPC init. Change-Id: I7b32747ee8012c220c8628994d749999c144b716 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2545 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-22x86: unify amd and non-amd MTRR routinesAaron Durbin
The amd_mtrr.c file contains a copy of the fixed MTRR algorithm. However, the AMD code needs to handle the RdMem and WrMem attribute bits in the fixed MTRR MSRs. Instead of duplicating the code with the one slight change introduce a Kconfig option, X86_AMD_FIXED_MTRRS, which indicates that the RdMem and WrMem fields need to be handled for writeback fixed MTRR ranges. The order of how the AMD MTRR setup routine is maintained by providing a x86_setup_fixed_mtrrs_no_enable() function which does not enable the fixed MTRRs after setting them up. All Kconfig files which had a Makefile that included amd/mtrr in the subdirs-y now have a default X86_AMD_FIXED_MTRRS selection. There may be some overlap with the agesa and socket code, but I didn't know the best way to tease out the interdependency. Change-Id: I256d0210d1eb3004e2043b46374dcc0337432767 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2866 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-22Add support for ASUS F2A85-M boardRudolf Marek
The patch is based on Thatcher board. So far it boots Linux (3.2/3.7), internal network adapter works, AHCI works. External PCI/PCIe slots works too. Power management/ACPI seems to work. Internal VGA works with dumped ROM (VGA/DVI), but lacks GART. PCI pref devices are being relocated by Linux, reason unknown. This is a good start. USB and XHCI untested but visible. Change-Id: I1869aecb2634d548b00b3c9139517d6a0e0c9817 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/2038 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-22Fix compilation of Intel LynxPoint based boardsStefan Reinauer
The haswell patches that verified correctly were not yet submitted, but verified correctly. However they still used romcc_io.h which was dropped in another patch earlier today. With a lot of development happening in parallel, this is unfortunately nothing that the gerrit 2.6 Rebase If Necessary submit type could have fixed. Change-Id: Ifef9ae05b22c408e78d6cff37defd68e4ed91ed9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2876 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-22Asrock E350M1: Use SPD read code from F14 wrapperJens Rottmann
Changes: - Get rid of the E350M1 mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I08c2aebc62facc14f94400ee1ad188901ba73f19 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2875 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-03-22FrontRunner/Toucan-AF: Use SPD read code from F14 wrapperJens Rottmann
Changes: - Get rid of the LiPPERT FrontRunner-AF and Toucan-AF mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I4ee5e1bc34f4caee20615c48248d4f7605c09377 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2874 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-22Unify coreboot table generationStefan Reinauer
coreboot tables are, unlike general system tables, a platform independent concept. Hence, use the same code for coreboot table generation on all platforms. lib/coreboot_tables.c is based on the x86 version of the file, because some important fixes were missed on the ARMv7 version lately. Change-Id: Icc38baf609f10536a320d21ac64408bef44bb77d Signed-off-by: Stefan Reinauer <reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/2863 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2013-03-22wtm2: build-time dev and recovery settingsAaron Durbin
It's helpful to switch back and forth for developer and recovery settings while testing boards. The wtm2 board currently doesn't have gpios which dynamically seelect that. Might as well make it easy to change the value for each setting with one define. The original defaults are kept. Change-Id: I7b928c592fd20a1b847e4733f4cdef09d6ddad4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2861 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22vboot: pass correct coreboot include pathsAaron Durbin
The coreboot include were not being passed correctly when building vboot_reference. The paths being included were of the src/<dir> form. However, vboot_reference lives in src/../vboot_reference. That coupled with the recursive make call made vboot_reference not see coreboot's header files. Fix this by appending ../ to coreboot's default include paths. Change-Id: I73949c6f854ecfce77ac36bb995918d51f91445e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2860 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22haswell: Add microcode for ULT C0 stepping 0x40651Duncan Laurie
Change-Id: I53982d88f94255abdbb38ca18f9d891d4bc161b0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2858 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22coreboot: add vboot_handoff to coreboot tablesAaron Durbin
The vboot_handoff structure contians the VbInitParams as well as the shared vboot data. In order for the boot loader to find it, the structure address and size needs to be obtained from the coreboot tables. Change-Id: I6573d479009ccbf373a7325f861bebe8dc9f5cf8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2857 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22haswell: vboot path support in romstageAaron Durbin
Take the vboot path in romstage. This will complete the haswell support for vboot firmware selection. Built and booted. Noted firmware select worked on an image with RW firmware support. Also checked that recovery mode worked as well by choosing the RO path. Change-Id: Ie2b0a34e6c5c45e6f0d25f77a5fdbaef0324cb09 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2856 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22haswell boards: support added chromeos functionAaron Durbin
The get_write_protect_state() function was added to the chromeos API that needs to be supported by the boards. Implement this support. Built and booted. Noted firmware select worked on an image with RW firmware support. Also checked that recovery mode worked as well by choosing the RO path. Change-Id: Ifd213be25304163fc61d153feac4f5a875a40902 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2855 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22romstage: add support for vboot firmware selectionAaron Durbin
This patch implements support for vboot firmware selection. The vboot support is comprised of the following pieces: 1. vboot_loader.c - this file contains the entry point, vboot_verify_firmware(), for romstage to call in order to perform vboot selection. The loader sets up all the data for the wrapper to use. 2. vboot_wrapper.c - this file contains the implementation calling the vboot API. It calls VbInit() and VbSelectFirmware() with the data supplied by the loader. The vboot wrapper is compiled and linked as an rmodule and placed in cbfs as 'fallback/vboot'. It's loaded into memory and relocated just like the way ramstage would be. After being loaded the loader calls into wrapper. When the wrapper sees that a given piece of firmware has been selected it parses firmware component information for a predetermined number of components. Vboot result information is passed to downstream users by way of the vboot_handoff structure. This structure lives in cbmem and contains the shared data, selected firmware, VbInitParams, and parsed firwmare components. During ramstage there are only 2 changes: 1. Copy the shared vboot data from vboot_handoff to the chromeos acpi table. 2. If a firmware selection was made in romstage the boot loader component is used for the payload. Noteable Information: - no vboot path for S3. - assumes that all RW firmware contains a book keeping header for the components that comprise the signed firmware area. - As sanity check there is a limit to the number of firmware components contained in a signed firmware area. That's so that an errant value doesn't cause the size calculation to erroneously read memory it shouldn't. - RO normal path isn't supported. It's assumed that firmware will always load the verified RW on all boots but recovery. - If vboot requests memory to be cleared it is assumed that the boot loader will take care of that by looking at the out flags in VbInitParams. Built and booted. Noted firmware select worked on an image with RW firmware support. Also checked that recovery mode worked as well by choosing the RO path. Change-Id: I45de725c44ee5b766f866692a20881c42ee11fa8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22rmodule: add vboot rmodule typeAaron Durbin
For completeness add a vboot rmodule type since vboot will be built as an rmodule. Change-Id: I4b9b1e6f6077f811cafbb81effd4d082c91d4300 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2853 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22timestamp: add vboot check pointsAaron Durbin
It's desirable to measure the vboot firmware selection time. Therefore add vboot check points to the timestamp ids. Change-Id: Ib103a9e91652cf96abcacebf0f211300e03f71fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2852 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-22cbmem: add vboot cmbem idAaron Durbin
The vboot firmware selection from romstage will need to pass the resulting vboot data to other consumers. This will be done using a cbmem entry. Change-Id: I497caba53f9f3944513382f3929d21b04bf3ba9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2851 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22haswell: use dynamic cbmemAaron Durbin
Convert the existing haswell code to support reloctable ramstage to use dynamic cbmem. This patch always selects DYNAMIC_CBMEM as this option is a hard requirement for relocatable ramstage. Aside from converting a few new API calls, a cbmem_top() implementation is added which is defined to be at the begining of the TSEG region. Also, use the dynamic cbmem library for allocating a stack in ram for romstage after CAR is torn down. Utilizing dynamic cbmem does mean that the cmem field in the gnvs chromeos acpi table is now 0. Also, the memconsole driver in the kernel won't be able to find the memconsole because the cbmem structure changed. Change-Id: I7cf98d15b97ad82abacfb36ec37b004ce4605c38 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2850 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22coreboot: dynamic cbmem requirementAaron Durbin
Dynamic cbmem is now a requirement for relocatable ramstage. This patch replaces the reserve_* fields in the romstage_handoff structure by using the dynamic cbmem library. The haswell code is not moved over in this commit, but it should be safe because there is a hard requirement for DYNAMIC_CBMEM when using a reloctable ramstage. Change-Id: I59ab4552c3ae8c2c3982df458cd81a4a9b712cc2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21rmodule: correct ordering of bss clearingAaron Durbin
This patch fixes an issue for rmodules which are copied into memory at the final load/link location. If the bss section is cleared for that rmodule the relocation could not take place properly since the relocation information was wiped by act of clearing the bss. The reason is that the relocation information resides at the same address as the bss section. Correct this issue by performing the relocation before clearing the bss. Change-Id: I01a124a8201321a9eaf6144c743fa818c0f004b4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2822 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-03-21cbmem: dynamic cbmem supportAaron Durbin
This patch adds a parallel implementation of cbmem that supports dynamic sizing. The original implementation relied on reserving a fixed-size block of memory for adding cbmem entries. In order to allow for more flexibility for adding cbmem allocations the dynamic cbmem infrastructure was developed as an alternative to the fixed block approach. Also, the amount of memory to reserve for cbmem allocations does not need to be known prior to the first allocation. The dynamic cbmem code implements the same API as the existing cbmem code except for cbmem_init() and cbmem_reinit(). The add and find routines behave the same way. The dynamic cbmem infrastructure uses a top down allocator that starts allocating from a board/chipset defined function cbmem_top(). A root pointer lives just below cbmem_top(). In turn that pointer points to the root block which contains the entries for all the large alloctations. The corresponding block for each large allocation falls just below the previous entry. It should be noted that this implementation rounds all allocations up to a 4096 byte granularity. Though a packing allocator could be written for small allocations it was deemed OK to just fragment the memory as there shouldn't be that many small allocations. The result is less code with a tradeoff of some wasted memory. +----------------------+ <- cbmem_top() | +----| root pointer | | | +----------------------+ | | | |--------+ | +--->| root block |-----+ | | +----------------------+ | | | | | | | | | | | | | | alloc N |<----+ | | +----------------------+ | | | | | | | | | \|/ | alloc N + 1 |<-------+ v +----------------------+ In addition to preserving the previous cbmem API, the dynamic cbmem API allows for removing blocks from cbmem. This allows for the boot process to allocate memory that can be discarded after it's been used for performing more complex boot tasks in romstage. In order to plumb this support in there were some issues to work around regarding writing of coreboot tables. There were a few assumptions to how cbmem was layed out which dictated some ifdef guarding and other runtime checks so as not to incorrectly tag the e820 and coreboot memory tables. The example shown below is using dynamic cbmem infrastructure. The reserved memory for cbmem is less than 512KiB. coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000002ffff: RAM 2. 0000000000030000-000000000003ffff: RESERVED 3. 0000000000040000-000000000009ffff: RAM 4. 00000000000a0000-00000000000fffff: RESERVED 5. 0000000000100000-0000000000efffff: RAM 6. 0000000000f00000-0000000000ffffff: RESERVED 7. 0000000001000000-000000007bf80fff: RAM 8. 000000007bf81000-000000007bffffff: CONFIGURATION TABLES 9. 000000007c000000-000000007e9fffff: RESERVED 10. 00000000f0000000-00000000f3ffffff: RESERVED 11. 00000000fed10000-00000000fed19fff: RESERVED 12. 00000000fed84000-00000000fed84fff: RESERVED 13. 0000000100000000-00000001005fffff: RAM Wrote coreboot table at: 7bf81000, 0x39c bytes, checksum f5bf coreboot table: 948 bytes. CBMEM ROOT 0. 7bfff000 00001000 MRC DATA 1. 7bffe000 00001000 ROMSTAGE 2. 7bffd000 00001000 TIME STAMP 3. 7bffc000 00001000 ROMSTG STCK 4. 7bff7000 00005000 CONSOLE 5. 7bfe7000 00010000 VBOOT 6. 7bfe6000 00001000 RAMSTAGE 7. 7bf98000 0004e000 GDT 8. 7bf97000 00001000 ACPI 9. 7bf8b000 0000c000 ACPI GNVS 10. 7bf8a000 00001000 SMBIOS 11. 7bf89000 00001000 COREBOOT 12. 7bf81000 00008000 And the corresponding e820 entries: BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 BIOS-e820: [mem 0x0000000000001000-0x000000000002ffff] usable BIOS-e820: [mem 0x0000000000030000-0x000000000003ffff] reserved BIOS-e820: [mem 0x0000000000040000-0x000000000009ffff] usable BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x0000000000efffff] usable BIOS-e820: [mem 0x0000000000f00000-0x0000000000ffffff] reserved BIOS-e820: [mem 0x0000000001000000-0x000000007bf80fff] usable BIOS-e820: [mem 0x000000007bf81000-0x000000007bffffff] type 16 BIOS-e820: [mem 0x000000007c000000-0x000000007e9fffff] reserved BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved BIOS-e820: [mem 0x00000000fed10000-0x00000000fed19fff] reserved BIOS-e820: [mem 0x00000000fed84000-0x00000000fed84fff] reserved BIOS-e820: [mem 0x0000000100000000-0x00000001005fffff] usable Change-Id: Ie3bca52211800a8652a77ca684140cfc9b3b9a6b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2848 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21cbfs: Change false ERROR print to a WARNING.Shawn Nematbakhsh
Change "ERROR" to "WARNING" -- not finding the indicated file is usually not a fatal error. Change-Id: I0600964360ee27484c393125823e833f29aaa7e7 Signed-off-by: Shawn Nematbakhsh <shawnn@google.com> Reviewed-on: http://review.coreboot.org/2833 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21Intel: Update CPU microcode for 6fx CPUsStefan Reinauer
Using the CPU microcode update script and Intel's Linux* Processor Microcode Data File from 2013-02-22 Change-Id: I9bb60bdc46f69db85487ba923e62315f6e5352f9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2845 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21Intel: Update CPU microcode for 106cx CPUsStefan Reinauer
Using the CPU microcode update script and Intel's Linux* Processor Microcode Data File from 2013-02-22 Change-Id: Icaf0e39978daa9308cc2f0c4856d99fb6b7fdffa Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2844 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21Intel: Update CPU microcode scriptStefan Reinauer
for latest URL of their microcode tar ball Change-Id: I3da2bdac4b2ca7d3f48b20ed389f6a47275d24fe Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2842 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21Butterfly, Stout: Force SATA link speed to 3 GbpsShawn Nematbakhsh
Force link speed on these platforms to 3 Gbps to defeat buggy SATA drives. Change-Id: Ia38a7c486fb1f4469cd67ca5244bbf61f877d556 Signed-off-by: Shawn Nematbakhsh <shawnn@google.com> Reviewed-on: http://review.coreboot.org/2823 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21rmodule: add string functions to rmodules classAaron Durbin
The standard string functions memcmp(), memset(), and memcpy() are needed by most programs. The rmodules class provides a way to build objects for the rmodules class. Those programs most likely need the string functions. Therefore provide those standard functions to be used by any generic rmodule program. Change-Id: I2737633f03894d54229c7fa7250c818bf78ee4b7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2821 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Fix up handling for LynxPoint-LP chipsetsDuncan Laurie
This configures power management registers according to the 1.2.0 reference code drop. There are many inconsistencies with the documentation and I tried to note those with ?. This does not do the same for LynxPoint-H yet. Change-Id: I9b8f5c24a8b0931075a44398571c9b0d54cce6a6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2819 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Change sata.c to get rid of #ifDuncan Laurie
This uses the new helper function added earlier. Change-Id: Icdb5d5c51f70eeb7e39e11062276ceb3eb3d9473 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2818 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Fix ELOG logging of power management eventsDuncan Laurie
This is updated to handle LynxPoint-H and LynxPoint-LP and a new wake event is added for the power button. Boot, suspend/resume, reboot, etc on WTM2 and then check the event log to see if expected events have been added. Change-Id: I15cbc3901d81f4fd77cc04de37ff5fa048f9d3e8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2817 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21haswell/lynxpoint: Use new PCH/PM helper functionsDuncan Laurie
This makes use of the new functions from pmutil.c that take care of the differences between -H and -LP chipsets. It also adds support for the LynxPoint-LP GPE0 register block and the SMI/SCI routing differences. The FADT is updated to report the new 256 byte GPE0 block on wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address block so that part is zeroed to prevent IASL and the kernel from complaining about a mismatch. This was tested on WTM2. Unfortunately I am still unable to get an SCI delivered from the EC but I suspect that is due to a magic command needed to put the EC in ACPI mode. Instead I verified that all of the power management and GPIO registers were set to expected values. I also tested transitions into S3 and S5 from both the kernel and by pressing the power button at the developer mode screen and they all function as expected. Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2816 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Fix GPIO and PM base reservationsDuncan Laurie
The kernel ACPI was not happy with the Add inside a ResourceTemplate (or perhaps within the IO declaration) Instead make a buffer of IO reservations and turn _CRS into a method that updates the buffer depending on the chipset type. This adds an \ISLP() method that checks the chipset LPC device ID to see if it is -LP or -H. It also increases the PM base reservation to 256 bytes and moves both GPIO and PM base to above 0x1000 on -LP chipsets. Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2815 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: remove DEBUG_PERIODIC_SMISDuncan Laurie
This was put in for debugging and experimentation on i945 and has been copied around since. Drop it from lynxpoint. Change-Id: I0b53f4e1362cd3ce703625ef2b4988139c48b989 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2814 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Add power management helper functionsDuncan Laurie
There are subtle yet significant differences in some of the registers in the power management region between LynxPoint-H and LynxPoint-LP. In order to reduce code that is accessing these registers and would need special cases this adds a number of helper functions that can be used in both ramstage and SMM. This commit just adds the new functions, subsequent commits will start to use them. Change-Id: I411da75da519f5b3198a408078cbf3114e426992 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2813 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Add helper functions for reading PM and GPIO baseDuncan Laurie
These base addresses are used in several places and it is helpful to have one location that is reading it. Change-Id: Ibf589247f37771f06c18e3e58f92aaf3f0d11271 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2812 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Add function for checking for LP chipsetDuncan Laurie
Add a helper function pch_is_lp() that will return 1 if the current chipset is of the new "low power" variant used with Haswell ULT. Additionally these functions are added to SMM so it can be used there. Change-Id: I9acdea2c56076cd8d9627aba66cf0844c56a38fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2811 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Enable EC IO ports 0x62/0x66Duncan Laurie
In order to be able to talk to an EC via standard path. Change-Id: I3fe76882dec9a0596cbc1c844afa2ddb03ed771c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2810 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21haswell: Drop the device ID check in graphics init pathDuncan Laurie
Change-Id: I10c4264d317b5fac02a44f50ed10b457e1865e17 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2809 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: update MBP give up routineAaron Durbin
I'm not sure if I screwed this up originally or the Intel docs changed (I didn't bother to go back and check). According to ME BWG 1.1.0 the give up bit is in the host general status #2 register. Change-Id: Ieaaf524b93e9eb9806173121dda63d0133278c2d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2808 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21haswell: RESET_ON_INVALID_RAMSTAGE_CACHE optionAaron Durbin
The RESET_ON_INVALID_RAMSTAGE_CACHE option indicates what to do when the ramstage cache is found to be invalid on a S3 wake. If selected the system will perform a system reset on S3 wake when the ramstage cache is invalid. Otherwise it will signal to load the ramstage from cbfs. Change-Id: I8f21fcfc7f95fb3377ed2932868aa49a68904803 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2807 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21haswell: implement ramstage caching in SMM regionAaron Durbin
Cache the relocated ramstage into the SMM region. There is a reserved region within the final SMM region (TSEG). Use that space to cache the relocated ramstage program. That way, on S3 resume there is a copy that can be loaded quickly instead of accessing the flash. Caching the ramstage in the SMM space is also helpful in that it prevents the OS from tampering with the ramstage program. Change-Id: Ifa695ad1c350d5b504b14cc29d3e83c79b317a62 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2806 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21coreboot: add caching loaded ramstage interfaceAaron Durbin
Instead of hard coding the policy for how a relocated ramstage image is saved add an interface. The interface consists of two functions. cache_loaded_ramstage() and load_cached_ramstage() are the functions to cache and load the relocated ramstage, respectively. There are default implementations which cache and load the relocated ramstage just below where the ramstage runs. Change-Id: I4346e873d8543e7eee4c1cd484847d846f297bb0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2805 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21haswell: add multipurpose SMM memory regionAaron Durbin
The SMM region is available for multipurpose use before the SMM handler is relocated. Provide a configurable sized region in the TSEG for use before the SMM handler is relocated. This feature is implemented by making the reserved size a Kconfig option. Also make the IED region a Kconfig option as well. Lastly add some sanity checking on the Kconfig options. Change-Id: Idd7fccf925a8787146906ac766b7878845c75935 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2804 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21haswell: set TSEG as WB cacheable in romstageAaron Durbin
The TSEG region is accessible until the SMM handler is relocated to that region. Set the region as cacheable in romstage so that it can be used for other purposes with fast access. Change-Id: I92b83896e40bc26a54c2930e05c02492918e0874 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2803 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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