summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2023-09-14mb/google/dedede: Update dibbi ec.h settingsReka Norman
Update the dibbi ec.h so that it's correct for a chromebox. Remove everything related to: - Lid - Battery - Built-in keyboard - AC connect/disconnect - Mode changes BUG=b:294963793 TEST=Boot dibbi and check the APCI tables no longer contain lid and PS/2 keyboard devices. Change-Id: Idfa5adcec308d68555d292fddc1db43c9a64d649 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77863 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14mb/google/dedede: Use a separate ec.h for dibbi variantsReka Norman
Dibbi variants are chromeboxes, so they need different settings in ec.h. Add a new dibbi baseboard ec.h and use it for dibbi variants. For now it's identical to the dedede baseboard ec.h. It will be updated in the following CL. BUG=b:294963793 TEST=With the following CL, boot dibbi and check the APCI tables no longer contain lid and PS/2 keyboard devices. Change-Id: I4075041ab8f02026623d1a26a555bee5eb09e77b Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77782 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
2023-09-14acpi.c: Add XSDT on QEMUArthur Heymans
Since d8f2dce "acpi.c: Swap XSDT and RSDT for adding/finding tables" XSDT is primarily used to add new tables or to find the S3 resume vector. However with QEMU coreboot does not generate most ACPI tables but takes them from whatever QEMU provides. Qemu only creates an RSDT and lacks an XSDT. To keep the codebase simple with the assumption that XSDT is always present, create an XSDT based on the existing RSDT and update the address in RSDP. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ia9b7f090f55e436de98afad6f23597c3d426bb88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77385 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14chromeos/cse_board_reset.c: Clear EC AP_IDLE flagDerek Huang
When CSE jumps between RO and RW, it triggers global reset so the AP goes down to S5 and back to S0. For Chromebox, when AP goes down to S5 EC set AP_IDLE flag. This cause an issue to warm reset the Chromebox device when it is in recovery mode and powered by USB-C adapter. This patch allows AP to direct EC to clear AP_IDLE flag before trigger reset. BUG=b:296173534 BRANCH=firmware-dedede-136-6.B TEST=Chromebox DUT which is powered by USB-C adapter boots up after warm reset in recovery mode Change-Id: Ib0002c1b8313c6f25d2b8767c60639aed8a4f904 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77632 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
2023-09-14vc/google/chromeos: Move clear_ec_ap_idle() to common codeDerek Huang
Previously the clear_ec_ap_idle() is implemented in cr50_enable_update.c and be called in the file. Move it to common code so that it can be called in cse_board_reset.c TEST=emerge-brask coreboot Change-Id: I2dbe41b01e70f7259f75d967e6df694a3e0fac23 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-09-13mb/google/brya: Create dochi variantMorris Hsu
Create the dochi variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:299570339 BRANCH=firmware-brya-14505.B TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_DOCHI Change-Id: Iadeb97bd217278cdf777ae350100313b4345ecf3 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77756 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13mb/google/brya/var/craask: Add audio codec ALC5650Ren Kuo
Add audio codec ALC5650 related settings. BUG=b:289969623 TEST=emerge-nissa coreboot confirm the device in kernel log. Change-Id: I4b8a19e6248bd91cfc31feb84c6108413cd719e2 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77701 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13soc/intel/cmd/blk/cse: Shorten CBMEM field name for better alignmentDinesh Gehlot
This patch shortens the name of the CBMEM field CBMEM_ID_CSE_INFO from "CSE SPECIFIC INFORMATION" to "CSE SPECIFIC INFO" to improve the alignment of the text on the screen. The functionality of the field has not been changed. BUG=NA Test=Boot verified on rex board. Change-Id: I39c716dab7d02d49e7d552cff77d544a1c168433 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77743 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13acpi/soundwire.[ch]: Fix dpn entry array overrunMartin Roth
In soundwire.h, SOUNDWIRE_DPN MIN & MAX are set to 1 and 14. When creating the dpn array, the length was set to MAX - MIN or 13, numbered 0 to 12. When accessing the array, the code was bailing out if a value greater than MAX was trying to be accessed, so the array was able to be overrun by two structure lengths. Fix this problem by: 1) Not subtracting the MIN value when creating the array, which does waste a little space. If anyone wants to refactor the code to fix that, please feel free. 2) Breaking out of the loop when the port is equal to the MAX port number instead of just when it's greater than the max port number. Reported-by: Coverity (CID:1429766 & CID:1429771) Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0841bb8c9869fe9f53958f05614848785a98b766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-09-13mb/google/nissa/var/pujjo: Select VBT based on FW_CONFIG for pujjo1eLeo Chou
Select pujjo1e vbt bin files based on PANEL_IVO_BOE field of FW_CONFIG. BUG=b:299852789 TEST=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I344f97331e79e713af47ad743e27794e21be4ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-09-13mb/google/brya/var/pujjo: modify fw_config to separate pujjo1e wifi sar tableLeo Chou
Use fw_config for a dedicated pujjo1e intel wifi sar table. BUG=b:293360900 Test=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I635d3d23384cc4efd85b0c420817dd18a65d2872 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77648 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13soc/intel/{alderlake,meteorlake}: Remove the dummy PS0 and PS3 methodsSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8515407eb10e1a74f37ea5a80fa31533c38badec Reviewed-on: https://review.coreboot.org/c/coreboot/+/77455 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13soc/intel/{tigerlake,meteorlake}: Check ITBT FW versionSean Rhodes
The ensures that ITBT is ready to operate. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If60404a88208c632cd60e8aaa6ba70494eefbed2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77454 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-13soc/intel/{tigerlake,alderlake,meteorlake}: Start to unify the TCSS ACPISean Rhodes
The ACPI used for Tiger Lake, Alder Lake and Meteor Lake are very similar, so can be moved to shared code. This commit aligns minor difference between then, such as comments and tabs/spaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If6554c7ef9e83740d7ec5dcca6a9d7e32fb182db Reviewed-on: https://review.coreboot.org/c/coreboot/+/77453 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13mb/siemens/mc_ehl5: Enable PWM passthrough mode on PTN3460Mario Scheithauer
The connected panel on this mainboard gets the PWM frequency directly from the Elkhart Lake CPU. The PWM controls the brightness of the backlight. Therefore, it is necessary to activate the PWM passthrough mode in the PTN3460 eDP-to-LVDS bridge (see PTN3460 Programming Guide - 5. Configuration Registers). Link to PTN3460 Programming Guide: https://web.archive.org/web/20230908074244/https://www.nxp.com/docs/en/application-note/AN11128.pdf BUG=none TEST=Boot into Linux and change the brightness of the screen Change-Id: Iec9d8ae22fced40c45e5bfa8989ad655a722d7ef Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77702 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-12soc/amd/*/Makefile: drop wrong EFS diagramsFelix Held
The EFS data structure diagrams in the Makefiles of Picasso and newer SoCs were wrong, since the BIOS directory table pointer is in a different location than shown in the diagram. Since the diagram also wasn't that easy to understand and amdfwtool does all of that handling, drop the wrong diagram from the Makefiles. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5f86fea29f956ff10746d35dbe967a4a89e11cca Reviewed-on: https://review.coreboot.org/c/coreboot/+/77799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-09-12x86/tables: Upgrade error to criticalPatrick Rudolph
When more ACPI tables are written than space is available in CBMEM, the buffer overflow corrupts other CBMEM tables and a successful boot is unlikely. Upgrade the error message to critical and be more precise what to do. Change-Id: I152842945f552905729265f7d623cd581dd0a8d0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-09-12soc/intel/common: Fix invalid MADT entries creationJeremy Compostella
commit f8ac3dda02f22ebf857efb5b845db97f00598f7d ("soc/intel/common: Order the CPUs based on their APIC IDs") sort algorithnm walks all the `cpu_info' entries without discarding empty ones. Since `cpu_info' is not initialized, the data that is used is undefined and it generally results in the creation of invalid `Local x2APIC' entries in the MADT ("APIC") ACPI table. Depending on the X2APIC ID value the Linux kernel behavior changes (cf. arch/x86/kernel/acpi/boot.c::acpi_register_lapic()): 1. If (int)ID >= MAX_LOCAL_APIC (32768), the Linux kernel discards the entry with the "skipped apicid that is too big" INFO level message. 2. If (int)ID < MAX_LOCAL_APIC (32768) (including negative) this data is taken into account and it can lead to undesirable behavior such as core being disabled as (cf. "native_cpu_up: bad cpu" ERROR kernel message). TEST=Verified the MADT does not contain any invalid entries on rex. Change-Id: I19c7aa51f232bf48201bd6d28f108e9120a21f7e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77615 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2023-09-12drivers/mipi: sta_himax83102: Completely pull GPW to VGL before TP termRuihai Zhou
The sta_himax83102 panel sometimes shows abnormally flickering horizontal lines. The front gate output will precharge the X point of the next pole circuit before TP term starts, and wait until the end of the TP term to resume the CLK. For this reason, the X point must be maintained during the TP term. In abnormal case, we measured a slight leakage at point X. This is because during the TP term, the GPW does not fully pull the VGL low, causing the TFT to not be closed tightly. To fix this, we completely pull GPW to VGL before entering the TP term. This will ensure that the TFT is closed tightly and prevent the abnormal display. BUG=b:299249186 BRANCH=corsola TEST=FW Screen display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I5dddaaa38917a65990c1474b657db5eb551940b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77692 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-12arch/x86: Reduce max phys address size for Intel TME capable SoCsJeremy Compostella
On Intel SoCs, if TME is supported, TME key ID bits are reserved and should be subtracted from the maximum physical addresses available. BUG=288978352 TEST=Verified that DMAR ACPI table `Host Address Width` field on rex went from 45 to 41. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-12cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella
It makes the detection of this feature accessible without the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency. BUG=288978352 TEST=compilation Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11mb/packardbell: Remove space between function name and '('Elyes Haouas
Change-Id: Ied86fb05a3930f1bd900d106b5f3c79466a81a6d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-11soc/intel: Remove space between function name and '('Elyes Haouas
Change-Id: I1dbfca33c437c680118eb3a92e60b5607c93e565 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77768 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11mb/lenovo: Remove space between function name and '('Elyes Haouas
Change-Id: I9b1e3ad668c332bebdaf48a2e95f1f9e2131d598 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-11mb/google: Remove space between function name and '('Elyes Haouas
Change-Id: I0909f24844fab3dfc859ea8c5325344a9872799f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-11arch/arm64: Remove space between function name and '('Elyes Haouas
Change-Id: I0cba99070f251d86679c068bb737c05178f4a7c5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77771 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11soc/cavium: Remove space between function name and '('Elyes Haouas
Change-Id: I25e3cf15a77cf61a60bd31519eae019742842389 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-11sb/intel: Remove space between function name and '('Elyes Haouas
Change-Id: I2e8eb3632c93b4449f108cb690f9bfd8e1ea3776 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77767 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11nb/intel: Remove space between function name and '('Elyes Haouas
Change-Id: Ibffaf86f9e32d747c8f2f7a3643df8935fb00047 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-11soc/nvidia: Remove space between function name and '('Elyes Haouas
Change-Id: I5b0cdb7b8484080db6571d70ddef145bbaf2e87d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77769 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11drivers: Remove space between function name and '('Elyes Haouas
Change-Id: I42e995952a72a23a5f3aeadf428ad13f25546854 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-09security/intel/stm: Remove __attribute__(())Elyes Haouas
Change-Id: Id35a0a589128ea2dfb2f0e5873d4fa087b0886a9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-09soc/amd/common: Remove __attribute__(())Elyes Haouas
Change-Id: I2866dcdd6900c98310b4b3736b40ebe4eaa77ea2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77719 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-09drivers/net/ne2k: Remove space before semicolonElyes Haouas
Also move the semicolon on next line. Change-Id: I68412407ec8c8f99c15f39b0ec08d4fb33eb1b3f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08vendorcode/eltan/security: update attribute useJon Murphy
Update the use of __attribute__((weak)) to the preferred __weak BUG=None TEST=Builds BRANCH=None Change-Id: I75a0e7c03e537be2d38b7f9c6b81eafbb5fb8018 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08mb/purism/librem_cnl: Enable HDMI1 output for Mini native graphics initJonathon Hall
Enable HDMI1 output, which corresponds to the physical DisplayPort connector, so passive adapters to DVI or HDMI will work with native graphics init. Change-Id: I95a147978697f4af092fe61ceacd2e725155d489 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-09-08mb/google/rex: Fix ACPI MPTS method for non-5G board SKUsCliff Huang
MPTS method should only be generated for the board sku with 5G. BUG=NA TEST=Check kernel messages when going to S3. The following errors should not be seen: ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.RP06.RTD3._STA] ACPI Error: Aborting method \_SB.MPTS due to previous error (AE_NOT_FOUND) ACPI Error: Aborting method \_PTS due to previous error (AE_NOT_FOUND) Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I78f434c9049773cf5229d3a1f3934ae82d1fe46d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77690 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-08mb/starlabs/starbook/rpl: Enable the PD interrupt GPIOSean Rhodes
Enable the PD interrupt GPIO, GPP_B11, so that HPD works when Thunderbolt is disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie37976d58921b7a12dff16d93d7ac9bdd92edbea Reviewed-on: https://review.coreboot.org/c/coreboot/+/77673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08mb/starlabs/starbook/rpl: Correct GPP_A19Sean Rhodes
A19 was incorrectly labelled as TCP0 HPD. It is not connected so configure it accordingly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5aea723c2e8c0758d413bbc4bfd0ce92b22d0c87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08mb/starlabs/starbook/{adl,rpl}: Remove unnecessary entriesSean Rhodes
Certain devices are enabled in Alder Lakes chipset.cb, so remove them from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08mb/google/rex: Require VBOOT_LID_SWITCH for Chromebook designSubrata Banik
This patch ensures that platforms with lids, such as Chromebooks, only select the VBOOT_LID_SWITCH configuration option. Only samples the LID GPIO if VBOOT_LID_SWITCH config is enabled, otherwise fake LID is open to avoid shutdown after reaching depthcharge. Tested by building and booting Google/Rex with the VBOOT_LID_SWITCH configuration option enabled, and verifying that google/ovis does not required VBOOT_LID_SWITCH config. Change-Id: Ic5123b822a5a7021023319cb08a3f9e5225961ba Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77693 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-08vc/intel/fsp2/alderlake_n: Drop unused header filesFelix Singer
Change-Id: I870fa65ff05cf5907d62b3af1b2f9c4334b62603 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77260 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-08soc/intel/alderlake_n: Hook up the FSP repositoryFelix Singer
Change-Id: I57b54653bd29a728825210403c8f426eb1c9cc48 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-08arch to drivers/intel: Fix misspellings & capitalization issuesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07drivers/pc80/vga/vga_io: Remove unnecessary parenthesesElyes Haouas
Parentheses are not required. Change-Id: Iad1f766a3eb569af39030e43365e8a0a609f5944 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77706 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-07security/intel: Remove unnecessary blank line after '{'Elyes Haouas
Change-Id: I0d2a9c30d332b16efd548433a54f974067bd281e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-07drivers/siemens/nc_fpga/nc_fpga: Remove space before '++'Elyes Haouas
Change-Id: I6ff11df45ddc396391efd651f9938e04646dc0d3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77707 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-07ec/lenovo/h8/h8.c: Use sizeof()Elyes Haouas
Use 'sizeof(ecfw)' instead of 'sizeof ecfw'. sizeof operator should only be used for types and variables require sizeof(). Change-Id: Ifae1680917bb0ce610e6ba753741aae233a71103 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-07mb/google/myst: Set i2c2 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: I41fc7f847ef08138cb0f430bfd1a170f209163f1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77681 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07mb/google/zork: Set i2c3 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: I19f0a5a72ec409b306be7bc4bb53425870fc6298 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-07mb/google/skyrim: Set i2c3 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: Idb5d2cd6eca2a2746e89a371005332e9f621df83 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77675 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07mb/google/guybrush: Set i2c3 to hidden in devicetreeMatt DeVillier
Allows ACPI SSDT generator to hide the device from Windows via _STA Change-Id: I22b3ccc2c89a3f7ababd0eaf4e35604880aa0ce7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-07mb/google/nissa/var/craask: Modify SD_CARD element to prevent confuseTyler Wang
Modify SD_CARD element "SD_GL9750S" to "SD_PRESENT" to prevent confusion. Origin: 0 --> SD_GL9750S Modify: 0 --> SD_PRESENT BUG=b:296505165 TEST=emerge-nissa coreboot Change-Id: Ic355b7df9f9added4489a764f774851f2e4451c3 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-09-07soc/intel/meteorlake: Update LidStatus UPD dynamicallySubrata Banik
This patch ensures that the LidStatus UPD is passed a dynamic value, rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0 devices. Problem statement: * FSP-S GFX PEIM initializes the on-board display (eDP) even when the LID is physically closed, because LidStatus is always set to 1. * FSP-S skips external display initialization even when the LID is closed. Solution: * FSP-S GFX PEIM module understands the presence of an external display if LidStatus is not set, and tries to probe the other display endpoint. * Statically passing LidStatus as always enabled (aka 1) does not illustrate the exact device scenarios, so this patch updates LidStatus dynamically by reading the EC memory map offset. BUG=b:299137940 TEST=Able to build and boot google/rex to redirect the display using external HDMI monitor while LID is closed. Change-Id: I7d7b678227a6c8e32114de069af8455b8c1aa058 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-07mb/google/rex/var/karis: Update MIPI User facing camera settingsTyler Wang
Update overridetree and GPIO settings for MIPI UFC due to updated schematic updates. BUG=b:298133153 TEST=emerge-rex coreboot Change-Id: I4c3197e3f15e0cb3fc640b1749d8681299981563 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77591 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eran Mitrani <mitrani@google.com>
2023-09-07mb/google/brya/var/{kano,osiris,taeko}: Add null pointer checkWisley Chen
Without part no. in CBI, mainboard_get_dram_part_num returns null. To prevent passing this null pointer to strcmp and avoid unexpected behavior, proper handling is necessary. BUG=none TEST=emerge-brya coreboot Change-Id: I47e42376c6b1347c56afaec218aed63c5469f0aa Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77646 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07mb/google/brya/var/yavilla: Add VBT data fileRobert Chen
Add data.vbt file for yavilla recovery image. Select INTEL_GMA_HAVE_VBT for yavilla which currently have a VBT file. BUG=b:298320552 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I72f98181b3487f8ae9acf6e0f2382a0204f7989c Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-06device/pci_rom: rename pci_rom_acpi_fill_vfct()Matt DeVillier
Rename pci_rom_acpi_fill_vfct() to ati_rom_acpi_fill_vfct() to make it clear that the function is only used for AMD/ATI VGA option ROMs. Change-Id: I0e310dd2d7a0432918861632e09a23e162082ea5 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77634 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-06device/pci_rom: Set VBIOS checksum when filling VFCT tableMatt DeVillier
AMD's Windows display drivers validate the checksum of the VBIOS data in the VFCT table (which gets modified by the FSP GOP driver), so ensure it is set correctly after copying the VBIOS into the table if the FSP GOP driver was run. Without the correct checksum, the Windows GPU drivers will fail to load with a code 43 error in Device Manager. Thanks to coolstar for root causing the issue. TEST=build/boot Win11 on google/skyrim (frostflow), ensure GPU driver loaded and functional. Change-Id: I809f87865fd2a25fb106444574b619746aec068d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-09-06soc/amd: correctly report I2C controller state in ACPIFelix Held
Instead of reporting all I2C controllers in the system as enabled in the corresponding ACPI device's _STA method, report the I2C devices that are disabled in the devicetree as disabled in the corresponding _STA method too. This is done by returning the contents of the STAT variable inside each device's scope in the DSDT that have a default value of 0 (device not present/disabled). For all enabled and hidden I2C devices i2c_acpi_fill_ssdt gets called which then writes 0xf (device enabled and visible) or 0xb (device enabled, but hidden) to the STAT name inside the same scope, but in the SSDT. This object in the SSDT will then override the default in the DSDT resulting in the _STA method returning the correct status of each device. The code was inspired by commit 7cf9c7451808 ("soc/amd/*: Fix UART ACPI device status"). TEST=On Mandolin all I2C controllers are disabled and with this patch none shows up in the Windows 10 device manager. When enabling an I2C controller in the devicetree for testing, it shows up again in the Windows device manager. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4cd9f447ded3a7f0b092218410c89767ec517417 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-09-06soc/intel/common/block/acpi: Change __attribute__((weak)) to __weakElyes Haouas
Change-Id: I9ecd81ffaa48dbed225a23900704b259569cb7c8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77527 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-06google/puff: Enable ASPM of RTL8111HAlexis Savery
With kernel 5.15, puff hangs during power idle tests because the NIC does not enter ASPM L1.2. We add "enable_aspm_l1_2" in devicetree for RTL8111H to enable ASPM L1.2. BUG=b:268859220, b:279618219 TEST=emerge and run power.Idle Change-Id: I129dfd79e8112191453be513b2e3a260429b3030 Signed-off-by: Alexis Savery <asavery@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77570 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-06google/puff: remove workaround that toggled the #ISOLATE pinAlexis Savery
A workaround was added for puff to assert/deassert the #ISOLATE pin during suspend/resume to resolve the situation where the realtek ethernet device cannot enter L1.2 mode when its ASPM is disabled. The realtek driver has since been fixed and ASPM of realtek devices have been enabled on kernel 5.10 and 5.15 and this original workaround is now causing suspend/resume errors on kernel 5.15: r8169 0000:01:00.0: Unable to change power state from D3cold to D0, device inaccessible Puff devices were originally shipped with kernel 4.19, and applying this change to the firmware on a device running 4.19 causes suspend/resume failures, basically reversing the problem. We are upreving the puff kernel to 5.15 so we need this patch, but since it is incompatible with 4.19 we will have to take that into consideration when pushing new firmware and potentially will need to backport the necessary fixes to 4.19. BUG=b:268859220 TEST=suspend_stress_test -c 500 on wyvern Change-Id: I5eead2d70cd9528b3ca3fadd11f98c0330601324 Signed-off-by: Alexis Savery <asavery@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77378 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2023-09-06mb/google/nissa/yaviks: Disable V1P05 control pinWisley Chen
Yaviks already disabled external V1P05, so disable V1P05 control pin which controls the VCC_V1P105_EXT_1P05. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I4128cfcfa5be0d141f0173e87518407331d79e8e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77645 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-05soc/amd/common/vboot: Drop reporting of Silicon levelMatt DeVillier
Per the PSP team, this field in the transfer buffer isn't used anymore and always set to zero, causing devices to incorrectly report having pre-production silicon. Change-Id: Ida4bf4b9328ac83d905e4c3f822e6ceabe9be79d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77630 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-09-05mb/google/nissa/var/yavilla: Disable SUSCLK based on fw_configShon Wang
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage. SAR_ID_0 : Yaviks_Gfp2 SAR_ID_1 : Yaviks & Yavilla_MT7921 SAR_ID_2 : Yahiko_Gfp2 SAR_ID_3 : Yavilla_MT7922 BUG=b:298138654 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I2f191683d0623aa5dce815998a24fddce2a36b2c Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77559 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-05amdfwtool: Add FW type FUSE_CHAIN in the config fileZheng Bao
We don't have file for the fuse chain, but we need to set the level for some cases. Change-Id: Idb546f761ae10b0d19a9879a9a644b788828d523 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-09-05mb/siemens/fa_ehl: Process LPDDR4 SPD files and add MT53E512M32D1NP SPDJohannes Hahn
The board uses soldered down LPDDR4, so process their SPD files, and add the SPD for Micron MT53E512M32D1NP-046WTB provided by Micron. Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Change-Id: I978b7450b106b86eef322df8b33df41e038599eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/77349 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-09-05mb/google/nissa/var/yaviks: Disable AUX pins based on FW_CONFIGWisley Chen
Configure the AUX pins as NC based on the FW_CONFIG setting when the C1 port is not present. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I24fb8f16c2e3b05edf1056b5687ae5ea28c022c0 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-05mb/google/nissa/var/yavilla: Restore WLAN_PERST_L power sequenceTony Huang
Restore TPERST_HIGH to 160ms since it has beed validated in other OEM projects and haven't heard any issue so far. This change back commit d710c6d5a773 ("mb/google/nissa/var/yavilla: Adjust WLAN_PERST_L power sequence"). BUG=b:295277868 TEST=emerge coreboot boot to system and check wifi connection is fine Change-Id: Ifc66e596fc7b6efdc0c286ee187969c8774bdc80 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-05mb/google/nissa/var/pirrha: Use GpioInt instead of GPE for digitizer penSeunghwan Kim
Currently pirrha's digitizer pen uses GPP_F12 for I2C HID interrupt signal. But its IRQ number is the same as GPD2, which is used as EC_SYNC_IRQ. It caused EC driver loading error from dmesg: cros_ec_lpcs GOOG0004:00: Failed to request IRQ 98: -16 cros_ec_lpcs GOOG0004:00: couldn't register ec_dev (-16) cros_ec_lpcs: probe of GOOG0004:00 failed with error -16 So change the digitizer pen interrupt type to GpioInt to prevent the conflict. BUG=b:292134655 TEST=Verified EC driver reported no error and pen device worked Change-Id: Ieb88e87fcfb06544a4b5b5133b752aa821fab76a Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77346 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-05mb/google/nissa/var/pirrha: Update device configurationsSeunghwan Kim
Based on schematics and gpio table of pirrha, generate overridetree.cb to configure internal devices and generate fw_config.c to override GPIO configurations following FW_CONFIG. BUG=b:292134655 TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage Change-Id: I91013b0ad89e26f0a4c433c305c6b883d000f042 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77116 Reviewed-by: Jamie Chen <jamie.chen@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jimmy Su <jimmy.su@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-09-05mb/amd/onyx: Add FMD file and update romsizeArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Idd6f711f5ca5c8a421c0c38edd404b1900bb29b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76497 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-05drivers/wifi: Add PCI ID for Misty Peak WLAN moduleSubrata Banik
This patch adds support for Intel WIFI-7 series PCIe based WLAN module. Change-Id: Ia31fdb87e15b50471dc7664e42b1e2625ce1ac58 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-05drivers/wifi: Avoid camel casing in macro definitionSubrata Banik
Convert camel case macros to uppercase and underscore separated macros, such as: PCI_DID_CyP_6SERIES_WIFI -> PCI_DID_CP_6SERIES_WIFI PCI_DID_TyP_6SERIES_WIFI -> PCI_DID_TP_6SERIES_WIFI This makes the macros more consistent with the rest of the code and easier to read. Change-Id: I9c739aab93dc0d043a3c9d9ce799087952c1e20b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77644 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-05drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIsSubrata Banik
This patch refactors the existing MRC cache storing logic, which was spread between the ROM and RAM stages, into a single early MRC cache store stage. The only exception is when SoC user selects FSP_NVS_DATA_POST_SILICON_INIT to store MRC cache from ramstage (after FSP-S). It reverts all the boot-state logic previously used to locate and store MRC cache from NVS HOB into NVS because majority of the platform can potentially use the early MRC cache store with improved memory caching at the pre-RAM phase (with the ramtop implementation). The only exception is the Xeon SP platform, which currently locates the MRC cache post in FSP-S (at ramstage). Therefore, this patch provides an API to the FSP 2.x silicon init code to perform late storing of the MRC cache. In majority cases the updated logic, the romstage (post FSP-M) will attempt to save the MRC cache. Platform that selects FSP_NVS_DATA_POST_SILICON_INIT config performs the same operation post FSP-S. Depending on whether the MRC_STASH_TO_CBMEM config is enabled, the MRC cache will either be written directly to NVRAM at the romstage or stashed into CBMEM for a late NVRAM write at ramstage. Below table captures the change in the boot state w/ and w/o this patch for storing the MRC cache. Overall the goal is to ensure the platform behavior is remain unchanged before and after this patch. w/o this patch: | | Save MRC | Finalize | Lock the | | | Cache | MRC Cache | Boot Medium | +-----------+----------------+----------------+----------------+ | MRC_WRITE | BS_OS_RESUME | BS_OS_RESUME | BS_ON_RESUME | | NV_LATE | CHECK_ENTRY | CHECK_ENTRY | CHECK_EXIT | +-----------+----------------+----------------+----------------+ | MRC_STASH | BS_DEV | BS_DEV | BS_DEV | | TO_CBMEM | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| +-----------+----------------+----------------+----------------+ | FSP_NVS | BS_DEV_INIT | BS_DEV | BS_DEV | | DATA_POST | CHIPS_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| | SILICON | | | | | INIT | | | | +-----------+----------------+----------------+----------------+ | Platform | BS_PRE | BS_DEV | BS_DEV | | w/o above | DEVICE_ENTRY | ENUMERATE_EXIT | ENUMERATE_ENTRY| | config | | | | | (FSP 2.0 | | | | | platforms | | | | w/ this patch: | | Save MRC | Finalize | Lock the | | | Cache | MRC Cache | Boot Medium | +-----------+----------------+----------------+----------------+ | MRC_WRITE | BS_OS_RESUME | BS_OS_RESUME | BS_ON_RESUME | | NV_LATE | CHECK_ENTRY | CHECK_ENTRY | CHECK_EXIT | +-----------+----------------+----------------+----------------+ | MRC_STASH | BS_DEV | BS_DEV | BS_DEV | | TO_CBMEM | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| +-----------+----------------+----------------+----------------+ | FSP_NVS | Post FSP-S | BS_DEV | BS_DEV | | DATA_POST | (ramstage) | ENUMERATE_EXIT | RESOURCES_ENTRY| | SILICON | | | | | INIT | | | | +-----------+----------------+----------------+----------------+ | Platform | Post FSP-M | BS_DEV | BS_DEV | | w/o above | (romstage) | ENUMERATE_EXIT | ENUMERATE_ENTRY| | config | | | | | (FSP 2.0 | | | | | platforms | | | | BUG=b:296704537 TEST=Able to build and boot google/rex without any boot time impact. Change-Id: Id1e91d25916594f59d1e467a142f5042c6138b51 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77556 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-09-04soc/amd/common: Use CBFSTOOL_ADD_CMD_OPTIONS when adding psp imageArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I639fb1e911a7449d0db0d2bfcfbb6f4f225b0cef Reviewed-on: https://review.coreboot.org/c/coreboot/+/76496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-04soc/amd/mendocino: Specify and use FSP binaries for platformMatt DeVillier
Specify the default path to, and automatically include the FSP binaries needed to boot a board if USE_AMD_BLOBS is selected. Simplifies board configs, and matches use in previous patforms. TEST=build/boot google/skyrim Change-Id: Ic837d264327723c8dc18a60fb16e8d41fe38b44e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77625 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-04soc/amd/cezanne: select ADD_FSP_BINARIES if USE_AMD_BLOBSMatt DeVillier
Automatically include the FSP binaries needed to boot a board if USE_AMD_BLOBS is selected. Simplifies board configs, and matches use in soc/amd/picasso. TEST=build/boot google/guybrush Change-Id: I5b6e34085410a2aafe5d7876be5097f28f521ce8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77624 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-04{drivers/intel/fsp2_0, soc/intel}: Rename `SAVE_MRC_AFTER_FSPS` configSubrata Banik
This patch renames `SAVE_MRC_AFTER_FSPS` config to `FSP_NVS_DATA_POST_SILICON_INIT` to highlight the violation in the Xeon SP FSP implementation, where the FSP Silicon Init API produces Non-Volatile Storage (NVS) instead of the FSP-Memory Init API. According to the FSP 2.x specification (section 11.3), the FSP populates the NVS data using the FSP_NON_VOLATILE_STORAGE_HOB and expects the boot firmware to parse the FSP_NON_VOLATILE_STORAGE_HOB after the FspMemoryInit() API in API mode. However, not all Intel SoC platforms that support the FSP 2.x specification adhere to this requirement. For example, the FSP binary for XEON SP platform produces NVS data (aka FSP_NON_VOLATILE_STORAGE_HOB) after the FspSiliconInit() API. Therefore, attempting to locate NVS data after the FspMemoryInit() API on these platforms would result in an error. The `save_mrc_data.c` implementation provides the required hooks to locate the NVS post FSP-Silicon Init and store into Non-Volatile Storage. BUG=b:296704537 TEST=Able to build and boot Intel Xeon SP w/o any functional impact. Change-Id: I815a64263fa1415bfe30bb3c1c35e4adee307e86 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-04mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hangWentao Qin
Setting SaGvWpMask to SAGV_POINTS_0_1_2 in dev tree can effectively avoid the idle hang issue, but it will affect the system power. (Before root cause, this is a short term workaround to unblock function test.) BUG=b:287170545 TEST=Able to idle for more than 5+ hours without any hang. Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Change-Id: I0947815ab79b470d2ae922cffdd8250c60cf1afd Reviewed-on: https://review.coreboot.org/c/coreboot/+/77520 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2023-09-02mb/google/rex/var/karis: Drop unused audio codecs and amplifiersTyler Wang
BUG=b:294155897, b:295112765 TEST=emerge-rex coreboot Change-Id: Ic7e272a484ea76dfc3a314b3597cbc18c856a9ca Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-02mb/google/rex/var/karis: Add audio codec ALC5650Tyler Wang
Add audio codec ALC5650 related settings. BUG=b:294155897, b:295112765 TEST=emerge-rex coreboot Change-Id: I2b54dd600b47ecdfd1f488a8c623bc0599c8936f Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77360 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-02mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control RegisterMario Scheithauer
With the introduction of a new Linux version a problem has appeared after a software initiated reset via CF9h register. The problem manifests itself in the fact that the Linux kernel does not start after the reboot. The problem is solved by setting bit 3 to 1 in Reset Control Register (I/O port CF9h). This leads to the fact that the PCH will drive SLP_S3 active low in the reset sequence. It leads to the same behavior as in commit 04ea73ee78bc ("siemens/mc_apl3: Set Full Reset Bit into Reset Control Register") explained. Change-Id: Ibc6d538c939e38732f42995d5ec6c8b61f979a6a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77603 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-02mb/google/rex/var/screebo: add hook for WiFi SAR tableYH Lin
As a preparation for WiFi SAR table addition, adding hook for it. BUG=b:291155207 TEST=emerge-rex coreboot Change-Id: Ia313cfddec278e6bf8498407b242c027a5891deb Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77598 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-02mb/google/rex/var/screebo: add FP_MCU fw_configYH Lin
Add FP_MCU definitions for fw_config according to the current build matrix. BUG=b:291155207 TEST=emerge-rex coreboot Change-Id: Id67b20a750d14eb23c62be9a30a5ef21d80e486a Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-02mb/google/rex/var/screebo: remove SD_ABSENTYH Lin
Remove SD_ABSENT since it's not being used, and CBI FW_CONFIG in current build does not reflect this config neither. BUG=b:291155207 TEST=emerge-rex coreboot Change-Id: Icfa472ff5570ac728038ec67a762289407760812 Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77596 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-02mb/google/nissa/var/uldren: Enable Weida touchscreenDtrain Hsu
Support Weida WDT8790A touchscreen. BUG=b:297453122 BRANCH=firmware-brya-14505.B TEST=touchscreen is workable and evtest shows WDHT2601 $evtest No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event10: sof-cs42l42 HDMI/DP,pcm=2 /dev/input/event11: sof-cs42l42 HDMI/DP,pcm=3 /dev/input/event12: sof-cs42l42 HDMI/DP,pcm=4 /dev/input/event13: sof-cs42l42 HDMI/DP,pcm=5 /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: Elan Touchpad /dev/input/event5: WDHT2601:00 2575:0921 /dev/input/event6: WDHT2601:00 2575:0921 Stylus /dev/input/event7: WDHT2601:00 2575:0921 Stylus /dev/input/event8: DELL Dell USB Entry Keyboard /dev/input/event9: sof-cs42l42 Headset Jack Change-Id: If9539afaf891c8352bc7fc8e548fd77ea57ea6ca Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77575 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-02mb/google/rex/var/karis: Enable ELAN touchscreenTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I179df1e0e544783f77a485ad08293530e8a86ecd Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77592 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-02mb/google/nissa/var/yaviks: Add wifi sar for yahikoWisley Chen
Add intel wifi sar table for yahiko BUG=b:298280621 BRANCH=firmware-nissa-15217.B TEST=build, enable iwlwifi debug option, and check dmesg Change-Id: I38d2e640fc2f7cbde3986474ca1bf7de9b2d25b4 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77585 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-02mb/google/brya/var/skolas: add nau8318 speaker supportMac Chiang
Add variant of NAU8318(SPK) + NAU88L25B(Headphone) audio support on brya and skolas board. In fw_config settings, reuse max98360_enable_pads[] due to identical i2s configurations as nau8318. In addition, separated GPP_R7 as SPK_BEEP_EN pin. BUG=b:236561637 TEST=emerge-brya coreboot BRANCH=none Signed-off-by: Mac Chiang <mac.chiang@intel.com> Suggested-by: David Lin <CTLIN0@nuvoton.com> Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Change-Id: Ife47a83fca902cf63e09d11206e9d99fac0dc9a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-02soc/intel/meteorlake: Fix black screen after booting to OSSubrata Banik
This patch ensures that the VR configuration for IA, SA, and GFX is properly initialized, assigning zero values to VR causes a black screen (no display) issue. Problem Statement: Override CEP (Current Excursion Protection) value with zero aka set to disable results into black screen issue (no display). Solution: Keep CEP default enabled and don't override w/ zero value. w/o this patch: [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[0] : 0x0 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[1] : 0x0 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[2] : 0x0 w/ this patch: [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[0] : 0x1 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[1] : 0x1 [SPEW ] CPU_POWER_MGMT_VR_CONFIG : CepEnable[2] : 0x1 Change-Id: I8908e8b6c995390b559212d456db6ddf984448a3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-09-02soc/intel/cannonlake/Kconfig: Deduplicate selectionsFelix Singer
All of the SoCs in the cannonlake directory select the following options. So move them to the common option SOC_INTEL_CANNONLAKE_BASE in order to deduplicate selections. * FSP_USES_CB_STACK * HAVE_INTEL_FSP_REPO * SOC_INTEL_CONFIGURE_DDI_A_4_LANES Change-Id: I6ce5edb2ba2c138b44601b32c3ecba2e761136f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77447 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-09-02soc/intel/cannonlake/Makefile.inc: Remove dead code of CNL SoCFelix Singer
Intel Cannon Lake was removed with commit d456f65056. Thus, remove this dead code. Change-Id: I53cd9d53b01e26f530684aa9c404f50b305c1f54 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-01drivers/mrc_cache: Fix extra space at the beginning of lineSubrata Banik
Change-Id: Ic49cb6c67aa707efa6495788137b550683008868 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-01soc/intel/{adl,jsl,mtl,tgl}: Add ACPI name for GNA deviceMatt DeVillier
Add SA_DEV_SLOT_GNA definition to SoCs missing it, so the name resolves properly. TEST=tested with rest of patch train Change-Id: I31c8b14e5083fc8e212a4e32330125fa72696c73 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-01soc/intel/common/acpi: Add stub for GNA scoring acceleratorMatt DeVillier
Allows boards which enable the GNA device to provide an attachment point for the OS drivers. TEST=tested with rest of patch train Change-Id: I3398eefb80e4407594883dd39128cd7885105ac3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-09-01soc/intel/common: Rename crashlog macrosPratikkumar Prajapati
Remove MAILBOX word from CPU_CRASHLOG_MAILBOX_WAIT_STALL and CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT macros, because they can be used for other interface as well. BUG=b:262501347 TEST=Able to build google/rex. Change-Id: I62b04fa4b05c427db494a536ca6504db02dfeb68 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77236 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01soc/intel/meteorlake: Skip crashlog region with metadata tagPratikkumar Prajapati
Region with metadata tag contains information about BDF entry for SOC PMC SRAM and IOE SRAM. We don't need to parse this as we already define BDFs in soc/pci_devs.h for these SRAMs. Also we need to skip to region as it does not contain any crashlog data. BUG=b:262501347 TEST=Able to build google/rex. Able to trigger crashlog and decode correctly. Change-Id: Id8ed40b865cde8e89045f5c9e713398fcbff5890 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76834 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01soc/intel/common: Add metadata tag definition for crashlogPratikkumar Prajapati
When parsing descriptor table the record can have tag type = 7. This tag contains metadata depending on SOC. The platform may choose to parse it based on implementation of crashlog. BUG=b:262501347 TEST=Able to build google/rex. Change-Id: I60dda06950974f7949fa5635141e4b7798c4d1f2 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 16:16:18 +0000