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2022-08-19mb/system76/gaze16: Move stray header to include folderTim Crawford
Change-Id: Id3367a708744d6a3ed0ba69ed8e0cafe0a5934b6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-19mb/system76/gaze16: Configure GPIOs in mainboard_init()Tim Crawford
Configure GPIOs in `mainboard_init()` instead of during FSP config. Change-Id: Icc40ce71d2bd104c5f41e992f9b28824a3b734d6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66169 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-19mb/system76/gaze16: Split gpio.h into data filesTim Crawford
Split `gpio.h` into `gpio_early.c` for bootblock and `gpio.c` for ramstage to match other System76 boards. Change-Id: I24398ad459754ac80d92d70687ab70b22894a01c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-18mb/google/trogdor: remove variant "pazquel360"Chao Gui
This reverts commit feb551a92550fcc28b32aca77117aa743018b233. Adding new variant "pazquel360" is not needed. BUG=b:239599467 TEST=emerge-trogdor coreboot Signed-off-by: chaogui@google.com BRANCH=none Change-Id: I4878d3a54f96fb9d38f2da1a1c918dfdef80a301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66805 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18mb/google/brya/var/crota: update DPTF setting in CrotaJohnny Li
DPTF Policy and temperature sensor values update from thermal team. BUG=b:237640264 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I45b4f80cbec0723c63ac7fc7176e13ae5a2b54c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66365 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18soc/intel/tigerlake/fsp_params.c: Add INT D routing for PEG60Frans Hendriks
Debian 11 reports ´0:6:0 can´t derive routing for PCI INT D´. Use FIXED_INT_PIRQ for INT D to PIRQ routing table. BUG=NA TEST=Boot Debian 11 on Siemens AS_TGL1 and verify no PIRQ error message in ´dmesg´ Change-Id: If38c7b6f664e0f6533e583ce62504281a4092720 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-18mb/google/brya/acpi: Add PCIe SRCCLK# control to RTD3 methodsTim Wawrzynczak
This patch adds support for turning the PCIe SRCCLK# on and off during RTD3 (just like the soc/intel/common/block/pcie/rtd3 driver). TEST=GC6 and GCOFF sequences still work Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4b369cfcc7245a1c212fa65f65fdab542f60e196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-18mb/google/brya/var/agah: Update NVVDD VR PGOOD GPIOTim Wawrzynczak
For board revs 3 and later, the PG pin for the NVVDD VR moved from GPP_E16 to GPP_E3. To accommodate this, the DSDT contains a Name that this code will write the correct GPIO # to depending on the board rev, and we'll use that instead. BUG=b:239721380 TEST=still works on board rev 2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I11aec6069da8e086789419303871c6d0f5fb29af Reviewed-on: https://review.coreboot.org/c/coreboot/+/66806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-18soc/mediatek/mt8186: spm: Remove redundant callYidi Lin
spm_set_power_control() is already called in spm_init(). It is not necessary to call spm_set_power_control() again in the mtk_mcu reset callback. TEST=check SPM PC value (0x250) after SPM is loaded. [INFO ] SPM: spm_init done in 54 msecs, spm pc = 0x250 Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: I7ee517e1eb6485c52155a69d05781a61ddfe4cad Reviewed-on: https://review.coreboot.org/c/coreboot/+/66785 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18mb/google/brya/var/pujjo: Modify GPIO for SD_WAKE_NLeo Chou
Modify GPP_D17 setting for SD_WAKE_N. BUG=b:242647845 TEST=Build and boot on pujjo Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Iacd89d27174869e34c48d1f62793ddc45b43f3f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-18ec/google: Notify DPTF driver power participant on PD eventVarshit B Pandya
The DPTF power participant device needs to be notified when power source changes so it can re-evaluate power source and power source change count, this can be later used by DPTF along with methods provided by EC. Corresponding changes in EC are https://crrev.com/c/3545778 and https://crrev.com/c/3547317 BUG=b:205928013 TEST=Build, boot brya0 and dump DSDT to check change Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I07f58b928a0dba92bec3817177142c586e5014b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-18soc/amd/mendocino: enable CPPC featureFelix Held
This is sort-of reverts commit cbf290c692b2 ("soc/amd/sabrina: drop CPPC code"), since it turned out that the CPPC feature is supported on Sabrina (now Mendocino) despite this being missing from the documentation I looked at when writing the patch referenced above. Since the CPPC ACPI code generation functionality has been moved to common code, this isn't a direct revert. BUG=b:237336330 TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1c059653eeae207d723c77e8a78b19c86e362296 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-18mb/google/rex: Create 64MB AP Firmware binary for Proto 0Subrata Banik
This patch provides a mitigation path for having different size SPINOR parts across Rex board revisions. Rex Proto 0 only has 64MB SPINOR mounted on the board, and the plan is to use 32MB later with Proto 1 onwards. Hence, the idea here is to maintain a 32MB SPI Flash layout across all Rex board revisions, but the Proto 0 build only selects BOARD_ROMSIZE_KB_65536 config for adding padding at the end of the 32MB range. BUG=b:242825380 TEST=Able to create 64MB AP Firmware for Rex with below layout: SI_ALL: 0-9MB SI_BIOS: 9MB-32MB Padding/Unused: 32MB-64MB Additionally, able to hit CPU reset on MTLRVP (has 64MB SPINOR) with Rex AP Firmware binary. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibcc2206456639ef4ff22e0c4069521e583be58cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66828 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-18Revert "soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSS"Subrata Banik
This reverts commit eb80b1efa36c99e485b2604e913c2aa316168eea. Reason for revert: Results into hard hang with serial debug msg inside FSP-S. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8e7cf804828da8939f591eb0770c8daf830c8d94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-17mb/google/nissa: Simplify LTE GPIO config using pad-based overridesReka Norman
Currently, to enable/disable LTE based on fw_config on nissa, we have two sets of GPIOs: lte_enable_pads and lte_disable_pads. This was to prevent the SAR interrupt pin GPP_H19 from floating for the short period of time between enabling it in gpio.c and disabling it in fw_config.c (see CB:64270 for more details). With the new pad-based GPIO overrides (CB:64712), this is no longer an issue since the gpio.c and fw_config.c overrides are applied at the same time. So simplify the LTE GPIO configuration by enabling all the LTE pins in the variant gpio.c, then disabling them in fw_config.c if needed. BUG=b:231690996 TEST=LTE still works on nivviks Change-Id: I5bf20a027414ea5e7c1f198d69e355c76f467244 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66776 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17mb/google/skyrim/port_descriptors: replace sbna acronym with mdnFelix Held
Since the SoC that was upstreamed as Sabrina was finally renamed to Mendocino, also adjust the abbreviation used for the DXIO/DDI descriptor struct array names. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I14ecf98e4a94376a70e783774c8f7b8701581220 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66815 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17ec/google/chromec: Add BFIV, BFCTTim Van Patten
The flag EC_BATT_FLAG_CUT_OFF was added with the CL: 3704470: battery: Set battery cutoff flag https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3704470 This flag is set in the ACPI memory mapped area when the command `ectool batterycutoff` is issued so ACPI code can respond appriopriately. This CL adds the flags to coreboot ACPI. BRANCH=none BUG=b:217911928 TEST=Boot nipperkin with low & no battery TEST=Boot skyrim with low & no battery Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I4e63ff4fc2d6b0ecf767a6bffd81f823c74c15bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/66803 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17commonlib/clamp.h: Relicense file to be BSD-compatibleAngel Pons
I added this header in commit a6c8b4becbd12fe6043557ca1e398c1a7c691007 (nb/intel/sandybridge: Rewrite get_FRQ). Relicense it as "BSD-3-Clause OR GPL-2.0-or-later" and move it into the BSD-licensed commonlib part. Change-Id: I89ebdcdf8d06e78e624e37a443696981b3b17b7d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66711 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17soc/intel/apollolake: Add the remaining CSE Firmware Status RegistersSean Rhodes
Add the Shadow Registers from 2 through 5 and print information from them accordingly. All values were taken from Intel document number 571993. Tested on the StarLite Mk III and the correct values are shown: [DEBUG] CSE: IBB Verification Result: PASS [DEBUG] CSE: IBB Verification Done : YES [DEBUG] CSE: Actual IBB Size : 88 [DEBUG] CSE: Verified Boot Valid : FAIL [DEBUG] CSE: Verified Boot Test : NO [DEBUG] CSE: FPF status : FUSED Please note, the values shown are in an error state. This replaces the Fuse check that is done via Heci, as this will only work whilst the CSE is in a normal state. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8a9e7b329010fae1a2ed9c3fefc9765e617cdfe4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-17soc/intel/apollolake: Enable DPTF & SMBus as it is a required deviceSean Rhodes
coreboot is unable to disable certain devices, whilst many are hidden DPTF and SMBus are not. Set this to enabled chipset so that it is enabled by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I85d74179b6fe3c6126566422f82f7b806f80d0c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-17mb/google/nissa/var/yaviks: Generate SPD ID for supported memory partsWisley Chen
Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56AK6BX069 2 (0010) K3LKBKB0BM-MGCP 2 (0010) BUG=b:242277219 BRANCH=None TEST=run part_id_gen to generate SPD id Change-Id: I46c168482113beb7cd28f387ed495847aba8602f Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-17mb/google/nissa: Create yaviks variantWisley Chen
Create the yaviks variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:242277219 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVIKS Change-Id: Id60fe0e54a8e0196a302141f58c6695779ac251a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-08-17soc/intel/tigerlake: Disable DISPLAY_FSP_VERSION_INFO on IOTFrans Hendriks
Build error for platforms using Intel FSP for TGL_IOT (FSP_TYPE_IOT). File FirmwareVersionInfoHob.h does not exist in Intel FSP TGL IOT package. File FirmwareVersionInfoHob.h is included when DISPLAY_FSP_VERSION_INFO is enabled. Enable this config for non TGL_IOT only. BUG = NA TEST = Verify that DISPLAY_FSP_VERSION_INFO is disabled by default for TGL_IOT configuration (Build Siemens AS_TGL1). Change-Id: Ief5a7222daf6f1658e8dc04f97b4ddc2bcb74905 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66636 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17soc/amd/common/include/espi: add more decode rangesFelix Held
Mendocino has more eSPI decode ranges than Picasso or Cezanne. To support these additional ranges, introduce a new Kconfig option SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES that can be selected by the SoCs that support the additional eSPI IO/MMIO decode ranges. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-17mb/google/brya/var/ghost: Enable NXP UWB SR150 chipJack Rosenthal
Add GPIO configuration and device tree to enable the chip. BUG=b:240607130 BRANCH=firmware-brya-14505.B TEST=Patch linux with NXP's pending drivers UWB device is probed and can respond to a simple hello packet Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I83be712d243c365a5cbfe6f69a6bd85440c5bec7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17soc/intel/common: Update the comments for CSE RX and TX functionsSridhar Siricilla
The patch updates the comments on return values and heci_reset() triggering during error scenarios of heci_receive() and heci_send() functions to reflect the current implementation. Test=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6c6c3312602c772147cb315db9ea1753d84a0fb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17mb/google/nissa/var/pujjo: Configure EE noise mitigation for pujjoLeo Chou
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 - Set pre-wake randomization time (DPA) to 100 BUG=b:241349500 TEST=build FW and checked fsp log. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Id4a1540de8c3ee74695631acc8181dcc446fe137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66783 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17mb/google/nissa/var/pujjo: Add FW_CONFIG probe for supported devicesStanley Wu
Add FW_CONFIG probe based on pujjoteen boxster of below devices: LTE, SD card, stylus, WFC camera, AUDIO BUG=b:236158122 TEST=Boot to OS and verify that above devices are set based on fw_cofnig. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I49fc5461e7affba68a6b89bf166c84598fbfa088 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66741 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17mb/google/brya/var/ghost: Add max98396 supportEric Lai
Ghost has two amps and address are 0x3c and 0x3d. BUG=b:231581723 BRANCH=firmware-brya-14505.B TEST=max98396 driver can get the DSD property correctly. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I3b6a331ca42e97f984f3a585726c02452bb067f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17drivers/i2c: add MAX98396 driverEric Lai
Add MAX98396 support. BUG=b:232606045 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I835b51ea1fcc9363992d43a625f80cb545802fc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17soc/intel/broadwell: Unselect VBOOT_STARTS_IN_ROMSTAGEYu-Ping Wu
Starting vboot earlier in bootblock instead of romstage is usually preferred (smaller root of trust, among other things). Therefore unselect VBOOT_STARTS_IN_ROMSTAGE for broadwell. Also remove the unused BROADWELL_VBOOT_IN_BOOTBLOCK option. Change-Id: If8feea403ee4cd3a16ed8cb0faf9f4ccb34feaaf Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-17Revert "soc/intel/broadwell: Drop vboot support"Yu-Ping Wu
This reverts commit f87489bbae5bb1ae3b17b6a03af9e309769b1f72. Reason for revert: Broadwell actually supports early flash writes. Change-Id: I342aefe464c72a32b41a40062b62d871caa0707b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17mb/google/skyrim: Move I2C config to devicetreeJon Murphy
The I2C config was unnecessarily placed in the overridetree. As we prepare for fanout, this is going to cause unnecessary noisy changes. Move the I2C config to the devicetree to avoid this. BUG=None TEST=Build Change-Id: I09ad5c911a0fd00274761cb71e9b659b47cd6da1 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66802 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17pciexp_device: Fix offset handling for extended capabilitiesNico Huber
The PCIe spec explicitly states that the bottom-two bits of the next offset are reserved for future use and should be masked. We can also change the loop condition to avoid wrong offsets below 0x100 (exten- ded capabilities always reside in the extended config space). The whole patch series was tested on Google Samus and keeps the L1ss configuration of the WiFi device in tact. Change-Id: I0b622a0ce0a4a1127d266226ade0ec1e66e9fb79 Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66459 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17pciexp: Refactor extended capability handlingNico Huber
Add some inline functions for the bit-wise operations, change the loop body to an if-bail-out style and remove stateful variables. Change-Id: Ia8db915f375737064e3486d313383d9b6c3eb2b8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66458 Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17pciexp_device: Drop quirk handling in pciexp_get_ext_cap_offset()Nico Huber
Keeping these checks in generic code seems rather dangerous. In theory, it could lead to endless loops even for compliant devices, if we accidentally detect arbitrary register contents as capability and use them as a pointer to another one. Not to forget that the register reads can have side effects. All users of this `cafe` have been converted to use pciexp_find_ext_vendor_cap(). Change-Id: I70d21534e04282a4156572a290b83c46be085e0c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66456 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17pciexp_device: Properly search for Intel's 0xcafe capabilityNico Huber
We have this quirk in our tree since the introduction of L1-substate support[1]. The way we searched for this capability was rather crude: We simply assumed that it would show up in the first data word of another capability. As it turned out that it is actually a proper vendor-specific capa- bility that we are looking for, we can drop some of the mystic code. This was confirmed to work on the device that was originally used during development, Google/Samus. [1] commit 31c6e632cf (PCIe: Add L1 Sub-State support.) Change-Id: I886fb96e9a92387bc0e2a7feb746f7842cee5476 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17pciexp_device: Introduce pciexp_find_ext_vendor_cap()Nico Huber
Vendors can choose to add non-standard capabilities inside a Vendor-Specific Extended Capability. These are identified by the Extended Capability ID 0x0b. Change-Id: Idd6dd0e98bd53b19077afdd4c402114578bec966 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17pciexp_device: Join pciexp_find_(next_)extended_cap() APIsNico Huber
Move the `offset` parameter into pciexp_find_extended_cap(). If it's called with `0`, we start a new search. If it's an existing offset, we continue the search. This makes it easier to search for multiple occurences of a capa- bility in a single loop. Change-Id: I80115372a82523b90460d97f0fd0fa565c3f56cb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17soc/amd/common/acpi/cppc: add nominal and minimum frequenciesFelix Held
Now that we have functionality to get the minimal and nominal frequencies, the corresponding fields in the CPPC config can now be populated. If the HOB isn't present and/or the frequency values could not be obtained, CPPC_UNSUPPORTED is still used; otherwise the HOB-provided frequency in MHz is used for those two fields. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Change-Id: Id3257690a3388d44ceceb7ac4f1db3d49e195caa Reviewed-on: https://review.coreboot.org/c/coreboot/+/66551 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17soc/amd/common/fsp: add common CPPC data HOB supportFelix Held
Add common AMD FSP functionality to get the nominal and minimal CPU core CPPC frequencies. Those functions will be used in the _CPC ACPI object generation in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Change-Id: I68ebdf610795d2673e0118a732f54f5f719b73c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66550 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17soc/intel/alderlake/acpi: Changing USB ports indexing.Adam Mills
xhci.asl places the SS ports at 11-14, following HS ports 1-10. However, for Nissa, the kernel detects 12 HS ports 1-12 and 4 SS ports at 13-16, resulting in the PLD intended for SS ports 1 and 2 being associated with HS ports 11 and 12. Changing the asl for SS to 13-16 makes locations associate correctly and peering work. BUG=b:234544025 BRANCH=firmware-brya-14505.B TEST=manually verified on Nissa and Brya devices Change-Id: I57aef771a7ff086b71a9e90b81e1a3635f832b2f Signed-off-by: Adam Mills <adamjmills@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66590 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17soc/amd/cezanne,picasso,sabrina/smihandler: add comment about SMN accessFelix Held
The SMI sleep entry handler will access the SMN space via the index/data register at PCI config space offsets 0xb8 and 0xbc of the device at bus 0, device 0, function 0. This register pair is also used by other software components running on the x86 cores after boot, so it should be saved and restored at the beginning/end of the SMI handler if it accesses SMN. The sleep entry SMI handler is a special case, since the OS is already done at the moment we enter the sleep SMI handler which is the last code that gets run on the x86 cores before entering S3/4/5. BUG=b:237004699 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0980562ef8a61489082a81c71d6d00d0786d68cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-17mb/google/brask/variants/moli: use specific gpio table by board_verRaihow Shi
EN_PP3300_EMMC will change to GPP_A21 to meet DP++ function and it based on Moli GPIO Table_20220803.xlsx. But it will let current eMMC skus can't boot into OS, so use the board_ver to decide which gpio table return and set override_gpio_table_id2 and early_gpio_table_id2 based on Moli GPIO Table_20220803.xlsx 1. set GPP_A21 to EN_PP3300_EMMC 2. set GPP_A22 to NC 3. set GPP_E20 to DDIC_DP_CTRCLK 4. set GPP_E21 to DDIC_DP_CTRLDATA BUG=b:241370405 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I0a2c8684d140738f43658cd6075ed083eee44e65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-08-16soc/intel/alderlake: Fill ucode loading UPD if USE_FSP_MP_INIT enableSubrata Banik
This patch calls into a helper function to fill `2nd microcode loading FSP UPD` if FSP is running CPU feature programming. TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8534305e4e973c975ad271b181a2ea767c840ae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66686 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-16mb/google/skyrim: Create winterhold variantIsaac Lee
Create the winterhold variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:240970782 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_WINTERHOLD Signed-off-by: Isaac Lee <isaaclee@google.com> Change-Id: I0e16f0a674aa3f4687cd82d5840a3c2087148a51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66620 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-16mb/google/skyrim: Enable PSP PostcodesJon Murphy
This reverts commit I73b7ddec50936f7836f915f459ca0bdc0777cb22. Revert change to disable post codes. Post codes were initially disabled because of an issue with initialization within the SMU. BUG=b:227201571 TEST=Build and boot to OS in Skyrim. Change-Id: I2a2bd2252a103c682b5d4ad5ecd1da42b3744083 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66092 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-16mb/google/brya/acpi: Add minimum off timer for GCOFFTim Wawrzynczak
By moving the large wait for FBVDD discharge from PGOF to PGON, the whole time may be avoided if enough time has elapsed between the successive calls. BUG=b:239719056 TEST=With Nvidia test software, verify ACPI prints Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I891aa14f120d58c45b8965038a9d2f2a417b3f3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-16mb/google/brya/acpi: Fix GC6 entry and exit sequencesTim Wawrzynczak
Now that the virtual wire situation is figured out, the GC6 sequence is updated to match the latest HW design guide from Nvidia. This allows Nvidia test software to (mostly) successfully execute the GC6 test, but with some PCIe AER errors. BUG=b:214581763 TEST=tested with Nvidia test software Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia094c4fa9b4db094a59b9b6f02be1a649ee8569b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-16mb/google/brya/var/agah: Move VW GPIO programming to bootblockCliff Huang
Since the VW GPIOs are not in the baseboard GPIO table, they do not actually override anything, and hence do not actually get programmed. This patch moves the programming from the ramstage table to the bootblock table so they get programmed. BUG=b:214581763 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I42db44d38df20dd2695921e2f252be163f6b17f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-16mb/**/dsdt.asl: Drop misleading "OEM revision" commentAngel Pons
It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725 on mainboards with a chipset not yet released on 2011-07-25. Since this comment is most likely to have been copy-pasted from other boards, drop it from boards which use a chipset newer than Sandy/Ivy Bridge. Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-08-16mb/**/dsdt.asl: Drop superfluous commentsAngel Pons
These comments don't add much value, so remove them. Change-Id: I7e9692e3fe82345cb7ddcb11c32841c69768cd36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66713 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-08-16soc/intel/common/cpu: Remove the address-of (`&`) operator usageSubrata Banik
This patch drops explicit usage of the address-of operator ('&') while passing the function pointer (argument 0) to the `mp_run_on_all_cpus` API. Note: It's just cosmetic change without any real difference in the operation. TEST=Able to build and boot Google/Kano where CPU feature programming is successful on all logical processors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2c77959a76d2240ad1bfb7a9d7b9db7e8aee42f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66685 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-15pciexp_device: Fix pciexp_find_next_extended_cap()Nico Huber
If we already encountered the last extended capability in the list, we'd call pciexp_get_ext_cap_offset() with `offset == 0`. So it also needs to check if the passed offset is valid. As there were no callers of pciexp_find_next_extended_cap() yet, pciexp_get_ext_cap_offset() was only ever called with `PCIE_EXT_CAP_OFFSET`. Change-Id: I155c4691a34ff16661919913a3446fa915ac535e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-15soc/amd/common/fsp/fsp-acpi: rework HOB pointer validity checkFelix Held
Checking if the return value of the fsp_find_extension_hob_by_guid call is NULL should make the code a bit easier to read. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6bdb07eab6da80f46c57f5d7b3c894b41ac23b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-15mb/google/guybrush: Pass in Cr50 IRQ to PSPRaul E Rangel
Different guybrush boards have different TPM IRQs. This change passes in the correct GPIO to the TPM. BUG=b:241824257 TEST=Boot guybrush and verify GPIO 3 was passed and that OEM Crypto test passes Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I61954fa4493fd56e528b616ca65166a31917f557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-15soc/amd/common/block/psp: Add psp_set_tpm_irq_gpioRaul E Rangel
The PSP currently uses a hard coded GPIO for the TPM IRQ. Not all board versions use the same GPIO. This method allows the mainboard to pass in the correct GPIO. BUG=b:241824257 TEST=Boot guybrush and verify PSP message prints Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie05d095d7f141d6a526d08fbf25eb2652e96aa49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-15soc/amd/*: move reset_i2c_peripherals call after early GPIO setupFelix Held
Since bootblock_soc_early_init gets called before bootblock_mainboard_early_init which does the early GPIO setup, external I2C level shifters that are controlled by GPIOs might not be enabled yet. Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure that the early GPIO setup is already done when reset_i2c_peripherals is called. Haven't probed any SCL signal on the non-SoC side of the I2C level shifters yet, but the waveform on the SCL pin of I2C3 on the SoC of a barla/careena Chromebook doesn't have the longer than expected SCL pulses any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-14soc/intel/common/block/cse: Tidy up table in commentAngel Pons
Adjust an ASCII art table so that it looks good: consistent padding and aligned table borders. Change-Id: I26196f969406e03f320256b0c3a337282f636914 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66707 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-14mb/google/corsola: Distinguish anx7625 and ps8640 for steelixZanxi Chen
Steelix uses ps8640 for board revision < 2, and uses anx7625 for newer revisions. So we use board_id to distinguish anx7625 and ps8640. BUG=b:242018373 TEST=firmware bootsplash is shown on eDP panel of steelix. Change-Id: Ia6907d2e6e290375946afb13176ab9a26dedd671 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org>
2022-08-14mb/google/herobrine: Update modem status with skuid infoSudheer Kumar Amrabadi
BUG=b:232302324 TEST=Validated on qualcomm sc7280 development board Observing 9th bit of skuid with below values, 1 means Modem device 0 means non-modem device Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com> Change-Id: If62b272a43a4588f96e49c8b2b1d75862d401d31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-14soc/qualcomm/sc7280: Add SocInfo support in corebootTaniya Das
Add support for SocInfo in coreboot. The API socinfo_modem_supported is added to help to differentiate between LTE and WiFi SKUs. BUG=b:232302324 TEST=Validate boards are detected correctly on LTE and Wifi SKUs Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: I61047ad49772c3796ba403cafde311ad184a4093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-14drivers/nxp/uwb: Add new driver for NXP UWB SR1xx chipJack Rosenthal
Add a new driver for NXP UWB SR1xx (e.g., SR150) device. The driver was originally written by Tim Wawrzynczak as a WIP in CL:3503703, and was based on drivers/spi/acpi. BUG=b:240607130 BRANCH=firmware-brya-14505.B TEST=On ghost (with follow-up CL), patch linux with NXP's pending drivers -> UWB device is probed and can respond to a simple hello packet Co-authored-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I5b1b0a5c1b48d0b09e7ab5f2ea6b6bc2fba2a7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66466 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-14mb/google/brya/var/ghost: Enable cameraJack Rosenthal
Add OV 5675 MIPI camera to ghost, sensor eeprom, and IPU device to device tree. Enable config for MIPI camera. BUG=b:241343306 BRANCH=firmware-brya-14505.B TEST=with ghost overlay changes, camera in camera app works Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ie079e43ae0f34efba396331922ea4a89eda72128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-14Revert "soc/amd/sabrina: Re-init eSPI in bootblock"Karthikeyan Ramasubramanian
This reverts commit 8b1c6c6cb384c89659abbd043c2566df358d8f95. With updated APCB, eSPI configuration carries over to bootblock. Hence eSPI does not need to be re-initialized in bootblock. BUG=b:241426419 TEST=Build and boot to OS in Skyrim with PSP verstage. Cq-Depend: chrome-internal:4929421 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I426b07329d4a0154d915381c99dcc9746b7a3d7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-14broadwell: Decouple LPDDR3 DQ/DQS maps from `pei_data`Angel Pons
Introduce the `BROADWELL_LPDDR3` Kconfig option along with some wrapper code to allow mainboards using LPDDR3 DRAM to supply the DQ/DQS maps to chipset code without having to use `pei_data`. The only mainboard using LPDDR3 is Google Samus. Change-Id: I0aaf0ace243c03600430c2a7ab6389a7b20cb432 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55812 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-14soc/intel/broadwell: Consolidate SPD handlingAngel Pons
Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. As done on Haswell, add the `mb_get_spd_map` function and the `struct spd_info` type to retrieve SPD information from mainboard code without having to use `pei_data` in said mainboard code. Unlike Haswell MRC, Broadwell MRC uses all positions of the `spd_data` array, not just the first. The placeholder SPD address for memory-down seems to be different as well. Adapt the existing code to handle these variations. Once complete, the abstraction layer for both MRC binaries will have the same API. Change-Id: I92a05003a319c354675368cae8e34980bd2f9e10 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-14broadwell boards: Do not set `ddr_refresh_2x` againAngel Pons
The `ddr_refresh_2x` setting is already set in chipset code. Change-Id: I76478689b3aa27c369a0413d9fbde03674d5e528 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55810 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-14broadwell: Move some MRC/refcode settings to devicetreeAngel Pons
There's no generic way to tell whether a mainboard has an EC or not. Making Kconfig symbols for these options seems overkill, too. So, just put them on the devicetree. Also, drop unnecessary assignments when the board's current value is zero, as the struct defaults to zero already. Change-Id: I8d3b352333bea7ea6f7b0f96d73e6c2d7d1a2cfb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55809 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-14mb/google/auron: Move SPD file handling to chipsetAngel Pons
The SPD file handling code is generic and can be used on any other mainboard. Move it to chipset scope to enable code reuse. Change-Id: I85b1460ccb82f0c1bf409db4a6b4c9355c25e76d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55808 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-14broadwell: Compute channel disable masks at runtimeAngel Pons
Introduce the `SPD_MEMORY_DOWN` macro to indicate that a slot is used with memory-down. This enables computing the channel disable masks as the bits for slots where the SPD address is zero. To preserve current behavior, zero the SPD addresses for memory-down slots afterwards. Change-Id: I75b7be7c72062d1a26cfc7b09b79de62de0a9cea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55807 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13vc/amd/fsp/cezanne,mendocino: add FSP CCX CPPC HOB GUID and structFelix Held
To generate a complete _CPC ACPI object, coreboot needs the minimal and nominal core speed values which are specific to the CPU and not only the CPU family. Since this is done by an undocumented mechanism, FSP has to do this and puts the information we need into a HOB. This adds the HOB GUID and the structure of the HOB data. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Change-Id: Ibf338c32de367a3fd57695873da1625338fa196d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66549 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/amd/mendocino/chipset_rembrandt: use right chipset folderFelix Held
Since the path after the chip keyword needs to point to the directory that contains the chipset's chip.h file, change this from soc/amd/rembrandt to soc/amd/mendocino. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63334fbd59e74df491035b5cf7e296818cc02665 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66688 Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-13src/mb: Update unlicensable files with the CC-PDDC SPDX IDMartin Roth
These files contain no creative content, and therefore have no copyright. This effectively means that they are in the public domain. This commit updates the unlicensable empty (and effectively empty) files with the CC-PDDX identifier for license compliance scanning. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I0b76921a32e482b6aed154dddaba368f29ac2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66497 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13arm/libgcc: Support signed 64-bit divisionRob Barnes
Add support for signed 64-bit division. The implementation mostly relies on __aeabi_uldivmod, which is already implemented. ldivmod.S was adapted from CrOS EC version of ldivmod.S: https://chromium.googlesource.com/chromiumos/platform/ec/+/main/third_party/libaeabi-cortexm0/core/cortex-m0/ldivmod.S The CrOS EC version was adapted from: https://github.com/bobbl/libaeabi-cortexm0/blob/master/ldivmod.S BUG=b:240316722 BRANCH=None TEST=Signed division works in PSP verstage (runs on ARM) Change-Id: I53785c732b0fa35a4809bc054f1482c5461ada7b Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2022-08-13timer: Switch mono_time to uint64_tRob Barnes
A 32-bit long storing microseconds will rollover every ~1.19 hours. This can cause stopwatch to misbehave, causing unexpected failures. If the current field in stopwatch is near 2^31, the expires field may rollover when initialized. If this occurs, stopwatch_expired() will instantly return true. If current and expires fields are near 2^31, the current field could rollover before being checked. In this case, stopwatch_expired() will not return true for over an hour. Also stopwatch_duration_usecs() will return a large negative duration. This issue has only been observed in SMM since it never takes more than 35 minutes to boot. Switching to uint64_t mitigates this issue since it will not rollover for over 500K+ years. The raw TSC would rollover sooner than this, ~200 years, depending on the tick frequency. BUG=b:237082996 BRANCH=All TEST=Boot Nipperkin Change-Id: I4c24894718f093ac7cd1e434410bc64e6436869a Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65403 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-13soc/mediatek/mt8188: Initialize DFDRex-BC Chen
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values can be shown for debugging using MTK internal parsing tools. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6d19dc6f4e47ed69ba2ea87c79984020a413aee9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66586 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/mediatek: Move common definition of DFD to common folderRex-BC Chen
We use the same dump address and size for DFD in all MediaTek SoCs, so we move them to dfd_common.h and rename dfd_common.h to dfd.h. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I162bbb0a82e3b55c8cfbbd20e28a54ad01fd6b0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66585 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/mediatek/mt8188: Fix the order of register address in addressmap.hRex-BC Chen
TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ie9d7b361dda8c5850bc0682c255bc20f9e26675c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66668 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13soc/mediatek/mt8188: Add tracker dumpRex-BC Chen
Tracker is a debugging tool. When bus timeout occurs, the system will reboot and latch some values of tracker registers which could be used for debugging. This function will be triggered only when it encounters the bus hanging issue. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I78f676c08ea44e9bb10bd99bbfed70e3e8ece993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66584 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-13soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MITMacpaul Lin
This replaces 'SPDX-License-Identifier' tags in all the files under soc/mediatek/mt8188 for better code re-use in other open source software stack. These files were originally from MediaTek and follow coreboot's main license: "GPL-2.0-only". Now MediaTek replaces these files to "GPL-2.0-only OR MIT" license. Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Change-Id: If61e8b252400e8e5ecd185b6806b1ca279065f15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66628 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-13mb/google/brya: Use default EPP of 50% for skolasJeremy Compostella
A power and performance analysis performed on Alder Lake demonstrated that with an EPP (Energy Performance Preference) at 50% along with EET (Energy Efficient Turbo) disabled, the overall SoC performance are similar or better and the SoC uses less power. For instance some browser benchmark results improved by 2% and some multi-core tests by 4% while at the same time power consumption lowered by approximately 7.6%. Similar results are observed on Raptor Lake. BRANCH=firmware-brya-14505.B BUG=b:240669428 TEST=verify that EPP is back to the by default 50% setting `iotools rdmsr 0 0x774' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I735ad9d88c7bf54def7a23b75abc4e89a213fb61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-13Revert "mb/google/brya: Set EPP to 45% for all Brya variants"Jeremy Compostella
This reverts commit 938f33e9f7756d730a1da278679087476a476bf2. A power and performance analysis performed on Alder Lake demonstrated that with an EPP (Energy Performance Preference) at 50% along with EET (Energy Efficient Turbo) disabled, the overall SoC performance are similar or better and the SoC uses less power. For instance some browser benchmark results improved by 2% and some multi-core tests by 4% while at the same time power consumption lowered by approximately 7.6%. BRANCH=firmware-brya-14505.B BUG=b:240669428 TEST=verify that EPP is back to the by default 50% setting `iotools rdmsr 0 0x774' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Icacc555e62533ced30db83e0a036db1c85c0bfa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-13Revert "soc/intel/alderlake: Enable energy efficiency turbo mode"Jeremy Compostella
This reverts commit 844dcb3725fc95df53a7229703f5059d2c36f98e. A power and performance analysis performed on Alder Lake demonstrated that with an EPP (Energy Performance Preference) at 50% along with EET (Energy Efficient Turbo) disabled, the overall SoC performance are similar or better and the SoC uses less power. For instance some browser benchmark results improved by 2% and some multi-core tests by 4% while at the same time power consumption lowered by approximately 7.6%. BRANCH=firmware-brya-14505.B BUG=b:240669428 TEST=verify that ETT is disabled `iotools rdmsr 0 0x1fc' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I96a72009aaf96d4237d57f4d5c8b1f41f87174d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66281 Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-13mb/google/brya/var/taniks: Disable PCH USB2 phy power gating for taniksJoey Peng
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for taniks board. Please refer Intel doc#723158 for more information. BUG=b:241965786 TEST=Verify on taniks boards. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib95430c7ba9d84f8bafcb1febcff9b4e4038cadc Reviewed-on: https://review.coreboot.org/c/coreboot/+/66622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-13mb/google/brask/variants/moli: modify psys_pl2 for 15W and 28W SOCRaihow Shi
Moli has 90W adapter for 15W SOC and 135W adapter for 28W SOC, so modify the Psys_PL2 for both 15W and 28W SOC. -set 90W Psys_PL2 for 15W SOC -set 135W Psys_PL2 for 28W SOC BUG=b:242119726 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: If8f9006d797d74f6d5d802d445edc425a4700420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-13device: Skip not assigned resources during global resource searchShuo Liu
It's possible that some BARs are not got their resource successfully mapped, e.g. when these BARs are too large to fit into the available MMIO window. Not assigned resources might be with base address as 0x0. During global resource search, these not assigned resources should not be picked up. One example is MTRR calculation. MTRR calculation is based on global memory ranges. An unmapped BAR whose base is left as 0x0 will be mistakenly picked up and recognized as an UC range starting from 0x0. Change-Id: I9c3ea302058914f38a13a7739fc28d7f94527704 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66347 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-08-13mb/starlabs/starbook/tgl: Enable TPM Measured BootSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I251840b409dead62586cefe5856b6c544401ba30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-13mb/starlabs/starbook/kbl: Enable CRB_TPMSean Rhodes
Enable CRB_TPM to allow the use of the fTPM (Intel PTT). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b69854ea636947480402ce12450f431028660a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-08-13payloads/tianocore: Rename TianoCore to edk2Sean Rhodes
coreboot uses TianoCore interchangeably with EDK II, and whilst the meaning is generally clear, it's not the payload it uses. EDK II is commonly written as edk2. coreboot builds edk2 directly from the edk2 repository. Whilst it can build some components from edk2-platforms, the target is still edk2. [1] tianocore.org - "Welcome to TianoCore, the community supporting" [2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform firmware development environment for the UEFI and UEFI Platform Initialization (PI) specifications." Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-12soc/amd/cezanne,common: factor out CPPC code to common AMD SoC codeFelix Held
The Cezanne CPPC ACPI table generation code also applies to Sabrina, so move it to the common AMD SoC code directory so that it can be used for Sabrina too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5ce082a27429948f8af7f55944a1062ba03155da Reviewed-on: https://review.coreboot.org/c/coreboot/+/66400 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-12soc/amd/mendocino: clear Port80 enable bit in ESPI DecodeJon Murphy
This reverts commit Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae. There was a bug that caused the SMU to hang when writing port80. it has since been resolved, so revert this workaround. BUG=b:227201571 TEST=Build and boot to OS in Skyrim. Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5f10e282ab03756c7dbfb48182940f979eb122e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66470 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-12soc/(amd|rockchip): Update vb2ex_hwcrypto implementations to new API reqJulius Werner
We want to extend the vb2ex_hwcrypto APIs on the vboot side to allow passing 0 for the data_size parameter to vb2ex_hwcrypto_digest_init() (see CL:3825558). This is because not all use cases allow knowing the amount of data to be hashed beforehand (most notable the metadata hash for CBFS verification), and some HW crypto engines do not need this information, so we don't want to preclude them from optimizing these use cases just because others do. The new API requirement is that data_size may be 0, which indicates that the amount of data to be hashed is unknown. If a HW crypto engine cannot support this case, it should return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED to those calls (this patch adds the code to do that to existing HW crypto implementations). If the passed-in data_size value is non-zero, the HW crypto implementation can trust that it is accurate. Also reduce a bit of the console spew for existing HW crypto implementations, since vboot already logs the same information anyway. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ieb7597080254b31ef2bdbc0defc91b119c618380 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-12mb/google/brya/var/taeko: Disable PCH USB2 phy power gating for taekoJoey Peng
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for taeko board. Please refer Intel doc#723158 for more information. BUG=b:241965786 TEST=Verify on taeko/tarlo boards. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I03042906d5bea9b9010016adb98fbe68e2dc92f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-12soc/mediatek/mt8186: Enable USB macro controlAllen-KH Cheng
When powering down SSUSB, the system needs to wait the ACK from SSUSB. We found that the setting of USB PAD top macro is not correct and it will cause timeout waiting for the ACK from SSUSB. To resolve this, we add mt_pll_set_usb_clock() in pll.c to enable usb macro control for powering down SSUSB. TEST=timeout of ssusb powerdown ack does not occur. BUG=b:239634625 Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> Change-Id: I58ba86e0467284e9947bfda1005c151a3e0c8881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66600 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-12mb/google/brya/var/mithrax: Add new memory H9HCNNNCPMMLXR-NEEJohn Su
Add new ram_id:0001 for memory part H9HCNNNCPMMLXR-NEE. BUG=b:241494931 TEST=none Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Iee9f881d8ab21396d208a6af9f0cec8414cb50a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-08-12Fix Alder Lake and Raptor Lake Device ID'sMaximilian Brune
- ADP_P_* -> RPP_S_* (got mixed up I guess) - Remove duplicates of ADP_S_ESPI_* - Add infix _ESPI_ to all ADP_S device ID's Document: 619362 Change-Id: Ic18ecbd420fc598f0ef6e3cf38e987ac3ae6067e Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66629 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12Add missing ADL-S device identificationMaximilian Brune
R680E, Q670E, H610E are the ADL-S IoT variants TEST=Boot ADL-S RVP DDR5 and see silicon info is reported as PCH: AlderLake-S R680E Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I1804994b4b72f0484eabb15323736679d2668078 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-12soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSSJohn Zhao
This change provides access to IOE through P2SB Sideband interface for Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication. There is a policy of locking the P2SB access at the end of platform initialization. The tbt_authentication is read from IOM register through IOE P2SB at early silicon initialization phase and its usage is deferred to usb4 driver. BUG=b:213574324 TEST=Built coreboot and validated booting to OS successfully on MTLRVP board. No boot hung was observed. Change-Id: Icd644c945bd293a8b9c4a364aaed99ec4a7c12f9 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-12soc/intel/common: Delete the TBT authenticaton functionJohn Zhao
Delete the Thunderbolt authentication function ioe_tcss_valid_tbt_auth from the common block. Meteor Lake Platform will implement it. BUG=b:213574324 TEST=Built coreboot image successfully. Change-Id: I97a289faa6351fe562f91d8478b72c9403ce88cb Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
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