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2018-12-19mb/google/octopus: Override emmc DLL values for YorpBora Guvendik
New emmc DLL values for Yorp. BUG=b:120561055 BRANCH=octopus TEST=Boot to OS, chromeos-install, mmc_test Change-Id: I771c959a15959160224f056c0a16aa65bfbba94e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/30073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-12-19mb/ocp/wedge100s/romstage: Workaround broken platform statePatrick Rudolph
Sometimes the platform boots in an invalid state, that will cause FSP-M to fail. As a board_reset() doesn't fix it, issue an full_reset() as soon as the IA32_FEATURE_CONTROL MSR is locked at beging of romstage. Tested on wedge100s. After full reset the system behaves as normal. Change-Id: I1a382b8fb650311b0c24b48e0986d22edfa2d261 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-12-19mb/google/sarien: Enable DMI/SATA power OptimizeLijian Zhao
Turn on power optimizer of PCH side DMI and SATA controller. BUG=N/A TEST=Build and boot up into sarien platoform, able to finish 100 cycles of s0ix. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I41da2b4106d683945cdc296e2a77311176144f43 Reviewed-on: https://review.coreboot.org/c/30212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19soc/intel/cannonlake: SATA and DMI power optimizeLijian Zhao
Expose the FSP interface to enable SATA and PCH side DMI power optimize options. Actual step executed in FSP, step defined in cannonlake pch BIOS spec(CDI# 570374). Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78 Reviewed-on: https://review.coreboot.org/c/30211 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19soc/intel/skylake: Add Sagv enum value definitionPraveen hodagatta pranesh
SaGv(system Agent Dynamic Frequency) have 4 settings Disabled, Fixedlow, Fixedhigh, Enabled. This patch add all 4 settings in enum definition and used in devicetree. BUG=None Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: I8f3b56f4d2bea1836373cc505ef5147144100b95 Reviewed-on: https://review.coreboot.org/c/30305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19soc/intel/braswell/linclude/soc/device_nvs.h: Fix typoFrans Hendriks
Use 'BAR 1' for the bar1 structure fields. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I1d1278f549fc8a2f3e743e2e2019d3e5f7005614 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/30277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2018-12-19mb/google/kahlee: Remove board_id check for Liara 2T timingsMartin Roth
Use 2T memory timings on Liara for all board IDs. BUG=b:116082728 TEST=Build & boot on Liara Change-Id: I5814e63db35cf7761f4f20792b0f3cf4120a1b60 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/30285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-12-19mb/google/variant/nocturne: set CONFIG_NO_FADT_8042Nick Vaccaro
Set CONFIG_NO_FADT_8042 to avoid probing for the 8042 controller. This speeds up boot on nocturne by 1.3 seconds: Before change: [2.162266] EXT4-fs (mmcblk0p3): mounting ext2 file system using the ext4 subsystem After change: [0.867735] EXT4-fs (mmcblk0p3): mounting ext2 file system using the ext4 subsystem BUG=b:120960844 BRANCH=none TEST=build, flash, and boot nocturne; check dmesg to verify that boot is faster and that you don't see the following log in dmesg: [0.671501] i8042: Probing ports directly. Change-Id: I62a16e6de5e74fa17970d9967f6d1628497ec1d3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/30283 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19google/rambi: disable TXE in devicetree for all variantsMatt DeVillier
The TXE PCI device serves no function under Linux, and doesn't work properly under Windows, so disable/hide it from the OS. Test: Boot Windows 10 on google/squawks, verify TXE not visible under Device Manager. Change-Id: Idaa152e15106b826fd5aa787090acd45719f4228 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-19google/cyan: set touchscreen GPIO to non_maskableMatt DeVillier
Commit 73b723d [google/cyan: Switch Touchpad and Touchscreen...] in additon to changing the touchpad/touchscreen interrupts from edge to level triggered, also marked them as maskable. This not only broke the touchpad functionality, but caused issues with the touchpad as well. Revert the touchpad to being non_maskable for all cyan variants with a touchscreen. Test: boot GalliumOS on google/cyan with a range of kernel versions (4.15.18, 4.16.13, 4.17.x, 4.18.x) and verify touchscreen functional, touchpad working properly (not jittery) Change-Id: I0e0357912f9404af7d0f4e7938a1a94c74810b37 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-19mb/asus/maximus_iv_gene-z: Select NO_UART_ON_SUPERIOTristan Corrick
This board doesn't have a UART on the super I/O. Selecting this option speeds up boot time from ~493 ms to ~416 ms. Change-Id: I1d84f373831381da79022638e1082adf68f47aad Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-19arch/riscv: Don't set FPU state to "dirty"Jonathan Neuschäfer
Quoting from the RISC-V Privileged Architecture manual version 1.10, chapter 3.1.11: The FS and XS fields use the same status encoding as shown in Table 3.3, with the four possible status values being Off, Initial, Clean, and Dirty. Status FS Meaning XS Meaning 0 Off All off 1 Initial None dirty of clean, some on 2 Clean None dirty, some clean 3 Dirty Some dirty Change-Id: If0225044ed52215ce64ea979d120014e02d4ce37 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/28987 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19mb/sifive/hifive-unleashed: remove the definition of MAX_CPUSXiang Wang
When I debug with HiFive Unleashed, I found that hart 4 could not be running. Then find the duplicate MAX_CPUS definition. The correct MAX_CPUS is located in src/soc/sifive/fu540/Kconfig Change-Id: I583f6ba548daeeb6c7e341dc3fa8817e7dec5697 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/30179 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19arch/riscv: Define and use SBI_ENOSYSJonathan Neuschäfer
Change-Id: Ia7f409ebc7e50383a7e445ef8806953347501dab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-19smsc/sch5147: Implement ACPI handling of a few LDNArthur Heymans
Change-Id: Ide30a7396b6248e2037041e177dc8514533718a4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-19mb/lenovo/thinkcentre_a58: Add mainboardArthur Heymans
The following was tested: - Using two DDR2 DIMMs - S3 sleep and resume (on SeaBIOS it needs sercon disabled) - Ethernet NIC - Libgfxinit (native res and textmode) - SATA - USB - 800MHz FSB CPU (Pentium(R) E5200 @ 2.50GHz) - PS2 Keyboard - Serial output TODO: - Add ACPI code for SuperIO devices (done in a follow-up patch) - Add documentation TESTED with SeaBIOS (sercon disabled), Linux 4.19 Change-Id: I483e1143e4095b8a58fed142d31ca7f233a854e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30239 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19superio/smsc: Add SCH5147Arthur Heymans
There are no public datasheets for this SuperIO. The results are from probing the registers manually. Change-Id: Ie5659533c5f224603f918d17942a7057e6701222 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-19mb/foxconn/g41s-k: Don't reprogram inherited subsystemidArthur Heymans
Change-Id: I85b5aef758a1ed30c46ed0adabec3293edb0f3fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-19soc/intel/skylake: Generate DMAR tables for FSP 1.1 boardsMatt DeVillier
Commit c37b0e3 [soc/intel/skylake: Generate ACPI DMAR table] only generates DMAR tables for boards using FSP 2.0, which leaves out Skylake Chromebooks, which use FSP 1.1. Correct this omission by adding the same functionality for FSP 1.1 boards. Test: build/boot on U-series Skylake Chromebook, observe IOMMU fully functional with intel_iommu=on kernel parameter. Change-Id: I68837f58aac357fa3f58979fe92d8993fae58640 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-19soc/intel/cannonlake: Auto turn on HDA controllerLijian Zhao
Update HDAenable bit in Fsp memory init UPD data base on devicetree settings. BUG=N/A TEST=N/A Change-Id: I5159c00a855a2a9516714ccee8ee9933465c5063 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19mb/google/sarien: Use meaningful SATA modeLijian Zhao
Define SATA mode to AHCI mode instead of 0, make devicetree more readable. BUG=N/A Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19soc/intel/cannonlake: Declare SATA Mode clearLijian Zhao
FSP support two SATA modes as AHCI mode (0) and RAID mode (1), make it more clear in header file. Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30093 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19soc/intel/cannonlake: Enable CPU flexible ratioLijian Zhao
CPU ratio will be fixed to non-turbo max value if CpuRatio UPD had been set to zero. BUG=N/A TEST=Boot up into sarien system, cat /proc/cpuinfo and cpu frequency is changing. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I3e82293c8b6027ddf9a528d0654fe46f233dcb82 Reviewed-on: https://review.coreboot.org/c/30216 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19mb/asrock/h81m-hds: Allow "keep state" for power_on_after_failTristan Corrick
When I added the cmos.layout file, I did not realise that the southbridge code cleverly emulated the "keep state" option. Tested on an ASRock H81M-HDS. The `Keep` option works as it should. Change-Id: I908e59d1e1eedefa6610e7f980afc3c04390a519 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-19sb/intel/lynxpoint: Don't force state keep after power failTristan Corrick
The deleted line crept in with commit 562db3bb3fa1 ("libpayload: find source of input characters"). Tested on an ASRock H81M-HDS with `power_on_after_fail` set to `Disable` via CMOS. After this patch, the system no longer powers on as soon as power is restored after a power failure. Change-Id: Ie9d9dab9885b285db1c5094c2c8d62aae551f1e7 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-19src/soc/intel/braswell/northcluster.c: Correct Chromeos RAM reservationFrans Hendriks
RAM is reserved for Chromeos even when Chrome is not used. Use CONFIG_CHROMEOS to determine if RAM must be reserved. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I3f55bf96ab2ec66cddbb54de03455a9bfd194682 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-19mb/google/sarien: Enable ELAN Touchpad and Disable ALPS TouchpadChris Zhou
Enable ELAN Touchpad and Disable ALPS Touchpad BUG=b:119628524 BRANCH=master TEST=ELAN Touchpad can work normally. Change-Id: I7839459a70768fa95ba4871b1915d2ea86419bbb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-12-19soc/intel/cannonlake: Amend comment typoLijian Zhao
Fix typo of "VGOIO" back to "VGPIO". Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ia2b7cb0e5fe2817acc3e3f4656b98dc2462b397f Reviewed-on: https://review.coreboot.org/c/30147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-12-19mainboard: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: I4ee3cc42302c44dc80ae1f285579a4d1775aec16 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-12-19southbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-12-19{device,drivers}: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ib96bf7d48711f518e36f8d12244b5749d84a0f68 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19northbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ie221a142ed804988a05269d42904aba3ac79e0be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19cpu: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ica9514609616e0602fae9b0437d3fa404b645878 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19soc: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Idef8c556ac8c05c5e2047a38629422544392cd62 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19soc/intel/cannonlake: Add Acoustic featuresLijian Zhao
Expose the following FSP UPD interface into coreboot, which is the following: AcousticNoiseMitigation FastPkgCRampDisableIa FastPkgCRampDisableGt FastPkgCRampDisableSa FastPkgCRampDisableFivr SlowSlewRateForIa SlowSlewRateForGt SlowSlewRateForSa SlowSlewRateForFivr Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I21f53c594a085794474e87eb6781b51db88d0c10 Reviewed-on: https://review.coreboot.org/c/30207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19lib/fit: Normalize spaces in board names to dashesJonathan Neuschäfer
CONFIG_MAINBOARD_PART_NUMBER sometimes contains spaces, but spaces inside compat strings aren't nice, so let's convert all spaces to dashes. Change-Id: I46f2b2d7091782e04df5476e50698001511f664b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-19mb/google/octopus/var/ampton: Tune I2C AudioJustin TerAvest
The previous settings caused the I2C frequency for the audio bus to be too high, at 417kHz. The settings in this commit correct the frequency to 396kHz. BUG=b:119423345 Change-Id: Ibed886e6e1b0df4df6b87f6291e515364b3bf718 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/c/30129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-19soc/intel/icelake: Add GPIO group pad base for ACPISubrata Banik
commit msg copied from commit id: 64c9f1584c63403207ee85b1d54ca594ae1fbedf The GPIO drivers in Windows and Linux for the Icelake CPU have a sparse GPIO map and do not allocate pins contiguously. Each GPIO group is allocated as 32 pads regardless of whether the hardware actually has that many in the group. It appears this originated with a bug in Windows/UEFI and was carried over to Linux in order to work with existing firmware: https://lore.kernel.org/patchwork/patch/855244/ In order to support using ACPI GPIOs it is necessary for coreboot to be compatible with this implementation. The GPIO groups that are usable by the OS are declared with a pad base which is then used to compute the number for ACPI GPIOs. Change-Id: I94fafd8af13cf229f5c467de5179aed021465739 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-18Revert "google/sarien: Increase BIOS region to 28MB"Lijian Zhao
This reverts commit ad41f5512306d118047d2f7243678ddb32b4b06b. Reason for revert: <Issue have seen on EVT platform that vboot always fail to verify keyblock A> BUG=b:121169122 Change-Id: I2790ef3463a228008b614498009fbdc8b493cfb0 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30286 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-18mb/asus/kgpe-d16: Set ASpeed GPIO SPD mux lines during bootTimothy Pearson
When the BMC firmware module is installed on the KGPE-D16, the RAM SPD multiplexer lines are disconnected by hardware from the SP5100 GPIOs and attached to BMC GPIO lines instead. Set the BMC GPIOs to match the state of the SP5100 GPIOs during RAM setup. Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac5 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/19820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18southbridge: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: Ic3f7d4d570cb5e343a9cf616e6e71935f9522b0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18northbridge: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: Icae59721db530572d76035975a4e90686bf4fa65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18cpu: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: I67bc60b9e0eb6289193d698787c18ea4593c991a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18soc: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: I64e061017ee0b1202ce5482b26c7550e4cd0f0a7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18{drivers,superio}: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: Ia42c1f8559667e7711fac919df8bfbee8455e3cc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18nb/intel/haswell: Add server processor host bridge device IDIru Cai
The device ID is documented in "Intel Xeon Processor E3-1200 v3 Product Family Datasheet volume 2" section 2.2. Tested with ASRock H81M-HDS with Xeon E3-1271 v3. SeaBIOS payload can find the boot devices, and GRUB payload can boot Debian GNU/Linux on the SATA disk. Change-Id: I999391c9bbc6b39526ad7aec8a6d8fe1a9b5f921 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/30266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18mb/google/sarien/variants/arcada: Enable touchpad and touchscreenCasper Chang
Enable Elan touchpad and WACOM touchscreen BUG=b:119924134, b:120103010 BRANCH=master TEST=Verify touchpad and touchscreen on arcada work with this change. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I3dcdb4eeeb32766e64553d9e69e6b7e2b5ba85aa Reviewed-on: https://review.coreboot.org/c/30146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-18soc/braswell: ensure ACPI opregion restored on S3 with GOP initMatt DeVillier
The Intel GMA ACPI opregion address needs to be set on S3 resume, otherwise the Windows display driver fails to re-initialize correctly. Fix by ensuring the address is set correctly regardless of display init type used (GOP or VBIOS). Test: build/boot on google/edgar, ensure internal display functional following S3 resume under Windows 10. Change-Id: I471c44e8ba4514e4a2ddf6739109b759145598ed Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-18soc/baytrail: add vmx support via CPU_INTEL_COMMONMatt DeVillier
Mirrors addition to Braswell SoC in commit d3d0f07. Test: build/boot Windows 10 on Baytrail ChromeOS device, verify Windows shows virtualization as enabled. Change-Id: Ia1fafa73325814fed30b2ac91290b682dd8eab04 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-18mb/google/kahlee/liara: Document why IOMMU is disabledJonathan Neuschäfer
Commit d80884ea5a ("mb/google/kahlee: Disable IOMMU") disabled the IOMMU in all kahlee variants, but omitted the explaining comment only in liara's devicetree.cb. Copy this comment to liara. Change-Id: I564013a16217445003467e2a0579abd50597b205 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18arch/riscv: Don't hardcode CSR numbers anymoreJonathan Neuschäfer
They are hopefully stable enough by now. TEST=Building with for emulation/spike-riscv with BUILD_TIMELESS, with and without this patch, results in the same coreboot.rom. Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-18src/mb/google/*/Kconfig: Consistently use $(...) for variablesJonathan Neuschäfer
Using ${...} in some places is slightly confusing. Fixes: 395cbb4f97 ("mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree") Change-Id: Id0856a10d92786a41d45ca697945699f6f4c1f4c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18soc/amd/stoneyridge: Improve grammar through punctuationJonathan Neuschäfer
Change-Id: Iebae12f0b0397b5d4ad1fb09b5d9b847bc63c5d1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18Fix typos involving "the the"Jonathan Neuschäfer
Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-18mb/google/poppy/variants/nami: Add sku_ids for SyndraAmanda Huang
Sync'ing the sku_ids list in the master sku sheet. BUG=b:112876867 Change-Id: I658e8dc67679b5b528ab267861a1151f50e42414 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-17Revert "vendorcode/google/chromeos: Get ACPI pin from GPIO library"Duncan Laurie
This reverts commit 6217e9beff16d805ca833e79a2931bcdb3d02a44. Reason for revert: boards with CROS_GPIO_VIRTUAL selected in absence of dedicated recovery GPIO pin is die-ing now at gpio.c file line. 127 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ief20681b2a7ed4d15fd2d637ae034d54a96b2d6f Reviewed-on: https://review.coreboot.org/c/30278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-17mb/google/octopus/variants/fleex: Update Charger throttling settingsSumeet Pawnikar
Update dptf settings for Charger throttling. Also, update Power Limit1 minimum value setting from 4.5W to 3W. BUG=b:112448519 BRANCH=octopus TEST=Built and tested on Fleex system Change-Id: I8c2a796ff28254ebef28ed5745b344f925d6e649 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-12-17mb/google/octopus: Add custom SAR values for BobbaJustin TerAvest
Bobba would prefer to use different SAR values per sku-id for regulatory compliance. This commit uses the newly added interface for custom wifi SAR CBFS filenames. CQ-DEPEND=CL:*729429 BUG=b:120958726 BRANCH=octopus TEST=build Signed-off-by: Justin TerAvest <teravest@chromium.org> Change-Id: I354382d651d65d533459f0ca460ca6fd6de547fd Reviewed-on: https://review.coreboot.org/c/30223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-17vendorcode/google: support multiple SAR filenamesJustin TerAvest
Using a fixed filename only allows for one SAR configuration to be checked into CBFS. However, we have devices with shared firmware that would desire separate SAR configurations. This change allows boards to define a function to select one of multiple files stored in CBFS to be used. BUG=b:120958726 BRANCH=octopus TEST=build Signed-off-by: Justin TerAvest <teravest@chromium.org> Change-Id: Ib852aaaff39f1e9149fa43bf8dc25b2400737ea5 Reviewed-on: https://review.coreboot.org/c/30222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-17soc/intel/fsp_broadwell_de: Drop unused filesNico Huber
It seems they are not included anywhere, Jenkins? Change-Id: I629cdeb337fce381c69bd1ba0520e524ccdd90dd Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/26756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-17mb/google/poppy/variants/nami: perform PL2 setting for bard/ekkoRen Kuo
According to bard/ekko cpu types, PL2 need to set the values 1. KBL_U PL2 is 25w. 2. KBL_R PL2 is 29w. BUG=b:120874861 TEST=power on and check the DUT can boot up well Change-Id: I5f9d672c4244c363a7cfb362653663a065259fc0 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-17siemens/mc_apl4: Enable RTC RX6110SA on this mainboardUwe Poeche
Enaebl the RTC driver to be used on mc_apl4. Change-Id: Ib8d2a9f6b8cea47cd10db4dfcc59eec1b21c7993 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-12-17siemens/mc_apl4: Enable LVDS Display on mc_apl4Uwe Poeche
Enable PTN3460 chip initialization to get LVDS attached LCD working on mc_apl4. Change-Id: I3ccf5398f16831db321eba846d6b041daadf31dd Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-12-17siemens/mc_apl4: Add GPIO configurationUwe Poeche
Add GPIO configuration to match the hardware of mc_apl4. Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/30128 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-16superio/ite/it8772f: Fix typoElyes HAOUAS
Change-Id: I4fd7bc6a21909a7facd16799c0ef9296ed65a7b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-16superio/ite/it8721f/acpi: Remove unneeded white spaceElyes HAOUAS
Change-Id: Ie605ab8ff13332359aa44fff12acbadd23dcdf74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-15cpu/x86: Make mp_get_apic_id() function externally availableSubrata Banik
This function returns APIC id for respective cpu core. BUG=b:74436746 BRANCH=none TEST=mp_get_apic_id() can be accessed in other files now. Change-Id: I5c5eda8325f941ab84d8a3fe0dae64be71c44855 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/25620 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-15mb/{intel,google}/{icelake_rvp,dragonegg}: make use of cpu_get_cpuid() ↵Subrata Banik
helper function This patch replaces cpuid(1) references from icelake mainboard with x86 cpu common code library functions cpu_get_cpuid(). - cpu_get_cpuid() -> to get processor id (from cpuid.eax) Change-Id: Ia12d95d911dd6ee60a3a35937264fef668ad9e35 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-12-14cheza: Add board reset via Chrome ECJulius Werner
This patch implements board reset on the Cheza board. The real board reset used by the operating system uses the PMIC, but unfortunately the PMIC needs to be configured right for that to work. The PMIC configuration currently happens in the Qualcomm blob (QcLib) that is run from romstage, but vboot needs to be able to reboot during verstage already. Porting all the PMIC initialization code to run in the bootblock seems excessive (and at odds with the goal of doing as little as possible before verification), so we'll just do a little hack and ask the EC to perform a cold reset instead. For vboot purposes, this should work just as well. BUG=b:118501305 TEST=Hacked vboot code to call vboot_reboot(), confirmed that board reset and came back up as expected. Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/29849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-14soc/intel/cannonlake: Fix CNL-H GPIO pin mapDuncan Laurie
The GPIO pin map for CNL-H does not match with the OS expected pin numbers. This has been updated to match what is used by the Linux kernel pinctrl driver and the pad base has been set for the GPIO groups to match the sparse GPIO map used by the kernel. I do not have CNL-H hardware to test this so it is verified against the kernel driver at drivers/pinctrl/intel/pinctrl-cannonlake.c Change-Id: Ife7d3090d654b0b88c6911befa08bf6abd4f2ff9 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30134 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-14soc/intel/cannonlake: Add GPIO group pad base for ACPIDuncan Laurie
The GPIO drivers in Windows and Linux for the Cannonlake CPU have a sparse GPIO map and do not allocate pins contiguously. Each GPIO group is allocated as 32 pads regardless of whether the hardware actually has that many in the group. It appears this originated with a bug in Windows/UEFI and was carried over to Linux in order to work with existing firmware: https://lore.kernel.org/patchwork/patch/855244/ In order to support using ACPI GPIOs it is necessary for coreboot to be compatible with this implementation. The GPIO groups that are usable by the OS are declared with a pad base which is then used to compute the number for ACPI GPIOs. BUG=b:120686247 TEST=tested with write protect GPIO on sarien board. Before this change the ACPI pin number was 220 which did not correspond to the pin number in Linux. After this change the ACPI number is 303, which maps to the correct GPIO in Linux. Now the GPIO value reported by the kernel changes when the WP pin is toggled in hardware. Change-Id: I4f1a9e118d7e48f2445ccbb62a12a22e9a832c51 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-14vendorcode/google/chromeos: Get ACPI pin from GPIO libraryDuncan Laurie
If the generic GPIO library is enabled the code that generates the GPIO table in ACPI should attempt to get the GPIO pin value from the gpio_acpi_pin() function. BUG=b:120686247 TEST=Tested on Sarien board to ensure that GPIO pin exported by Chrome OS for the Write Protect signal is correct. Change-Id: I267694b576009f79bacac6eda5f32bbf51742d78 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-14soc/intel/common: Add support for GPIO group pad baseDuncan Laurie
In some situations the GPIO pad numbers used by the OS are not contiguous and coreboot must provide a way for ACPI to provide the expected GPIO number to the OS. To do this each GPIO group can now have a pad base value, which will be used as the starting pin number for this group and it is added to the relative pin number of this GPIO to compute the ACPI pin number for a particular GPIO. By default this change has no effect because the existing uses of INTEL_GPP() will set the pad base to PAD_BASE_NONE and the GPIO number is used as the ACPI pin number without translation. BUG=b:120686247 TEST=tested on a sarien(cannonlake) board Change-Id: I25f73df45ffae18c5721a00ca230a6b07c250bab Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30131 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-14mb/google/octopus: Override emmc DLL values for BobbaBora Guvendik
New emmc DLL values for Bobba. BUG=b:120561055 TEST=Boot to OS, chromeos-install, mmc_test Change-Id: I5a0d9587a91b3c71c042cd8ea360c816ea29fb91 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/30176 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-14google/grunt: Correct mismatch character hynix-H5AN8G6NAFR-UH.spd.hex SPD ↵Lucas Chen
file Module Part Number Correct Ram_ID=0b0000 SPD Module Part Number mismatch last alphabet 'C' to "H5AN8G6NAFR-UHC". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I4f4b83589ad6b53c0a24f2637f0fe8b92a1168e3 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-14google/grunt: Correct mismatch character hynix-H5ANAG6NAMR-UH.spd.hex SPD ↵Lucas Chen
file Module Part Number Correct to add Ram_ID=0b0001 SPD Module Part Number mismatch last alphabet 'C' to "H5ANAG6NAMR-UHC". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I4d320b2e10c4865456a9a9ccb400db5dd9256b3e Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30177 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-13cpuid: Add helper function for cpuid(1) functionsSubrata Banik
This patch introduces 3 helper function for cpuid(1) : 1. cpu_get_cpuid() -> to get processor id (from cpuid.eax) 2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx) 3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx) Above 3 helper functions are targeted to replace majority of cpuid(1) references. Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-13mb/google/hatch: Creating skeleton directories and filesShelley Chen
Creating skeleton files and directories in mainboard for the new Hatch board. This is to facilitate development for different parties involved. BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-12-12cheza: board-level GPIO supportT Michael Turney
Change-Id: I64e79904c7ad95091ea29d9f80444c4e3b493471 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/29298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-12mb/google/octopus/ampton: Fix the TRACKPAD_INT_ODL GPIO configurationKarthikeyan Ramasubramanian
Update the TRACKPAD_INT1_1V8_ODL GPIO configuration so that it acts as a wakeup source BUG=b:119598593 BRANCH=octopus TEST=Ensure that the system wakes up on trackpad events. Ensure that the suspend_stress_test runs successfully for 25 iterations. Change-Id: I28292682cf9c8037abb87d265e49a60139550db2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/30171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-12cheza: TPM/EC enable Kconfig in mainboardT Michael Turney
Change-Id: I15cfbbab15b940641c3952f2cfb4b11c37574816 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/29299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-11mb/google/octopus/variants/meep: Add 20ms reset delay for WACOM deviceTony Huang
Add reset delay in power resource to prevent bind to fail after unbind. BUG=b:119795901 BRANCH=master TEST=emerge-octopus coreboot, verified that WACOM touchscreen can re-bind successfully. Change-Id: Idcf02b1c931ed64951995403ec9ebe6b8f2db31d Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30099 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-11mb/google/sarien: Disable unused SATA portsLijian Zhao
Disable SATA port 0 and port 1 as that's not used as SATA on platform. BUG=N/A TEST=Build and boot up fine on google arcada board. Change-Id: I1b8801f7a0f9b7847b85d7c315fa0a2093b32f70 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-12-11mb/google/sarien: Disable PCH Gigabit LANLijian Zhao
There's no LAN connection on Arcada board, so disable PCH GBE. BUG=N/A Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-12-11mb/intel/x200: Add data.vbtArthur Heymans
There are 2 vendor BIOS's for the Lenovo X200 with the difference being the settings in the VBT blob to accommodate different backlight frequencies. Linux however sticks with the setting set by the firmware. Tested on Lenovo X200 with CCFL backlight. Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29904 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-11soc/intel/braswell/northcluster.c: Fix typoFrans Hendriks
Correct typo of 'resource' BUG=N/A TEST=N/A Change-Id: I79dde87007759b7cab92061df37fd3a19d5e3d1f Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/30125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-11mediatek/mt8183: Add DDR driver of tx rx window perbit cal partHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I4434897864993e254e1362416316470083351493 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/28842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-12-11mb/google/poppy/variants/nami: Modify SPD for hynix memory partRen Kuo
correct memory part name form hynix_dimm_H5ANAG6NCMR-VKC to hynix_dimm_H5AN4G6NAFR-UHC BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I0c33343eb1269919fba324333897805da1d1ff9b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-12-10mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parametersAamir Bohra
This implementation configures below parameters: 1. Enable SaGv, isclk. 2. Set Pcie rootport enable, Clock source usage and clkreq. 3. Configure SATA and LPSS controllers parameters. 4. Enable CNVI controller, configure Wifi end device under PCIE RP1. 5. Add TPM device support under GSPI1. Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-10mb/google/octopus: Update the PEN_EJECT GPIO configurationKarthikeyan Ramasubramanian
PEN_EJECT GPIOs are active high and also require an internal pull-up. Update the GPIO configuration appropriately. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools open on pen eject. Ensure that the system can enter S0ix and S3 states successfully when the pen is inserted. Ensure that the system wakes on Pen Eject. Ensure that the system does not enter S0ix and S3 states when the pen is placed in its holder. Ensure that the suspend_stress_test runs successfully for 25 iterations with the pen placed in its holder. Change-Id: Ibf9cb214a8ce7561efbb77a7e99d1e386cf064c3 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/30107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-10drivers/generic/gpio_keys: Add mechanism to configure GPE wake eventKarthikeyan Ramasubramanian
Add mechanism to configure GPE wake event which in turn can be used as ACPI Power Resources for Wake BRANCH=octopus BUG=b:117953118 TEST=Ensure that the wake GPE event is added to ACPI Power Resource for Wake. Change-Id: Iacc12b8636aaac98a8689a211cbe1dcfe306f342 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/30106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-10mb/google/sarien: Update GPIOs for next buildDuncan Laurie
Update the GPIOs for the next board build. Mostly minor changes but the polarity change on GPP_E8/RECOVERY on sarien will result in it booting to recovery every time unless using new hardware. For this reason the recovery mode GPIO that is passed to vboot is commented out for sarien. It is only used for testing and currently it is useful to have an image that works on both board versions. Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30062 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-10mb/google/sarien: Setup GPIOs again after FSP-SDuncan Laurie
Currently CoffeeLake FSP is incorrectly modifying GPIO pad configuration if specific UPD variables are not set as it expects. This affects the display-related SOC pads with the following UPD variables: UINT8 DdiPortBHpd; // GPP_E13 UINT8 DdiPortCHpd; // GPP_E14 UINT8 DdiPortDHpd; // GPP_E15 UINT8 DdiPortFHpd; // GPP_E16 UINT8 DdiPortBDdc; // GPP_E18/GPP_E19 UINT8 DdiPortCDdc; // GPP_E20/GPP_E21 UINT8 DdiPortDDdc; // GPP_E22/GPP_E23 UINT8 DdiPortFDdc; // GPP_H16/GPP_H17 Until FSP is fixed to not touch the pad configuration this workaround will reprogram the GPIO settings after FSP-S step so they are correct when the OS attempts to use them. This was found in CoffeLake FSP Gold release: https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg As well as the current top-of-tree for the FSP sources. BUG=b:120686247,chromium:913216 TEST=verify correct GPIO configuration for GPP_E group in the kernel Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-10soc/intel/cannonlake: Fix GPIO reportingDuncan Laurie
The kernel GPIO driver only expects some GPIO communities to be exported in the _CRS and it will not work correctly if the other communities are exported. CNL-LP: GPIO communities 0, 1, 4 CNL-H: GPIO communities 0, 1, 3, 4 Additionally one of the pin offset values was incorrect in GPIO community 1 for CNL-LP. This doesn't have any specific failure mode but it was found when auditing the GPIO code. Details of the kernel expected map can be found in the linux kernel at drivers/pinctrl/intel/pinctrl-cannonlake.c BUG=b:120686247 TEST=check /sys/kernel/debug/pinctrl/INT34BB:00/pins to ensure that pins >= 198 are not reading all zeros for the pin config registers. Change-Id: Ie1a2f3b9f9f4b24a9fc57e468dee50e99753912f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-09mb/google/octopus/phaser: Fix trackpad GPE wake configurationKarthikeyan Ramasubramanian
Synaptics Trackpad wake event is incorrectly routed to GPE0_DW2_02. The concerned GPIO is not connected and hence wont trigger a wakeup. Fix the GPE wake configuration for synaptics trackpad. BUG=b:120666158 BRANCH=octopus TEST=Ensure that the wake on trackpad works with Synaptics touch pad. Ensure that the system can enter S0ix successfully(run suspend_stress_test -c 25). Change-Id: I87b8c266266280f61700839d428e6f8938b0f72f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/30105 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-09mb/google/sarien: Enable LAN clock source usageLijian Zhao
FSP defined a special clock source usage 0x70 for PCH LAN device, update that to google sarien platform. BUG=b:120003760 TEST=Boot up into OS, ethernet able to be listed in ifconfig. Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-08google/grunt: Update micron-MT40A1G16KNR-075-E.spd.hex SPD file ModuleLucas Chen
Part Number Correct Ram_ID=0b0011 SPD Module Part Number to "MT40A1G16KNR-075:E" from "4ATS1G64HZ-2G6E1". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I9d582b3753de9a48865eb6eca7e4fbdb31b799ff Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-07google/grunt: Update hynix-H5AN8G6NAFR-UH.spd.hex SPD file Module PartLucas Chen
Number Correct Ram_ID=0b0000 SPD Module Part Number to "H5AN8G6NAFR-UH" from "HMA851S6AFR6N-UH". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I1f6e885638589a35334a9a8f905af4877c5d1f91 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-07google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file ModuleLucas Chen
Part Number Correct Ram_ID=0b0010 SPD Module Part Number to "MT40A512M16JY-083E:B" from "4ATF51264HZ-2G3B2". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-07mb/google/sarien: Enable ISH on arcada, disable on sarienDuncan Laurie
The Intel Sensor Hub was enabled on the wrong variant so this change moves the enable from sarien to arcada. Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 11:17:44 +0000