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On Intel Meteor Lake (MTL), PCIe CLK control register is accessed by
P2SB on IOE/SOC die.
So this patch does:
1. Enable PCIE_CLOCK_CONTROL_THROUGH_P2SB
2. Include pcie_clk.asl
3. Set the correct IOE_DIE_CLOCK_START for MTL-U/H.
BUG=b:288976547, b:289461604
TEST=Test on google/screebo and found the pcie clock is on/off properly
and sdcard PCIe port doesn't block S0ix with RTD3 cold enabled.
Change-Id: I6788ae766f36c9a0d4910fda1d6700f20ce73ea8
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76356
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In the older platform such as Raptor Lake (RPL), Tiger Lake (TGL), it
needs PMC IPC cmd to turn on/off the corresponding clock.
Now on Meteor Lake (MTL), it control pcie clock registers on P2SB on
IOE or SoC die.
BUG=b:288976547, b:289461604
TEST=Test on google/screebo and found the pcie clock is on/off properly
and sdcard pcie port doesn't block S0ix with RTD3 cold enabled.
Change-Id: Ia729444b561daafc2dca0ed86c797eb98ce1f165
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76347
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch includes the ioe_pcr.asl file as Intel Meteor Lake has
support for IOE die.
BUG=b:290856936
TEST=Able to build and boot google/rex.
Change-Id: Ia534dbc0db5e54e173da9cdf475a7eb2bfda9e2f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76410
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch implements APIs to access PCR registers from IOE die.
BUG=b:290856936
TEST=Able to build and boot google/rex.
Change-Id: Ief7a00c4e81048f87ee308e659faeba3fde4c9cd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76409
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch introduces a new config named IOE_PCR_BASE_ADDRESS to define
P2SB base address.
BUG=b:290856936
TEST=Able to build and boot google/rex.
Change-Id: I289358f9c53b557a397bd7186e6b7419c5d8c954
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76411
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch creates a helper library to migrate all the common P2SB
access routines. The PCH P2SB ACPI implementation will now rely on the
common library to perform PCR read/write operations. This will make the
code more modular and easier to maintain.
The helper library provides a single interface for accessing P2SB
registers. This makes it easier to port the code to different platforms,
for example: adding support for PS2B belongs to the IOE die for
Meteor Lake SoC generation.
BUG=b:290856936
TEST=Able to build and boot google/rex.
Change-Id: I0b2e7ea416ca7082f68d0b822ebb9a87025b4a8b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76408
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I73549b23bd1bfd4009e6467a5bdfeef7de81a0cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76272
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib649943e13b9b319297c4be68b7039b760ebd820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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In the JPEG decoder, use `bytes_per_line` instead of `width` for
address calculations, to allow for bigger framebuffers. When
calling jpeg_decode(), add an offset to the framebuffer address
so the picture gets centered.
Change-Id: I0174bdccfaad425e708a5fa50bcb28a1b98a23f7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Factor out all functions that use the indirect IO port based access to
the PM registers into a new compilation unit and only select it on
platforms that support this interface.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If9c059e450e2137f7e05441ab89c1f0e7077be9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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In all SoC pm_set_power_failure_state gets called either after a call to
enable_acpimmio_decode_pm04() or the ACPIMMIO mapping is already enabled
after reset on the SoC. This allows to use pm_read8 and pm_write8 that
use the ACPIMMIO mapping of the PM registers instead of pm_io_read8 and
pm_io_write8 which won't work on Phoenix and Glinda due to the IO ports
used on older generations to access to the PM registers not being
implemented any more.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0d0523d2c4920da41b3fb73cf62f22a60f1643a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Use pm_io_write8 instead of open coding the same functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d9397f2d85e48883f961adbbca0e1e71e825ce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: I5c5b125ac03e07a22bcc15ad2d34c62edf74ee04
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76452
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In all SoC lpc_early_init gets called either after a call to
enable_acpimmio_decode_pm04() or the ACPIMMIO mapping is already enabled
after reset on the SoC. This allows to use pm_read8 and pm_write8 that
use the ACPIMMIO mapping of the PM registers to set the PM_LPC_ENABLE
bit in the PM_LPC_GATING register instead of pm_io_read8 and
pm_io_write8 which won't work on Phoenix and Glinda due to the IO ports
used on older generations to access to the PM registers not being
implemented any more.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b31ec4e03a06796502c89e3c2cfaac2d41b0ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76461
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change i2c[0] parameter Thd:dat = 50ns;
Change i2c[1] parameter Thd:dat = 100ns;
BUG=b:287898252
BRANCH=none
TEST=Test success by EE.
Change-Id: Ibdbe4e17cf21c914b48fa6dc7d3eecf8218a2d8b
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76430
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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None of the platforms that used enable_acpimmio_decode_pm24 is in the
tree any more, so drop this function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iea345a825c4581bf2acb932692ebcad2a7a5b4ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The enable_acpimmio_decode_pm04 function uses the IO port based indirect
access of the PM register space. The PM_INDEX and PM_DATA registers
don't exist any more on Glinda, so the code shouldn't access those.
Since the PM_04_ACPIMMIO_DECODE_EN bit in the
ACPIMMIO_DECODE_REGISTER_04 register is 1 after reset, the ACPIMMIO
space is still accessible.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6bc0479ea4ea2b9fe3629a6e15940b31b2864d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The enable_acpimmio_decode_pm04 function uses the IO port based indirect
access of the PM register space. The PM_INDEX and PM_DATA registers
don't exist any more on Phoenix, so the code shouldn't access those.
Since the PM_04_ACPIMMIO_DECODE_EN bit in the
ACPIMMIO_DECODE_REGISTER_04 register is 1 after reset, the ACPIMMIO
space is still accessible.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia41f239b023edc094f5cbae63ed7c079649c74da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76437
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch disables early EC sync to avoid an idle delay (~3sec)
without a provision to notify the user about some critical task
in progress.
Doing EC sync at later stage allows us to notify using graphical msg
on screen to make user aware of the WIP task.
BUG=b:279944831
TEST=Able to perform EC sync from depthcharge on google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I03ed40827c50e75ceaaf94e30d675014ebf22dac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Disable DMI link ASPM which can degrade performance of overall system.
Desktop does not need to be concerned that much about idle power
consumption.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I60af9d2ab2913db449059e1e007999fa2f307f5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69826
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change touchscreen reset_gpio GPP_C01 -> GPP_D07;
Change touchscreen enable_gpio GPP_C00 -> GPP_B17.
BUG=b:289425753
BRANCH=none
TEST=Test success by EE.
Change-Id: I7be6a2b4e87126b281f138c819d2a0a5b1af5821
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Allows the new Infineon TPM chip used on Clevo laptops to be recognized.
Change-Id: I2ee31b787d80c0b9c24c748b1b28906a22a1dee7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Create the craaskov variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:290248526
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_CRAASKOV
Change-Id: I1d12f7c3d0ef7067f4530c1c69c560f9a83561f6
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
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Add karis supported memory parts in mem_parts_used.txt, generate
SPD id.
1. MICRON MT62F1G32D2DS-023 WT:B
2. HYNIX H9JCNNNBK3MLYR-N6E
3. HYNIX H58G56BK8BX068
4. SAMSUNG K3KL8L80CM-MGCT
BUG=b:291018417
TEST=Use part_id_gen to generate related settings
Change-Id: I87c2c4f59454dec84d29590ee91379c9fa60ddcf
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76443
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I01ae5a484287d2adb1516e1e4551b185b895fdde
Ref: RPL-UPH and RPL-U Refresh Platform Design Guide (#686872, rev 2.1)
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Id092b6dd9d42f2965801b0327a857a5a4945f793
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76288
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for AP initiated mode entry. The code flow has been
optimized as below -
Code flow when AP initiated mode entry is disabled:
+-------+
| Start |
+---+---+
|
|
+---------+---------+
|wait_for_connection|
| Is DP ALT mode |
| available? |
+---------+---------+
|
+--------------->-------+
Yes| No |
+---------+---------+ |
|Skip enter_dp_mode | |
+---------+---------+ |
| |
| |
+-----------+----------+ |
|wait_for_dp_mode_entry| |
| Is DP flag set? | |
+-----------+----------+ |
| |
+--------------->--------
Yes| No |
+-----------+----------+ |
| wait_for_hpd | |
| Is HPD_LVL flag set? | |
+-----------+----------+ |
| |
+--------------->--------
Yes| No |
+-----------+----------+ |
| Rest of the code | |
+-----------+----------+ |
| |
+---------------<-------+
|
+---+---+
| End |
+-------+
Code flow when AP initiated mode entry is enabled:
+-------+
| Start |
+---+---+
|
+------------+-----------+
|Skip wait_for_connection|
+------------+-----------+
|
+--------+-------+
| enter_dp_mode |
| Is USB device? |
+--------+-------+
|
+--------------->-------+
Yes| No |
+---------+---------+ |
| enter_dp_mode | |
| Send DP mode | |
| entry command | |
+---------+---------+ |
| |
+-----------+----------+ |
|wait_for_dp_mode_entry| |
| Is DP flag set? | |
| (If not, loop wait | |
| until timed out) | |
+-----------+----------+ |
| |
+--------------->--------
Yes| No |
+-----------+----------+ |
| wait_for_hpd | |
| Is HPD_LVL flag set? | |
| (If not, loop wait | |
| until timed out) | |
+-----------+----------+ |
| |
+--------------->--------
Yes| No |
+-----------+----------+ |
| Rest of the code | |
+-----------+----------+ |
| |
+---------------<-------+
|
+---+---+
| End |
+-------+
BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex
Time taken by enter_dp_mode / wait_for_dp+hpd / MultiPhaseSiInit
functions with this patch train:
1. When AP Mode entry is enabled
- With type-c display on C1 and SuzyQ on C0: 6.9ms / 420ms / 616ms
- With USB key on C1 and SuzyQ on C0 : 6.0ms / 505ms / 666ms
- Without any device on C1 and SuzyQ on C0 : 3.7ms / 0ms / 178ms
2. When AP Mode entry is disabled
- With type-c display on C1 and SuzyQ on C0: 1.7ms / 2.5ms / 213ms
- With USB key on C1 and SuzyQ on C0 : 0.9ms / 3.3ms / 177ms
- Without any device on C1 and SuzyQ on C0 : 0.8ms / 1.8ms / 165ms
Without this patch train, wait_for_hpd would cause a constant delay of
WAIT_FOR_HPD_TIMEOUT_MS (i.e. 3 seconds) per type-c port when there is
no device connected.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I514ccbdbaf905c49585dc00746d047554d7c7a58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Split wait-loop for DP and HPD flags as below -
- google_chromeec_wait_for_hpd
- google_chromeec_wait_for_dp_mode_entry
BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3e565d6134f6433930916071e94d56d92dc6cb06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76370
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Wait for DP/HPD flags only in AP initiated mode entry
BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5137c346fbf1edabc60a53e0978e32f54885c330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76369
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Skip TCSS `wait_for_connection` for AP initiated mode entry.
BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia04ff470961831237fe851f7ae3feaa5623d4b4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76368
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Skip TCSS `enter_dp_mode` command when there is no USB device detected
on the port.
BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ie6cd84cab3631596d4d7178dae2040e25c621f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Change-Id: Iad0244e798c03a26f755024453ecdd745e6286f3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76473
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iafc3735b6d903a4496828189db14b09d3c4d2081
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76432
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PRESERVE flag in the FMD file tells futility not to erase the
fmap partition when updating the firmware. Because of an issue on
myst right now, we want the RW_MRC_CACHE partition to be erased
when the firmware is updated.
BUG=b:290763369
TEST=None
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id586ae057b2fd6d513ddbba5e1284dea39467d95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76478
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Phoenix doesn't have an eMMC controller and those UPDs were carried over
from Picasso. The SoC's fsp_m_params.c didn't write to any of those
fields, so this doesn't change any behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie3640c1493a92c1effba3ce42103d022bd8399ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Because of the way that the CBFS filename is generated from the contents
of the microcode patch, if a duplicate microcode patch is included in
the build, the makefile would create a second copy of the name, which
doesn't work. This led to "odd" results where the other attributes of
the first copy were erased, causing cbfstool to fail. The cause of the
failure is not immediately obvious, and is a little difficult to track
down.
This patch causes an immediate failure and gives a reason as to the
cause of the issue.
When a failure is seen, this is the result:
File1: 3rdparty/amd_blobs/phoenix/psp/TypeId0x66_UcodePatch_PHXn4_A0.bin
File2: 3rdparty/amd_blobs/phoenix/psp/TypeId0x66_UcodePatch_PHX4_A0.bin
src/soc/amd/common/block/cpu/Makefile.inc:25: *** Error: The cbfs
filename "cpu_microcode_a740.bin" is used for both above files. Check
your microcode patches for duplicates.. Stop.
TEST=Now checked for both positive and negative failures.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3d34dc5585182545bdcbfa6370ebc34aa767cae2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76423
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Hook up microcode from 3rdparty repo for:
- 06-a5-03 (CPUID signature: 0xa0653)
- 06-a5-05 (CPUID signature: 0xa0655)
Fixes loading microcode on system76/bonw14.
Change-Id: Ie6789420926fe46fc61ea6773f02dc07dc2e9b5e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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System76 boards use the VBT data file, not the VGA optionrom.
Change-Id: Ie4100e09221ae4f301a621e7aac62e38ac04a444
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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There is a data abort in ABL when the memory training data is used from
APOB Cache. Disable APOB Cache until the cause is identified. The
downside of this change is that the memory training happens in every
boot cycle.
BUG=b:290763369
TEST=Build BIOS image and boot to OS in Myst. Trigger a reboot from AP
console and ensure that the system boots to OS.
Change-Id: I20f4f40cdaac68bca6e121e3a238d13fe80d0d3c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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The dxio_port_param_type enum was copied over from Cezanne, but the enum
on the AGESA/FSP side changed between the generations. Add a TODO as a
reminder that this needs to be updated.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8063ab00a508b045265bab73197c8ca117622800
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76448
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the proper dxio_link_hotplug_type enum values for the link_hotplug
field in the DXIO descriptors to replace the magic values in the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieb1513737e6022a668287dc80a39d96cda2b18d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76439
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the dxio_link_hotplug_type enum definition for the link_hotplug
field in the DXIO descriptor struct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieeb3e3edaed2c689707edc4df7d25c777005fde2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The dxio_port_param_type enum was copied over from Cezanne to Mendocino
to Phoenix, but the enum on the AGESA/FSP side changed between the
generations. Update the definition to match the definition used in the
Phoenix FSP.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3c87fdc8bf0849d797c2af74c1d1495c7d85019f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76447
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The dxio_port_param_type enum was copied over from Cezanne to Mendocino,
but the enum on the AGESA/FSP side changed between the two generations.
Update the definition to match the definition used in the Mendocino FSP.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie4c4d7e4e3eaf7af9a43007363135412633c7440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76446
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic6f42053b5303151906360d8512b9d63dd297854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76249
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie585a66118c6bd1951bd004bbccbed0ee0ba9f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76248
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The OxPCIe952 serial cards currently fails after entering
postcar, since the state of oxpcie_present is not maintained
from previous stage.
As a quick work-around test the expected UART register space
to see if anyone decodes the address.
Change-Id: I5601034be6e413616fb3433c894fb008a3e02138
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74597
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change `CBFS_SIZE` to match the actual BIOS region size, as specified in
the FIT XML config.
Fixes building with `VALIDATE_INTEL_DESCRIPTOR` selected.
Change-Id: I91a46b3ed6cc3161df27eed19d8cdf2820e90d7e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76326
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It moves cr50_plat_irq_status() to common code and adds Kconfig
option to specify GPIO used for interrupt.
BUG=b:277787305
TEST=Build all affected platform and confirm using right GPIO
number. Tested on Skyrim.
Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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The file for Mendocino and Phoenix still used Cezanne in the comment and
from the file it's already clear to which SoC generation this belongs,
so just drop the SoC name from the comment.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I73e8b01e46904578226bb64e5e4659016c491880
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76440
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Adder Workstation 3 (addw3) is a Raptor Lake-HX board.
Tested with a custom TianoCore UefiPayloadPkg.
Working:
- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots with 5200 MT/s memory
- Both M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7
Not working:
- Discrete/Hybrid graphics
- Thunderbolt
Change-Id: I165a434fe18f8c0aac49cb872bb87f98551d8f2c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested by booting System76 Adder WS 3 (addw3) and Serval WS 13 (serw13)
to edk2 payload and then OS.
Ref: Intel Raptor Lake EDS, Volume 1 (#640555, rev. 2.8)
Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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coreboot logs the error below, since the value of hporch is too small. Increasing hbl from 80 to 174, and hso from 40 to 72 to revise the HBP(Horizontal Back Porch) and HFP(Horizontal Front Porch). After revising this, the actual measurement frame rate is 60.1Hz.
[ERROR]HFP plus HBP is not greater than d_phy, the panel may not work
properly.
BUG=b:284812193
TEST=cbmem -c | grep "ERROR" and measure frame rate
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I7de5984ce8aec12d8ebe292974e05776835330d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76218
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates the MemInfoHob header file as per Meteor Lake
version 3251.81.
Changes include:
1. Drop DimmDFE structure variable
2. Drop unused macro MAX_COPY_DIMM_DFE_TAPS
BUG=b:290898626
TEST=Able to build and boot google/rex.
w/o this patch:
cbmem -c -1 | grep DIMM
[ERROR] No DIMMs found
w/ this patch:
cbmem -c -1 | grep DIMM
[DEBUG] 8 DIMMs found
Change-Id: I8eed410831399bb4835244f48c14d5ed9e701e68
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76433
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Per the suggestion in CB:76218, print actual values to the error
messages, which may be helpful for debugging.
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Id3a7a8c76b6ad15e7cf71225d8529f3e034935ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76442
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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When set to 1, the link_compliance_mode element of the DXIO port
descriptor will cause the corresponding PCIe port to not be trained but
to output a compliance testing pattern instead. Update the comment to
point out that this is only a testing mode.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaabb16c51a0c08391cd2d63b8064c524a748ccb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76441
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi.
Meteor Lake rex platform does not wake up from low power state by
bluetooth keyboard and mouse properly. It is identified that IO Standby
State needs to be configured as masked to function properly for CNVi.
BUG=b:286803481
TEST=Make screebo suspend to s0ix state and press a key from
bluetooth keyboard. Check the platform wakes up properly from s0ix.
Change-Id: I7fd342e52fa0f9126eab4c857a5adc04c26e49c6
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76406
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PCR (Private Configuration Register) is applicable to access the
P2SB register space starting with the Intel SkyLake generation of SoC.
Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside
the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in
SoC die (same as PCH die for U/H SoC) and another in IOE die.
This patch renames pcr.asl to pch_pcr.asl to reflect the actual source
of the P2SB IP in the die (i.e., SoC die or PCH die).
BUG=b:290856936
TEST=Able to build and boot google/rex.
Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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GMBus is an I2C compatible link on Intel IGPUs. Most non-Linux OS's
don't support accessing this ordinarily, so a custom driver is
needed with a bit of ACPI hackery. Reserve 2 IDs from the
coreboot namespace so that the 2 devices required can be populated
in Windows device manager
Change-Id: I389612441e96ce2fc5e006051e523661953eba6e
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4769f79c67c372e11bb267de3acec0920d7ab0d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80c8a1b58e8102ed11e22b74f30750d5a6c4eae4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76283
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Pujjo support WWAN EM060 device, use FW_CONFIG to handle the
power on sequence.
BUG=b:290709711
TEST=Build and check WWAN EM060 power on sequence.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I66800c75274e8e1e55d4314c82b7fcdf2a4477bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76403
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With the latest hardware revision, the polarity of GPP_B5 has been
changed. For a full-populated DRAM configuration, the input signal is
now connected to 3.3 V and for a half-populated configuration it is
connected to ground.
BUG=none
TEST=Use different populated mainboards and check coreboot log
GPP_B5 = 0:
[INFO ] meminit_channels: DRAM half-populated
[DEBUG] 1 DIMMs found
GPP_B5 = 1:
[DEBUG] 2 DIMMs found
Change-Id: Iaa3a63fa52c802d8f5d8c6cc11dd6edfac117e88
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76434
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify reset_delay_ms from 300ms to 6ms for ELAN EKTH7D18.
BUG=b:285999032
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and touchscreen is workable.
Change-Id: Iffcddbe7735b7a837887dec68e1270c2af5f4556
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76417
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Disable scalability tracking for autonomous frequency control in
order to improve power and performance.
BUG=b:280021171
TEST=Boot to OS on brya0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: If71ee5374c67611b32691bbec4effdf828b3e566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74723
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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Hook the newly exposed EnableHwpScalabilityTracking UPD up so that
boards can configure is via devicetree.
BUG=b:280021171
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I4c8845c445d46caa30a0245386ab9cd690d2623f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74722
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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Hook the newly exposed DisableSagvReorder UPD up so that
boards can configure is via devicetree.
BUG=b:268546941
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I89235d9384b67f03e68425aadd3458e1c77ff555
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Disable re-ordering SaGv point on warm reset so that most
performant SaGv point is picked after memory training and
boot time is reduced.
BUG=b:268546941
TEST=Observe boot time improvement with these two UPDs set
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I44a1c054d52bb8585a320bb8a52a8f137e639804
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74721
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable upd to reduce size of the memory test.
BUG=b:268546941
TEST=Observe boot time improvement with these two UPDs set
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I95c7d8503596c2712d7abe123ed1f911ac4abacf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Hook the newly exposed LowerBasicMemTestSize UPD up so that
boards can configure is via devicetree.
BUG=b:268546941
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib813e9f3b7419a3cb54b4e176dcc5cc74a783dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74718
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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The headers added are generated as per FSP v4221.00
BUG=b:290038558
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I23f6e1e4baa39883475cd93fa6aabcec4e7152cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76147
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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test: Warm reboot from Windows 11 w/ Samsung 980 Pro on Banshee
Verify memory type detected properly and following boot works
Change-Id: Iad0a2024bd0ef39f6ab57ff7a6e6aa651d7882a6
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Avoid enabling SIO UART to prevent conflicts with BMC console; utilize VUART0 instead.
TEST=Build for sbp1 & make sure coreboot logs do not spill into BMC
console. Also made sure coreboot logs are accessible via VUART.
Change-Id: I2d4bbd74bb7d37b74378650dd569bca7fa13c29b
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76396
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Set coreboot ready gpio. This gpio is used to indicate to BMC of BIOS
completion.
Change-Id: Iaed8bec12e593cf1687d973765b0117bdc115cb8
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76404
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables PCH to CPU energy report feature which can be used
by Intel Telemetry Driver.
BUG=b:269563588
TEST=Able to build and boot google/rex and perform below check to ensure
the energy reporting is correct
w/o this cl:
# lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXX0000
w/ this cl:
#lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXXfc004
Change-Id: I9bd4625ea311a05071878aaec68433a1ba018c0d
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76353
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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Only A step ADL-S CPUs were added to CPU table for MP init. Add
the remaining ADL-S CPUs to the table.
TEST=Boot MSI PRO Z690-A with C step i5-12600K and observe coreboot
no longer uses generic CPU ops.
Change-Id: I3692a3f089ca23af860bd1c8e3c29fee9d9234c9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76204
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: I68416e1633c3d67070790a9db2cd9a13a8981042
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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In newer ADL/RPL PCH EDS 619362 revision 2.1 the ESPI ID 0x7A8A
belongs to the W790 chipset. Earlier revisions had the chipset with
ID 0x7A8A named W685, which was probably just a temporary name.
Change the naming throughout the tree to W790, which is the real
existing chipset.
Change-Id: I87603298d655e9bf898b34acdd5b403f5affaee3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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CPUID is the same for Alder Lake and Raptor Lake S and HX variants.
To reduce the confusion and concerns how to name the macros, remove
the suffixes from macros and platform reporting strings. Thankfully
the stepping names are unique across mobile (P suffixed) and desktop
(S and HX suffixed) SKUs. Distinguishing the S from HX is possible via
host bridge PCI ID.
Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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Add PCI IDs, default VR values and power limits for Raptor Lake S
CPUs. Based on docs 639116 and 640555.
TEST=Tested on a MSI PRO Z690-A (ms7d25) with i9-13900K with Ubuntu
22.10 and LinuxBoot (Linux + u-root). Also tested on MSI PRO Z790-P
with i5-13600K (UEFI Payload) usign RPL-S IoT FSP and Ubuntu 22.04.
Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155
Signed-off-by: Max Fritz <antischmock@googlemail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69798
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
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The static function read_space_firmware() is used only once, so merge it
into antirollback_read_space_firmware(). Also change a debug log to
error.
BUG=none
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I8abcb8b90e82c3e1b01a2144070a5fde6fe7157f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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The CB:76219 removed mtk_i2c_bus_init() from tps65132s_setup(), so
we should initialize I2C bus for TPS65132 in mainboard now.
BUG=None
TEST=./util/abuild/abuild -t google/geralt -a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Iacf78221d2416f41467c709402b7e02e03dc5fc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Some of the microcode update files listed in the Makefile are redundant:
* 06-97-02 is exactly the same as 06-97-05
* 06-9a-03 is completely contained in 06-9a-04 (at offset 0x1c400)
So drop these files. This saves us about 200KiB CBFS space in each case.
Change-Id: Idfcab1de26ea4712295c1d22790bab3a73c17f93
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I62f34a12bc5c4807638ddcb39fa5e450d99511fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76277
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iad8b7c705d5053700850065f90314444904b5b54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76289
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Idd623e99ee20ad94e493c8560cfdac9f7baaf890
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76281
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I852d6daebdcb8461c18e7c0eaf1c54ad7c59c0c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If7fe96220ce5b13f5541e25935afd0c681ff40f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76286
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5728dc144b0d04a92a1e0a4b9abbe17ef0a06e41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76282
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie44518988e999794fba35f41075ff62e82663d70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76285
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I40b8482f41e8fece55fd60fec7ec3f63f83bd030
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76280
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reserving resources needs to have inclusive region ends.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I88a09d205ef9699de7f18e0a2f33c9ad3ce9fa36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76279
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
- Don't have resources overlap
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ia8562660cf69d188b0cab4869aa3190f014dbfdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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There is no PCH FIVR participant on MTL and we should remove it
in Rex.
TEST=compile ok and make sure there no TPCH device in acpi
BUG=b:290322310
Change-Id: Icf4be86da3f3cb9b1f0a3f2586b029a533c3e6a9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76402
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5c6dcbc8ed79b79ee097c7a14fe14ed87af33c2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I502eeb39c05bd4d00b01976c96884636baf3030c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I61ae378867f8c0d9e86092ebe8deec53800c4717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch drops the unnecessary alignment of 64 bytes that was
introduced when implementing the split Intel microcode packing logic
into CBFS.
- The 16-byte alignment that is already used for Intel microcode is
sufficient.
- Removes unnecessary alignment check of 64 bytes against an AMD
platform specific config.
TEST=Able to build and boot google/rex without any functional
impact.
Change-Id: Icc44e9511e321592de7ab8d1346103d0a9951c9b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76397
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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During the ACPI dump of the System Resource Affinity Table (SRAT), it
was noticed that the reserved field within the Memory Affinity structure
contained a non-zero value. This commit addresses the issue by
performing a memset to zero on the reserved field, ensuring the
avoidance of any potential problems arising from garbage values.
TEST= Build for ibm/sbp1 & make sure SRAT Memory Affinity entries
reserved fields read zeroes
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I4ba697a6bd59054e74c84b98f3d9b517d333a5d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75417
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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for saving boot time, change ramstage compression from LZMA to LZ4.
Boot time saving is around 35ms (30-37ms) while SPI size impact is 230KB.
For detail, refer below.
Existing: LZMA(55.6 ms)
8:starting to load ramstage 894,519 (0)
15:starting LZMA decompress (ignore for x86) 903,556 (9,036)
16:finished LZMA decompress (ignore for x86) 949,997 (46,441)
9:finished loading ramstage 950,179 (182)
Changed: LZ4(17.8ms)
8:starting to load ramstage 900,876 (0)
17:starting LZ4 decompress (ignore for x86) 917,650 (16,774)
18:finished LZ4 decompress (ignore for x86) 918,690 (1,040)
9:finished loading ramstage 918,849 (158)
Size impact (73KB * 3 = 219KB)
fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed)
fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed)
BUG=b:286930648
TEST= Boot to OS and check boot time
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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