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2007-06-14Fix the static device tree of the ASI MB-5BLMP target. This was broken inUwe Hermann
more than just one way. This version should be (more) correct. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14his patch fixes the CAS map for -.5 and -1 CAS settings. The -.5 setting ↵Marc Jones
should only shift the mask one bit, not two. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14Small bugfix in i82801xx_lpc.c.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14Add initial support for the Intel 82810 northbridge.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14This patch adds support for the Intel i82810 northbridge and various i82801xxCorey Osgood
southbridges, along with the Asus MEW-VM. With this, my machine attempts to boot linux, but does so very slowly and fails during the boot process, probably because of the irq tables. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-12Add the AMD DB800 (AKA Salsa) mainboard.Marc Jones
The DB800 is the AMD LX Reference Design Kit platform. For details see: http://www.amd.com/geodelxdb800 Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-07Minor tweaks in the 440BX RAM init code (trivial).Uwe Hermann
Still hardcoded for Tyan S1846. This slightly increases performance, but it's still pretty horrible. Some RAM settings are causing a dramatically slow system (confirmed by comparing memtest performance results of the proprietary BIOS and our code). Haven't found the problem, yet. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-07Add support for the IEI JUKI-511P and IEI ROCKY-512 half-size boards.Nikolay Petukhov
Both are very similar, thus both use the JUKI-511P target. Linux with patches from Juergen Beisert (http://www.linuxbios.org/pipermail/linuxbios/2007-May/020932.html) boots and work fine (ide, usb, ethernet, serial, keyboard and sound work normally). Problems: - Filo loads a bzImage only from ide0 (ide1 doesn't work yet). - Video doesn't work, yet. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-06Add support for the Winbond W83977F-A Super I/O.Nikolay Petukhov
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03Tyan S1846: Minor fixes in static device tree (trivial):Uwe Hermann
- Linux booted with the proprietary BIOS reports 2e.f as PS/2 mouse in the output of 'lspnp -v'. - The floppy on 2e.f was a typo, should have been 2e.e from the beginning. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03Fix the static device tree of the Tyan S1846. Especially theUwe Hermann
Super I/O part was incorrect. Also, add ide0_enable/ide1_enable variables, and enable both the primary and secondary IDE interface per default. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03Intel 82371EB: Some code simplifications (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-02The UART disable code was causing a hang and was worked around with aMarc Jones
return that skipped the disable code. This patch removes the return and fixes the UART disable code. The problem was that the disable code was ORing bits into the Legacy_IO MSR causing issues with the LPC SIOs init code that would manifest as a hang because the IO would not be decoded correctly. ANDing to clear the bits fixes the issue. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29Drop duplicate 82371AB device IDs (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29Use the common LinuxBIOS license header format.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29Intel 82371EB: Add IDE init support.Uwe Hermann
In a mainboard's Config.lb file you can configure whether the primary and/or secondary IDE interfaces shall be enabled. Also, various fixups in the rest of the southbridge code, most notably the early SMBus code, plus some documentation improvements. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey_osgood@verizon.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-28Lower the RAM init delays we use on the Intel 440BX.Uwe Hermann
As per JEDEC, we should wait 200us until voltages and clocks are stable. Then apply NOPs for 200 clock cycles (for simplicity we use 200us here). All other delays are so low that we get away with just waiting 1us. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-27Various 440BX and Tyan S1846 related minor changes and fixes (trivial):Uwe Hermann
- Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's available on all boards, regardless of what DIMMs you use. Tested on the Tyan S1846, works fine. - Properly set the PAM registers to allow the region from 768 KB - 1 MB to be used as normal RAM (required for the above). - Document all of this properly. Add/improve other documentation, too. - Simplify and document code in northbridge.c. - Cosmetics and coding style. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-27Init for the Intel 82371EB southbridge: make all ROM/BIOS regionsUwe Hermann
accessible (but not writable), so that reading/loading a payload from that area can work (for instance). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-26This patch fixes the processor name string for Rev F. CPUs.Sven Kapferer
It moves the complete naming functionality to src/cpu/amd/model_fxx/processor_name.c. The current code sets the processor name string twice for Rev. F CPUs. In src/cpu/amd/model_fxx/model_fxx_init.c the function amd_set_name_string_f is called first. Several lines later init_processor_name is called which doesn't recognize newer CPUs and actually programs incorrect values, thus overwriting the previously set CPU name. For example, this resulted in identifying an Opteron 2218 as a Turion processor. This patch removes the amd_set_name_string_f function from src/cpu/amd/model_fxx/model_fxx_init.c and adds support for Rev. F CPUs to src/cpu/amd/model_fxx/processor_name.c as described in the Revision Guide for AMD NPT Family 0Fh Processors, AMD Document ID 33610 Rev 3.00, October 2006. Signed-off-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24Add initial support for the ASUS A8N-E board.Philipp Degler
Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24Drop the src/southbridge/amd/cs5536_lx directory and its contents, asUwe Hermann
the new src/southbridge/amd/cs5536 code completely replaces it. The Artecgroup dbe61 board currently uses it, but that is broken anyway at the moment. A fix to use the new CS5536 code for it is being worked on. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24Various IT8712F fixes:Philipp Degler
- Add missing IT8712F_GPIO definition. - Add functions for entering and exiting MB PnP mode. - Add some more device init lines to pnp_dev_info[]. Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24Small patch that adds an error message in case the keyboard selftest fails.Philipp Degler
Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-22reverting 2683, NAK by YhLu, patch not necessary.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-22Add missing license headers, minor cosmetic fixes in existing headers.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21Drop the (non-working, almost non-existant) support forUwe Hermann
- the Transmeta TM5800 northbridge - the Densitron DPX114 mainboard (the only one using the TM5800) Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21Drop romcc related stuff, as this board only uses CAR.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21The Gigabyte m57sli-s4 board supports Rev. F CPUs.Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21fix some typos, clarify comments and drop dead code (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21This is the last remainder from Yinghai's mega patch. It fixes issues withYinghai Lu
devices conflicting with the northbridge devices on PCI bus 0. Signed-off-by: Yinghai Lu <yinghailu@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-20Add additional CPU device ID:Jeremy Jackson
CPU: vendor AMD device 30ff2 CPU: family 0f, model 3f, stepping 02 All I know is this makes it boot when it didn't before, YMMV. Signed-off-by: Jeremy Jackson <jerj@coplanar.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-19Fix typos (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-19Minor cosmetics (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-19Initialize the fans on the adt7463 chip to be dynamically regulated by theWard Vandewege
hardware, rather than always on at full speed. Set temperature treshold values to safe defaults, rather than the not-so-safe power-on defaults. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Yinghai Lu <yinghailu@gmail.com> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-17Whitespace fixes (trivial).Corey Osgood
Signed-off-by: Corey Osgood <corey_osgood@verizon.net> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-16Cosmetic changes: push includes to top of file in chip.h files.Roger Zauner
Signed-off-by: Roger Zauner <roger@eskimo.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15Simplify spd_read_byte() functions (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15Various cosmetic fixes (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15IEI NOVA-4899R: Add missing license headers.Luis Correia
Signed-off-by: Luis Correia <luis.f.correia@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15IEI NOVA-4899R: Correctly configure Super I/O PNP devices.Luis Correia
Signed-off-by: Luis Correia <luis.f.correia@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15IEI NOVA-4899R: Fix incorrect irq_tables.c.Luis Correia
Signed-off-by: Luis Correia <luis.f.correia@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15IEI NOVA-4899R: Drop unused files.Luis Correia
Signed-off-by: Luis Correia <luis.f.correia@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-14AMD Norwich: minor cosmetic fixes and drop dead code (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-11Clean up whitespace in preparation for another patch to fix fan control.Ward Vandewege
This is nothing more than the result of running indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs adm1027.c Signed-off-by: Ward Vandewege <ward@gnu.org> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-11The Super I/O needs 0x87 sent twice to 0x2e (or 0x4e) to enable extendedRoger Zauner
function (power-on strapping). Although this is already done in superio.c, it's not being done when w83627thf_early_serial.c is executed. As such, no console_init() without it. Signed-off-by: Roger Zauner <roger@eskimo.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fixup the 440BX northbridge.c (self-ack as this wasn't working anyway).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This fix properly hides the UDC and OTG PCI headers when the cs5536 isMarc Jones
setup as the host on USB port4. In client mode the headers remain available. Also fixes an outb to 0x80 to use the post_code() function. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Changes by Richard Smith and Peter Stuge from the LinuxBIOS symposium 2006.Peter Stuge
With CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0, 1 million outb():s are used for timer calibration, which takes about one second. All EPIA-M boards have timer2 so we use it to boot faster. Only some EPIA boards have the Nehemiah CPU with timer2 so we default to IO calibration but add the TSC options so that they can be set in Config.lb. src/mainboard/via/epia*/reset.c is dead code (entire file within #if 0) so we set HAVE_HARD_RESET=0 for both boards. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This patch cleans up and clarifies Geode source code comments.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This patch cleans up \r left in the print strings. They were required for ↵Marc Jones
romcc code but no longer needed in cache as ram code. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This patch updates the PCI ID of the Geode IDE device to include the revision.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fixed a bug within the 440BX RAM size calculation. Since the DRB valuesCeri Coburn
on the 440BX are 8 MB units we need to shift left by 13 to get it into KB. Signed-off-by: Ceri Coburn <ceri.coburn@gmail.com> Signed-off-by: Roger Zauner <roger@eskimo.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10indent is by no means as harmless as one might think ;-)Stefan Reinauer
trivial fix. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10The attached patch sets the MA map type correctly for all DIMMs I wasAlex Mauer
able to find to test with the Epia. Signed-off-by: Alex Mauer <hawke@hawkesnest.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This patch removes auto.c from the Norwich mainboard directory. Marc Jones
Acked-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fix the indent and whitespace to match LinuxBIOS standardsJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fix the indent and whitespace to match LinuxBIOS standardsJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fix the indent and whitespace to match LinuxBIOS standardsJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fix the indent and whitespace to match LinuxBIOS standardsJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Add missing licenses to several of the files.Jordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Add missing licenses to several of the files.Jordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09The superio needs 0x87 sent twice to 0x3f0 to enable extended functionRoger Zauner
(power-on strapping). Although this is already done in superio.c, it's not being done when w83977tf_early_serial.c is executed. As such, no console_init() without it. Signed-off-by: Roger Zauner <roger@eskimo.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09Uncomment compression config variables. This should fix the abuildUwe Hermann
problems with the asi/mb_5bmlp (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09This patch uses auto.c from Uwe's tyan s1846 for both boards, with someCorey Osgood
minor changes, to bring them up to par. It also should remove (but might just clean out) the irq_tables.c from both boards, because they were just copied from Via Epia to begin with, and weren't usable. As far as I can tell, these are the only changes needed to the targets for now, aside from fixups to reset.c when the time comes. Both have been build tested, but not checked on hardware since I don't have it. I have left Uwe as the copyright holder since the only changes I've made are trivial. Signed-off-by: Corey Osgood <corey_osgood@verizon.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09Add initial support for the ASI/BCom MB-5BLMP mainboard, as used inUwe Hermann
the IGEL Winnet III thin client. It boots a Linux kernel, but there are some problems. The login prompt is never reached, it simply hangs at some point. One possible reason is the IRQ table, which needs fixing. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-08New irq table, and a correct setting forRonald G. Minnich
the 5c register in the southbridge so that interrupts are routed correctly. With this patch, ethernet works quite well. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-07Add missing licenses to several of the files.Jordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-05This is the final patch to enable the msm800sev to build. This patchRonald G. Minnich
adds a symbol to the model_lx/cache_as_ram.inc, and modifies some files in the mainboard directory. This patch has been tested but there is a remaining problem which I am tracking down. Expect one more patch to "get it all working". Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-05With this patch, the msm800sev runs FILO and boots a kernel.Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> -This line, and those below, will be ignored-- M cs5536.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch as a cache_as_ram_auto.c for the msm800sev.Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04Drop src/mainboard/amd/norwich/debug.c as it is not used.Uwe Hermann
I'm self-acking as this is pretty trivial. I tested both a normal build and an abuild-run, and nothing breaks. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04Some minor fixes in it8716f/superio.c:Uwe Hermann
- Add Ward Vandewege <ward@gnu.org> as copyright holder. - Use explicit 'uint16_t' instead of 'unsigned long'. - Minor cosmetics. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04patch to fix the IDE configuration on EPIA boards. At some point thisBen Hewson
broke and stopped FILO from being able to boot. The fix is a simple one line change plus a comment to src/mainboard/via/epia/auto.c to write to the IDE configuration register 0x42 . This has always been done here, however at some point something broke it. The same register was also being set correctly in ide_init(), however for some reason this does not work. Possibly the register needs to be set before the IDE peripheral is enabled or maybe it is a timing issue. The section of code in ide_init() ( src/southbridge/via/vt8231/vt8231_ide.c ) that does write to register 0x42 has been commented out as it is superfluous and I have added a comment to indicate the reason, should someone at a future date wonder why. I have also changed the default COM speed from 19200 to 115200 in src/mainboard/via/epia/Options.lb There has been mention before about the EPIA board not being able to use 115200 but I have seen no such problems with my board. Signed-off-by: Ben Hewson <ben@hewson-venieri.com> This patch worked for me and allowed me to boot Debian kernel 2.5.16-4-486 on an epia 800 mhz system. It is able to consistently get through the initialization and start init now. However, after that it crashes at various points in the boot process. Acked-by: Alex Mauer <hawke@hawkesnest.net> Note from comitter: I am commiting this, although: 1. it's not the exact right way to fix it up, the chip.h for the sb should change 2. Alex reports problems, which are almost certainly memory issues. But it is as close as we've gotten. I can't test it. Ron Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This repairs the other Geode mainboards so they'll build with the newMarc Jones
Geode changes. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch re-implements support for the CS5536 companion chip for theMarc Jones
AMD GX and LX processors. This aguments the previous code, which was very specific to the OLPC platform with general purpose support and better integration with the VSA and CPUs. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch adds support for the northbridge integrated into the AMDMarc Jones
Geode LX platform, including memory and graphics. (rediffed for whitespace) Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch adds support for the AMD Norwich development platformMarc Jones
based on the Geode LX processor. The Norwich is the canonical Geode reference, and will server as a good basis for other Geode based platforms. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch adds support for the AMD Geode LX CPU. (rediffed)Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04Cosmetics (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03Add missing license headers to some Geode LX related files.Jordan Crouse
The following original authors agreed to the license: - Ronald G. Minnich <rminnich@gmail.com> - Indrek Kruusa <indrek.kruusa@artecdesign.ee> - Stefan Reinauer <stepan@coresystems.de> - Andrei Birjukov <andrei.birjukov@artecdesign.ee> Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB,Uwe Hermann
as that is not RAM but used for other stuff. First try at PCI init added to src/mainboard/tyan/s1846/Config.lb. Use a real payload (FILO) per default now. Note: this cannot boot a payload, yet, but it gets a lot further now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-30Fix typo: s/PRINT_DEBUG_/PRINT_DEBUG/ (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-27Add fan control support to ITE IT8716F.Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-26Activate EC for access to fan speeds and temperature sensors.Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-24trivial: fix filename in comment. Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-22Add explicit license headers to all files in src/device.Uwe Hermann
For files derived from the Linux kernel we merely add a small header which states the origin of the file and the copyright owners of the modifications to the file. We know all files from Linux are licensed under the GPLv2. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-22Use __PAYLOAD__ instead of PAYLOAD as replacement template for abuild.Uwe Hermann
Comment out code which currently doesn't compile. Needs fixing later. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-14This patch makes a some elf debugging information available at log levelStefan Reinauer
debug instead of spew. (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12On behalf of AMD:Yinghai Lu
Drop AMD prototype mainboards that were for internal testing & validation use only. Note: These boards could never be purchased. No reasons to worry. Questions welcome via private mail. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12add uses CONFIG_COMPRESSED_PAYLOAD_* to allow building the board inStefan Reinauer
abuild with a payload. Trivial Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12Fix two boards broken by the large patches of late.Peter Stuge
artecgroup/dbe61 Add CONFIG_COMPRESSED_PAYLOAD_NRV2B to Options.lb since it's used in Config.lb. Change default for CONFIG_PCI_ROM_RUN to 1 so VGA ROM can run. technologic/ts5300 Removed CONFIG_CONSOLE_VGA, the embedded board has no VGA without the development addon card anyways. Changes to target Config.lb so it actually builds. Signed-off-by: Peter Stuge <peter@stuge.se> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12Vendor specific patch, thus self-acked.Stefan Reinauer
* going back to old board specific dsdt for agami aruma. This is hopefully dropped again some day, but until then here's a working solution. * Some minor Agami specific changes. * drop obsolete bringup workaround hyperclocking.diff * increase image size again, x86emu wants it. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-09This patch corrects r2587. It makes sure that the VGA is initializedRoman Kononov
when CONFIG_CONSOLE_VGA==0 and CONFIG_PCI_ROM_RUN==1 Signed-off-by: Roman Kononov <kononov@dls.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-07Fix epia-m build after u8/u16/u32 changes in Yh Lu's patch.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06YhLu's patch from January 18th.Yinghai Lu
hypertransport specific updates Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Ed Swierk <eswierk@arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06This commit is part of YhLu's patch from January 18th.Yinghai Lu
Drop a lot of debugging code from northbridge.c Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Ed Swierk <eswierk@arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06YhLu's patch from January 18th. This part is mostly cleaning up Yinghai Lu
dead code and adding a few fixmes. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Ed Swierk <eswierk@arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06next part of YhLu's large patch. I am not sure whether the tables.cYinghai Lu
changes are correct. If someone could look into this, thank you. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Ed Swierk <eswierk@arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06Disable USB console on the m57sli for now.Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 23:48:26 +0000