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2021-09-23soc/amd/common/blocks/include: rename gpio_banks.h to gpio.hFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd/common/blocks: rename gpio_banks folder to gpioFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3dfcca2f126eb49c962b5cc32cbcf72e04f3f170 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23mb/intel/adlrvp_m: Enable HECI1 communicationzhixingma
The patch enables HECI1 interface to allow OS applications to communicate with CSE. TEST=Verify PCI device 0:16.0 exposed in the lspci output Signed-off-by: zhixingma <zhixing.ma@intel.com> Change-Id: Ifd338345caa183f03097f1003080992da70296ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/57813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-09-23soc/amd: rename program_gpios to gpio_configure_padsFelix Held
Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd,intel/common/include/gpio: improve documentation of overridesFelix Held
Explicitly point out that gpio_configure_pads_with_override will ignore GPIOs that are only in the override configuration, but not in the base configuration. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1bdfcac89b81fef773938133a2699897c6ee9415 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/brya/variants/gimble: Update DPTF sensorsMark Hsieh
Add two thermal sensors for fan and charger for DPTF based thermal control. BUG=b:199180746 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I1529dd5dff3445dd499ed665386a9b06d67c7028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57833 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23mb/google/brya/variants/gimble: Update audio settingMark Hsieh
Add vmon-slot-no,imon-slot-no and dsm_param_file_name in overridetree.cb BUG=b:197701952 TEST=build and check SSDT Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie646360c4ebbf25762b374c5bc3ef2017989fb2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57832 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23mb/google: Update comments in mem_parts_used.txt to match new templatesReka Norman
BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iafcbb3ce33cd2299ff98b54b9200f3e70929fb1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google: Bulk rename mem_list_variant.txt to mem_parts_used.txtReka Norman
The variant creation script creates a placeholder file called mem_parts_used.txt, with the intent that variant owners will populate this file with memory parts as needed. But instead, some partners have been adding the parts in a new file called mem_list_variant.txt and removing the placeholder file. E.g. https://review.coreboot.org/55735. There's nothing wrong with this, but it's confusing to have two different file names which serve the same purpose. Bulk rename all the mem_list_variant.txt files to mem_parts_used.txt. The only time these file names are used is as an argument to the spd_tools part_id_gen script, so no other changes are necessary. BUG=None TEST=Re-run part_id_gen for all variants of brya/volteer/dedede/guybrush/zork. Check that the only change is to the "Generated by" comment in Makefile.inc and dram_id.generated.txt. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Icdeee78ae5c01e97f66c759c127175b4962d5635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/volteer: Remove unused mem_parts_used.txt from copano/collisReka Norman
The copano and collis variants have both a mem_parts_used.txt and a mem_list_variant.txt. The mem_parts_used.txt files are empty, so delete them. BUG=None TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ia98aad7238b0173b8d5c048d89637bc297d02283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/zork: Migrate zork to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all zork variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for dalboz: util/spd_tools/bin/part_id_gen \ PCO \ ddr4 \ src/mainboard/google/zork/variants/dalboz/spd \ src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/zork -a -x --timeless Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I305a24f9345bab28ff35e317b6e7fd7efba22413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57772 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23soc/intel/xeon_sp/cpx: Use FSP repoArthur Heymans
Some headers in vendorcode are still needed but the UPD definitions can be taken from the FSP repo. Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23soc/intel/xeon_sp/cpx: Rename FSP UPDs using CPPArthur Heymans
coreboot expects different names for FSP UPDs so use some CPP to make it happy. Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23soc/intel/xeon_sp: correct wrong gpio register base offsetsMichael Niewöhner
Reference: Intel doc# 633935-005 and 547817 rev1.5. Change-Id: I38c20288a9839f8c3cf895f7b49941387bdca5e2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Lance Zhao Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-09-23soc/intel/tgl: correct wrong gpio GPI enable register base offsetMichael Niewöhner
Reference: Intel doc# 631120-001. Change-Id: Iaf3a1b7bc38a1b30f8cc901bd6496e77f2d92cfd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23soc/intel/icelake: correct wrong gpio SMI register base offsetsMichael Niewöhner
Reference: Intel doc# 341081-002. Change-Id: If6e0503cc042c26c4077b8b32bb447d4e3a9bb6a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-23soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registersMichael Niewöhner
Add NMI_EN and NMI_STS registers, so NMI interrupts can be used. References: - XEON-SP: Intel doc# 633935-005 and 547817 rev1.5 - ICL-LP: Intel doc# 341081-002 - TGL-LP: Intel doc# 631120-001 - TGL-H: Intel doc# 636174-002 - JSL: Intel doc# 634545-001 - EHL: Intel doc# 636722-002 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
2021-09-23soc/intel/icl: add missing gpio group to fix the group indexesMichael Niewöhner
There is another gpio group, namely HVCMOS, between GPP_C and GPP_E. Add it, so the group index calculation for GPI/SMI/NMI results in the correct value. Reference: Linux linux/drivers/pinctrl/intel/pinctrl-icelake.c Change-Id: I7725191173ddc0d43bbe940cdf3b0dc2aa3e5f8d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/hatch/moonbuggy: copy PCIe configuration from genesisJeff Chase
The moonbuggy pcie topology is the same as genesis so copy from its device tree and gpios in order to enable these devices. BUG=b:199746414 TEST=lspci Change-Id: I4e916a95047b9f955734f164d7578c520478f5af Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/brya/var/anahera: Update gpio and devicetreeWisley Chen
Based on latest shcematic to update the device tree and gpio. BUG=b:197850509 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I0a999de479c7b2e4776a57e1e56b1568450ec31a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23elog: calculate year correctly in timestampRicardo Quesada
This CL uses a 16-bit value (instead of an 8-bit value) for the year. This is needed because the function internally does a "year % 100", so the year should not be truncated to 8-bit before applying the modulo. This fixes a regression introduced in commit e929a75. BUG=b:200538760 TEST=deployed coreboot. Manually verified that year is correct using "elogtool list" TEST=test_that -b $BOARD $DUT firmware_EventLog Change-Id: I17578ff99af5b31b216ac53c22e53b1b70df5084 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/guybrush: Migrate guybrush to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all guybrush variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for guybrush: util/spd_tools/bin/part_id_gen \ CZN \ lp4x \ src/mainboard/google/guybrush/variants/guybrush/memory \ src/mainboard/google/guybrush/variants/guybrush/memory/mem_list_variant.txt For dewatt, the Makefile.inc was manually modified to use the new placeholder value. BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/guybrush -a -x --timeless Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I48ca430b80b892d68dad582b1d9937a9edafa5d4 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/dedede: Migrate dedede to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all dedede variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for cret: util/spd_tools/bin/part_id_gen \ JSL \ lp4x \ src/mainboard/google/dedede/variants/cret/memory \ src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt For cappy, the Makefile.inc was manually modified to use the new placeholder value. BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/dedede -a -x --timeless Change-Id: I2871ff45d6202520d4466b68a4d5bb283faf2b63 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/dedede: Remove unnecessary fixed IDs from galtic mem_parts_used.txtReka Norman
Currently, trying to regenerate the galtic Makefile.inc and dram_id.generated.txt using part_id_gen fails due to duplicate fixed IDs in the mem_parts_used.txt file. Remove the fixed IDs since they aren't needed. The part IDs assigned are the same either way. Also delete the comments from mem_parts_used.txt, since lp4x/gen_part_id currently doesn't support comments. BUG=b:191776301 Regenerate the Makefile.inc and dram_id.generated.txt using gen_part_id, and check that the part IDs don't changed. Command used: util/spd_tools/lp4x/gen_part_id \ src/soc/intel/jasperlake/spd \ src/mainboard/google/dedede/variants/galtic/memory \ src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ida83814b2f19b4a56eb9fde5939fa6c7874803c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23mb/google/volteer: Migrate volteer to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all volteer variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for voema: util/spd_tools/bin/part_id_gen \ TGL \ lp4x \ src/mainboard/google/volteer/variants/voema/memory \ src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/volteer -a -x --timeless Change-Id: Ibd4f42fd421bfa58354b532fe7a67ee59dac5e1d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google/brya: Migrate brya to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all brya variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for anahera: util/spd_tools/bin/part_id_gen \ ADL \ lp4x \ src/mainboard/google/brya/variants/anahera/memory \ src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/brya -a -x --timeless Change-Id: I08efe1d75438c81161d9b496af2fa30ce6f59ade Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23lib/Makefile.inc: Generate placeholder spd.bin in lib/Makefile.incReka Norman
When a new variant is created, it needs to have a path to its SPD binary defined. Currently, this is done by setting SPD_SOURCES to a placeholder SPD file, which just contains zero bytes. To remove the need for a placeholder file, automatically generate a single-byte spd.bin in lib/Makefile.inc when SPD_SOURCES is set to the marker value 'placeholder'. BUG=b:191776301 TEST=Change cappy/memory/Makefile to `SPD_SOURCES = placeholder`. Build and check that spd.bin contains a single zero byte. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I11f8f9b7ea3bc32aa5c7a617558572a5c1c74c72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23soc/qualcomm/common: Move UART SC7180 driver to common sectionRajesh Patil
Move existing UART driver from sc7180 to common folder. This implements UART driver for QCOM SoC's BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I7bc2d3765f956e04bae3e45c3a9b9e2ad424c7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-23mb/google/brya/var/taeko: Correct IOM port configurationJoey Peng
Enable programming of Type-C AUX DC bias GPIOs. BUG=b:199833078 TEST=Verify that a Type-C monitor works when connected in both orientations. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I4f6d80a9f2fc8cdc93226d6c234b54e5db830d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-22soc/amd/common/block/gpio_banks: Rework GPIO pad configurationFelix Held
Before this patch, gpio_configure_pads_with_override called program_gpios once for each GPIO that needed to be configured which resulted in base_num_pads - 1 unneeded master_switch_set/ master_switch_clr sequences for the gpio_configure_pads_with_override call. Instead implement gpio_configure_pads_with_override as the more generic function and program_gpios as a special case of that which passes an empty override configuration and override pad number to gpio_configure_pads_with_override. TEST=GPIO configuration and multiplexer register values are the same for all GPIOs on google/guybrush right before jumping to the payload before and after the patch. Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-22mb/system76/addw1: Add Adder WS 2 as a variantTim Crawford
Change-Id: I3965a90151bd9250a87dabc715d68a39699ff9e1 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-22mb/system76/addw1: Add System76 Adder Workstation 1Tim Crawford
Change-Id: I5dd3bc320ca640728e1d86180c6bfa0dc7295760 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-22ec/google/chromeec: Update ec_commands.hRob Barnes
This change copies ec_commands.h directly from Chromium OS EC repo at sha 8c2c6bd5b1d44b367929af498d4d4b0df126a4ef. BUG=b:188073399 TEST=Build coreboot BRANCH=None Change-Id: I674cb860adb6b8497a8aecf47952ed8f85ddaa70 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2021-09-22soc/intel/alderlake: Drop unused HECI_DISABLE_USING_SMM KconfigSubrata Banik
Earlier generation platform used `HeciEnabled` chip config (set to 0) and HECI_DISABLE_USING_SMM Kconfig to make the CSE function disable at the end of the post. `HeciEnabled` chip config remains enabled in all latest generation platforms hence drop HECI_DISABLE_USING_SMM Kconfig selection from SoC Kconfig as CSE remains default enabled. BUG=b:200644229 TEST=No functional impact during boot as CSE (B:0, D:0x16, F:0) device is listed with `lspci`. Change-Id: I5278e5c2e015b91bb3df3a3c73a6c659a56794b5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-09-22mb/google/brya/var/redrix: Update audio settingWisley Chen
Update codec/amp setting. 1. Update hid for ALC5682VS 2. Add maxim properties. BUG=b:197076844 TEST=build and check SSDT Change-Id: I8bedd4d0737caf46769ad27bce1768c225ce8a82 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-22mb/google/brya/var/redrix: Correct SSD power sequenceWisley Chen
The current power sequencing for the SSD does not work in a non-serial enabled BIOS image. It appears that the FSP scans the PCIe RPs before the SSD has time to prepare itself for PCIe, so the FSP disables the RP and so depthcharge cannot find a boot disk. Changing the power sequence timing to enable power in bootblock and deassert reset in ramstage follows the SSD's power sequence and allows it to be discovered by the FSP so the RP does not get disabled. BUG=b:199714453 TEST=build, boot into SSD, and run reboot stress test. Change-Id: I5e7943a6cc88bc02bcbd97a1086b2d8044d7b1c3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-21soc/amd/common/block/gpio_banks: add missing types.h includeFelix Held
In this file bool, uint8_t and uint32_t are used, so include types.h directly to have those types defined instead of relying to have those included indirectly via amdblocks/gpio_banks.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6f4626a50219fab818e8bc5087961a731b44e71b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-21soc/qualcomm/common/spi: Configure SPI QUP driverRavi Kumar Bokka
This implements the SPI driver for the QUP core. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I7e5d3ad07f68255727958d53e6919944d3038260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56399 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-21sc7280: Enable SPI driverRajesh Patil
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I34a45422e38ea3a47f29e9856fc5679e8aebbcdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21soc/qualcomm/common/spi: Add support for SPI common driverRavi Kumar Bokka
This implements qup spi driver for qualcomm chipsets Rename header file names for trogdor to prevent breakage. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I2f2b25b6661fcd518f70383da0c7788c5269c97b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55953 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-21sc7280: Enable I2C driverRajesh Patil
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I58c2b79ea2feeab0ad4c2b7cdaa041984160a7ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/55961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21soc/qualcomm/common/i2c: Add support for I2C common driverRajesh Patil
copy existing I2C driver from /soc/qualcomm/sc7180 to common folder. This implements i2c driver for qualcomm chipsets BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I16e6fc2c1c24b9814d1803bffd5cfbb657201cfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21src/mainboard/herobrine: Load GSI FW in ramstageRavi Kumar Bokka
Load GSI FW in ramstage and make it part of RW BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21src/mainboard/herobrine: Load respective QUP FW for I2C and SPIRajesh Patil
Loading QUP FW as per herobrine and piglin configuration for I2C, SPI and UART. As part of the code clean up, update the header files of the QUP drivers with the correct path. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: Ic218c6a91ffc4484830446d707d1f3403e2dc46b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21sc7280: Refactor QUP driverRajesh Patil
Enable common qup driver in sc7280 BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I0e9049557ff63898037210e72333e1739ab62413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21lib/Makefile.inc: Fail build if SPD file doesn't existReka Norman
Currently, if LIB_SPD_DEPS contains an SPD file which doesn't exist, the file is silently skipped when creating spd.bin. Instead, fail the build. BUG=b:191776301 TEST=Build test on brya. Build fails if a non-existent file is included in LIB_SPD_DEPS. Change-Id: I1bdadb72e087c2ee7a88fbab2f3607bd400fa2e4 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21mb/google/guybrush: Add placeholder SPD fileReka Norman
BUG=b:191776301 TEST=dewatt build no longer fails when a check for non-existent files in LIB_SPD_DEPS is added (following commit). Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iee0c5e8b71f7cc7c016a38a60569daff99a55027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21mb/google/guybrush: Use open drain eSPI alertsRob Barnes
Remove the override in guybrush devicetree that configured in-band eSPI alerts. This will result in guybrush using dedicated open-drain eSPI alerts. Guybrush boards must be reworked to connect the eSPI alert line, otherwise they will not boot with this change BUG=b:198596430 TEST=Boot on reworked guybrush BRANCH=None Change-Id: I185eec773336fb662d9fe7f4c11991813e4d7cd6 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57778 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-21util: Add DDR4 generic SPD for 4JQA-0622ADFrank Wu
Add SPD support for DDR4 memory part BUG=b:199469240 TEST=none Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ie67cf6b90304f0bcf80838866c7461c0cea86dc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21soc/amd/picasso/fsp_m_params: use DEV_PTR to check if device is enabledFelix Held
The aliases are defined in the chipset devicetree, so the device pointers will be available for all boards using this SoC. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4c921575e978bb29e61f35e78ff2a1711acf06a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21soc/amd/cezanne/fsp_m_params: use DEV_PTR to check if device is enabledFelix Held
The aliases are defined in the chipset devicetree, so the device pointers will be available for all boards using this SoC. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id655e9eba9b8e9898fa01bf03876074e136cc7c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21drivers/gfx/generic: Drop unused find_gfx_devFurquan Shaikh
This change drops the function `find_gfx_dev()` as it is unused now. Change-Id: Ie42707bd45348dc7485ca0ca12ebff2994897e6b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21mb/google/hatch/var/jinlon: Switch to using device pointersFurquan Shaikh
This change replaces the device tree walks with device pointers by adding alias for igpu (integrated graphics) device in the tree. Change-Id: I6d159f6dc674f4a0b38ebb553c5141105405a883 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21mb/google/guybrush: Switch to using device pointersFurquan Shaikh
This change replaces the device tree walks with device pointers by adding alias for following devices: 1. FPMCU 2. WWAN Additionally, this change drops the __weak attribute for variant_has_* functions as there is no need for different implementations for the variants. Change-Id: I8af5e27f226270e6b40a50640c87de99a5a703f7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21mb/google/dedede: Clean up LTE device enablingFurquan Shaikh
On some dedede variants, USB port 2.3/3.3 might be connected to either LTE device or Type-A external port depending upon FW_CONFIG. Commit 856b579 ("mb/google/dedede/var/kracko: Update LTE USB port configuration") enabled Type-A external port by default in override tree and updated the config dynamically for LTE USB device if FW_CONFIG indicated support for it. This was required because sconfig lacked the support for multiple override devices. Commit b9c22e0 ("util/sconfig: Compare probe conditions for override device match") fixed this behavior in sconfig and now we can add multiple override devices using different FW_CONFIG probe statements in override tree. Hence, this change moves the LTE USB device to override tree for metaknight, kracko and drawcia variants. In addition to that, drawcia needs to be update reset_gpio depending upon board_id. Thus, alias `lte_usb2` is used in drawcia override tree to fix the reset_gpio for older boards i.e. board_id <= 9. Change-Id: Ie5b205594680d9c2b8543c5c99325d95620cafd2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21mb/google/dedede/var/sasukette: Drop special codec device handlingFurquan Shaikh
On sasukette, codec device might be either 10EC5682 or RTL5682 depending upon the provisioned FW_CONFIG value for AUDIO_CODEC_SOURCE. The HID for the device was updated in ramstage.c because sconfig lacked the support for multiple override devices. Commit b9c22e0 ("util/sconfig: Compare probe conditions for override device match") fixed this behavior in sconfig and now we can add multiple override devices using different FW_CONFIG probe statements in override tree. Hence, this change moves the codec device to override tree and drops the special handling in ramstage.c This change also probes for UNPROVISIONED value of FW_CONFIG for "10EC5682" device since some devices might have shipped with UNPROVISIONED value and using "10EC5682" device. Change-Id: I909a29c3df0cbb7ac3c07ca7663a49ad47007232 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20mb/google/volteer: Switch to using device pointers using alias namesFurquan Shaikh
This change replaces the device tree walks with device pointers by using alias names for the following devices: 1. PMC MUX connector 2. SPI TPM 3. I2C TPM Change-Id: I38f87d3a90a7253f2a29aba7db9a9f9744985494 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20mb/google/brya: Switch to using device pointers using alias namesFurquan Shaikh
This change replaces the device tree walks with device pointers by adding alias for dptf_policy generic device in the tree. Change-Id: I8fd5476a9cea84ab8b2678167b3e0504eecacf6c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20mb/google/brya/var/redrix: Enable EC keyboard backlightWisley Chen
Enable EC keyboard backlight for redrix. BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Change-Id: I175d8b91b37c6645ab1a7f05fc6915b3b016e3ff Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20herobrine: Add Hoglin variantShelley Chen
Create a variant for the QC CRD device. BUG=b:197366666 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HOGLIN -x -a -B Change-Id: I883d17b3ad3c7e44a00f0d0e7007c119417c5028 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-20soc/intel/elkhartlake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: I95753fa536fae8ca4bb95007419875815c1bcb06 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20soc/intel/icelake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: I1a55df754c711b2afb8939b442019831c25cce29 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20soc/intel/jasperlake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: Idfaa9a24f7b7fefa4f63ab8e3bc4ee6a0f1faedf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20soc/intel/tigerlake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: Ie86822f22aa5899a7e446398370424ca5a4ca43d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20vc/amd/sb800: Fix out of bounds shiftPaul Menzel
Fix the two issues below. SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:49:18 ubsan: unrecoverable error. SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:66:18 ubsan: unrecoverable error. Found by: UBSAN Change-Id: Id42e62d35f59793bad10998f14422ab7fb4fc029 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-09-20soc/amd/cezanna/acpi/mmio.asl: enable ACPI AOAC for I2CJulian Schroeder
This enables runtime power management for the I2C controllers. BUG=b:182556027, b:183983959 TEST=enable dynamic debug in kernel and check i2c D3/D0 transitions during suspend_stress_test. Change-Id: Ia6b9ca95d751f32b7cd701494377f15091c22d2f Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56462 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-20soc/amd/cezanne/acpi/mmio: uncomment AOAC_DEVICE macro for UARTsFelix Held
This enables runtime power management for the UART controllers. BUG=b:183983959 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e57d6312feda459cec65f330c6d2072774d4eb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-20driver/i2c/max98390: Add vmon_slot_no/imon_slot_no propertyWisley Chen
Add two properties (maxim, vmon-slot-no/maxim, imon-slot-no) in maxim9839 driver. This is I/V source destination definition that from below properties . maxim,vmon-slot-no => PCM_IVADC_V_DEST maxim,imon-slot-no => PCM_IVADC_I_DEST BUG=b:197076844 TEST=build and check SSDT Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Idb24d19c7cfea559bf6d53f401d66cadb8b3acc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20soc/intel/{common,tgl,adl}: guard TME Kconfig option by SoC supportMichael Niewöhner
Currently, Intel TME (Total Memory Encryption) can be enabled regardless of SoC support. Add a Kconfig to guard the option depending on actual support. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia20152bb0fc56b0aec3019c592dd6d484829aefe Reviewed-on: https://review.coreboot.org/c/coreboot/+/57762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-20device: Add helper macros for device pointers using alias namesFurquan Shaikh
This change provides helper macros for generating pointer name and weak pointer definition for devices using alias names. This will be helpful for developers to reference the device pointer with alias names used in the device tree. Change-Id: I3a5a3c7fdc2c521bac9ab3336f5a6ebecd621e04 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20mb/google/brya/var/redrix: Get wifi sar nameWisley Chen
Add get_wifi_sar_cbfs_file_name() to return the wifi SAR file name BUG=None TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I87e7a30619fd93d0eae692c4c540c29850ff6721 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20mb/google/brya: Add CHROMEOS_WIFI_SARWisley Chen
Add CHROMEOS_WIFI_SAR to include the SAR configs. BUG=None TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I50a413f3425d0b0e0b5ce71dabf6b9477800795e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20device/dram/spd.c: Add more manufacturer ID codesJingleHsuWiwynn
Add manufacturer ID codes for Hynix, Samsung and Micron. Tested=On OCP Crater Lake, dmidecode -t 17 shows expected info. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I0b4bbc46d3bfd9e9534cdd59f90cbdc150f29542 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daocheng Bu <daocheng.bu@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20mb/system76/cml-u: Add Darter Pro 6 as a variantTim Crawford
Change-Id: I9ba7d2af3c9c298fda2b2997d52546cc2f702a82 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-20mb/system76/cml-u: Add System76 Galago Pro 4Tim Crawford
Change-Id: I3dfa2ab430439d8dc71531b92aa7800db94d603b Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-20vc/amd/agesa/Kconfig: Move SPD options out of choiceAngel Pons
The Kconfig options for custom SPD values aren't supposed to be part of the choice block. Change-Id: I12eb1012f94000b14e5d7f1e5123dddf69ac1a94 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57717 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-20mb/google/brya/var/felwinter: Configurate AUX pin for USB3 MBEric Lai
USB3 MB doesn't have re-timer. Thus we have to configurate the AUX pin. For now, we use USB3 DB to determine the USB3 MB. BUG=b:197907500 TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ide45c77e0a6f736a02d5dc9ad05aa1ef9e754fa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20mb/google/cherry: Fix unusable USB3 HUBRex-BC Chen
To save the S3 power, USB3_HUB_RST_L is externally pulled up to a weak resistor so we have to reset the hub via GPIO84 as early as possible. Otherwise the USB3 hub may be not usable. BUG=b:199822702 TEST=measure voltage of USB3_HUB_RST_L as 1.8V Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ie87d631e83ede819ee9f9951dfc6517beae50247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57663 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-20mb/google/brya/var/redrix: Update thermal table.Wisley Chen
Update thermal setting from thermal team. BUG=b:200134784 TEST=build and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: If74c3bc19cf4abd64d646b842cbb6a61b910e933 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20device/mmio: Make buffer_to_fifo32() take a const bufferJulius Werner
The input buffer to the buffer_to_fifo family of functions is only read, so it can be a const pointer. (Also, remove the MIPS check in libpayload for these functions... the MIPS architecture has been removed a while ago.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I021069680cf691590fdacc3d51f747f12ae3df31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-19arch/riscv: Avoid gcc11 replacing memset implementation with memset callPatrick Georgi
SBI comes with its own memset implementation (under a slightly different name) that gcc11 "helpfully" tries to replace with a call to memset(). Since we don't provide a memset, the linker isn't happy, so prevent gcc from doing that. Change-Id: I3459a519d46a123f873306000b8b2261bd64e0c3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-17console: Remove asmlinkage from console_initRaul E Rangel
We never call console_init from asm, so we don't need the asmlinkage. This allows us to remove the arch/cpu.h include since we only needed it for the asmlinkage #define. BUG=b:179699789 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9a7895d4f5cba59f6b05915fa4d6c6fd6ab85773 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57568 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-17drivers/ipmi/ocp: add missing commonlib/bsd/cb_err.h includeFelix Held
This include provides the definition of enum cb_err. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idfee720de920377796e3fd64cb47514b8cb08c34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17sb/intel/ibexpeak/early_cir: add missing arch/cpu.h includeFelix Held
Including arch/cpu.h is needed to have the declaration for cpuid_eax, get_fms and struct cpuinfo_x86. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18b60f8cf33f71c7215a97ea209b8f8cf66cf42f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17drivers/gic/gic: add missing arch/cpu.h includeFelix Held
smp_processor_id is defined in src/arch/arm64/include/armv8/arch/cpu.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0b610189bf439774cb900f74559dee314cbc5854 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17sb/intel/bd82x6x,ibexpeak,lynxpoint/me.h: add missing includesFelix Held
Include device/device.h to have struct device defined and types.h to have bool, u8, u16 and u32 defined. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3c5d5a78c2e2dab21432ced5f84665eb78a49d52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17soc/intel/{ehl,jsl}: make use of Kconfig options for PRMRR sizeMichael Niewöhner
Migrate the last two platforms to using Kconfig through `get_valid_prmrr_size()` instead of hardcoded values in the devicetree. Change-Id: I93aa177f741ca8b2a2d50fae2515606b96784e83 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17mb/google/brya/primus: add NVMe power and reset pin to early_gpio_tableMalik_Hsu
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that primus can successfully boot into OS with non-serial coreboot. BUG=b:199967106 TEST=USE="project_primus" emerge-brya coreboot and verify it builds without error. Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I9c66efe96515347502d059556052c764c1be5d09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17mb/google/dedede/var/cappy2: Update DPTF parametersSunwei Li
Update DPTF parameters from internal thermal team. BUG=b:197546694 BRANCH=dedede TEST=emerge-keeby coreboot Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I71a76a4d94a704aef7b3cefa2fca3009eb765bb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57693 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-17security/intel/txt/romstage: add missing arch/cpu.h includeFelix Held
Including arch/cpu.h is needed to have the declaration for cpu_get_feature_flags_ecx. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I091c82f5a55ee9aa84a255c75c7721eff989344d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17cpu: add missing arch/cpu.h includesFelix Held
Including arch/cpu.h is needed to have the declaration for cpuid_eax. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic22aba062117e3afa818fa2fc39cb0738e6a1612 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17mb/scaleway/tagada/bmcinfo: replace stdbool.h include with types.hFelix Held
Apart from the u8, u16 and u32 types, the bool type is used in this file so include types.h instead of stdint.h to have bool defined too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95f037deb0fe11b717586df655065bfbb33b0d23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17soc/amd/common/block/pi/image: replace stdbool.h include with types.hFelix Held
Apart from the bool type, uint8_t, uint32_t and uint64_t are used in this file, so include types.h instead of stdbool.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I30088d68132058f40b974fbaa822f322b58ed6c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17arch/riscv/trap_handler: add missing types.h includeFelix Held
Both bool and uintptr_t types are used in this file, so include types.h to have the definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I647d9f50cd6edaf08bebf5d713cd05731fadfc1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17broadwell boards: Reflow USB2 parameter statementsAngel Pons
These statements fit on a single line. Reflow them to ease future works. Change-Id: Ie18e9a00f67b999fdcedcab3c28b68e34bc93da4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-17mb/google/brya/var/redrix: Enable USB4 PCIe resourcesWisley Chen
Enable USB4 PCIe resources for redrix BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Change-Id: I759618055b1282653d8a05fa66e8cdab0c43e3a6 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17mb/google/brya: Add WWAN poweroff sequenceEric Lai
Follow FIBOCOM_L850-GL Hardware User Manual_V1.0.8. BUG=b:180166408,b:187691798 TEST=measure WWAN power off by scope is meeting the spec. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I6b2725cd61d5b54bc7fd70a9daffd29e7b43690b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17mb/system76/gaze15: Correct CMOS type for debug_levelTim Crawford
When the century byte was reserved, the debug_level was accidentally converted from an enum to a hidden value. Change it back to an enum. Fixes: f05bd8830de ("mb/system76/*: cmos.layout: Reserve century byte") Change-Id: Id88a7aed7b2fc793fd003db5b45f3f201b1a7630 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-17soc/amd/picasso/Kconfig: increase FSP_M_SIZEFelix Held
When using a debug build of the FSP, the FSP-M binary is larger than the memory region we have allocated for it, so increase the size to make the binary of the debug build fit in there. Also adjust the VERSTAGE_ADDR so that it starts right after the the FSP-M memory region. TEST=coreboot builds now successfully when using a debug version of the FSP Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib64806bcf948d5ed4bcf8e1f50004091f125dc7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17skylake DDR4 boards: Set `CaVrefConfig` to 2Angel Pons
The `CaVrefConfig` FSP-M UPD describes how the on-die Vref generators are connected to the DRAM. With the exception of an early Skylake RVP board (which doesn't have coreboot support), mainboards using DDR3 or LPDDR3 memory should set `CaVrefConfig` to 0, whereas mainboards with DDR4 should set `CaVrefConfig` to 2. MRC uses this information during memory training, so it is important to use the correct value to avoid any issues, such as increased power usage, system instability or even boot failures. However, several Skylake DDR4 mainboards don't set `CaVrefConfig` to 2. Although they can boot successfully, it's not optimal. For boards that set `DIMM_SPD_SIZE` to 512 (DDR4 SPD size), set `CaVrefConfig` to 2. Change-Id: Idab77daff311584b3e3061e9bf107c2fc1b7bdf1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 14:22:13 +0000