| Age | Commit message (Collapse) | Author |
|---|
|
The file and all of it's functions are unused. Drop the dead code.
Change-Id: Iaddd7a688d431d40f38293939e084d19b286aed4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Clang Static Analyzer version 8.0.0 detects that log2_ceil(bios_size)
and log2_ceil(window_size) are garbage or undefined if the value of
bios_size and window_size is zero. Check bios_size and window_size after
MIN operation to prevent error.
TEST=Built and boot up to kernel.
Change-Id: Ifc3f3da52d129ef5d6063a46b045603a236be759
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Clang Static Analyzer version 8.0.0 detects the division by zero if
gspi_clk_mhz is initialized to 0. gspi_clk_mhz is referred to speed_mhz
in devicetree. Set gspi_clk_mhz to 1 if it is detected as 0 in order to
prevent the division by zero in DIV_ROUND_UP operation. Then the value
of (ref_clk_mhz - 1) will be fed into GSPI's Serial Clock Rate value.
TEST=Built and boot up to kernel.
Change-Id: I6a09474bff114c57d7a9c4c232bb636ff287e4d5
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: Ic50b16916261abb8c63b8fe571819af5c830ff8d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
All platforms using this code use NO_CAR_GLOBAL_MIGRATION.
Change-Id: I426dee60521045db4711cd253432c65223a64b93
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: If952ad8129e1fa6e45858cb77ec99c9fec55c4a6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I91b6ce3b52d987e2fc0f79e550fda2891502bfe8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This platform uses NO_CAR_GLOBAL_MIGRATION.
Change-Id: Idc9434e5a1a8bc5ed76a9f80c9a7cfba2fd474c0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I5dfbc718fd82f0511b0049383e4e93c6f15ee932
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This soc has NO_CAR_GLOBAL_MIGRATION and does not require CAR_GLOBAL
and car_get/set_x.
Change-Id: I4e2c1c5766e3bcdd4763b42fb925074f7ccd7002
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32998
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These are only used where they are initially declared.
Change-Id: I0a81a945b771b6c29a170c479b9e72c98e8f3c5a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Now that this soc supports NO_CAR_GLOBAL_MIGRATION CAR_GLOBAL and
car_get/set_x are not needed anymore.
Change-Id: Ia7fa97135a4b376ac0bd8b30093a77614cc2cf55
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: Ib863e23863ba6d7504b6c4d32de2f1fea4e57fec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I0f393385aa94f18c2e05af3b5a54999575323d18
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
When using native raminit with https://review.coreboot.org/#/c/22683/
I've found that timC training usually fails unless the ram is
overspecced (i.e. DDR3L-1600 rated for 1.35V works most of the time with
native raminit as DDR3-1333 @1.5V).
Looking at the training data I've found that during timC training it is
reading register values in the 0-4000 range and checking for runs of 0,
but with the failing training the values don't go all the way down to 0.
The solution for me has been to do a thresholing pre-pass, after which
both the DDR3-1333 @1.5V and the DDR3L-1600 @1.35V work fine for me.
Tested:
- Intel NUC DCP847SKE
- RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V),
boots fine with native raminit @1.5V
- RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V),
boots fine with native raminit @1.35V
- Casual use with these settings
- Tested on Lenovo T520 with Crucial HyperX DDR3-1833.
- Memtest86+ stable.
Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/22776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
The Gigabyte GA-B75M-D3H/D3V mainboard trees share a lot of duplicate
code, and can serve as a base for porting other Gigabyte 7 series
motherboards. Switch the Gigabyte GA-B75M-D3H/D3V mainboard trees to a
variant setup, defining ga-b75m-d3v as a variant of ga-b75m-d3h.
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: Ia175207a2568aefe1aa9bd8d4d990de6a26f1657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Use the mainboard post code hook to inform the wilco EC driver of the
every stage.
BUG=b:124401932,b:133466714,b:133600566
BRANCH=sarien
TEST=Remove DIMM module, confirm diagnostic LED pattern for memory
failure (2 amber, 4 white).
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
It doesn't make sense to add a property to a non-existent Device
Property package. However, some of these functions will proceed anyway
and allocate a new Device Property package, add the property to
that, and then immediately leak the new package. This changes all the
acpi_dp_add_* functions to ignore a null package.
Change-Id: I664dcdbaa6b1b8a3aeb9a0126d622e2ffb736efd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 135745{6,7}, 138029{2-6}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Even fingerprint device probe failed on non-fingerpint boards,the CRFP driver
still register the device that cause the GPE#1 as wake source every time.
Override devicetree for non-fingerpirnt variants to avoid unexpected wake
event(GPE#1).
BUG=b:129650040
BRANCH=firmware-nami-10775.108.B
TEST=Boots to OS and check no GPE#1 wake event from eventlog when S0ix exit.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I6fa96e04a34e296889414b96a8c604fc61b8a236
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33017
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This also removes the unnecessary mask.
TEST: X201 Boots again.
Change-Id: Ia637bd01cd7dc1aecd1a87a739d5243c70419553
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I90f595d7d789429c8717261c6edb6c756f6c0e1f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
|
|
Dumping ME status displays wrong information if we disable Heci1 because
it is called after fsp notifies EndOfFirmware and disables Heci1. This patch
moves the ME status dump before fsp notify EndOfFirmware.
TEST=Boot to OS, check ME dump information
Change-Id: Ifd8b18a41c502c4ecfb84698a7669028394589fd
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Due to we turn off SSD power in S5. CB:32952
Based on M2 spec we have to turn on SSD power
before RST assert.
BUG=b:133389422
TEST=verify warm boot and cold boot are boot
successfully.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5b78bab4be675bbb8795361bcfa5af52cb54bb1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Turn off SSD power in S5.
BUG=b:133389422
TEST=measure H13 is low in S5
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
SMBIOS Type41 Entries will be automatically created. Type 41 entries
define attributes of the onboard devices.
Change-Id: Idcb3532a5c05666d6613af4f303df85f4f1f6e97
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32910
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Added missing new line to Info Output.
Change-Id: Ic4cd63f231de918fad7cd34724651bf8eb1c8e62
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Ib11981543575311a32896df385d44cf30aa9387f
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32964
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Modify reset delay to 20ms of touchscreen to address
i2c hid driver rebind failed issue after auto update of
touchscreen firmware
BUG=b:132211627
TEST=Touchscreen works after auto update and no re-bind
driver failed issue
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: If17afbd160a2c97beb69d0cb50e4a7dc654775f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Crews <ncrews@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Since all targets using sb/intel/common and cpu/intel/smm/gen1
are now using PARALLEL_MP, some code is not used anymore.
Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30019
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
TESTED on Thinkpad X201 with a i7 CPU M620 CPU (hyperthread dual core).
Boots ~28ms faster.
Change-Id: I56b352f9d76ee58f5c82cd431a4e0fa206f848a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
TODO in followup patch: Some not mainboard specific things should be
moved out of mainboard_smi_apmc.
Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
drivers/intel/fsp1_0/Kconfig is a better location than
cpu/x86/Kconfig.
Change-Id: Ic1c86c26a66c33760484bb6a86e9763c148a7c96
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This function is unused since POSTCAR_STAGE is used.
(be291e8 soc/intel/fsp1.1: Implement postcar stage)
Change-Id: Ia9ff5236295a0e1c4f7634d27cf0ae1d87029678
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
This list is incorrect and not up to date. The FSP1.1 romstage
bootflow is unnecessarily clumsy and instead of trying to update this
comment effort is better spend making the bootflow more streamlined.
Change-Id: If1e4c462acd0748f072f33e6397a7b43f3bfc834
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
On reset this platform can sometimes hang.
This also fixes pineview mainboards not building due to the symbol
'check_mtrr' lacking.
Change-Id: I61fe77113004ea664522bda549240a33e3742a98
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Change-Id: I993055d237b2bd607822485d34d5508c74a7744c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This adds a file i82801gx/bootblock_gcc.c since other targets that
don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled
bootblock.c.
Tested on Foxconn D41S.
Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Unify thermal handling across Lenovo boards (except g505, which is
different). Namely, do the following:
* Move thermal levels from acpi_tables to thermal.h (and create if
necessary).
* Don't use board-specific ifdef guards.
* Set thermal levels using dedicated acpi_update_thermal_table function
as almost all Lenovo boards do.
* Update list of authors in comments. Merge all author's entries.
* Minor whitespace and formatting.
This makes diff -ruw between the Lenovo boards smaller.
Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29659
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The call to timestamp_rescale_table() had to be moved
before TS_AGESA_INIT_{POST/RESUME}_DONE to have that
timestamp appear without rescaling.
Change-Id: I71e09d3bc4c8657979d447b90fb6ac7cae959479
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Stop assuming the list is complete with no gaps, and
use a lookup-table to match AGESA_STRUCT_NAME types
of the entrypoints we use with names.
Change-Id: Ibef4690d8aa76ff5b47c879f5ceb9d8fc4c4c4cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Change-Id: I2d74f934936e250886526b9c8482f500628a1158
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31513
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Extra variable is no longer required here.
Change-Id: I2a6839ee0349e3019de3b2a91f9e7bb1c435603d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Place it within class libagesa to avoid including
AGESA internal header heapManager.h in coreboot
proper build CPPFLAGS.
Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This command is working as written, but it is not actually correct
as to what the format of the command should be. Fix this and add
define the other radios. There is no change in the command send to
the EC.
Change-Id: Ia551b08561b673d27bec2f900d97b746699b30c4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Change-Id: I45f32ea1ebf59a20d475dfad2d9d0980dec6918b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Change-Id: I715adbe3d90d0f5195b54c274fb7843945d3e6be
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: Ic2f2788142329e2e4d04b531805a32d4dcaa293c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32949
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I309cf83a1fec16b796c72c1803d27e1b7932940f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Change-Id: I14c69b324de795ba6dead7932b3267887130a6df
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Add support for ASpeed AST2400.
This device uses write twice 0xA5 to enter config mode.
BUG = N/A
TEST = ASRock D1521D4U
Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: I496b3a91f765d4fa137c32c9ee1e244803fc25d8
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32850
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We got another tag in the meantime, so resolve the conflict.
Change-Id: I64cb5e02a9bed3d8746b75e451c13a1598341ba1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32954
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Pass the return value from early_mmc_wake_hw() to the payload so that
payload can skip sending CMD0 and resetting the card in case of success
or in case of a failure in firmware, payload can recover by sending
CMD0 and resetting the card.
BUG=b:78106689
TEST=Boot to OS
Change-Id: Ia4c57d05433c3966118c3642913d7017958cce55
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25464
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In order to improve boot time with emmc, add ability to send CMD0
and CMD1 early in romstage. This way, by the time system boots to
payload, we are ready to continue with emmc setup and we don't need
to send CMD0 in payload again, and wait for card to reset and be ready.
BUG=b:78106689
TESTS = Boot to OS
Force early_mmc_wake_hw() to return error, recover in payload
Force an error in payload, make sure system can recover/boot
Change-Id: I3488b077bf5100a1e0f2c879fb1436105607d25e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
|
|
There are indeed two temperature sensors hooked up to the EC, but they
are indexed as 0 and 1, not 1 and 2.
BUG=b:132999028
TEST=Boot hatch with hardened EC, observe no more index overflows
Change-Id: Ia7f503bc1dc941635db52fce40f217bf34da6d2b
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
While not implemented, copying the definitions from
later AGESA/AMD.h to older helps us avoid lots of
preprocessor directives.
Change-Id: I34edc1ca23e9c063c4286273c53249ff0a953798
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31510
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ic04cb7c51862bea4d01f853ee2c88cc03c414e35
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32899
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I3e304b9b19978c4100ef3486088d809c2a7fe1d7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32898
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: If9ca551794a52e47a3649b126c3f061a68c494e4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32897
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I8d0ab8bdc506592ef1d731e557b2397481aed725
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32896
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I4e7f74f67f03131fae205a93dae3d61eca9cc0c7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32895
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ic04231525c1aaaf3afc8c11cddc409b1f5b46743
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I73f35ea80976ab445c797c4800b1e2fd24d34fdf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32893
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
CMOS isn't used that early, but the chipset initialization may be
required to access it.
In one instance, Intel Apollo Lake, the sanitize_cmos() function
seems to hang if called before bootblock_soc_early_init(). The
missing step is fast_spi_early_init(). But even without, one might
expect sanitize_cmos() to return eventually (it didn't within
about 20min).
Change-Id: I6e1a029e4be7e109be43a3dad944bd7e05ea1f02
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
|
|
This patch rewrites some of the device tree code to use the new
be32dec/be32enc helpers where they can make the code cleaner.
Change-Id: I437bbd6645a556ae9a0cfe6ea14638098e4c3606
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32860
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In some cases we may have boards that need to differentiate SKUs but
don't really want to differentiate revisions (at least for some SKUs).
Let's add a compatible string match that includes only the SKU but not
the revision so that kernel DTSes don't have to specify every possible
revision if they want to match this.
This patch was adapted from depthcharge's http://crosreview.com/1512004
Change-Id: Ib88862424b350a213761f5662fe170a1f8fccc7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32859
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
vtxprintf.c seems to have been written before string.h was as fleshed
out as it is today -- this patch removes some custom implementation of
stuff we now have globally. It also makes the skip_atoi() function
globally available, because I need it somewhere else, and while we maybe
don't want a huge fully-featured string parsing library in coreboot,
being able to parse an integer is occasionally useful.
Change-Id: Iecb2b970aecfc768540d2bf8b3023445f54853a4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
|
|
coreboot should not have a definition of printf() anywhere -- it's too
easy to accidentally sneak it into code otherwise. Where that is needed
in code shared with userspace utilities, we should instead use printk()
and define a shim for that for the userspace side.
Change-Id: Iaa459df7122c88beb56695eee7c252d90bbde861
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32857
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Libpayload has a family of functions that can "encode" or "decode" an
endian-specific integer onto a byte stream pointer. These allow writing
more pretty code than a raw be32_to_cpu/cpu_to_be32 with pointer casts
in many (de-)serialization scenarios, so let's add them to coreboot as
well.
Change-Id: I049c5665484da12b3cf977a529310b0bde177d2d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Required for automatic onboard device detection in the next patch.
Change-Id: I3087de779faf8d006510c460b5372b22ae54b887
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32909
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
* Add VBT
* Configure OnBoard NIC
* Add documentation
Change-Id: Iad739b4e1dacb41f5f63247150951df7013bbf0c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Use the mainboard post code hook to inform the wilco EC driver of the
latest boot stage.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
TEST=Remove DIMM module, confirm diagnostic LED pattern for memory
failure (2 amber, 4 white).
Change-Id: If5bf69365d8be3bdbd433f305c85848206ded7b0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32937
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
On Wilco devices, if any of the coreboot stages fails with a fatal
error, set the diagnostic LEDs with the Wilco EC. The last saved
post code is used to determine the error code sent to the EC.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
TEST=Remove DIMM module, confirm diagnostic LED pattern for memory
failure (2 amber, 4 white).
TEST=Forced a fatal error in both bootblock and verstage to confirm
diagnostic LEDs during these stages. This works on cold-boots only. Bug
b:132622888 tracks the mailbox failures on warm boots.
Change-Id: If865ab8203f89e499130f4677fec166b40d80174
Signed-off-by: Keith Short <keithshort@chromium.org>
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon
initialization returns an error when graphics was also initialized.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to
detect or initialize a required hardware component.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails
to initialize RAM.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails
to locate or validate a vendor supplied binary.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Add a new post code POST_INVALID_CBFS, used when coreboot fails to
locate or validate a resource that is stored in CBFS.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: If1c8b92889040f9acd6250f847db02626809a987
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Add a new post code, POST_INVALID_ROM, used when coreboot fails to
locate or validate a resource that is stored in ROM.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Now that we call post_code in other stages other than RAMSTAGE, we need
to guard the elog calls with the appropriate condition in order to
compile correctly.
Change-Id: I766c276f28d46492fb05e0e3be71853e21f4e8e0
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Works:
- bootblock, romstage, ramstage
- Serial console UART0, UART1
- SPI flash console
- iGPU init with libgfxinit
- LAN1, LAN2
- USB2, USB3
- HDMI, DisplayPort
- eMMC
- flashing with flashrom externally
WIP:
- Documentation
- VGA
For some reason Seabios can not find the CBFS region
and therefore it can't load seavgabios, but generally
it is working as soon as Linux is booted.
- ACPI
Works not:
- Devices needs proper configuration
- Seabios can't find CBFS region
Untested:
- GPIO pin header
- 60 pin EXHAT
- Camera interface
- MIPI-CSI2 2-lane (2MP)
- MIPI-CSI2 4-lane (8MP)
- SATA3
- USB3 OTG
- embedded DisplayPort
- M.2 slot
- mini PCIe
- flashing with flashrom internally using Linux
Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
At the end of device enable, print the ME f/w version number.
Before resume or loading payload, dump the ME's Host Firmware
Status registers.
BUG=b:131437724
BRANCH=none
TEST=Prints seemingly sane values on WHL and CML devices.
Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32527
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The entry to AGESA always follows pattern:
amd_create_struct()
amd_dispatch()
amd_release_struct()
Separate the create/release_struct calls from the more
relevant entry point details.
Change-Id: I1037c9daef3365c8672a198ac60f47fc79ffaea1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31488
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Include spi.c in romstage. Since FSP 1.0 can't use
NO_CAR_GLOBAL_MIGRATION, adjust global variables in spi.c
to use CAR_GLOBAL.
Adapted from early versions of CB:21107
Change-Id: I3487fb8ac317ce920bf1c3ef9d89590051932378
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Enabling flashconsole on these platforms fails to build due to
spi.c not being compiled in prior to ramstage. Include in early stages
(bootblock/romstage/postcar) as needed to enable flashconsole support.
Early inclusion of monotonic_timer.c is needed for Broadwell as well.
Change-Id: Idae0578ca92939246021bb85e34b0dcbd41df3b5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Display is required by recovery mode. Determine display init
before recovery check.
BUG=b:133197727,b:133175864
TEST=enter recovery mode, checked the display shows up
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id6ac611f51241373bca3e2b394a94dcd52d3fde7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This moves FSP1.1 to use postcar stage to tear down CAR.
On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found
during the postcar stage so there is no need to push to save it
in CAR global variables.
On FSP1.1 platforms with an open source CAR implementation (Skylake,
even though it still runs the FSP-T), the
soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR.
This also uses common functions to set up the MTRR to use after
CAR is torn down.
Test: build/boot on google/celes (BSW) and google/chell (SKL)
Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Change-Id: Iad3982d9db07a1f17ac39e87ff9c37956e40c258
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This patch removes redundant mca_configure() function call
from ramstage to clear machine check exception. First time it's
getting called from soc_core_init() function inside cpu.c file.
TEST=Build and boot SKL/KBL/AML platform without any machine-check
exception.
Change-Id: I7e54fd07816c6317588ab6db06365937c4300ccd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This commit creates a garg variant for Octopus. The initial settings
override the baseboard was copied from variant bobba.
BUG=b:132668378
BRANCH=master
TEST=emerge-octopus coreboot
Change-Id: I9a36bc5dc3d2b891b1bce86015aa264894d1434b
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
Change-Id: I4fe5771dd1ebf3d2a981dab08e98f1c018d14133
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Currently, GPP_H0 gpio input rout is set to GPI_INT.
So, ACPI_GPIO_IRQ is required for GPP_H0 in devicetree
This change also aligns hatch's setting.
BUG=b:131742713
TEST=headset is working
Change-Id: Ie1264641bc4dfa5f98b6dab2d6f2133a6f9cbdb8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Change-Id: Id48de8b2f6feb6c29d745140c872215faa32eb37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31487
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
AmdCreateStruct() and AmdReleaseStruct() are equally bad
when it comes to lack of correct function declarations
for definitions found in vendorcode binaryPI/AGESA.c.
Replace these with calls that go through the common
module_dispatch() functions.
Change-Id: I611bcbe2a71fb65c8eb759a9dc74cbd9cb74136e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31486
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested:
- Ethernet NIC
- Wifi RFKill
- USB
- LVDS, VGA with libgfxinit
- Booting with dock attached (COM1)
- Keyboard, trackpoint
- SeaBIOS 1.12
- S3 resume
- Tested in descriptor mode, with vendor FD and ME
- Add VBT to ACPI OPregion
Untested:
- SATA (likely works)
- Trackpad (my cable is broken, likely works)
- Displayport (likely works)
- Descriptorless mode
- DVD drive
- Extra battery
- model with ATI GPU
Does not work:
- Dock hotplug
- Quad core CPU (hangs during AP init, probably needs hardware mod)
- Hotplugging the expresscard slot (works with 'echo 1 | sudo tee
/sys/bus/pci/rescan')
TODO:
- proper dock support
- documentation
note: This board was hard to flash, I had to desolder the flash.
TESTED: on a R500 with an Intel iGPU, SeaBIOS 1.12, Debian 9,
Linux 4.9 from USB
Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
All variants (t400, r400, t500, w500) use the same OPROM for the IGD.
Change-Id: I1b9db7b29b22809542f80f60a5e2eb3283fe1c02
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Probably a copy/paste issue.
Change-Id: I0334bc1f5d145df5af0a307cf8e7c23cc0605f76
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
When FSP UPD parameters are configured, also configure the GSPI CS lines
appropriately. GSPI driver assumes CS0 is the CS signal to use.
BUG=b:130329260
BRANCH=None
TEST=Boot Kohaku, TPM communcation still functional.
Change-Id: Ic816395b7d198a52c704e6cabcb56889150b741c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32791
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This microcode update for CPU IDs 0x610F01/0x610F31 improves system stability:
in particular, fixes Xen hardware virtualization freezes. Also it attempts to
patch some Spectre-related security vulnerabilities. This new microcode has been
tested by multiple coreboot community members and found working perfectly.
Old version: 0x600110F [2012-01-11]
replaced by
New version: 0x600111F [2018-03-05]
Change-Id: Ied5da0ff85abb63c2db2eeafd051b8e00916d961
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28273
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: <awokd@danwin1210.me>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
