summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2022-04-23soc/intel/alderlake: Refactor `pmc_lockdown_cfg` functionSubrata Banik
This patch refactors the `pmc_lockdown_cfg()` to remove the helper functions and uses the `setbits32` function to enforce bit locking as applicable. BUG=b:211954778 TEST=Able to build google/redrix with these changes and boot to OS. > localhost ~ # iotools mmio_read32 0xfe0018c4 0x85000000 (bit 31 is set) > localhost ~ # iotools mmio_read32 0xfe001024 0x00062610 (bits 4, 17 and 18 are set) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-23soc/intel/common/smbus: Add `finalize` operation for smbusSubrata Banik
This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs i.e. Post PCI Enumeration. The smbus `.final` operation ensures locking the TCO register when coreboot decides to skip FspNotifyApi() calls. BUG=b:211954778 TEST=Able to build google/brya with these changes and coreboot log with this code change as below with ADL SoC skip calling into FspNotifyAPIs: [INFO ] Finalize devices... [DEBUG] PCI: 00:1f.4 final > localhost ~ # lspci -xxx | less 00:1f.4 Intel Corporation Alder Lake PCH-P SMBus Host Controller (rev 01) Offset 8, Bit 12 a.k.a TCO Lock bit is set (meaning locked). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie945680049514e6c5d797790a381a6946e836926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-04-23soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configurationSubrata Banik
This patch drops SoC specific lpc lock down configuration as commit 63630 (soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration) implements the lpc registers lock down configuration in common code. BUG=b:211954778 TEST=Build. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I99ec6d63dfe9a8ac8d9846067a9afc3ef83dc1c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-23soc/intel/cmn/pch/lockdown: Implement LPC lock down configurationSubrata Banik
This patch implements a helper function to perform LPC registers lock down configuration. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified LPC PCI configuration register offset 0xDC bits BILD and LE are set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-23soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS regSubrata Banik
Typically, the SPIBAR_HSFSTS_W1C_BITS macro is used to clear all HSFSTS register bit-fields with the W1C attribute. So far SPIBAR_HSFSTS_W1C_BITS is 1 byte width hence, missed to clear SAF_CE (bit 8). This patch expands the `SPIBAR_HSFSTS_W1C_BITS` macro to include SAF_CE (bit 8). BUG=b:211954778 TEST=Able to build google/brya with this patch and clear SPI controller HSFSTS_CTL register Bits 0 to 4 and 8. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-04-22mainboard/ti: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: If0d9910db1d5626c2d49b85cb7a1ad54e935791b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-22drivers: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: I1d4473d297871b2bc8b614926bcf7390660a3d0d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-22device: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: I81bf00af1b56a0181c376db92f5f85297b6993ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-22cpu/amd: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: Ie9344da411a86186fa161e82db3c3fd3ffb911f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-22soc/amd: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: Ic8fea24f5f830294ce5b94374ce64d7ca2013c9c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-04-22soc/intel: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: I529c822c9e952dae6613d3de64f6709e0fd9b385 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-22mb/purism/librem_mini: Rework front status LED to show all disk activityMatt DeVillier
The front status LED on the Librem Mini is driven by the SATALED# GPIO line configured for native function, so only shows disk activity for SATA drives, but not NVMe. To allow it to show disk activity for NVMe drives as well, reconfigure the GPIO as GPIO-OUT (rather than native function), and configure it via ACPI so that the linux gpio-leds driver will attach and use it accordingly. This has the added benefit of allowing the user to reconfigure the LED as they see fit via sysfs. Test: boot Linux (PureOS) on Librem Mini v2 with NVMe drive, observe status LED blinks during periods of disk activity (tested via 'stress'). Change-Id: I34c2a5f3fd1038266f4514544abfc1020da6f85b Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-22soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumptionJamie Chen
According to Intel TA#724456, work around the higher SoC power consumption in S0iX when CNVI has background activity. BUG=b:201263040 TEST=Turn on this setting and build and verify on Drawcia. The SLP_S0 toggling become slower or gone at the same CNVI background activity. Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63675 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-22nb/intel/i945/memmap.c: Fix TOLUD bit field maskPetr Cvek
Register TOLUD is defined as bit field 7:3 (section 5.1.26, page 103, i945GM datasheet), fix the mask accordingly. Change-Id: Ia27661084e11ea93d5f0dc20bafb488ae2995b49 Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-04-22soc/amd/sabrina: enable warm reset functionalityFelix Held
Commit 3e1943ec46d04aff01c7fc755ac371e33e7a2dcb (soc/amd/cezanne: Force resets to be cold) forced all resets on Cezanne to be cold resets to work around a bug. Since the bug is fixed on Sabrina, this workaround copied over from the Cezanne code isn't needed here, so sort-of revert what the patch referenced above changed for Cezanne in the Sabrina code. BUG=b:229105416 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I785e43124a9a969eeb129454e6e15dc245625250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-22mb/google/brya/var/taniks: Configure Acoustic noise mitigationleo.chou
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:227165770 TEST=build FW and system power on. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I262ef14032e0e412c63403dbb8c8fbc6a8b03dd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-22mb/google/brya/var/taniks: Add WiFi SAR table for taniksleo.chou
Add WiFi SAR table for taniks. BUG=b:226690925 TEST=build FW and checked SAR table can load by WiFi driver. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I7b52f71b1fe49c02beaa48410495b81661b58fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/63684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-22mb/prodrive/atlas: Fix build errorEric Lai
commit c6b041a12e refactor the TPM Kconfig. MAINBOARD_HAS_LPC_TPM has changed to MEMORY_MAPPED_TPM. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Iff7e20ac271eb5b2afc9061819e2cc0cf2264cbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63773 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21mb/google/dewatt: Set SPI speed to 100Mhz on board version 3Rob Barnes
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 BRANCH=guybrush TEST=Build and boot to OS in Dewatt board version 3. Change-Id: If0318abf1fed9b1f4ba876f736fdbf92c1ea6933 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63747 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/dedede/var/kracko: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on kracko. BUG=b:223687184 TEST=emerge-dedede coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: Ib12265591e679e6b9ed34299f1256db05147eaef Reviewed-on: https://review.coreboot.org/c/coreboot/+/63111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/dedede/var/drawcia: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on drawcia. BUG=b:223687184 TEST=emerge-dedede coreboot Change-Id: I683049e9d2b10fc9455ef782ce798f1c453073bc Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on lantis. BUG=b:223687184 TEST=emerge-dedede coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: I3d8eec1d2f962d42f3be225eef8498e8b722aace Reviewed-on: https://review.coreboot.org/c/coreboot/+/63112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/nipperkin: Fix WLAN to GEN2 speedRob Barnes
Fix WLAN PCIE speed to GEN2. Dynamic switching between speeds is causing the PSP to hang when resuming from S0ix suspend. The root cause is still under investigation. Just disabling PSPP fixes the hang but causes poor PLT performance. BUG=b:228830362 BRANCH=guybrush TEST=suspend_stress_test on AC and DC Change-Id: I988365e51aca0d6515c5605b3032521cf59d8d30 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63722 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/brask/variants/moli: update overridetreeRaihow Shi
Add FW_CONFIG STORAGE and probe for UNKNOWN, NVME and eMMC. BUG=b:220039297 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-04-21soc/intel/cmn/lpc: Add APIs to enable/disable LPC write protect (WP)Subrata Banik
This patch implements two APIs to perform LPC/eSPI write protect enable/ disable operation using PCI configuration space register 0xDC (BIOS Controller). BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8ce831218025a1d682ea2ad6be76901b0345b362 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-04-21soc/intel/cmn/pch/lockdown: Perform additional SPI lock configurationSubrata Banik
This patch performs additional SPI lock configuration as per Intel Flash Security Specification. BUG=b:211954778 TEST=Able to build google/brya and verified all flash security recommendations are being met. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21soc/intel/cannonlake: Drop unused LPC BIOS Control macroSubrata Banik
This patch drops unused LPC BIOS control macros. BUG=b:211954778 TEST=Able to build and boot google/hatch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib309c6bd0f27115357f8e62200808764748f51a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-21mb/intel/adlrvp: Set half_populated true for ADL-NUsha P
Alder Lake-N has single memory controller with 64-bit bus width. Alder Lake common meminit block driver considers bus width to be 128-bit and populates the meminit data accordingly. By setting half_populated to true, only the bottom half is populated. Ideally, half_populated is used in platforms with multiple channels to enable only one half of the channel. Alder Lake N has single channel, and it would require for new structures to be defined in meminit block driver for LPx memory configurations. In order to avoid adding new structures, set half_populated to true. This has the same effect as having single channel with 64-bit width. BRANCH=NONE TEST=Build and boot ADL-N RVP. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62913 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21soc/intel/common/block/cse: Simplify CSE final opsAngel Pons
Looks like the `notify_data` struct array idea comes from the FSP 2.0 notify driver, which has a similar struct but with several additional fields. However, there's no need for this mechanism in the CSE driver because the struct only contains a condition (boolean) and a function to execute, which can be expressed as a regular if-block. Change-Id: I65fcb2fc02ea16b37c764f1fd69bdff3382fad18 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63708 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/brya/var/taeko: Add WIFI SAR support for tarloJoey Peng
Taeko/Tarlo uses the WIFI_SAR_ID field in FW_CONFIG to pick which SAR table to load. BUG=b:226684990 TEST=emerge-brya coreboot Cq-Depend: chrome-internal:4676926, chrome-internal:4686953 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I9852553f5c91494db845d45a94e2566248538bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/brya/var/osiris: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B (Micron) MT53E1G32D2NP-046 WT:B (Micron) H54G46CYRBX267 (Hynix) H54G56CYRBX247 (Hynix) K4U6E3S4AB-MGCL (Samsung) K4UBE3D4AB-MGCL (Samsung) BUG=None TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63706 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/brya: Create osiris variantDavid Wu
Create the osiris variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:229352299 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OSIRIS Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I41e088a3415add86cba87c919af23494f816bb24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63650 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21cpu/x86/fpu_enable.inc: Remove file used by romccArthur Heymans
Change-Id: I530bb217bb9a944990232dcf4e08f160b5267512 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55008 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20mb/google/skyrim: Update SPI settings for skyrimChris.Wang
Update SPI setting as below: Normal speed:33mhz Fast speed:66mhz Alt speed:66mz TPM speed:33mhz BUG=b:225213679 TEST=boot skyrim and verify spi settings. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Icbe4b9f4794f7e883c3819258ede809c3c8922b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-20mb/google/brya/var/vell: increase RFI Spread Spectrum to 6%Robert Chen
Increase RFI Spread Spectrum to 6% for Vell as RF team request. The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard as default. BUG=b:228929196 TEST=emerge-brya coreboot and pass RF test as before Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20mb/prodrive/atlas: Enable SPI TPM 2.0Lean Sheng Tan
Enable SPI dTPM using eSPI bus. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I18ca41c143ade024ee2840b619ba777b22a2a86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-20mb/prodrive/atlas: Enable UFS and ISHLean Sheng Tan
The PCI Local Bus Specification Revision 3.0 requires that multi-function devices always implement function 0. Because of this, enabling UFS (PCI device 12.7) requires ISH (PCI device 12.0) to be enabled as well. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia8b9561973640edc5f7d0f579dd640e805c0af17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-20mb/prodrive/atlas: Enable PCH PCIe RP7Lean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I3f438a7b1dff1a44a81edc8adc983d08708fdd57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-20mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVPMeera Ravindranath
In order to enable the UFS controller (PCI device 12.7), the PCI specification says that the device at function 0 in the same slot must also be enabled, which is the ISH. Therefore, this CL enables both the UFS controller and ISH. TEST=Boot to kernel and check lspci output 00:12.0 Serial controller: Intel Corporation Device 54fc 00:12.7 Mass storage controller [0109]: Intel Corporation Device 54ff Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62662 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20mb/google/brya/var/brya0: configure gpio for headsetAmanda Huang
Configure GPP_R0, GPP_R1, GPP_R2 and GPP_R3 for headset function enable with ALC5682I+MAX98360. BUG=b:202671753 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I93070a8096d43557a50e5a545227f2906e299d8e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-04-20mb/google/brya/var/brya0: Swap TPM and touchscreen I2C busAmanda Huang
Based on the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:202671753 TEST=emerge-brya coreboot Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-20Revert "mb/google/guybrush/var/dewatt: Override SPI fast speed"Rob Barnes
This reverts commit d80d88c0fec96b2fff93db87d0c83f4c6754ae7a. Reason for revert: 100Mhz should only be enabled on DeWatt on board version >=3. Enabling it on board version 2 will cause failures. BUG=b:213403891 BRANCH=guybrush TEST=Build dewatt Change-Id: I0b6acd2cda2af35ff33e89e3b339731e35d72cb1 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63746 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20commonlib/coreboot_tables.h: Don't pack structsArthur Heymans
Packing structs will result in unaligned sizes, possible causing problems for other entries. Change-Id: Ifb756ab4e3562512e1160224678a6de23f3b84ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63714 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20lib/coreboot_table.c: Use align macroArthur Heymans
Change-Id: Ie874fe2c023157fad0adc021faa45e70822208da Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20mb/bap/ode_e20XX: Drop `_PRS` from static devicesAngel Pons
The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed. Change-Id: If56267e8a68897236d5ff73322317cbef7ab2243 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20mb/ibase/mb899: Drop `_PRS` and `_DIS` from static devicesAngel Pons
The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. The no-op `_DIS` methods can also be removed for the same reason. Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed. Change-Id: I7e702e9318fbf68dbd883a145111e6beb6815b8b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20mb/protectli/vault_bsw: Drop `_PRS` from static devicesAngel Pons
The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed. Change-Id: Ic37608ac9622b37cae6d81045740a033e9aa9d4f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
This should no longer be needed because the ASL has been fixed. Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20ec/google/chromeec: Drop `_PRS` from static devicesAngel Pons
The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. Change-Id: Ief40e790fdee336fd6c786e18cd01c41fa658c2c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-20superio/smsc/mec1308: Drop `_PRS` from static devicesAngel Pons
The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the two mainboards using the MEC1308 code, `samsung/{lumpy, stumpy}`. Change-Id: I5d5cdc28c2cfaa5dfcffd656060b931208977386 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20superio/smsc/sch5545: Drop `_PRS` from static devicesAngel Pons
The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the only mainboard using the SCH5545 code, `dell/snb_ivb_workstations`. Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20mb/kontron/986lcd-m: Drop `_PRS` and `_DIS` from static devicesAngel Pons
The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. The no-op `_DIS` methods can also be removed for the same reason. Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed. Change-Id: I71275f2581b999d606f36773578b36dbdccf6452 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-04-20drivers/intel/dptf: Add support for PROP methodVarshit B Pandya
Add PROP method under \_SB.DPTF.TPWR scope which will return static worst case rest of platform power in miliWatts. This value is static, which has to configured from devicetree of overridetree for each platform BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check PROP method Scope (\_SB) { Device (DPTF) { Device (TPWR) { Method (PROP, 0, Serialized) { Return (XXXX) } } } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-20soc/intel: clean up dmi driver codeWonkyu Kim
1. Remove dmi.h as it's migrated as gpmr.header 2. Remove unused gpmr definitions 3. For old platforms, define DMI defintions in c code for less code changes. TEST=Build Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-20soc/intel/cmn/{block, pch}: Migrate GPMR driverSubrata Banik
This patch migrates GPMR driver over DMI to accommodate future SOCs with different interface (other than PCR/DMI). TEST=Able to build and boot google/redrix. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-20mb/google/brya/var/redrix: Add alias back to RP6 WWAN deviceTim Wawrzynczak
This alias name is required for the mainboard.c code to generate the appropriate power-off seqeuence for use during orderly S5 shutdown from the OS. It had been accidentally removed, but is required, so this patch adds it. BUG=b:227788351 TEST=compile Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8936a01bd3a6b908033a8c58bd4e84b30d199e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-20mb/intel/adlrvp_n: Disable SATA controllerUsha P
Disable SATA config from devicetree for ADL-N RVP, since we are not planning to use it in chrome config. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ic9dce3a0b06e1a0d0d9fa495aa406eb12557d842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-20nb/intel/snb: Reduce scope of functionsArthur Heymans
Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-20mb/google/brya/var/anahera{4es}: Enable power saving for Smart CardWisley Chen
Configure the power saving pin for Smart Card. BUG=b:229356121 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20mb/google/guybrush/var/dewatt: Override SPI fast speedKenneth Chan
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 TEST=Build and boot to OS in Dewatt board version 2. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63685 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20lib: Check for non-existent DIMMs in check_if_dimm_changedEric Lai
Treat dimm addr_map 0 non-existent. addr_map default is 0, we don't set it if Hw is not present. Also change the test case default to avoid 0. SODIMM SMbus address 0x50 to 0x53 is commonly used. BUG=b:213964936 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The MRC training does not be performed again after rebooting. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac Reviewed-on: https://review.coreboot.org/c/coreboot/+/63628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19drivers/usb/pci_xhci: Add Sabrina xhci pci device idKarthikeyan Ramasubramanian
BUG=None TEST=Build and boot to OS in Skyrim. Ensure that the XHCI controllers are enumerated successfully and ACPI device objects are added in SSDT. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7ad4555212ed38ea0f9029275345e4945855a8c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-19mb/google/brya: Disable PCH USB2 phy power gating for felwinterSridhar Siricilla
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for felwinter board. Please refer Intel doc#723158 for more information. BUG=b:221461379, b:226020977 TEST=Verify the build for felwinter board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-19mb/google/brask/variants/moli: update type-c setting in overridetreeRaihow Shi
Add conn1 for pch_espi and add type-c port2 for pmc_mux. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-19mb/google/brask/variants/moli: add delay time to rtd3-coldRaihow Shi
This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence, the reason is that the rise and fall times of each signal may differ by board, and so those board-specific delays must be taken into account when power sequencing. We checked power on sequence requires enable pin prior to reset pin, so added delay to meet the sequence. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:228907551 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/brask/variants/moli: remove i2c1 in overridetreeRaihow Shi
Remove i2c1 because brask devicetree is already has it. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/skyrim: Configure Pen Detect deviceIan Feng
Enable pen garage. Pen detect is active low. BUG=b:229168203 TEST:Build and boot to OS in skyrim. Evtest work as expected Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 1 Properties: Testing ... (interrupt to exit) Event: time 1649922170.578779, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649922170.578779, -------------- SYN_REPORT ------------ Event: time 1649922172.070740, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I3bb07af6aebdc355a73148d8be79b1014147f61d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-19mb/google/skyrim: Add Goodix touchscreenIan Feng
Add Goodix touchscreen according to the Programming Guide Rev.0.7 BUG=b:228907558 TEST=local build and tested with Goodix touch screen Change-Id: I35dd3ca76e9e0f17508bef46c90b53b4be5d0033 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63573 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19mb/google/brask: fix boot beepDtrain Hsu
Fix the issue that can't hear the boot beep at dev screen. GPP_B14 is used for PWM_PP3300_BUZZER and it should set to GPO. Modify GPP_B14 from PAD_CFG_NF_LOCK to PAD_CFG_GPO_LOCK. BUG=b:229345416 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot and verify if the buzzer beeps. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I601735ab20974cd992ca5dd6dbaca1517a395aa2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63645 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19mb/google/brask/variants/moli: Pick VBT based on FW_CONFIGRaihow Shi
Pick specific VBTs for HDMI, DP, and ABSENT according to FW_CONFIG. BUG=b:220241277 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Icc8fbef1467605505459fce264697f670591c81e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63604 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19mb/google/brya/var/anahera{4es}: select DRIVERS_GENESYSLOGIC_GL9750Wisley Chen
select DRIVERS_GENESYSLOGIC_GL9750 to disable ASPM L0s. BUG=b:229213455 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ie89fa6c66974284063cd25ae8097db94a93326ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/63638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-19Kconfig: Make HAVE_EM100_SUPPORT invisibleArthur Heymans
This is a property of a platform and should not be exposed to the user. Change-Id: I34f9097d40b2bf732cecf30bf13ba5a413dd53a5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-19cpu/x86/Kconfig*: Guard with ARCH_X86Arthur Heymans
None of these options make sense on different ARCH. Change-Id: Ie90ad24ff9013e38c42f10285cc3b546a3cc0571 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63673 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19soc/intel/alderlake: Enable Pre Reset CPU TelemetryBora Guvendik
Insert CSE timestamps to coreboot timestamp table. BUG=b:182575295 TEST=Boot to OS on Brya Redrix board. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ifbea7155a294e0039a5bd1d16588775e90a29ae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/nissa: Add gpio lock pinsEric Lai
Followed the Brya series to lock the gpio pins in baseboard. Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216671701 TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that nivviks boots successfully to kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-19mb/google/brya: Add Kconfig for TPM I2C busRaihow Shi
Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:229200525 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/brya/var/crota: Kconfig: Select TPM I2C bus driverTerry Chen
Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:226315394 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/guybrush/var/dewatt: Update APU STT settingChris.Wang
update STT setting for dewatt. BUG=b:228040295 BRANCH=guybrush TEST=build, verify the parameter has been applied to the system by checking the AGT tool. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Id319d42747dd0d5f6a9ca727635d85e6b9bd65af Reviewed-on: https://review.coreboot.org/c/coreboot/+/63699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-19soc/intel/cmn/fast_spi: Add API to set SPI controller VCLSubrata Banik
This patch creates a helper function to set SPI controller VCL bit as recommended by Intel Flash Security Specification. BUG=b:211954778 TEST=Able to build google/brya and verified that SPI flash controller MMIO register 0xC4 bit 30 is set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie9a12db1bab81779fd8e7db90221d08da3c65011 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-19soc/intel/cmn/fast_spi: Add API to clear outstanding SPI statusSubrata Banik
This patch creates a helper function to clear HSFSTS_CTL (offset 0x04) register Bits 0 to 4. As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation, it's important to clear all SPI outstanding status before setting SPI lock bits. BUG=b:211954778 TEST=Able to build google/brya with this patch and clear SPI controller HSFSTS_CTL register Bits 0 to 4. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I62adba0d0cef1d4c53b24800f90b4fe76a9d78b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-19soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In ProgressSubrata Banik
This patch creates a helper function to check if any SPI transaction is pending. As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation, it's important to ensure there is no pending SPI transaction before setting SPI lock bits. BUG=b:211954778 TEST=Able to build google/brya with this patch and no error msg seen due to `SPI transaction is pending`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-19soc/intel/cmn/lpc: Fix typo from FAST_SPIBAR to LPCSubrata Banik
BUG=b:211954778 TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib8cc4b8d13b61e3935f2050d25ce0278162c91c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-19soc/intel/cmn/fast_spi: Use tab instead spaceSubrata Banik
This patch converts whitespace into tabs to maintain the uniformity across the fast_spi_def.h file. BUG=b:211954778 TEST=Able to build google/brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I56bcd263c6a5c0036e459926a25538e3448fbce6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-04-18mb/google/guybrush: Remove EC_ENABLE_LID_SWITCHRob Barnes
Remove EC_ENABLE_LID_SWITCH since this causes a duplicate SW_LID entries. The other SW_LID entry is generated by MKBP. BUG=b:228907256 BRANCH=guybrush TEST=Lid open close triggers events on Nipperkin Change-Id: I5c1cf7aeac8405bce7bfc77110eceaf3e5383fe7 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-18mb/google/guybrush/var/nipperkin: turn off WLAN ASPM L1ssKevin Chiu
BUG=b:227296841 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass PLT criteria: S0 > 600ms, s0i3 > 14 days Change-Id: I9c61e1d0f3db8b9885040255d6de266616768b68 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-04-18mb/hp/z220_series: Add Z220 CMT Workstation variantDamien Zammit
This is based on previous work done by a good friend of mine. The notable differences between this board and the SFF variant is that: - CMT has 4 more PCI/PCIe ports than SFF. - CMT has 2 more SATA ports than SFF. TESTED on Z220 CMT Workstation (boots to payload) Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-16mb/lenovo/t440p/Kconfig: Reorder selects alphabeticallyFelix Singer
Built lenovo/t440p with BUILD_TIMELESS=1 and coreboot.rom remains the same. Change-Id: I7bac7ad5236346a3c2a8928ecdfadde6564ff232 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-16mb/lenovo/t440p/dsdt.asl: Remove redundant commentFelix Singer
Change-Id: Ie772701192a3589b51642df446f0b2527fb7d630 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-14mb/google/guybrush: Set BT USB to use GPIO for statusTim Van Patten
Set the BT USB device to use GPIO for the power status. This causes an ACPI `_STA()` function to be generated that returns the power status of the BT USB device, rather than always returning `0x1`. This `_STA()` function can be used during boot to skip enabling the device (and performing the associated sleep) if the device is already powered on. BRANCH=None BUG=b:225022810 TEST=Dump SSDT table for guybrush Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I72f6b28671efddfbef53f328d904a05f73f39efa Reviewed-on: https://review.coreboot.org/c/coreboot/+/63559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-14src/acpi/device: Early return in _ON if device already enabledTim Van Patten
If the device has enabled `use_gpio_for_status`, then call the `_STA` method in `_ON` to determine if the device is already enabled. If it is already enabled, return early to skip re-enabling the device and performing the associated sleep. This change is necessary since the Linux kernel does not call `_STA` before calling `_ON`. BRANCH=None BUG=b:225022810 TEST=Dump SSDT table for guybrush Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I13aa41766555953b86eded4c72e3b317fe6db5c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63613 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-14drivers/usb/acpi: acpi_power_res_params: Add use_gpio_for_statusTim Van Patten
Add the member `use_gpio_for_status` to the structure `drivers_usb_acpi_config`, so the `devicetree.cb` can specify it. This field is then used to initialize the corresponding field in the structure `acpi_power_res_params` in `usb_acpi_fill_ssdt_generator()`. The member `acpi_power_res_params::use_gpio_for_status()` is already being used by `acpi_device_add_power_res()` to determine which version of the `_STA()` method to output. BRANCH=None BUG=b:225022810 TEST=Dump SSDT table for guybrush Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I69eb5f1ad79f3b2980f43dcf4a36585fca198ec9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-14coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_tJianjun Wang
Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no longer needed. Also replace 'struct cbuint64' with 'cb_uint64_t' and remove 'cb_unpack64' in libpayload for compatible with lb_uint64_t. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-14mb/google/skyrim: Inject SPDs into APCBKarthikeyan Ramasubramanian
Update the build scripts to inject variant specific SPDs into APCB. BUG=None TEST=Build and boot to OS in Skyrim boards with all the concerned memory parts. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3b3f6f248d54681c6f55c00660d1f2988ae906ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63600 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-14mb/google/skyrim/var/skyrim: Add supported memory partsKarthikeyan Ramasubramanian
Add supported memory parts and generate the associated DRAM part ID. Also for MT62F2G32D8DR-031 WT:B memory part, add a custom SPD that configures the DRAM speed at 5500 MHz. Use this custom SPD until that part can operate at full speed (i.e. 6400 MHz). BUG=None TEST=Build Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id87e79f5d6187d57d74487841c09aa309f1450b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-14mb/google/brya/var/kano: Configure Acoustic noise mitigationDavid Wu
Setup the following acoustic noise mitigation features: 1) Slew rate for both IA and GT domains to 1/8 2) Disable Fast package C ramp BUG=b:229046516 TEST=build and verified by power team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ifb5700391e33818878994f205acae7ee3b1b96d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-14mb/prodrive/atlas: Update KconfigLean Sheng Tan
Update Kconfig per Atlas usages: 1. Set EC I/O mapped UART as default UART output 2. Add EC IFD region & ACPI support Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I970de724237bcb08899aed7a4b87a23c5cdb0b48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-04-14soc/amd/sabrina: Allow to specify custom SPL FileKarthikeyan Ramasubramanian
PSP needs SPL file to boot. Introduce the support to add SPL file. Currently Sabrina does not have a specific SPL file. Use Cezanne SPL file as a placeholder. BUG=b:224618411 TEST=Build and boot to OS in Skyrim after adding Sabrina specific SPL file. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63313 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-14mb/google/nipperkin: Disable PSPP for WLANRob Barnes
Disable PSPP parameters for WLAN card on Nipperkin. This feature is causing S0ix resume hangs. BUG=b:227296841,b:228830362 BRANCH=guybrush TEST=Suspend stress test passes on Nipperkin Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I38f05b92ace4aba61163194a6a638915882b8871 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63593 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-14x86/mtrr: Print address ranges inclusive to be more consistentWerner Zeh
The printed address ranges in the tree (resource allocator and even some MTRR code) usually shows the range inclusive (meaning from start address to the real end address of the range). Though there is still some code in the MTRR context which prints the ranges with an exclusive end. This patch aligns the printing of ranges in the MTRR code to be consistent among the tree so that the shown end addresses are now inclusive. Change-Id: I0ca292f9cf272564cb5ef1c4ea38f5c483605c94 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 15:02:12 +0000