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2022-01-28src/{drivers,soc}: Fix some code indentsElyes HAOUAS
Change-Id: I55682de4a1bc74f170e2044de35b0d8d53ef51ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-28soc/intel/common/cse: skip heci_init() if HECI1 is disabledMatt DeVillier
If the HECI1 PCI device is disabled, either via devicetree or other method (HAP, me_cleaner), then we don't want/need to program a BAR, set the PCI config, or call heci_reset(), as the latter will result in a 15s timeout delay when booting. Test: build/boot Purism Librem 13v2, verify heci_reset() timeout delay is no longer present. Change-Id: I0babe417173d10e37327538dc9e7aae980225367 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-28mb/google/brya: Remove EC_GOOGLE_CHROMEEC_ACPI_MEMMAP KconfigTim Wawrzynczak
The EC_GOOGLE_CHROMEEC_ACPI_MEMMAP is intended for Chrome microchip ECs only, which have different requirements as to the amount of memory mapped space they can claim. The brya family of boards does not use any microchip ECs, therefore remove this Kconfig. BUG=b:214460174 TEST=boot brya4es to kernel, no EC errors seen in cbmem log, EC software sync still works. Change-Id: I6e9858f29d079140ec43341de90f222b03986edb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-28mb/google/dedede/var/drawcia: Change power sequencing of Camera and VCMVarshit B Pandya
Drawcia's MIPI camera sensor and VCM both share the same reset GPIO from the PCH. The current power sequence does not take this into account, and this leads to an unbalanced ref count of the reset GPIO, which can cause one or the other of the devices to reset unexpectedly. This patch corrects that by explicitly sequencing the reset GPIO for both devices, which the builtin refcounting of this driver will automatically handle. BUG=b:214665783 TEST=Build, boot to OS and check VCM once camera stream off Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Ib676fd1f43dbd9cf75e4aff01baab4a4bb4e2a89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-28driver/intel/mipi_camera: Increase max power ops count to 6Varshit B Pandya
Current max count for camera power ops is 5 which is not sufficient. If we increase the ops by 1 in current variants the compiler will not throw error for intel mipi camera driver. Hence increase current max count for camera power ops to 6 from 5. BUG=b:214665783 TEST=Build and boot to OS Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I4f4c090f2275616816dfc697f27520cd1cbc1a80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61146 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-28soc/intel/alderlake: Enable CPPCv3Sridahr Siricilla
The patch defines the following helper functions: get_cpu_scaling_factor(): Returns scaling factors of big and small core. cpu_is_nominal_freq_supported(): Returns true if CPU supports Nominal Frequency, otherwise false. cpu_is_nominal_freq_supported(): Check CPU supports nominal frequency or not. The patch also enables CPPCv3 support for Intel Alder Lake which is based on hybrid core architecture. TEST=Verified Nominal Frequency and Nominal Performance are getting updated for ADL-P small and big cores correctly. Signed-off-by: Sridahr Siricilla <sridhar.siricilla@intel.com> Change-Id: I963690a4fadad322095d202bcc08c92dcd845360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-28soc/intel/common: Implement ACPI CPPCv3 package to support hybrid coreSridhar Siricilla
The patch implements ACPI CPPCv3 package. It implements and updates the following methods: generate_cppc_entries(): Updates method to support CPPCv3 package acpi_get_cpu_nominal_freq(): Calculates CPU's nominal frequency acpi_get_cpu_nomi_perf(): Calculates nominal performance for big and small cores. acpigen_write_CPPC_hybrid_method(): It generates ACPI code to implement _CPC method. acpigen_cppc_update_nominal_freq_perf(): It updates CPPC3 package if cpu supports Nominal Frequency. It generates ACPI code which sets Nominal Frequency and updates Nominal Performance. It uses below calculation to update the Nominal Frequency and Nominal Performance: Nominal Frequency = Max non-turbo ratio * cpu_bus_frequency Nominal Performance = Max non-turn ratio * cpu scaling factor CPU scaling factor varies in the hybrid core environment. So, the generated ACPI code updates Nominal Performance based on the CPU's scaling factor. TEST=Verified CPPCv3 package is getting created in the SSDT table. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: ravindr1 <ravindra@intel.com> Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-28ec/google/chromeec: Consider custom_pld when checking USB port numberWon Chung
Currently only PLD group is used to check USB port number. In the future, we want to use custom PLD fields, so custom PLD should also be considered when checking USB port number. BUG=b:216376040 TEST=emerge-brya coreboot & SSDT dump in Brya test device Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Id8076a2a952de61a6f38fbdecd76e991487bf696 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-27soc/amd/sabrina/chipset.cb: update USB portsFelix Held
The corresponding mainboard design guide was used as a reference here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie61af7dab35b560d2eec1ea62058f3a4dad5cb0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina/include/smu: update mailbox SMN addressesFelix Held
The SMU message response register was moved compared to Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie384de52b1efb1d52f9018315a4b72916a4c9cee Reviewed-on: https://review.coreboot.org/c/coreboot/+/61095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina/include/southbridge: add new I2C_PAD_CTRL bitsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iac1b7308851c34bd1556c02af6b270e9346073e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: drop PM_ESPI_CS_USE_DATA2 define and eSPI util codeFelix Held
The Sabrina SoC doesn't have the PM_ESPI_CS_USE_DATA2 bit defined in the PM_SPI_PAD_PU_PD register. It also doesn't have a physical LPC interface any more, so there are no LPC pins that can be reconfigured as eSPI interface. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I02bc8d007901c71942475fe707637c5da7227230 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: drop CPPC codeFelix Held
The CPPC feature isn't available on the Sabrina SoC, so drop the corresponding code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71a1b0717571729ebca3600ac433e621cafc4e61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: update PCI devices in devicetree.cbFelix Held
Also update mb/amd/chausie accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb4dcffa48c3dbdcffb66f1398b99ee96562efb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: update pci_devs.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic0226afd9e7fffd6bf196f06ee6c34b6b9c92f30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina/fsp_m_params: drop sata_enable UPD writeFelix Held
There are no SATA controllers on the Sabrina SoC. The UPD field will be removed later as a part of the initial UPD header update. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iedefd9f150e5bcb78173288e5fc9f1bbd6b498cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-01-27soc/amd/sabrina/include: update smi.hFelix Held
Some of the names have slightly changed in the PPR, but I kept the current names for consistency across all AMD SoCs in coreboot. Revision 1.50 of the PPR #57243 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6bda656015858a57e221b8d7819f944c21564a39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina/include/data_fabric: update IOMS0_FABRIC_IDFelix Held
The data fabric ID table in PPR #57243 Rev 1.50 has a different IOMS0 fabric ID than Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32890b5c03219f6ebf8180929d71ef726d382483 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-01-27soc/amd/sabrina: drop graphics.cFelix Held
Since we don't need to support PCI ID remapping for finding the correct VBIOS binary for the integrated GPU, graphics.c can be dropped for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd5b678f472b3b5888353efd057203eb641be874 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina/cpu: update CPUIDFelix Held
Sabrina is family 17h model A0h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I01e02e3491fb90941c767058986da876bdf7ca1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: add additional UART controllersFelix Held
Compared to Cezanne there are 3 more UART controllers. Revision 1.50 of the PPR #57243 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I628b1a7a0930f3409acdcabda2b864d42bf6bd23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-01-27soc/amd/sabrina/gpio: update GPIO definitions and gpio_event_tableFelix Held
The GPIO and GPIO MUX mapping as well as some GPIO to GEVENT mappings have changed compared to Cezanne. Sabrina also doesn't have a remote GPIO bank. Revision 1.50 of PPR #57243 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iabb85a3d24c881055e94400d08d01505df44a07a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-01-27soc/amd/sabrina/include/amd_pci_int_defs: add additional UARTsFelix Held
Compared to Cezanne there are 3 more UARTs controllers. The PCI interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't contain a PIRQ mapping for UART4. The reference code has a mapping for this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5. Since the I2C5 controller isn't owned by the x86 side and I didn't see any mapping of the I2C5 controller into the x86 MMIO space, this seems very plausible. Also add the corresponding fields to the ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27mb/google/brya/var/taniks: Enable Bayhub LV2 driverJoey Peng
Some SKUs of google/taniks have a Bayhub LV2 card reader chip, therefore enable the corresponding driver for the mainboard. BUG=b:215487382 TEST=Build FW and checking SD card reader register is correct. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I34adb122bd2edc343e894a53bc12e105f4225984 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-27drivers/intel/usb4/retimer: Use usb4_retimer_scope replace dev pathEric Lai
Without acpi name, acpi_device_path will return NULL. <NULL>: Intel USB4 Retimer at GENERIC: 0.0 Replace with usb4_retimer_scope for the identify. BUG=b:215742472 TEST=show below meaasge in coreboot log \_SB.PCI0.TMD0.HR : Intel USB4 Retimer at GENERIC: 0.0 \_SB.PCI0.TMD1.HR : Intel USB4 Retimer at GENERIC: 0.0 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idfa8b204894409b11936e5f221c218daa206cc02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-27cpu/intel/socket_p: Drop 'select SSE'Elyes HAOUAS
SSE is already selected by SSE2 through model_{1067x,6fx}/Kconfig Change-Id: I3641118905f1fcc1e34d7fe4f7ca3082c3cf0d3b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27cpu/intel/socket_m: Drop 'select SSE'Elyes HAOUAS
SSE is already slected by SSE2 through model_6{e,f}x/Kconfig Change-Id: Ibe215cfe6aa6d7c215dd62e1ab2966d079c2a78d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27cpu/intel/socket_LGA775: Drop 'select SSE'Elyes HAOUAS
SSE is already selected by SSE2 through model_1067x/Kconfig Change-Id: I7b16af0277dc01c5905c5990244d3738a33723b3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27cpu/intel/socket_FCBGA559: Drop 'select SSE'Elyes HAOUAS
SSE is already selected by SSE2 through model_106cx/Kconfig Change-Id: I31b8345fdd901e1d05df5fa8351db3255f9cf9cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use <device/dram/ddr3.h> macrosElyes HAOUAS
Change-Id: Icca870d1c97a2737dec3f31b0f2e4c3222c711ae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use DDR3_SPD_SODIMM macroElyes HAOUAS
Change-Id: Ibbb6e6d44b1415b18aa59310f4d36d61b9a2a080 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use <smbios.h> macrosElyes HAOUAS
Use macros defined in <smbios.h> for 'ddr_type' and 'bus_width' Change-Id: I0501147139387cd9b5c7ec6b7ba7f8a5c5bd18bb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27mb/google/kukui: Add DRAM support for burnet/escheKevin Chiu
0x18 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:B 0x19 HYNIX 4GB LP4X H54G56CYRBX247 0x1a SAMSUNG 4GB LP4X K4UBE3D4AB-MGCL 0x1b HYNIX 8GB LP4X H54G68CYRBX248 BUG=b:165768895 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: Ib1c09ff2b88bf121de702985680b2388c0fb8427 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-01-27mb/google/kukui: Add dedicated memory map for kappaKevin Chiu
Add a dedicated memory mapping table starting at index 0x40: 0x40 SAMSUNG 4GB LP4X K4UBE3D4AA-MGCR 0x41 HYNIX 4GB QDP LP4X H9HCNNNCPMALHR-NEE 0x42 MICRON 4GB LP4X MT53E1G32D4NQ-046 WT:E 0x43 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:A 0x44 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:B 0x45 HYNIX 4GB LP4X H54G56CYRBX247 0x46 SAMSUNG 4GB LP4X K4UBE3D4AB-MGCL 0x48 SAMSUNG 4GB LP4X K4UBE3D4AA-MGCL 0x49 MICRON 8GB LP4X MT53E2G32D4NQ-046 WT:A 0x4A HYNIX 4GB QDP LP4X H9HCNNNCPMMLXR-NEE 0x4B Micron MT29VZZZAD9GQFSM BUG=b:162379736 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I97f296cb8c35fd2f979a05d0b97a0562c1b472f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-01-27mb/google/dedede/var/metaknight: Set core display clock to 172.8 MHzDavid Wu
When using the default initial core display clock frequency, Metaknight has a rare stability issue where the startup of Chrome OS in secure mode may hang. Slowing the initial core display clock frequency down to 172.8 MHz as per Intel recommendation avoids this problem. The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0 (172.8 MHz) for metaknight. BUG=None BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode well. Change-Id: I987277fec2656fe6f10827bc6685d3d04093235e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-01-27mb/google/brya/variants/volmar: Init devicetree for volmarDavid Wu
Init basic override devicetree based on schematics BUG=b:211891086 TEST=FW_NAME="volmar" emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I40b364e3df2f04a6b828f4f288667b96b6e0bd22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-01-27mb/google/brya/var/brask: set tcc_offset value to 10℃David Wu
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:214890058 BRANCH=None TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I86acb172ed427d45973b9360e0413978cbd46645 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-27soc/intel/common/cse: Drop CSE library usage in bootblockSubrata Banik
This patch drops the CSE common code block from getting compiled in bootblock without any SoC code using heci communication so early in the boot flow. BUG=none TEST=Able to build brya, purism/librem_skl without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib4d221c6f19b60aeaf64696e64d0c4209dbf14e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-01-27soc/intel/skylake: move heci_init() from bootblock to romstageMatt DeVillier
Aligns with all other soc/intel/common platforms calling heci_init(). Test: build/boot Purism Librem 13v2 Change-Id: I43029426c5683077c111b3382cf4c8773b3e5b20 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61378 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-27mb/google/zork/var/vilboz: Add new memory K4AAG165WB-BCWEFrank Wu
Add new ram_id:1100 for memory part K4AAG165WB-BCWE. BUG=b:212507858 TEST=Generate new spd file and build coreboot. Then boot from the DUT with new memory K4AAG165WB-BCWE Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I4e409a5a5a3b3d1b0013d2c020eeb4c0aeec51ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/60191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-26src: Add missing 'void' in function definitionElyes HAOUAS
Change-Id: I7fa1f9402b177a036f08bf99c98a6191c35fa0b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-26vc/amd/agesa: fix out-of-bounds readJason Nien
Fix the out-of-bounds read issue found by Coverity. TEST=none Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I01e134cb6b025bf7cb5030cd9378297d7f6df509 Reported-by: Coverity (CID:1376956) Reviewed-on: https://review.coreboot.org/c/coreboot/+/58803 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-26soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-MMatt DeVillier
Commit b67c5ed [3rdparty/fsp: Update submodule pointer to newest master] updated the FSP binaries/headers for Comet Lake, which included a change moving PcieRpHotPlug from FSP-S to FSP-M. Unfortunately the existing UDP in FSP-S was left in and deprecated, which allowed the change to go unnoticed until it was discovered that hotplug wasn't working. Since other related platforms (WHL, CFL) share the SoC code but use different FSP packages, add the setting of the PcieRpHotPlug UPD to romstage/FSP-M and guard it with '#if CONFIG(SOC_INTEL_COMETLAKE)'. Test: build/boot Purism Librem 14, verify WiFi killswitch operates as expected / WiFi is re-enabled when turning switch to on position. Change-Id: I4e1c2ea909933ab21921e63ddeb31cefe1ceef13 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-26soc/intel/denverton_ns: Fix logging levelKyösti Mälkki
Level should match that used in print_num_status_bits(). Change-Id: I1beb65e4c141e195dd59eaa2bf55fff6e7dc910d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-26Revert "mb/google/brya/var/brask: Configure the ISOLATE pin of LAN"Alan Huang
This reverts commit 2bf2e6d1ccd87cdd8d9c189972eae89e47e542c8. According to the latest schematics, Brask supports D3-Hot for RTL8125 and does not need to operate the ISOLATE pin. BUG=b:193750191 BRANCH=None TEST=emerge-brask coreboot chromeos-bootimage Test with command suspend_stress_test Change-Id: Ica6bfb810887861f6b17ff527373824547e2406c Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-26mb/google/brya/var/kano: Reduce reset delay time to 20ms for ELAN TSDavid Wu
Set register "reset_delay_ms" to 20 to reduce power resume time. BUG=b:204009580 TEST=tested on kano Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib0695edd7c342c65df9138b1590281c5f442769b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-26mb/google/guybrush/var/dewatt: Update Elan touchpad interrupt triggerKenneth Chan
Update Elan touchpad interrupt trigger to level low from edge low to keep consistency with Synaptics touchpad. Checked with Elan PM Iris and other projects(spherion), the touchpad can be set to edge or level low trigger. Sepherion Elan touchpad IRQ setting: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.4/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi;l=415?q=mt8192-asurada.dtsi&ss=chromiumos%2Fchromiumos%2Fcodesearch:src%2Fthird_party%2Fkernel%2F BUG=b:214143249 TEST=emerge-guybrush coreboot chromeos-bootimage; Tested Elan and Synaptics touchpad wakeup from s0i3 well with proto build. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ifac49b131cadc1f8838bb6243ad6d17feb272bd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-26mb/google/guybrush/var/dewatt: Update touchpad GPIO configurationKenneth Chan
Update GPIO configuration to fix Synaptics touchpad can't wakeup system from s0i3. BUG=b:214143249 TEST=emerge-guybrush coreboot chromeos-bootimage; Tested Synaptics touchpad wakeup from S3 with proto build. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I29734595d37283adc6fd4a0ed17f51a5c9061796 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-01-26soc/intel/alderlake: Add GPIO Controller device ID for ADL-NUsha P
Add PCH ACPI Device ID for Alder Lake N SOC GPIO Controller. Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I6eb15751dd303b4b445cb64f25a040302e50c09d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-01-26soc/mediatek/mt8186: Use BIT() macro for arbiter enable bitRex-BC Chen
Replace (1 << x) with BIT(x) in pmic_wrap.h. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I463589f02065a228a8af74447b4586e5b54e0b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61351 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-26soc/intel/alderlake: Choose non-posted write to lock GPIO PADSubrata Banik
Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI config on Alder Lake to instruct Pad Configuration Lock to use non-posted sideband writes as posted write is not supported on Alder Lake while locking GPIO pads. BUG=b:211573253, b:211950520 TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id8d394b97de9c328b3f75df3649d7efc782f006b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-26soc/intel/alderlake: Skip FSP to unlock GPIO PadsSubrata Banik
This patch makes FSP-S skip unlocking the GPIO Pads. BUG=b:211573253, b:211950520 TEST=FSP-S debug log below: Without this change: UnlockGpioPads= 1 With this changes UnlockGpioPads= 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I236a19a67372e9668e304d0054d477daff6a0266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-26soc/intel/common/gpio: Rework PAD config macro to add lock supportSubrata Banik
This patch extends `struct pad_config` to add new variable for gpio lock action. Additionally, it creates new GPIO PAD configuration macros that perform GPIO pad configuration and pad lock configuration as well. List of new macros are: 1. PAD_CFG_NF_LOCK 2. PAD_CFG_GPO_LOCK 3. PAD_CFG_GPI_LOCK 4. PAD_CFG_GPI_TRIG_OWN_LOCK 5. PAD_CFG_GPI_GPIO_DRIVER_LOCK 6. PAD_CFG_GPI_INT_LOCK 7. PAD_CFG_GPI_APIC_LOCK 8. PAD_CFG_GPI_IRQ_WAKE_LOCK Mainboard users can use the above macros to lock the PAD after configuration. So far on IA chipset, the default GPIO pad lock configuration reset type is POWERGOOD hence, it's recommended as per GPIO BWG (doc: 630603) to configure the GPP PAD reset type the same as lock configuration reset type to avoid GPP reset value misconfiguration issue. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-26soc/intel/common/gpio: Perform GPIO PAD lock outside SMMSubrata Banik
This patch performs GPIO PAD lock configuration in non-smm mode. Typically, coreboot enables SMI at latest boot phase post FSP-S, hence, FSP-S might get chance to perform GPP lock configuration. With this code changes, coreboot is able to perform GPIO PAD lock configuration early in the boot flow, prior to calling FSP-S. Also, this patch ensures to have two possible options as per GPIO BWG to lock the GPIO PAD configuration. 1. Using SBI message with opcode 0x13 2. Using Private Configuration Register (PCR) BUG=b:211573253, b:211950520 TEST=Able to build and boot brya variant with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I71b4e2f24303b6acb56debd581bd6bc818b6f926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60801 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-26mb/google/guybrush/dewatt: Add variant to disable HDMIZheng Bao
For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. get_cpu_count() == 4 && get_threads_per_core() == 2: This case is for 2 Core and 4 Thread CPU (2C/4T for short). get_cpu_count() == 2: This is for 2C/2T. This is for a possible future case. BUG=b:208677293 Change-Id: I8d0fa96818a768b7960d92821b927dbc622675ae Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
2022-01-26soc/amd/cezanne,picasso,sabrina: factor out get_threads_per_coreFelix Held
This code is common to at least all Zen-based APUs (Picasso, Cezanne, Sabrina) and is also useful outside of the SoC-specific dynamic ACPI table generation code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie96d4429fb6ed9223efed9b3c754e04052d7ca7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-by: Eric Peers <epeers@google.com>
2022-01-26soc/mediatek/mt8186: Update PWRAP arbiter enable bitRex-BC Chen
There is no wakeup source when we test function of suspend and resume. The root cause is that the monitor enable bit of PWRAP is not configured correctly. BUG=b:213255218, b:214978483 TEST=receive wakeup source from MT6366 successfully Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I324d18fa5d3cd745c35fcf0f207e1b444b5e898b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61330 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-26soc/amd/common: Don't reserve VERSTAGE region when using PSP verstageRaul E Rangel
The VERSTAGE region is only needed when running verstage in the x86. This change reduces the early ram size by 512 KiB when using PSP verstage. BUG=none TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I45ce421397807dbb1eb48aedd05209b91e89aa4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-25mb/google/guybrush/var/nipperkin: Add Board values for eDP tuningZheng Bao
Reference test document, update tuning registers from pass experiment setting of phy_settings. The document about eDP tuning can be gotten from the issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-25soc/amd/cezanne: FSP: Add UPD entry for eDP tuningZheng Bao
The FSP gets these values from the UPD and sets the internal values. The document about eDP tuning is attached in issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Cq-Depend: chrome-internal:4303901 Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-25mb/system76: Enable SrcClk pin for CPU PCIe RPsTim Crawford
This reverts commit bd9b044a96cc ("mb/system76: rtd3: Remove SrcClk pin on CPU RP"). Previously, RTD3 expected a PCH index for the root port and did not work with the CPU PCIe RP present on TGL, so SrcClk pin was disabled. Set them now that RTD3 supports mapping the index for the CPU RP. Change-Id: Ia7519b9f5a2be52cd5575615c28d20371a26996b Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-01-25mb/google/brya/var/taniks: Modify DPTF settings for taniksJoey Peng
Update DPTF settings provided by thermal team BUG=b:215033682 TEST=build and tested on taniks board Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ic6860980b06e876dd4c21af26752ab6c1a3f7fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/61337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-25mb/google/brya/var/taniks: swap TPM i2c with TS i2c for next buildJoey Peng
Taniks is going to exchange i2c port for touchscreen and cr50. BUG=b:215039999 TEST=emerge-brya coreboot Cq-Depend:chromium:3397562 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I179949887f6d8f4bbdff7d806319e2ac368ebc2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-25mb/google/brya/var/taniks: Run time probe for NVMe SSD and MMCJoey Peng
Taniks will use two PCIE port signals with one slot, one CLK and one CLKREQ at next build. In order to accommodate this, probe statements are added to the devicetree. This only affects NVME SSD and EMMC. BUG=b:215040000 TEST=Build FSP with debug output enabled, and observe the correct root ports being initialized depending on the FW_CONFIG values for BOOT_EMMC and BOOT_NVME. Cq-Depend:chromium:3397561 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2ead505088f19fd3bf9768b541838395c82ef051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-25mb/siemens/mc_ehl: Prevent reset when TCO expiresWerner Zeh
In order to guarantee data integrity an expired TCO must not hard reset the board. Select the Kconfig switch to prevent this reset. Change-Id: I04080c6bcd486e3a406438cc7a703165bb6945a0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-25soc/intel/ehl: Add Kconfig option to disable reset on TCO expirationWerner Zeh
The TCO timer is the default watchdog of an x86 host and can reset the system once it has expired for the second time. There are applications where this reset is not acceptable while the TCO is used. In these applications the TCO expire event generates an interrupt and software takes care. There is a bit in the TCO1_CNT register on Elkhart Lake to prevent this reset on expiration (called NO_REBOOT, see doc #636722 ). This bit can either be strapped on hardware or set in this register to avoid the reset on expiration. While the hardware strap cannot be overridden in software, the pure software solution is more flexible. Unfortunately, the location for this bit differs among the different platforms. This is why it has to be handled on soc level rather than on TCO common code level. This commit adds a Kconfig option where NO_REBOOT can be enabled. This makes it easy to reach this feature over to the mainboard where it can be selected if needed. Change-Id: Iaa81bfbe688edd717aa02db86f0a93fecdfcd16b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-25northbridge/intel/i945: Change types to uintptr_t where appropriateElyes HAOUAS
Prepares compilation for x86_64 by avoiding casts to different sizes. Current patch fixes: 1. src/northbridge/intel/i945/raminit.c: In function 'ram_read32': src/northbridge/intel/i945/raminit.c:77:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 77 | read32((void *)offset); | ^ 2. src/northbridge/intel/i945/rcven.c: In function 'sample_strobes': src/northbridge/intel/i945/rcven.c:29:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 29 | read32((void *)addr); | ^ src/northbridge/intel/i945/rcven.c:30:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 30 | read32((void *)(addr + 0x80)); | ^ 3. src/northbridge/intel/i945/gma.c: In function 'intel_gma_init_lvds': src/northbridge/intel/i945/gma.c:98:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 98 | (void *)pgfx, mmiobase, piobase, pphysbase); | ^ src/northbridge/intel/i945/gma.c:359:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 359 | (void *)pgfx, hactive * vactive * 4); | ^ src/northbridge/intel/i945/gma.c:360:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 360 | memset((void *)pgfx, 0x00, hactive * vactive * 4); | ^ src/northbridge/intel/i945/gma.c: In function 'intel_gma_init_vga': src/northbridge/intel/i945/gma.c:384:17: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 384 | (u32)mmiobase, piobase, pphysbase); | 4. src/northbridge/intel/i945/northbridge.c: In function 'mch_domain_read_resources': src/northbridge/intel/i945/northbridge.c:64:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 64 | cbmem_topk = ((uint32_t)cbmem_top() / KiB); | ^ Change-Id: I5ac7a1cb5d85a346114f909047d5a7c21ddb43e9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-25lib/cbmem_console,console: Resurrect CONSOLE_CBMEM_DUMP_TO_UARTRaul E Rangel
Chromebooks normally run with non-serial enabled firmware because writing to the UART console is very slow. This unfortunately makes debugging boot errors more difficult. We tend to rely on port 80s and/or the vboot recovery code. When CONSOLE_CBMEM_DUMP_TO_UART is selected it will dump the entire cbmem console to the UART whenever `vboot_reboot()` is called. We don't incur any boot time penalty in the happy path, but still retain the ability to access the logs when an error occurs. The previous implementation was using a hard coded UART index and `get_uart_baudrate` was always returning 0 since `CONFIG_TTYS0_BAUD` wasn't defined. This change makes it so the UART console properties are available when CONSOLE_CBMEM_DUMP_TO_UART is set. This results in the following .config diff: +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_TTYS0_LCS=3 +CONFIG_CONSOLE_SERIAL_115200=y +CONFIG_TTYS0_BAUD=115200 This functionality is especially helpful on Guybrush. PSP Verstage is run on S0i3 resume. Today, if there is an error, the cbmem console is lost since it lives in the PSP SRAM. BUG=b:213828947, b:215599230 TEST=Build non-serial guybrush FW and verify no serial output happens in happy path. Inject a vboot error and perform an S0i3 suspend/resume. Verify CBMEM console gets dumped to the correct UART. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I997942204603362e51876a9ae25e493fe527437b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-25drivers/intel/fsp2_0: Make FSP Notify Phase APIs optionalSubrata Banik
The FSP API is used to notify the FSP about different phases in the boot process. The current FSP specification supports three notify phases: - Post PCI enumeration - Ready to Boot - End of Firmware This patch attempts to make calling into the FSP Notify Phase APIs optional by using native coreboot implementations to perform the required lock down and chipset register configuration prior boot to payload. BUG=b:211954778 TEST=Able to build brya without any compilation issue and coreboot log with this code changes when SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT and SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config enabled. coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-25soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
Since Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM. In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1 device can undergo the PCI enumeration and later based on the mainboard policy the HECI1 device can be disabled. Mainboards that choose to make HECI1 enable during boot don't override `DISABLE_HECI1_AT_PRE_BOOT` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-25mb/google/brya/var/volmar: Enable EC keyboard backlightDavid Wu
Enable EC keyboard backlight for volmar. BUG=b:211891086 TEST=FW_NAME=volmar emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I24ec7c8ca770cb438aabcf16b252032eef6d734d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-01-25mb/google/brya/variants/volmar: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for volmar BUG=b:211891086 TEST=FW_NAME=volmar emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1bd3f1b3807b546d5a827ac89f0dc9bc8aaec40a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-01-25soc/intel/common: Include Alder Lake-N device IDsUsha P
Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs. Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-25soc/intel/elkhartlake: Add PSE TSN supportLean Sheng Tan
Enable PSE GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Add PSE GBE ACPI devices 3. Refactor PCH GBE FSP-S code and merge it together with PSE GBE code Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-01-25soc/intel/elkhartlake: Introduce Intel PSELean Sheng Tan
The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and its peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate the PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate the PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enable the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-01-25mainboard/asus/p8x7x-series: Add new variant P8Z77-MKeith Hui
Constructed out of a mix of autoport results, p8z77-m_pro, and tool dumps. Working: - Core i7-3770K CPU - SeaBIOS 1.13.0 boot to Linux 5.4.24 and Windows 10 1903 (all further tests are under these versions) - USB2 / USB3 - SATA - Gigabit ethernet - CPU temp sensors (memtest86+ 5.0.1) - Hardware monitoring under Linux - Native and MRC raminit - PCIe GPU in both "PCIEX16" slots (16x/4x, nVidia Quadro 600) - Integrated graphics with Intel OpROM and libgfxinit (all ports) - Serial port - Windows with libgfxinit framebuffer - 2ch sound playback, Linux and Windows Not working: - PS/2 mouse - 6ch analog audio out - PCI POST card in PCI slot Untested: - PS/2 keyboard - Internal USB3 ports - Digital audio out Change-Id: If756e791ddce747cb1706414be8e41e83f88922b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-25soc/mediatek: Save dramc_param header to mrc_cacheXi Chen
Fast-k flow may need to re-init header because mrc_cache doesn't store header. Storing header together with dparam data is better for data consistancy. TEST=fast calibration pass on Corsola BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I22982923dce06c9e770aa4f20f3dcd2f33685d84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-01-25ec/google/chromeec: Add checks before creating Type C devicePrashant Malani
Check for situations where a Type C device isn't useful and avoid creating one for those scenarios. BUG=b:215199976 TEST=Tested on brya; verified that USBC device is created. Signed-off-by: Prashant Malani <pmalani@chromium.org> Tested-by: Alyssa Ross <hi@alyssa.is> Change-Id: I5e1598bd637ec9f50e7bf8dab9e3c757a30b9848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-01-25soc/amd/sabrina/include/aoac_defs: add additional UARTsFelix Held
Compared to Cezanne there are 3 more UARTs controllers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id98767197a21cb1a61f54fc9b256b10a9506c791 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25soc/amd/sabrina/include/iomap: update MMIO device mappingsFelix Held
Compared to Cezanne there are 3 more UARTs with DMA controllers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a3d255bb4976a55623f3a161e791e80f1d01c69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25soc/amd/cezanne: Increase PRERAM_CBMEM_CONSOLE_SIZE to 0x2000Raul E Rangel
Let's increase this to avoid losing any logs. BUG=b:213828947 TEST=Boot guybrush and no longer see *** Pre-CBMEM romstage console overflowed, log truncated! Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3258145e352af3a75893c7cc96f36eb238c99abb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-25soc/amd/sabrina: use correct PCI IDsFelix Held
Replace the Renoir/Cezanne PCI IDs with the Sabrina ones that were added in commit 27b02c2eee68f4b6c8520c4737224aaaf81f137d (include/device/ pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoC). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I427df6f8e8c08fb47ae8513b6cf1085d4294e28f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25mb/amd/chausie: add mainboard as copy of mb/amd/majolicaFelix Held
To have the new AMD Sabrina SoC code tested, add the AMD Chausie mainboard as a copy of Majolica. This patch also changes the name from Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC and comments out the APCB_SOURCES since those aren't available in the 3rdparty/blobs repository yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25soc/amd/common/block/include/psp_efs: update defines for sabrinaFelix Held
Document #55758 Rev. 1.13 says that family 17h models 30h-3Fh and later use the spi_readmode_f17_mod_30_3f struct element for SPI_MODE_FIELD and spi_fastspeed_f17_mod_30_3f for SPI_SPEED_FIELD, so also use this for The AMD Sabrina SoC which is family 17h models A0h-AFh. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I336f9ea4a0defdf34e1af4b6d568cfe46488f75e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25soc/amd/sabrina: add new SoC as copy of soc/amd/cezanneFelix Held
The Cezanne SoC code was initially started as a copy of example/min86 which only provides enough code to make the SoC code build. Then the different parts of the real SoC support was brought in patch by patch which also helped cleaning up and untangling the code. Since the Cezanne SoC code is now in a rather good shape and the Sabrina SoC is similar to the Cezanne SoC from the coreboot side, the new SoC support is started with a copy of the Cezanne code and all the needed changes will be applied on top of that. In order for the build not to fail due to duplicate files, this patch does not only copy the directory, but also replaces most instances of the Cezanne name with Sabrina. Since the needed blobs aren't available in the 3rdparty/amd_blobs repository yet, the Cezanne blobs are used for now so that the build will succeed. As soon as the proper blobs will be available in that repository, the code will be switched over to use them. As suggested by Nico, I added a "TODO: Check if this is still correct" comment to the beginning of every copied file and all SOC_AMD_COMMON_* Kconfig option selects which will be removed after re-verifying that each file and each selected common code block is still correct for the new SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25vc/amd/fsp/sabrina: add as a copy of vc/amd/fsp/cezanneFelix Held
The AMD Sabrina SoC will be using the FSP driver to call into the corresponding FSP binary to do its part of for the silicon initialization, so we need an initial set of FSP headers for the AMD Sabrina SoC code to build. Since the FSP interface for this SoC won't be too different from the Cezanne FSP interface, we'll start with a copy of the Cezanne FSP headers and update/replace them as soon as the proper FSP headers for Sabrina will be available. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib3bf50598efe60673b81cf99da491866fb5dc121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-24mb/google/brya/var/banshee: Configure TPM I2C BUSIvy Jian
Add I2C bus for banshee in Kconfig BUG=b:214871796 TEST=emerge-brya coreboot Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I67592051b367d5a5715f8d1253ea0c11d2deb1c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-24mb/google/brya/var/banshee: update overridetreeIvy Jian
Update override devicetree based on schematics BUG=b:214871796 TEST=emerge-brya coreboot Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I05b63ebcded2f37dfb0f6c428e1fb993f476006a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-24device: constify pciexp_find_extended_cap()Tim Wawrzynczak
The object pointed to by the struct device * argument is not modified, therefore it can be made const. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I300d2a59eb0513ddd08d4f1d2a3c6eb829e3f836 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-24mb/google/brya: Alphabetize BOARD_GOOGLE_* in Kconfig.nameTim Wawrzynczak
Change-Id: I624dd67b6ce9b87a6031b5467eacb9a8d7cda1cd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-24mb/google/brya/var/{taeko, taeko4es}: Modify touchpad i2c signalJoey Peng
Modify i2c signal to meet touchpad vendor spec. Please see issue tracker for more details. BUG=b:215487482 TEST=emerge-brya coreboot and check measured waveform in spec Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib3797d4e232654ada97092d9f2742ca040d0f0e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-24mb/system76/lemp10: Remove incorrect SPD address 0x50Tim Crawford
The Lemur Pro, with its mixed memory topology, only has a DIMM at address 0x52. Change-Id: Iecea8c70c7fd40943d86f8918f8e3b384538b5c3 Fixes: 4dcee4f21db5 ("mb/system76/lemp10: Add System76 Lemur Pro 10") Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-24soc/intel/common/block/pcie/rtd3: Fix PMC IPC method for CPU PCIe RPTim Wawrzynczak
When calling get_pcie_rp_pmc_idx(), the following code checked the return value to see if it was negative or `> CONFIG_MAX_ROOT_PORTS`. However, the expected return value for CPU PCIe RPs is above MAX_ROOT_PORTS. Since the static, local function is intended to return -1 or a valid value, drop the check for `> CONFIG_MAX_ROOT_PORTS`. Change-Id: I2039273ad246884cd8736a7f0355e621a706a526 Fixes: b6a15a7 ("soc/intel/common/block/pcie/rtd3: Update ACPI Update ACPI methods for CPU PCIe RPs") Tested-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-01-24soc/amd/common: Make the function in cpu.c available in romstageZheng Bao
Change-Id: I909f74853a37a783582471e05071bc3d07e3dcf8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-24mb/google/guybrush: Change DDI settings for guybrush variantsZheng Bao
Like the variant function to change DXIO settings, add a similar weak function to modify the DDI settings. Currently we follow the old way. Later we will find out a better way to avoid using weak function. Change-Id: I9898d717bc3025ea1ddc3b0db41325083324ed57 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
2022-01-24soc/mediatek: Extract dramc_param_header to a common headerXi Chen
To be shared with different SOCs, move the dramc_param_header struct as well DRAMC_PARAM_FLAG and DRAMC_PARAM_CONFIG enums to a common header file dramc_param_common.h. TEST=fast calibration pass BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I087971799803e47e34c30063b2b0bd0cfc5795ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61132 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-23Makefile.inc: Add `-fno-pie` to `ADAFLAGS_common`Paul Menzel
Building libgfxinit with Debian’s toolchain – latest test with *gnat-11* 11.2.0-13 from Debian sid/unstable – the build fails with the error below. E: Invalid reloc type: 10 E: Unable to create rmodule from 'build/cbfs/fallback/ramstage.debug'. Debian’s toolchain is built without enabling PIE by default. So, explicitly pass `-fno-pie` to `ADAFLAGS_common` to be independent from how the toolchain was built. TEST=*gnat* 11.2.0-13 successfully. builds purism/librem_cnl/variants/librem_mini with libgfxint. With the coreboot toolchain `make BUILD_TIMELESS=1` produces the same `build/coreboot.rom` for `BOARD_PURISM_LIBREM_MINI_V2=y` on top of commit 50251400d2 (sb/intel/common/firmware: Reword me_cleaner warning) with and without the change. Change-Id: I6661937906d95c130c6099f598d61b21e958fd85 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-23soc/amd/{common,cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZERaul E Rangel
This change splits the size of the console transfer region and size of the bootblock/romstage Pre-RAM console region. This allows having a larger Pre-RAM console while not impacting the size of the PSP verstage console. Instead of directly using the PRE_X86_CBMEM_CONSOLE_SIZE symbol in `setup_cbmem_console`, I chose to use the offsets provided in the transfer buffer. It would be nice to eventually do this for all the fields in the transfer buffer. BUG=b:213828947 TEST=Boot guybrush and verify verstage logs are no longer truncated Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8b8cc46600192a7db00f5c1f24c3c8304c4db31d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-23lib/cbmem_console: Add cbmemc_copy_in functionRaul E Rangel
When running in verstage before bootblock, the PSP (ARM co-processor) is running with limited SRAM. It needs to stash the verstage console data internally until DRAM is brought up. Once DRAM is brought up the data is stashed in a "transfer buffer" region. In the current design, we are using the same region for the transfer buffer and the preram_cbmem_console region. This has the following downsides: 1) The pre-x86 buffer needs to be large enough to hold all the verstage, bootblock and romstage console logs. 2) On AMD platforms, the PSP verstage is signed. Changing the size of preram_cbmem_console after the fact will result in a mismatch of the transfer buffer between verstage and bootblock. This CL adds a new method that allows SoC specific code to copy the CBMEM console in the transfer buffer to the active CBMEM console. BUG=b:213828947 TEST=Boot guybrush and no longer see *** Pre-CBMEM romstage console overflowed, log truncated! Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idc0ab8090db740e0d1b3d21d8968f26471f2e930 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-22mb/system76/lemp9: Make GPIO for touchpad interrupt level triggeredJeremy Soller
Fixes commit 6bcaf6f (mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C), which changed the interrupt configuration in the device tree but not in the GPIO definitions. Tested on a System76 Lemur Pro (lemp9), multi-touch I2C-HID was working. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I7f0559675a65453a1ad071f96049549a2dc21378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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