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2020-01-26soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 deviceSubrata Banik
As per PC client TPM specification, the TPM description contains the base address of the TIS interface 0xfed40000 and the size of the MMIO area is 20KB (0x5000). Hence ACPI used to reserve those fixed system memory from getting used by OS. Platform with TPM_CR50 doesn't require fixed SoC mapped memory hence additional reservation might not required. TEST=Build and boot EVE and Soraka to OS. Change-Id: Id02a2659ce42f705180370000df89d4f6b64afce Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38512 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-25soc/intel/tigerlake: Add IPU in ACPIWonkyu Kim
Add IPU ACPI object for Camera ACPI. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I8c1ca9c053f0c8ef8d7c027c317c7af74d5f0f8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-01-25mb/intel/tglrvp: Enable rp11 for optaneWonkyu Kim
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk pins. This is also dependent on pciecontroller3 config to be set as 2x2 instead of 1x4 in fit configuration in IFWI. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from Optane and check 2 NVMe devices from lspci Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ic81244bebac78102af7ba6308ab64b18c886f839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-01-25soc/intel/tigerlake: Configure ClkReq according to mainboard designWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I14997e0a7d03bf1a97d115cbf0a7ad2603ef9953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38285 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-25vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header files for Tiger LakeSrinidhi N Kaushik
Update FSP header files for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I47574844a8b5fd888e8e75ed2f60f6df465b33ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/38555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-01-25soc/intel/tigerlake: Add GPIO helper functionShaunak Saha
This patch adds ASL methods like GRXS, GTXS, STXS and CTXS which are used to get, set and clear gpio values. We use ASL 2.0 syntax here for gpio.asl. BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board Change-Id: I17e75ff2a7cb67e94669059a1ed9d73a720ebcb1 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38442 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-25soc/intel/tigerlake: Fix GPIO communitiesShaunak Saha
GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups in coreboot so that they are mapped properly. GPIO comuinities in coreboot should match with the kernel gpio communities also. Kernel reads the ASL file from coreboot. This patch adds the proper community mapping in ASL code to match with kernel code. In gpio_soc_defs.c file we are indexing the groups correctly. In gpio.h file we define all the gpio devices as kernel populates sysfs with separate gpio device for each community. This patch is created based on Intel Tiger Lake Processor PCH Datasheet with Document number:575857 and Chapter number:27. BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board. In /sys/kernel/debug/pinctrl verify INTC34C5:0<1-3> listing all the pins for each community. e.g., #cat /sys/kernel/debug/pinctrl/INT34C5:00/pins should list all the community 0 pins. Change-Id: I40c386db060d84c1b7fba9c587f960d6a92f84ba Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-01-25vboot: Remove hard dependency on MISSING_BOARD_RESETJulius Werner
Having a working board reset is certainly better when you're running vboot (because otherwise you'll hang when transitioning into recovery mode), but I don't think it should be strictly required, since it's still somewhat usable without. This is particularly important for certain test platforms that don't have a good way to reset but might still be useful for vboot testing/prototyping. Change-Id: Ia765f54b6e2e176e2d54478fb1e0839d8cab9849 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38417 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-24soc/intel/skylake: Remove unused ICH memory referenceSubrata Banik
TEST=Build and boot EVE and Soraka to OS. Change-Id: Ic7840ce264393b4a955f17b16f5e0f556e34a776 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38511 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-24soc/intel/skylake: Move pci_irqs.asl from SA to PCHSubrata Banik
SoC handles PCI IRQs programming inside PCH related ASL. TEST=Build and boot EVE and Soraka to OS. Change-Id: If95101193fa1b528dc64f57c0fc12f13f16d82b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-24mb/google/drallion: Remove fixed IccMax valuesJohn Su
Remove fixed IccMax values for U22 CPU. IccMax will be selected by CPU SKU. BUG=b:148110226 BRANCH=None TEST=build coreboot and fsp with enabled fw_debug. Flashed to device and checked IccMax[1]. Change-Id: Ifcd31ad5b608ce599d4294a6522fdda022f8a177 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-01-24mb/portwell/m107: Remove mainboard sleepstates.aslWim Vervoorn
BUG=N/A TEST=build Change-Id: Ifb45bc1f7f4d3744124d6797fb4c791fd5f227ca Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-24arch/x86/acpi_device: Add macros to define gpio interrupt with wakeAlex Levin
Add Provides ACPI_GPIO_IRQ_LEVEL_[LOW|HIGH]_WAKE versions to allow board to define a gpio irq as wake capable. Change-Id: I42f5084c5f0f5da0a4b39df77707b2f158bcc03d Signed-off-by: Alex Levin <levinale@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-24mb/intel/tglrvp: Enable SATAWonkyu Kim
Enable both SATA ports for TGLRVP. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38505 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-24soc/intel/tigerlake: Enable SATAWonkyu Kim
Configure SATA FSP UPD according to mainboard design. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38504 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-23soc/intel/common: Update SA bit fields as per EDSSubrata Banik
This patch updates system agent related registers bit definitions as per EDS. For example: As per CNL/ICL EDS MCHBAR register base is between bit 16-38 but coreboot programming was not aligned with EDS previously. CNL EDS doc number: 566216 Also provide provision to program 64bit values as per SA EDS definitions TEST=Dump MCHBAR in coreboot and ASL shows same 32 bit value. Change-Id: I37340408fe89c94ce81953c751c8d7e22bc81a42 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-22mb/google/hatch/var/dratini: Update DPTF parametersWisley Chen
1. Add a TEMP_SENSOR3 2. Update DFPS (fan performance state) table with values received from thermal team 3. Update PL1 override to 15W 4. Update PL2 override to 51W BRANCH=hatch BUG=b:147792204 TEST=build and verify by thermal team Change-Id: I21c17c09a097c963f4dd1b7d5f8212c83a639dc3 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38025 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22soc/intel/tigerlake: enable gpio dual route supportNick Vaccaro
Enable SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT for tigerlake. BUG=b:142961277, b:145494156 BRANCH=none TEST=none Change-Id: I1f785f410982f7d7598942f9b12196851e77c240 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37629 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22mb/google/hatch: Kohaku: Add MKBP to suspend wake eventsTim Wawrzynczak
This CL allows MKBP events from the EC to wake the system from suspend states. BUG=b:144122000 BRANCH=firmware-hatch-12672.B TEST=Verify that MKBP events generated from EC will wake the system from S0ix. Change-Id: I8a0d2c7ed89fa1ea937a08c3082cc5d3e782efff Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-22ec/google/chromeec: add support for fw_config cbi fieldJett Rink
The firmware configuration (fw_config) field is store in the CBI EEPROM and it should be used to make firmware customization instead of sku/variant id. BUG=b:145519081 TEST=builds Change-Id: I790998a29e724ecdff8876cca072267537b7cea6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-01-22ec/google/chromeec: update ec_commands.hJett Rink
Copy ec_commands.h directly from Chromium OS EC repo at sha e57217a250. This is needed for the FW_CONFIG CBI field definition. Change-Id: Id010721033ebe32ac9c9482d666cf790442a26ee Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-01-22soc/intel/tigerlake: Update fsp_params for TGLSrinidhi N Kaushik
Add initial fsp upd settings for TGL, both romstage and ramstage upd's to support basic build and boot of TGL RVP. - Add Silicon upd settings which includes * Serial IO/UART settings * Graphics settings * USB2/USB3 settings - Add Romstage upd settings which includes * Pcie Root port settings * IGD initialization * Hyper Threading settings * SMBus controller settings * Debug probe settings BUG=none BRANCH=none TEST=Build and boot Tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I16df66451fd3a681df1222d283d97dd6bdaff0e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37960 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22soc/intel/tigerlake: Update GPIO configRavi Sarawadi
GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups from coreboot so that they are mapped properly. GPIO communities should be properly configured in GPIO_CFG and MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured in GPIO_CFG register while the PMC_GPP_* in pmc.h are used to configure the MISCCFG registers. BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board. Verified that after setting the gpe from devicetree the GPP_EN register for that community gets updated setting that specific bit. From the iotools i checked that GPE_EN register for that community is updated with that specific bit set to 1. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/37427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-22soc/intel/common: Add Elkhartlake Device IDsTan, Lean Sheng
Add Elkhartlake CPU, SA and PCH IDs. EHL PCH is code named as MCC. Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22soc/intel/tigerlake: Update interrupt infoWonkyu Kim
Update interrupt header and interrupt mapping per Intel Silcon reference code. Need to match pci_irqs.asl with FSP setting which followed by PCH BIOS spec. Reference PCH BIOS spec#613495 https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg /IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/PeiItssPolicyLibVer2.c BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iffc4efad4d0aa55fc0de88d7fe32c0356dbc3c60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38258 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22mb/facebook/fbg1701: Remove ACPI S4 supportWim Vervoorn
Align the fbg1701 sleepstates implementation with monolith. BUG=N/A TEST=build Change-Id: I3a715781bf51da41d6954463ad38ed94b0dfd217 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-22mb/facebook/monolith: Disable S3 and S4Wim Vervoorn
The monolith board doesn't support the S3 and S4 states because of the watchdog and failover mechanisms. Remove S3 and S4 from the available sleepstates. BUG=N/A TEST=build Change-Id: I01f67d8bb3f9e45caef748caca91eeb6859d7393 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-22{soc,southbridge}/*/*/acpi: Add possibility to disable S4Wim Vervoorn
Some boards don't support S3 or S4. The S4 state can't be removed from the available sleep states. Add a config item that allows removal of the S4 state from the list of available sleep states. The S4 state can be removed by selecting the item on board level. For the AMD chipsets the SSFG mask is updated to remove the S4 state. BUG=N/A TEST=build Change-Id: Id802c4cc40308ddf39e99e7f226d55e0e020f0c9 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38431 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-21mb/google/puff: Add ac/dc loadline configuationsJamie Chen
According to VRTT report, add ac/dc loadline configuations in puff device tree. BUG=b:147206535 BRANCH=None TEST=build coreboot and fsp with enabled fw_debug. Flashed to puff and checked the log. All ac/dc loadline configs were set correctly. Change-Id: Ia806de23a1fefcaac3ce9a462a8a04eee5eabcae Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-21mb/google/hatch/var/jinlon: Remove DPTF fan controlWisley Chen
Jinlon will use EC to control fan, so remove DPTF fan control. BUG=b:141259174 TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I8ada4fe72eee260fecf45d00510da8b91e3f10a4 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-21mb/lenovo/t410/Kconfig: Don't select ONBOARD_VGA_IS_PRIMARY explicitlyPeter Lemenkov
ONBOARD_VGA_IS_PRIMARY is selected if board selects DRIVERS_LENOVO_HYBRID_GRAPHICS. See commit 35abe73e with Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff ("mb/lenovo/t430: Fix Dual Graphics"). Change-Id: I39687e5cd34979fd4318978f5aa46ac6cdf721e8 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-21mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)Ivan Vatlin
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin <jenrus@tuta.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-21mb/pcengines/apu2/mainboard.c: Add SMBIOS type 16 and 17 entriesMichał Żygowski
Use information provided by AGESA to fill the SMBIOS memory tables. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I45bb2fc36cf0c01670e9fc8559d3a6183ea271f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-21biostar/a68n_5200: Switch away from ROMCC_BOOTBLOCKMike Banon
Following the example of change CB:37737 (ee8f969). Switching was done by moving a SIO configuration and the clocks setup from 'romstage.c' to 'bootblock.c'. Tested-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Change-Id: I2e710ac61843c09a055523c7971e4c05bae56a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-21mainboard/hatch: Fix puff USB ACPI names and typesEdward O'Callaghan
Fix devicetree to advertise the correct USB names and types in the generated ASL. BUG=b:146437991 BRANCH=none TEST=booted and inspected the reported generated ASL. Change-Id: I133b4db444f9a5f0a36d8e976ae490f24cf307d8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-01-20soc/amd/picasso: Add SMMSTORE supportMarshall Dawson
Add SMMSTORE support for saving EFI NVRAM variables in conjuction with Tianocore payload. Test: none, as this duplicates tested functionality in amd/stoneyridge. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id05b33edf949611c3f9eac94e7b63a4266c6c4d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20drivers/smmstore: Clarify Kconfig cbfs wordingMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ibb37c2d99c1a95b1d37bec784c98e636da4836d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38470 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20mb/lenovo/x201: Support undock button on X200 ultrabaseMaciej Matuszczyk
Only the ACPI code needs to be extended, as smihandler.c already supported it. The _Q50 Method is just _Q18 with changed name. On Linux, pressing the undock button does nothing, so the only safe way to undock is to press Fn+F9. With this patch, when the undock button is pressed, the green LED lights up, and undocking is safe. Change-Id: Iaaecad031bb1f39dd1a778d0c8eaea6bce9e0f57 Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38446 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20mb/pcengines/*: enable simple IO-based GPIO controlPiotr Kleinschmidt
Add Nuvoton NCT5104D GPIO IO VLDN and define an IO base address unused by any peripheral for GPIO use. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I034c5d0169b8d97eac97a20c92c22816fd674f79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-20superio/nuvoton/nct5104d: Add virtual LDN for simple GPIO IO controlPiotr Kleinschmidt
Now, Super I/O GPIOs can also be controlled directly through access to I/O registers. VLDN 108 and specific I/O port from a range <100h; ff8h> may be enabled in mainboard devicetree. Change-Id: I4ce99bb44e6f5db684170f4190bdc38a944849f6 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35849 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20mb/facebook/monolith: Drop PWRB deviceWim Vervoorn
The mainboard ASL code contained a power button definition. This is not required as the system uses the standard ACPI power button. Remove the PWRB device from ASL. BUG=N/A TEST=tested using fwts on a facebook monolith. Found-by: fwts 19.12.00 Change-Id: I25a842539ee2e8febc8a1ae88843a71ccb4ee68e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38133 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20{mb/facebook/fbg1701,mb/portwell/m107}: Drop PWRB deviceWim Vervoorn
The mainboard ASL code contained a power button definition. This is not required as the system uses the standard ACPI power button. Remove the PWRB device from ASL. BUG=N/A TEST=build Found-by: fwts 19.12.00 Change-Id: I4fac1411fd99475551bc970818759649f80b3f0e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38134 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20soc/amd/stoneyridge: Add SMMSTORE supportMatt DeVillier
Add SMMSTORE support for saving EFI NVRAM variables in conjunction with Tianocore payload. Test: build/boot several google/kahlee variants, test manipulation and persistence of Tianocore bootorder variables. Change-Id: Ida604a44d1fa5288e96dbe05de1f847e597cc95d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-20mb/hp/snb_ivb_laptops: Switch to overridetree setupAngel Pons
NOTE: The ME interface was disabled on folio_9470m and revolve_810_g1. It is assumed that they were ported while the ME was in an abnormal state (usually due to me_cleaner usage), and that it should be enabled. In any case, the MEI device is hidden if the ME fails to boot already. Change-Id: Ibf32a034653946f49f72a2c19c41a4033964ef83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/revolve_810_g1: Transform into variantAngel Pons
Update Makefile.inc so as to add the SPD data when needed. Tested building other variants, no spd.bin gets added because they don't select GENERIC_SPD_BIN. Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I0cda3f839baa227ce6a4b8f0510934125e5afb59 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/folio_9470m: Transform into variantAngel Pons
Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I65696c5739469b33253c22c1d5a65cc31ef3a421 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/8770w: Transform into variantAngel Pons
Since this board does not have integrated graphics, do not install the INT15 handler if it is not selected in Kconfig. NOTE: Since cmos options are not very flexible, this board ends up with a spurious gfx_uma_size option. Other than that, everything is the same. Tested with BUILD_TIMELESS=1, binary does not change when ignoring the cmos options. Change-Id: I2ebcfd5160773bf98a3d23e797a89e290063d112 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/8470p: Transform into variantAngel Pons
Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I6dbecb0b4d38ed4af8966f5391fce1f2c9c5d182 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/8460p: Transform into variantAngel Pons
Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I17b6ac9ac2433b760e125a1ce708d3b422b632b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/2670p: Transform into variantAngel Pons
Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: Idc4d0a3d7384ad4e5a3eb3d7ecefaa2f35093ac0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20mb/hp/2570p: Transform into variant-enabled structureAngel Pons
Get ready to squash all the HP Sandy Bridge and Ivy Bridge laptops together, so as to factor out lots of repeated code. Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I0b68e524b57e3705e91e3cd98be5571b3554bd67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-19mb/google/kahlee/treeya: Update STAPM parameters for TreeyaPeichao Wang
Change stapm percentage to 80 and time to 2000 seconds make DUT meets Lenovo spec and pass CTS respectively. BUG=b:147333429 TEST=build firmware and install it to DUT and run CTS relevant test, check temperature whether meets spec. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6a2f059fbd5c89f897cfb46d1f7a82b0923edb17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38443 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboardKeith Hui
These predate hyperthreading so they are not SMP capable unless installed in a SMP board. Turning SMP off shaves 128 compressed bytes from ramstage. Change-Id: I114bdc83ed40ccd9d3996aabf77422236d9d12fa Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDsGaggery Tsai
This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for 10-Core ID. Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-18google/eve: tweak VBT settingsMatt DeVillier
- Disable Windows driver DPST function - Set POST resolution to 1800x1200 - Set POST brightness to 225 (0-255 scale) Test: Boot Windows on EVE, verify display backlight control functional and no lock ups from switching in/out of tablet mode. Change-Id: Ida64a44df2449f1ff0dc5c8d0ec7b40a183566a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18mainboard/google/puff: update SATA strengthTim Chen
Base on SATA SI report to fine tune the strength for port 1. BRANCH=none BUG=b:147351936 TEST=build and test SATA port works fine. Change-Id: Ib82b7e5df32b4ce794682781f33c44dfeb6e68bf Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-18soc/intel/cannonlake: Add chip config for SATA strengthJamie Chen
Add config to chip.h for tuning SATA gen3 strength. BUG=b:147351936 BRANCH=none TEST=build successful in puff Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38432 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18ec/google/wilco: Set minimum UCSI_ACPI region lengthBernardo Perez Priego
IMD provides support for small and large allocations. Region IMD Small memory is 1 KB with 32 Bytes alignment, this region holds smaller entries without having to reserve a whole 4 KB page. Remaining space is assigned to IMD Large to hold various regions with 4 KB alignment. The UCSI kernel (kernel version 4.19) driver maps the UCSI_ACPI memory as not cached. Cache mapping is set on page boundaries and all IMD Small is within the same page. If another driver maps the memory as write-back before the UCSI driver is loaded then the UCSI driver will fail to map the memory as not cached. Placing UCSI_ACPI in IMD Large region will prevent this mapping issue since it will now be located within its own page. This patch will force UCSI_ACPI region to be located in IMD Large region. BUG=b:144826008 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Id00e76dca240279773a95c8054831e05df390664 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38414 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/tigerlake: Update ACPI filesRavi Sarawadi
Add and update ACPI files for Tiger Lake SoC Use ASL2.0 code syntax for new acpi(camera_clock_ctl.asl) Reference PCH EDS#576591 vol1 rev1.2 PCH EDS#575857 vol2 rev1.0 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ib82156830273c2937f5f02713ed7dd27da41c857 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37781 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/tigerlake: Update pci dev definitionWonkyu Kim
This change updates pci dev definition according to TGL EDS. Add GSPI3 case in chip.c according to updated pci dev definitions. Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38341 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mb/facebook/monolith: Enable the xDCI controllerWim Vervoorn
Enable the VBOOT_ALWAYS_ALLOW_UDC option to actually enable the xDCI controller. BUG=N/A TEST=build Change-Id: Ib51f2c82e69db83cebceb71ba5f1305764e0feca Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18security/vboot: Allow UDC regardless of vboot stateWim Vervoorn
When a VBOOT enabled system is used without ChromeOS it may be valid to allow the UDC independent of the vboot state. Provide the option to always allow UDC when CHROMEOS is not selected. BUG=N/A TEST=build Change-Id: I6142c4a74ca6930457b16f62f32e1199b8baaff8 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-18mb/intel/tglrvp: Update tglrvp_up3 devicetreeRavi Sarawadi
Update Tigerlake RVP UP3 devicetree to reflect devices used by tglrvp_up3. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Idd0d9efe0ab4e050d2160f7662e4dc40a002672f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37929 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/common: Fix typosSridhar Siricilla
Fix typos and replace spaces with tab in macro definitions. TEST=Build and Boot hatch board Change-Id: I43b2df7defc97aaeb7c8c9dfbe08ce78ba81f39b Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38384 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/common/cse: Add description for macrosSridhar Siricilla
Below changes are done in the patch: 1. Remove unnecessary lining, and replace spaces with tabs 2. Add description for macros 3. Correct comment mentioned for wrapper #ifndef TEST=Build and Boot hatch board Change-Id: I630446234321e7998ab42f8506a58b16e9ce4eb0 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-18soc/intel/tigerlake: Update chip filesRavi Sarawadi
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure Reference PCH EDS#576591 vol1 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mb/intel/jasperlake_rvp: Remove sd card detect gpioMaulik V Vaghela
Tigerlake SoC doesn't have GPIO defined for GPP_G. so compilation is failing due to this. We will update correct gpio for sd card detect once we have Jasper Lake soc gpio patch. partner bug for tracking: https://ticket.coreboot.org/issues/251 BUG=None BRANCH=NONE TEST='jslrvp' mainboard builds successfully Change-Id: I097b2f3a4fef1a487495a4aa9d2bcf88aa64f017 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-01-18arch/x86/post.c: Hide cmos_post_code from SMM contextMaulik V Vaghela
Code in SMM segment using cmos_post_code will give compiler error since cmos_post_code function is not getting compiled during SMM stage. Also as per patch discussion, CMOS uses a split IO transaction and it's not really safe to call cmos_post_code from SMM context. Thus we'll hide the call for SMM context. Change-Id: Iffdcccaad48e7ad96e068d07046630fbe4297e65 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-18mb/opencellular/elgon: Fix typoElyes HAOUAS
Change-Id: I6724637c7333ae6be7ada3e8ebe878b2a1061dd1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-18mb/amd/bettong: Fix typoElyes HAOUAS
Use 'irremovable' over 'unremovable' Change-Id: Id305dbe56a93740abc49d85d11402d1b63989dad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37527 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18src/include: Fix typosElyes HAOUAS
Change-Id: Ia8e6e5bd5ac2565263d81df8ca81d62436a3301f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18soc/intel/common/cse: Add consistent HECI command id/group id namingSridhar Siricilla
Below changes are done: 1. Consistent HECI command/group ID naming. 2. Rename macros to match with Intel ME BIOS Spec. 3. Move command ids, group ids and related macros into cse.h 4. Add description for structure members. TEST=Build and Boot hatch board. Change-Id: Ia902095483d5badf778d0c1faa6bf8cc431f0e50 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-18mainboard/google/puff: update USB configurationJamie Chen
Base on USB SI report to fine tune the strength and correct some OC pin settings. BRANCH=none BUG=b:147206010 TEST=build and test all usb ports function work fine. Change-Id: Idbee5cdddf3a83f97109214a95e0f9875b3b3f8f Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-18console/post: NOPOST means NOPOSTPatrick Georgi
Not "NOPOST except when the board says something else". Change-Id: I3608e9c3a7d2338363a4320c8718b20ef25a038a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18mb/google/link: drop dummy mainboard_post functionPatrick Georgi
It was never filled it, it probably never will be filled in, so stop the pretense. Change-Id: I7632b763b8518304d36a818ce262cc127f95b9f0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18mb/facebook/monolith: Describe device 4.0 in devicetreeWim Vervoorn
BUG=N/A TEST=build Change-Id: Id7267aa6d4266bb7807fb3c25b5e2704c8d81df7 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38430 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/{skylake,common}/acpi/dptf/thermal.asl: Prevent iasl remarksWim Vervoorn
Prevent iasl remarks about unused parameters. BUG=N/A TEST=build Change-Id: I54fa4712e618038fdd5a96c2012c2ec64ca34706 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mb/facebook/monolith: Add support to read cpu temperatureWim Vervoorn
Read the CPU temperature from the EC. For this board the EC support is limited to reading the CPU temperature sensor at this moment. Events are not supported. BUG=N/A TEST=tested on facebook monolith using acpidbg The TSR0._TMP method is returning the correct values. Change-Id: I6793070602e253f1e15cfc641bb47d25d269b136 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18cbfs: Remove locator conceptJulius Werner
When vboot was first integrated into CBFS it was still part of Google vendorcode. So to not directly tie custom vendorcode into the core CBFS library, the concept of cbfs_locator was introduced to decouple core code from an arbitrary amount of platform-specific implementations that want to decide where the CBFS can be found. Nowadays vboot is a core coreboot feature itself, and the locator concept isn't used by anything else anymore. This patch simplifies the code by removing it and just calling vboot from the CBFS library directly. That should make it easier to more closely integrate vboot into CBFS in the future. Change-Id: I7b9112adc7b53aa218c58b8cb5c85982dcc1dbc0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18intel/apollolake: Remove CBFS locator overrideJulius Werner
This patch removes the CBFS locator override for the Apollolake SoC and instead integrates the extra sanity check it was used for straight in the boot device initializer. Change-Id: Iccdb885be233bb027a6a1f2cc79054582cbdf3fc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-18mb/facebook/monolith: Update power supply settingsWim Vervoorn
Update the IccMax for the SYSTEM_AGENT and IA_CORE power supplies according to the information in the schematic. The IccMax for these supplies is lower than the standard supported by the SoC. BUG=N/A TEST=build Change-Id: I20b92e7dfc85427bcf9cb9f0efda02459c862809 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mainboard/puff: Fix ACPI tables to advertise correct featuresEdward O'Callaghan
Provide Puff with it's own copy of ec.h copied from the baseboard/includes however with the battery, lid and ps2 defines stripped. This is to ensure the correct ASL is generated so that we don't advertise PS2 keyboard support and battery/lid interrupts which don't exist. V.2: drop EC_ENABLE_ALS_DEVICE as well. V.3: set MAINBOARD_EC_SMI_EVENTS to 0 and drop EC_HOST_EVENT_LID_CLOSED smi event. V.4: drop EC_HOST_EVENT_MODE_CHANGE && provide wake pin for EC for _PRW WoL method V.5: drop EC_HOST_EVENT_KEY_PRESSED BUG=b:147850335 BRANCH=none TEST=builds Change-Id: If13bd124c7229ced996efb841980604d13be09af Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-17mb/tglrvp: update gpio pin mux for NVMeWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38286 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-17drivers/spi/spi_flash: organize spi flash by sector topologyAaron Durbin
By grouping the spi flash parts by their {vendor, sector topology} tuple one can use a common probe function for looking up the part instead of having per-vendor probe functions. Additionally, by grouping by the command set one can save more space as well. SST is the exception that requires after_probe() function to unlock the parts. 2KiB of savings in each of verstage, romstage, and ramstage on Aleena Chrome OS Build. Change-Id: I9cc20ca0f3d0a1b97154b000c95ff2e7e87f3375 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-17drivers/spi/spi_flash: introduce common spi_flash_part_id objectAaron Durbin
To further drive to a common approach for describing the spi flash parts in the drivers add spi_flash_part_id object. All the drivers are updated to utilize the new object. Additionally, the driver_private is also not needed in the spi_flash object. A Chrome OS build of Aleena provides 960 byte saving of text. A subsequent patch will save more memory. Change-Id: I9c0cc75f188ac004ab647805b9551bf06a0c646b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-17drivers/spi/spi_flash: remove continuation byte supportAaron Durbin
There was code to handle the case of continuation bytes for identifying the manufacturer id to a jedec rdid command. However, all the parts that currently supported have this defined to be 0. Remove the unused continuation byte support. Change-Id: Ia7c63162e4ef9dc46ef916ca8c31ebd721cbeca7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38361 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-16/mb/google/hatch/variants/helios: Remove MAX98357A devicetree entryKrishna Prasad Bhat
Helios does not have MAX98357A speaker amplifier, so remove the devicetree entry. BRANCH=firmware-hatch-12672.B Change-Id: Id02410553f018385d407086b2f9bc3ee1e7a5f40 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@google.com>
2020-01-16soc/intel/{cnl,icl,skl, tgl}: Move SOC_INTEL_COMMON_BLOCK_THERMAL into SoC ↵Subrata Banik
specific Kconfig This patch moves common pch code SOC_INTEL_COMMON_BLOCK_THERMAL Kconfig selection into SoC specific Kconfig selection as PCH thermal device is not available with latest PCH (i.e. TGP and JSP). Also added TODO for TGL thermal configuration as applicable. TEST=Able to build and boot TGL RVP with this CL Change-Id: Ibce17cc9f38fb666011ccd8f97bee63033ff5302 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38444 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-16drivers/spi/spi_flash: add missing status() command callbacksAaron Durbin
The adesto, amic, atmel, and stmicro spi flash drivers didn't have the status() call back. These parts do support the status command retrieval. Fill them in accordingly. Change-Id: Ie0e63bec844b8e01e292ef8c4df707494df02e69 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-16drivers/spi/spi_flash: separate out protection opsAaron Durbin
Put the write protection into its own object. This allows for easier future reuse of objects in future consolidation patches. It's also possible to eliminate the code implmementing these in the future if the platform doesn't require it. For now leave current behavior as-is. The names of the callbacks were shortened as they are now in the spi_flash_protection_ops object which is a new field in the spi_flash object. Change-Id: I2fec4e4430709fcf3e08a55dd36583211c035c08 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-16drivers/spi/spi_flash: assume spi_flash read callback existsAaron Durbin
spi_flash_erase() and spi_flash_write() already assume their respective callbacks are supplied in the spi_flash_ops object. Make the same assumption in spi_flash_read(). In order to do this the spi_flash_ops objects from the drivers need to reference the the previously used fallback read command, spi_flash_read_chunked(). This function is made global and renamed to spi_flash_cmd_read() for consistency. By doing this further dead code elimination can be achieved when the spi flash drivers aren't included in the build. A Hatch Chrome OS build achieves a further text segment reduction of 0.5KiB in verstage, romstage, and ramstage. Change-Id: I7fee55e6ffc1983657c3adde025a0e8c9d12ca23 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-16nb/intel/sandybridge: sort LANEBASE_* defines by their addressFelix Held
Change-Id: I32fcd36298f41d3b6d8b3e16b6641b9404220461 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16nb/intel/sandybridge: add macros for byte lane register offsetsFelix Held
This patch doesn't change the resulting binary of a timeless build. Change-Id: Ife0e70699df3efa162f8f6c0fd8c2928887fda2d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16nb/intel/sandybridge: refactor code around lane_base[]Felix Held
This is to get a uniform format that matches the macros added in the next patch, so that said follow-up patch won't change the output binary. lenovo/x230 still boots with this patch. Change-Id: Ibfbeb847cab09427a57bef3cbd2069036de5a21e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-15mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft resetPiotr Kleinschmidt
LDN 0xf keeps registers with open-drain configuration of the GPIO. Enabling the LDN is required for proper GPIO soft reset operation by the SuperIO driver. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia769e3d8e66015297942bddf328a6fde0bb27ce6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15superio/nuvoton/nct5104d: Add soft reset GPIO functionalityPiotr Kleinschmidt
So far, only hard power off could reset GPIOs state to defaults: IN, Open-drain. Now, defaults are set with every boot to ensure that GPIOs are not in unknown/unwanted state. Change-Id: I67878dbab2ddf0deaaa8f5d79416368c6164ba1d Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15soc/intel/common/block/fast_spi: don't include all spi flash driversAaron Durbin
The fast spi driver implements hardware sequencing which abstracts away the underlying spi flash commands in the hardware block. It also has its own spi flash probe function to intercept the spi flash ops. As such it's not necessary to include all spi flash drivers. On a hatch Chrome OS build this saves 9.5KiB of text in each of verstage, romstage, and ramstage. Change-Id: Ifb1b962cde3a6a02353ddf83279234057a9ec2fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-15drives/spi/spi_flash: add option to not select all driversAaron Durbin
Add a new Kconfig option, SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS, to make it easier for other parts of the code base to indicate that all spi flash drivers should not be included. Change-Id: Ibf2c4f1d2b8a73cff14bb627ddf759d7970920ea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-15soc/intel/tigerlake: Update header filesRavi Sarawadi
Modify header files to update/include tigerlake: - IOMAP BARs according to silicon reference code - Update Serial IO devices according to PCH EDS - Add board types BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I185f2c22c54a6ae386527069606abb52cce1ec80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-15nb/intel/sandybridge: refactor lane_registers[]Felix Held
Rename array and use defines for the values. The patch doesn't change the resulting binary when using BUILD_TIMELESS=1 Change-Id: I774373d231a0f4a2fe82ab7c6f1318fc56bcc678 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 16:48:50 +0000