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2015-03-27tegra132: separate/refactor clock enable/reset codeTom Warren
Added distinct functions for clock_enable and clock_clear_reset, and rewrote clock_enable_clear_reset() to use them. Useful when unpowergating SOR partition, for instance, where we need to enable a bunch of periph clocks, unclamp SOR, then take all of those periphs out of reset. BUG=none BRANCH=none TEST=none, built rush/ryu OK. Change-Id: I92edf3104adc8eb7637c47a5e000788fd55f1452 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fd76a6d0d0fb7922c6beacbc1cfcb365b6537b2 Original-Change-Id: I6fef5a72421cb4e3d7edb33a66f62b6e14865a32 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212916 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8991 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: never recover cbmem from romstageAaron Durbin
Tegra132 has 2 different paths for booting and resuming from sleep. The boot path uses the typical bootblock, romstage, and ramstage. However, the resume path is completely orthogonal. cbmem_initialize() attempts to recover the cbmem area, but that functionality should not be used from romstage because tegra132 is by definition in a fresh boot if it is executing romstage. Therefore, use cbmem_initialize_empty() so that cbmem is always initialized from scratch on each boot. BUG=chrome-os-partner:31239 BRANCH=None TEST=Built and ran on ryu. Was able to enter recovery and stay in recovery without entering a reboot loop. Change-Id: I0453c15e57a873a7ce7a63190dceafb75e4c9342 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 28ebc092e6721552c18db03e7578424c23a64b64 Original-Change-Id: I2016146fdc3aea493a78bab31ea8c8cbd78935c5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211424 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8990 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27samus: Update SPD with correct geometry and timingsDuncan Laurie
This memory is also x16 and needs slight tweak to tRFCmin in order to be functional. BUG=chrome-os-partner:31833 BRANCH=None TEST=build and boot on EVT unit with this config Original-Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217190 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 6c4bf71c8c8e1e46ce290441c2e21bc7b2839760) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I389936d85e61a0a939cd4485fcc0723d2a0aa4d6 Reviewed-on: http://review.coreboot.org/8972 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-27broadwell: Fix some errors in selftestKane Chen
1. Fixed some errors in selftest compare to reference. 2. Some WA steps for xhci in sleep trap is only for lpt. BUG=chrome-os-partner:28234 TEST=compile ok, run selftest on auron to verify boot to OS BRANCH=None Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Change-Id: Iaccb087581d5f51453614246bf80132fcb414131 Original-Reviewed-on: https://chromium-review.googlesource.com/215646 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> Original-Tested-by: Kane Chen <kane.chen@intel.com> (cherry picked from commit 97761b4ad3073fff89aabce3ef4f763383ca5cad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2b1d5be4f8a13eb00009a36a199520cd35a67abf Reviewed-on: http://review.coreboot.org/8971 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27samus: Add PD MCU ACPI device and unmask host eventShawn Nematbakhsh
Samus has a PD MCU, and should handle PD MCU host events. BUG=chrome-os-partner:31361 TEST=Manual on Samus. Verify that ACPI Notify routine is called when host event is sent from EC. BRANCH=None. Original-Change-Id: Id40ebd438b3dd60cefc7650f2edc695c589343e9 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214860 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> (cherry picked from commit d0752be013f66313d4218338e62372d0f5975097) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I08eb51eceeb7d2835d55e7e861126b137de72bf6 Reviewed-on: http://review.coreboot.org/8969 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27chromeec: Add ACPI device for PD MCU and handle related EC host eventShawn Nematbakhsh
Add ACPI device for PD MCU, if present. Call Notify routine when the corresponding EC host event is received. BUG=chrome-os-partner:31361 TEST=Manual on Samus. Enable EC_ENABLE_PD_MCU_DEVICE, unmask PD MCU host event, and verify ACPI Notify routine is called when host event is sent from EC. BRANCH=None. Original-Change-Id: I6db61031e434d7ecb211802a4caeaba051e22a28 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214809 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> (cherry picked from commit 226b349e40ed8eacce20d0a8063877382f707c69) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iecff6c06f1b37651ff61e36d6085d397d66f861c Reviewed-on: http://review.coreboot.org/8968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Apply pcie updates from 2.1.0 ref codeKane Chen
some clock gating and pcie settings are missed in original code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214568 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 57e42c781d435092a08238461f0605dbf092e576) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia62a50f28a411bbd2ba51b94de17ca70051ea093 Reviewed-on: http://review.coreboot.org/8967 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27broadwell: Read and save HSIO version from ME in romstageDuncan Laurie
This can be used to know if HSIO registers need updating in ramstage but it is not possible to query the ME for HSIO version after sending the DRAM-init-done message. BUG=chrome-os-partner:28234 BRANCH=samus TEST=build and boot on samus, check for HSIO version messages in log Original-Change-Id: Id6beeaf57287e8826b9f142f768636a9c055d7eb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214259 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 637cbf5c1a1d922dab3f8a5cd4b3cd05617d1b92) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29ce907804e892afde5f91e0b21688a50217cf13 Reviewed-on: http://review.coreboot.org/8966 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix GPE register addressesDuncan Laurie
This macro is incorrect and should be counting by dword instead of byte. The effects of this were subtle: incorrect events in ELOG and hanging when waking from USB input because PME_B0 was not disabled properly. BUG=chrome-os-partner:31611 BRANCH=none TEST=test wake from suspend with USB keyboard Original-Change-Id: I7caf1d46283071787550a9765703897181774957 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214258 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3cfc4a1812466cb1c1317b8f21321aafee623857) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3e2f8190d824692ecb961615becf65319a6ffd8b Reviewed-on: http://review.coreboot.org/8965 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Changes from 2.2.0 ref codeDuncan Laurie
- The SATA CAP register setup was moved outside the refcode blob we run so it needs to be set up by coreboot again... - Slight tweak to fast ramp voltage for broadwell CPU BUG=chrome-os-partner:25491 BRANCH=None TEST=Build and boot on samus Original-Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173 Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org> Original-CReviewed-on: https://chromium-review.googlesource.com/214024 Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5d166a0c4d206eaa885ecebaa0c3cefefdc59280) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id58d3bee5e713139edf6e8fda8cdf4c48ba95bd1 Reviewed-on: http://review.coreboot.org/8964 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Updates for EVT boardDuncan Laurie
- Remove NFC GPIOs - Change EC wake to GPIO27 - Enable wake on HOTWORD_DET_L_3V3 - Add new Hynix memory SKU BUG=chrome-os-partner:31549 BRANCH=none TEST=emerge-samus coreboot, cannot fully test until EVT Original-Change-Id: Ia25fc39f0b67c53305b3fd9150117d6a7867eb3a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213796 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 740ac0bb7eaa9ae35fce8a04825f9c5ecf7cab79) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2b1c194eae2ebc53291f078c00ba04f82e10b0c1 Reviewed-on: http://review.coreboot.org/8963 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Switch to using broadwell platform ASLDuncan Laurie
Instead of providing a local copy use the chipset provided one. BUG=chrome-os-partner:28234 BRANCH=none TEST=build and boot on samus Original-Change-Id: I60dd9bbeefbf4298511abec54635c515fc9b1621 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213793 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9dc8e7ae61f0337aa145b7d99acc23852d1cfc9a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I259be321e01e2047666b4be106dea59a5578d9d3 Reviewed-on: http://review.coreboot.org/8962 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add broadwell specific platform ASLDuncan Laurie
This can be shared between mainboards, they are still free to override if needed. BUG=chrome-os-partner:28234 BRANCH=none TEST=build and boot on samus Change-Id: I85fae6e254adcbda1c52410d5ba046f3f05b54c0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/213792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3e40cb804e7a95ce2183ebb3ef5d86820aef61b5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8961 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: fixed power gating enable for disabled sata portKane Chen
The original code won't set power gating for disabled port correctly, due to it must be set before Lock BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify bit 24, 26 is set in RCBA(0x3a84) for samus Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Change-Id: Id78d391ac657665a972cb4fd1810df6304a5a6ab Original-Reviewed-on: https://chromium-review.googlesource.com/213561 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> (cherry picked from commit 066c8c81df8be9ae9ab7b33342a93b0b3ea7b240) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic7c87b04863f93de5665d72e0f95b4105b1d4d3b Reviewed-on: http://review.coreboot.org/8960 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: sata updates from 2.1.0 ref codeKane Chen
fixed a coding error and sync sata configuration with ref code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I09dd80a9772ac82b841363a540c9b7a8689e04a9 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213137 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 0fbb59e3c5117a513ef19117560bb41dfe8c0d71) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I99a389b06f4ec077c298100ca878c68ef69debfa Reviewed-on: http://review.coreboot.org/8959 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix devslp enable to use correct registerDuncan Laurie
This was a merge error when I was pulling in some of the code into this file I put it after the read of CAP2 but before it is modified and written back. In the end the DEVSLP bits are getting set/cleared that need to but the other bits in the register may be wrong. Also when enabling devslp set the devslp-present bit in each enabled port. Also remove much of the 0:1f.2@0x98 setup and the attempt to write (the write once) CAP register that is already being written in the reference code. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212308 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9110a42982183b2954c865abbf18e008a39c997c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7db5c7ccf619aa28856388dd40f59495ef6d7e77 Reviewed-on: http://review.coreboot.org/8958 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add small delay before Flex Ratio rebootDuncan Laurie
In order to prevent possible TPM lockout due to PLTRST assertion shortly after powering up add a small delay before the reset. This will affect cold power up only, reboot/resume/warmboot will all have the flex ratio locked already so this reset is unneeded. BUG=chrome-os-partner:29859 BRANCH=None TEST=build and boot on samus. I tried unsuccessfully to trigger the TPM lockout, but I was not able to do that consistently without this patch so it is unknown yet whether this is 100% effective. Original-Change-Id: Ief8c9261c0268b0f90a3022213ebd2b06633b481 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 20413f2eafa144f5f381eb6f92d8b959415ca049) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I665e9ed1faa65e88d988660a24bdad40a4c5ab7e Reviewed-on: http://review.coreboot.org/8957 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix TCO register size and event reportingDuncan Laurie
TCO registers are 16bit not 32bit. Also do not log the TCO reset event in S3 resume path to avoid it being logged when TCO is not actually tripping. BUG=chrome-os-partner:28234 BRANCH=None TEST=manual: 1) build and boot on samus 2) modify kernel command line with nmi_watchdog=0 3) while sleep 1 ; do echo -n V ; done > /dev/watchdog & 4) fg 1 5) ctrl-Z 6) wait for reboot 7) check event log for TCO event 8) check suspend/resume path to ensure no TCO event logged Original-Change-Id: I9cd8627de8498b280deb088f3a8e1e20546e2f96 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211840 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5952fe4672d07bd39e345f2048c2bfc510bf9f2a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6cdeffb8b50c5001d714edd3a1264cf117cd1ad6 Reviewed-on: http://review.coreboot.org/8954 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Enable WLAN wake GPIO in _PRWDuncan Laurie
Add ACPI device for WLAN and enable GPIO 10 as wake source in _PRW. BUG=chrome-os-partner:28234,chrome-os-partner:30671 BRANCH=None TEST=boot on samus, check for WLAN in /proc/acpi/wakeup Original-Change-Id: I09b6eeae5bd88ee9d7e0b7e735ed871e8ae6963a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211820 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c65ce028e64aebffb99648b2c34c4ff0e7c4e70f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If192564ddd10c7fe758a4d7266394a30e7d966d4 Reviewed-on: http://review.coreboot.org/8953 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Misc updates from 2.1.0 ref codeDuncan Laurie
- ADSP IRQ should be exclusive - HDA should write reg 0x43 even if disabled - A few clock gating tweaks based on ref code changes - Move SATA clock gating to sata.c where SIR changes are done - Add support for enabling Deep SX in AC/DC modes - CLKREQ VR Idle for enabled PCIE ports BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211611 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99 Reviewed-on: http://review.coreboot.org/8952 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Fix some SPD geometry againDuncan Laurie
I was using the wrong datasheet for these parts. Revert to the previous geometry settings so they work again. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: Ibc4a864d458e5ee5ef69aa4f1db5efe14076422a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211610 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f8591e1579d205609a959082d8047d407b4f6a5a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I52ed3609c9686fef13711578597065ca4e907df4 Reviewed-on: http://review.coreboot.org/8951 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Disable CMDPWR on broadwellKane Chen
Workaround for auto shutdown issue on broadwell SKU. Now we can see C7 transition, and MRC fastboot BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build ok and boot on samus Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Commit-Id: 932152b16c3943b00bd317e7370402dda451529f Original-Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e Original-Reviewed-on: https://chromium-review.googlesource.com/210870 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> (cherry picked from commit 932152b16c3943b00bd317e7370402dda451529f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie9fb792635b39d33136cef576ae5559013d5947a Reviewed-on: http://review.coreboot.org/8950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Tweak GFXPAUSE settings based on revisionDuncan Laurie
Changes from 2.1.0 reference code release. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I6110a9bdb2973f1a134d8105c37659bf43f61d34 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210607 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit ef660ddc6c17a003f06b8995e821c7642c49a56e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibb41cd7369cfc7b9b86b61460650a56415b3d8fb Reviewed-on: http://review.coreboot.org/8949 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Update SPDDuncan Laurie
- geometry was incorrect for 8GB modules, should be x32, so refactor the rest of the geometry to match - some of the timing values were off, calcualte new values from the datasheet BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I645f354ef21c5032ab73c66e1ad843136ec93eff Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210660 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8b2ce5c58442e039f5f6e0e053c0072fdec76e9c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29daa9e0ad1bf32be914c0d998f188b9827344a1 Reviewed-on: http://review.coreboot.org/8948 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add config option to disable DSP power gating in D3Duncan Laurie
This is useful for debug and testing. BUG=chrome-os-partner:29649 BRANCH=None TEST=build and boot on samus Original-Change-Id: I9050e75fd7c308ebd97d196298c687f8b0f8f97d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210599 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 2831154af4f33717489cb0b62aef228fb8f7c2e2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie622df02d9ab219cefce5f11332e010b47e3ec6e Reviewed-on: http://review.coreboot.org/8947 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-26timer: remove rela_time typeAaron Durbin
Current usage doesn't require rela_time. Remove it. BUG=None BRANCH=None TEST=Built and booted. Change-Id: I25dcc1912f5db903a0523428ed1c0307db088eaa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 26a13d4c615473407f401af4330199bbfe0dd2b1 Original-Change-Id: I487ea81ffb586110e9a1c3c2629d4af749482177 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219714 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8896 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26rk3288: switch to stopwatch APIAaron Durbin
Instead of using rela_time use the stopwatch API as the semantics fit perfectly with the expiration usage. BUG=None BRANCH=None TEST=None, but similar usage tested on tegra132. Change-Id: I91ef59212a2dd1b48640b1aaaab6acacf4e9b3e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b1dd8380f04641f4f73caa3441f349d9eca6be05 Original-Change-Id: Iff3293debc2f85553c9e9b765084e5c00720012c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219713 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26cbfs: support concurrent media channels properlyVadim Bendebury
Coreboot generic CBFS media API does not support multiple media access instances, but it should. With this fix the CBFS context (memory cache for SPI accesses) is shared among all open media access streams. A better memory management scheme might be required, but for now this fix allows to support booting deptcharge and accessing VPD through two independent CBFS media streams. BUG=chrome-os-partner:32152 TEST=no exception is thrown when the second stream is opened Change-Id: I62889089b4832c9e9760ef24ecc517220d8f3ec4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 691f9794805d04beff349f1bc60ac9d7530d7cbf Original-Change-Id: Ib9d9d1f5209c2e515a95d7acbf4a8ac1255d3f8a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219441 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26rush: Remove CHROMEOS defaultPatrick Georgi
We don't set these by default in upstream. Change-Id: Ida7aa498e0fe291c6cf3cf31d6516530a9d136d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/8988 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-26Chrome OS vendorcode: Fix vboot_reference compilationStefan Reinauer
Includes moved into $(CPPFLAGS_*), so add that to VBOOT_CFLAGS. Shift vboot build parameters from the environment to be make parameters, and use $(MAKE) instead of make to fix non-Linux build systems. Change-Id: I5aee9935ab36ad571fbcf9f6fa8d8ace2bac16b3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8703 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-26tegra132: allow mainboards to insert memory regions in address mapAaron Durbin
Depending on the needs of the mainboard certain regions of the address map may need to be adjusted. Allow for that. BUG=chrome-os-partner:31293 BRANCH=None TEST=With ryu patches able to insert a non-cacheable memory region. Change-Id: I68ead4a0f29da9a48d6d975cd41e2969db43ca55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 88342562885b09c4350ba1c846b725b5f12c63d9 Original-Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212161 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8925 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26arm64: Seed the stack at stage_entryFurquan Shaikh
Seed the stack in order to avoid boot process from complaining false stack overflow. BUG=chrome-os-partner:30824 BRANCH=None TEST=Compiles successfully for rush and stack overflow error fixed in boot flow Change-Id: I5d29d24eb5270d38a35a32171881b1aab8bf32e5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 26e53568e82ad8418c20c2410f0cbc5c444c9917 Original-Change-Id: Ie51e1bcd263e3b886feb2e0e9c7d544f23c3444e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210594 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8942 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: Initialize CNTFRQFurquan Shaikh
BUG=chrome-os-partner:31356 BRANCH=None TEST=Kernel boots with the changes required in depthcharge Change-Id: I061305e0ab8f6145c0dc74b2ff958a667ff7276a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ff2fc86c1c6e6b592fa3faffd360a3a8c6351a9 Original-Change-Id: If1c5850607174ab0f485ef41d47016056d9832cd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212730 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8941 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add I2C6 controller to funit libraryTom Warren
BUG=None BRANCH=None TEST=Built rush and ryu, ran on rush into recovery mode. I2C6 is in the SOR domain, so a lot of further init is needed before it can be used. A follow-on patch will do this. Change-Id: I5701bfcf1d0bb8c6edd3d885b1b7dd14e67ba73a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 69908f2489d1a918bb109d43e713932214741b46 Original-Change-Id: I1160a182ee6e2b2b56479384efc6a9063590448f Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212671 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8940 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: enable external usb 2.0 portAaron Durbin
BUG=chrome-os-partner:31293 BRANCH=None TEST=Able to get sporadic USB communication in depthcharge on ryu. Change-Id: I6bf6559d167a6ea94523d2500b54c1c7854330f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e5412cfc149902298f2ebeb3030d8f09f27e5ee8 Original-Change-Id: Ic5402d18943c3cc8fb4556c47e587134633fbf72 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212333 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8939 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add usb initialization support to funitAaron Durbin
Continuing down the path of easing mainboard maintenance provide a way to bring up the USB 2.0 ports through funit. BUG=chrome-os-partner:31251 BRANCH=None TEST=With ryu patch was able to get same sporadic USB communication. Change-Id: Ic75821acf1d48a9f1659849fa007251c61658640 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5183c5081a95219f84c4d6dfca70926b383abc1a Original-Change-Id: Iee5ca30b3c8b876a9cae7b91db096fef933a8412 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212332 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8938 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26rush: Add usb support for rush in corebootFurquan Shaikh
BUG=chrome-os-partner:31293 BRANCH=None TEST=With non-cacheable memory region and dma range addition, booting from usb reaches the same point as mmc. Change-Id: I218c751f41fb881af4fed0bcccc378dde1fd07b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a26e07b58f454c598bf5b7a4940c238135548bbd Original-Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211039 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8937 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: include what is actually usedAaron Durbin
The clk_rst.h file wasn't including files that had functionality it was using resulting in broken builds if just this file was included. BUG=None BRANCH=None TEST=Built with just this file included -> no more errors. Change-Id: I229cb3890f1320edc3bc3e82469b301cbaff0f72 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 03b455aa9da64d6e110690206db65939ca023c27 Original-Change-Id: I8dc0fcab363e1089587e6dc8ff04c2a76c5e364c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212331 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8936 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: provide more robust array bounds checkingAaron Durbin
Make sure the array size matches the number of supported FUNITs. Also remove the FUNIT_NONE enumeration so that there isn't an empty slot in the array at index 0. BUG=chrome-os-partner:31251 BRANCH=None TEST=Built when array wasn't large enough. Compiler threw an error. Change-Id: I1b83ddff799a56ea39efa23a91dca1a9e0f10862 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4cbe74905bbeb815e9f20bcc0fad3751a3133b04 Original-Change-Id: I0bb37c51311d202729b7fb9731d6eec0a28dc040 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212330 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8935 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add base addresses to funit structuresAaron Durbin
To provide easier access to the base addresses of the controllers by funit identifier add the base addresses to the data structure. BUG=chrome-os-partner:31251 BUG=chrome-os-partner:31106 BRANCH=None TEST=Built. Change-Id: I427d432beef36e6342c188d607c0e33b3845c0e1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c8f09e61e3dbfbc96980b98ad25e09554fd49a8d Original-Change-Id: Iff5564b250dcf2038252d54a4caec3df5f7f3de7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212169 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8934 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add more base addresses to address mapAaron Durbin
Provide consistently named base address enumerations as well as provide some that were missing. BUG=chrome-os-partner:31251 BRANCH=None TEST=Built. Change-Id: I2551bbaa83d1d2c158b87d239098c22fba4d3961 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 07954a231f3c11c4102f9db0a2d35654abda208f Original-Change-Id: I75030598f7da7dacf8e8eff1d7427c5bf202814f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212168 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: break out clock config in funit libraryAaron Durbin
In order to prepare for USB initialization move the clock configuration into a separate routine in the funit library. BUG=chrome-os-partner:31251 BRANCH=None TEST=Built and booted into recovery mode. Change-Id: I090b5d12c5805f0179c29cfc62499fad2f245c01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f7adaf969762b8296034f4373f550a902d1ed06b Original-Change-Id: Iea6cd2fbe8369a91c06b15d94b63c409ae83124f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212167 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8932 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: use pointers in funitcfgAaron Durbin
Just use direct pointers to the registers in the pre-filled data structures. In 64-bit the sizes increase, but it's small. The fields now directly point to the correct register so no need to do any arithmetic to identify the correct register. BUG=chrome-os-partner:31251 BRANCH=None TEST=Built and booted on ryu into recovery. Change-Id: I0de85c486c005aed23b6118ec91b45dd39acdfb0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 358b78c1c4cb72e0166f91b36011676e65576666 Original-Change-Id: I186bf5d145437472126067960e62d7ed6a25f295 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212166 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8931 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: convert hardware initialization to funit APIAaron Durbin
Use the new funit API to do all the dirty work. BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and ran through depthcharge and into recovery just like before. Change-Id: I8625a06dd847bd3dcfc3ce5a50a31d6aff0b860f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ebc04a174269ae072eda804e172fd24362f417d2 Original-Change-Id: Ief2d81c5569c33a90fc9458d741edef1dcbd8239 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212152 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8930 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add i2c2 controller to funit libraryAaron Durbin
BUG=chrome-os-partner:31251 BRANCH=None TEST=Built and ran on ryu through depthcharge into recovery mode. Change-Id: Ie49968c47d59b3149fc75e709825129b3cd9b09f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0cf78e310e51426371b0632e089eef500d687e48 Original-Change-Id: I76fa8f1c3469b049df7f5bf943701ce18deeb927 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212151 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8929 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26rush: support for DMA regionFurquan Shaikh
Currently rush needs a DMA region in order to communicate with USB devices. Therefore, add that region to the memory map. BUG=chrome-os-partner:31293 BRANCH=None TEST=With the changes for adding non-cacheable memory range and adding DMA region, booting from USB reaches same point as MMC. Change-Id: I82d97840fad8cc96bf958c6efa13d2fdc1233d79 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b182651a1b6db1a7adbf315b6865467590a0785c Original-Change-Id: I6a465eaa77e0d5ab4d5fb22161e88e7a5fd9c4a8 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212193 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8928 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra: Clean up USB codeFurquan Shaikh
Pull out the common usb setup utmip functions from t124 into tegra usb.h. These can be reused for t132 as well. BUG=chrome-os-partner:31293 BRANCH=None TEST=Compiles successfully for nyan, big and blaze Change-Id: Idddd40e409b56875436db6918d05f2889d83870b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 12f12cb30a033cce645f53457d13a987aeec22a1 Original-Change-Id: I83f83bafad0f52ad651fe5989430f41142803f2b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211200 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8927 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: support for DMA regionAaron Durbin
Currently ryu needs a DMA region in order to communicate with USB devices. Therefore, add that region to the memory map. BUG=chrome-os-partner:31293 BRANCH=None TEST=With usb added am able to talk to a USB mass storage device albeit inconsistently. Change-Id: I7efaf2ba44cc94dc64af3f1cd916bdc5c7ff0795 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e93389479518ee28dc3477da0c6e6e33fa8a47d1 Original-Change-Id: I6b5c052ccaafce30705349e07639dffbb994901f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212162 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8926 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26arm64: handle non-cacheable normal memoryAaron Durbin
Non-cacheable normal memory is needed when one wants an easy way to have a DMA region. That way all the reads and writes will be picked up by the CPU and the device without any cache management operations. BUG=chrome-os-partner:31293 BRANCH=None TEST=With a bevy of other patches can use a carved out DMA region for talking to USB. Change-Id: I8172f4b7510dee250aa561d040b27af3080764d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a5bc7ab1709edd97d8795aa9687e6a0edf26ffc6 Original-Change-Id: I36b7fc276467fe3e9cec4d602652d6fa8098c133 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212160 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8924 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: fix carveout address calculation >= 4GiBAaron Durbin
The high address field was being shifted in the wrong direction resulting in the lower 12 bits of the upper address being dropped. BUG=chrome-os-partner:30572 BRANCH=None TEST=Was able to run on ryu and not hang while wiping memory. Change-Id: If1d7ef1c63ce79c143af3c5012b206ee297cd889 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6b0da6fa391db2ec2bc1e0bec9325f4e74b5286c Original-Change-Id: I7bf173bb0373d2d25ce9014c80236fb55cc8e17e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211941 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8923 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26rush: Convert rush initialization to use funitcfg apiFurquan Shaikh
Use funitcfg api for bootblock, romstage as well as ramstage initialization in rush. BUG=chrome-os-partner:31251 BRANCH=None TEST=Compiles successfully and boots till last known good point. Change-Id: I243597de9ec13904a2bb58a04b402f9545424760 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0618ea6828bae3e700b85b79b185aec28568b8ae Original-Change-Id: I8f5801c1c214f05ef9d2ba976838605da2d8b914 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211766 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8922 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26t132: Implement clock initialization api for functional unitsFurquan Shaikh
This api provides a common interface to initialize various clock sources, dividers as well as enabling the clock for various functional units. BUG=chrome-os-partner:31251 BRANCH=None TEST=Compiles successfully for rush and boots till last known good point. Change-Id: I2b8df5abf7301bc940315427af4cb38a635f07f8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9814f93a9f99fc9df6267167f991ebef427e9ae3 Original-Change-Id: I7abb193d6a9cfa448df1c48c346b4edbad802329 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211765 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8921 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26t132: ryu: Correct how board id is retrievedJimmy Zhang
Two changes: 1. A44 ID straps use different gpio pins than nyan. 2. A44 uses tristate values instead two state values. BUG=none BRANCH=none TEST=Built and tested on A44 board. Change-Id: I6a36f6da0c9f6168780606ba76595c7a0af8e8bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2eb0cae0e3396da1eaeaa72411c4b74300138a7b Original-Change-Id: Ia2a4309d3b63b0a94d79465dd727b01fae01e1b9 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211753 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26fix how to interpret board id read from gpiosDaisuke Nojiri
nyan blaze fails to boot because tristates of the board id are interpreted in the reverse order. this change fixes it. BUG=none TEST=Booted Blaze to Linux. Built firmware for Storm. Branch=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I4ff8a15cf62869cea22931b5255c3a408a778ed2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3f59b13d615a8985edf2029d89af05e95aefad33 Original-Change-Id: I6d81092becb60d12e1cd2a92fc2c261da42c60f5 Original-Reviewed-on: https://chromium-review.googlesource.com/211700 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/8980 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26Restore name of the function reading tertiary GPIO statesVadim Bendebury
The name was changed due to review comments misunderstanding, it should be restored to properly convey what the function does. BUG=chrome-os-partner:30489 TEST=verified that Storm still properly reports board ID Change-Id: Iba33cf837e137424bfac970b0c9764d26786be9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c0fff28c6ebf255cb9cf9dfe4c961d7a25bb13ff Original-Change-Id: I4bd63f29afbfaf9f3e3e78602564eb52f63cc487 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211413 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8979 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: Update BCT to Max Frequency 924MHzJimmy Zhang
Replace previous 528MHz BCT. This BCT contains four entries as below: 0: Samsung 1: Hynix 2: Micron 3: (spare) 528MHz Micron BUG=none BRANCH=none TEST=Built and tested on Micron LPDDR. Change-Id: Ibe9e299ac1dd4cabd390b2e78bbec6c0f3a3871b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3fcb3e82998c88220e87118efff0595ba3572e38 Original-Change-Id: I49e18ca8dc69f2ce9ded71f4f55c02a8b91f92b2 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211479 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: convert mainboard initialization to use padconfig APIAaron Durbin
BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and booted through depthcharge on ryu Change-Id: I79373a171922bffacb56f8ba2c0f8d40d0215963 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d635c8b67658fa95ab2688eac926334849c286a2 Original-Change-Id: I129c17045db95732aa7d548ba6dde754937fdb08 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211192 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: move common bootblock init into SoC codeAaron Durbin
The current 2 boards were setting up clocks and enabling peripherals that apply to the SoC generically. Therefore, move the common pieces into the SoC code. BUG=chrome-os-partner:31105 BRANCH=None TEST=Built and booted through depthcharge on ryu. Change-Id: I94ed4b5cc4fafee508d86eefe44cf3ba6f65dc3b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6dad573c8689b79bb4aa615811a10f44e7d8c809 Original-Change-Id: I6df1813f88362b8beaf1a716f4f92e42e4b73406 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211191 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8917 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-26ryu: configure EC I2C pads as open drainAaron Durbin
The I2C pads connected to the EC are pulled to 3.3V. Therefore the pads need to be configured as open drain. BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and booted through depthcharge on ryu Change-Id: Ie5eadfe6aca78eb31fbca4e8d8117d1061acbbec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1530e7e7f500be47355eada56591ac2dbf1e9326 Original-Change-Id: Ia4ad2377d01296235fc7efbba72fa790016c04af Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211135 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8916 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-26ryu: use EC proto v3 over i2cAaron Durbin
Ryu's EC talks proto v3 over i2c. Select the correct protocol. BUG=chrome-os-partner:31148 BRANCH=None TEST=Built and ran on ryu. Coreboot can speak to the EC now. Change-Id: Iaed0d2db3c3c93667d65beea98b9719bdbbbfe41 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b71cad3bb1e9b64c48b6f2eeb7573c408a508fb3 Original-Change-Id: I50e192cd58f7a29103ab94afc002da18822d4080 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211240 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8915 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: enable vboot firmware verificationAaron Durbin
Add the supporting Kconfig options and infrastructure for performing vboot firmware verification. BUG=chrome-os-partner:30784 BRANCH=None TEST=Built and ran on ryu into depthcharge noting vboot paths being taken. Change-Id: I1d803208cd5789bd73244b91beac6a5a4598ea70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a2e7d84725739843a1ed1868fcadebb60477a6dc Original-Change-Id: Ie4c8c3939990a12fc528423948b236230392eb7c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211134 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8914 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-25tegra132: enable pinmux input for PAD_CFG_GPIO_INPUT()Aaron Durbin
The original intent was to set the equivalent flags by default for the PAD_CFG_* macros so as not to make the usage too chatty. The GPIO_INPUT variant didn't have the PINMUX_INPUT_ENABLE field set. Therefore, automaticaly set it for PAD_CFG_GPIO_INPUT(). BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and ran on ryu. Change-Id: Iab058874314430de08010912c3fc758a98b73eb0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 535cdb354efc067caf32d32641846f11fb0cd2ee Original-Change-Id: Ifb630601cf04d2984542933382aace16540863ad Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211133 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8913 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: select HAVE_MONOTONIC_TIMERAaron Durbin
The tegra132 SoC provides the monotonic timer API. Therefore, ensure the reset of the coreboot infrastructure is aware. BUG=None BRANCH=None TEST=Built and ran on Ryu. Noted that ramsgage is showing timings for each bootstate. Change-Id: Ifc2d5b7eb318ffac0ad79bfbc3d1b61a7ba4b10c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b691572c63a43a01a290f1c00f71097028d1415e Original-Change-Id: I9b8fcf38cba9bdaaf0455701df1d6328bf1927c1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211132 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8912 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: use pre-existing reset APIAaron Durbin
coreboot already has a reset API. Utilize it by selecting HAVE_HARD_RESET. The tegra132 boards have to provide the hard_reset() implementation as that involves board-specific bits. The tegra132 code then provides a cpu_reset() routine that just promotes that call to a hard_reset(). For the existing tegra132 boards remove the unnecessary files from the build. BUG=chrome-os-partner:30784 BRANCH=None TEST=Ensured hard_reset() does something on Ryu. Change-Id: I6d5aa928fec95b361175e35e0a26812829ffdfc3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 31edd4ff7486ded87d2525cd360d48959b6aef7c Original-Change-Id: I1e1b014062dafb5d81fb9da40006c5405073a95d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211131 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25rush/ryu: restore full-speed clocks to TPM I2C and EC SPITom Warren
Now that there's a working udelay() in tegra132, upclock CAM_I2C and SPI1 to the same speeds as used on Nyan. BUG=chrome-os-partner:30998 BRANCH=rush_ryu TEST=Built Rush and tested, no nack errors seen. Change-Id: If1ee6d5c711252e294818d6263732bb34b2fe6f0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 859c0d4fde2cf098cb829e96a5d6dec394bea600 Original-Change-Id: I58fd03ed3512c2498c793cfe30b0c302e4b0e3d4 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211043 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25rush: switch to padconfig API in ramstageFurquan Shaikh
BUG=chrome-os-partner:29981 BRANCH=None TEST=Compiles successfully and boots until kernel FIT header error as before. Change-Id: Ib4160b622c15cc5e4230bb43688a825ef68a69f0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fed2969242909921dc843de063e67b3769d1786 Original-Change-Id: I5637b84d5153c745b4a07a4bf8c72ae1e6f2f21c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211033 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8909 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra: correct gpio_index_to_port() calculationAaron Durbin
The gpio_index_to_port() incorrectly was dividing by GPIO_PORTS_PER_BANK on a value including the bit number. After masking off the BANK offset just divide by the number of gpios in a port to get the port offset. BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and ran through to depthcharge. Printed bank, port, and bit numbers for validation. Change-Id: I3fbbb90f369bace90e787148a58795b7b1b40c1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 97e1f830b4a8e948673433bfa6d81586204b6ee2 Original-Change-Id: I8bb50e922c9fd7c0a1c247ba95394f6deb9f1533 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210909 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8908 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: fix gpio constantsAaron Durbin
I erroneously added GPIO_NONE_INDEX at the beginning of the enum block effectively putting every GPIO index off by 1. Instead, move it to the end. BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and ran through to depthcharge on rush. Also printed out banks, port, and bit offsets to validate. Change-Id: I4f6510c1b6fcdddddbe36ff738299b4439ffc597 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c020c2125b9a2378a7faa17209d1b78e019c7df Original-Change-Id: I0471480e8658de9e534beb859a1f5027a961d73e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210908 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8907 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: output chip information and MTS versionAaron Durbin
It's helpful to be able to track this information. Therefore dump it in to the console log. BRANCH=None BUG=chrome-os-partner:31126 TEST=Built and ran on rush. Revision information is put out on the console. Change-Id: I22e7d222259c1179b90edda6d7807559357f6725 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18d318331b696a6a32e0a45b8f903eb740896b02 Original-Change-Id: Ic95382126a6b8929d0998d1c9adfcbd10e90663f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210903 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8905 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25ryu: Add 4 LPDDR3 SDRAM BCTsAaron Durbin
These are used by the LPDDR3 code in sdram.c. Based on the schematic and email, I've filled in 4 slots in sdram_configs.c. My A44 returns RAMCODE 0 (using only bits 1:0) for Samsung SDRAM. I haven't tested the other 2 types of RAM (Hynix and Micron). The 4th slot is a fallback slow Micron config. Previously existing configurations were dropped. BUG=chrome-os-partner:29921 BUG=chrome-os-partner:31031 BRANCH=None TEST=Built for rush and rush_ryu. Change-Id: I55a737db269fe5fac1565d58bd8f8afcbc5beecb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a431466171a85a5c8151e7466eb5f77862e7b44 Original-Change-Id: If216096ffc9e9836b6d082ad0668640b3eec37b7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Id: a45e7788dd78697ac5f48b6cc64108ca0e4912dd Original-Change-Id: Ib7e8b814eb6dadb9b366536721876a3eeba0d2c0 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216000 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8976 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25ryu: Add three more full LPDDR3 SDRAM BCTsJimmy Zhang
Add in the following BCTs to source code tree: Hynix 4GB 924MHz BCT Micron 4GB 924MHz BCT Samsung 4GB 924MHz BCT BUG=none BRANCH=none TEST=Built and tested Micron 924 bct on A44 board with Elpida memory chip. Change-Id: I59a5cc1133bf41a51f40a771ff0a7b7ef8d549fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a72f1b704928fad341bda460ecc349914ec612c Original-Change-Id: I9e5b54c3eb7ee4c4010b5aaf5dad030eba75108b Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210872 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8904 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25ryu: switch to padconfig API in romstageAaron Durbin
BUG=chrome-os-partner:29981 BRANCH=None TEST=Built. Change-Id: I84abb36d4b39b60837b68c24f5cacffb74c1a985 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 42a5d3a8a8c46b20361522bc5cb1c1faafaae0cc Original-Change-Id: Ib3ee8a14a34d0a2e73f3b912879eb65ac2d97c50 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210900 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25rush: switch to padconfig API in romstageAaron Durbin
BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and ran on rush like before. Change-Id: I8182051314bea1ebfed1ce5346eaa1588daa2b59 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5ec4e7156ce1315c9a6bc6c5e5426cad9b0ef142 Original-Change-Id: Ied3eb82fc1eb656f92875cf4a508de16fb1bc65b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210839 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8902 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: introduce romstage_mainboard_init()Aaron Durbin
Instead of calling out with function names all the possible combinations of interface and device provide one call to the mainboard to configure all the necessary bits. BUG=chrome-os-partner:31104 BUG=chrome-os-partner:31105 BRANCH=None TEST=Built and ran on rush. Change-Id: Id7817e85065884d64f90ac514bf698bf539f2afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4f63f5965d403a32872d7b52c180694f5ef679d Original-Change-Id: Id27d9c2da4dccdff38c48dc5cdeb1a68cf23cbfc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210838 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8901 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-25rush: Fix recovery mode switch functionFurquan Shaikh
BUG=chrome-os-partner:31032 BRANCH=None TEST=Compiles successfully Change-Id: I5c9fa9e613cc24f3f9f17330c5453cdd4306b92a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7ba56b2459889ef24a9ce7331476c258c8b10d3 Original-Change-Id: I97da77c4f2ec3934066916c62491335a6536a85c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210435 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8899 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25rush: Add support for chromeos_ecFurquan Shaikh
BUG=chrome-os-partner:31032 BRANCH=None TEST=Compiles successfully and ec error fixed while booting. Change-Id: I7bb78b8986931407ee67f33e83b9d887bea7ac70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5447adb964276b9e13399ac93140ae763a149aad Original-Change-Id: I02172a30863b7b97892289e880c29f2d71220fda Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210436 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8898 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25ryu: Add mainboard_init_xxx functions to get it building againTom Warren
Rush has its EC on SPI, and Ryu has it on I2C, so need both mainboard_init_ec_spi and mainboard_init_ec_i2c in both builds, due to romstage.c being in the common tegra132 subdir. BUG=none BRANCH=rush_ryu TEST=Built both rush and rush_ryu images OK. Will try to boot on Ryu later. Change-Id: Iddbf9e9f6de7ba7244f9dd2e810fb6178937c85a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d8b81717c366d19b43964bed3c4047598db4495 Original-Change-Id: I48d9530697d5669177ecd9ba3c34360197002003 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210595 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25cpu/amd/model_10xxx: Increase preram buffer size to 32kTimothy Pearson
This resolves an issue where large sections of the cbmem logs were being dropped on AMD Fam10h boards. Change-Id: I0e4e86e169aa4f20f06472f1a6e3136705ae4f9d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8851 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-25console: Convert cbmem log line endings to UNIX standardTimothy Pearson
The cbmem console output retains usage of the CRLF line ending. Converting line endings to the standard UNIX LF avoids the need to use dos2unix before running analysis on log files. Change-Id: I74a04ee69836d82640c94f250465acb4d1ee1071 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8857 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-24cbfs: expose init_backing_media()Aaron Durbin
I broke cbfs loading with commit 358901. As multiple functions are being reused one needs to ensure there is always a cbfs media object allocated on the stack and initialized. Ya for no common writable globals. TEST=Ran qemu-armv7. CBFS loading works again. Change-Id: Ibd047af7dcd8575e6203651471079fc2042da282 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8973 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-03-24ryu: use padconfig API in bootblockAaron Durbin
Switch over to the padconfig API for bootblock PAD configurations. Aside from support code, each entry is 4 bytes. The open coded calls were 12 bytes each. BUG=chrome-os-partner:29981 BRANCH=None TEST=Built for ryu. Change-Id: Iff981509f258c8fe7bbc2e24ce87bad0c43a55b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8a7ee469124eeb6d05b978b5e68a2fc03b102f47 Original-Change-Id: I2d32d702da38bc0d87a1c159113bba32f4c03407 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210837 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8879 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24rush: use padconfig API in bootblockAaron Durbin
Switch over to the padconfig API for bootblock PAD configurations. Aside from support code, each entry is 4 bytes. The open coded calls were 12 bytes each. BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and ran on rush. Observed consistent results. Change-Id: Ibfa6fc188a7c503cfad41420ed50c7a88fdec579 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2245478f8e21167e93a6e97b12730788a7f927ae Original-Change-Id: I1d5d38322bda6740a0ea50b89f88b722febdee22 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210836 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24tegra132: add bootblock_mainboard_early_init()Aaron Durbin
Instead of hard coding certain pieces of a board in the common chipset code provide a way to initialize things early in the bootblock path. Add a bootblock_mainboard_early_init() function before console init to performany necessary mainboard initialization early in the bootblock. BUG=chrome-os-partner:31104 BUG=chrome-os-partner:31105 BUG=chrome-os-partner:29981 BRANCH=None TEST=built both on rush and ryu. rush still behaves the same. Change-Id: Idcf081eeffd189a4e2cbfeb8a4ac5dd0a3d1f838 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4a523add6de03bea0d88e95b9dbb5e283c629400 Original-Change-Id: I7d93641dff3a961f120e8f0ec2d959182477ef87 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210835 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8877 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24tegra132: use padconfig for initializing uart padsAaron Durbin
Start using the soc_configure_pads() API. This allows for bulk processing of pads. BUG=chrome-os-partner:31105 BUG=chrome-os-partner:31104 BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and can get console messages on rush. Change-Id: Id2c8a685a4566bda8fc260f74f5dffdd0da03056 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bbd7c81bc0777b38bb641b9fcf89425bfd93566d Original-Change-Id: Iaa6a6ff4d559aedb98b078e87b0ecddefd3402d6 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210834 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8876 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24tegra132: provide pad configuration interfaceAaron Durbin
Instead of sprinkling the pad configuration and pinmux selection throughout the code allow for a data-driven initialization sequence. Most of the calls in the original pinmux functions require 12 bytes per pad plus the support code. This implementation allows for 4 bytes per pad in addition to the support code. BUG=chrome-os-partner:29981 TEST=Built and booted into depthcharge on rush. Change-Id: I22c243a5f9891a97e14b78d8c8064e36adaf50b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9329c17bbadcaab803b38842e38e1704d262817d Original-Change-Id: I3a119b4068e880b74a0a1597f143d7c4e108a6c1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210833 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8875 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24pinky: implement hard_resetDaisuke Nojiri
this change implements hard_reset, which resets the board. BUG=none TEST=Booted Pinky BRANCH=none Change-Id: Iefb9d96fbddc77892191b62cc2bd0fe6054c3857 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 17633fc8d4132d99c5b4f9f208bf9bd0fbb0773b Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia375644be01aa4c2c078ba8c7df94e316d155402 Original-Reviewed-on: https://chromium-review.googlesource.com/219624 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/8874 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-03-24veyron: add config values for fmap and tpmDaisuke Nojiri
this change adds missing config values needed to access fmap and tpm. BUG=None TEST=Booted Veyron Pinky BRANCH=None Change-Id: If74ebe84bd9117edd70f62f67a1745e71bbbcdb7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58d2f40c853b2b698bedc96c1d7000cd4eeb2f8d Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I534d060c9e61a9cfd1ee4efe709cf1e30ca2663f Original-Reviewed-on: https://chromium-review.googlesource.com/218874 Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8873 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: sync i2c driver with depthchargeDaisuke Nojiri
this change syncs the i2c driver with the one in depthcharge. BUG=None TEST=Booted Veyron Pinky BRANCH=None Change-Id: Ic9c7006770bba50fd412e0bcefc52f879b7195ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Id: 95ca6c88061062c0de95a8dd3567a71a372771b0 Original-Change-Id: I0d0fdefa58c5b4cc5c991be40796a800ccf074a5 Original-Reviewed-on: https://chromium-review.googlesource.com/218873 Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8872 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24veyron_pinky: Move PMIC driver into SoC directoryJulius Werner
The Rk808 PMIC is a part that will probably be used by most Rk3288 boards, so it makes sense to keep it as common code in the the SoC directory. This patch puts LDO control functions into rk3288/rk808.c, so that the mainboard only has to call a simple interface to set up the specific LDOs it requires. BUG=chrome-os-partner:30167 TEST=Booted both this and the old version with a stubbed-out i2c_writeb(), ensured that the final values are the same. Change-Id: I7efa60f8a357ce6be7490e64d2e0e3f72ad16f1c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4df22cd78ee04fefc6f7fa0e5c3d903eb1794422 Original-Change-Id: Ic172f9c402e829995f049726d3cb6dbd637039d1 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217598 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8871 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24veyron_pinky: Add board ID supportJulius Werner
This patch adds code to read the board ID from Pinky and put it into the coreboot table. (Note: This implementation differs slightly from Tegra since it pinmuxes the GPIOs inside board_id(). That means the pinmuxing might be set more than once if called in multiple stages, which is perfectly harmless and in my opinion cleaner than having to (remember to) do it manually in one of the per-stage files.) BUG=chrome-os-partner:30167 TEST=With depthcharge patch, select -rev1 device tree for board ID 0. Change-Id: I265fafcb176a31a46f7792ecf352f1671be7dd41 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9da10ce8b62ec98243fc7c82544b3004316799a8 Original-Change-Id: I5b5689373e1e47b1e0944b5fe5f2e70a285b931f Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217675 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8870 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24veyron: Rename "veyron" board to "veyron_pinky"Julius Werner
We retroactively decided to use the variant name "pinky" for the Rk3288 board we're currently bringing up, and retcon the unadorned "veyron" name to refer to the Rockchip evaluation board. Since we currently have no interest to maintain coreboot support for that board in our tree, let's rename everything to "veyron_pinky" and forget about "veyron". CQ-DEPEND=CL:217592 BUG=chrome-os-partner:30167 TEST='emerge-veyron libpayload coreboot' fails but 'emerge-veyron_pinky libpayload coreboot' succeeds. Change-Id: I88bf5cc2da7c2f969ea184b5f12affaa94045a06 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aa8ec24b63d11798fec1993091b113a0c0938c7a Original-Change-Id: I366391efc8e0a7c610584b50cea331a0164da6f3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217674 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8869 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24veyron: Fix file permissionsJulius Werner
Some files for the veyron project were checked in with execute permissions where it doesn't make sense. Fix. BUG=chrome-os-partner:30167 TEST=None Change-Id: I2a96816d4fd0af3949b0adaf5208fd2862835b5b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7a408ff273d848b60aaad4f8b27103318e56111 Original-Change-Id: Ia3788abf3755baf028518efb975701cf6cb37e46 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217673 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8868 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: update romstage & mainboardhuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I877b4bf741f45f6cfd032ad5018a60e8a1453622 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 640da5ad5597803c62d9374a1a48832003077723 Original-Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209469 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8867 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24rk3288: add cpu and chiphuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I4c1864171e56a81e8eda95a15ca6a6bc1adc7a70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 814af4b653432295cb6d7222af4a6e5a8d9dfbf6 Original-Change-Id: I1a986fbc8b3737bae655207dd89865dd39aecf87 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209467 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/8866 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: add ddr driverJinkun Hong
Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz. ddr timing config file in src\mainboard\google\veyron\sdram_inf Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz). BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I429eb0b8c365c6285fb6cfef008b41776cc9c2d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 52838c68fe6963285c974af5dc5837e819efc321 Original-Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209465 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8865 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: add gpiohuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I63b4a62f624d34f7028321cb4576cbdb9cd10817 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3606d7eb06d66e23f4ee7ecb6862d23bde3acfd2 Original-Change-Id: I3e0cff1c6de464a8a79e30e239cfb0960cbae253 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209460 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8864 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: add i2chuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I23af280764eb28d3f6b215ab32553fe42ee73272 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: abf5c14c8b32573107d2a1c73a752e740264db7e Original-Change-Id: I46257cc71cc3cd1e867edf589ddf09f7990d6784 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209462 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8863 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24add make_idb.py & update bootblockhuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: Ica7b2bf2cf649c2731933ce59a263692bb2c0282 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba9c36daedc749748f45e68a84f8c34c636adb1c Original-Change-Id: Ia0e4e39d4391674f25e630b40913eb99ff3f75c4 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8862 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-24rk3288: add mediahuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I74b30ecfe40c039855b835db0dfd0cd25adf960e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a30378a3152c930029a5b170cc6bf46180b5c7b8 Original-Change-Id: I5105e5277b8072c06bb41b39479373697ef81c67 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209468 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8860 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24rk3288: add iomux operationhuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: Ia19f8084a945992d9f252eb080c6c5c9990ac7de Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 30d02610e8e1e018025c2c1c970fb5b33d67d51b Original-Change-Id: I8f273f8850e4792ca976bb7c2ed39cbe501401f2 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209461 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8861 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 23:54:20 +0000